gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987-2013 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 /* This module is essentially the "combiner" phase of the U. of Arizona
  21    Portable Optimizer, but redone to work on our list-structured
  22    representation for RTL instead of their string representation.
  23
  24    The LOG_LINKS of each insn identify the most recent assignment
  25    to each REG used in the insn.  It is a list of previous insns,
  26    each of which contains a SET for a REG that is used in this insn
  27    and not used or set in between.  LOG_LINKs never cross basic blocks.
  28    They were set up by the preceding pass (lifetime analysis).
  29
  30    We try to combine each pair of insns joined by a logical link.
  31    We also try to combine triplets of insns A, B and C when C has
  32    a link back to B and B has a link back to A.  Likewise for a
  33    small number of quadruplets of insns A, B, C and D for which
  34    there's high likelihood of of success.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information isn't
  53    completely updated (however this is only a local issue since it is
  54    regenerated before the next pass that uses it):
  55
  56    - reg_live_length is not updated
  57    - reg_n_refs is not adjusted in the rare case when a register is
  58      no longer required in a computation
  59    - there are extremely rare cases (see distribute_notes) when a
  60      REG_DEAD note is lost
  61    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  62      removed because there is no way to know which register it was
  63      linking
  64
  65    To simplify substitution, we combine only when the earlier insn(s)
  66    consist of only a single assignment.  To simplify updating afterward,
  67    we never combine when a subroutine call appears in the middle.
  68
  69    Since we do not represent assignments to CC0 explicitly except when that
  70    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  71    the condition code for the insn that set the condition code.
  72    Fortunately, these two insns must be consecutive.
  73    Therefore, every JUMP_INSN is taken to have an implicit logical link
  74    to the preceding insn.  This is not quite right, since non-jumps can
  75    also use the condition code; but in practice such insns would not
  76    combine anyway.  */
  77
  78 #include "config.h"
  79 #include "system.h"
  80 #include "coretypes.h"
  81 #include "tm.h"
  82 #include "rtl.h"
  83 #include "tree.h"
  84 #include "tm_p.h"
  85 #include "flags.h"
  86 #include "regs.h"
  87 #include "hard-reg-set.h"
  88 #include "basic-block.h"
  89 #include "insn-config.h"
  90 #include "function.h"
  91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  92 #include "expr.h"
  93 #include "insn-attr.h"
  94 #include "recog.h"
  95 #include "diagnostic-core.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 #include "params.h"
 101 #include "tree-pass.h"
 102 #include "df.h"
 103 #include "valtrack.h"
 104 #include "cgraph.h"
 105 #include "obstack.h"
 106
 107 /* Number of attempts to combine instructions in this function.  */
 108
 109 static int combine_attempts;
 110
 111 /* Number of attempts that got as far as substitution in this function.  */
 112
 113 static int combine_merges;
 114
 115 /* Number of instructions combined with added SETs in this function.  */
 116
 117 static int combine_extras;
 118
 119 /* Number of instructions combined in this function.  */
 120
 121 static int combine_successes;
 122
 123 /* Totals over entire compilation.  */
 124
 125 static int total_attempts, total_merges, total_extras, total_successes;
 126
 127 /* combine_instructions may try to replace the right hand side of the
 128    second instruction with the value of an associated REG_EQUAL note
 129    before throwing it at try_combine.  That is problematic when there
 130    is a REG_DEAD note for a register used in the old right hand side
 131    and can cause distribute_notes to do wrong things.  This is the
 132    second instruction if it has been so modified, null otherwise.  */
 133
 134 static rtx i2mod;
 135
 136 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 137
 138 static rtx i2mod_old_rhs;
 139
 140 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 141
 142 static rtx i2mod_new_rhs;
 143 \f
 144 typedef struct reg_stat_struct {
 145   /* Record last point of death of (hard or pseudo) register n.  */
 146   rtx                           last_death;
 147
 148   /* Record last point of modification of (hard or pseudo) register n.  */
 149   rtx                           last_set;
 150
 151   /* The next group of fields allows the recording of the last value assigned
 152      to (hard or pseudo) register n.  We use this information to see if an
 153      operation being processed is redundant given a prior operation performed
 154      on the register.  For example, an `and' with a constant is redundant if
 155      all the zero bits are already known to be turned off.
 156
 157      We use an approach similar to that used by cse, but change it in the
 158      following ways:
 159
 160      (1) We do not want to reinitialize at each label.
 161      (2) It is useful, but not critical, to know the actual value assigned
 162          to a register.  Often just its form is helpful.
 163
 164      Therefore, we maintain the following fields:
 165
 166      last_set_value             the last value assigned
 167      last_set_label             records the value of label_tick when the
 168                                 register was assigned
 169      last_set_table_tick        records the value of label_tick when a
 170                                 value using the register is assigned
 171      last_set_invalid           set to nonzero when it is not valid
 172                                 to use the value of this register in some
 173                                 register's value
 174
 175      To understand the usage of these tables, it is important to understand
 176      the distinction between the value in last_set_value being valid and
 177      the register being validly contained in some other expression in the
 178      table.
 179
 180      (The next two parameters are out of date).
 181
 182      reg_stat[i].last_set_value is valid if it is nonzero, and either
 183      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 184
 185      Register I may validly appear in any expression returned for the value
 186      of another register if reg_n_sets[i] is 1.  It may also appear in the
 187      value for register J if reg_stat[j].last_set_invalid is zero, or
 188      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 189
 190      If an expression is found in the table containing a register which may
 191      not validly appear in an expression, the register is replaced by
 192      something that won't match, (clobber (const_int 0)).  */
 193
 194   /* Record last value assigned to (hard or pseudo) register n.  */
 195
 196   rtx                           last_set_value;
 197
 198   /* Record the value of label_tick when an expression involving register n
 199      is placed in last_set_value.  */
 200
 201   int                           last_set_table_tick;
 202
 203   /* Record the value of label_tick when the value for register n is placed in
 204      last_set_value.  */
 205
 206   int                           last_set_label;
 207
 208   /* These fields are maintained in parallel with last_set_value and are
 209      used to store the mode in which the register was last set, the bits
 210      that were known to be zero when it was last set, and the number of
 211      sign bits copies it was known to have when it was last set.  */
 212
 213   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 214   char                          last_set_sign_bit_copies;
 215   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 216
 217   /* Set nonzero if references to register n in expressions should not be
 218      used.  last_set_invalid is set nonzero when this register is being
 219      assigned to and last_set_table_tick == label_tick.  */
 220
 221   char                          last_set_invalid;
 222
 223   /* Some registers that are set more than once and used in more than one
 224      basic block are nevertheless always set in similar ways.  For example,
 225      a QImode register may be loaded from memory in two places on a machine
 226      where byte loads zero extend.
 227
 228      We record in the following fields if a register has some leading bits
 229      that are always equal to the sign bit, and what we know about the
 230      nonzero bits of a register, specifically which bits are known to be
 231      zero.
 232
 233      If an entry is zero, it means that we don't know anything special.  */
 234
 235   unsigned char                 sign_bit_copies;
 236
 237   unsigned HOST_WIDE_INT        nonzero_bits;
 238
 239   /* Record the value of the label_tick when the last truncation
 240      happened.  The field truncated_to_mode is only valid if
 241      truncation_label == label_tick.  */
 242
 243   int                           truncation_label;
 244
 245   /* Record the last truncation seen for this register.  If truncation
 246      is not a nop to this mode we might be able to save an explicit
 247      truncation if we know that value already contains a truncated
 248      value.  */
 249
 250   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 251 } reg_stat_type;
 252
 253
 254 static vec<reg_stat_type> reg_stat;
 255
 256 /* Record the luid of the last insn that invalidated memory
 257    (anything that writes memory, and subroutine calls, but not pushes).  */
 258
 259 static int mem_last_set;
 260
 261 /* Record the luid of the last CALL_INSN
 262    so we can tell whether a potential combination crosses any calls.  */
 263
 264 static int last_call_luid;
 265
 266 /* When `subst' is called, this is the insn that is being modified
 267    (by combining in a previous insn).  The PATTERN of this insn
 268    is still the old pattern partially modified and it should not be
 269    looked at, but this may be used to examine the successors of the insn
 270    to judge whether a simplification is valid.  */
 271
 272 static rtx subst_insn;
 273
 274 /* This is the lowest LUID that `subst' is currently dealing with.
 275    get_last_value will not return a value if the register was set at or
 276    after this LUID.  If not for this mechanism, we could get confused if
 277    I2 or I1 in try_combine were an insn that used the old value of a register
 278    to obtain a new value.  In that case, we might erroneously get the
 279    new value of the register when we wanted the old one.  */
 280
 281 static int subst_low_luid;
 282
 283 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 284    must consider all these registers to be always live.  */
 285
 286 static HARD_REG_SET newpat_used_regs;
 287
 288 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 289    insn is the earlier than I2 or I3, combine should rescan starting at
 290    that location.  */
 291
 292 static rtx added_links_insn;
 293
 294 /* Basic block in which we are performing combines.  */
 295 static basic_block this_basic_block;
 296 static bool optimize_this_for_speed_p;
 297
 298 \f
 299 /* Length of the currently allocated uid_insn_cost array.  */
 300
 301 static int max_uid_known;
 302
 303 /* The following array records the insn_rtx_cost for every insn
 304    in the instruction stream.  */
 305
 306 static int *uid_insn_cost;
 307
 308 /* The following array records the LOG_LINKS for every insn in the
 309    instruction stream as struct insn_link pointers.  */
 310
 311 struct insn_link {
 312   rtx insn;
 313   struct insn_link *next;
 314 };
 315
 316 static struct insn_link **uid_log_links;
 317
 318 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 319 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 320
 321 #define FOR_EACH_LOG_LINK(L, INSN)                              \
 322   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
 323
 324 /* Links for LOG_LINKS are allocated from this obstack.  */
 325
 326 static struct obstack insn_link_obstack;
 327
 328 /* Allocate a link.  */
 329
 330 static inline struct insn_link *
 331 alloc_insn_link (rtx insn, struct insn_link *next)
 332 {
 333   struct insn_link *l
 334     = (struct insn_link *) obstack_alloc (&insn_link_obstack,
 335                                           sizeof (struct insn_link));
 336   l->insn = insn;
 337   l->next = next;
 338   return l;
 339 }
 340
 341 /* Incremented for each basic block.  */
 342
 343 static int label_tick;
 344
 345 /* Reset to label_tick for each extended basic block in scanning order.  */
 346
 347 static int label_tick_ebb_start;
 348
 349 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 350    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 351
 352 static enum machine_mode nonzero_bits_mode;
 353
 354 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 355    be safely used.  It is zero while computing them and after combine has
 356    completed.  This former test prevents propagating values based on
 357    previously set values, which can be incorrect if a variable is modified
 358    in a loop.  */
 359
 360 static int nonzero_sign_valid;
 361
 362 \f
 363 /* Record one modification to rtl structure
 364    to be undone by storing old_contents into *where.  */
 365
 366 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
 367
 368 struct undo
 369 {
 370   struct undo *next;
 371   enum undo_kind kind;
 372   union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
 373   union { rtx *r; int *i; struct insn_link **l; } where;
 374 };
 375
 376 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 377    num_undo says how many are currently recorded.
 378
 379    other_insn is nonzero if we have modified some other insn in the process
 380    of working on subst_insn.  It must be verified too.  */
 381
 382 struct undobuf
 383 {
 384   struct undo *undos;
 385   struct undo *frees;
 386   rtx other_insn;
 387 };
 388
 389 static struct undobuf undobuf;
 390
 391 /* Number of times the pseudo being substituted for
 392    was found and replaced.  */
 393
 394 static int n_occurrences;
 395
 396 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
 397                                          enum machine_mode,
 398                                          unsigned HOST_WIDE_INT,
 399                                          unsigned HOST_WIDE_INT *);
 400 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
 401                                                 enum machine_mode,
 402                                                 unsigned int, unsigned int *);
 403 static void do_SUBST (rtx *, rtx);
 404 static void do_SUBST_INT (int *, int);
 405 static void init_reg_last (void);
 406 static void setup_incoming_promotions (rtx);
 407 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 408 static int cant_combine_insn_p (rtx);
 409 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
 410 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
 411 static int contains_muldiv (rtx);
 412 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
 413 static void undo_all (void);
 414 static void undo_commit (void);
 415 static rtx *find_split_point (rtx *, rtx, bool);
 416 static rtx subst (rtx, rtx, rtx, int, int, int);
 417 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
 418 static rtx simplify_if_then_else (rtx);
 419 static rtx simplify_set (rtx);
 420 static rtx simplify_logical (rtx);
 421 static rtx expand_compound_operation (rtx);
 422 static const_rtx expand_field_assignment (const_rtx);
 423 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 424                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 425 static rtx extract_left_shift (rtx, int);
 426 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 427                               unsigned HOST_WIDE_INT *);
 428 static rtx canon_reg_for_combine (rtx, rtx);
 429 static rtx force_to_mode (rtx, enum machine_mode,
 430                           unsigned HOST_WIDE_INT, int);
 431 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 432 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 433 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 434 static rtx make_field_assignment (rtx);
 435 static rtx apply_distributive_law (rtx);
 436 static rtx distribute_and_simplify_rtx (rtx, int);
 437 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 438                                      unsigned HOST_WIDE_INT);
 439 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 440                                    unsigned HOST_WIDE_INT);
 441 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 442                             HOST_WIDE_INT, enum machine_mode, int *);
 443 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 444 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 445                                  int);
 446 static int recog_for_combine (rtx *, rtx, rtx *);
 447 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 448 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
 449 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 450 static void update_table_tick (rtx);
 451 static void record_value_for_reg (rtx, rtx, rtx);
 452 static void check_promoted_subreg (rtx, rtx);
 453 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 454 static void record_dead_and_set_regs (rtx);
 455 static int get_last_value_validate (rtx *, rtx, int, int);
 456 static rtx get_last_value (const_rtx);
 457 static int use_crosses_set_p (const_rtx, int);
 458 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 459 static int reg_dead_at_p (rtx, rtx);
 460 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 461 static int reg_bitfield_target_p (rtx, rtx);
 462 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
 463 static void distribute_links (struct insn_link *);
 464 static void mark_used_regs_combine (rtx);
 465 static void record_promoted_value (rtx, rtx);
 466 static int unmentioned_reg_p_1 (rtx *, void *);
 467 static bool unmentioned_reg_p (rtx, rtx);
 468 static int record_truncated_value (rtx *, void *);
 469 static void record_truncated_values (rtx *, void *);
 470 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
 471 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 472 \f
 473
 474 /* It is not safe to use ordinary gen_lowpart in combine.
 475    See comments in gen_lowpart_for_combine.  */
 476 #undef RTL_HOOKS_GEN_LOWPART
 477 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 478
 479 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 480 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 481 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 482
 483 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 484 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 485
 486 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 487 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 488
 489 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 490 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 491
 492 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 493
 494 \f
 495 /* Convenience wrapper for the canonicalize_comparison target hook.
 496    Target hooks cannot use enum rtx_code.  */
 497 static inline void
 498 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
 499                                 bool op0_preserve_value)
 500 {
 501   int code_int = (int)*code;
 502   targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
 503   *code = (enum rtx_code)code_int;
 504 }
 505
 506 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 507    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 508    This is a wrapper around split_insns which ensures that the
 509    reg_stat vector is made larger if the splitter creates a new
 510    register.  */
 511
 512 static rtx
 513 combine_split_insns (rtx pattern, rtx insn)
 514 {
 515   rtx ret;
 516   unsigned int nregs;
 517
 518   ret = split_insns (pattern, insn);
 519   nregs = max_reg_num ();
 520   if (nregs > reg_stat.length ())
 521     reg_stat.safe_grow_cleared (nregs);
 522   return ret;
 523 }
 524
 525 /* This is used by find_single_use to locate an rtx in LOC that
 526    contains exactly one use of DEST, which is typically either a REG
 527    or CC0.  It returns a pointer to the innermost rtx expression
 528    containing DEST.  Appearances of DEST that are being used to
 529    totally replace it are not counted.  */
 530
 531 static rtx *
 532 find_single_use_1 (rtx dest, rtx *loc)
 533 {
 534   rtx x = *loc;
 535   enum rtx_code code = GET_CODE (x);
 536   rtx *result = NULL;
 537   rtx *this_result;
 538   int i;
 539   const char *fmt;
 540
 541   switch (code)
 542     {
 543     case CONST:
 544     case LABEL_REF:
 545     case SYMBOL_REF:
 546     CASE_CONST_ANY:
 547     case CLOBBER:
 548       return 0;
 549
 550     case SET:
 551       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 552          of a REG that occupies all of the REG, the insn uses DEST if
 553          it is mentioned in the destination or the source.  Otherwise, we
 554          need just check the source.  */
 555       if (GET_CODE (SET_DEST (x)) != CC0
 556           && GET_CODE (SET_DEST (x)) != PC
 557           && !REG_P (SET_DEST (x))
 558           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 559                 && REG_P (SUBREG_REG (SET_DEST (x)))
 560                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 561                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 562                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 563                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 564         break;
 565
 566       return find_single_use_1 (dest, &SET_SRC (x));
 567
 568     case MEM:
 569     case SUBREG:
 570       return find_single_use_1 (dest, &XEXP (x, 0));
 571
 572     default:
 573       break;
 574     }
 575
 576   /* If it wasn't one of the common cases above, check each expression and
 577      vector of this code.  Look for a unique usage of DEST.  */
 578
 579   fmt = GET_RTX_FORMAT (code);
 580   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 581     {
 582       if (fmt[i] == 'e')
 583         {
 584           if (dest == XEXP (x, i)
 585               || (REG_P (dest) && REG_P (XEXP (x, i))
 586                   && REGNO (dest) == REGNO (XEXP (x, i))))
 587             this_result = loc;
 588           else
 589             this_result = find_single_use_1 (dest, &XEXP (x, i));
 590
 591           if (result == NULL)
 592             result = this_result;
 593           else if (this_result)
 594             /* Duplicate usage.  */
 595             return NULL;
 596         }
 597       else if (fmt[i] == 'E')
 598         {
 599           int j;
 600
 601           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 602             {
 603               if (XVECEXP (x, i, j) == dest
 604                   || (REG_P (dest)
 605                       && REG_P (XVECEXP (x, i, j))
 606                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 607                 this_result = loc;
 608               else
 609                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 610
 611               if (result == NULL)
 612                 result = this_result;
 613               else if (this_result)
 614                 return NULL;
 615             }
 616         }
 617     }
 618
 619   return result;
 620 }
 621
 622
 623 /* See if DEST, produced in INSN, is used only a single time in the
 624    sequel.  If so, return a pointer to the innermost rtx expression in which
 625    it is used.
 626
 627    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 628
 629    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 630    care about REG_DEAD notes or LOG_LINKS.
 631
 632    Otherwise, we find the single use by finding an insn that has a
 633    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 634    only referenced once in that insn, we know that it must be the first
 635    and last insn referencing DEST.  */
 636
 637 static rtx *
 638 find_single_use (rtx dest, rtx insn, rtx *ploc)
 639 {
 640   basic_block bb;
 641   rtx next;
 642   rtx *result;
 643   struct insn_link *link;
 644
 645 #ifdef HAVE_cc0
 646   if (dest == cc0_rtx)
 647     {
 648       next = NEXT_INSN (insn);
 649       if (next == 0
 650           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 651         return 0;
 652
 653       result = find_single_use_1 (dest, &PATTERN (next));
 654       if (result && ploc)
 655         *ploc = next;
 656       return result;
 657     }
 658 #endif
 659
 660   if (!REG_P (dest))
 661     return 0;
 662
 663   bb = BLOCK_FOR_INSN (insn);
 664   for (next = NEXT_INSN (insn);
 665        next && BLOCK_FOR_INSN (next) == bb;
 666        next = NEXT_INSN (next))
 667     if (INSN_P (next) && dead_or_set_p (next, dest))
 668       {
 669         FOR_EACH_LOG_LINK (link, next)
 670           if (link->insn == insn)
 671             break;
 672
 673         if (link)
 674           {
 675             result = find_single_use_1 (dest, &PATTERN (next));
 676             if (ploc)
 677               *ploc = next;
 678             return result;
 679           }
 680       }
 681
 682   return 0;
 683 }
 684 \f
 685 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 686    insn.  The substitution can be undone by undo_all.  If INTO is already
 687    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 688    also call SUBST, we have to compute it before we put anything into
 689    the undo table.  */
 690
 691 static void
 692 do_SUBST (rtx *into, rtx newval)
 693 {
 694   struct undo *buf;
 695   rtx oldval = *into;
 696
 697   if (oldval == newval)
 698     return;
 699
 700   /* We'd like to catch as many invalid transformations here as
 701      possible.  Unfortunately, there are way too many mode changes
 702      that are perfectly valid, so we'd waste too much effort for
 703      little gain doing the checks here.  Focus on catching invalid
 704      transformations involving integer constants.  */
 705   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 706       && CONST_INT_P (newval))
 707     {
 708       /* Sanity check that we're replacing oldval with a CONST_INT
 709          that is a valid sign-extension for the original mode.  */
 710       gcc_assert (INTVAL (newval)
 711                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 712
 713       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 714          CONST_INT is not valid, because after the replacement, the
 715          original mode would be gone.  Unfortunately, we can't tell
 716          when do_SUBST is called to replace the operand thereof, so we
 717          perform this test on oldval instead, checking whether an
 718          invalid replacement took place before we got here.  */
 719       gcc_assert (!(GET_CODE (oldval) == SUBREG
 720                     && CONST_INT_P (SUBREG_REG (oldval))));
 721       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 722                     && CONST_INT_P (XEXP (oldval, 0))));
 723     }
 724
 725   if (undobuf.frees)
 726     buf = undobuf.frees, undobuf.frees = buf->next;
 727   else
 728     buf = XNEW (struct undo);
 729
 730   buf->kind = UNDO_RTX;
 731   buf->where.r = into;
 732   buf->old_contents.r = oldval;
 733   *into = newval;
 734
 735   buf->next = undobuf.undos, undobuf.undos = buf;
 736 }
 737
 738 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 739
 740 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 741    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 742    not safe.  */
 743
 744 static void
 745 do_SUBST_INT (int *into, int newval)
 746 {
 747   struct undo *buf;
 748   int oldval = *into;
 749
 750   if (oldval == newval)
 751     return;
 752
 753   if (undobuf.frees)
 754     buf = undobuf.frees, undobuf.frees = buf->next;
 755   else
 756     buf = XNEW (struct undo);
 757
 758   buf->kind = UNDO_INT;
 759   buf->where.i = into;
 760   buf->old_contents.i = oldval;
 761   *into = newval;
 762
 763   buf->next = undobuf.undos, undobuf.undos = buf;
 764 }
 765
 766 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 767
 768 /* Similar to SUBST, but just substitute the mode.  This is used when
 769    changing the mode of a pseudo-register, so that any other
 770    references to the entry in the regno_reg_rtx array will change as
 771    well.  */
 772
 773 static void
 774 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 775 {
 776   struct undo *buf;
 777   enum machine_mode oldval = GET_MODE (*into);
 778
 779   if (oldval == newval)
 780     return;
 781
 782   if (undobuf.frees)
 783     buf = undobuf.frees, undobuf.frees = buf->next;
 784   else
 785     buf = XNEW (struct undo);
 786
 787   buf->kind = UNDO_MODE;
 788   buf->where.r = into;
 789   buf->old_contents.m = oldval;
 790   adjust_reg_mode (*into, newval);
 791
 792   buf->next = undobuf.undos, undobuf.undos = buf;
 793 }
 794
 795 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 796
 797 #ifndef HAVE_cc0
 798 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */
 799
 800 static void
 801 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
 802 {
 803   struct undo *buf;
 804   struct insn_link * oldval = *into;
 805
 806   if (oldval == newval)
 807     return;
 808
 809   if (undobuf.frees)
 810     buf = undobuf.frees, undobuf.frees = buf->next;
 811   else
 812     buf = XNEW (struct undo);
 813
 814   buf->kind = UNDO_LINKS;
 815   buf->where.l = into;
 816   buf->old_contents.l = oldval;
 817   *into = newval;
 818
 819   buf->next = undobuf.undos, undobuf.undos = buf;
 820 }
 821
 822 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
 823 #endif
 824 \f
 825 /* Subroutine of try_combine.  Determine whether the replacement patterns
 826    NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
 827    than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 828    that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 829    undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 830    of all the instructions can be estimated and the replacements are more
 831    expensive than the original sequence.  */
 832
 833 static bool
 834 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
 835                        rtx newi2pat, rtx newotherpat)
 836 {
 837   int i0_cost, i1_cost, i2_cost, i3_cost;
 838   int new_i2_cost, new_i3_cost;
 839   int old_cost, new_cost;
 840
 841   /* Lookup the original insn_rtx_costs.  */
 842   i2_cost = INSN_COST (i2);
 843   i3_cost = INSN_COST (i3);
 844
 845   if (i1)
 846     {
 847       i1_cost = INSN_COST (i1);
 848       if (i0)
 849         {
 850           i0_cost = INSN_COST (i0);
 851           old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 852                       ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
 853         }
 854       else
 855         {
 856           old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 857                       ? i1_cost + i2_cost + i3_cost : 0);
 858           i0_cost = 0;
 859         }
 860     }
 861   else
 862     {
 863       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 864       i1_cost = i0_cost = 0;
 865     }
 866
 867   /* Calculate the replacement insn_rtx_costs.  */
 868   new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
 869   if (newi2pat)
 870     {
 871       new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
 872       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 873                  ? new_i2_cost + new_i3_cost : 0;
 874     }
 875   else
 876     {
 877       new_cost = new_i3_cost;
 878       new_i2_cost = 0;
 879     }
 880
 881   if (undobuf.other_insn)
 882     {
 883       int old_other_cost, new_other_cost;
 884
 885       old_other_cost = INSN_COST (undobuf.other_insn);
 886       new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
 887       if (old_other_cost > 0 && new_other_cost > 0)
 888         {
 889           old_cost += old_other_cost;
 890           new_cost += new_other_cost;
 891         }
 892       else
 893         old_cost = 0;
 894     }
 895
 896   /* Disallow this combination if both new_cost and old_cost are greater than
 897      zero, and new_cost is greater than old cost.  */
 898   if (old_cost > 0 && new_cost > old_cost)
 899     {
 900       if (dump_file)
 901         {
 902           if (i0)
 903             {
 904               fprintf (dump_file,
 905                        "rejecting combination of insns %d, %d, %d and %d\n",
 906                        INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
 907                        INSN_UID (i3));
 908               fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
 909                        i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
 910             }
 911           else if (i1)
 912             {
 913               fprintf (dump_file,
 914                        "rejecting combination of insns %d, %d and %d\n",
 915                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 916               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 917                        i1_cost, i2_cost, i3_cost, old_cost);
 918             }
 919           else
 920             {
 921               fprintf (dump_file,
 922                        "rejecting combination of insns %d and %d\n",
 923                        INSN_UID (i2), INSN_UID (i3));
 924               fprintf (dump_file, "original costs %d + %d = %d\n",
 925                        i2_cost, i3_cost, old_cost);
 926             }
 927
 928           if (newi2pat)
 929             {
 930               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 931                        new_i2_cost, new_i3_cost, new_cost);
 932             }
 933           else
 934             fprintf (dump_file, "replacement cost %d\n", new_cost);
 935         }
 936
 937       return false;
 938     }
 939
 940   /* Update the uid_insn_cost array with the replacement costs.  */
 941   INSN_COST (i2) = new_i2_cost;
 942   INSN_COST (i3) = new_i3_cost;
 943   if (i1)
 944     {
 945       INSN_COST (i1) = 0;
 946       if (i0)
 947         INSN_COST (i0) = 0;
 948     }
 949
 950   return true;
 951 }
 952
 953
 954 /* Delete any insns that copy a register to itself.  */
 955
 956 static void
 957 delete_noop_moves (void)
 958 {
 959   rtx insn, next;
 960   basic_block bb;
 961
 962   FOR_EACH_BB (bb)
 963     {
 964       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 965         {
 966           next = NEXT_INSN (insn);
 967           if (INSN_P (insn) && noop_move_p (insn))
 968             {
 969               if (dump_file)
 970                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 971
 972               delete_insn_and_edges (insn);
 973             }
 974         }
 975     }
 976 }
 977
 978 \f
 979 /* Fill in log links field for all insns.  */
 980
 981 static void
 982 create_log_links (void)
 983 {
 984   basic_block bb;
 985   rtx *next_use, insn;
 986   df_ref *def_vec, *use_vec;
 987
 988   next_use = XCNEWVEC (rtx, max_reg_num ());
 989
 990   /* Pass through each block from the end, recording the uses of each
 991      register and establishing log links when def is encountered.
 992      Note that we do not clear next_use array in order to save time,
 993      so we have to test whether the use is in the same basic block as def.
 994
 995      There are a few cases below when we do not consider the definition or
 996      usage -- these are taken from original flow.c did. Don't ask me why it is
 997      done this way; I don't know and if it works, I don't want to know.  */
 998
 999   FOR_EACH_BB (bb)
1000     {
1001       FOR_BB_INSNS_REVERSE (bb, insn)
1002         {
1003           if (!NONDEBUG_INSN_P (insn))
1004             continue;
1005
1006           /* Log links are created only once.  */
1007           gcc_assert (!LOG_LINKS (insn));
1008
1009           for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
1010             {
1011               df_ref def = *def_vec;
1012               int regno = DF_REF_REGNO (def);
1013               rtx use_insn;
1014
1015               if (!next_use[regno])
1016                 continue;
1017
1018               /* Do not consider if it is pre/post modification in MEM.  */
1019               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1020                 continue;
1021
1022               /* Do not make the log link for frame pointer.  */
1023               if ((regno == FRAME_POINTER_REGNUM
1024                    && (! reload_completed || frame_pointer_needed))
1025 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1026                   || (regno == HARD_FRAME_POINTER_REGNUM
1027                       && (! reload_completed || frame_pointer_needed))
1028 #endif
1029 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1030                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1031 #endif
1032                   )
1033                 continue;
1034
1035               use_insn = next_use[regno];
1036               if (BLOCK_FOR_INSN (use_insn) == bb)
1037                 {
1038                   /* flow.c claimed:
1039
1040                      We don't build a LOG_LINK for hard registers contained
1041                      in ASM_OPERANDs.  If these registers get replaced,
1042                      we might wind up changing the semantics of the insn,
1043                      even if reload can make what appear to be valid
1044                      assignments later.  */
1045                   if (regno >= FIRST_PSEUDO_REGISTER
1046                       || asm_noperands (PATTERN (use_insn)) < 0)
1047                     {
1048                       /* Don't add duplicate links between instructions.  */
1049                       struct insn_link *links;
1050                       FOR_EACH_LOG_LINK (links, use_insn)
1051                         if (insn == links->insn)
1052                           break;
1053
1054                       if (!links)
1055                         LOG_LINKS (use_insn)
1056                           = alloc_insn_link (insn, LOG_LINKS (use_insn));
1057                     }
1058                 }
1059               next_use[regno] = NULL_RTX;
1060             }
1061
1062           for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1063             {
1064               df_ref use = *use_vec;
1065               int regno = DF_REF_REGNO (use);
1066
1067               /* Do not consider the usage of the stack pointer
1068                  by function call.  */
1069               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1070                 continue;
1071
1072               next_use[regno] = insn;
1073             }
1074         }
1075     }
1076
1077   free (next_use);
1078 }
1079
1080 /* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
1081    true if we found a LOG_LINK that proves that A feeds B.  This only works
1082    if there are no instructions between A and B which could have a link
1083    depending on A, since in that case we would not record a link for B.
1084    We also check the implicit dependency created by a cc0 setter/user
1085    pair.  */
1086
1087 static bool
1088 insn_a_feeds_b (rtx a, rtx b)
1089 {
1090   struct insn_link *links;
1091   FOR_EACH_LOG_LINK (links, b)
1092     if (links->insn == a)
1093       return true;
1094 #ifdef HAVE_cc0
1095   if (sets_cc0_p (a))
1096     return true;
1097 #endif
1098   return false;
1099 }
1100 \f
1101 /* Main entry point for combiner.  F is the first insn of the function.
1102    NREGS is the first unused pseudo-reg number.
1103
1104    Return nonzero if the combiner has turned an indirect jump
1105    instruction into a direct jump.  */
1106 static int
1107 combine_instructions (rtx f, unsigned int nregs)
1108 {
1109   rtx insn, next;
1110 #ifdef HAVE_cc0
1111   rtx prev;
1112 #endif
1113   struct insn_link *links, *nextlinks;
1114   rtx first;
1115   basic_block last_bb;
1116
1117   int new_direct_jump_p = 0;
1118
1119   for (first = f; first && !INSN_P (first); )
1120     first = NEXT_INSN (first);
1121   if (!first)
1122     return 0;
1123
1124   combine_attempts = 0;
1125   combine_merges = 0;
1126   combine_extras = 0;
1127   combine_successes = 0;
1128
1129   rtl_hooks = combine_rtl_hooks;
1130
1131   reg_stat.safe_grow_cleared (nregs);
1132
1133   init_recog_no_volatile ();
1134
1135   /* Allocate array for insn info.  */
1136   max_uid_known = get_max_uid ();
1137   uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1138   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1139   gcc_obstack_init (&insn_link_obstack);
1140
1141   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1142
1143   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1144      problems when, for example, we have j <<= 1 in a loop.  */
1145
1146   nonzero_sign_valid = 0;
1147   label_tick = label_tick_ebb_start = 1;
1148
1149   /* Scan all SETs and see if we can deduce anything about what
1150      bits are known to be zero for some registers and how many copies
1151      of the sign bit are known to exist for those registers.
1152
1153      Also set any known values so that we can use it while searching
1154      for what bits are known to be set.  */
1155
1156   setup_incoming_promotions (first);
1157   /* Allow the entry block and the first block to fall into the same EBB.
1158      Conceptually the incoming promotions are assigned to the entry block.  */
1159   last_bb = ENTRY_BLOCK_PTR;
1160
1161   create_log_links ();
1162   FOR_EACH_BB (this_basic_block)
1163     {
1164       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1165       last_call_luid = 0;
1166       mem_last_set = -1;
1167
1168       label_tick++;
1169       if (!single_pred_p (this_basic_block)
1170           || single_pred (this_basic_block) != last_bb)
1171         label_tick_ebb_start = label_tick;
1172       last_bb = this_basic_block;
1173
1174       FOR_BB_INSNS (this_basic_block, insn)
1175         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1176           {
1177 #ifdef AUTO_INC_DEC
1178             rtx links;
1179 #endif
1180
1181             subst_low_luid = DF_INSN_LUID (insn);
1182             subst_insn = insn;
1183
1184             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1185                          insn);
1186             record_dead_and_set_regs (insn);
1187
1188 #ifdef AUTO_INC_DEC
1189             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1190               if (REG_NOTE_KIND (links) == REG_INC)
1191                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1192                                                   insn);
1193 #endif
1194
1195             /* Record the current insn_rtx_cost of this instruction.  */
1196             if (NONJUMP_INSN_P (insn))
1197               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1198                                                 optimize_this_for_speed_p);
1199             if (dump_file)
1200               fprintf(dump_file, "insn_cost %d: %d\n",
1201                     INSN_UID (insn), INSN_COST (insn));
1202           }
1203     }
1204
1205   nonzero_sign_valid = 1;
1206
1207   /* Now scan all the insns in forward order.  */
1208   label_tick = label_tick_ebb_start = 1;
1209   init_reg_last ();
1210   setup_incoming_promotions (first);
1211   last_bb = ENTRY_BLOCK_PTR;
1212
1213   FOR_EACH_BB (this_basic_block)
1214     {
1215       rtx last_combined_insn = NULL_RTX;
1216       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1217       last_call_luid = 0;
1218       mem_last_set = -1;
1219
1220       label_tick++;
1221       if (!single_pred_p (this_basic_block)
1222           || single_pred (this_basic_block) != last_bb)
1223         label_tick_ebb_start = label_tick;
1224       last_bb = this_basic_block;
1225
1226       rtl_profile_for_bb (this_basic_block);
1227       for (insn = BB_HEAD (this_basic_block);
1228            insn != NEXT_INSN (BB_END (this_basic_block));
1229            insn = next ? next : NEXT_INSN (insn))
1230         {
1231           next = 0;
1232           if (NONDEBUG_INSN_P (insn))
1233             {
1234               while (last_combined_insn
1235                      && INSN_DELETED_P (last_combined_insn))
1236                 last_combined_insn = PREV_INSN (last_combined_insn);
1237               if (last_combined_insn == NULL_RTX
1238                   || BARRIER_P (last_combined_insn)
1239                   || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1240                   || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1241                 last_combined_insn = insn;
1242
1243               /* See if we know about function return values before this
1244                  insn based upon SUBREG flags.  */
1245               check_promoted_subreg (insn, PATTERN (insn));
1246
1247               /* See if we can find hardregs and subreg of pseudos in
1248                  narrower modes.  This could help turning TRUNCATEs
1249                  into SUBREGs.  */
1250               note_uses (&PATTERN (insn), record_truncated_values, NULL);
1251
1252               /* Try this insn with each insn it links back to.  */
1253
1254               FOR_EACH_LOG_LINK (links, insn)
1255                 if ((next = try_combine (insn, links->insn, NULL_RTX,
1256                                          NULL_RTX, &new_direct_jump_p,
1257                                          last_combined_insn)) != 0)
1258                   goto retry;
1259
1260               /* Try each sequence of three linked insns ending with this one.  */
1261
1262               FOR_EACH_LOG_LINK (links, insn)
1263                 {
1264                   rtx link = links->insn;
1265
1266                   /* If the linked insn has been replaced by a note, then there
1267                      is no point in pursuing this chain any further.  */
1268                   if (NOTE_P (link))
1269                     continue;
1270
1271                   FOR_EACH_LOG_LINK (nextlinks, link)
1272                     if ((next = try_combine (insn, link, nextlinks->insn,
1273                                              NULL_RTX, &new_direct_jump_p,
1274                                              last_combined_insn)) != 0)
1275                       goto retry;
1276                 }
1277
1278 #ifdef HAVE_cc0
1279               /* Try to combine a jump insn that uses CC0
1280                  with a preceding insn that sets CC0, and maybe with its
1281                  logical predecessor as well.
1282                  This is how we make decrement-and-branch insns.
1283                  We need this special code because data flow connections
1284                  via CC0 do not get entered in LOG_LINKS.  */
1285
1286               if (JUMP_P (insn)
1287                   && (prev = prev_nonnote_insn (insn)) != 0
1288                   && NONJUMP_INSN_P (prev)
1289                   && sets_cc0_p (PATTERN (prev)))
1290                 {
1291                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1292                                            &new_direct_jump_p,
1293                                            last_combined_insn)) != 0)
1294                     goto retry;
1295
1296                   FOR_EACH_LOG_LINK (nextlinks, prev)
1297                     if ((next = try_combine (insn, prev, nextlinks->insn,
1298                                              NULL_RTX, &new_direct_jump_p,
1299                                              last_combined_insn)) != 0)
1300                       goto retry;
1301                 }
1302
1303               /* Do the same for an insn that explicitly references CC0.  */
1304               if (NONJUMP_INSN_P (insn)
1305                   && (prev = prev_nonnote_insn (insn)) != 0
1306                   && NONJUMP_INSN_P (prev)
1307                   && sets_cc0_p (PATTERN (prev))
1308                   && GET_CODE (PATTERN (insn)) == SET
1309                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1310                 {
1311                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1312                                            &new_direct_jump_p,
1313                                            last_combined_insn)) != 0)
1314                     goto retry;
1315
1316                   FOR_EACH_LOG_LINK (nextlinks, prev)
1317                     if ((next = try_combine (insn, prev, nextlinks->insn,
1318                                              NULL_RTX, &new_direct_jump_p,
1319                                              last_combined_insn)) != 0)
1320                       goto retry;
1321                 }
1322
1323               /* Finally, see if any of the insns that this insn links to
1324                  explicitly references CC0.  If so, try this insn, that insn,
1325                  and its predecessor if it sets CC0.  */
1326               FOR_EACH_LOG_LINK (links, insn)
1327                 if (NONJUMP_INSN_P (links->insn)
1328                     && GET_CODE (PATTERN (links->insn)) == SET
1329                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1330                     && (prev = prev_nonnote_insn (links->insn)) != 0
1331                     && NONJUMP_INSN_P (prev)
1332                     && sets_cc0_p (PATTERN (prev))
1333                     && (next = try_combine (insn, links->insn,
1334                                             prev, NULL_RTX, &new_direct_jump_p,
1335                                             last_combined_insn)) != 0)
1336                   goto retry;
1337 #endif
1338
1339               /* Try combining an insn with two different insns whose results it
1340                  uses.  */
1341               FOR_EACH_LOG_LINK (links, insn)
1342                 for (nextlinks = links->next; nextlinks;
1343                      nextlinks = nextlinks->next)
1344                   if ((next = try_combine (insn, links->insn,
1345                                            nextlinks->insn, NULL_RTX,
1346                                            &new_direct_jump_p,
1347                                            last_combined_insn)) != 0)
1348                     goto retry;
1349
1350               /* Try four-instruction combinations.  */
1351               FOR_EACH_LOG_LINK (links, insn)
1352                 {
1353                   struct insn_link *next1;
1354                   rtx link = links->insn;
1355
1356                   /* If the linked insn has been replaced by a note, then there
1357                      is no point in pursuing this chain any further.  */
1358                   if (NOTE_P (link))
1359                     continue;
1360
1361                   FOR_EACH_LOG_LINK (next1, link)
1362                     {
1363                       rtx link1 = next1->insn;
1364                       if (NOTE_P (link1))
1365                         continue;
1366                       /* I0 -> I1 -> I2 -> I3.  */
1367                       FOR_EACH_LOG_LINK (nextlinks, link1)
1368                         if ((next = try_combine (insn, link, link1,
1369                                                  nextlinks->insn,
1370                                                  &new_direct_jump_p,
1371                                                  last_combined_insn)) != 0)
1372                           goto retry;
1373                       /* I0, I1 -> I2, I2 -> I3.  */
1374                       for (nextlinks = next1->next; nextlinks;
1375                            nextlinks = nextlinks->next)
1376                         if ((next = try_combine (insn, link, link1,
1377                                                  nextlinks->insn,
1378                                                  &new_direct_jump_p,
1379                                                  last_combined_insn)) != 0)
1380                           goto retry;
1381                     }
1382
1383                   for (next1 = links->next; next1; next1 = next1->next)
1384                     {
1385                       rtx link1 = next1->insn;
1386                       if (NOTE_P (link1))
1387                         continue;
1388                       /* I0 -> I2; I1, I2 -> I3.  */
1389                       FOR_EACH_LOG_LINK (nextlinks, link)
1390                         if ((next = try_combine (insn, link, link1,
1391                                                  nextlinks->insn,
1392                                                  &new_direct_jump_p,
1393                                                  last_combined_insn)) != 0)
1394                           goto retry;
1395                       /* I0 -> I1; I1, I2 -> I3.  */
1396                       FOR_EACH_LOG_LINK (nextlinks, link1)
1397                         if ((next = try_combine (insn, link, link1,
1398                                                  nextlinks->insn,
1399                                                  &new_direct_jump_p,
1400                                                  last_combined_insn)) != 0)
1401                           goto retry;
1402                     }
1403                 }
1404
1405               /* Try this insn with each REG_EQUAL note it links back to.  */
1406               FOR_EACH_LOG_LINK (links, insn)
1407                 {
1408                   rtx set, note;
1409                   rtx temp = links->insn;
1410                   if ((set = single_set (temp)) != 0
1411                       && (note = find_reg_equal_equiv_note (temp)) != 0
1412                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1413                       /* Avoid using a register that may already been marked
1414                          dead by an earlier instruction.  */
1415                       && ! unmentioned_reg_p (note, SET_SRC (set))
1416                       && (GET_MODE (note) == VOIDmode
1417                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1418                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1419                     {
1420                       /* Temporarily replace the set's source with the
1421                          contents of the REG_EQUAL note.  The insn will
1422                          be deleted or recognized by try_combine.  */
1423                       rtx orig = SET_SRC (set);
1424                       SET_SRC (set) = note;
1425                       i2mod = temp;
1426                       i2mod_old_rhs = copy_rtx (orig);
1427                       i2mod_new_rhs = copy_rtx (note);
1428                       next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1429                                           &new_direct_jump_p,
1430                                           last_combined_insn);
1431                       i2mod = NULL_RTX;
1432                       if (next)
1433                         goto retry;
1434                       SET_SRC (set) = orig;
1435                     }
1436                 }
1437
1438               if (!NOTE_P (insn))
1439                 record_dead_and_set_regs (insn);
1440
1441             retry:
1442               ;
1443             }
1444         }
1445     }
1446
1447   default_rtl_profile ();
1448   clear_bb_flags ();
1449   new_direct_jump_p |= purge_all_dead_edges ();
1450   delete_noop_moves ();
1451
1452   /* Clean up.  */
1453   obstack_free (&insn_link_obstack, NULL);
1454   free (uid_log_links);
1455   free (uid_insn_cost);
1456   reg_stat.release ();
1457
1458   {
1459     struct undo *undo, *next;
1460     for (undo = undobuf.frees; undo; undo = next)
1461       {
1462         next = undo->next;
1463         free (undo);
1464       }
1465     undobuf.frees = 0;
1466   }
1467
1468   total_attempts += combine_attempts;
1469   total_merges += combine_merges;
1470   total_extras += combine_extras;
1471   total_successes += combine_successes;
1472
1473   nonzero_sign_valid = 0;
1474   rtl_hooks = general_rtl_hooks;
1475
1476   /* Make recognizer allow volatile MEMs again.  */
1477   init_recog ();
1478
1479   return new_direct_jump_p;
1480 }
1481
1482 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1483
1484 static void
1485 init_reg_last (void)
1486 {
1487   unsigned int i;
1488   reg_stat_type *p;
1489
1490   FOR_EACH_VEC_ELT (reg_stat, i, p)
1491     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1492 }
1493 \f
1494 /* Set up any promoted values for incoming argument registers.  */
1495
1496 static void
1497 setup_incoming_promotions (rtx first)
1498 {
1499   tree arg;
1500   bool strictly_local = false;
1501
1502   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1503        arg = DECL_CHAIN (arg))
1504     {
1505       rtx x, reg = DECL_INCOMING_RTL (arg);
1506       int uns1, uns3;
1507       enum machine_mode mode1, mode2, mode3, mode4;
1508
1509       /* Only continue if the incoming argument is in a register.  */
1510       if (!REG_P (reg))
1511         continue;
1512
1513       /* Determine, if possible, whether all call sites of the current
1514          function lie within the current compilation unit.  (This does
1515          take into account the exporting of a function via taking its
1516          address, and so forth.)  */
1517       strictly_local = cgraph_local_info (current_function_decl)->local;
1518
1519       /* The mode and signedness of the argument before any promotions happen
1520          (equal to the mode of the pseudo holding it at that stage).  */
1521       mode1 = TYPE_MODE (TREE_TYPE (arg));
1522       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1523
1524       /* The mode and signedness of the argument after any source language and
1525          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1526       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1527       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1528
1529       /* The mode and signedness of the argument as it is actually passed,
1530          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1531       mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1532                                      TREE_TYPE (cfun->decl), 0);
1533
1534       /* The mode of the register in which the argument is being passed.  */
1535       mode4 = GET_MODE (reg);
1536
1537       /* Eliminate sign extensions in the callee when:
1538          (a) A mode promotion has occurred;  */
1539       if (mode1 == mode3)
1540         continue;
1541       /* (b) The mode of the register is the same as the mode of
1542              the argument as it is passed; */
1543       if (mode3 != mode4)
1544         continue;
1545       /* (c) There's no language level extension;  */
1546       if (mode1 == mode2)
1547         ;
1548       /* (c.1) All callers are from the current compilation unit.  If that's
1549          the case we don't have to rely on an ABI, we only have to know
1550          what we're generating right now, and we know that we will do the
1551          mode1 to mode2 promotion with the given sign.  */
1552       else if (!strictly_local)
1553         continue;
1554       /* (c.2) The combination of the two promotions is useful.  This is
1555          true when the signs match, or if the first promotion is unsigned.
1556          In the later case, (sign_extend (zero_extend x)) is the same as
1557          (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
1558       else if (uns1)
1559         uns3 = true;
1560       else if (uns3)
1561         continue;
1562
1563       /* Record that the value was promoted from mode1 to mode3,
1564          so that any sign extension at the head of the current
1565          function may be eliminated.  */
1566       x = gen_rtx_CLOBBER (mode1, const0_rtx);
1567       x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1568       record_value_for_reg (reg, first, x);
1569     }
1570 }
1571
1572 /* Called via note_stores.  If X is a pseudo that is narrower than
1573    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1574
1575    If we are setting only a portion of X and we can't figure out what
1576    portion, assume all bits will be used since we don't know what will
1577    be happening.
1578
1579    Similarly, set how many bits of X are known to be copies of the sign bit
1580    at all locations in the function.  This is the smallest number implied
1581    by any set of X.  */
1582
1583 static void
1584 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1585 {
1586   rtx insn = (rtx) data;
1587   unsigned int num;
1588
1589   if (REG_P (x)
1590       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1591       /* If this register is undefined at the start of the file, we can't
1592          say what its contents were.  */
1593       && ! REGNO_REG_SET_P
1594            (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1595       && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1596     {
1597       reg_stat_type *rsp = &reg_stat[REGNO (x)];
1598
1599       if (set == 0 || GET_CODE (set) == CLOBBER)
1600         {
1601           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1602           rsp->sign_bit_copies = 1;
1603           return;
1604         }
1605
1606       /* If this register is being initialized using itself, and the
1607          register is uninitialized in this basic block, and there are
1608          no LOG_LINKS which set the register, then part of the
1609          register is uninitialized.  In that case we can't assume
1610          anything about the number of nonzero bits.
1611
1612          ??? We could do better if we checked this in
1613          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1614          could avoid making assumptions about the insn which initially
1615          sets the register, while still using the information in other
1616          insns.  We would have to be careful to check every insn
1617          involved in the combination.  */
1618
1619       if (insn
1620           && reg_referenced_p (x, PATTERN (insn))
1621           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1622                                REGNO (x)))
1623         {
1624           struct insn_link *link;
1625
1626           FOR_EACH_LOG_LINK (link, insn)
1627             if (dead_or_set_p (link->insn, x))
1628               break;
1629           if (!link)
1630             {
1631               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1632               rsp->sign_bit_copies = 1;
1633               return;
1634             }
1635         }
1636
1637       /* If this is a complex assignment, see if we can convert it into a
1638          simple assignment.  */
1639       set = expand_field_assignment (set);
1640
1641       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1642          set what we know about X.  */
1643
1644       if (SET_DEST (set) == x
1645           || (paradoxical_subreg_p (SET_DEST (set))
1646               && SUBREG_REG (SET_DEST (set)) == x))
1647         {
1648           rtx src = SET_SRC (set);
1649
1650 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1651           /* If X is narrower than a word and SRC is a non-negative
1652              constant that would appear negative in the mode of X,
1653              sign-extend it for use in reg_stat[].nonzero_bits because some
1654              machines (maybe most) will actually do the sign-extension
1655              and this is the conservative approach.
1656
1657              ??? For 2.5, try to tighten up the MD files in this regard
1658              instead of this kludge.  */
1659
1660           if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1661               && CONST_INT_P (src)
1662               && INTVAL (src) > 0
1663               && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1664             src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1665 #endif
1666
1667           /* Don't call nonzero_bits if it cannot change anything.  */
1668           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1669             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1670           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1671           if (rsp->sign_bit_copies == 0
1672               || rsp->sign_bit_copies > num)
1673             rsp->sign_bit_copies = num;
1674         }
1675       else
1676         {
1677           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1678           rsp->sign_bit_copies = 1;
1679         }
1680     }
1681 }
1682 \f
1683 /* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
1684    optionally insns that were previously combined into I3 or that will be
1685    combined into the merger of INSN and I3.  The order is PRED, PRED2,
1686    INSN, SUCC, SUCC2, I3.
1687
1688    Return 0 if the combination is not allowed for any reason.
1689
1690    If the combination is allowed, *PDEST will be set to the single
1691    destination of INSN and *PSRC to the single source, and this function
1692    will return 1.  */
1693
1694 static int
1695 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1696                rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1697                rtx *pdest, rtx *psrc)
1698 {
1699   int i;
1700   const_rtx set = 0;
1701   rtx src, dest;
1702   rtx p;
1703 #ifdef AUTO_INC_DEC
1704   rtx link;
1705 #endif
1706   bool all_adjacent = true;
1707   int (*is_volatile_p) (const_rtx);
1708
1709   if (succ)
1710     {
1711       if (succ2)
1712         {
1713           if (next_active_insn (succ2) != i3)
1714             all_adjacent = false;
1715           if (next_active_insn (succ) != succ2)
1716             all_adjacent = false;
1717         }
1718       else if (next_active_insn (succ) != i3)
1719         all_adjacent = false;
1720       if (next_active_insn (insn) != succ)
1721         all_adjacent = false;
1722     }
1723   else if (next_active_insn (insn) != i3)
1724     all_adjacent = false;
1725
1726   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1727      or a PARALLEL consisting of such a SET and CLOBBERs.
1728
1729      If INSN has CLOBBER parallel parts, ignore them for our processing.
1730      By definition, these happen during the execution of the insn.  When it
1731      is merged with another insn, all bets are off.  If they are, in fact,
1732      needed and aren't also supplied in I3, they may be added by
1733      recog_for_combine.  Otherwise, it won't match.
1734
1735      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1736      note.
1737
1738      Get the source and destination of INSN.  If more than one, can't
1739      combine.  */
1740
1741   if (GET_CODE (PATTERN (insn)) == SET)
1742     set = PATTERN (insn);
1743   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1744            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1745     {
1746       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1747         {
1748           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1749
1750           switch (GET_CODE (elt))
1751             {
1752             /* This is important to combine floating point insns
1753                for the SH4 port.  */
1754             case USE:
1755               /* Combining an isolated USE doesn't make sense.
1756                  We depend here on combinable_i3pat to reject them.  */
1757               /* The code below this loop only verifies that the inputs of
1758                  the SET in INSN do not change.  We call reg_set_between_p
1759                  to verify that the REG in the USE does not change between
1760                  I3 and INSN.
1761                  If the USE in INSN was for a pseudo register, the matching
1762                  insn pattern will likely match any register; combining this
1763                  with any other USE would only be safe if we knew that the
1764                  used registers have identical values, or if there was
1765                  something to tell them apart, e.g. different modes.  For
1766                  now, we forgo such complicated tests and simply disallow
1767                  combining of USES of pseudo registers with any other USE.  */
1768               if (REG_P (XEXP (elt, 0))
1769                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1770                 {
1771                   rtx i3pat = PATTERN (i3);
1772                   int i = XVECLEN (i3pat, 0) - 1;
1773                   unsigned int regno = REGNO (XEXP (elt, 0));
1774
1775                   do
1776                     {
1777                       rtx i3elt = XVECEXP (i3pat, 0, i);
1778
1779                       if (GET_CODE (i3elt) == USE
1780                           && REG_P (XEXP (i3elt, 0))
1781                           && (REGNO (XEXP (i3elt, 0)) == regno
1782                               ? reg_set_between_p (XEXP (elt, 0),
1783                                                    PREV_INSN (insn), i3)
1784                               : regno >= FIRST_PSEUDO_REGISTER))
1785                         return 0;
1786                     }
1787                   while (--i >= 0);
1788                 }
1789               break;
1790
1791               /* We can ignore CLOBBERs.  */
1792             case CLOBBER:
1793               break;
1794
1795             case SET:
1796               /* Ignore SETs whose result isn't used but not those that
1797                  have side-effects.  */
1798               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1799                   && insn_nothrow_p (insn)
1800                   && !side_effects_p (elt))
1801                 break;
1802
1803               /* If we have already found a SET, this is a second one and
1804                  so we cannot combine with this insn.  */
1805               if (set)
1806                 return 0;
1807
1808               set = elt;
1809               break;
1810
1811             default:
1812               /* Anything else means we can't combine.  */
1813               return 0;
1814             }
1815         }
1816
1817       if (set == 0
1818           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1819              so don't do anything with it.  */
1820           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1821         return 0;
1822     }
1823   else
1824     return 0;
1825
1826   if (set == 0)
1827     return 0;
1828
1829   /* The simplification in expand_field_assignment may call back to
1830      get_last_value, so set safe guard here.  */
1831   subst_low_luid = DF_INSN_LUID (insn);
1832
1833   set = expand_field_assignment (set);
1834   src = SET_SRC (set), dest = SET_DEST (set);
1835
1836   /* Don't eliminate a store in the stack pointer.  */
1837   if (dest == stack_pointer_rtx
1838       /* Don't combine with an insn that sets a register to itself if it has
1839          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1840       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1841       /* Can't merge an ASM_OPERANDS.  */
1842       || GET_CODE (src) == ASM_OPERANDS
1843       /* Can't merge a function call.  */
1844       || GET_CODE (src) == CALL
1845       /* Don't eliminate a function call argument.  */
1846       || (CALL_P (i3)
1847           && (find_reg_fusage (i3, USE, dest)
1848               || (REG_P (dest)
1849                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1850                   && global_regs[REGNO (dest)])))
1851       /* Don't substitute into an incremented register.  */
1852       || FIND_REG_INC_NOTE (i3, dest)
1853       || (succ && FIND_REG_INC_NOTE (succ, dest))
1854       || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1855       /* Don't substitute into a non-local goto, this confuses CFG.  */
1856       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1857       /* Make sure that DEST is not used after SUCC but before I3.  */
1858       || (!all_adjacent
1859           && ((succ2
1860                && (reg_used_between_p (dest, succ2, i3)
1861                    || reg_used_between_p (dest, succ, succ2)))
1862               || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1863       /* Make sure that the value that is to be substituted for the register
1864          does not use any registers whose values alter in between.  However,
1865          If the insns are adjacent, a use can't cross a set even though we
1866          think it might (this can happen for a sequence of insns each setting
1867          the same destination; last_set of that register might point to
1868          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1869          equivalent to the memory so the substitution is valid even if there
1870          are intervening stores.  Also, don't move a volatile asm or
1871          UNSPEC_VOLATILE across any other insns.  */
1872       || (! all_adjacent
1873           && (((!MEM_P (src)
1874                 || ! find_reg_note (insn, REG_EQUIV, src))
1875                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1876               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1877               || GET_CODE (src) == UNSPEC_VOLATILE))
1878       /* Don't combine across a CALL_INSN, because that would possibly
1879          change whether the life span of some REGs crosses calls or not,
1880          and it is a pain to update that information.
1881          Exception: if source is a constant, moving it later can't hurt.
1882          Accept that as a special case.  */
1883       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1884     return 0;
1885
1886   /* DEST must either be a REG or CC0.  */
1887   if (REG_P (dest))
1888     {
1889       /* If register alignment is being enforced for multi-word items in all
1890          cases except for parameters, it is possible to have a register copy
1891          insn referencing a hard register that is not allowed to contain the
1892          mode being copied and which would not be valid as an operand of most
1893          insns.  Eliminate this problem by not combining with such an insn.
1894
1895          Also, on some machines we don't want to extend the life of a hard
1896          register.  */
1897
1898       if (REG_P (src)
1899           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1900                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1901               /* Don't extend the life of a hard register unless it is
1902                  user variable (if we have few registers) or it can't
1903                  fit into the desired register (meaning something special
1904                  is going on).
1905                  Also avoid substituting a return register into I3, because
1906                  reload can't handle a conflict with constraints of other
1907                  inputs.  */
1908               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1909                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1910         return 0;
1911     }
1912   else if (GET_CODE (dest) != CC0)
1913     return 0;
1914
1915
1916   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1917     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1918       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1919         {
1920           /* Don't substitute for a register intended as a clobberable
1921              operand.  */
1922           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1923           if (rtx_equal_p (reg, dest))
1924             return 0;
1925
1926           /* If the clobber represents an earlyclobber operand, we must not
1927              substitute an expression containing the clobbered register.
1928              As we do not analyze the constraint strings here, we have to
1929              make the conservative assumption.  However, if the register is
1930              a fixed hard reg, the clobber cannot represent any operand;
1931              we leave it up to the machine description to either accept or
1932              reject use-and-clobber patterns.  */
1933           if (!REG_P (reg)
1934               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1935               || !fixed_regs[REGNO (reg)])
1936             if (reg_overlap_mentioned_p (reg, src))
1937               return 0;
1938         }
1939
1940   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1941      or not), reject, unless nothing volatile comes between it and I3 */
1942
1943   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1944     {
1945       /* Make sure neither succ nor succ2 contains a volatile reference.  */
1946       if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1947         return 0;
1948       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1949         return 0;
1950       /* We'll check insns between INSN and I3 below.  */
1951     }
1952
1953   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1954      to be an explicit register variable, and was chosen for a reason.  */
1955
1956   if (GET_CODE (src) == ASM_OPERANDS
1957       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1958     return 0;
1959
1960   /* If INSN contains volatile references (specifically volatile MEMs),
1961      we cannot combine across any other volatile references.
1962      Even if INSN doesn't contain volatile references, any intervening
1963      volatile insn might affect machine state.  */
1964
1965   is_volatile_p = volatile_refs_p (PATTERN (insn))
1966     ? volatile_refs_p
1967     : volatile_insn_p;
1968
1969   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1970     if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1971       return 0;
1972
1973   /* If INSN contains an autoincrement or autodecrement, make sure that
1974      register is not used between there and I3, and not already used in
1975      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1976      Also insist that I3 not be a jump; if it were one
1977      and the incremented register were spilled, we would lose.  */
1978
1979 #ifdef AUTO_INC_DEC
1980   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1981     if (REG_NOTE_KIND (link) == REG_INC
1982         && (JUMP_P (i3)
1983             || reg_used_between_p (XEXP (link, 0), insn, i3)
1984             || (pred != NULL_RTX
1985                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1986             || (pred2 != NULL_RTX
1987                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1988             || (succ != NULL_RTX
1989                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1990             || (succ2 != NULL_RTX
1991                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1992             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1993       return 0;
1994 #endif
1995
1996 #ifdef HAVE_cc0
1997   /* Don't combine an insn that follows a CC0-setting insn.
1998      An insn that uses CC0 must not be separated from the one that sets it.
1999      We do, however, allow I2 to follow a CC0-setting insn if that insn
2000      is passed as I1; in that case it will be deleted also.
2001      We also allow combining in this case if all the insns are adjacent
2002      because that would leave the two CC0 insns adjacent as well.
2003      It would be more logical to test whether CC0 occurs inside I1 or I2,
2004      but that would be much slower, and this ought to be equivalent.  */
2005
2006   p = prev_nonnote_insn (insn);
2007   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2008       && ! all_adjacent)
2009     return 0;
2010 #endif
2011
2012   /* If we get here, we have passed all the tests and the combination is
2013      to be allowed.  */
2014
2015   *pdest = dest;
2016   *psrc = src;
2017
2018   return 1;
2019 }
2020 \f
2021 /* LOC is the location within I3 that contains its pattern or the component
2022    of a PARALLEL of the pattern.  We validate that it is valid for combining.
2023
2024    One problem is if I3 modifies its output, as opposed to replacing it
2025    entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2026    doing so would produce an insn that is not equivalent to the original insns.
2027
2028    Consider:
2029
2030          (set (reg:DI 101) (reg:DI 100))
2031          (set (subreg:SI (reg:DI 101) 0) <foo>)
2032
2033    This is NOT equivalent to:
2034
2035          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2036                     (set (reg:DI 101) (reg:DI 100))])
2037
2038    Not only does this modify 100 (in which case it might still be valid
2039    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2040
2041    We can also run into a problem if I2 sets a register that I1
2042    uses and I1 gets directly substituted into I3 (not via I2).  In that
2043    case, we would be getting the wrong value of I2DEST into I3, so we
2044    must reject the combination.  This case occurs when I2 and I1 both
2045    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2046    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2047    of a SET must prevent combination from occurring.  The same situation
2048    can occur for I0, in which case I0_NOT_IN_SRC is set.
2049
2050    Before doing the above check, we first try to expand a field assignment
2051    into a set of logical operations.
2052
2053    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2054    we place a register that is both set and used within I3.  If more than one
2055    such register is detected, we fail.
2056
2057    Return 1 if the combination is valid, zero otherwise.  */
2058
2059 static int
2060 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2061                   int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2062 {
2063   rtx x = *loc;
2064
2065   if (GET_CODE (x) == SET)
2066     {
2067       rtx set = x ;
2068       rtx dest = SET_DEST (set);
2069       rtx src = SET_SRC (set);
2070       rtx inner_dest = dest;
2071       rtx subdest;
2072
2073       while (GET_CODE (inner_dest) == STRICT_LOW_PART
2074              || GET_CODE (inner_dest) == SUBREG
2075              || GET_CODE (inner_dest) == ZERO_EXTRACT)
2076         inner_dest = XEXP (inner_dest, 0);
2077
2078       /* Check for the case where I3 modifies its output, as discussed
2079          above.  We don't want to prevent pseudos from being combined
2080          into the address of a MEM, so only prevent the combination if
2081          i1 or i2 set the same MEM.  */
2082       if ((inner_dest != dest &&
2083            (!MEM_P (inner_dest)
2084             || rtx_equal_p (i2dest, inner_dest)
2085             || (i1dest && rtx_equal_p (i1dest, inner_dest))
2086             || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2087            && (reg_overlap_mentioned_p (i2dest, inner_dest)
2088                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2089                || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2090
2091           /* This is the same test done in can_combine_p except we can't test
2092              all_adjacent; we don't have to, since this instruction will stay
2093              in place, thus we are not considering increasing the lifetime of
2094              INNER_DEST.
2095
2096              Also, if this insn sets a function argument, combining it with
2097              something that might need a spill could clobber a previous
2098              function argument; the all_adjacent test in can_combine_p also
2099              checks this; here, we do a more specific test for this case.  */
2100
2101           || (REG_P (inner_dest)
2102               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2103               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2104                                         GET_MODE (inner_dest))))
2105           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2106           || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2107         return 0;
2108
2109       /* If DEST is used in I3, it is being killed in this insn, so
2110          record that for later.  We have to consider paradoxical
2111          subregs here, since they kill the whole register, but we
2112          ignore partial subregs, STRICT_LOW_PART, etc.
2113          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2114          STACK_POINTER_REGNUM, since these are always considered to be
2115          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
2116       subdest = dest;
2117       if (GET_CODE (subdest) == SUBREG
2118           && (GET_MODE_SIZE (GET_MODE (subdest))
2119               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2120         subdest = SUBREG_REG (subdest);
2121       if (pi3dest_killed
2122           && REG_P (subdest)
2123           && reg_referenced_p (subdest, PATTERN (i3))
2124           && REGNO (subdest) != FRAME_POINTER_REGNUM
2125 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2126           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2127 #endif
2128 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2129           && (REGNO (subdest) != ARG_POINTER_REGNUM
2130               || ! fixed_regs [REGNO (subdest)])
2131 #endif
2132           && REGNO (subdest) != STACK_POINTER_REGNUM)
2133         {
2134           if (*pi3dest_killed)
2135             return 0;
2136
2137           *pi3dest_killed = subdest;
2138         }
2139     }
2140
2141   else if (GET_CODE (x) == PARALLEL)
2142     {
2143       int i;
2144
2145       for (i = 0; i < XVECLEN (x, 0); i++)
2146         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2147                                 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2148           return 0;
2149     }
2150
2151   return 1;
2152 }
2153 \f
2154 /* Return 1 if X is an arithmetic expression that contains a multiplication
2155    and division.  We don't count multiplications by powers of two here.  */
2156
2157 static int
2158 contains_muldiv (rtx x)
2159 {
2160   switch (GET_CODE (x))
2161     {
2162     case MOD:  case DIV:  case UMOD:  case UDIV:
2163       return 1;
2164
2165     case MULT:
2166       return ! (CONST_INT_P (XEXP (x, 1))
2167                 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2168     default:
2169       if (BINARY_P (x))
2170         return contains_muldiv (XEXP (x, 0))
2171             || contains_muldiv (XEXP (x, 1));
2172
2173       if (UNARY_P (x))
2174         return contains_muldiv (XEXP (x, 0));
2175
2176       return 0;
2177     }
2178 }
2179 \f
2180 /* Determine whether INSN can be used in a combination.  Return nonzero if
2181    not.  This is used in try_combine to detect early some cases where we
2182    can't perform combinations.  */
2183
2184 static int
2185 cant_combine_insn_p (rtx insn)
2186 {
2187   rtx set;
2188   rtx src, dest;
2189
2190   /* If this isn't really an insn, we can't do anything.
2191      This can occur when flow deletes an insn that it has merged into an
2192      auto-increment address.  */
2193   if (! INSN_P (insn))
2194     return 1;
2195
2196   /* Never combine loads and stores involving hard regs that are likely
2197      to be spilled.  The register allocator can usually handle such
2198      reg-reg moves by tying.  If we allow the combiner to make
2199      substitutions of likely-spilled regs, reload might die.
2200      As an exception, we allow combinations involving fixed regs; these are
2201      not available to the register allocator so there's no risk involved.  */
2202
2203   set = single_set (insn);
2204   if (! set)
2205     return 0;
2206   src = SET_SRC (set);
2207   dest = SET_DEST (set);
2208   if (GET_CODE (src) == SUBREG)
2209     src = SUBREG_REG (src);
2210   if (GET_CODE (dest) == SUBREG)
2211     dest = SUBREG_REG (dest);
2212   if (REG_P (src) && REG_P (dest)
2213       && ((HARD_REGISTER_P (src)
2214            && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2215            && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2216           || (HARD_REGISTER_P (dest)
2217               && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2218               && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2219     return 1;
2220
2221   return 0;
2222 }
2223
2224 struct likely_spilled_retval_info
2225 {
2226   unsigned regno, nregs;
2227   unsigned mask;
2228 };
2229
2230 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2231    hard registers that are known to be written to / clobbered in full.  */
2232 static void
2233 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2234 {
2235   struct likely_spilled_retval_info *const info =
2236     (struct likely_spilled_retval_info *) data;
2237   unsigned regno, nregs;
2238   unsigned new_mask;
2239
2240   if (!REG_P (XEXP (set, 0)))
2241     return;
2242   regno = REGNO (x);
2243   if (regno >= info->regno + info->nregs)
2244     return;
2245   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2246   if (regno + nregs <= info->regno)
2247     return;
2248   new_mask = (2U << (nregs - 1)) - 1;
2249   if (regno < info->regno)
2250     new_mask >>= info->regno - regno;
2251   else
2252     new_mask <<= regno - info->regno;
2253   info->mask &= ~new_mask;
2254 }
2255
2256 /* Return nonzero iff part of the return value is live during INSN, and
2257    it is likely spilled.  This can happen when more than one insn is needed
2258    to copy the return value, e.g. when we consider to combine into the
2259    second copy insn for a complex value.  */
2260
2261 static int
2262 likely_spilled_retval_p (rtx insn)
2263 {
2264   rtx use = BB_END (this_basic_block);
2265   rtx reg, p;
2266   unsigned regno, nregs;
2267   /* We assume here that no machine mode needs more than
2268      32 hard registers when the value overlaps with a register
2269      for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
2270   unsigned mask;
2271   struct likely_spilled_retval_info info;
2272
2273   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2274     return 0;
2275   reg = XEXP (PATTERN (use), 0);
2276   if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2277     return 0;
2278   regno = REGNO (reg);
2279   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2280   if (nregs == 1)
2281     return 0;
2282   mask = (2U << (nregs - 1)) - 1;
2283
2284   /* Disregard parts of the return value that are set later.  */
2285   info.regno = regno;
2286   info.nregs = nregs;
2287   info.mask = mask;
2288   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2289     if (INSN_P (p))
2290       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2291   mask = info.mask;
2292
2293   /* Check if any of the (probably) live return value registers is
2294      likely spilled.  */
2295   nregs --;
2296   do
2297     {
2298       if ((mask & 1 << nregs)
2299           && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2300         return 1;
2301     } while (nregs--);
2302   return 0;
2303 }
2304
2305 /* Adjust INSN after we made a change to its destination.
2306
2307    Changing the destination can invalidate notes that say something about
2308    the results of the insn and a LOG_LINK pointing to the insn.  */
2309
2310 static void
2311 adjust_for_new_dest (rtx insn)
2312 {
2313   /* For notes, be conservative and simply remove them.  */
2314   remove_reg_equal_equiv_notes (insn);
2315
2316   /* The new insn will have a destination that was previously the destination
2317      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2318      the next use of that destination.  */
2319   distribute_links (alloc_insn_link (insn, NULL));
2320
2321   df_insn_rescan (insn);
2322 }
2323
2324 /* Return TRUE if combine can reuse reg X in mode MODE.
2325    ADDED_SETS is nonzero if the original set is still required.  */
2326 static bool
2327 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2328 {
2329   unsigned int regno;
2330
2331   if (!REG_P(x))
2332     return false;
2333
2334   regno = REGNO (x);
2335   /* Allow hard registers if the new mode is legal, and occupies no more
2336      registers than the old mode.  */
2337   if (regno < FIRST_PSEUDO_REGISTER)
2338     return (HARD_REGNO_MODE_OK (regno, mode)
2339             && (hard_regno_nregs[regno][GET_MODE (x)]
2340                 >= hard_regno_nregs[regno][mode]));
2341
2342   /* Or a pseudo that is only used once.  */
2343   return (REG_N_SETS (regno) == 1 && !added_sets
2344           && !REG_USERVAR_P (x));
2345 }
2346
2347
2348 /* Check whether X, the destination of a set, refers to part of
2349    the register specified by REG.  */
2350
2351 static bool
2352 reg_subword_p (rtx x, rtx reg)
2353 {
2354   /* Check that reg is an integer mode register.  */
2355   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2356     return false;
2357
2358   if (GET_CODE (x) == STRICT_LOW_PART
2359       || GET_CODE (x) == ZERO_EXTRACT)
2360     x = XEXP (x, 0);
2361
2362   return GET_CODE (x) == SUBREG
2363          && SUBREG_REG (x) == reg
2364          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2365 }
2366
2367 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2368    Note that the INSN should be deleted *after* removing dead edges, so
2369    that the kept edge is the fallthrough edge for a (set (pc) (pc))
2370    but not for a (set (pc) (label_ref FOO)).  */
2371
2372 static void
2373 update_cfg_for_uncondjump (rtx insn)
2374 {
2375   basic_block bb = BLOCK_FOR_INSN (insn);
2376   gcc_assert (BB_END (bb) == insn);
2377
2378   purge_dead_edges (bb);
2379
2380   delete_insn (insn);
2381   if (EDGE_COUNT (bb->succs) == 1)
2382     {
2383       rtx insn;
2384
2385       single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2386
2387       /* Remove barriers from the footer if there are any.  */
2388       for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2389         if (BARRIER_P (insn))
2390           {
2391             if (PREV_INSN (insn))
2392               NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2393             else
2394               BB_FOOTER (bb) = NEXT_INSN (insn);
2395             if (NEXT_INSN (insn))
2396               PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2397           }
2398         else if (LABEL_P (insn))
2399           break;
2400     }
2401 }
2402
2403 /* Try to combine the insns I0, I1 and I2 into I3.
2404    Here I0, I1 and I2 appear earlier than I3.
2405    I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2406    I3.
2407
2408    If we are combining more than two insns and the resulting insn is not
2409    recognized, try splitting it into two insns.  If that happens, I2 and I3
2410    are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2411    Otherwise, I0, I1 and I2 are pseudo-deleted.
2412
2413    Return 0 if the combination does not work.  Then nothing is changed.
2414    If we did the combination, return the insn at which combine should
2415    resume scanning.
2416
2417    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2418    new direct jump instruction.
2419
2420    LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2421    been I3 passed to an earlier try_combine within the same basic
2422    block.  */
2423
2424 static rtx
2425 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2426              rtx last_combined_insn)
2427 {
2428   /* New patterns for I3 and I2, respectively.  */
2429   rtx newpat, newi2pat = 0;
2430   rtvec newpat_vec_with_clobbers = 0;
2431   int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2432   /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2433      dead.  */
2434   int added_sets_0, added_sets_1, added_sets_2;
2435   /* Total number of SETs to put into I3.  */
2436   int total_sets;
2437   /* Nonzero if I2's or I1's body now appears in I3.  */
2438   int i2_is_used = 0, i1_is_used = 0;
2439   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2440   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2441   /* Contains I3 if the destination of I3 is used in its source, which means
2442      that the old life of I3 is being killed.  If that usage is placed into
2443      I2 and not in I3, a REG_DEAD note must be made.  */
2444   rtx i3dest_killed = 0;
2445   /* SET_DEST and SET_SRC of I2, I1 and I0.  */
2446   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2447   /* Copy of SET_SRC of I1 and I0, if needed.  */
2448   rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2449   /* Set if I2DEST was reused as a scratch register.  */
2450   bool i2scratch = false;
2451   /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
2452   rtx i0pat = 0, i1pat = 0, i2pat = 0;
2453   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2454   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2455   int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2456   int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2457   int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2458   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2459   rtx new_i3_notes, new_i2_notes;
2460   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2461   int i3_subst_into_i2 = 0;
2462   /* Notes that I1, I2 or I3 is a MULT operation.  */
2463   int have_mult = 0;
2464   int swap_i2i3 = 0;
2465   int changed_i3_dest = 0;
2466
2467   int maxreg;
2468   rtx temp;
2469   struct insn_link *link;
2470   rtx other_pat = 0;
2471   rtx new_other_notes;
2472   int i;
2473
2474   /* Only try four-insn combinations when there's high likelihood of
2475      success.  Look for simple insns, such as loads of constants or
2476      binary operations involving a constant.  */
2477   if (i0)
2478     {
2479       int i;
2480       int ngood = 0;
2481       int nshift = 0;
2482
2483       if (!flag_expensive_optimizations)
2484         return 0;
2485
2486       for (i = 0; i < 4; i++)
2487         {
2488           rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2489           rtx set = single_set (insn);
2490           rtx src;
2491           if (!set)
2492             continue;
2493           src = SET_SRC (set);
2494           if (CONSTANT_P (src))
2495             {
2496               ngood += 2;
2497               break;
2498             }
2499           else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2500             ngood++;
2501           else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2502                    || GET_CODE (src) == LSHIFTRT)
2503             nshift++;
2504         }
2505       if (ngood < 2 && nshift < 2)
2506         return 0;
2507     }
2508
2509   /* Exit early if one of the insns involved can't be used for
2510      combinations.  */
2511   if (cant_combine_insn_p (i3)
2512       || cant_combine_insn_p (i2)
2513       || (i1 && cant_combine_insn_p (i1))
2514       || (i0 && cant_combine_insn_p (i0))
2515       || likely_spilled_retval_p (i3))
2516     return 0;
2517
2518   combine_attempts++;
2519   undobuf.other_insn = 0;
2520
2521   /* Reset the hard register usage information.  */
2522   CLEAR_HARD_REG_SET (newpat_used_regs);
2523
2524   if (dump_file && (dump_flags & TDF_DETAILS))
2525     {
2526       if (i0)
2527         fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2528                  INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2529       else if (i1)
2530         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2531                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2532       else
2533         fprintf (dump_file, "\nTrying %d -> %d:\n",
2534                  INSN_UID (i2), INSN_UID (i3));
2535     }
2536
2537   /* If multiple insns feed into one of I2 or I3, they can be in any
2538      order.  To simplify the code below, reorder them in sequence.  */
2539   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2540     temp = i2, i2 = i0, i0 = temp;
2541   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2542     temp = i1, i1 = i0, i0 = temp;
2543   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2544     temp = i1, i1 = i2, i2 = temp;
2545
2546   added_links_insn = 0;
2547
2548   /* First check for one important special case that the code below will
2549      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2550      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2551      we may be able to replace that destination with the destination of I3.
2552      This occurs in the common code where we compute both a quotient and
2553      remainder into a structure, in which case we want to do the computation
2554      directly into the structure to avoid register-register copies.
2555
2556      Note that this case handles both multiple sets in I2 and also cases
2557      where I2 has a number of CLOBBERs inside the PARALLEL.
2558
2559      We make very conservative checks below and only try to handle the
2560      most common cases of this.  For example, we only handle the case
2561      where I2 and I3 are adjacent to avoid making difficult register
2562      usage tests.  */
2563
2564   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2565       && REG_P (SET_SRC (PATTERN (i3)))
2566       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2567       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2568       && GET_CODE (PATTERN (i2)) == PARALLEL
2569       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2570       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2571          below would need to check what is inside (and reg_overlap_mentioned_p
2572          doesn't support those codes anyway).  Don't allow those destinations;
2573          the resulting insn isn't likely to be recognized anyway.  */
2574       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2575       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2576       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2577                                     SET_DEST (PATTERN (i3)))
2578       && next_active_insn (i2) == i3)
2579     {
2580       rtx p2 = PATTERN (i2);
2581
2582       /* Make sure that the destination of I3,
2583          which we are going to substitute into one output of I2,
2584          is not used within another output of I2.  We must avoid making this:
2585          (parallel [(set (mem (reg 69)) ...)
2586                     (set (reg 69) ...)])
2587          which is not well-defined as to order of actions.
2588          (Besides, reload can't handle output reloads for this.)
2589
2590          The problem can also happen if the dest of I3 is a memory ref,
2591          if another dest in I2 is an indirect memory ref.  */
2592       for (i = 0; i < XVECLEN (p2, 0); i++)
2593         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2594              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2595             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2596                                         SET_DEST (XVECEXP (p2, 0, i))))
2597           break;
2598
2599       if (i == XVECLEN (p2, 0))
2600         for (i = 0; i < XVECLEN (p2, 0); i++)
2601           if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2602               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2603             {
2604               combine_merges++;
2605
2606               subst_insn = i3;
2607               subst_low_luid = DF_INSN_LUID (i2);
2608
2609               added_sets_2 = added_sets_1 = added_sets_0 = 0;
2610               i2src = SET_SRC (XVECEXP (p2, 0, i));
2611               i2dest = SET_DEST (XVECEXP (p2, 0, i));
2612               i2dest_killed = dead_or_set_p (i2, i2dest);
2613
2614               /* Replace the dest in I2 with our dest and make the resulting
2615                  insn the new pattern for I3.  Then skip to where we validate
2616                  the pattern.  Everything was set up above.  */
2617               SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2618               newpat = p2;
2619               i3_subst_into_i2 = 1;
2620               goto validate_replacement;
2621             }
2622     }
2623
2624   /* If I2 is setting a pseudo to a constant and I3 is setting some
2625      sub-part of it to another constant, merge them by making a new
2626      constant.  */
2627   if (i1 == 0
2628       && (temp = single_set (i2)) != 0
2629       && CONST_SCALAR_INT_P (SET_SRC (temp))
2630       && GET_CODE (PATTERN (i3)) == SET
2631       && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2632       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2633     {
2634       rtx dest = SET_DEST (PATTERN (i3));
2635       int offset = -1;
2636       int width = 0;
2637
2638       if (GET_CODE (dest) == ZERO_EXTRACT)
2639         {
2640           if (CONST_INT_P (XEXP (dest, 1))
2641               && CONST_INT_P (XEXP (dest, 2)))
2642             {
2643               width = INTVAL (XEXP (dest, 1));
2644               offset = INTVAL (XEXP (dest, 2));
2645               dest = XEXP (dest, 0);
2646               if (BITS_BIG_ENDIAN)
2647                 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2648             }
2649         }
2650       else
2651         {
2652           if (GET_CODE (dest) == STRICT_LOW_PART)
2653             dest = XEXP (dest, 0);
2654           width = GET_MODE_PRECISION (GET_MODE (dest));
2655           offset = 0;
2656         }
2657
2658       if (offset >= 0)
2659         {
2660           /* If this is the low part, we're done.  */
2661           if (subreg_lowpart_p (dest))
2662             ;
2663           /* Handle the case where inner is twice the size of outer.  */
2664           else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2665                    == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2666             offset += GET_MODE_PRECISION (GET_MODE (dest));
2667           /* Otherwise give up for now.  */
2668           else
2669             offset = -1;
2670         }
2671
2672       if (offset >= 0
2673           && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2674               <= HOST_BITS_PER_DOUBLE_INT))
2675         {
2676           double_int m, o, i;
2677           rtx inner = SET_SRC (PATTERN (i3));
2678           rtx outer = SET_SRC (temp);
2679
2680           o = rtx_to_double_int (outer);
2681           i = rtx_to_double_int (inner);
2682
2683           m = double_int::mask (width);
2684           i &= m;
2685           m = m.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2686           i = i.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2687           o = o.and_not (m) | i;
2688
2689           combine_merges++;
2690           subst_insn = i3;
2691           subst_low_luid = DF_INSN_LUID (i2);
2692           added_sets_2 = added_sets_1 = added_sets_0 = 0;
2693           i2dest = SET_DEST (temp);
2694           i2dest_killed = dead_or_set_p (i2, i2dest);
2695
2696           /* Replace the source in I2 with the new constant and make the
2697              resulting insn the new pattern for I3.  Then skip to where we
2698              validate the pattern.  Everything was set up above.  */
2699           SUBST (SET_SRC (temp),
2700                  immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2701
2702           newpat = PATTERN (i2);
2703
2704           /* The dest of I3 has been replaced with the dest of I2.  */
2705           changed_i3_dest = 1;
2706           goto validate_replacement;
2707         }
2708     }
2709
2710 #ifndef HAVE_cc0
2711   /* If we have no I1 and I2 looks like:
2712         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2713                    (set Y OP)])
2714      make up a dummy I1 that is
2715         (set Y OP)
2716      and change I2 to be
2717         (set (reg:CC X) (compare:CC Y (const_int 0)))
2718
2719      (We can ignore any trailing CLOBBERs.)
2720
2721      This undoes a previous combination and allows us to match a branch-and-
2722      decrement insn.  */
2723
2724   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2725       && XVECLEN (PATTERN (i2), 0) >= 2
2726       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2727       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2728           == MODE_CC)
2729       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2730       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2731       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2732       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2733       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2734                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2735     {
2736       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2737         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2738           break;
2739
2740       if (i == 1)
2741         {
2742           /* We make I1 with the same INSN_UID as I2.  This gives it
2743              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2744              never appear in the insn stream so giving it the same INSN_UID
2745              as I2 will not cause a problem.  */
2746
2747           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2748                              BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2749                              INSN_LOCATION (i2), -1, NULL_RTX);
2750
2751           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2752           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2753                  SET_DEST (PATTERN (i1)));
2754           SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2755         }
2756     }
2757 #endif
2758
2759   /* Verify that I2 and I1 are valid for combining.  */
2760   if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2761       || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2762                                  &i1dest, &i1src))
2763       || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2764                                  &i0dest, &i0src)))
2765     {
2766       undo_all ();
2767       return 0;
2768     }
2769
2770   /* Record whether I2DEST is used in I2SRC and similarly for the other
2771      cases.  Knowing this will help in register status updating below.  */
2772   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2773   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2774   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2775   i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2776   i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2777   i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2778   i2dest_killed = dead_or_set_p (i2, i2dest);
2779   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2780   i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2781
2782   /* For the earlier insns, determine which of the subsequent ones they
2783      feed.  */
2784   i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2785   i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2786   i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2787                           : (!reg_overlap_mentioned_p (i1dest, i0dest)
2788                              && reg_overlap_mentioned_p (i0dest, i2src))));
2789
2790   /* Ensure that I3's pattern can be the destination of combines.  */
2791   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2792                           i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2793                           i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2794                                  || (i1dest_in_i0src && !i0_feeds_i1_n)),
2795                           &i3dest_killed))
2796     {
2797       undo_all ();
2798       return 0;
2799     }
2800
2801   /* See if any of the insns is a MULT operation.  Unless one is, we will
2802      reject a combination that is, since it must be slower.  Be conservative
2803      here.  */
2804   if (GET_CODE (i2src) == MULT
2805       || (i1 != 0 && GET_CODE (i1src) == MULT)
2806       || (i0 != 0 && GET_CODE (i0src) == MULT)
2807       || (GET_CODE (PATTERN (i3)) == SET
2808           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2809     have_mult = 1;
2810
2811   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2812      We used to do this EXCEPT in one case: I3 has a post-inc in an
2813      output operand.  However, that exception can give rise to insns like
2814         mov r3,(r3)+
2815      which is a famous insn on the PDP-11 where the value of r3 used as the
2816      source was model-dependent.  Avoid this sort of thing.  */
2817
2818 #if 0
2819   if (!(GET_CODE (PATTERN (i3)) == SET
2820         && REG_P (SET_SRC (PATTERN (i3)))
2821         && MEM_P (SET_DEST (PATTERN (i3)))
2822         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2823             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2824     /* It's not the exception.  */
2825 #endif
2826 #ifdef AUTO_INC_DEC
2827     {
2828       rtx link;
2829       for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2830         if (REG_NOTE_KIND (link) == REG_INC
2831             && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2832                 || (i1 != 0
2833                     && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2834           {
2835             undo_all ();
2836             return 0;
2837           }
2838     }
2839 #endif
2840
2841   /* See if the SETs in I1 or I2 need to be kept around in the merged
2842      instruction: whenever the value set there is still needed past I3.
2843      For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2844
2845      For the SET in I1, we have two cases: if I1 and I2 independently feed
2846      into I3, the set in I1 needs to be kept around unless I1DEST dies
2847      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2848      in I1 needs to be kept around unless I1DEST dies or is set in either
2849      I2 or I3.  The same considerations apply to I0.  */
2850
2851   added_sets_2 = !dead_or_set_p (i3, i2dest);
2852
2853   if (i1)
2854     added_sets_1 = !(dead_or_set_p (i3, i1dest)
2855                      || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2856   else
2857     added_sets_1 = 0;
2858
2859   if (i0)
2860     added_sets_0 =  !(dead_or_set_p (i3, i0dest)
2861                       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
2862                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
2863                           && dead_or_set_p (i2, i0dest)));
2864   else
2865     added_sets_0 = 0;
2866
2867   /* We are about to copy insns for the case where they need to be kept
2868      around.  Check that they can be copied in the merged instruction.  */
2869
2870   if (targetm.cannot_copy_insn_p
2871       && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2872           || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2873           || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2874     {
2875       undo_all ();
2876       return 0;
2877     }
2878
2879   /* If the set in I2 needs to be kept around, we must make a copy of
2880      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2881      PATTERN (I2), we are only substituting for the original I1DEST, not into
2882      an already-substituted copy.  This also prevents making self-referential
2883      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2884      I2DEST.  */
2885
2886   if (added_sets_2)
2887     {
2888       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2889         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2890       else
2891         i2pat = copy_rtx (PATTERN (i2));
2892     }
2893
2894   if (added_sets_1)
2895     {
2896       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2897         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2898       else
2899         i1pat = copy_rtx (PATTERN (i1));
2900     }
2901
2902   if (added_sets_0)
2903     {
2904       if (GET_CODE (PATTERN (i0)) == PARALLEL)
2905         i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2906       else
2907         i0pat = copy_rtx (PATTERN (i0));
2908     }
2909
2910   combine_merges++;
2911
2912   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2913
2914   maxreg = max_reg_num ();
2915
2916   subst_insn = i3;
2917
2918 #ifndef HAVE_cc0
2919   /* Many machines that don't use CC0 have insns that can both perform an
2920      arithmetic operation and set the condition code.  These operations will
2921      be represented as a PARALLEL with the first element of the vector
2922      being a COMPARE of an arithmetic operation with the constant zero.
2923      The second element of the vector will set some pseudo to the result
2924      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2925      match such a pattern and so will generate an extra insn.   Here we test
2926      for this case, where both the comparison and the operation result are
2927      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2928      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2929
2930   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2931       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2932       && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
2933       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2934     {
2935       rtx newpat_dest;
2936       rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
2937       rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
2938       enum machine_mode compare_mode, orig_compare_mode;
2939       enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
2940
2941       newpat = PATTERN (i3);
2942       newpat_dest = SET_DEST (newpat);
2943       compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
2944
2945       if (undobuf.other_insn == 0
2946           && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
2947                                             &cc_use_insn)))
2948         {
2949           compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
2950           compare_code = simplify_compare_const (compare_code,
2951                                                  op0, &op1);
2952           target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
2953         }
2954
2955       /* Do the rest only if op1 is const0_rtx, which may be the
2956          result of simplification.  */
2957       if (op1 == const0_rtx)
2958         {
2959           /* If a single use of the CC is found, prepare to modify it
2960              when SELECT_CC_MODE returns a new CC-class mode, or when
2961              the above simplify_compare_const() returned a new comparison
2962              operator.  undobuf.other_insn is assigned the CC use insn
2963              when modifying it.  */
2964           if (cc_use_loc)
2965             {
2966 #ifdef SELECT_CC_MODE
2967               enum machine_mode new_mode
2968                 = SELECT_CC_MODE (compare_code, op0, op1);
2969               if (new_mode != orig_compare_mode
2970                   && can_change_dest_mode (SET_DEST (newpat),
2971                                            added_sets_2, new_mode))
2972                 {
2973                   unsigned int regno = REGNO (newpat_dest);
2974                   compare_mode = new_mode;
2975                   if (regno < FIRST_PSEUDO_REGISTER)
2976                     newpat_dest = gen_rtx_REG (compare_mode, regno);
2977                   else
2978                     {
2979                       SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2980                       newpat_dest = regno_reg_rtx[regno];
2981                     }
2982                 }
2983 #endif
2984               /* Cases for modifying the CC-using comparison.  */
2985               if (compare_code != orig_compare_code
2986                   /* ??? Do we need to verify the zero rtx?  */
2987                   && XEXP (*cc_use_loc, 1) == const0_rtx)
2988                 {
2989                   /* Replace cc_use_loc with entire new RTX.  */
2990                   SUBST (*cc_use_loc,
2991                          gen_rtx_fmt_ee (compare_code, compare_mode,
2992                                          newpat_dest, const0_rtx));
2993                   undobuf.other_insn = cc_use_insn;
2994                 }
2995               else if (compare_mode != orig_compare_mode)
2996                 {
2997                   /* Just replace the CC reg with a new mode.  */
2998                   SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
2999                   undobuf.other_insn = cc_use_insn;
3000                 }
3001             }
3002
3003           /* Now we modify the current newpat:
3004              First, SET_DEST(newpat) is updated if the CC mode has been
3005              altered. For targets without SELECT_CC_MODE, this should be
3006              optimized away.  */
3007           if (compare_mode != orig_compare_mode)
3008             SUBST (SET_DEST (newpat), newpat_dest);
3009           /* This is always done to propagate i2src into newpat.  */
3010           SUBST (SET_SRC (newpat),
3011                  gen_rtx_COMPARE (compare_mode, op0, op1));
3012           /* Create new version of i2pat if needed; the below PARALLEL
3013              creation needs this to work correctly.  */
3014           if (! rtx_equal_p (i2src, op0))
3015             i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3016           i2_is_used = 1;
3017         }
3018     }
3019 #endif
3020
3021   if (i2_is_used == 0)
3022     {
3023       /* It is possible that the source of I2 or I1 may be performing
3024          an unneeded operation, such as a ZERO_EXTEND of something
3025          that is known to have the high part zero.  Handle that case
3026          by letting subst look at the inner insns.
3027
3028          Another way to do this would be to have a function that tries
3029          to simplify a single insn instead of merging two or more
3030          insns.  We don't do this because of the potential of infinite
3031          loops and because of the potential extra memory required.
3032          However, doing it the way we are is a bit of a kludge and
3033          doesn't catch all cases.
3034
3035          But only do this if -fexpensive-optimizations since it slows
3036          things down and doesn't usually win.
3037
3038          This is not done in the COMPARE case above because the
3039          unmodified I2PAT is used in the PARALLEL and so a pattern
3040          with a modified I2SRC would not match.  */
3041
3042       if (flag_expensive_optimizations)
3043         {
3044           /* Pass pc_rtx so no substitutions are done, just
3045              simplifications.  */
3046           if (i1)
3047             {
3048               subst_low_luid = DF_INSN_LUID (i1);
3049               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3050             }
3051
3052           subst_low_luid = DF_INSN_LUID (i2);
3053           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3054         }
3055
3056       n_occurrences = 0;                /* `subst' counts here */
3057       subst_low_luid = DF_INSN_LUID (i2);
3058
3059       /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3060          copy of I2SRC each time we substitute it, in order to avoid creating
3061          self-referential RTL when we will be substituting I1SRC for I1DEST
3062          later.  Likewise if I0 feeds into I2, either directly or indirectly
3063          through I1, and I0DEST is in I0SRC.  */
3064       newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3065                       (i1_feeds_i2_n && i1dest_in_i1src)
3066                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3067                           && i0dest_in_i0src));
3068       substed_i2 = 1;
3069
3070       /* Record whether I2's body now appears within I3's body.  */
3071       i2_is_used = n_occurrences;
3072     }
3073
3074   /* If we already got a failure, don't try to do more.  Otherwise, try to
3075      substitute I1 if we have it.  */
3076
3077   if (i1 && GET_CODE (newpat) != CLOBBER)
3078     {
3079       /* Check that an autoincrement side-effect on I1 has not been lost.
3080          This happens if I1DEST is mentioned in I2 and dies there, and
3081          has disappeared from the new pattern.  */
3082       if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3083            && i1_feeds_i2_n
3084            && dead_or_set_p (i2, i1dest)
3085            && !reg_overlap_mentioned_p (i1dest, newpat))
3086            /* Before we can do this substitution, we must redo the test done
3087               above (see detailed comments there) that ensures I1DEST isn't
3088               mentioned in any SETs in NEWPAT that are field assignments.  */
3089           || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3090                                 0, 0, 0))
3091         {
3092           undo_all ();
3093           return 0;
3094         }
3095
3096       n_occurrences = 0;
3097       subst_low_luid = DF_INSN_LUID (i1);
3098
3099       /* If the following substitution will modify I1SRC, make a copy of it
3100          for the case where it is substituted for I1DEST in I2PAT later.  */
3101       if (added_sets_2 && i1_feeds_i2_n)
3102         i1src_copy = copy_rtx (i1src);
3103
3104       /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3105          copy of I1SRC each time we substitute it, in order to avoid creating
3106          self-referential RTL when we will be substituting I0SRC for I0DEST
3107          later.  */
3108       newpat = subst (newpat, i1dest, i1src, 0, 0,
3109                       i0_feeds_i1_n && i0dest_in_i0src);
3110       substed_i1 = 1;
3111
3112       /* Record whether I1's body now appears within I3's body.  */
3113       i1_is_used = n_occurrences;
3114     }
3115
3116   /* Likewise for I0 if we have it.  */
3117
3118   if (i0 && GET_CODE (newpat) != CLOBBER)
3119     {
3120       if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3121            && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3122                || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3123            && !reg_overlap_mentioned_p (i0dest, newpat))
3124           || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3125                                 0, 0, 0))
3126         {
3127           undo_all ();
3128           return 0;
3129         }
3130
3131       /* If the following substitution will modify I0SRC, make a copy of it
3132          for the case where it is substituted for I0DEST in I1PAT later.  */
3133       if (added_sets_1 && i0_feeds_i1_n)
3134         i0src_copy = copy_rtx (i0src);
3135       /* And a copy for I0DEST in I2PAT substitution.  */
3136       if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3137                            || (i0_feeds_i2_n)))
3138         i0src_copy2 = copy_rtx (i0src);
3139
3140       n_occurrences = 0;
3141       subst_low_luid = DF_INSN_LUID (i0);
3142       newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3143       substed_i0 = 1;
3144     }
3145
3146   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3147      to count all the ways that I2SRC and I1SRC can be used.  */
3148   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3149        && i2_is_used + added_sets_2 > 1)
3150       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3151           && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3152               > 1))
3153       || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3154           && (n_occurrences + added_sets_0
3155               + (added_sets_1 && i0_feeds_i1_n)
3156               + (added_sets_2 && i0_feeds_i2_n)
3157               > 1))
3158       /* Fail if we tried to make a new register.  */
3159       || max_reg_num () != maxreg
3160       /* Fail if we couldn't do something and have a CLOBBER.  */
3161       || GET_CODE (newpat) == CLOBBER
3162       /* Fail if this new pattern is a MULT and we didn't have one before
3163          at the outer level.  */
3164       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3165           && ! have_mult))
3166     {
3167       undo_all ();
3168       return 0;
3169     }
3170
3171   /* If the actions of the earlier insns must be kept
3172      in addition to substituting them into the latest one,
3173      we must make a new PARALLEL for the latest insn
3174      to hold additional the SETs.  */
3175
3176   if (added_sets_0 || added_sets_1 || added_sets_2)
3177     {
3178       int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3179       combine_extras++;
3180
3181       if (GET_CODE (newpat) == PARALLEL)
3182         {
3183           rtvec old = XVEC (newpat, 0);
3184           total_sets = XVECLEN (newpat, 0) + extra_sets;
3185           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3186           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3187                   sizeof (old->elem[0]) * old->num_elem);
3188         }
3189       else
3190         {
3191           rtx old = newpat;
3192           total_sets = 1 + extra_sets;
3193           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3194           XVECEXP (newpat, 0, 0) = old;
3195         }
3196
3197       if (added_sets_0)
3198         XVECEXP (newpat, 0, --total_sets) = i0pat;
3199
3200       if (added_sets_1)
3201         {
3202           rtx t = i1pat;
3203           if (i0_feeds_i1_n)
3204             t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3205
3206           XVECEXP (newpat, 0, --total_sets) = t;
3207         }
3208       if (added_sets_2)
3209         {
3210           rtx t = i2pat;
3211           if (i1_feeds_i2_n)
3212             t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3213                        i0_feeds_i1_n && i0dest_in_i0src);
3214           if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3215             t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3216
3217           XVECEXP (newpat, 0, --total_sets) = t;
3218         }
3219     }
3220
3221  validate_replacement:
3222
3223   /* Note which hard regs this insn has as inputs.  */
3224   mark_used_regs_combine (newpat);
3225
3226   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3227      consider splitting this pattern, we might need these clobbers.  */
3228   if (i1 && GET_CODE (newpat) == PARALLEL
3229       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3230     {
3231       int len = XVECLEN (newpat, 0);
3232
3233       newpat_vec_with_clobbers = rtvec_alloc (len);
3234       for (i = 0; i < len; i++)
3235         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3236     }
3237
3238   /* Is the result of combination a valid instruction?  */
3239   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3240
3241   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3242      the second SET's destination is a register that is unused and isn't
3243      marked as an instruction that might trap in an EH region.  In that case,
3244      we just need the first SET.   This can occur when simplifying a divmod
3245      insn.  We *must* test for this case here because the code below that
3246      splits two independent SETs doesn't handle this case correctly when it
3247      updates the register status.
3248
3249      It's pointless doing this if we originally had two sets, one from
3250      i3, and one from i2.  Combining then splitting the parallel results
3251      in the original i2 again plus an invalid insn (which we delete).
3252      The net effect is only to move instructions around, which makes
3253      debug info less accurate.
3254
3255      Also check the case where the first SET's destination is unused.
3256      That would not cause incorrect code, but does cause an unneeded
3257      insn to remain.  */
3258
3259   if (insn_code_number < 0
3260       && !(added_sets_2 && i1 == 0)
3261       && GET_CODE (newpat) == PARALLEL
3262       && XVECLEN (newpat, 0) == 2
3263       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3264       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3265       && asm_noperands (newpat) < 0)
3266     {
3267       rtx set0 = XVECEXP (newpat, 0, 0);
3268       rtx set1 = XVECEXP (newpat, 0, 1);
3269
3270       if (((REG_P (SET_DEST (set1))
3271             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3272            || (GET_CODE (SET_DEST (set1)) == SUBREG
3273                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3274           && insn_nothrow_p (i3)
3275           && !side_effects_p (SET_SRC (set1)))
3276         {
3277           newpat = set0;
3278           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3279         }
3280
3281       else if (((REG_P (SET_DEST (set0))
3282                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3283                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3284                     && find_reg_note (i3, REG_UNUSED,
3285                                       SUBREG_REG (SET_DEST (set0)))))
3286                && insn_nothrow_p (i3)
3287                && !side_effects_p (SET_SRC (set0)))
3288         {
3289           newpat = set1;
3290           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3291
3292           if (insn_code_number >= 0)
3293             changed_i3_dest = 1;
3294         }
3295     }
3296
3297   /* If we were combining three insns and the result is a simple SET
3298      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3299      insns.  There are two ways to do this.  It can be split using a
3300      machine-specific method (like when you have an addition of a large
3301      constant) or by combine in the function find_split_point.  */
3302
3303   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3304       && asm_noperands (newpat) < 0)
3305     {
3306       rtx parallel, m_split, *split;
3307
3308       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3309          use I2DEST as a scratch register will help.  In the latter case,
3310          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3311
3312       m_split = combine_split_insns (newpat, i3);
3313
3314       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3315          inputs of NEWPAT.  */
3316
3317       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3318          possible to try that as a scratch reg.  This would require adding
3319          more code to make it work though.  */
3320
3321       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3322         {
3323           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3324
3325           /* First try to split using the original register as a
3326              scratch register.  */
3327           parallel = gen_rtx_PARALLEL (VOIDmode,
3328                                        gen_rtvec (2, newpat,
3329                                                   gen_rtx_CLOBBER (VOIDmode,
3330                                                                    i2dest)));
3331           m_split = combine_split_insns (parallel, i3);
3332
3333           /* If that didn't work, try changing the mode of I2DEST if
3334              we can.  */
3335           if (m_split == 0
3336               && new_mode != GET_MODE (i2dest)
3337               && new_mode != VOIDmode
3338               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3339             {
3340               enum machine_mode old_mode = GET_MODE (i2dest);
3341               rtx ni2dest;
3342
3343               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3344                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3345               else
3346                 {
3347                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3348                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3349                 }
3350
3351               parallel = (gen_rtx_PARALLEL
3352                           (VOIDmode,
3353                            gen_rtvec (2, newpat,
3354                                       gen_rtx_CLOBBER (VOIDmode,
3355                                                        ni2dest))));
3356               m_split = combine_split_insns (parallel, i3);
3357
3358               if (m_split == 0
3359                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3360                 {
3361                   struct undo *buf;
3362
3363                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3364                   buf = undobuf.undos;
3365                   undobuf.undos = buf->next;
3366                   buf->next = undobuf.frees;
3367                   undobuf.frees = buf;
3368                 }
3369             }
3370
3371           i2scratch = m_split != 0;
3372         }
3373
3374       /* If recog_for_combine has discarded clobbers, try to use them
3375          again for the split.  */
3376       if (m_split == 0 && newpat_vec_with_clobbers)
3377         {
3378           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3379           m_split = combine_split_insns (parallel, i3);
3380         }
3381
3382       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3383         {
3384           m_split = PATTERN (m_split);
3385           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3386           if (insn_code_number >= 0)
3387             newpat = m_split;
3388         }
3389       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3390                && (next_nonnote_nondebug_insn (i2) == i3
3391                    || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3392         {
3393           rtx i2set, i3set;
3394           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3395           newi2pat = PATTERN (m_split);
3396
3397           i3set = single_set (NEXT_INSN (m_split));
3398           i2set = single_set (m_split);
3399
3400           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3401
3402           /* If I2 or I3 has multiple SETs, we won't know how to track
3403              register status, so don't use these insns.  If I2's destination
3404              is used between I2 and I3, we also can't use these insns.  */
3405
3406           if (i2_code_number >= 0 && i2set && i3set
3407               && (next_nonnote_nondebug_insn (i2) == i3
3408                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3409             insn_code_number = recog_for_combine (&newi3pat, i3,
3410                                                   &new_i3_notes);
3411           if (insn_code_number >= 0)
3412             newpat = newi3pat;
3413
3414           /* It is possible that both insns now set the destination of I3.
3415              If so, we must show an extra use of it.  */
3416
3417           if (insn_code_number >= 0)
3418             {
3419               rtx new_i3_dest = SET_DEST (i3set);
3420               rtx new_i2_dest = SET_DEST (i2set);
3421
3422               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3423                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3424                      || GET_CODE (new_i3_dest) == SUBREG)
3425                 new_i3_dest = XEXP (new_i3_dest, 0);
3426
3427               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3428                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3429                      || GET_CODE (new_i2_dest) == SUBREG)
3430                 new_i2_dest = XEXP (new_i2_dest, 0);
3431
3432               if (REG_P (new_i3_dest)
3433                   && REG_P (new_i2_dest)
3434                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3435                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3436             }
3437         }
3438
3439       /* If we can split it and use I2DEST, go ahead and see if that
3440          helps things be recognized.  Verify that none of the registers
3441          are set between I2 and I3.  */
3442       if (insn_code_number < 0
3443           && (split = find_split_point (&newpat, i3, false)) != 0
3444 #ifdef HAVE_cc0
3445           && REG_P (i2dest)
3446 #endif
3447           /* We need I2DEST in the proper mode.  If it is a hard register
3448              or the only use of a pseudo, we can change its mode.
3449              Make sure we don't change a hard register to have a mode that
3450              isn't valid for it, or change the number of registers.  */
3451           && (GET_MODE (*split) == GET_MODE (i2dest)
3452               || GET_MODE (*split) == VOIDmode
3453               || can_change_dest_mode (i2dest, added_sets_2,
3454                                        GET_MODE (*split)))
3455           && (next_nonnote_nondebug_insn (i2) == i3
3456               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3457           /* We can't overwrite I2DEST if its value is still used by
3458              NEWPAT.  */
3459           && ! reg_referenced_p (i2dest, newpat))
3460         {
3461           rtx newdest = i2dest;
3462           enum rtx_code split_code = GET_CODE (*split);
3463           enum machine_mode split_mode = GET_MODE (*split);
3464           bool subst_done = false;
3465           newi2pat = NULL_RTX;
3466
3467           i2scratch = true;
3468
3469           /* *SPLIT may be part of I2SRC, so make sure we have the
3470              original expression around for later debug processing.
3471              We should not need I2SRC any more in other cases.  */
3472           if (MAY_HAVE_DEBUG_INSNS)
3473             i2src = copy_rtx (i2src);
3474           else
3475             i2src = NULL;
3476
3477           /* Get NEWDEST as a register in the proper mode.  We have already
3478              validated that we can do this.  */
3479           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3480             {
3481               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3482                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3483               else
3484                 {
3485                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3486                   newdest = regno_reg_rtx[REGNO (i2dest)];
3487                 }
3488             }
3489
3490           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3491              an ASHIFT.  This can occur if it was inside a PLUS and hence
3492              appeared to be a memory address.  This is a kludge.  */
3493           if (split_code == MULT
3494               && CONST_INT_P (XEXP (*split, 1))
3495               && INTVAL (XEXP (*split, 1)) > 0
3496               && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3497             {
3498               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3499                                              XEXP (*split, 0), GEN_INT (i)));
3500               /* Update split_code because we may not have a multiply
3501                  anymore.  */
3502               split_code = GET_CODE (*split);
3503             }
3504
3505 #ifdef INSN_SCHEDULING
3506           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3507              be written as a ZERO_EXTEND.  */
3508           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3509             {
3510 #ifdef LOAD_EXTEND_OP
3511               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3512                  what it really is.  */
3513               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3514                   == SIGN_EXTEND)
3515                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3516                                                     SUBREG_REG (*split)));
3517               else
3518 #endif
3519                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3520                                                     SUBREG_REG (*split)));
3521             }
3522 #endif
3523
3524           /* Attempt to split binary operators using arithmetic identities.  */
3525           if (BINARY_P (SET_SRC (newpat))
3526               && split_mode == GET_MODE (SET_SRC (newpat))
3527               && ! side_effects_p (SET_SRC (newpat)))
3528             {
3529               rtx setsrc = SET_SRC (newpat);
3530               enum machine_mode mode = GET_MODE (setsrc);
3531               enum rtx_code code = GET_CODE (setsrc);
3532               rtx src_op0 = XEXP (setsrc, 0);
3533               rtx src_op1 = XEXP (setsrc, 1);
3534
3535               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3536               if (rtx_equal_p (src_op0, src_op1))
3537                 {
3538                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3539                   SUBST (XEXP (setsrc, 0), newdest);
3540                   SUBST (XEXP (setsrc, 1), newdest);
3541                   subst_done = true;
3542                 }
3543               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3544               else if ((code == PLUS || code == MULT)
3545                        && GET_CODE (src_op0) == code
3546                        && GET_CODE (XEXP (src_op0, 0)) == code
3547                        && (INTEGRAL_MODE_P (mode)
3548                            || (FLOAT_MODE_P (mode)
3549                                && flag_unsafe_math_optimizations)))
3550                 {
3551                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3552                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3553                   rtx r = XEXP (src_op0, 1);
3554                   rtx s = src_op1;
3555
3556                   /* Split both "((X op Y) op X) op Y" and
3557                      "((X op Y) op Y) op X" as "T op T" where T is
3558                      "X op Y".  */
3559                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3560                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3561                     {
3562                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3563                                               XEXP (src_op0, 0));
3564                       SUBST (XEXP (setsrc, 0), newdest);
3565                       SUBST (XEXP (setsrc, 1), newdest);
3566                       subst_done = true;
3567                     }
3568                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3569                      T is "X op Y".  */
3570                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3571                     {
3572                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3573                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3574                       SUBST (XEXP (setsrc, 0), newdest);
3575                       SUBST (XEXP (setsrc, 1), newdest);
3576                       subst_done = true;
3577                     }
3578                 }
3579             }
3580
3581           if (!subst_done)
3582             {
3583               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3584               SUBST (*split, newdest);
3585             }
3586
3587           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3588
3589           /* recog_for_combine might have added CLOBBERs to newi2pat.
3590              Make sure NEWPAT does not depend on the clobbered regs.  */
3591           if (GET_CODE (newi2pat) == PARALLEL)
3592             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3593               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3594                 {
3595                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3596                   if (reg_overlap_mentioned_p (reg, newpat))
3597                     {
3598                       undo_all ();
3599                       return 0;
3600                     }
3601                 }
3602
3603           /* If the split point was a MULT and we didn't have one before,
3604              don't use one now.  */
3605           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3606             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3607         }
3608     }
3609
3610   /* Check for a case where we loaded from memory in a narrow mode and
3611      then sign extended it, but we need both registers.  In that case,
3612      we have a PARALLEL with both loads from the same memory location.
3613      We can split this into a load from memory followed by a register-register
3614      copy.  This saves at least one insn, more if register allocation can
3615      eliminate the copy.
3616
3617      We cannot do this if the destination of the first assignment is a
3618      condition code register or cc0.  We eliminate this case by making sure
3619      the SET_DEST and SET_SRC have the same mode.
3620
3621      We cannot do this if the destination of the second assignment is
3622      a register that we have already assumed is zero-extended.  Similarly
3623      for a SUBREG of such a register.  */
3624
3625   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3626            && GET_CODE (newpat) == PARALLEL
3627            && XVECLEN (newpat, 0) == 2
3628            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3629            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3630            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3631                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3632            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3633            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3634                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3635            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3636                                    DF_INSN_LUID (i2))
3637            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3638            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3639            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3640                  (REG_P (temp)
3641                   && reg_stat[REGNO (temp)].nonzero_bits != 0
3642                   && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3643                   && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3644                   && (reg_stat[REGNO (temp)].nonzero_bits
3645                       != GET_MODE_MASK (word_mode))))
3646            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3647                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3648                      (REG_P (temp)
3649                       && reg_stat[REGNO (temp)].nonzero_bits != 0
3650                       && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3651                       && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3652                       && (reg_stat[REGNO (temp)].nonzero_bits
3653                           != GET_MODE_MASK (word_mode)))))
3654            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3655                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3656            && ! find_reg_note (i3, REG_UNUSED,
3657                                SET_DEST (XVECEXP (newpat, 0, 0))))
3658     {
3659       rtx ni2dest;
3660
3661       newi2pat = XVECEXP (newpat, 0, 0);
3662       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3663       newpat = XVECEXP (newpat, 0, 1);
3664       SUBST (SET_SRC (newpat),
3665              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3666       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3667
3668       if (i2_code_number >= 0)
3669         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3670
3671       if (insn_code_number >= 0)
3672         swap_i2i3 = 1;
3673     }
3674
3675   /* Similarly, check for a case where we have a PARALLEL of two independent
3676      SETs but we started with three insns.  In this case, we can do the sets
3677      as two separate insns.  This case occurs when some SET allows two
3678      other insns to combine, but the destination of that SET is still live.  */
3679
3680   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3681            && GET_CODE (newpat) == PARALLEL
3682            && XVECLEN (newpat, 0) == 2
3683            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3684            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3685            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3686            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3687            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3688            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3689            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3690                                   XVECEXP (newpat, 0, 0))
3691            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3692                                   XVECEXP (newpat, 0, 1))
3693            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3694                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3695     {
3696       /* Normally, it doesn't matter which of the two is done first,
3697          but the one that references cc0 can't be the second, and
3698          one which uses any regs/memory set in between i2 and i3 can't
3699          be first.  */
3700       if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3701                               DF_INSN_LUID (i2))
3702 #ifdef HAVE_cc0
3703           && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3704 #endif
3705          )
3706         {
3707           newi2pat = XVECEXP (newpat, 0, 1);
3708           newpat = XVECEXP (newpat, 0, 0);
3709         }
3710       else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3711                                    DF_INSN_LUID (i2))
3712 #ifdef HAVE_cc0
3713                && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3714 #endif
3715               )
3716         {
3717           newi2pat = XVECEXP (newpat, 0, 0);
3718           newpat = XVECEXP (newpat, 0, 1);
3719         }
3720       else
3721         {
3722           undo_all ();
3723           return 0;
3724         }
3725
3726       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3727
3728       if (i2_code_number >= 0)
3729         {
3730           /* recog_for_combine might have added CLOBBERs to newi2pat.
3731              Make sure NEWPAT does not depend on the clobbered regs.  */
3732           if (GET_CODE (newi2pat) == PARALLEL)
3733             {
3734               for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3735                 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3736                   {
3737                     rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3738                     if (reg_overlap_mentioned_p (reg, newpat))
3739                       {
3740                         undo_all ();
3741                         return 0;
3742                       }
3743                   }
3744             }
3745
3746           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3747         }
3748     }
3749
3750   /* If it still isn't recognized, fail and change things back the way they
3751      were.  */
3752   if ((insn_code_number < 0
3753        /* Is the result a reasonable ASM_OPERANDS?  */
3754        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3755     {
3756       undo_all ();
3757       return 0;
3758     }
3759
3760   /* If we had to change another insn, make sure it is valid also.  */
3761   if (undobuf.other_insn)
3762     {
3763       CLEAR_HARD_REG_SET (newpat_used_regs);
3764
3765       other_pat = PATTERN (undobuf.other_insn);
3766       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3767                                              &new_other_notes);
3768
3769       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3770         {
3771           undo_all ();
3772           return 0;
3773         }
3774     }
3775
3776 #ifdef HAVE_cc0
3777   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3778      they are adjacent to each other or not.  */
3779   {
3780     rtx p = prev_nonnote_insn (i3);
3781     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3782         && sets_cc0_p (newi2pat))
3783       {
3784         undo_all ();
3785         return 0;
3786       }
3787   }
3788 #endif
3789
3790   /* Only allow this combination if insn_rtx_costs reports that the
3791      replacement instructions are cheaper than the originals.  */
3792   if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3793     {
3794       undo_all ();
3795       return 0;
3796     }
3797
3798   if (MAY_HAVE_DEBUG_INSNS)
3799     {
3800       struct undo *undo;
3801
3802       for (undo = undobuf.undos; undo; undo = undo->next)
3803         if (undo->kind == UNDO_MODE)
3804           {
3805             rtx reg = *undo->where.r;
3806             enum machine_mode new_mode = GET_MODE (reg);
3807             enum machine_mode old_mode = undo->old_contents.m;
3808
3809             /* Temporarily revert mode back.  */
3810             adjust_reg_mode (reg, old_mode);
3811
3812             if (reg == i2dest && i2scratch)
3813               {
3814                 /* If we used i2dest as a scratch register with a
3815                    different mode, substitute it for the original
3816                    i2src while its original mode is temporarily
3817                    restored, and then clear i2scratch so that we don't
3818                    do it again later.  */
3819                 propagate_for_debug (i2, last_combined_insn, reg, i2src,
3820                                      this_basic_block);
3821                 i2scratch = false;
3822                 /* Put back the new mode.  */
3823                 adjust_reg_mode (reg, new_mode);
3824               }
3825             else
3826               {
3827                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3828                 rtx first, last;
3829
3830                 if (reg == i2dest)
3831                   {
3832                     first = i2;
3833                     last = last_combined_insn;
3834                   }
3835                 else
3836                   {
3837                     first = i3;
3838                     last = undobuf.other_insn;
3839                     gcc_assert (last);
3840                     if (DF_INSN_LUID (last)
3841                         < DF_INSN_LUID (last_combined_insn))
3842                       last = last_combined_insn;
3843                   }
3844
3845                 /* We're dealing with a reg that changed mode but not
3846                    meaning, so we want to turn it into a subreg for
3847                    the new mode.  However, because of REG sharing and
3848                    because its mode had already changed, we have to do
3849                    it in two steps.  First, replace any debug uses of
3850                    reg, with its original mode temporarily restored,
3851                    with this copy we have created; then, replace the
3852                    copy with the SUBREG of the original shared reg,
3853                    once again changed to the new mode.  */
3854                 propagate_for_debug (first, last, reg, tempreg,
3855                                      this_basic_block);
3856                 adjust_reg_mode (reg, new_mode);
3857                 propagate_for_debug (first, last, tempreg,
3858                                      lowpart_subreg (old_mode, reg, new_mode),
3859                                      this_basic_block);
3860               }
3861           }
3862     }
3863
3864   /* If we will be able to accept this, we have made a
3865      change to the destination of I3.  This requires us to
3866      do a few adjustments.  */
3867
3868   if (changed_i3_dest)
3869     {
3870       PATTERN (i3) = newpat;
3871       adjust_for_new_dest (i3);
3872     }
3873
3874   /* We now know that we can do this combination.  Merge the insns and
3875      update the status of registers and LOG_LINKS.  */
3876
3877   if (undobuf.other_insn)
3878     {
3879       rtx note, next;
3880
3881       PATTERN (undobuf.other_insn) = other_pat;
3882
3883       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3884          are still valid.  Then add any non-duplicate notes added by
3885          recog_for_combine.  */
3886       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3887         {
3888           next = XEXP (note, 1);
3889
3890           if (REG_NOTE_KIND (note) == REG_UNUSED
3891               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3892             remove_note (undobuf.other_insn, note);
3893         }
3894
3895       distribute_notes (new_other_notes, undobuf.other_insn,
3896                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3897                         NULL_RTX);
3898     }
3899
3900   if (swap_i2i3)
3901     {
3902       rtx insn;
3903       struct insn_link *link;
3904       rtx ni2dest;
3905
3906       /* I3 now uses what used to be its destination and which is now
3907          I2's destination.  This requires us to do a few adjustments.  */
3908       PATTERN (i3) = newpat;
3909       adjust_for_new_dest (i3);
3910
3911       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3912          so we still will.
3913
3914          However, some later insn might be using I2's dest and have
3915          a LOG_LINK pointing at I3.  We must remove this link.
3916          The simplest way to remove the link is to point it at I1,
3917          which we know will be a NOTE.  */
3918
3919       /* newi2pat is usually a SET here; however, recog_for_combine might
3920          have added some clobbers.  */
3921       if (GET_CODE (newi2pat) == PARALLEL)
3922         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3923       else
3924         ni2dest = SET_DEST (newi2pat);
3925
3926       for (insn = NEXT_INSN (i3);
3927            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3928                     || insn != BB_HEAD (this_basic_block->next_bb));
3929            insn = NEXT_INSN (insn))
3930         {
3931           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3932             {
3933               FOR_EACH_LOG_LINK (link, insn)
3934                 if (link->insn == i3)
3935                   link->insn = i1;
3936
3937               break;
3938             }
3939         }
3940     }
3941
3942   {
3943     rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3944     struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
3945     rtx midnotes = 0;
3946     int from_luid;
3947     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3948        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3949        same as i3dest, in which case newi2pat may be setting i1dest.  */
3950     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3951                    || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3952                    || !i2dest_killed
3953                    ? 0 : i2dest);
3954     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3955                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3956                    || !i1dest_killed
3957                    ? 0 : i1dest);
3958     rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
3959                    || (newi2pat && reg_set_p (i0dest, newi2pat))
3960                    || !i0dest_killed
3961                    ? 0 : i0dest);
3962
3963     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3964        clear them.  */
3965     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3966     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3967     if (i1)
3968       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3969     if (i0)
3970       i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
3971
3972     /* Ensure that we do not have something that should not be shared but
3973        occurs multiple times in the new insns.  Check this by first
3974        resetting all the `used' flags and then copying anything is shared.  */
3975
3976     reset_used_flags (i3notes);
3977     reset_used_flags (i2notes);
3978     reset_used_flags (i1notes);
3979     reset_used_flags (i0notes);
3980     reset_used_flags (newpat);
3981     reset_used_flags (newi2pat);
3982     if (undobuf.other_insn)
3983       reset_used_flags (PATTERN (undobuf.other_insn));
3984
3985     i3notes = copy_rtx_if_shared (i3notes);
3986     i2notes = copy_rtx_if_shared (i2notes);
3987     i1notes = copy_rtx_if_shared (i1notes);
3988     i0notes = copy_rtx_if_shared (i0notes);
3989     newpat = copy_rtx_if_shared (newpat);
3990     newi2pat = copy_rtx_if_shared (newi2pat);
3991     if (undobuf.other_insn)
3992       reset_used_flags (PATTERN (undobuf.other_insn));
3993
3994     INSN_CODE (i3) = insn_code_number;
3995     PATTERN (i3) = newpat;
3996
3997     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3998       {
3999         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4000
4001         reset_used_flags (call_usage);
4002         call_usage = copy_rtx (call_usage);
4003
4004         if (substed_i2)
4005           {
4006             /* I2SRC must still be meaningful at this point.  Some splitting
4007                operations can invalidate I2SRC, but those operations do not
4008                apply to calls.  */
4009             gcc_assert (i2src);
4010             replace_rtx (call_usage, i2dest, i2src);
4011           }
4012
4013         if (substed_i1)
4014           replace_rtx (call_usage, i1dest, i1src);
4015         if (substed_i0)
4016           replace_rtx (call_usage, i0dest, i0src);
4017
4018         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4019       }
4020
4021     if (undobuf.other_insn)
4022       INSN_CODE (undobuf.other_insn) = other_code_number;
4023
4024     /* We had one special case above where I2 had more than one set and
4025        we replaced a destination of one of those sets with the destination
4026        of I3.  In that case, we have to update LOG_LINKS of insns later
4027        in this basic block.  Note that this (expensive) case is rare.
4028
4029        Also, in this case, we must pretend that all REG_NOTEs for I2
4030        actually came from I3, so that REG_UNUSED notes from I2 will be
4031        properly handled.  */
4032
4033     if (i3_subst_into_i2)
4034       {
4035         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4036           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4037                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4038               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4039               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4040               && ! find_reg_note (i2, REG_UNUSED,
4041                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4042             for (temp = NEXT_INSN (i2);
4043                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4044                           || BB_HEAD (this_basic_block) != temp);
4045                  temp = NEXT_INSN (temp))
4046               if (temp != i3 && INSN_P (temp))
4047                 FOR_EACH_LOG_LINK (link, temp)
4048                   if (link->insn == i2)
4049                     link->insn = i3;
4050
4051         if (i3notes)
4052           {
4053             rtx link = i3notes;
4054             while (XEXP (link, 1))
4055               link = XEXP (link, 1);
4056             XEXP (link, 1) = i2notes;
4057           }
4058         else
4059           i3notes = i2notes;
4060         i2notes = 0;
4061       }
4062
4063     LOG_LINKS (i3) = NULL;
4064     REG_NOTES (i3) = 0;
4065     LOG_LINKS (i2) = NULL;
4066     REG_NOTES (i2) = 0;
4067
4068     if (newi2pat)
4069       {
4070         if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4071           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4072                                this_basic_block);
4073         INSN_CODE (i2) = i2_code_number;
4074         PATTERN (i2) = newi2pat;
4075       }
4076     else
4077       {
4078         if (MAY_HAVE_DEBUG_INSNS && i2src)
4079           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4080                                this_basic_block);
4081         SET_INSN_DELETED (i2);
4082       }
4083
4084     if (i1)
4085       {
4086         LOG_LINKS (i1) = NULL;
4087         REG_NOTES (i1) = 0;
4088         if (MAY_HAVE_DEBUG_INSNS)
4089           propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4090                                this_basic_block);
4091         SET_INSN_DELETED (i1);
4092       }
4093
4094     if (i0)
4095       {
4096         LOG_LINKS (i0) = NULL;
4097         REG_NOTES (i0) = 0;
4098         if (MAY_HAVE_DEBUG_INSNS)
4099           propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4100                                this_basic_block);
4101         SET_INSN_DELETED (i0);
4102       }
4103
4104     /* Get death notes for everything that is now used in either I3 or
4105        I2 and used to die in a previous insn.  If we built two new
4106        patterns, move from I1 to I2 then I2 to I3 so that we get the
4107        proper movement on registers that I2 modifies.  */
4108
4109     if (i0)
4110       from_luid = DF_INSN_LUID (i0);
4111     else if (i1)
4112       from_luid = DF_INSN_LUID (i1);
4113     else
4114       from_luid = DF_INSN_LUID (i2);
4115     if (newi2pat)
4116       move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4117     move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4118
4119     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
4120     if (i3notes)
4121       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4122                         elim_i2, elim_i1, elim_i0);
4123     if (i2notes)
4124       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4125                         elim_i2, elim_i1, elim_i0);
4126     if (i1notes)
4127       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4128                         elim_i2, elim_i1, elim_i0);
4129     if (i0notes)
4130       distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4131                         elim_i2, elim_i1, elim_i0);
4132     if (midnotes)
4133       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4134                         elim_i2, elim_i1, elim_i0);
4135
4136     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
4137        know these are REG_UNUSED and want them to go to the desired insn,
4138        so we always pass it as i3.  */
4139
4140     if (newi2pat && new_i2_notes)
4141       distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4142                         NULL_RTX);
4143
4144     if (new_i3_notes)
4145       distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4146                         NULL_RTX);
4147
4148     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
4149        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
4150        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
4151        in that case, it might delete I2.  Similarly for I2 and I1.
4152        Show an additional death due to the REG_DEAD note we make here.  If
4153        we discard it in distribute_notes, we will decrement it again.  */
4154
4155     if (i3dest_killed)
4156       {
4157         rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4158         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4159           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, elim_i2,
4160                             elim_i1, elim_i0);
4161         else
4162           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4163                             elim_i2, elim_i1, elim_i0);
4164       }
4165
4166     if (i2dest_in_i2src)
4167       {
4168         rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4169         if (newi2pat && reg_set_p (i2dest, newi2pat))
4170           distribute_notes (new_note,  NULL_RTX, i2, NULL_RTX, NULL_RTX,
4171                             NULL_RTX, NULL_RTX);
4172         else
4173           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4174                             NULL_RTX, NULL_RTX, NULL_RTX);
4175       }
4176
4177     if (i1dest_in_i1src)
4178       {
4179         rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4180         if (newi2pat && reg_set_p (i1dest, newi2pat))
4181           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4182                             NULL_RTX, NULL_RTX);
4183         else
4184           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4185                             NULL_RTX, NULL_RTX, NULL_RTX);
4186       }
4187
4188     if (i0dest_in_i0src)
4189       {
4190         rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4191         if (newi2pat && reg_set_p (i0dest, newi2pat))
4192           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4193                             NULL_RTX, NULL_RTX);
4194         else
4195           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4196                             NULL_RTX, NULL_RTX, NULL_RTX);
4197       }
4198
4199     distribute_links (i3links);
4200     distribute_links (i2links);
4201     distribute_links (i1links);
4202     distribute_links (i0links);
4203
4204     if (REG_P (i2dest))
4205       {
4206         struct insn_link *link;
4207         rtx i2_insn = 0, i2_val = 0, set;
4208
4209         /* The insn that used to set this register doesn't exist, and
4210            this life of the register may not exist either.  See if one of
4211            I3's links points to an insn that sets I2DEST.  If it does,
4212            that is now the last known value for I2DEST. If we don't update
4213            this and I2 set the register to a value that depended on its old
4214            contents, we will get confused.  If this insn is used, thing
4215            will be set correctly in combine_instructions.  */
4216         FOR_EACH_LOG_LINK (link, i3)
4217           if ((set = single_set (link->insn)) != 0
4218               && rtx_equal_p (i2dest, SET_DEST (set)))
4219             i2_insn = link->insn, i2_val = SET_SRC (set);
4220
4221         record_value_for_reg (i2dest, i2_insn, i2_val);
4222
4223         /* If the reg formerly set in I2 died only once and that was in I3,
4224            zero its use count so it won't make `reload' do any work.  */
4225         if (! added_sets_2
4226             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4227             && ! i2dest_in_i2src)
4228           INC_REG_N_SETS (REGNO (i2dest), -1);
4229       }
4230
4231     if (i1 && REG_P (i1dest))
4232       {
4233         struct insn_link *link;
4234         rtx i1_insn = 0, i1_val = 0, set;
4235
4236         FOR_EACH_LOG_LINK (link, i3)
4237           if ((set = single_set (link->insn)) != 0
4238               && rtx_equal_p (i1dest, SET_DEST (set)))
4239             i1_insn = link->insn, i1_val = SET_SRC (set);
4240
4241         record_value_for_reg (i1dest, i1_insn, i1_val);
4242
4243         if (! added_sets_1 && ! i1dest_in_i1src)
4244           INC_REG_N_SETS (REGNO (i1dest), -1);
4245       }
4246
4247     if (i0 && REG_P (i0dest))
4248       {
4249         struct insn_link *link;
4250         rtx i0_insn = 0, i0_val = 0, set;
4251
4252         FOR_EACH_LOG_LINK (link, i3)
4253           if ((set = single_set (link->insn)) != 0
4254               && rtx_equal_p (i0dest, SET_DEST (set)))
4255             i0_insn = link->insn, i0_val = SET_SRC (set);
4256
4257         record_value_for_reg (i0dest, i0_insn, i0_val);
4258
4259         if (! added_sets_0 && ! i0dest_in_i0src)
4260           INC_REG_N_SETS (REGNO (i0dest), -1);
4261       }
4262
4263     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4264        been made to this insn.  The order of
4265        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
4266        can affect nonzero_bits of newpat */
4267     if (newi2pat)
4268       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4269     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4270   }
4271
4272   if (undobuf.other_insn != NULL_RTX)
4273     {
4274       if (dump_file)
4275         {
4276           fprintf (dump_file, "modifying other_insn ");
4277           dump_insn_slim (dump_file, undobuf.other_insn);
4278         }
4279       df_insn_rescan (undobuf.other_insn);
4280     }
4281
4282   if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4283     {
4284       if (dump_file)
4285         {
4286           fprintf (dump_file, "modifying insn i1 ");
4287           dump_insn_slim (dump_file, i0);
4288         }
4289       df_insn_rescan (i0);
4290     }
4291
4292   if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4293     {
4294       if (dump_file)
4295         {
4296           fprintf (dump_file, "modifying insn i1 ");
4297           dump_insn_slim (dump_file, i1);
4298         }
4299       df_insn_rescan (i1);
4300     }
4301
4302   if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4303     {
4304       if (dump_file)
4305         {
4306           fprintf (dump_file, "modifying insn i2 ");
4307           dump_insn_slim (dump_file, i2);
4308         }
4309       df_insn_rescan (i2);
4310     }
4311
4312   if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4313     {
4314       if (dump_file)
4315         {
4316           fprintf (dump_file, "modifying insn i3 ");
4317           dump_insn_slim (dump_file, i3);
4318         }
4319       df_insn_rescan (i3);
4320     }
4321
4322   /* Set new_direct_jump_p if a new return or simple jump instruction
4323      has been created.  Adjust the CFG accordingly.  */
4324
4325   if (returnjump_p (i3) || any_uncondjump_p (i3))
4326     {
4327       *new_direct_jump_p = 1;
4328       mark_jump_label (PATTERN (i3), i3, 0);
4329       update_cfg_for_uncondjump (i3);
4330     }
4331
4332   if (undobuf.other_insn != NULL_RTX
4333       && (returnjump_p (undobuf.other_insn)
4334           || any_uncondjump_p (undobuf.other_insn)))
4335     {
4336       *new_direct_jump_p = 1;
4337       update_cfg_for_uncondjump (undobuf.other_insn);
4338     }
4339
4340   /* A noop might also need cleaning up of CFG, if it comes from the
4341      simplification of a jump.  */
4342   if (JUMP_P (i3)
4343       && GET_CODE (newpat) == SET
4344       && SET_SRC (newpat) == pc_rtx
4345       && SET_DEST (newpat) == pc_rtx)
4346     {
4347       *new_direct_jump_p = 1;
4348       update_cfg_for_uncondjump (i3);
4349     }
4350
4351   if (undobuf.other_insn != NULL_RTX
4352       && JUMP_P (undobuf.other_insn)
4353       && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4354       && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4355       && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4356     {
4357       *new_direct_jump_p = 1;
4358       update_cfg_for_uncondjump (undobuf.other_insn);
4359     }
4360
4361   combine_successes++;
4362   undo_commit ();
4363
4364   if (added_links_insn
4365       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4366       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4367     return added_links_insn;
4368   else
4369     return newi2pat ? i2 : i3;
4370 }
4371 \f
4372 /* Undo all the modifications recorded in undobuf.  */
4373
4374 static void
4375 undo_all (void)
4376 {
4377   struct undo *undo, *next;
4378
4379   for (undo = undobuf.undos; undo; undo = next)
4380     {
4381       next = undo->next;
4382       switch (undo->kind)
4383         {
4384         case UNDO_RTX:
4385           *undo->where.r = undo->old_contents.r;
4386           break;
4387         case UNDO_INT:
4388           *undo->where.i = undo->old_contents.i;
4389           break;
4390         case UNDO_MODE:
4391           adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4392           break;
4393         case UNDO_LINKS:
4394           *undo->where.l = undo->old_contents.l;
4395           break;
4396         default:
4397           gcc_unreachable ();
4398         }
4399
4400       undo->next = undobuf.frees;
4401       undobuf.frees = undo;
4402     }
4403
4404   undobuf.undos = 0;
4405 }
4406
4407 /* We've committed to accepting the changes we made.  Move all
4408    of the undos to the free list.  */
4409
4410 static void
4411 undo_commit (void)
4412 {
4413   struct undo *undo, *next;
4414
4415   for (undo = undobuf.undos; undo; undo = next)
4416     {
4417       next = undo->next;
4418       undo->next = undobuf.frees;
4419       undobuf.frees = undo;
4420     }
4421   undobuf.undos = 0;
4422 }
4423 \f
4424 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4425    where we have an arithmetic expression and return that point.  LOC will
4426    be inside INSN.
4427
4428    try_combine will call this function to see if an insn can be split into
4429    two insns.  */
4430
4431 static rtx *
4432 find_split_point (rtx *loc, rtx insn, bool set_src)
4433 {
4434   rtx x = *loc;
4435   enum rtx_code code = GET_CODE (x);
4436   rtx *split;
4437   unsigned HOST_WIDE_INT len = 0;
4438   HOST_WIDE_INT pos = 0;
4439   int unsignedp = 0;
4440   rtx inner = NULL_RTX;
4441
4442   /* First special-case some codes.  */
4443   switch (code)
4444     {
4445     case SUBREG:
4446 #ifdef INSN_SCHEDULING
4447       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4448          point.  */
4449       if (MEM_P (SUBREG_REG (x)))
4450         return loc;
4451 #endif
4452       return find_split_point (&SUBREG_REG (x), insn, false);
4453
4454     case MEM:
4455 #ifdef HAVE_lo_sum
4456       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4457          using LO_SUM and HIGH.  */
4458       if (GET_CODE (XEXP (x, 0)) == CONST
4459           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4460         {
4461           enum machine_mode address_mode = get_address_mode (x);
4462
4463           SUBST (XEXP (x, 0),
4464                  gen_rtx_LO_SUM (address_mode,
4465                                  gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4466                                  XEXP (x, 0)));
4467           return &XEXP (XEXP (x, 0), 0);
4468         }
4469 #endif
4470
4471       /* If we have a PLUS whose second operand is a constant and the
4472          address is not valid, perhaps will can split it up using
4473          the machine-specific way to split large constants.  We use
4474          the first pseudo-reg (one of the virtual regs) as a placeholder;
4475          it will not remain in the result.  */
4476       if (GET_CODE (XEXP (x, 0)) == PLUS
4477           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4478           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4479                                             MEM_ADDR_SPACE (x)))
4480         {
4481           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4482           rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4483                                                       XEXP (x, 0)),
4484                                          subst_insn);
4485
4486           /* This should have produced two insns, each of which sets our
4487              placeholder.  If the source of the second is a valid address,
4488              we can make put both sources together and make a split point
4489              in the middle.  */
4490
4491           if (seq
4492               && NEXT_INSN (seq) != NULL_RTX
4493               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4494               && NONJUMP_INSN_P (seq)
4495               && GET_CODE (PATTERN (seq)) == SET
4496               && SET_DEST (PATTERN (seq)) == reg
4497               && ! reg_mentioned_p (reg,
4498                                     SET_SRC (PATTERN (seq)))
4499               && NONJUMP_INSN_P (NEXT_INSN (seq))
4500               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4501               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4502               && memory_address_addr_space_p
4503                    (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4504                     MEM_ADDR_SPACE (x)))
4505             {
4506               rtx src1 = SET_SRC (PATTERN (seq));
4507               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4508
4509               /* Replace the placeholder in SRC2 with SRC1.  If we can
4510                  find where in SRC2 it was placed, that can become our
4511                  split point and we can replace this address with SRC2.
4512                  Just try two obvious places.  */
4513
4514               src2 = replace_rtx (src2, reg, src1);
4515               split = 0;
4516               if (XEXP (src2, 0) == src1)
4517                 split = &XEXP (src2, 0);
4518               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4519                        && XEXP (XEXP (src2, 0), 0) == src1)
4520                 split = &XEXP (XEXP (src2, 0), 0);
4521
4522               if (split)
4523                 {
4524                   SUBST (XEXP (x, 0), src2);
4525                   return split;
4526                 }
4527             }
4528
4529           /* If that didn't work, perhaps the first operand is complex and
4530              needs to be computed separately, so make a split point there.
4531              This will occur on machines that just support REG + CONST
4532              and have a constant moved through some previous computation.  */
4533
4534           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4535                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4536                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4537             return &XEXP (XEXP (x, 0), 0);
4538         }
4539
4540       /* If we have a PLUS whose first operand is complex, try computing it
4541          separately by making a split there.  */
4542       if (GET_CODE (XEXP (x, 0)) == PLUS
4543           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4544                                             MEM_ADDR_SPACE (x))
4545           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4546           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4547                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4548         return &XEXP (XEXP (x, 0), 0);
4549       break;
4550
4551     case SET:
4552 #ifdef HAVE_cc0
4553       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4554          ZERO_EXTRACT, the most likely reason why this doesn't match is that
4555          we need to put the operand into a register.  So split at that
4556          point.  */
4557
4558       if (SET_DEST (x) == cc0_rtx
4559           && GET_CODE (SET_SRC (x)) != COMPARE
4560           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4561           && !OBJECT_P (SET_SRC (x))
4562           && ! (GET_CODE (SET_SRC (x)) == SUBREG
4563                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4564         return &SET_SRC (x);
4565 #endif
4566
4567       /* See if we can split SET_SRC as it stands.  */
4568       split = find_split_point (&SET_SRC (x), insn, true);
4569       if (split && split != &SET_SRC (x))
4570         return split;
4571
4572       /* See if we can split SET_DEST as it stands.  */
4573       split = find_split_point (&SET_DEST (x), insn, false);
4574       if (split && split != &SET_DEST (x))
4575         return split;
4576
4577       /* See if this is a bitfield assignment with everything constant.  If
4578          so, this is an IOR of an AND, so split it into that.  */
4579       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4580           && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4581           && CONST_INT_P (XEXP (SET_DEST (x), 1))
4582           && CONST_INT_P (XEXP (SET_DEST (x), 2))
4583           && CONST_INT_P (SET_SRC (x))
4584           && ((INTVAL (XEXP (SET_DEST (x), 1))
4585                + INTVAL (XEXP (SET_DEST (x), 2)))
4586               <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4587           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4588         {
4589           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4590           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4591           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4592           rtx dest = XEXP (SET_DEST (x), 0);
4593           enum machine_mode mode = GET_MODE (dest);
4594           unsigned HOST_WIDE_INT mask
4595             = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4596           rtx or_mask;
4597
4598           if (BITS_BIG_ENDIAN)
4599             pos = GET_MODE_PRECISION (mode) - len - pos;
4600
4601           or_mask = gen_int_mode (src << pos, mode);
4602           if (src == mask)
4603             SUBST (SET_SRC (x),
4604                    simplify_gen_binary (IOR, mode, dest, or_mask));
4605           else
4606             {
4607               rtx negmask = gen_int_mode (~(mask << pos), mode);
4608               SUBST (SET_SRC (x),
4609                      simplify_gen_binary (IOR, mode,
4610                                           simplify_gen_binary (AND, mode,
4611                                                                dest, negmask),
4612                                           or_mask));
4613             }
4614
4615           SUBST (SET_DEST (x), dest);
4616
4617           split = find_split_point (&SET_SRC (x), insn, true);
4618           if (split && split != &SET_SRC (x))
4619             return split;
4620         }
4621
4622       /* Otherwise, see if this is an operation that we can split into two.
4623          If so, try to split that.  */
4624       code = GET_CODE (SET_SRC (x));
4625
4626       switch (code)
4627         {
4628         case AND:
4629           /* If we are AND'ing with a large constant that is only a single
4630              bit and the result is only being used in a context where we
4631              need to know if it is zero or nonzero, replace it with a bit
4632              extraction.  This will avoid the large constant, which might
4633              have taken more than one insn to make.  If the constant were
4634              not a valid argument to the AND but took only one insn to make,
4635              this is no worse, but if it took more than one insn, it will
4636              be better.  */
4637
4638           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4639               && REG_P (XEXP (SET_SRC (x), 0))
4640               && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4641               && REG_P (SET_DEST (x))
4642               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4643               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4644               && XEXP (*split, 0) == SET_DEST (x)
4645               && XEXP (*split, 1) == const0_rtx)
4646             {
4647               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4648                                                 XEXP (SET_SRC (x), 0),
4649                                                 pos, NULL_RTX, 1, 1, 0, 0);
4650               if (extraction != 0)
4651                 {
4652                   SUBST (SET_SRC (x), extraction);
4653                   return find_split_point (loc, insn, false);
4654                 }
4655             }
4656           break;
4657
4658         case NE:
4659           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4660              is known to be on, this can be converted into a NEG of a shift.  */
4661           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4662               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4663               && 1 <= (pos = exact_log2
4664                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4665                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4666             {
4667               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4668
4669               SUBST (SET_SRC (x),
4670                      gen_rtx_NEG (mode,
4671                                   gen_rtx_LSHIFTRT (mode,
4672                                                     XEXP (SET_SRC (x), 0),
4673                                                     GEN_INT (pos))));
4674
4675               split = find_split_point (&SET_SRC (x), insn, true);
4676               if (split && split != &SET_SRC (x))
4677                 return split;
4678             }
4679           break;
4680
4681         case SIGN_EXTEND:
4682           inner = XEXP (SET_SRC (x), 0);
4683
4684           /* We can't optimize if either mode is a partial integer
4685              mode as we don't know how many bits are significant
4686              in those modes.  */
4687           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4688               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4689             break;
4690
4691           pos = 0;
4692           len = GET_MODE_PRECISION (GET_MODE (inner));
4693           unsignedp = 0;
4694           break;
4695
4696         case SIGN_EXTRACT:
4697         case ZERO_EXTRACT:
4698           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4699               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4700             {
4701               inner = XEXP (SET_SRC (x), 0);
4702               len = INTVAL (XEXP (SET_SRC (x), 1));
4703               pos = INTVAL (XEXP (SET_SRC (x), 2));
4704
4705               if (BITS_BIG_ENDIAN)
4706                 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4707               unsignedp = (code == ZERO_EXTRACT);
4708             }
4709           break;
4710
4711         default:
4712           break;
4713         }
4714
4715       if (len && pos >= 0
4716           && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4717         {
4718           enum machine_mode mode = GET_MODE (SET_SRC (x));
4719
4720           /* For unsigned, we have a choice of a shift followed by an
4721              AND or two shifts.  Use two shifts for field sizes where the
4722              constant might be too large.  We assume here that we can
4723              always at least get 8-bit constants in an AND insn, which is
4724              true for every current RISC.  */
4725
4726           if (unsignedp && len <= 8)
4727             {
4728               SUBST (SET_SRC (x),
4729                      gen_rtx_AND (mode,
4730                                   gen_rtx_LSHIFTRT
4731                                   (mode, gen_lowpart (mode, inner),
4732                                    GEN_INT (pos)),
4733                                   GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4734                                            - 1)));
4735
4736               split = find_split_point (&SET_SRC (x), insn, true);
4737               if (split && split != &SET_SRC (x))
4738                 return split;
4739             }
4740           else
4741             {
4742               SUBST (SET_SRC (x),
4743                      gen_rtx_fmt_ee
4744                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4745                       gen_rtx_ASHIFT (mode,
4746                                       gen_lowpart (mode, inner),
4747                                       GEN_INT (GET_MODE_PRECISION (mode)
4748                                                - len - pos)),
4749                       GEN_INT (GET_MODE_PRECISION (mode) - len)));
4750
4751               split = find_split_point (&SET_SRC (x), insn, true);
4752               if (split && split != &SET_SRC (x))
4753                 return split;
4754             }
4755         }
4756
4757       /* See if this is a simple operation with a constant as the second
4758          operand.  It might be that this constant is out of range and hence
4759          could be used as a split point.  */
4760       if (BINARY_P (SET_SRC (x))
4761           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4762           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4763               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4764                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4765         return &XEXP (SET_SRC (x), 1);
4766
4767       /* Finally, see if this is a simple operation with its first operand
4768          not in a register.  The operation might require this operand in a
4769          register, so return it as a split point.  We can always do this
4770          because if the first operand were another operation, we would have
4771          already found it as a split point.  */
4772       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4773           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4774         return &XEXP (SET_SRC (x), 0);
4775
4776       return 0;
4777
4778     case AND:
4779     case IOR:
4780       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4781          it is better to write this as (not (ior A B)) so we can split it.
4782          Similarly for IOR.  */
4783       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4784         {
4785           SUBST (*loc,
4786                  gen_rtx_NOT (GET_MODE (x),
4787                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4788                                               GET_MODE (x),
4789                                               XEXP (XEXP (x, 0), 0),
4790                                               XEXP (XEXP (x, 1), 0))));
4791           return find_split_point (loc, insn, set_src);
4792         }
4793
4794       /* Many RISC machines have a large set of logical insns.  If the
4795          second operand is a NOT, put it first so we will try to split the
4796          other operand first.  */
4797       if (GET_CODE (XEXP (x, 1)) == NOT)
4798         {
4799           rtx tem = XEXP (x, 0);
4800           SUBST (XEXP (x, 0), XEXP (x, 1));
4801           SUBST (XEXP (x, 1), tem);
4802         }
4803       break;
4804
4805     case PLUS:
4806     case MINUS:
4807       /* Canonicalization can produce (minus A (mult B C)), where C is a
4808          constant.  It may be better to try splitting (plus (mult B -C) A)
4809          instead if this isn't a multiply by a power of two.  */
4810       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4811           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4812           && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4813         {
4814           enum machine_mode mode = GET_MODE (x);
4815           unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4816           HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4817           SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4818                                                          XEXP (XEXP (x, 1), 0),
4819                                                          GEN_INT (other_int)),
4820                                      XEXP (x, 0)));
4821           return find_split_point (loc, insn, set_src);
4822         }
4823
4824       /* Split at a multiply-accumulate instruction.  However if this is
4825          the SET_SRC, we likely do not have such an instruction and it's
4826          worthless to try this split.  */
4827       if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4828         return loc;
4829
4830     default:
4831       break;
4832     }
4833
4834   /* Otherwise, select our actions depending on our rtx class.  */
4835   switch (GET_RTX_CLASS (code))
4836     {
4837     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4838     case RTX_TERNARY:
4839       split = find_split_point (&XEXP (x, 2), insn, false);
4840       if (split)
4841         return split;
4842       /* ... fall through ...  */
4843     case RTX_BIN_ARITH:
4844     case RTX_COMM_ARITH:
4845     case RTX_COMPARE:
4846     case RTX_COMM_COMPARE:
4847       split = find_split_point (&XEXP (x, 1), insn, false);
4848       if (split)
4849         return split;
4850       /* ... fall through ...  */
4851     case RTX_UNARY:
4852       /* Some machines have (and (shift ...) ...) insns.  If X is not
4853          an AND, but XEXP (X, 0) is, use it as our split point.  */
4854       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4855         return &XEXP (x, 0);
4856
4857       split = find_split_point (&XEXP (x, 0), insn, false);
4858       if (split)
4859         return split;
4860       return loc;
4861
4862     default:
4863       /* Otherwise, we don't have a split point.  */
4864       return 0;
4865     }
4866 }
4867 \f
4868 /* Throughout X, replace FROM with TO, and return the result.
4869    The result is TO if X is FROM;
4870    otherwise the result is X, but its contents may have been modified.
4871    If they were modified, a record was made in undobuf so that
4872    undo_all will (among other things) return X to its original state.
4873
4874    If the number of changes necessary is too much to record to undo,
4875    the excess changes are not made, so the result is invalid.
4876    The changes already made can still be undone.
4877    undobuf.num_undo is incremented for such changes, so by testing that
4878    the caller can tell whether the result is valid.
4879
4880    `n_occurrences' is incremented each time FROM is replaced.
4881
4882    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4883
4884    IN_COND is nonzero if we are at the top level of a condition.
4885
4886    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
4887    by copying if `n_occurrences' is nonzero.  */
4888
4889 static rtx
4890 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4891 {
4892   enum rtx_code code = GET_CODE (x);
4893   enum machine_mode op0_mode = VOIDmode;
4894   const char *fmt;
4895   int len, i;
4896   rtx new_rtx;
4897
4898 /* Two expressions are equal if they are identical copies of a shared
4899    RTX or if they are both registers with the same register number
4900    and mode.  */
4901
4902 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
4903   ((X) == (Y)                                           \
4904    || (REG_P (X) && REG_P (Y)   \
4905        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4906
4907   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4908     {
4909       n_occurrences++;
4910       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4911     }
4912
4913   /* If X and FROM are the same register but different modes, they
4914      will not have been seen as equal above.  However, the log links code
4915      will make a LOG_LINKS entry for that case.  If we do nothing, we
4916      will try to rerecognize our original insn and, when it succeeds,
4917      we will delete the feeding insn, which is incorrect.
4918
4919      So force this insn not to match in this (rare) case.  */
4920   if (! in_dest && code == REG && REG_P (from)
4921       && reg_overlap_mentioned_p (x, from))
4922     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4923
4924   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4925      of which may contain things that can be combined.  */
4926   if (code != MEM && code != LO_SUM && OBJECT_P (x))
4927     return x;
4928
4929   /* It is possible to have a subexpression appear twice in the insn.
4930      Suppose that FROM is a register that appears within TO.
4931      Then, after that subexpression has been scanned once by `subst',
4932      the second time it is scanned, TO may be found.  If we were
4933      to scan TO here, we would find FROM within it and create a
4934      self-referent rtl structure which is completely wrong.  */
4935   if (COMBINE_RTX_EQUAL_P (x, to))
4936     return to;
4937
4938   /* Parallel asm_operands need special attention because all of the
4939      inputs are shared across the arms.  Furthermore, unsharing the
4940      rtl results in recognition failures.  Failure to handle this case
4941      specially can result in circular rtl.
4942
4943      Solve this by doing a normal pass across the first entry of the
4944      parallel, and only processing the SET_DESTs of the subsequent
4945      entries.  Ug.  */
4946
4947   if (code == PARALLEL
4948       && GET_CODE (XVECEXP (x, 0, 0)) == SET
4949       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4950     {
4951       new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
4952
4953       /* If this substitution failed, this whole thing fails.  */
4954       if (GET_CODE (new_rtx) == CLOBBER
4955           && XEXP (new_rtx, 0) == const0_rtx)
4956         return new_rtx;
4957
4958       SUBST (XVECEXP (x, 0, 0), new_rtx);
4959
4960       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4961         {
4962           rtx dest = SET_DEST (XVECEXP (x, 0, i));
4963
4964           if (!REG_P (dest)
4965               && GET_CODE (dest) != CC0
4966               && GET_CODE (dest) != PC)
4967             {
4968               new_rtx = subst (dest, from, to, 0, 0, unique_copy);
4969
4970               /* If this substitution failed, this whole thing fails.  */
4971               if (GET_CODE (new_rtx) == CLOBBER
4972                   && XEXP (new_rtx, 0) == const0_rtx)
4973                 return new_rtx;
4974
4975               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4976             }
4977         }
4978     }
4979   else
4980     {
4981       len = GET_RTX_LENGTH (code);
4982       fmt = GET_RTX_FORMAT (code);
4983
4984       /* We don't need to process a SET_DEST that is a register, CC0,
4985          or PC, so set up to skip this common case.  All other cases
4986          where we want to suppress replacing something inside a
4987          SET_SRC are handled via the IN_DEST operand.  */
4988       if (code == SET
4989           && (REG_P (SET_DEST (x))
4990               || GET_CODE (SET_DEST (x)) == CC0
4991               || GET_CODE (SET_DEST (x)) == PC))
4992         fmt = "ie";
4993
4994       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4995          constant.  */
4996       if (fmt[0] == 'e')
4997         op0_mode = GET_MODE (XEXP (x, 0));
4998
4999       for (i = 0; i < len; i++)
5000         {
5001           if (fmt[i] == 'E')
5002             {
5003               int j;
5004               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5005                 {
5006                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5007                     {
5008                       new_rtx = (unique_copy && n_occurrences
5009                              ? copy_rtx (to) : to);
5010                       n_occurrences++;
5011                     }
5012                   else
5013                     {
5014                       new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5015                                        unique_copy);
5016
5017                       /* If this substitution failed, this whole thing
5018                          fails.  */
5019                       if (GET_CODE (new_rtx) == CLOBBER
5020                           && XEXP (new_rtx, 0) == const0_rtx)
5021                         return new_rtx;
5022                     }
5023
5024                   SUBST (XVECEXP (x, i, j), new_rtx);
5025                 }
5026             }
5027           else if (fmt[i] == 'e')
5028             {
5029               /* If this is a register being set, ignore it.  */
5030               new_rtx = XEXP (x, i);
5031               if (in_dest
5032                   && i == 0
5033                   && (((code == SUBREG || code == ZERO_EXTRACT)
5034                        && REG_P (new_rtx))
5035                       || code == STRICT_LOW_PART))
5036                 ;
5037
5038               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5039                 {
5040                   /* In general, don't install a subreg involving two
5041                      modes not tieable.  It can worsen register
5042                      allocation, and can even make invalid reload
5043                      insns, since the reg inside may need to be copied
5044                      from in the outside mode, and that may be invalid
5045                      if it is an fp reg copied in integer mode.
5046
5047                      We allow two exceptions to this: It is valid if
5048                      it is inside another SUBREG and the mode of that
5049                      SUBREG and the mode of the inside of TO is
5050                      tieable and it is valid if X is a SET that copies
5051                      FROM to CC0.  */
5052
5053                   if (GET_CODE (to) == SUBREG
5054                       && ! MODES_TIEABLE_P (GET_MODE (to),
5055                                             GET_MODE (SUBREG_REG (to)))
5056                       && ! (code == SUBREG
5057                             && MODES_TIEABLE_P (GET_MODE (x),
5058                                                 GET_MODE (SUBREG_REG (to))))
5059 #ifdef HAVE_cc0
5060                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5061 #endif
5062                       )
5063                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5064
5065 #ifdef CANNOT_CHANGE_MODE_CLASS
5066                   if (code == SUBREG
5067                       && REG_P (to)
5068                       && REGNO (to) < FIRST_PSEUDO_REGISTER
5069                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5070                                                    GET_MODE (to),
5071                                                    GET_MODE (x)))
5072                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5073 #endif
5074
5075                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5076                   n_occurrences++;
5077                 }
5078               else
5079                 /* If we are in a SET_DEST, suppress most cases unless we
5080                    have gone inside a MEM, in which case we want to
5081                    simplify the address.  We assume here that things that
5082                    are actually part of the destination have their inner
5083                    parts in the first expression.  This is true for SUBREG,
5084                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5085                    things aside from REG and MEM that should appear in a
5086                    SET_DEST.  */
5087                 new_rtx = subst (XEXP (x, i), from, to,
5088                              (((in_dest
5089                                 && (code == SUBREG || code == STRICT_LOW_PART
5090                                     || code == ZERO_EXTRACT))
5091                                || code == SET)
5092                               && i == 0),
5093                                  code == IF_THEN_ELSE && i == 0,
5094                                  unique_copy);
5095
5096               /* If we found that we will have to reject this combination,
5097                  indicate that by returning the CLOBBER ourselves, rather than
5098                  an expression containing it.  This will speed things up as
5099                  well as prevent accidents where two CLOBBERs are considered
5100                  to be equal, thus producing an incorrect simplification.  */
5101
5102               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5103                 return new_rtx;
5104
5105               if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5106                 {
5107                   enum machine_mode mode = GET_MODE (x);
5108
5109                   x = simplify_subreg (GET_MODE (x), new_rtx,
5110                                        GET_MODE (SUBREG_REG (x)),
5111                                        SUBREG_BYTE (x));
5112                   if (! x)
5113                     x = gen_rtx_CLOBBER (mode, const0_rtx);
5114                 }
5115               else if (CONST_INT_P (new_rtx)
5116                        && GET_CODE (x) == ZERO_EXTEND)
5117                 {
5118                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5119                                                 new_rtx, GET_MODE (XEXP (x, 0)));
5120                   gcc_assert (x);
5121                 }
5122               else
5123                 SUBST (XEXP (x, i), new_rtx);
5124             }
5125         }
5126     }
5127
5128   /* Check if we are loading something from the constant pool via float
5129      extension; in this case we would undo compress_float_constant
5130      optimization and degenerate constant load to an immediate value.  */
5131   if (GET_CODE (x) == FLOAT_EXTEND
5132       && MEM_P (XEXP (x, 0))
5133       && MEM_READONLY_P (XEXP (x, 0)))
5134     {
5135       rtx tmp = avoid_constant_pool_reference (x);
5136       if (x != tmp)
5137         return x;
5138     }
5139
5140   /* Try to simplify X.  If the simplification changed the code, it is likely
5141      that further simplification will help, so loop, but limit the number
5142      of repetitions that will be performed.  */
5143
5144   for (i = 0; i < 4; i++)
5145     {
5146       /* If X is sufficiently simple, don't bother trying to do anything
5147          with it.  */
5148       if (code != CONST_INT && code != REG && code != CLOBBER)
5149         x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5150
5151       if (GET_CODE (x) == code)
5152         break;
5153
5154       code = GET_CODE (x);
5155
5156       /* We no longer know the original mode of operand 0 since we
5157          have changed the form of X)  */
5158       op0_mode = VOIDmode;
5159     }
5160
5161   return x;
5162 }
5163 \f
5164 /* Simplify X, a piece of RTL.  We just operate on the expression at the
5165    outer level; call `subst' to simplify recursively.  Return the new
5166    expression.
5167
5168    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
5169    if we are inside a SET_DEST.  IN_COND is nonzero if we are at the top level
5170    of a condition.  */
5171
5172 static rtx
5173 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5174                       int in_cond)
5175 {
5176   enum rtx_code code = GET_CODE (x);
5177   enum machine_mode mode = GET_MODE (x);
5178   rtx temp;
5179   int i;
5180
5181   /* If this is a commutative operation, put a constant last and a complex
5182      expression first.  We don't need to do this for comparisons here.  */
5183   if (COMMUTATIVE_ARITH_P (x)
5184       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5185     {
5186       temp = XEXP (x, 0);
5187       SUBST (XEXP (x, 0), XEXP (x, 1));
5188       SUBST (XEXP (x, 1), temp);
5189     }
5190
5191   /* If this is a simple operation applied to an IF_THEN_ELSE, try
5192      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
5193      things.  Check for cases where both arms are testing the same
5194      condition.
5195
5196      Don't do anything if all operands are very simple.  */
5197
5198   if ((BINARY_P (x)
5199        && ((!OBJECT_P (XEXP (x, 0))
5200             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5201                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5202            || (!OBJECT_P (XEXP (x, 1))
5203                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5204                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5205       || (UNARY_P (x)
5206           && (!OBJECT_P (XEXP (x, 0))
5207                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5208                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5209     {
5210       rtx cond, true_rtx, false_rtx;
5211
5212       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5213       if (cond != 0
5214           /* If everything is a comparison, what we have is highly unlikely
5215              to be simpler, so don't use it.  */
5216           && ! (COMPARISON_P (x)
5217                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5218         {
5219           rtx cop1 = const0_rtx;
5220           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5221
5222           if (cond_code == NE && COMPARISON_P (cond))
5223             return x;
5224
5225           /* Simplify the alternative arms; this may collapse the true and
5226              false arms to store-flag values.  Be careful to use copy_rtx
5227              here since true_rtx or false_rtx might share RTL with x as a
5228              result of the if_then_else_cond call above.  */
5229           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5230           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5231
5232           /* If true_rtx and false_rtx are not general_operands, an if_then_else
5233              is unlikely to be simpler.  */
5234           if (general_operand (true_rtx, VOIDmode)
5235               && general_operand (false_rtx, VOIDmode))
5236             {
5237               enum rtx_code reversed;
5238
5239               /* Restarting if we generate a store-flag expression will cause
5240                  us to loop.  Just drop through in this case.  */
5241
5242               /* If the result values are STORE_FLAG_VALUE and zero, we can
5243                  just make the comparison operation.  */
5244               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5245                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5246                                              cond, cop1);
5247               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5248                        && ((reversed = reversed_comparison_code_parts
5249                                         (cond_code, cond, cop1, NULL))
5250                            != UNKNOWN))
5251                 x = simplify_gen_relational (reversed, mode, VOIDmode,
5252                                              cond, cop1);
5253
5254               /* Likewise, we can make the negate of a comparison operation
5255                  if the result values are - STORE_FLAG_VALUE and zero.  */
5256               else if (CONST_INT_P (true_rtx)
5257                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5258                        && false_rtx == const0_rtx)
5259                 x = simplify_gen_unary (NEG, mode,
5260                                         simplify_gen_relational (cond_code,
5261                                                                  mode, VOIDmode,
5262                                                                  cond, cop1),
5263                                         mode);
5264               else if (CONST_INT_P (false_rtx)
5265                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5266                        && true_rtx == const0_rtx
5267                        && ((reversed = reversed_comparison_code_parts
5268                                         (cond_code, cond, cop1, NULL))
5269                            != UNKNOWN))
5270                 x = simplify_gen_unary (NEG, mode,
5271                                         simplify_gen_relational (reversed,
5272                                                                  mode, VOIDmode,
5273                                                                  cond, cop1),
5274                                         mode);
5275               else
5276                 return gen_rtx_IF_THEN_ELSE (mode,
5277                                              simplify_gen_relational (cond_code,
5278                                                                       mode,
5279                                                                       VOIDmode,
5280                                                                       cond,
5281                                                                       cop1),
5282                                              true_rtx, false_rtx);
5283
5284               code = GET_CODE (x);
5285               op0_mode = VOIDmode;
5286             }
5287         }
5288     }
5289
5290   /* Try to fold this expression in case we have constants that weren't
5291      present before.  */
5292   temp = 0;
5293   switch (GET_RTX_CLASS (code))
5294     {
5295     case RTX_UNARY:
5296       if (op0_mode == VOIDmode)
5297         op0_mode = GET_MODE (XEXP (x, 0));
5298       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5299       break;
5300     case RTX_COMPARE:
5301     case RTX_COMM_COMPARE:
5302       {
5303         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5304         if (cmp_mode == VOIDmode)
5305           {
5306             cmp_mode = GET_MODE (XEXP (x, 1));
5307             if (cmp_mode == VOIDmode)
5308               cmp_mode = op0_mode;
5309           }
5310         temp = simplify_relational_operation (code, mode, cmp_mode,
5311                                               XEXP (x, 0), XEXP (x, 1));
5312       }
5313       break;
5314     case RTX_COMM_ARITH:
5315     case RTX_BIN_ARITH:
5316       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5317       break;
5318     case RTX_BITFIELD_OPS:
5319     case RTX_TERNARY:
5320       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5321                                          XEXP (x, 1), XEXP (x, 2));
5322       break;
5323     default:
5324       break;
5325     }
5326
5327   if (temp)
5328     {
5329       x = temp;
5330       code = GET_CODE (temp);
5331       op0_mode = VOIDmode;
5332       mode = GET_MODE (temp);
5333     }
5334
5335   /* First see if we can apply the inverse distributive law.  */
5336   if (code == PLUS || code == MINUS
5337       || code == AND || code == IOR || code == XOR)
5338     {
5339       x = apply_distributive_law (x);
5340       code = GET_CODE (x);
5341       op0_mode = VOIDmode;
5342     }
5343
5344   /* If CODE is an associative operation not otherwise handled, see if we
5345      can associate some operands.  This can win if they are constants or
5346      if they are logically related (i.e. (a & b) & a).  */
5347   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5348        || code == AND || code == IOR || code == XOR
5349        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5350       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5351           || (flag_associative_math && FLOAT_MODE_P (mode))))
5352     {
5353       if (GET_CODE (XEXP (x, 0)) == code)
5354         {
5355           rtx other = XEXP (XEXP (x, 0), 0);
5356           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5357           rtx inner_op1 = XEXP (x, 1);
5358           rtx inner;
5359
5360           /* Make sure we pass the constant operand if any as the second
5361              one if this is a commutative operation.  */
5362           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5363             {
5364               rtx tem = inner_op0;
5365               inner_op0 = inner_op1;
5366               inner_op1 = tem;
5367             }
5368           inner = simplify_binary_operation (code == MINUS ? PLUS
5369                                              : code == DIV ? MULT
5370                                              : code,
5371                                              mode, inner_op0, inner_op1);
5372
5373           /* For commutative operations, try the other pair if that one
5374              didn't simplify.  */
5375           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5376             {
5377               other = XEXP (XEXP (x, 0), 1);
5378               inner = simplify_binary_operation (code, mode,
5379                                                  XEXP (XEXP (x, 0), 0),
5380                                                  XEXP (x, 1));
5381             }
5382
5383           if (inner)
5384             return simplify_gen_binary (code, mode, other, inner);
5385         }
5386     }
5387
5388   /* A little bit of algebraic simplification here.  */
5389   switch (code)
5390     {
5391     case MEM:
5392       /* Ensure that our address has any ASHIFTs converted to MULT in case
5393          address-recognizing predicates are called later.  */
5394       temp = make_compound_operation (XEXP (x, 0), MEM);
5395       SUBST (XEXP (x, 0), temp);
5396       break;
5397
5398     case SUBREG:
5399       if (op0_mode == VOIDmode)
5400         op0_mode = GET_MODE (SUBREG_REG (x));
5401
5402       /* See if this can be moved to simplify_subreg.  */
5403       if (CONSTANT_P (SUBREG_REG (x))
5404           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5405              /* Don't call gen_lowpart if the inner mode
5406                 is VOIDmode and we cannot simplify it, as SUBREG without
5407                 inner mode is invalid.  */
5408           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5409               || gen_lowpart_common (mode, SUBREG_REG (x))))
5410         return gen_lowpart (mode, SUBREG_REG (x));
5411
5412       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5413         break;
5414       {
5415         rtx temp;
5416         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5417                                 SUBREG_BYTE (x));
5418         if (temp)
5419           return temp;
5420       }
5421
5422       /* Don't change the mode of the MEM if that would change the meaning
5423          of the address.  */
5424       if (MEM_P (SUBREG_REG (x))
5425           && (MEM_VOLATILE_P (SUBREG_REG (x))
5426               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5427                                            MEM_ADDR_SPACE (SUBREG_REG (x)))))
5428         return gen_rtx_CLOBBER (mode, const0_rtx);
5429
5430       /* Note that we cannot do any narrowing for non-constants since
5431          we might have been counting on using the fact that some bits were
5432          zero.  We now do this in the SET.  */
5433
5434       break;
5435
5436     case NEG:
5437       temp = expand_compound_operation (XEXP (x, 0));
5438
5439       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5440          replaced by (lshiftrt X C).  This will convert
5441          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5442
5443       if (GET_CODE (temp) == ASHIFTRT
5444           && CONST_INT_P (XEXP (temp, 1))
5445           && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5446         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5447                                      INTVAL (XEXP (temp, 1)));
5448
5449       /* If X has only a single bit that might be nonzero, say, bit I, convert
5450          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5451          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
5452          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
5453          or a SUBREG of one since we'd be making the expression more
5454          complex if it was just a register.  */
5455
5456       if (!REG_P (temp)
5457           && ! (GET_CODE (temp) == SUBREG
5458                 && REG_P (SUBREG_REG (temp)))
5459           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5460         {
5461           rtx temp1 = simplify_shift_const
5462             (NULL_RTX, ASHIFTRT, mode,
5463              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5464                                    GET_MODE_PRECISION (mode) - 1 - i),
5465              GET_MODE_PRECISION (mode) - 1 - i);
5466
5467           /* If all we did was surround TEMP with the two shifts, we
5468              haven't improved anything, so don't use it.  Otherwise,
5469              we are better off with TEMP1.  */
5470           if (GET_CODE (temp1) != ASHIFTRT
5471               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5472               || XEXP (XEXP (temp1, 0), 0) != temp)
5473             return temp1;
5474         }
5475       break;
5476
5477     case TRUNCATE:
5478       /* We can't handle truncation to a partial integer mode here
5479          because we don't know the real bitsize of the partial
5480          integer mode.  */
5481       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5482         break;
5483
5484       if (HWI_COMPUTABLE_MODE_P (mode))
5485         SUBST (XEXP (x, 0),
5486                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5487                               GET_MODE_MASK (mode), 0));
5488
5489       /* We can truncate a constant value and return it.  */
5490       if (CONST_INT_P (XEXP (x, 0)))
5491         return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5492
5493       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5494          whose value is a comparison can be replaced with a subreg if
5495          STORE_FLAG_VALUE permits.  */
5496       if (HWI_COMPUTABLE_MODE_P (mode)
5497           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5498           && (temp = get_last_value (XEXP (x, 0)))
5499           && COMPARISON_P (temp))
5500         return gen_lowpart (mode, XEXP (x, 0));
5501       break;
5502
5503     case CONST:
5504       /* (const (const X)) can become (const X).  Do it this way rather than
5505          returning the inner CONST since CONST can be shared with a
5506          REG_EQUAL note.  */
5507       if (GET_CODE (XEXP (x, 0)) == CONST)
5508         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5509       break;
5510
5511 #ifdef HAVE_lo_sum
5512     case LO_SUM:
5513       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
5514          can add in an offset.  find_split_point will split this address up
5515          again if it doesn't match.  */
5516       if (GET_CODE (XEXP (x, 0)) == HIGH
5517           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5518         return XEXP (x, 1);
5519       break;
5520 #endif
5521
5522     case PLUS:
5523       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5524          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5525          bit-field and can be replaced by either a sign_extend or a
5526          sign_extract.  The `and' may be a zero_extend and the two
5527          <c>, -<c> constants may be reversed.  */
5528       if (GET_CODE (XEXP (x, 0)) == XOR
5529           && CONST_INT_P (XEXP (x, 1))
5530           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5531           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5532           && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5533               || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5534           && HWI_COMPUTABLE_MODE_P (mode)
5535           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5536                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5537                && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5538                    == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5539               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5540                   && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5541                       == (unsigned int) i + 1))))
5542         return simplify_shift_const
5543           (NULL_RTX, ASHIFTRT, mode,
5544            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5545                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
5546                                  GET_MODE_PRECISION (mode) - (i + 1)),
5547            GET_MODE_PRECISION (mode) - (i + 1));
5548
5549       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5550          can become (ashiftrt (ashift (xor x 1) C) C) where C is
5551          the bitsize of the mode - 1.  This allows simplification of
5552          "a = (b & 8) == 0;"  */
5553       if (XEXP (x, 1) == constm1_rtx
5554           && !REG_P (XEXP (x, 0))
5555           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5556                 && REG_P (SUBREG_REG (XEXP (x, 0))))
5557           && nonzero_bits (XEXP (x, 0), mode) == 1)
5558         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5559            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5560                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5561                                  GET_MODE_PRECISION (mode) - 1),
5562            GET_MODE_PRECISION (mode) - 1);
5563
5564       /* If we are adding two things that have no bits in common, convert
5565          the addition into an IOR.  This will often be further simplified,
5566          for example in cases like ((a & 1) + (a & 2)), which can
5567          become a & 3.  */
5568
5569       if (HWI_COMPUTABLE_MODE_P (mode)
5570           && (nonzero_bits (XEXP (x, 0), mode)
5571               & nonzero_bits (XEXP (x, 1), mode)) == 0)
5572         {
5573           /* Try to simplify the expression further.  */
5574           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5575           temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5576
5577           /* If we could, great.  If not, do not go ahead with the IOR
5578              replacement, since PLUS appears in many special purpose
5579              address arithmetic instructions.  */
5580           if (GET_CODE (temp) != CLOBBER
5581               && (GET_CODE (temp) != IOR
5582                   || ((XEXP (temp, 0) != XEXP (x, 0)
5583                        || XEXP (temp, 1) != XEXP (x, 1))
5584                       && (XEXP (temp, 0) != XEXP (x, 1)
5585                           || XEXP (temp, 1) != XEXP (x, 0)))))
5586             return temp;
5587         }
5588       break;
5589
5590     case MINUS:
5591       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5592          (and <foo> (const_int pow2-1))  */
5593       if (GET_CODE (XEXP (x, 1)) == AND
5594           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5595           && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5596           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5597         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5598                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5599       break;
5600
5601     case MULT:
5602       /* If we have (mult (plus A B) C), apply the distributive law and then
5603          the inverse distributive law to see if things simplify.  This
5604          occurs mostly in addresses, often when unrolling loops.  */
5605
5606       if (GET_CODE (XEXP (x, 0)) == PLUS)
5607         {
5608           rtx result = distribute_and_simplify_rtx (x, 0);
5609           if (result)
5610             return result;
5611         }
5612
5613       /* Try simplify a*(b/c) as (a*b)/c.  */
5614       if (FLOAT_MODE_P (mode) && flag_associative_math
5615           && GET_CODE (XEXP (x, 0)) == DIV)
5616         {
5617           rtx tem = simplify_binary_operation (MULT, mode,
5618                                                XEXP (XEXP (x, 0), 0),
5619                                                XEXP (x, 1));
5620           if (tem)
5621             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5622         }
5623       break;
5624
5625     case UDIV:
5626       /* If this is a divide by a power of two, treat it as a shift if
5627          its first operand is a shift.  */
5628       if (CONST_INT_P (XEXP (x, 1))
5629           && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5630           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5631               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5632               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5633               || GET_CODE (XEXP (x, 0)) == ROTATE
5634               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5635         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5636       break;
5637
5638     case EQ:  case NE:
5639     case GT:  case GTU:  case GE:  case GEU:
5640     case LT:  case LTU:  case LE:  case LEU:
5641     case UNEQ:  case LTGT:
5642     case UNGT:  case UNGE:
5643     case UNLT:  case UNLE:
5644     case UNORDERED: case ORDERED:
5645       /* If the first operand is a condition code, we can't do anything
5646          with it.  */
5647       if (GET_CODE (XEXP (x, 0)) == COMPARE
5648           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5649               && ! CC0_P (XEXP (x, 0))))
5650         {
5651           rtx op0 = XEXP (x, 0);
5652           rtx op1 = XEXP (x, 1);
5653           enum rtx_code new_code;
5654
5655           if (GET_CODE (op0) == COMPARE)
5656             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5657
5658           /* Simplify our comparison, if possible.  */
5659           new_code = simplify_comparison (code, &op0, &op1);
5660
5661           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5662              if only the low-order bit is possibly nonzero in X (such as when
5663              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5664              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5665              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5666              (plus X 1).
5667
5668              Remove any ZERO_EXTRACT we made when thinking this was a
5669              comparison.  It may now be simpler to use, e.g., an AND.  If a
5670              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5671              the call to make_compound_operation in the SET case.
5672
5673              Don't apply these optimizations if the caller would
5674              prefer a comparison rather than a value.
5675              E.g., for the condition in an IF_THEN_ELSE most targets need
5676              an explicit comparison.  */
5677
5678           if (in_cond)
5679             ;
5680
5681           else if (STORE_FLAG_VALUE == 1
5682               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5683               && op1 == const0_rtx
5684               && mode == GET_MODE (op0)
5685               && nonzero_bits (op0, mode) == 1)
5686             return gen_lowpart (mode,
5687                                 expand_compound_operation (op0));
5688
5689           else if (STORE_FLAG_VALUE == 1
5690                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5691                    && op1 == const0_rtx
5692                    && mode == GET_MODE (op0)
5693                    && (num_sign_bit_copies (op0, mode)
5694                        == GET_MODE_PRECISION (mode)))
5695             {
5696               op0 = expand_compound_operation (op0);
5697               return simplify_gen_unary (NEG, mode,
5698                                          gen_lowpart (mode, op0),
5699                                          mode);
5700             }
5701
5702           else if (STORE_FLAG_VALUE == 1
5703                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5704                    && op1 == const0_rtx
5705                    && mode == GET_MODE (op0)
5706                    && nonzero_bits (op0, mode) == 1)
5707             {
5708               op0 = expand_compound_operation (op0);
5709               return simplify_gen_binary (XOR, mode,
5710                                           gen_lowpart (mode, op0),
5711                                           const1_rtx);
5712             }
5713
5714           else if (STORE_FLAG_VALUE == 1
5715                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5716                    && op1 == const0_rtx
5717                    && mode == GET_MODE (op0)
5718                    && (num_sign_bit_copies (op0, mode)
5719                        == GET_MODE_PRECISION (mode)))
5720             {
5721               op0 = expand_compound_operation (op0);
5722               return plus_constant (mode, gen_lowpart (mode, op0), 1);
5723             }
5724
5725           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5726              those above.  */
5727           if (in_cond)
5728             ;
5729
5730           else if (STORE_FLAG_VALUE == -1
5731               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5732               && op1 == const0_rtx
5733               && (num_sign_bit_copies (op0, mode)
5734                   == GET_MODE_PRECISION (mode)))
5735             return gen_lowpart (mode,
5736                                 expand_compound_operation (op0));
5737
5738           else if (STORE_FLAG_VALUE == -1
5739                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5740                    && op1 == const0_rtx
5741                    && mode == GET_MODE (op0)
5742                    && nonzero_bits (op0, mode) == 1)
5743             {
5744               op0 = expand_compound_operation (op0);
5745               return simplify_gen_unary (NEG, mode,
5746                                          gen_lowpart (mode, op0),
5747                                          mode);
5748             }
5749
5750           else if (STORE_FLAG_VALUE == -1
5751                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5752                    && op1 == const0_rtx
5753                    && mode == GET_MODE (op0)
5754                    && (num_sign_bit_copies (op0, mode)
5755                        == GET_MODE_PRECISION (mode)))
5756             {
5757               op0 = expand_compound_operation (op0);
5758               return simplify_gen_unary (NOT, mode,
5759                                          gen_lowpart (mode, op0),
5760                                          mode);
5761             }
5762
5763           /* If X is 0/1, (eq X 0) is X-1.  */
5764           else if (STORE_FLAG_VALUE == -1
5765                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5766                    && op1 == const0_rtx
5767                    && mode == GET_MODE (op0)
5768                    && nonzero_bits (op0, mode) == 1)
5769             {
5770               op0 = expand_compound_operation (op0);
5771               return plus_constant (mode, gen_lowpart (mode, op0), -1);
5772             }
5773
5774           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5775              one bit that might be nonzero, we can convert (ne x 0) to
5776              (ashift x c) where C puts the bit in the sign bit.  Remove any
5777              AND with STORE_FLAG_VALUE when we are done, since we are only
5778              going to test the sign bit.  */
5779           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5780               && HWI_COMPUTABLE_MODE_P (mode)
5781               && val_signbit_p (mode, STORE_FLAG_VALUE)
5782               && op1 == const0_rtx
5783               && mode == GET_MODE (op0)
5784               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5785             {
5786               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5787                                         expand_compound_operation (op0),
5788                                         GET_MODE_PRECISION (mode) - 1 - i);
5789               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5790                 return XEXP (x, 0);
5791               else
5792                 return x;
5793             }
5794
5795           /* If the code changed, return a whole new comparison.  */
5796           if (new_code != code)
5797             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5798
5799           /* Otherwise, keep this operation, but maybe change its operands.
5800              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5801           SUBST (XEXP (x, 0), op0);
5802           SUBST (XEXP (x, 1), op1);
5803         }
5804       break;
5805
5806     case IF_THEN_ELSE:
5807       return simplify_if_then_else (x);
5808
5809     case ZERO_EXTRACT:
5810     case SIGN_EXTRACT:
5811     case ZERO_EXTEND:
5812     case SIGN_EXTEND:
5813       /* If we are processing SET_DEST, we are done.  */
5814       if (in_dest)
5815         return x;
5816
5817       return expand_compound_operation (x);
5818
5819     case SET:
5820       return simplify_set (x);
5821
5822     case AND:
5823     case IOR:
5824       return simplify_logical (x);
5825
5826     case ASHIFT:
5827     case LSHIFTRT:
5828     case ASHIFTRT:
5829     case ROTATE:
5830     case ROTATERT:
5831       /* If this is a shift by a constant amount, simplify it.  */
5832       if (CONST_INT_P (XEXP (x, 1)))
5833         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5834                                      INTVAL (XEXP (x, 1)));
5835
5836       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5837         SUBST (XEXP (x, 1),
5838                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5839                               ((unsigned HOST_WIDE_INT) 1
5840                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5841                               - 1,
5842                               0));
5843       break;
5844
5845     default:
5846       break;
5847     }
5848
5849   return x;
5850 }
5851 \f
5852 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5853
5854 static rtx
5855 simplify_if_then_else (rtx x)
5856 {
5857   enum machine_mode mode = GET_MODE (x);
5858   rtx cond = XEXP (x, 0);
5859   rtx true_rtx = XEXP (x, 1);
5860   rtx false_rtx = XEXP (x, 2);
5861   enum rtx_code true_code = GET_CODE (cond);
5862   int comparison_p = COMPARISON_P (cond);
5863   rtx temp;
5864   int i;
5865   enum rtx_code false_code;
5866   rtx reversed;
5867
5868   /* Simplify storing of the truth value.  */
5869   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5870     return simplify_gen_relational (true_code, mode, VOIDmode,
5871                                     XEXP (cond, 0), XEXP (cond, 1));
5872
5873   /* Also when the truth value has to be reversed.  */
5874   if (comparison_p
5875       && true_rtx == const0_rtx && false_rtx == const_true_rtx
5876       && (reversed = reversed_comparison (cond, mode)))
5877     return reversed;
5878
5879   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5880      in it is being compared against certain values.  Get the true and false
5881      comparisons and see if that says anything about the value of each arm.  */
5882
5883   if (comparison_p
5884       && ((false_code = reversed_comparison_code (cond, NULL))
5885           != UNKNOWN)
5886       && REG_P (XEXP (cond, 0)))
5887     {
5888       HOST_WIDE_INT nzb;
5889       rtx from = XEXP (cond, 0);
5890       rtx true_val = XEXP (cond, 1);
5891       rtx false_val = true_val;
5892       int swapped = 0;
5893
5894       /* If FALSE_CODE is EQ, swap the codes and arms.  */
5895
5896       if (false_code == EQ)
5897         {
5898           swapped = 1, true_code = EQ, false_code = NE;
5899           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5900         }
5901
5902       /* If we are comparing against zero and the expression being tested has
5903          only a single bit that might be nonzero, that is its value when it is
5904          not equal to zero.  Similarly if it is known to be -1 or 0.  */
5905
5906       if (true_code == EQ && true_val == const0_rtx
5907           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5908         {
5909           false_code = EQ;
5910           false_val = gen_int_mode (nzb, GET_MODE (from));
5911         }
5912       else if (true_code == EQ && true_val == const0_rtx
5913                && (num_sign_bit_copies (from, GET_MODE (from))
5914                    == GET_MODE_PRECISION (GET_MODE (from))))
5915         {
5916           false_code = EQ;
5917           false_val = constm1_rtx;
5918         }
5919
5920       /* Now simplify an arm if we know the value of the register in the
5921          branch and it is used in the arm.  Be careful due to the potential
5922          of locally-shared RTL.  */
5923
5924       if (reg_mentioned_p (from, true_rtx))
5925         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5926                                       from, true_val),
5927                           pc_rtx, pc_rtx, 0, 0, 0);
5928       if (reg_mentioned_p (from, false_rtx))
5929         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5930                                    from, false_val),
5931                            pc_rtx, pc_rtx, 0, 0, 0);
5932
5933       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5934       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5935
5936       true_rtx = XEXP (x, 1);
5937       false_rtx = XEXP (x, 2);
5938       true_code = GET_CODE (cond);
5939     }
5940
5941   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5942      reversed, do so to avoid needing two sets of patterns for
5943      subtract-and-branch insns.  Similarly if we have a constant in the true
5944      arm, the false arm is the same as the first operand of the comparison, or
5945      the false arm is more complicated than the true arm.  */
5946
5947   if (comparison_p
5948       && reversed_comparison_code (cond, NULL) != UNKNOWN
5949       && (true_rtx == pc_rtx
5950           || (CONSTANT_P (true_rtx)
5951               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5952           || true_rtx == const0_rtx
5953           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5954           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5955               && !OBJECT_P (false_rtx))
5956           || reg_mentioned_p (true_rtx, false_rtx)
5957           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5958     {
5959       true_code = reversed_comparison_code (cond, NULL);
5960       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5961       SUBST (XEXP (x, 1), false_rtx);
5962       SUBST (XEXP (x, 2), true_rtx);
5963
5964       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5965       cond = XEXP (x, 0);
5966
5967       /* It is possible that the conditional has been simplified out.  */
5968       true_code = GET_CODE (cond);
5969       comparison_p = COMPARISON_P (cond);
5970     }
5971
5972   /* If the two arms are identical, we don't need the comparison.  */
5973
5974   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5975     return true_rtx;
5976
5977   /* Convert a == b ? b : a to "a".  */
5978   if (true_code == EQ && ! side_effects_p (cond)
5979       && !HONOR_NANS (mode)
5980       && rtx_equal_p (XEXP (cond, 0), false_rtx)
5981       && rtx_equal_p (XEXP (cond, 1), true_rtx))
5982     return false_rtx;
5983   else if (true_code == NE && ! side_effects_p (cond)
5984            && !HONOR_NANS (mode)
5985            && rtx_equal_p (XEXP (cond, 0), true_rtx)
5986            && rtx_equal_p (XEXP (cond, 1), false_rtx))
5987     return true_rtx;
5988
5989   /* Look for cases where we have (abs x) or (neg (abs X)).  */
5990
5991   if (GET_MODE_CLASS (mode) == MODE_INT
5992       && comparison_p
5993       && XEXP (cond, 1) == const0_rtx
5994       && GET_CODE (false_rtx) == NEG
5995       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5996       && rtx_equal_p (true_rtx, XEXP (cond, 0))
5997       && ! side_effects_p (true_rtx))
5998     switch (true_code)
5999       {
6000       case GT:
6001       case GE:
6002         return simplify_gen_unary (ABS, mode, true_rtx, mode);
6003       case LT:
6004       case LE:
6005         return
6006           simplify_gen_unary (NEG, mode,
6007                               simplify_gen_unary (ABS, mode, true_rtx, mode),
6008                               mode);
6009       default:
6010         break;
6011       }
6012
6013   /* Look for MIN or MAX.  */
6014
6015   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6016       && comparison_p
6017       && rtx_equal_p (XEXP (cond, 0), true_rtx)
6018       && rtx_equal_p (XEXP (cond, 1), false_rtx)
6019       && ! side_effects_p (cond))
6020     switch (true_code)
6021       {
6022       case GE:
6023       case GT:
6024         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6025       case LE:
6026       case LT:
6027         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6028       case GEU:
6029       case GTU:
6030         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6031       case LEU:
6032       case LTU:
6033         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6034       default:
6035         break;
6036       }
6037
6038   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6039      second operand is zero, this can be done as (OP Z (mult COND C2)) where
6040      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6041      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6042      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6043      neither 1 or -1, but it isn't worth checking for.  */
6044
6045   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6046       && comparison_p
6047       && GET_MODE_CLASS (mode) == MODE_INT
6048       && ! side_effects_p (x))
6049     {
6050       rtx t = make_compound_operation (true_rtx, SET);
6051       rtx f = make_compound_operation (false_rtx, SET);
6052       rtx cond_op0 = XEXP (cond, 0);
6053       rtx cond_op1 = XEXP (cond, 1);
6054       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6055       enum machine_mode m = mode;
6056       rtx z = 0, c1 = NULL_RTX;
6057
6058       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6059            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6060            || GET_CODE (t) == ASHIFT
6061            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6062           && rtx_equal_p (XEXP (t, 0), f))
6063         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6064
6065       /* If an identity-zero op is commutative, check whether there
6066          would be a match if we swapped the operands.  */
6067       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6068                 || GET_CODE (t) == XOR)
6069                && rtx_equal_p (XEXP (t, 1), f))
6070         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6071       else if (GET_CODE (t) == SIGN_EXTEND
6072                && (GET_CODE (XEXP (t, 0)) == PLUS
6073                    || GET_CODE (XEXP (t, 0)) == MINUS
6074                    || GET_CODE (XEXP (t, 0)) == IOR
6075                    || GET_CODE (XEXP (t, 0)) == XOR
6076                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6077                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6078                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6079                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6080                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6081                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6082                && (num_sign_bit_copies (f, GET_MODE (f))
6083                    > (unsigned int)
6084                      (GET_MODE_PRECISION (mode)
6085                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6086         {
6087           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6088           extend_op = SIGN_EXTEND;
6089           m = GET_MODE (XEXP (t, 0));
6090         }
6091       else if (GET_CODE (t) == SIGN_EXTEND
6092                && (GET_CODE (XEXP (t, 0)) == PLUS
6093                    || GET_CODE (XEXP (t, 0)) == IOR
6094                    || GET_CODE (XEXP (t, 0)) == XOR)
6095                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6096                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6097                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6098                && (num_sign_bit_copies (f, GET_MODE (f))
6099                    > (unsigned int)
6100                      (GET_MODE_PRECISION (mode)
6101                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6102         {
6103           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6104           extend_op = SIGN_EXTEND;
6105           m = GET_MODE (XEXP (t, 0));
6106         }
6107       else if (GET_CODE (t) == ZERO_EXTEND
6108                && (GET_CODE (XEXP (t, 0)) == PLUS
6109                    || GET_CODE (XEXP (t, 0)) == MINUS
6110                    || GET_CODE (XEXP (t, 0)) == IOR
6111                    || GET_CODE (XEXP (t, 0)) == XOR
6112                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6113                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6114                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6115                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6116                && HWI_COMPUTABLE_MODE_P (mode)
6117                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6118                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6119                && ((nonzero_bits (f, GET_MODE (f))
6120                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6121                    == 0))
6122         {
6123           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6124           extend_op = ZERO_EXTEND;
6125           m = GET_MODE (XEXP (t, 0));
6126         }
6127       else if (GET_CODE (t) == ZERO_EXTEND
6128                && (GET_CODE (XEXP (t, 0)) == PLUS
6129                    || GET_CODE (XEXP (t, 0)) == IOR
6130                    || GET_CODE (XEXP (t, 0)) == XOR)
6131                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6132                && HWI_COMPUTABLE_MODE_P (mode)
6133                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6134                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6135                && ((nonzero_bits (f, GET_MODE (f))
6136                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6137                    == 0))
6138         {
6139           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6140           extend_op = ZERO_EXTEND;
6141           m = GET_MODE (XEXP (t, 0));
6142         }
6143
6144       if (z)
6145         {
6146           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6147                                                  cond_op0, cond_op1),
6148                         pc_rtx, pc_rtx, 0, 0, 0);
6149           temp = simplify_gen_binary (MULT, m, temp,
6150                                       simplify_gen_binary (MULT, m, c1,
6151                                                            const_true_rtx));
6152           temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6153           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6154
6155           if (extend_op != UNKNOWN)
6156             temp = simplify_gen_unary (extend_op, mode, temp, m);
6157
6158           return temp;
6159         }
6160     }
6161
6162   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6163      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6164      negation of a single bit, we can convert this operation to a shift.  We
6165      can actually do this more generally, but it doesn't seem worth it.  */
6166
6167   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6168       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6169       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6170            && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6171           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6172                == GET_MODE_PRECISION (mode))
6173               && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6174     return
6175       simplify_shift_const (NULL_RTX, ASHIFT, mode,
6176                             gen_lowpart (mode, XEXP (cond, 0)), i);
6177
6178   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
6179   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6180       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6181       && GET_MODE (XEXP (cond, 0)) == mode
6182       && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6183           == nonzero_bits (XEXP (cond, 0), mode)
6184       && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6185     return XEXP (cond, 0);
6186
6187   return x;
6188 }
6189 \f
6190 /* Simplify X, a SET expression.  Return the new expression.  */
6191
6192 static rtx
6193 simplify_set (rtx x)
6194 {
6195   rtx src = SET_SRC (x);
6196   rtx dest = SET_DEST (x);
6197   enum machine_mode mode
6198     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6199   rtx other_insn;
6200   rtx *cc_use;
6201
6202   /* (set (pc) (return)) gets written as (return).  */
6203   if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6204     return src;
6205
6206   /* Now that we know for sure which bits of SRC we are using, see if we can
6207      simplify the expression for the object knowing that we only need the
6208      low-order bits.  */
6209
6210   if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6211     {
6212       src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6213       SUBST (SET_SRC (x), src);
6214     }
6215
6216   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6217      the comparison result and try to simplify it unless we already have used
6218      undobuf.other_insn.  */
6219   if ((GET_MODE_CLASS (mode) == MODE_CC
6220        || GET_CODE (src) == COMPARE
6221        || CC0_P (dest))
6222       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6223       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6224       && COMPARISON_P (*cc_use)
6225       && rtx_equal_p (XEXP (*cc_use, 0), dest))
6226     {
6227       enum rtx_code old_code = GET_CODE (*cc_use);
6228       enum rtx_code new_code;
6229       rtx op0, op1, tmp;
6230       int other_changed = 0;
6231       rtx inner_compare = NULL_RTX;
6232       enum machine_mode compare_mode = GET_MODE (dest);
6233
6234       if (GET_CODE (src) == COMPARE)
6235         {
6236           op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6237           if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6238             {
6239               inner_compare = op0;
6240               op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6241             }
6242         }
6243       else
6244         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6245
6246       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6247                                            op0, op1);
6248       if (!tmp)
6249         new_code = old_code;
6250       else if (!CONSTANT_P (tmp))
6251         {
6252           new_code = GET_CODE (tmp);
6253           op0 = XEXP (tmp, 0);
6254           op1 = XEXP (tmp, 1);
6255         }
6256       else
6257         {
6258           rtx pat = PATTERN (other_insn);
6259           undobuf.other_insn = other_insn;
6260           SUBST (*cc_use, tmp);
6261
6262           /* Attempt to simplify CC user.  */
6263           if (GET_CODE (pat) == SET)
6264             {
6265               rtx new_rtx = simplify_rtx (SET_SRC (pat));
6266               if (new_rtx != NULL_RTX)
6267                 SUBST (SET_SRC (pat), new_rtx);
6268             }
6269
6270           /* Convert X into a no-op move.  */
6271           SUBST (SET_DEST (x), pc_rtx);
6272           SUBST (SET_SRC (x), pc_rtx);
6273           return x;
6274         }
6275
6276       /* Simplify our comparison, if possible.  */
6277       new_code = simplify_comparison (new_code, &op0, &op1);
6278
6279 #ifdef SELECT_CC_MODE
6280       /* If this machine has CC modes other than CCmode, check to see if we
6281          need to use a different CC mode here.  */
6282       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6283         compare_mode = GET_MODE (op0);
6284       else if (inner_compare
6285                && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6286                && new_code == old_code
6287                && op0 == XEXP (inner_compare, 0)
6288                && op1 == XEXP (inner_compare, 1))
6289         compare_mode = GET_MODE (inner_compare);
6290       else
6291         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6292
6293 #ifndef HAVE_cc0
6294       /* If the mode changed, we have to change SET_DEST, the mode in the
6295          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
6296          a hard register, just build new versions with the proper mode.  If it
6297          is a pseudo, we lose unless it is only time we set the pseudo, in
6298          which case we can safely change its mode.  */
6299       if (compare_mode != GET_MODE (dest))
6300         {
6301           if (can_change_dest_mode (dest, 0, compare_mode))
6302             {
6303               unsigned int regno = REGNO (dest);
6304               rtx new_dest;
6305
6306               if (regno < FIRST_PSEUDO_REGISTER)
6307                 new_dest = gen_rtx_REG (compare_mode, regno);
6308               else
6309                 {
6310                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6311                   new_dest = regno_reg_rtx[regno];
6312                 }
6313
6314               SUBST (SET_DEST (x), new_dest);
6315               SUBST (XEXP (*cc_use, 0), new_dest);
6316               other_changed = 1;
6317
6318               dest = new_dest;
6319             }
6320         }
6321 #endif  /* cc0 */
6322 #endif  /* SELECT_CC_MODE */
6323
6324       /* If the code changed, we have to build a new comparison in
6325          undobuf.other_insn.  */
6326       if (new_code != old_code)
6327         {
6328           int other_changed_previously = other_changed;
6329           unsigned HOST_WIDE_INT mask;
6330           rtx old_cc_use = *cc_use;
6331
6332           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6333                                           dest, const0_rtx));
6334           other_changed = 1;
6335
6336           /* If the only change we made was to change an EQ into an NE or
6337              vice versa, OP0 has only one bit that might be nonzero, and OP1
6338              is zero, check if changing the user of the condition code will
6339              produce a valid insn.  If it won't, we can keep the original code
6340              in that insn by surrounding our operation with an XOR.  */
6341
6342           if (((old_code == NE && new_code == EQ)
6343                || (old_code == EQ && new_code == NE))
6344               && ! other_changed_previously && op1 == const0_rtx
6345               && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6346               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6347             {
6348               rtx pat = PATTERN (other_insn), note = 0;
6349
6350               if ((recog_for_combine (&pat, other_insn, &note) < 0
6351                    && ! check_asm_operands (pat)))
6352                 {
6353                   *cc_use = old_cc_use;
6354                   other_changed = 0;
6355
6356                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6357                                              op0, GEN_INT (mask));
6358                 }
6359             }
6360         }
6361
6362       if (other_changed)
6363         undobuf.other_insn = other_insn;
6364
6365       /* Otherwise, if we didn't previously have a COMPARE in the
6366          correct mode, we need one.  */
6367       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6368         {
6369           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6370           src = SET_SRC (x);
6371         }
6372       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6373         {
6374           SUBST (SET_SRC (x), op0);
6375           src = SET_SRC (x);
6376         }
6377       /* Otherwise, update the COMPARE if needed.  */
6378       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6379         {
6380           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6381           src = SET_SRC (x);
6382         }
6383     }
6384   else
6385     {
6386       /* Get SET_SRC in a form where we have placed back any
6387          compound expressions.  Then do the checks below.  */
6388       src = make_compound_operation (src, SET);
6389       SUBST (SET_SRC (x), src);
6390     }
6391
6392   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6393      and X being a REG or (subreg (reg)), we may be able to convert this to
6394      (set (subreg:m2 x) (op)).
6395
6396      We can always do this if M1 is narrower than M2 because that means that
6397      we only care about the low bits of the result.
6398
6399      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6400      perform a narrower operation than requested since the high-order bits will
6401      be undefined.  On machine where it is defined, this transformation is safe
6402      as long as M1 and M2 have the same number of words.  */
6403
6404   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6405       && !OBJECT_P (SUBREG_REG (src))
6406       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6407            / UNITS_PER_WORD)
6408           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6409                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6410 #ifndef WORD_REGISTER_OPERATIONS
6411       && (GET_MODE_SIZE (GET_MODE (src))
6412         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6413 #endif
6414 #ifdef CANNOT_CHANGE_MODE_CLASS
6415       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6416             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6417                                          GET_MODE (SUBREG_REG (src)),
6418                                          GET_MODE (src)))
6419 #endif
6420       && (REG_P (dest)
6421           || (GET_CODE (dest) == SUBREG
6422               && REG_P (SUBREG_REG (dest)))))
6423     {
6424       SUBST (SET_DEST (x),
6425              gen_lowpart (GET_MODE (SUBREG_REG (src)),
6426                                       dest));
6427       SUBST (SET_SRC (x), SUBREG_REG (src));
6428
6429       src = SET_SRC (x), dest = SET_DEST (x);
6430     }
6431
6432 #ifdef HAVE_cc0
6433   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6434      in SRC.  */
6435   if (dest == cc0_rtx
6436       && GET_CODE (src) == SUBREG
6437       && subreg_lowpart_p (src)
6438       && (GET_MODE_PRECISION (GET_MODE (src))
6439           < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6440     {
6441       rtx inner = SUBREG_REG (src);
6442       enum machine_mode inner_mode = GET_MODE (inner);
6443
6444       /* Here we make sure that we don't have a sign bit on.  */
6445       if (val_signbit_known_clear_p (GET_MODE (src),
6446                                      nonzero_bits (inner, inner_mode)))
6447         {
6448           SUBST (SET_SRC (x), inner);
6449           src = SET_SRC (x);
6450         }
6451     }
6452 #endif
6453
6454 #ifdef LOAD_EXTEND_OP
6455   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6456      would require a paradoxical subreg.  Replace the subreg with a
6457      zero_extend to avoid the reload that would otherwise be required.  */
6458
6459   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6460       && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6461       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6462       && SUBREG_BYTE (src) == 0
6463       && paradoxical_subreg_p (src)
6464       && MEM_P (SUBREG_REG (src)))
6465     {
6466       SUBST (SET_SRC (x),
6467              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6468                             GET_MODE (src), SUBREG_REG (src)));
6469
6470       src = SET_SRC (x);
6471     }
6472 #endif
6473
6474   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6475      are comparing an item known to be 0 or -1 against 0, use a logical
6476      operation instead. Check for one of the arms being an IOR of the other
6477      arm with some value.  We compute three terms to be IOR'ed together.  In
6478      practice, at most two will be nonzero.  Then we do the IOR's.  */
6479
6480   if (GET_CODE (dest) != PC
6481       && GET_CODE (src) == IF_THEN_ELSE
6482       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6483       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6484       && XEXP (XEXP (src, 0), 1) == const0_rtx
6485       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6486 #ifdef HAVE_conditional_move
6487       && ! can_conditionally_move_p (GET_MODE (src))
6488 #endif
6489       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6490                                GET_MODE (XEXP (XEXP (src, 0), 0)))
6491           == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6492       && ! side_effects_p (src))
6493     {
6494       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6495                       ? XEXP (src, 1) : XEXP (src, 2));
6496       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6497                    ? XEXP (src, 2) : XEXP (src, 1));
6498       rtx term1 = const0_rtx, term2, term3;
6499
6500       if (GET_CODE (true_rtx) == IOR
6501           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6502         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6503       else if (GET_CODE (true_rtx) == IOR
6504                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6505         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6506       else if (GET_CODE (false_rtx) == IOR
6507                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6508         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6509       else if (GET_CODE (false_rtx) == IOR
6510                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6511         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6512
6513       term2 = simplify_gen_binary (AND, GET_MODE (src),
6514                                    XEXP (XEXP (src, 0), 0), true_rtx);
6515       term3 = simplify_gen_binary (AND, GET_MODE (src),
6516                                    simplify_gen_unary (NOT, GET_MODE (src),
6517                                                        XEXP (XEXP (src, 0), 0),
6518                                                        GET_MODE (src)),
6519                                    false_rtx);
6520
6521       SUBST (SET_SRC (x),
6522              simplify_gen_binary (IOR, GET_MODE (src),
6523                                   simplify_gen_binary (IOR, GET_MODE (src),
6524                                                        term1, term2),
6525                                   term3));
6526
6527       src = SET_SRC (x);
6528     }
6529
6530   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6531      whole thing fail.  */
6532   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6533     return src;
6534   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6535     return dest;
6536   else
6537     /* Convert this into a field assignment operation, if possible.  */
6538     return make_field_assignment (x);
6539 }
6540 \f
6541 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6542    result.  */
6543
6544 static rtx
6545 simplify_logical (rtx x)
6546 {
6547   enum machine_mode mode = GET_MODE (x);
6548   rtx op0 = XEXP (x, 0);
6549   rtx op1 = XEXP (x, 1);
6550
6551   switch (GET_CODE (x))
6552     {
6553     case AND:
6554       /* We can call simplify_and_const_int only if we don't lose
6555          any (sign) bits when converting INTVAL (op1) to
6556          "unsigned HOST_WIDE_INT".  */
6557       if (CONST_INT_P (op1)
6558           && (HWI_COMPUTABLE_MODE_P (mode)
6559               || INTVAL (op1) > 0))
6560         {
6561           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6562           if (GET_CODE (x) != AND)
6563             return x;
6564
6565           op0 = XEXP (x, 0);
6566           op1 = XEXP (x, 1);
6567         }
6568
6569       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6570          apply the distributive law and then the inverse distributive
6571          law to see if things simplify.  */
6572       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6573         {
6574           rtx result = distribute_and_simplify_rtx (x, 0);
6575           if (result)
6576             return result;
6577         }
6578       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6579         {
6580           rtx result = distribute_and_simplify_rtx (x, 1);
6581           if (result)
6582             return result;
6583         }
6584       break;
6585
6586     case IOR:
6587       /* If we have (ior (and A B) C), apply the distributive law and then
6588          the inverse distributive law to see if things simplify.  */
6589
6590       if (GET_CODE (op0) == AND)
6591         {
6592           rtx result = distribute_and_simplify_rtx (x, 0);
6593           if (result)
6594             return result;
6595         }
6596
6597       if (GET_CODE (op1) == AND)
6598         {
6599           rtx result = distribute_and_simplify_rtx (x, 1);
6600           if (result)
6601             return result;
6602         }
6603       break;
6604
6605     default:
6606       gcc_unreachable ();
6607     }
6608
6609   return x;
6610 }
6611 \f
6612 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6613    operations" because they can be replaced with two more basic operations.
6614    ZERO_EXTEND is also considered "compound" because it can be replaced with
6615    an AND operation, which is simpler, though only one operation.
6616
6617    The function expand_compound_operation is called with an rtx expression
6618    and will convert it to the appropriate shifts and AND operations,
6619    simplifying at each stage.
6620
6621    The function make_compound_operation is called to convert an expression
6622    consisting of shifts and ANDs into the equivalent compound expression.
6623    It is the inverse of this function, loosely speaking.  */
6624
6625 static rtx
6626 expand_compound_operation (rtx x)
6627 {
6628   unsigned HOST_WIDE_INT pos = 0, len;
6629   int unsignedp = 0;
6630   unsigned int modewidth;
6631   rtx tem;
6632
6633   switch (GET_CODE (x))
6634     {
6635     case ZERO_EXTEND:
6636       unsignedp = 1;
6637     case SIGN_EXTEND:
6638       /* We can't necessarily use a const_int for a multiword mode;
6639          it depends on implicitly extending the value.
6640          Since we don't know the right way to extend it,
6641          we can't tell whether the implicit way is right.
6642
6643          Even for a mode that is no wider than a const_int,
6644          we can't win, because we need to sign extend one of its bits through
6645          the rest of it, and we don't know which bit.  */
6646       if (CONST_INT_P (XEXP (x, 0)))
6647         return x;
6648
6649       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6650          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6651          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6652          reloaded. If not for that, MEM's would very rarely be safe.
6653
6654          Reject MODEs bigger than a word, because we might not be able
6655          to reference a two-register group starting with an arbitrary register
6656          (and currently gen_lowpart might crash for a SUBREG).  */
6657
6658       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6659         return x;
6660
6661       /* Reject MODEs that aren't scalar integers because turning vector
6662          or complex modes into shifts causes problems.  */
6663
6664       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6665         return x;
6666
6667       len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6668       /* If the inner object has VOIDmode (the only way this can happen
6669          is if it is an ASM_OPERANDS), we can't do anything since we don't
6670          know how much masking to do.  */
6671       if (len == 0)
6672         return x;
6673
6674       break;
6675
6676     case ZERO_EXTRACT:
6677       unsignedp = 1;
6678
6679       /* ... fall through ...  */
6680
6681     case SIGN_EXTRACT:
6682       /* If the operand is a CLOBBER, just return it.  */
6683       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6684         return XEXP (x, 0);
6685
6686       if (!CONST_INT_P (XEXP (x, 1))
6687           || !CONST_INT_P (XEXP (x, 2))
6688           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6689         return x;
6690
6691       /* Reject MODEs that aren't scalar integers because turning vector
6692          or complex modes into shifts causes problems.  */
6693
6694       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6695         return x;
6696
6697       len = INTVAL (XEXP (x, 1));
6698       pos = INTVAL (XEXP (x, 2));
6699
6700       /* This should stay within the object being extracted, fail otherwise.  */
6701       if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6702         return x;
6703
6704       if (BITS_BIG_ENDIAN)
6705         pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6706
6707       break;
6708
6709     default:
6710       return x;
6711     }
6712   /* Convert sign extension to zero extension, if we know that the high
6713      bit is not set, as this is easier to optimize.  It will be converted
6714      back to cheaper alternative in make_extraction.  */
6715   if (GET_CODE (x) == SIGN_EXTEND
6716       && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6717           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6718                 & ~(((unsigned HOST_WIDE_INT)
6719                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6720                      >> 1))
6721                == 0)))
6722     {
6723       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6724       rtx temp2 = expand_compound_operation (temp);
6725
6726       /* Make sure this is a profitable operation.  */
6727       if (set_src_cost (x, optimize_this_for_speed_p)
6728           > set_src_cost (temp2, optimize_this_for_speed_p))
6729        return temp2;
6730       else if (set_src_cost (x, optimize_this_for_speed_p)
6731                > set_src_cost (temp, optimize_this_for_speed_p))
6732        return temp;
6733       else
6734        return x;
6735     }
6736
6737   /* We can optimize some special cases of ZERO_EXTEND.  */
6738   if (GET_CODE (x) == ZERO_EXTEND)
6739     {
6740       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6741          know that the last value didn't have any inappropriate bits
6742          set.  */
6743       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6744           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6745           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6746           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6747               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6748         return XEXP (XEXP (x, 0), 0);
6749
6750       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6751       if (GET_CODE (XEXP (x, 0)) == SUBREG
6752           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6753           && subreg_lowpart_p (XEXP (x, 0))
6754           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6755           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6756               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6757         return SUBREG_REG (XEXP (x, 0));
6758
6759       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6760          is a comparison and STORE_FLAG_VALUE permits.  This is like
6761          the first case, but it works even when GET_MODE (x) is larger
6762          than HOST_WIDE_INT.  */
6763       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6764           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6765           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6766           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6767               <= HOST_BITS_PER_WIDE_INT)
6768           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6769         return XEXP (XEXP (x, 0), 0);
6770
6771       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6772       if (GET_CODE (XEXP (x, 0)) == SUBREG
6773           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6774           && subreg_lowpart_p (XEXP (x, 0))
6775           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6776           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6777               <= HOST_BITS_PER_WIDE_INT)
6778           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6779         return SUBREG_REG (XEXP (x, 0));
6780
6781     }
6782
6783   /* If we reach here, we want to return a pair of shifts.  The inner
6784      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6785      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6786      logical depending on the value of UNSIGNEDP.
6787
6788      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6789      converted into an AND of a shift.
6790
6791      We must check for the case where the left shift would have a negative
6792      count.  This can happen in a case like (x >> 31) & 255 on machines
6793      that can't shift by a constant.  On those machines, we would first
6794      combine the shift with the AND to produce a variable-position
6795      extraction.  Then the constant of 31 would be substituted in
6796      to produce such a position.  */
6797
6798   modewidth = GET_MODE_PRECISION (GET_MODE (x));
6799   if (modewidth >= pos + len)
6800     {
6801       enum machine_mode mode = GET_MODE (x);
6802       tem = gen_lowpart (mode, XEXP (x, 0));
6803       if (!tem || GET_CODE (tem) == CLOBBER)
6804         return x;
6805       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6806                                   tem, modewidth - pos - len);
6807       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6808                                   mode, tem, modewidth - len);
6809     }
6810   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6811     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6812                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6813                                                         GET_MODE (x),
6814                                                         XEXP (x, 0), pos),
6815                                   ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6816   else
6817     /* Any other cases we can't handle.  */
6818     return x;
6819
6820   /* If we couldn't do this for some reason, return the original
6821      expression.  */
6822   if (GET_CODE (tem) == CLOBBER)
6823     return x;
6824
6825   return tem;
6826 }
6827 \f
6828 /* X is a SET which contains an assignment of one object into
6829    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6830    or certain SUBREGS). If possible, convert it into a series of
6831    logical operations.
6832
6833    We half-heartedly support variable positions, but do not at all
6834    support variable lengths.  */
6835
6836 static const_rtx
6837 expand_field_assignment (const_rtx x)
6838 {
6839   rtx inner;
6840   rtx pos;                      /* Always counts from low bit.  */
6841   int len;
6842   rtx mask, cleared, masked;
6843   enum machine_mode compute_mode;
6844
6845   /* Loop until we find something we can't simplify.  */
6846   while (1)
6847     {
6848       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6849           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6850         {
6851           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6852           len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6853           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6854         }
6855       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6856                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6857         {
6858           inner = XEXP (SET_DEST (x), 0);
6859           len = INTVAL (XEXP (SET_DEST (x), 1));
6860           pos = XEXP (SET_DEST (x), 2);
6861
6862           /* A constant position should stay within the width of INNER.  */
6863           if (CONST_INT_P (pos)
6864               && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
6865             break;
6866
6867           if (BITS_BIG_ENDIAN)
6868             {
6869               if (CONST_INT_P (pos))
6870                 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
6871                                - INTVAL (pos));
6872               else if (GET_CODE (pos) == MINUS
6873                        && CONST_INT_P (XEXP (pos, 1))
6874                        && (INTVAL (XEXP (pos, 1))
6875                            == GET_MODE_PRECISION (GET_MODE (inner)) - len))
6876                 /* If position is ADJUST - X, new position is X.  */
6877                 pos = XEXP (pos, 0);
6878               else
6879                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6880                                            GEN_INT (GET_MODE_PRECISION (
6881                                                     GET_MODE (inner))
6882                                                     - len),
6883                                            pos);
6884             }
6885         }
6886
6887       /* A SUBREG between two modes that occupy the same numbers of words
6888          can be done by moving the SUBREG to the source.  */
6889       else if (GET_CODE (SET_DEST (x)) == SUBREG
6890                /* We need SUBREGs to compute nonzero_bits properly.  */
6891                && nonzero_sign_valid
6892                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6893                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6894                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6895                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6896         {
6897           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6898                            gen_lowpart
6899                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
6900                             SET_SRC (x)));
6901           continue;
6902         }
6903       else
6904         break;
6905
6906       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6907         inner = SUBREG_REG (inner);
6908
6909       compute_mode = GET_MODE (inner);
6910
6911       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
6912       if (! SCALAR_INT_MODE_P (compute_mode))
6913         {
6914           enum machine_mode imode;
6915
6916           /* Don't do anything for vector or complex integral types.  */
6917           if (! FLOAT_MODE_P (compute_mode))
6918             break;
6919
6920           /* Try to find an integral mode to pun with.  */
6921           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6922           if (imode == BLKmode)
6923             break;
6924
6925           compute_mode = imode;
6926           inner = gen_lowpart (imode, inner);
6927         }
6928
6929       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
6930       if (len >= HOST_BITS_PER_WIDE_INT)
6931         break;
6932
6933       /* Now compute the equivalent expression.  Make a copy of INNER
6934          for the SET_DEST in case it is a MEM into which we will substitute;
6935          we don't want shared RTL in that case.  */
6936       mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
6937       cleared = simplify_gen_binary (AND, compute_mode,
6938                                      simplify_gen_unary (NOT, compute_mode,
6939                                        simplify_gen_binary (ASHIFT,
6940                                                             compute_mode,
6941                                                             mask, pos),
6942                                        compute_mode),
6943                                      inner);
6944       masked = simplify_gen_binary (ASHIFT, compute_mode,
6945                                     simplify_gen_binary (
6946                                       AND, compute_mode,
6947                                       gen_lowpart (compute_mode, SET_SRC (x)),
6948                                       mask),
6949                                     pos);
6950
6951       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6952                        simplify_gen_binary (IOR, compute_mode,
6953                                             cleared, masked));
6954     }
6955
6956   return x;
6957 }
6958 \f
6959 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
6960    it is an RTX that represents the (variable) starting position; otherwise,
6961    POS is the (constant) starting bit position.  Both are counted from the LSB.
6962
6963    UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
6964
6965    IN_DEST is nonzero if this is a reference in the destination of a SET.
6966    This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
6967    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6968    be used.
6969
6970    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
6971    ZERO_EXTRACT should be built even for bits starting at bit 0.
6972
6973    MODE is the desired mode of the result (if IN_DEST == 0).
6974
6975    The result is an RTX for the extraction or NULL_RTX if the target
6976    can't handle it.  */
6977
6978 static rtx
6979 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6980                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6981                  int in_dest, int in_compare)
6982 {
6983   /* This mode describes the size of the storage area
6984      to fetch the overall value from.  Within that, we
6985      ignore the POS lowest bits, etc.  */
6986   enum machine_mode is_mode = GET_MODE (inner);
6987   enum machine_mode inner_mode;
6988   enum machine_mode wanted_inner_mode;
6989   enum machine_mode wanted_inner_reg_mode = word_mode;
6990   enum machine_mode pos_mode = word_mode;
6991   enum machine_mode extraction_mode = word_mode;
6992   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6993   rtx new_rtx = 0;
6994   rtx orig_pos_rtx = pos_rtx;
6995   HOST_WIDE_INT orig_pos;
6996
6997   if (pos_rtx && CONST_INT_P (pos_rtx))
6998     pos = INTVAL (pos_rtx), pos_rtx = 0;
6999
7000   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7001     {
7002       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7003          consider just the QI as the memory to extract from.
7004          The subreg adds or removes high bits; its mode is
7005          irrelevant to the meaning of this extraction,
7006          since POS and LEN count from the lsb.  */
7007       if (MEM_P (SUBREG_REG (inner)))
7008         is_mode = GET_MODE (SUBREG_REG (inner));
7009       inner = SUBREG_REG (inner);
7010     }
7011   else if (GET_CODE (inner) == ASHIFT
7012            && CONST_INT_P (XEXP (inner, 1))
7013            && pos_rtx == 0 && pos == 0
7014            && len > UINTVAL (XEXP (inner, 1)))
7015     {
7016       /* We're extracting the least significant bits of an rtx
7017          (ashift X (const_int C)), where LEN > C.  Extract the
7018          least significant (LEN - C) bits of X, giving an rtx
7019          whose mode is MODE, then shift it left C times.  */
7020       new_rtx = make_extraction (mode, XEXP (inner, 0),
7021                              0, 0, len - INTVAL (XEXP (inner, 1)),
7022                              unsignedp, in_dest, in_compare);
7023       if (new_rtx != 0)
7024         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7025     }
7026   else if (GET_CODE (inner) == TRUNCATE)
7027     inner = XEXP (inner, 0);
7028
7029   inner_mode = GET_MODE (inner);
7030
7031   /* See if this can be done without an extraction.  We never can if the
7032      width of the field is not the same as that of some integer mode. For
7033      registers, we can only avoid the extraction if the position is at the
7034      low-order bit and this is either not in the destination or we have the
7035      appropriate STRICT_LOW_PART operation available.
7036
7037      For MEM, we can avoid an extract if the field starts on an appropriate
7038      boundary and we can change the mode of the memory reference.  */
7039
7040   if (tmode != BLKmode
7041       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7042            && !MEM_P (inner)
7043            && (inner_mode == tmode
7044                || !REG_P (inner)
7045                || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7046                || reg_truncated_to_mode (tmode, inner))
7047            && (! in_dest
7048                || (REG_P (inner)
7049                    && have_insn_for (STRICT_LOW_PART, tmode))))
7050           || (MEM_P (inner) && pos_rtx == 0
7051               && (pos
7052                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7053                      : BITS_PER_UNIT)) == 0
7054               /* We can't do this if we are widening INNER_MODE (it
7055                  may not be aligned, for one thing).  */
7056               && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7057               && (inner_mode == tmode
7058                   || (! mode_dependent_address_p (XEXP (inner, 0),
7059                                                   MEM_ADDR_SPACE (inner))
7060                       && ! MEM_VOLATILE_P (inner))))))
7061     {
7062       /* If INNER is a MEM, make a new MEM that encompasses just the desired
7063          field.  If the original and current mode are the same, we need not
7064          adjust the offset.  Otherwise, we do if bytes big endian.
7065
7066          If INNER is not a MEM, get a piece consisting of just the field
7067          of interest (in this case POS % BITS_PER_WORD must be 0).  */
7068
7069       if (MEM_P (inner))
7070         {
7071           HOST_WIDE_INT offset;
7072
7073           /* POS counts from lsb, but make OFFSET count in memory order.  */
7074           if (BYTES_BIG_ENDIAN)
7075             offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7076           else
7077             offset = pos / BITS_PER_UNIT;
7078
7079           new_rtx = adjust_address_nv (inner, tmode, offset);
7080         }
7081       else if (REG_P (inner))
7082         {
7083           if (tmode != inner_mode)
7084             {
7085               /* We can't call gen_lowpart in a DEST since we
7086                  always want a SUBREG (see below) and it would sometimes
7087                  return a new hard register.  */
7088               if (pos || in_dest)
7089                 {
7090                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7091
7092                   if (WORDS_BIG_ENDIAN
7093                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7094                     final_word = ((GET_MODE_SIZE (inner_mode)
7095                                    - GET_MODE_SIZE (tmode))
7096                                   / UNITS_PER_WORD) - final_word;
7097
7098                   final_word *= UNITS_PER_WORD;
7099                   if (BYTES_BIG_ENDIAN &&
7100                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7101                     final_word += (GET_MODE_SIZE (inner_mode)
7102                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7103
7104                   /* Avoid creating invalid subregs, for example when
7105                      simplifying (x>>32)&255.  */
7106                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
7107                     return NULL_RTX;
7108
7109                   new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7110                 }
7111               else
7112                 new_rtx = gen_lowpart (tmode, inner);
7113             }
7114           else
7115             new_rtx = inner;
7116         }
7117       else
7118         new_rtx = force_to_mode (inner, tmode,
7119                              len >= HOST_BITS_PER_WIDE_INT
7120                              ? ~(unsigned HOST_WIDE_INT) 0
7121                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7122                              0);
7123
7124       /* If this extraction is going into the destination of a SET,
7125          make a STRICT_LOW_PART unless we made a MEM.  */
7126
7127       if (in_dest)
7128         return (MEM_P (new_rtx) ? new_rtx
7129                 : (GET_CODE (new_rtx) != SUBREG
7130                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
7131                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7132
7133       if (mode == tmode)
7134         return new_rtx;
7135
7136       if (CONST_SCALAR_INT_P (new_rtx))
7137         return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7138                                          mode, new_rtx, tmode);
7139
7140       /* If we know that no extraneous bits are set, and that the high
7141          bit is not set, convert the extraction to the cheaper of
7142          sign and zero extension, that are equivalent in these cases.  */
7143       if (flag_expensive_optimizations
7144           && (HWI_COMPUTABLE_MODE_P (tmode)
7145               && ((nonzero_bits (new_rtx, tmode)
7146                    & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7147                   == 0)))
7148         {
7149           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7150           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7151
7152           /* Prefer ZERO_EXTENSION, since it gives more information to
7153              backends.  */
7154           if (set_src_cost (temp, optimize_this_for_speed_p)
7155               <= set_src_cost (temp1, optimize_this_for_speed_p))
7156             return temp;
7157           return temp1;
7158         }
7159
7160       /* Otherwise, sign- or zero-extend unless we already are in the
7161          proper mode.  */
7162
7163       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7164                              mode, new_rtx));
7165     }
7166
7167   /* Unless this is a COMPARE or we have a funny memory reference,
7168      don't do anything with zero-extending field extracts starting at
7169      the low-order bit since they are simple AND operations.  */
7170   if (pos_rtx == 0 && pos == 0 && ! in_dest
7171       && ! in_compare && unsignedp)
7172     return 0;
7173
7174   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7175      if the position is not a constant and the length is not 1.  In all
7176      other cases, we would only be going outside our object in cases when
7177      an original shift would have been undefined.  */
7178   if (MEM_P (inner)
7179       && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7180           || (pos_rtx != 0 && len != 1)))
7181     return 0;
7182
7183   enum extraction_pattern pattern = (in_dest ? EP_insv
7184                                      : unsignedp ? EP_extzv : EP_extv);
7185
7186   /* If INNER is not from memory, we want it to have the mode of a register
7187      extraction pattern's structure operand, or word_mode if there is no
7188      such pattern.  The same applies to extraction_mode and pos_mode
7189      and their respective operands.
7190
7191      For memory, assume that the desired extraction_mode and pos_mode
7192      are the same as for a register operation, since at present we don't
7193      have named patterns for aligned memory structures.  */
7194   struct extraction_insn insn;
7195   if (get_best_reg_extraction_insn (&insn, pattern,
7196                                     GET_MODE_BITSIZE (inner_mode), mode))
7197     {
7198       wanted_inner_reg_mode = insn.struct_mode;
7199       pos_mode = insn.pos_mode;
7200       extraction_mode = insn.field_mode;
7201     }
7202
7203   /* Never narrow an object, since that might not be safe.  */
7204
7205   if (mode != VOIDmode
7206       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7207     extraction_mode = mode;
7208
7209   if (!MEM_P (inner))
7210     wanted_inner_mode = wanted_inner_reg_mode;
7211   else
7212     {
7213       /* Be careful not to go beyond the extracted object and maintain the
7214          natural alignment of the memory.  */
7215       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7216       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7217              > GET_MODE_BITSIZE (wanted_inner_mode))
7218         {
7219           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7220           gcc_assert (wanted_inner_mode != VOIDmode);
7221         }
7222     }
7223
7224   orig_pos = pos;
7225
7226   if (BITS_BIG_ENDIAN)
7227     {
7228       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7229          BITS_BIG_ENDIAN style.  If position is constant, compute new
7230          position.  Otherwise, build subtraction.
7231          Note that POS is relative to the mode of the original argument.
7232          If it's a MEM we need to recompute POS relative to that.
7233          However, if we're extracting from (or inserting into) a register,
7234          we want to recompute POS relative to wanted_inner_mode.  */
7235       int width = (MEM_P (inner)
7236                    ? GET_MODE_BITSIZE (is_mode)
7237                    : GET_MODE_BITSIZE (wanted_inner_mode));
7238
7239       if (pos_rtx == 0)
7240         pos = width - len - pos;
7241       else
7242         pos_rtx
7243           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7244       /* POS may be less than 0 now, but we check for that below.
7245          Note that it can only be less than 0 if !MEM_P (inner).  */
7246     }
7247
7248   /* If INNER has a wider mode, and this is a constant extraction, try to
7249      make it smaller and adjust the byte to point to the byte containing
7250      the value.  */
7251   if (wanted_inner_mode != VOIDmode
7252       && inner_mode != wanted_inner_mode
7253       && ! pos_rtx
7254       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7255       && MEM_P (inner)
7256       && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7257       && ! MEM_VOLATILE_P (inner))
7258     {
7259       int offset = 0;
7260
7261       /* The computations below will be correct if the machine is big
7262          endian in both bits and bytes or little endian in bits and bytes.
7263          If it is mixed, we must adjust.  */
7264
7265       /* If bytes are big endian and we had a paradoxical SUBREG, we must
7266          adjust OFFSET to compensate.  */
7267       if (BYTES_BIG_ENDIAN
7268           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7269         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7270
7271       /* We can now move to the desired byte.  */
7272       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7273                 * GET_MODE_SIZE (wanted_inner_mode);
7274       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7275
7276       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7277           && is_mode != wanted_inner_mode)
7278         offset = (GET_MODE_SIZE (is_mode)
7279                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
7280
7281       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7282     }
7283
7284   /* If INNER is not memory, get it into the proper mode.  If we are changing
7285      its mode, POS must be a constant and smaller than the size of the new
7286      mode.  */
7287   else if (!MEM_P (inner))
7288     {
7289       /* On the LHS, don't create paradoxical subregs implicitely truncating
7290          the register unless TRULY_NOOP_TRUNCATION.  */
7291       if (in_dest
7292           && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7293                                              wanted_inner_mode))
7294         return NULL_RTX;
7295
7296       if (GET_MODE (inner) != wanted_inner_mode
7297           && (pos_rtx != 0
7298               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7299         return NULL_RTX;
7300
7301       if (orig_pos < 0)
7302         return NULL_RTX;
7303
7304       inner = force_to_mode (inner, wanted_inner_mode,
7305                              pos_rtx
7306                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7307                              ? ~(unsigned HOST_WIDE_INT) 0
7308                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7309                                 << orig_pos),
7310                              0);
7311     }
7312
7313   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7314      have to zero extend.  Otherwise, we can just use a SUBREG.  */
7315   if (pos_rtx != 0
7316       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7317     {
7318       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7319
7320       /* If we know that no extraneous bits are set, and that the high
7321          bit is not set, convert extraction to cheaper one - either
7322          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7323          cases.  */
7324       if (flag_expensive_optimizations
7325           && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7326               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7327                    & ~(((unsigned HOST_WIDE_INT)
7328                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7329                        >> 1))
7330                   == 0)))
7331         {
7332           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7333
7334           /* Prefer ZERO_EXTENSION, since it gives more information to
7335              backends.  */
7336           if (set_src_cost (temp1, optimize_this_for_speed_p)
7337               < set_src_cost (temp, optimize_this_for_speed_p))
7338             temp = temp1;
7339         }
7340       pos_rtx = temp;
7341     }
7342
7343   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7344      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7345      be a CONST_INT.  */
7346   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7347     pos_rtx = orig_pos_rtx;
7348
7349   else if (pos_rtx == 0)
7350     pos_rtx = GEN_INT (pos);
7351
7352   /* Make the required operation.  See if we can use existing rtx.  */
7353   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7354                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7355   if (! in_dest)
7356     new_rtx = gen_lowpart (mode, new_rtx);
7357
7358   return new_rtx;
7359 }
7360 \f
7361 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7362    with any other operations in X.  Return X without that shift if so.  */
7363
7364 static rtx
7365 extract_left_shift (rtx x, int count)
7366 {
7367   enum rtx_code code = GET_CODE (x);
7368   enum machine_mode mode = GET_MODE (x);
7369   rtx tem;
7370
7371   switch (code)
7372     {
7373     case ASHIFT:
7374       /* This is the shift itself.  If it is wide enough, we will return
7375          either the value being shifted if the shift count is equal to
7376          COUNT or a shift for the difference.  */
7377       if (CONST_INT_P (XEXP (x, 1))
7378           && INTVAL (XEXP (x, 1)) >= count)
7379         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7380                                      INTVAL (XEXP (x, 1)) - count);
7381       break;
7382
7383     case NEG:  case NOT:
7384       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7385         return simplify_gen_unary (code, mode, tem, mode);
7386
7387       break;
7388
7389     case PLUS:  case IOR:  case XOR:  case AND:
7390       /* If we can safely shift this constant and we find the inner shift,
7391          make a new operation.  */
7392       if (CONST_INT_P (XEXP (x, 1))
7393           && (UINTVAL (XEXP (x, 1))
7394               & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7395           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7396         return simplify_gen_binary (code, mode, tem,
7397                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7398
7399       break;
7400
7401     default:
7402       break;
7403     }
7404
7405   return 0;
7406 }
7407 \f
7408 /* Look at the expression rooted at X.  Look for expressions
7409    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7410    Form these expressions.
7411
7412    Return the new rtx, usually just X.
7413
7414    Also, for machines like the VAX that don't have logical shift insns,
7415    try to convert logical to arithmetic shift operations in cases where
7416    they are equivalent.  This undoes the canonicalizations to logical
7417    shifts done elsewhere.
7418
7419    We try, as much as possible, to re-use rtl expressions to save memory.
7420
7421    IN_CODE says what kind of expression we are processing.  Normally, it is
7422    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
7423    being kludges), it is MEM.  When processing the arguments of a comparison
7424    or a COMPARE against zero, it is COMPARE.  */
7425
7426 rtx
7427 make_compound_operation (rtx x, enum rtx_code in_code)
7428 {
7429   enum rtx_code code = GET_CODE (x);
7430   enum machine_mode mode = GET_MODE (x);
7431   int mode_width = GET_MODE_PRECISION (mode);
7432   rtx rhs, lhs;
7433   enum rtx_code next_code;
7434   int i, j;
7435   rtx new_rtx = 0;
7436   rtx tem;
7437   const char *fmt;
7438
7439   /* Select the code to be used in recursive calls.  Once we are inside an
7440      address, we stay there.  If we have a comparison, set to COMPARE,
7441      but once inside, go back to our default of SET.  */
7442
7443   next_code = (code == MEM ? MEM
7444                : ((code == PLUS || code == MINUS)
7445                   && SCALAR_INT_MODE_P (mode)) ? MEM
7446                : ((code == COMPARE || COMPARISON_P (x))
7447                   && XEXP (x, 1) == const0_rtx) ? COMPARE
7448                : in_code == COMPARE ? SET : in_code);
7449
7450   /* Process depending on the code of this operation.  If NEW is set
7451      nonzero, it will be returned.  */
7452
7453   switch (code)
7454     {
7455     case ASHIFT:
7456       /* Convert shifts by constants into multiplications if inside
7457          an address.  */
7458       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7459           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7460           && INTVAL (XEXP (x, 1)) >= 0
7461           && SCALAR_INT_MODE_P (mode))
7462         {
7463           HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7464           HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7465
7466           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7467           if (GET_CODE (new_rtx) == NEG)
7468             {
7469               new_rtx = XEXP (new_rtx, 0);
7470               multval = -multval;
7471             }
7472           multval = trunc_int_for_mode (multval, mode);
7473           new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7474         }
7475       break;
7476
7477     case PLUS:
7478       lhs = XEXP (x, 0);
7479       rhs = XEXP (x, 1);
7480       lhs = make_compound_operation (lhs, next_code);
7481       rhs = make_compound_operation (rhs, next_code);
7482       if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7483           && SCALAR_INT_MODE_P (mode))
7484         {
7485           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7486                                      XEXP (lhs, 1));
7487           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7488         }
7489       else if (GET_CODE (lhs) == MULT
7490                && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7491         {
7492           tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7493                                      simplify_gen_unary (NEG, mode,
7494                                                          XEXP (lhs, 1),
7495                                                          mode));
7496           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7497         }
7498       else
7499         {
7500           SUBST (XEXP (x, 0), lhs);
7501           SUBST (XEXP (x, 1), rhs);
7502           goto maybe_swap;
7503         }
7504       x = gen_lowpart (mode, new_rtx);
7505       goto maybe_swap;
7506
7507     case MINUS:
7508       lhs = XEXP (x, 0);
7509       rhs = XEXP (x, 1);
7510       lhs = make_compound_operation (lhs, next_code);
7511       rhs = make_compound_operation (rhs, next_code);
7512       if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7513           && SCALAR_INT_MODE_P (mode))
7514         {
7515           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7516                                      XEXP (rhs, 1));
7517           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7518         }
7519       else if (GET_CODE (rhs) == MULT
7520                && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7521         {
7522           tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7523                                      simplify_gen_unary (NEG, mode,
7524                                                          XEXP (rhs, 1),
7525                                                          mode));
7526           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7527         }
7528       else
7529         {
7530           SUBST (XEXP (x, 0), lhs);
7531           SUBST (XEXP (x, 1), rhs);
7532           return x;
7533         }
7534       return gen_lowpart (mode, new_rtx);
7535
7536     case AND:
7537       /* If the second operand is not a constant, we can't do anything
7538          with it.  */
7539       if (!CONST_INT_P (XEXP (x, 1)))
7540         break;
7541
7542       /* If the constant is a power of two minus one and the first operand
7543          is a logical right shift, make an extraction.  */
7544       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7545           && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7546         {
7547           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7548           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7549                                  0, in_code == COMPARE);
7550         }
7551
7552       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
7553       else if (GET_CODE (XEXP (x, 0)) == SUBREG
7554                && subreg_lowpart_p (XEXP (x, 0))
7555                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7556                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7557         {
7558           new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7559                                          next_code);
7560           new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7561                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7562                                  0, in_code == COMPARE);
7563         }
7564       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
7565       else if ((GET_CODE (XEXP (x, 0)) == XOR
7566                 || GET_CODE (XEXP (x, 0)) == IOR)
7567                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7568                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7569                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7570         {
7571           /* Apply the distributive law, and then try to make extractions.  */
7572           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7573                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7574                                              XEXP (x, 1)),
7575                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7576                                              XEXP (x, 1)));
7577           new_rtx = make_compound_operation (new_rtx, in_code);
7578         }
7579
7580       /* If we are have (and (rotate X C) M) and C is larger than the number
7581          of bits in M, this is an extraction.  */
7582
7583       else if (GET_CODE (XEXP (x, 0)) == ROTATE
7584                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7585                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7586                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7587         {
7588           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7589           new_rtx = make_extraction (mode, new_rtx,
7590                                  (GET_MODE_PRECISION (mode)
7591                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
7592                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
7593         }
7594
7595       /* On machines without logical shifts, if the operand of the AND is
7596          a logical shift and our mask turns off all the propagated sign
7597          bits, we can replace the logical shift with an arithmetic shift.  */
7598       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7599                && !have_insn_for (LSHIFTRT, mode)
7600                && have_insn_for (ASHIFTRT, mode)
7601                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7602                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7603                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7604                && mode_width <= HOST_BITS_PER_WIDE_INT)
7605         {
7606           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7607
7608           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7609           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7610             SUBST (XEXP (x, 0),
7611                    gen_rtx_ASHIFTRT (mode,
7612                                      make_compound_operation
7613                                      (XEXP (XEXP (x, 0), 0), next_code),
7614                                      XEXP (XEXP (x, 0), 1)));
7615         }
7616
7617       /* If the constant is one less than a power of two, this might be
7618          representable by an extraction even if no shift is present.
7619          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7620          we are in a COMPARE.  */
7621       else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7622         new_rtx = make_extraction (mode,
7623                                make_compound_operation (XEXP (x, 0),
7624                                                         next_code),
7625                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7626
7627       /* If we are in a comparison and this is an AND with a power of two,
7628          convert this into the appropriate bit extract.  */
7629       else if (in_code == COMPARE
7630                && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7631         new_rtx = make_extraction (mode,
7632                                make_compound_operation (XEXP (x, 0),
7633                                                         next_code),
7634                                i, NULL_RTX, 1, 1, 0, 1);
7635
7636       break;
7637
7638     case LSHIFTRT:
7639       /* If the sign bit is known to be zero, replace this with an
7640          arithmetic shift.  */
7641       if (have_insn_for (ASHIFTRT, mode)
7642           && ! have_insn_for (LSHIFTRT, mode)
7643           && mode_width <= HOST_BITS_PER_WIDE_INT
7644           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7645         {
7646           new_rtx = gen_rtx_ASHIFTRT (mode,
7647                                   make_compound_operation (XEXP (x, 0),
7648                                                            next_code),
7649                                   XEXP (x, 1));
7650           break;
7651         }
7652
7653       /* ... fall through ...  */
7654
7655     case ASHIFTRT:
7656       lhs = XEXP (x, 0);
7657       rhs = XEXP (x, 1);
7658
7659       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7660          this is a SIGN_EXTRACT.  */
7661       if (CONST_INT_P (rhs)
7662           && GET_CODE (lhs) == ASHIFT
7663           && CONST_INT_P (XEXP (lhs, 1))
7664           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7665           && INTVAL (XEXP (lhs, 1)) >= 0
7666           && INTVAL (rhs) < mode_width)
7667         {
7668           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7669           new_rtx = make_extraction (mode, new_rtx,
7670                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7671                                  NULL_RTX, mode_width - INTVAL (rhs),
7672                                  code == LSHIFTRT, 0, in_code == COMPARE);
7673           break;
7674         }
7675
7676       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7677          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7678          also do this for some cases of SIGN_EXTRACT, but it doesn't
7679          seem worth the effort; the case checked for occurs on Alpha.  */
7680
7681       if (!OBJECT_P (lhs)
7682           && ! (GET_CODE (lhs) == SUBREG
7683                 && (OBJECT_P (SUBREG_REG (lhs))))
7684           && CONST_INT_P (rhs)
7685           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7686           && INTVAL (rhs) < mode_width
7687           && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7688         new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7689                                0, NULL_RTX, mode_width - INTVAL (rhs),
7690                                code == LSHIFTRT, 0, in_code == COMPARE);
7691
7692       break;
7693
7694     case SUBREG:
7695       /* Call ourselves recursively on the inner expression.  If we are
7696          narrowing the object and it has a different RTL code from
7697          what it originally did, do this SUBREG as a force_to_mode.  */
7698       {
7699         rtx inner = SUBREG_REG (x), simplified;
7700
7701         tem = make_compound_operation (inner, in_code);
7702
7703         simplified
7704           = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7705         if (simplified)
7706           tem = simplified;
7707
7708         if (GET_CODE (tem) != GET_CODE (inner)
7709             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7710             && subreg_lowpart_p (x))
7711           {
7712             rtx newer
7713               = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7714
7715             /* If we have something other than a SUBREG, we might have
7716                done an expansion, so rerun ourselves.  */
7717             if (GET_CODE (newer) != SUBREG)
7718               newer = make_compound_operation (newer, in_code);
7719
7720             /* force_to_mode can expand compounds.  If it just re-expanded the
7721                compound, use gen_lowpart to convert to the desired mode.  */
7722             if (rtx_equal_p (newer, x)
7723                 /* Likewise if it re-expanded the compound only partially.
7724                    This happens for SUBREG of ZERO_EXTRACT if they extract
7725                    the same number of bits.  */
7726                 || (GET_CODE (newer) == SUBREG
7727                     && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7728                         || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7729                     && GET_CODE (inner) == AND
7730                     && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7731               return gen_lowpart (GET_MODE (x), tem);
7732
7733             return newer;
7734           }
7735
7736         if (simplified)
7737           return tem;
7738       }
7739       break;
7740
7741     default:
7742       break;
7743     }
7744
7745   if (new_rtx)
7746     {
7747       x = gen_lowpart (mode, new_rtx);
7748       code = GET_CODE (x);
7749     }
7750
7751   /* Now recursively process each operand of this operation.  We need to
7752      handle ZERO_EXTEND specially so that we don't lose track of the
7753      inner mode.  */
7754   if (GET_CODE (x) == ZERO_EXTEND)
7755     {
7756       new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7757       tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7758                                             new_rtx, GET_MODE (XEXP (x, 0)));
7759       if (tem)
7760         return tem;
7761       SUBST (XEXP (x, 0), new_rtx);
7762       return x;
7763     }
7764
7765   fmt = GET_RTX_FORMAT (code);
7766   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7767     if (fmt[i] == 'e')
7768       {
7769         new_rtx = make_compound_operation (XEXP (x, i), next_code);
7770         SUBST (XEXP (x, i), new_rtx);
7771       }
7772     else if (fmt[i] == 'E')
7773       for (j = 0; j < XVECLEN (x, i); j++)
7774         {
7775           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7776           SUBST (XVECEXP (x, i, j), new_rtx);
7777         }
7778
7779  maybe_swap:
7780   /* If this is a commutative operation, the changes to the operands
7781      may have made it noncanonical.  */
7782   if (COMMUTATIVE_ARITH_P (x)
7783       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7784     {
7785       tem = XEXP (x, 0);
7786       SUBST (XEXP (x, 0), XEXP (x, 1));
7787       SUBST (XEXP (x, 1), tem);
7788     }
7789
7790   return x;
7791 }
7792 \f
7793 /* Given M see if it is a value that would select a field of bits
7794    within an item, but not the entire word.  Return -1 if not.
7795    Otherwise, return the starting position of the field, where 0 is the
7796    low-order bit.
7797
7798    *PLEN is set to the length of the field.  */
7799
7800 static int
7801 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7802 {
7803   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7804   int pos = m ? ctz_hwi (m) : -1;
7805   int len = 0;
7806
7807   if (pos >= 0)
7808     /* Now shift off the low-order zero bits and see if we have a
7809        power of two minus 1.  */
7810     len = exact_log2 ((m >> pos) + 1);
7811
7812   if (len <= 0)
7813     pos = -1;
7814
7815   *plen = len;
7816   return pos;
7817 }
7818 \f
7819 /* If X refers to a register that equals REG in value, replace these
7820    references with REG.  */
7821 static rtx
7822 canon_reg_for_combine (rtx x, rtx reg)
7823 {
7824   rtx op0, op1, op2;
7825   const char *fmt;
7826   int i;
7827   bool copied;
7828
7829   enum rtx_code code = GET_CODE (x);
7830   switch (GET_RTX_CLASS (code))
7831     {
7832     case RTX_UNARY:
7833       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7834       if (op0 != XEXP (x, 0))
7835         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7836                                    GET_MODE (reg));
7837       break;
7838
7839     case RTX_BIN_ARITH:
7840     case RTX_COMM_ARITH:
7841       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7842       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7843       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7844         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7845       break;
7846
7847     case RTX_COMPARE:
7848     case RTX_COMM_COMPARE:
7849       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7850       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7851       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7852         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7853                                         GET_MODE (op0), op0, op1);
7854       break;
7855
7856     case RTX_TERNARY:
7857     case RTX_BITFIELD_OPS:
7858       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7859       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7860       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7861       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7862         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7863                                      GET_MODE (op0), op0, op1, op2);
7864
7865     case RTX_OBJ:
7866       if (REG_P (x))
7867         {
7868           if (rtx_equal_p (get_last_value (reg), x)
7869               || rtx_equal_p (reg, get_last_value (x)))
7870             return reg;
7871           else
7872             break;
7873         }
7874
7875       /* fall through */
7876
7877     default:
7878       fmt = GET_RTX_FORMAT (code);
7879       copied = false;
7880       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7881         if (fmt[i] == 'e')
7882           {
7883             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7884             if (op != XEXP (x, i))
7885               {
7886                 if (!copied)
7887                   {
7888                     copied = true;
7889                     x = copy_rtx (x);
7890                   }
7891                 XEXP (x, i) = op;
7892               }
7893           }
7894         else if (fmt[i] == 'E')
7895           {
7896             int j;
7897             for (j = 0; j < XVECLEN (x, i); j++)
7898               {
7899                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7900                 if (op != XVECEXP (x, i, j))
7901                   {
7902                     if (!copied)
7903                       {
7904                         copied = true;
7905                         x = copy_rtx (x);
7906                       }
7907                     XVECEXP (x, i, j) = op;
7908                   }
7909               }
7910           }
7911
7912       break;
7913     }
7914
7915   return x;
7916 }
7917
7918 /* Return X converted to MODE.  If the value is already truncated to
7919    MODE we can just return a subreg even though in the general case we
7920    would need an explicit truncation.  */
7921
7922 static rtx
7923 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7924 {
7925   if (!CONST_INT_P (x)
7926       && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7927       && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
7928       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7929     {
7930       /* Bit-cast X into an integer mode.  */
7931       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7932         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7933       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7934                               x, GET_MODE (x));
7935     }
7936
7937   return gen_lowpart (mode, x);
7938 }
7939
7940 /* See if X can be simplified knowing that we will only refer to it in
7941    MODE and will only refer to those bits that are nonzero in MASK.
7942    If other bits are being computed or if masking operations are done
7943    that select a superset of the bits in MASK, they can sometimes be
7944    ignored.
7945
7946    Return a possibly simplified expression, but always convert X to
7947    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
7948
7949    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7950    are all off in X.  This is used when X will be complemented, by either
7951    NOT, NEG, or XOR.  */
7952
7953 static rtx
7954 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7955                int just_select)
7956 {
7957   enum rtx_code code = GET_CODE (x);
7958   int next_select = just_select || code == XOR || code == NOT || code == NEG;
7959   enum machine_mode op_mode;
7960   unsigned HOST_WIDE_INT fuller_mask, nonzero;
7961   rtx op0, op1, temp;
7962
7963   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
7964      code below will do the wrong thing since the mode of such an
7965      expression is VOIDmode.
7966
7967      Also do nothing if X is a CLOBBER; this can happen if X was
7968      the return value from a call to gen_lowpart.  */
7969   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7970     return x;
7971
7972   /* We want to perform the operation is its present mode unless we know
7973      that the operation is valid in MODE, in which case we do the operation
7974      in MODE.  */
7975   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7976               && have_insn_for (code, mode))
7977              ? mode : GET_MODE (x));
7978
7979   /* It is not valid to do a right-shift in a narrower mode
7980      than the one it came in with.  */
7981   if ((code == LSHIFTRT || code == ASHIFTRT)
7982       && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
7983     op_mode = GET_MODE (x);
7984
7985   /* Truncate MASK to fit OP_MODE.  */
7986   if (op_mode)
7987     mask &= GET_MODE_MASK (op_mode);
7988
7989   /* When we have an arithmetic operation, or a shift whose count we
7990      do not know, we need to assume that all bits up to the highest-order
7991      bit in MASK will be needed.  This is how we form such a mask.  */
7992   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7993     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7994   else
7995     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7996                    - 1);
7997
7998   /* Determine what bits of X are guaranteed to be (non)zero.  */
7999   nonzero = nonzero_bits (x, mode);
8000
8001   /* If none of the bits in X are needed, return a zero.  */
8002   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8003     x = const0_rtx;
8004
8005   /* If X is a CONST_INT, return a new one.  Do this here since the
8006      test below will fail.  */
8007   if (CONST_INT_P (x))
8008     {
8009       if (SCALAR_INT_MODE_P (mode))
8010         return gen_int_mode (INTVAL (x) & mask, mode);
8011       else
8012         {
8013           x = GEN_INT (INTVAL (x) & mask);
8014           return gen_lowpart_common (mode, x);
8015         }
8016     }
8017
8018   /* If X is narrower than MODE and we want all the bits in X's mode, just
8019      get X in the proper mode.  */
8020   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8021       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8022     return gen_lowpart (mode, x);
8023
8024   /* We can ignore the effect of a SUBREG if it narrows the mode or
8025      if the constant masks to zero all the bits the mode doesn't have.  */
8026   if (GET_CODE (x) == SUBREG
8027       && subreg_lowpart_p (x)
8028       && ((GET_MODE_SIZE (GET_MODE (x))
8029            < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8030           || (0 == (mask
8031                     & GET_MODE_MASK (GET_MODE (x))
8032                     & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8033     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8034
8035   /* The arithmetic simplifications here only work for scalar integer modes.  */
8036   if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8037     return gen_lowpart_or_truncate (mode, x);
8038
8039   switch (code)
8040     {
8041     case CLOBBER:
8042       /* If X is a (clobber (const_int)), return it since we know we are
8043          generating something that won't match.  */
8044       return x;
8045
8046     case SIGN_EXTEND:
8047     case ZERO_EXTEND:
8048     case ZERO_EXTRACT:
8049     case SIGN_EXTRACT:
8050       x = expand_compound_operation (x);
8051       if (GET_CODE (x) != code)
8052         return force_to_mode (x, mode, mask, next_select);
8053       break;
8054
8055     case TRUNCATE:
8056       /* Similarly for a truncate.  */
8057       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8058
8059     case AND:
8060       /* If this is an AND with a constant, convert it into an AND
8061          whose constant is the AND of that constant with MASK.  If it
8062          remains an AND of MASK, delete it since it is redundant.  */
8063
8064       if (CONST_INT_P (XEXP (x, 1)))
8065         {
8066           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8067                                       mask & INTVAL (XEXP (x, 1)));
8068
8069           /* If X is still an AND, see if it is an AND with a mask that
8070              is just some low-order bits.  If so, and it is MASK, we don't
8071              need it.  */
8072
8073           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8074               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8075                   == mask))
8076             x = XEXP (x, 0);
8077
8078           /* If it remains an AND, try making another AND with the bits
8079              in the mode mask that aren't in MASK turned on.  If the
8080              constant in the AND is wide enough, this might make a
8081              cheaper constant.  */
8082
8083           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8084               && GET_MODE_MASK (GET_MODE (x)) != mask
8085               && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8086             {
8087               unsigned HOST_WIDE_INT cval
8088                 = UINTVAL (XEXP (x, 1))
8089                   | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8090               int width = GET_MODE_PRECISION (GET_MODE (x));
8091               rtx y;
8092
8093               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8094                  number, sign extend it.  */
8095               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8096                   && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8097                 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8098
8099               y = simplify_gen_binary (AND, GET_MODE (x),
8100                                        XEXP (x, 0), GEN_INT (cval));
8101               if (set_src_cost (y, optimize_this_for_speed_p)
8102                   < set_src_cost (x, optimize_this_for_speed_p))
8103                 x = y;
8104             }
8105
8106           break;
8107         }
8108
8109       goto binop;
8110
8111     case PLUS:
8112       /* In (and (plus FOO C1) M), if M is a mask that just turns off
8113          low-order bits (as in an alignment operation) and FOO is already
8114          aligned to that boundary, mask C1 to that boundary as well.
8115          This may eliminate that PLUS and, later, the AND.  */
8116
8117       {
8118         unsigned int width = GET_MODE_PRECISION (mode);
8119         unsigned HOST_WIDE_INT smask = mask;
8120
8121         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8122            number, sign extend it.  */
8123
8124         if (width < HOST_BITS_PER_WIDE_INT
8125             && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8126           smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8127
8128         if (CONST_INT_P (XEXP (x, 1))
8129             && exact_log2 (- smask) >= 0
8130             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8131             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8132           return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0),
8133                                                (INTVAL (XEXP (x, 1)) & smask)),
8134                                 mode, smask, next_select);
8135       }
8136
8137       /* ... fall through ...  */
8138
8139     case MULT:
8140       /* For PLUS, MINUS and MULT, we need any bits less significant than the
8141          most significant bit in MASK since carries from those bits will
8142          affect the bits we are interested in.  */
8143       mask = fuller_mask;
8144       goto binop;
8145
8146     case MINUS:
8147       /* If X is (minus C Y) where C's least set bit is larger than any bit
8148          in the mask, then we may replace with (neg Y).  */
8149       if (CONST_INT_P (XEXP (x, 0))
8150           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8151                                         & -INTVAL (XEXP (x, 0))))
8152               > mask))
8153         {
8154           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8155                                   GET_MODE (x));
8156           return force_to_mode (x, mode, mask, next_select);
8157         }
8158
8159       /* Similarly, if C contains every bit in the fuller_mask, then we may
8160          replace with (not Y).  */
8161       if (CONST_INT_P (XEXP (x, 0))
8162           && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8163         {
8164           x = simplify_gen_unary (NOT, GET_MODE (x),
8165                                   XEXP (x, 1), GET_MODE (x));
8166           return force_to_mode (x, mode, mask, next_select);
8167         }
8168
8169       mask = fuller_mask;
8170       goto binop;
8171
8172     case IOR:
8173     case XOR:
8174       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8175          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8176          operation which may be a bitfield extraction.  Ensure that the
8177          constant we form is not wider than the mode of X.  */
8178
8179       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8180           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8181           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8182           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8183           && CONST_INT_P (XEXP (x, 1))
8184           && ((INTVAL (XEXP (XEXP (x, 0), 1))
8185                + floor_log2 (INTVAL (XEXP (x, 1))))
8186               < GET_MODE_PRECISION (GET_MODE (x)))
8187           && (UINTVAL (XEXP (x, 1))
8188               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8189         {
8190           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8191                           << INTVAL (XEXP (XEXP (x, 0), 1)));
8192           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8193                                       XEXP (XEXP (x, 0), 0), temp);
8194           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8195                                    XEXP (XEXP (x, 0), 1));
8196           return force_to_mode (x, mode, mask, next_select);
8197         }
8198
8199     binop:
8200       /* For most binary operations, just propagate into the operation and
8201          change the mode if we have an operation of that mode.  */
8202
8203       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8204       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8205
8206       /* If we ended up truncating both operands, truncate the result of the
8207          operation instead.  */
8208       if (GET_CODE (op0) == TRUNCATE
8209           && GET_CODE (op1) == TRUNCATE)
8210         {
8211           op0 = XEXP (op0, 0);
8212           op1 = XEXP (op1, 0);
8213         }
8214
8215       op0 = gen_lowpart_or_truncate (op_mode, op0);
8216       op1 = gen_lowpart_or_truncate (op_mode, op1);
8217
8218       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8219         x = simplify_gen_binary (code, op_mode, op0, op1);
8220       break;
8221
8222     case ASHIFT:
8223       /* For left shifts, do the same, but just for the first operand.
8224          However, we cannot do anything with shifts where we cannot
8225          guarantee that the counts are smaller than the size of the mode
8226          because such a count will have a different meaning in a
8227          wider mode.  */
8228
8229       if (! (CONST_INT_P (XEXP (x, 1))
8230              && INTVAL (XEXP (x, 1)) >= 0
8231              && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8232           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8233                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8234                     < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8235         break;
8236
8237       /* If the shift count is a constant and we can do arithmetic in
8238          the mode of the shift, refine which bits we need.  Otherwise, use the
8239          conservative form of the mask.  */
8240       if (CONST_INT_P (XEXP (x, 1))
8241           && INTVAL (XEXP (x, 1)) >= 0
8242           && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8243           && HWI_COMPUTABLE_MODE_P (op_mode))
8244         mask >>= INTVAL (XEXP (x, 1));
8245       else
8246         mask = fuller_mask;
8247
8248       op0 = gen_lowpart_or_truncate (op_mode,
8249                                      force_to_mode (XEXP (x, 0), op_mode,
8250                                                     mask, next_select));
8251
8252       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8253         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8254       break;
8255
8256     case LSHIFTRT:
8257       /* Here we can only do something if the shift count is a constant,
8258          this shift constant is valid for the host, and we can do arithmetic
8259          in OP_MODE.  */
8260
8261       if (CONST_INT_P (XEXP (x, 1))
8262           && INTVAL (XEXP (x, 1)) >= 0
8263           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8264           && HWI_COMPUTABLE_MODE_P (op_mode))
8265         {
8266           rtx inner = XEXP (x, 0);
8267           unsigned HOST_WIDE_INT inner_mask;
8268
8269           /* Select the mask of the bits we need for the shift operand.  */
8270           inner_mask = mask << INTVAL (XEXP (x, 1));
8271
8272           /* We can only change the mode of the shift if we can do arithmetic
8273              in the mode of the shift and INNER_MASK is no wider than the
8274              width of X's mode.  */
8275           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8276             op_mode = GET_MODE (x);
8277
8278           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8279
8280           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8281             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8282         }
8283
8284       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8285          shift and AND produces only copies of the sign bit (C2 is one less
8286          than a power of two), we can do this with just a shift.  */
8287
8288       if (GET_CODE (x) == LSHIFTRT
8289           && CONST_INT_P (XEXP (x, 1))
8290           /* The shift puts one of the sign bit copies in the least significant
8291              bit.  */
8292           && ((INTVAL (XEXP (x, 1))
8293                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8294               >= GET_MODE_PRECISION (GET_MODE (x)))
8295           && exact_log2 (mask + 1) >= 0
8296           /* Number of bits left after the shift must be more than the mask
8297              needs.  */
8298           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8299               <= GET_MODE_PRECISION (GET_MODE (x)))
8300           /* Must be more sign bit copies than the mask needs.  */
8301           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8302               >= exact_log2 (mask + 1)))
8303         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8304                                  GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8305                                           - exact_log2 (mask + 1)));
8306
8307       goto shiftrt;
8308
8309     case ASHIFTRT:
8310       /* If we are just looking for the sign bit, we don't need this shift at
8311          all, even if it has a variable count.  */
8312       if (val_signbit_p (GET_MODE (x), mask))
8313         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8314
8315       /* If this is a shift by a constant, get a mask that contains those bits
8316          that are not copies of the sign bit.  We then have two cases:  If
8317          MASK only includes those bits, this can be a logical shift, which may
8318          allow simplifications.  If MASK is a single-bit field not within
8319          those bits, we are requesting a copy of the sign bit and hence can
8320          shift the sign bit to the appropriate location.  */
8321
8322       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8323           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8324         {
8325           int i;
8326
8327           /* If the considered data is wider than HOST_WIDE_INT, we can't
8328              represent a mask for all its bits in a single scalar.
8329              But we only care about the lower bits, so calculate these.  */
8330
8331           if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8332             {
8333               nonzero = ~(unsigned HOST_WIDE_INT) 0;
8334
8335               /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8336                  is the number of bits a full-width mask would have set.
8337                  We need only shift if these are fewer than nonzero can
8338                  hold.  If not, we must keep all bits set in nonzero.  */
8339
8340               if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8341                   < HOST_BITS_PER_WIDE_INT)
8342                 nonzero >>= INTVAL (XEXP (x, 1))
8343                             + HOST_BITS_PER_WIDE_INT
8344                             - GET_MODE_PRECISION (GET_MODE (x)) ;
8345             }
8346           else
8347             {
8348               nonzero = GET_MODE_MASK (GET_MODE (x));
8349               nonzero >>= INTVAL (XEXP (x, 1));
8350             }
8351
8352           if ((mask & ~nonzero) == 0)
8353             {
8354               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8355                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
8356               if (GET_CODE (x) != ASHIFTRT)
8357                 return force_to_mode (x, mode, mask, next_select);
8358             }
8359
8360           else if ((i = exact_log2 (mask)) >= 0)
8361             {
8362               x = simplify_shift_const
8363                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8364                    GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8365
8366               if (GET_CODE (x) != ASHIFTRT)
8367                 return force_to_mode (x, mode, mask, next_select);
8368             }
8369         }
8370
8371       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
8372          even if the shift count isn't a constant.  */
8373       if (mask == 1)
8374         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8375                                  XEXP (x, 0), XEXP (x, 1));
8376
8377     shiftrt:
8378
8379       /* If this is a zero- or sign-extension operation that just affects bits
8380          we don't care about, remove it.  Be sure the call above returned
8381          something that is still a shift.  */
8382
8383       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8384           && CONST_INT_P (XEXP (x, 1))
8385           && INTVAL (XEXP (x, 1)) >= 0
8386           && (INTVAL (XEXP (x, 1))
8387               <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8388           && GET_CODE (XEXP (x, 0)) == ASHIFT
8389           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8390         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8391                               next_select);
8392
8393       break;
8394
8395     case ROTATE:
8396     case ROTATERT:
8397       /* If the shift count is constant and we can do computations
8398          in the mode of X, compute where the bits we care about are.
8399          Otherwise, we can't do anything.  Don't change the mode of
8400          the shift or propagate MODE into the shift, though.  */
8401       if (CONST_INT_P (XEXP (x, 1))
8402           && INTVAL (XEXP (x, 1)) >= 0)
8403         {
8404           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8405                                             GET_MODE (x), GEN_INT (mask),
8406                                             XEXP (x, 1));
8407           if (temp && CONST_INT_P (temp))
8408             SUBST (XEXP (x, 0),
8409                    force_to_mode (XEXP (x, 0), GET_MODE (x),
8410                                   INTVAL (temp), next_select));
8411         }
8412       break;
8413
8414     case NEG:
8415       /* If we just want the low-order bit, the NEG isn't needed since it
8416          won't change the low-order bit.  */
8417       if (mask == 1)
8418         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8419
8420       /* We need any bits less significant than the most significant bit in
8421          MASK since carries from those bits will affect the bits we are
8422          interested in.  */
8423       mask = fuller_mask;
8424       goto unop;
8425
8426     case NOT:
8427       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8428          same as the XOR case above.  Ensure that the constant we form is not
8429          wider than the mode of X.  */
8430
8431       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8432           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8433           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8434           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8435               < GET_MODE_PRECISION (GET_MODE (x)))
8436           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8437         {
8438           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8439                                GET_MODE (x));
8440           temp = simplify_gen_binary (XOR, GET_MODE (x),
8441                                       XEXP (XEXP (x, 0), 0), temp);
8442           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8443                                    temp, XEXP (XEXP (x, 0), 1));
8444
8445           return force_to_mode (x, mode, mask, next_select);
8446         }
8447
8448       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8449          use the full mask inside the NOT.  */
8450       mask = fuller_mask;
8451
8452     unop:
8453       op0 = gen_lowpart_or_truncate (op_mode,
8454                                      force_to_mode (XEXP (x, 0), mode, mask,
8455                                                     next_select));
8456       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8457         x = simplify_gen_unary (code, op_mode, op0, op_mode);
8458       break;
8459
8460     case NE:
8461       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8462          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8463          which is equal to STORE_FLAG_VALUE.  */
8464       if ((mask & ~STORE_FLAG_VALUE) == 0
8465           && XEXP (x, 1) == const0_rtx
8466           && GET_MODE (XEXP (x, 0)) == mode
8467           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8468           && (nonzero_bits (XEXP (x, 0), mode)
8469               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8470         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8471
8472       break;
8473
8474     case IF_THEN_ELSE:
8475       /* We have no way of knowing if the IF_THEN_ELSE can itself be
8476          written in a narrower mode.  We play it safe and do not do so.  */
8477
8478       SUBST (XEXP (x, 1),
8479              gen_lowpart_or_truncate (GET_MODE (x),
8480                                       force_to_mode (XEXP (x, 1), mode,
8481                                                      mask, next_select)));
8482       SUBST (XEXP (x, 2),
8483              gen_lowpart_or_truncate (GET_MODE (x),
8484                                       force_to_mode (XEXP (x, 2), mode,
8485                                                      mask, next_select)));
8486       break;
8487
8488     default:
8489       break;
8490     }
8491
8492   /* Ensure we return a value of the proper mode.  */
8493   return gen_lowpart_or_truncate (mode, x);
8494 }
8495 \f
8496 /* Return nonzero if X is an expression that has one of two values depending on
8497    whether some other value is zero or nonzero.  In that case, we return the
8498    value that is being tested, *PTRUE is set to the value if the rtx being
8499    returned has a nonzero value, and *PFALSE is set to the other alternative.
8500
8501    If we return zero, we set *PTRUE and *PFALSE to X.  */
8502
8503 static rtx
8504 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8505 {
8506   enum machine_mode mode = GET_MODE (x);
8507   enum rtx_code code = GET_CODE (x);
8508   rtx cond0, cond1, true0, true1, false0, false1;
8509   unsigned HOST_WIDE_INT nz;
8510
8511   /* If we are comparing a value against zero, we are done.  */
8512   if ((code == NE || code == EQ)
8513       && XEXP (x, 1) == const0_rtx)
8514     {
8515       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8516       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8517       return XEXP (x, 0);
8518     }
8519
8520   /* If this is a unary operation whose operand has one of two values, apply
8521      our opcode to compute those values.  */
8522   else if (UNARY_P (x)
8523            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8524     {
8525       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8526       *pfalse = simplify_gen_unary (code, mode, false0,
8527                                     GET_MODE (XEXP (x, 0)));
8528       return cond0;
8529     }
8530
8531   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8532      make can't possibly match and would suppress other optimizations.  */
8533   else if (code == COMPARE)
8534     ;
8535
8536   /* If this is a binary operation, see if either side has only one of two
8537      values.  If either one does or if both do and they are conditional on
8538      the same value, compute the new true and false values.  */
8539   else if (BINARY_P (x))
8540     {
8541       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8542       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8543
8544       if ((cond0 != 0 || cond1 != 0)
8545           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8546         {
8547           /* If if_then_else_cond returned zero, then true/false are the
8548              same rtl.  We must copy one of them to prevent invalid rtl
8549              sharing.  */
8550           if (cond0 == 0)
8551             true0 = copy_rtx (true0);
8552           else if (cond1 == 0)
8553             true1 = copy_rtx (true1);
8554
8555           if (COMPARISON_P (x))
8556             {
8557               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8558                                                 true0, true1);
8559               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8560                                                  false0, false1);
8561              }
8562           else
8563             {
8564               *ptrue = simplify_gen_binary (code, mode, true0, true1);
8565               *pfalse = simplify_gen_binary (code, mode, false0, false1);
8566             }
8567
8568           return cond0 ? cond0 : cond1;
8569         }
8570
8571       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8572          operands is zero when the other is nonzero, and vice-versa,
8573          and STORE_FLAG_VALUE is 1 or -1.  */
8574
8575       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8576           && (code == PLUS || code == IOR || code == XOR || code == MINUS
8577               || code == UMAX)
8578           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8579         {
8580           rtx op0 = XEXP (XEXP (x, 0), 1);
8581           rtx op1 = XEXP (XEXP (x, 1), 1);
8582
8583           cond0 = XEXP (XEXP (x, 0), 0);
8584           cond1 = XEXP (XEXP (x, 1), 0);
8585
8586           if (COMPARISON_P (cond0)
8587               && COMPARISON_P (cond1)
8588               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8589                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8590                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8591                   || ((swap_condition (GET_CODE (cond0))
8592                        == reversed_comparison_code (cond1, NULL))
8593                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8594                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8595               && ! side_effects_p (x))
8596             {
8597               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8598               *pfalse = simplify_gen_binary (MULT, mode,
8599                                              (code == MINUS
8600                                               ? simplify_gen_unary (NEG, mode,
8601                                                                     op1, mode)
8602                                               : op1),
8603                                               const_true_rtx);
8604               return cond0;
8605             }
8606         }
8607
8608       /* Similarly for MULT, AND and UMIN, except that for these the result
8609          is always zero.  */
8610       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8611           && (code == MULT || code == AND || code == UMIN)
8612           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8613         {
8614           cond0 = XEXP (XEXP (x, 0), 0);
8615           cond1 = XEXP (XEXP (x, 1), 0);
8616
8617           if (COMPARISON_P (cond0)
8618               && COMPARISON_P (cond1)
8619               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8620                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8621                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8622                   || ((swap_condition (GET_CODE (cond0))
8623                        == reversed_comparison_code (cond1, NULL))
8624                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8625                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8626               && ! side_effects_p (x))
8627             {
8628               *ptrue = *pfalse = const0_rtx;
8629               return cond0;
8630             }
8631         }
8632     }
8633
8634   else if (code == IF_THEN_ELSE)
8635     {
8636       /* If we have IF_THEN_ELSE already, extract the condition and
8637          canonicalize it if it is NE or EQ.  */
8638       cond0 = XEXP (x, 0);
8639       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8640       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8641         return XEXP (cond0, 0);
8642       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8643         {
8644           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8645           return XEXP (cond0, 0);
8646         }
8647       else
8648         return cond0;
8649     }
8650
8651   /* If X is a SUBREG, we can narrow both the true and false values
8652      if the inner expression, if there is a condition.  */
8653   else if (code == SUBREG
8654            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8655                                                &true0, &false0)))
8656     {
8657       true0 = simplify_gen_subreg (mode, true0,
8658                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8659       false0 = simplify_gen_subreg (mode, false0,
8660                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8661       if (true0 && false0)
8662         {
8663           *ptrue = true0;
8664           *pfalse = false0;
8665           return cond0;
8666         }
8667     }
8668
8669   /* If X is a constant, this isn't special and will cause confusions
8670      if we treat it as such.  Likewise if it is equivalent to a constant.  */
8671   else if (CONSTANT_P (x)
8672            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8673     ;
8674
8675   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8676      will be least confusing to the rest of the compiler.  */
8677   else if (mode == BImode)
8678     {
8679       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8680       return x;
8681     }
8682
8683   /* If X is known to be either 0 or -1, those are the true and
8684      false values when testing X.  */
8685   else if (x == constm1_rtx || x == const0_rtx
8686            || (mode != VOIDmode
8687                && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8688     {
8689       *ptrue = constm1_rtx, *pfalse = const0_rtx;
8690       return x;
8691     }
8692
8693   /* Likewise for 0 or a single bit.  */
8694   else if (HWI_COMPUTABLE_MODE_P (mode)
8695            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8696     {
8697       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8698       return x;
8699     }
8700
8701   /* Otherwise fail; show no condition with true and false values the same.  */
8702   *ptrue = *pfalse = x;
8703   return 0;
8704 }
8705 \f
8706 /* Return the value of expression X given the fact that condition COND
8707    is known to be true when applied to REG as its first operand and VAL
8708    as its second.  X is known to not be shared and so can be modified in
8709    place.
8710
8711    We only handle the simplest cases, and specifically those cases that
8712    arise with IF_THEN_ELSE expressions.  */
8713
8714 static rtx
8715 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8716 {
8717   enum rtx_code code = GET_CODE (x);
8718   rtx temp;
8719   const char *fmt;
8720   int i, j;
8721
8722   if (side_effects_p (x))
8723     return x;
8724
8725   /* If either operand of the condition is a floating point value,
8726      then we have to avoid collapsing an EQ comparison.  */
8727   if (cond == EQ
8728       && rtx_equal_p (x, reg)
8729       && ! FLOAT_MODE_P (GET_MODE (x))
8730       && ! FLOAT_MODE_P (GET_MODE (val)))
8731     return val;
8732
8733   if (cond == UNEQ && rtx_equal_p (x, reg))
8734     return val;
8735
8736   /* If X is (abs REG) and we know something about REG's relationship
8737      with zero, we may be able to simplify this.  */
8738
8739   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8740     switch (cond)
8741       {
8742       case GE:  case GT:  case EQ:
8743         return XEXP (x, 0);
8744       case LT:  case LE:
8745         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8746                                    XEXP (x, 0),
8747                                    GET_MODE (XEXP (x, 0)));
8748       default:
8749         break;
8750       }
8751
8752   /* The only other cases we handle are MIN, MAX, and comparisons if the
8753      operands are the same as REG and VAL.  */
8754
8755   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8756     {
8757       if (rtx_equal_p (XEXP (x, 0), val))
8758         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8759
8760       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8761         {
8762           if (COMPARISON_P (x))
8763             {
8764               if (comparison_dominates_p (cond, code))
8765                 return const_true_rtx;
8766
8767               code = reversed_comparison_code (x, NULL);
8768               if (code != UNKNOWN
8769                   && comparison_dominates_p (cond, code))
8770                 return const0_rtx;
8771               else
8772                 return x;
8773             }
8774           else if (code == SMAX || code == SMIN
8775                    || code == UMIN || code == UMAX)
8776             {
8777               int unsignedp = (code == UMIN || code == UMAX);
8778
8779               /* Do not reverse the condition when it is NE or EQ.
8780                  This is because we cannot conclude anything about
8781                  the value of 'SMAX (x, y)' when x is not equal to y,
8782                  but we can when x equals y.  */
8783               if ((code == SMAX || code == UMAX)
8784                   && ! (cond == EQ || cond == NE))
8785                 cond = reverse_condition (cond);
8786
8787               switch (cond)
8788                 {
8789                 case GE:   case GT:
8790                   return unsignedp ? x : XEXP (x, 1);
8791                 case LE:   case LT:
8792                   return unsignedp ? x : XEXP (x, 0);
8793                 case GEU:  case GTU:
8794                   return unsignedp ? XEXP (x, 1) : x;
8795                 case LEU:  case LTU:
8796                   return unsignedp ? XEXP (x, 0) : x;
8797                 default:
8798                   break;
8799                 }
8800             }
8801         }
8802     }
8803   else if (code == SUBREG)
8804     {
8805       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8806       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8807
8808       if (SUBREG_REG (x) != r)
8809         {
8810           /* We must simplify subreg here, before we lose track of the
8811              original inner_mode.  */
8812           new_rtx = simplify_subreg (GET_MODE (x), r,
8813                                  inner_mode, SUBREG_BYTE (x));
8814           if (new_rtx)
8815             return new_rtx;
8816           else
8817             SUBST (SUBREG_REG (x), r);
8818         }
8819
8820       return x;
8821     }
8822   /* We don't have to handle SIGN_EXTEND here, because even in the
8823      case of replacing something with a modeless CONST_INT, a
8824      CONST_INT is already (supposed to be) a valid sign extension for
8825      its narrower mode, which implies it's already properly
8826      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8827      story is different.  */
8828   else if (code == ZERO_EXTEND)
8829     {
8830       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8831       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8832
8833       if (XEXP (x, 0) != r)
8834         {
8835           /* We must simplify the zero_extend here, before we lose
8836              track of the original inner_mode.  */
8837           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8838                                           r, inner_mode);
8839           if (new_rtx)
8840             return new_rtx;
8841           else
8842             SUBST (XEXP (x, 0), r);
8843         }
8844
8845       return x;
8846     }
8847
8848   fmt = GET_RTX_FORMAT (code);
8849   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8850     {
8851       if (fmt[i] == 'e')
8852         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8853       else if (fmt[i] == 'E')
8854         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8855           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8856                                                 cond, reg, val));
8857     }
8858
8859   return x;
8860 }
8861 \f
8862 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8863    assignment as a field assignment.  */
8864
8865 static int
8866 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8867 {
8868   if (x == y || rtx_equal_p (x, y))
8869     return 1;
8870
8871   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8872     return 0;
8873
8874   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8875      Note that all SUBREGs of MEM are paradoxical; otherwise they
8876      would have been rewritten.  */
8877   if (MEM_P (x) && GET_CODE (y) == SUBREG
8878       && MEM_P (SUBREG_REG (y))
8879       && rtx_equal_p (SUBREG_REG (y),
8880                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8881     return 1;
8882
8883   if (MEM_P (y) && GET_CODE (x) == SUBREG
8884       && MEM_P (SUBREG_REG (x))
8885       && rtx_equal_p (SUBREG_REG (x),
8886                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8887     return 1;
8888
8889   /* We used to see if get_last_value of X and Y were the same but that's
8890      not correct.  In one direction, we'll cause the assignment to have
8891      the wrong destination and in the case, we'll import a register into this
8892      insn that might have already have been dead.   So fail if none of the
8893      above cases are true.  */
8894   return 0;
8895 }
8896 \f
8897 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8898    Return that assignment if so.
8899
8900    We only handle the most common cases.  */
8901
8902 static rtx
8903 make_field_assignment (rtx x)
8904 {
8905   rtx dest = SET_DEST (x);
8906   rtx src = SET_SRC (x);
8907   rtx assign;
8908   rtx rhs, lhs;
8909   HOST_WIDE_INT c1;
8910   HOST_WIDE_INT pos;
8911   unsigned HOST_WIDE_INT len;
8912   rtx other;
8913   enum machine_mode mode;
8914
8915   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8916      a clear of a one-bit field.  We will have changed it to
8917      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
8918      for a SUBREG.  */
8919
8920   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8921       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8922       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8923       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8924     {
8925       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8926                                 1, 1, 1, 0);
8927       if (assign != 0)
8928         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8929       return x;
8930     }
8931
8932   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8933       && subreg_lowpart_p (XEXP (src, 0))
8934       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8935           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8936       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8937       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8938       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8939       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8940     {
8941       assign = make_extraction (VOIDmode, dest, 0,
8942                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8943                                 1, 1, 1, 0);
8944       if (assign != 0)
8945         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8946       return x;
8947     }
8948
8949   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8950      one-bit field.  */
8951   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8952       && XEXP (XEXP (src, 0), 0) == const1_rtx
8953       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8954     {
8955       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8956                                 1, 1, 1, 0);
8957       if (assign != 0)
8958         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8959       return x;
8960     }
8961
8962   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8963      SRC is an AND with all bits of that field set, then we can discard
8964      the AND.  */
8965   if (GET_CODE (dest) == ZERO_EXTRACT
8966       && CONST_INT_P (XEXP (dest, 1))
8967       && GET_CODE (src) == AND
8968       && CONST_INT_P (XEXP (src, 1)))
8969     {
8970       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8971       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8972       unsigned HOST_WIDE_INT ze_mask;
8973
8974       if (width >= HOST_BITS_PER_WIDE_INT)
8975         ze_mask = -1;
8976       else
8977         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8978
8979       /* Complete overlap.  We can remove the source AND.  */
8980       if ((and_mask & ze_mask) == ze_mask)
8981         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8982
8983       /* Partial overlap.  We can reduce the source AND.  */
8984       if ((and_mask & ze_mask) != and_mask)
8985         {
8986           mode = GET_MODE (src);
8987           src = gen_rtx_AND (mode, XEXP (src, 0),
8988                              gen_int_mode (and_mask & ze_mask, mode));
8989           return gen_rtx_SET (VOIDmode, dest, src);
8990         }
8991     }
8992
8993   /* The other case we handle is assignments into a constant-position
8994      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
8995      a mask that has all one bits except for a group of zero bits and
8996      OTHER is known to have zeros where C1 has ones, this is such an
8997      assignment.  Compute the position and length from C1.  Shift OTHER
8998      to the appropriate position, force it to the required mode, and
8999      make the extraction.  Check for the AND in both operands.  */
9000
9001   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9002     return x;
9003
9004   rhs = expand_compound_operation (XEXP (src, 0));
9005   lhs = expand_compound_operation (XEXP (src, 1));
9006
9007   if (GET_CODE (rhs) == AND
9008       && CONST_INT_P (XEXP (rhs, 1))
9009       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9010     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9011   else if (GET_CODE (lhs) == AND
9012            && CONST_INT_P (XEXP (lhs, 1))
9013            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9014     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9015   else
9016     return x;
9017
9018   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9019   if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9020       || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9021       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9022     return x;
9023
9024   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9025   if (assign == 0)
9026     return x;
9027
9028   /* The mode to use for the source is the mode of the assignment, or of
9029      what is inside a possible STRICT_LOW_PART.  */
9030   mode = (GET_CODE (assign) == STRICT_LOW_PART
9031           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9032
9033   /* Shift OTHER right POS places and make it the source, restricting it
9034      to the proper length and mode.  */
9035
9036   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9037                                                      GET_MODE (src),
9038                                                      other, pos),
9039                                dest);
9040   src = force_to_mode (src, mode,
9041                        GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9042                        ? ~(unsigned HOST_WIDE_INT) 0
9043                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9044                        0);
9045
9046   /* If SRC is masked by an AND that does not make a difference in
9047      the value being stored, strip it.  */
9048   if (GET_CODE (assign) == ZERO_EXTRACT
9049       && CONST_INT_P (XEXP (assign, 1))
9050       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9051       && GET_CODE (src) == AND
9052       && CONST_INT_P (XEXP (src, 1))
9053       && UINTVAL (XEXP (src, 1))
9054          == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9055     src = XEXP (src, 0);
9056
9057   return gen_rtx_SET (VOIDmode, assign, src);
9058 }
9059 \f
9060 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9061    if so.  */
9062
9063 static rtx
9064 apply_distributive_law (rtx x)
9065 {
9066   enum rtx_code code = GET_CODE (x);
9067   enum rtx_code inner_code;
9068   rtx lhs, rhs, other;
9069   rtx tem;
9070
9071   /* Distributivity is not true for floating point as it can change the
9072      value.  So we don't do it unless -funsafe-math-optimizations.  */
9073   if (FLOAT_MODE_P (GET_MODE (x))
9074       && ! flag_unsafe_math_optimizations)
9075     return x;
9076
9077   /* The outer operation can only be one of the following:  */
9078   if (code != IOR && code != AND && code != XOR
9079       && code != PLUS && code != MINUS)
9080     return x;
9081
9082   lhs = XEXP (x, 0);
9083   rhs = XEXP (x, 1);
9084
9085   /* If either operand is a primitive we can't do anything, so get out
9086      fast.  */
9087   if (OBJECT_P (lhs) || OBJECT_P (rhs))
9088     return x;
9089
9090   lhs = expand_compound_operation (lhs);
9091   rhs = expand_compound_operation (rhs);
9092   inner_code = GET_CODE (lhs);
9093   if (inner_code != GET_CODE (rhs))
9094     return x;
9095
9096   /* See if the inner and outer operations distribute.  */
9097   switch (inner_code)
9098     {
9099     case LSHIFTRT:
9100     case ASHIFTRT:
9101     case AND:
9102     case IOR:
9103       /* These all distribute except over PLUS.  */
9104       if (code == PLUS || code == MINUS)
9105         return x;
9106       break;
9107
9108     case MULT:
9109       if (code != PLUS && code != MINUS)
9110         return x;
9111       break;
9112
9113     case ASHIFT:
9114       /* This is also a multiply, so it distributes over everything.  */
9115       break;
9116
9117     /* This used to handle SUBREG, but this turned out to be counter-
9118        productive, since (subreg (op ...)) usually is not handled by
9119        insn patterns, and this "optimization" therefore transformed
9120        recognizable patterns into unrecognizable ones.  Therefore the
9121        SUBREG case was removed from here.
9122
9123        It is possible that distributing SUBREG over arithmetic operations
9124        leads to an intermediate result than can then be optimized further,
9125        e.g. by moving the outer SUBREG to the other side of a SET as done
9126        in simplify_set.  This seems to have been the original intent of
9127        handling SUBREGs here.
9128
9129        However, with current GCC this does not appear to actually happen,
9130        at least on major platforms.  If some case is found where removing
9131        the SUBREG case here prevents follow-on optimizations, distributing
9132        SUBREGs ought to be re-added at that place, e.g. in simplify_set.  */
9133
9134     default:
9135       return x;
9136     }
9137
9138   /* Set LHS and RHS to the inner operands (A and B in the example
9139      above) and set OTHER to the common operand (C in the example).
9140      There is only one way to do this unless the inner operation is
9141      commutative.  */
9142   if (COMMUTATIVE_ARITH_P (lhs)
9143       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9144     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9145   else if (COMMUTATIVE_ARITH_P (lhs)
9146            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9147     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9148   else if (COMMUTATIVE_ARITH_P (lhs)
9149            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9150     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9151   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9152     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9153   else
9154     return x;
9155
9156   /* Form the new inner operation, seeing if it simplifies first.  */
9157   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9158
9159   /* There is one exception to the general way of distributing:
9160      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
9161   if (code == XOR && inner_code == IOR)
9162     {
9163       inner_code = AND;
9164       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9165     }
9166
9167   /* We may be able to continuing distributing the result, so call
9168      ourselves recursively on the inner operation before forming the
9169      outer operation, which we return.  */
9170   return simplify_gen_binary (inner_code, GET_MODE (x),
9171                               apply_distributive_law (tem), other);
9172 }
9173
9174 /* See if X is of the form (* (+ A B) C), and if so convert to
9175    (+ (* A C) (* B C)) and try to simplify.
9176
9177    Most of the time, this results in no change.  However, if some of
9178    the operands are the same or inverses of each other, simplifications
9179    will result.
9180
9181    For example, (and (ior A B) (not B)) can occur as the result of
9182    expanding a bit field assignment.  When we apply the distributive
9183    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9184    which then simplifies to (and (A (not B))).
9185
9186    Note that no checks happen on the validity of applying the inverse
9187    distributive law.  This is pointless since we can do it in the
9188    few places where this routine is called.
9189
9190    N is the index of the term that is decomposed (the arithmetic operation,
9191    i.e. (+ A B) in the first example above).  !N is the index of the term that
9192    is distributed, i.e. of C in the first example above.  */
9193 static rtx
9194 distribute_and_simplify_rtx (rtx x, int n)
9195 {
9196   enum machine_mode mode;
9197   enum rtx_code outer_code, inner_code;
9198   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9199
9200   /* Distributivity is not true for floating point as it can change the
9201      value.  So we don't do it unless -funsafe-math-optimizations.  */
9202   if (FLOAT_MODE_P (GET_MODE (x))
9203       && ! flag_unsafe_math_optimizations)
9204     return NULL_RTX;
9205
9206   decomposed = XEXP (x, n);
9207   if (!ARITHMETIC_P (decomposed))
9208     return NULL_RTX;
9209
9210   mode = GET_MODE (x);
9211   outer_code = GET_CODE (x);
9212   distributed = XEXP (x, !n);
9213
9214   inner_code = GET_CODE (decomposed);
9215   inner_op0 = XEXP (decomposed, 0);
9216   inner_op1 = XEXP (decomposed, 1);
9217
9218   /* Special case (and (xor B C) (not A)), which is equivalent to
9219      (xor (ior A B) (ior A C))  */
9220   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9221     {
9222       distributed = XEXP (distributed, 0);
9223       outer_code = IOR;
9224     }
9225
9226   if (n == 0)
9227     {
9228       /* Distribute the second term.  */
9229       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9230       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9231     }
9232   else
9233     {
9234       /* Distribute the first term.  */
9235       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9236       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9237     }
9238
9239   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9240                                                      new_op0, new_op1));
9241   if (GET_CODE (tmp) != outer_code
9242       && (set_src_cost (tmp, optimize_this_for_speed_p)
9243           < set_src_cost (x, optimize_this_for_speed_p)))
9244     return tmp;
9245
9246   return NULL_RTX;
9247 }
9248 \f
9249 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9250    in MODE.  Return an equivalent form, if different from (and VAROP
9251    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
9252
9253 static rtx
9254 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9255                           unsigned HOST_WIDE_INT constop)
9256 {
9257   unsigned HOST_WIDE_INT nonzero;
9258   unsigned HOST_WIDE_INT orig_constop;
9259   rtx orig_varop;
9260   int i;
9261
9262   orig_varop = varop;
9263   orig_constop = constop;
9264   if (GET_CODE (varop) == CLOBBER)
9265     return NULL_RTX;
9266
9267   /* Simplify VAROP knowing that we will be only looking at some of the
9268      bits in it.
9269
9270      Note by passing in CONSTOP, we guarantee that the bits not set in
9271      CONSTOP are not significant and will never be examined.  We must
9272      ensure that is the case by explicitly masking out those bits
9273      before returning.  */
9274   varop = force_to_mode (varop, mode, constop, 0);
9275
9276   /* If VAROP is a CLOBBER, we will fail so return it.  */
9277   if (GET_CODE (varop) == CLOBBER)
9278     return varop;
9279
9280   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9281      to VAROP and return the new constant.  */
9282   if (CONST_INT_P (varop))
9283     return gen_int_mode (INTVAL (varop) & constop, mode);
9284
9285   /* See what bits may be nonzero in VAROP.  Unlike the general case of
9286      a call to nonzero_bits, here we don't care about bits outside
9287      MODE.  */
9288
9289   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9290
9291   /* Turn off all bits in the constant that are known to already be zero.
9292      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9293      which is tested below.  */
9294
9295   constop &= nonzero;
9296
9297   /* If we don't have any bits left, return zero.  */
9298   if (constop == 0)
9299     return const0_rtx;
9300
9301   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9302      a power of two, we can replace this with an ASHIFT.  */
9303   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9304       && (i = exact_log2 (constop)) >= 0)
9305     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9306
9307   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9308      or XOR, then try to apply the distributive law.  This may eliminate
9309      operations if either branch can be simplified because of the AND.
9310      It may also make some cases more complex, but those cases probably
9311      won't match a pattern either with or without this.  */
9312
9313   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9314     return
9315       gen_lowpart
9316         (mode,
9317          apply_distributive_law
9318          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9319                                simplify_and_const_int (NULL_RTX,
9320                                                        GET_MODE (varop),
9321                                                        XEXP (varop, 0),
9322                                                        constop),
9323                                simplify_and_const_int (NULL_RTX,
9324                                                        GET_MODE (varop),
9325                                                        XEXP (varop, 1),
9326                                                        constop))));
9327
9328   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9329      the AND and see if one of the operands simplifies to zero.  If so, we
9330      may eliminate it.  */
9331
9332   if (GET_CODE (varop) == PLUS
9333       && exact_log2 (constop + 1) >= 0)
9334     {
9335       rtx o0, o1;
9336
9337       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9338       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9339       if (o0 == const0_rtx)
9340         return o1;
9341       if (o1 == const0_rtx)
9342         return o0;
9343     }
9344
9345   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9346   varop = gen_lowpart (mode, varop);
9347   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9348     return NULL_RTX;
9349
9350   /* If we are only masking insignificant bits, return VAROP.  */
9351   if (constop == nonzero)
9352     return varop;
9353
9354   if (varop == orig_varop && constop == orig_constop)
9355     return NULL_RTX;
9356
9357   /* Otherwise, return an AND.  */
9358   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9359 }
9360
9361
9362 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9363    in MODE.
9364
9365    Return an equivalent form, if different from X.  Otherwise, return X.  If
9366    X is zero, we are to always construct the equivalent form.  */
9367
9368 static rtx
9369 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9370                         unsigned HOST_WIDE_INT constop)
9371 {
9372   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9373   if (tem)
9374     return tem;
9375
9376   if (!x)
9377     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9378                              gen_int_mode (constop, mode));
9379   if (GET_MODE (x) != mode)
9380     x = gen_lowpart (mode, x);
9381   return x;
9382 }
9383 \f
9384 /* Given a REG, X, compute which bits in X can be nonzero.
9385    We don't care about bits outside of those defined in MODE.
9386
9387    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9388    a shift, AND, or zero_extract, we can do better.  */
9389
9390 static rtx
9391 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9392                               const_rtx known_x ATTRIBUTE_UNUSED,
9393                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
9394                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9395                               unsigned HOST_WIDE_INT *nonzero)
9396 {
9397   rtx tem;
9398   reg_stat_type *rsp;
9399
9400   /* If X is a register whose nonzero bits value is current, use it.
9401      Otherwise, if X is a register whose value we can find, use that
9402      value.  Otherwise, use the previously-computed global nonzero bits
9403      for this register.  */
9404
9405   rsp = &reg_stat[REGNO (x)];
9406   if (rsp->last_set_value != 0
9407       && (rsp->last_set_mode == mode
9408           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9409               && GET_MODE_CLASS (mode) == MODE_INT))
9410       && ((rsp->last_set_label >= label_tick_ebb_start
9411            && rsp->last_set_label < label_tick)
9412           || (rsp->last_set_label == label_tick
9413               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9414           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9415               && REG_N_SETS (REGNO (x)) == 1
9416               && !REGNO_REG_SET_P
9417                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9418     {
9419       *nonzero &= rsp->last_set_nonzero_bits;
9420       return NULL;
9421     }
9422
9423   tem = get_last_value (x);
9424
9425   if (tem)
9426     {
9427 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9428       /* If X is narrower than MODE and TEM is a non-negative
9429          constant that would appear negative in the mode of X,
9430          sign-extend it for use in reg_nonzero_bits because some
9431          machines (maybe most) will actually do the sign-extension
9432          and this is the conservative approach.
9433
9434          ??? For 2.5, try to tighten up the MD files in this regard
9435          instead of this kludge.  */
9436
9437       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9438           && CONST_INT_P (tem)
9439           && INTVAL (tem) > 0
9440           && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9441         tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9442 #endif
9443       return tem;
9444     }
9445   else if (nonzero_sign_valid && rsp->nonzero_bits)
9446     {
9447       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9448
9449       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9450         /* We don't know anything about the upper bits.  */
9451         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9452       *nonzero &= mask;
9453     }
9454
9455   return NULL;
9456 }
9457
9458 /* Return the number of bits at the high-order end of X that are known to
9459    be equal to the sign bit.  X will be used in mode MODE; if MODE is
9460    VOIDmode, X will be used in its own mode.  The returned value  will always
9461    be between 1 and the number of bits in MODE.  */
9462
9463 static rtx
9464 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9465                                      const_rtx known_x ATTRIBUTE_UNUSED,
9466                                      enum machine_mode known_mode
9467                                      ATTRIBUTE_UNUSED,
9468                                      unsigned int known_ret ATTRIBUTE_UNUSED,
9469                                      unsigned int *result)
9470 {
9471   rtx tem;
9472   reg_stat_type *rsp;
9473
9474   rsp = &reg_stat[REGNO (x)];
9475   if (rsp->last_set_value != 0
9476       && rsp->last_set_mode == mode
9477       && ((rsp->last_set_label >= label_tick_ebb_start
9478            && rsp->last_set_label < label_tick)
9479           || (rsp->last_set_label == label_tick
9480               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9481           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9482               && REG_N_SETS (REGNO (x)) == 1
9483               && !REGNO_REG_SET_P
9484                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9485     {
9486       *result = rsp->last_set_sign_bit_copies;
9487       return NULL;
9488     }
9489
9490   tem = get_last_value (x);
9491   if (tem != 0)
9492     return tem;
9493
9494   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9495       && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9496     *result = rsp->sign_bit_copies;
9497
9498   return NULL;
9499 }
9500 \f
9501 /* Return the number of "extended" bits there are in X, when interpreted
9502    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
9503    unsigned quantities, this is the number of high-order zero bits.
9504    For signed quantities, this is the number of copies of the sign bit
9505    minus 1.  In both case, this function returns the number of "spare"
9506    bits.  For example, if two quantities for which this function returns
9507    at least 1 are added, the addition is known not to overflow.
9508
9509    This function will always return 0 unless called during combine, which
9510    implies that it must be called from a define_split.  */
9511
9512 unsigned int
9513 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9514 {
9515   if (nonzero_sign_valid == 0)
9516     return 0;
9517
9518   return (unsignedp
9519           ? (HWI_COMPUTABLE_MODE_P (mode)
9520              ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9521                                - floor_log2 (nonzero_bits (x, mode)))
9522              : 0)
9523           : num_sign_bit_copies (x, mode) - 1);
9524 }
9525
9526 /* This function is called from `simplify_shift_const' to merge two
9527    outer operations.  Specifically, we have already found that we need
9528    to perform operation *POP0 with constant *PCONST0 at the outermost
9529    position.  We would now like to also perform OP1 with constant CONST1
9530    (with *POP0 being done last).
9531
9532    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9533    the resulting operation.  *PCOMP_P is set to 1 if we would need to
9534    complement the innermost operand, otherwise it is unchanged.
9535
9536    MODE is the mode in which the operation will be done.  No bits outside
9537    the width of this mode matter.  It is assumed that the width of this mode
9538    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9539
9540    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
9541    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
9542    result is simply *PCONST0.
9543
9544    If the resulting operation cannot be expressed as one operation, we
9545    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
9546
9547 static int
9548 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9549 {
9550   enum rtx_code op0 = *pop0;
9551   HOST_WIDE_INT const0 = *pconst0;
9552
9553   const0 &= GET_MODE_MASK (mode);
9554   const1 &= GET_MODE_MASK (mode);
9555
9556   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
9557   if (op0 == AND)
9558     const1 &= const0;
9559
9560   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
9561      if OP0 is SET.  */
9562
9563   if (op1 == UNKNOWN || op0 == SET)
9564     return 1;
9565
9566   else if (op0 == UNKNOWN)
9567     op0 = op1, const0 = const1;
9568
9569   else if (op0 == op1)
9570     {
9571       switch (op0)
9572         {
9573         case AND:
9574           const0 &= const1;
9575           break;
9576         case IOR:
9577           const0 |= const1;
9578           break;
9579         case XOR:
9580           const0 ^= const1;
9581           break;
9582         case PLUS:
9583           const0 += const1;
9584           break;
9585         case NEG:
9586           op0 = UNKNOWN;
9587           break;
9588         default:
9589           break;
9590         }
9591     }
9592
9593   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
9594   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9595     return 0;
9596
9597   /* If the two constants aren't the same, we can't do anything.  The
9598      remaining six cases can all be done.  */
9599   else if (const0 != const1)
9600     return 0;
9601
9602   else
9603     switch (op0)
9604       {
9605       case IOR:
9606         if (op1 == AND)
9607           /* (a & b) | b == b */
9608           op0 = SET;
9609         else /* op1 == XOR */
9610           /* (a ^ b) | b == a | b */
9611           {;}
9612         break;
9613
9614       case XOR:
9615         if (op1 == AND)
9616           /* (a & b) ^ b == (~a) & b */
9617           op0 = AND, *pcomp_p = 1;
9618         else /* op1 == IOR */
9619           /* (a | b) ^ b == a & ~b */
9620           op0 = AND, const0 = ~const0;
9621         break;
9622
9623       case AND:
9624         if (op1 == IOR)
9625           /* (a | b) & b == b */
9626         op0 = SET;
9627         else /* op1 == XOR */
9628           /* (a ^ b) & b) == (~a) & b */
9629           *pcomp_p = 1;
9630         break;
9631       default:
9632         break;
9633       }
9634
9635   /* Check for NO-OP cases.  */
9636   const0 &= GET_MODE_MASK (mode);
9637   if (const0 == 0
9638       && (op0 == IOR || op0 == XOR || op0 == PLUS))
9639     op0 = UNKNOWN;
9640   else if (const0 == 0 && op0 == AND)
9641     op0 = SET;
9642   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9643            && op0 == AND)
9644     op0 = UNKNOWN;
9645
9646   *pop0 = op0;
9647
9648   /* ??? Slightly redundant with the above mask, but not entirely.
9649      Moving this above means we'd have to sign-extend the mode mask
9650      for the final test.  */
9651   if (op0 != UNKNOWN && op0 != NEG)
9652     *pconst0 = trunc_int_for_mode (const0, mode);
9653
9654   return 1;
9655 }
9656 \f
9657 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9658    the shift in.  The original shift operation CODE is performed on OP in
9659    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
9660    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
9661    result of the shift is subject to operation OUTER_CODE with operand
9662    OUTER_CONST.  */
9663
9664 static enum machine_mode
9665 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9666                       enum machine_mode orig_mode, enum machine_mode mode,
9667                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9668 {
9669   if (orig_mode == mode)
9670     return mode;
9671   gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9672
9673   /* In general we can't perform in wider mode for right shift and rotate.  */
9674   switch (code)
9675     {
9676     case ASHIFTRT:
9677       /* We can still widen if the bits brought in from the left are identical
9678          to the sign bit of ORIG_MODE.  */
9679       if (num_sign_bit_copies (op, mode)
9680           > (unsigned) (GET_MODE_PRECISION (mode)
9681                         - GET_MODE_PRECISION (orig_mode)))
9682         return mode;
9683       return orig_mode;
9684
9685     case LSHIFTRT:
9686       /* Similarly here but with zero bits.  */
9687       if (HWI_COMPUTABLE_MODE_P (mode)
9688           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9689         return mode;
9690
9691       /* We can also widen if the bits brought in will be masked off.  This
9692          operation is performed in ORIG_MODE.  */
9693       if (outer_code == AND)
9694         {
9695           int care_bits = low_bitmask_len (orig_mode, outer_const);
9696
9697           if (care_bits >= 0
9698               && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9699             return mode;
9700         }
9701       /* fall through */
9702
9703     case ROTATE:
9704       return orig_mode;
9705
9706     case ROTATERT:
9707       gcc_unreachable ();
9708
9709     default:
9710       return mode;
9711     }
9712 }
9713
9714 /* Simplify a shift of VAROP by ORIG_COUNT bits.  CODE says what kind
9715    of shift.  The result of the shift is RESULT_MODE.  Return NULL_RTX
9716    if we cannot simplify it.  Otherwise, return a simplified value.
9717
9718    The shift is normally computed in the widest mode we find in VAROP, as
9719    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9720    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9721
9722 static rtx
9723 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9724                         rtx varop, int orig_count)
9725 {
9726   enum rtx_code orig_code = code;
9727   rtx orig_varop = varop;
9728   int count;
9729   enum machine_mode mode = result_mode;
9730   enum machine_mode shift_mode, tmode;
9731   unsigned int mode_words
9732     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9733   /* We form (outer_op (code varop count) (outer_const)).  */
9734   enum rtx_code outer_op = UNKNOWN;
9735   HOST_WIDE_INT outer_const = 0;
9736   int complement_p = 0;
9737   rtx new_rtx, x;
9738
9739   /* Make sure and truncate the "natural" shift on the way in.  We don't
9740      want to do this inside the loop as it makes it more difficult to
9741      combine shifts.  */
9742   if (SHIFT_COUNT_TRUNCATED)
9743     orig_count &= GET_MODE_BITSIZE (mode) - 1;
9744
9745   /* If we were given an invalid count, don't do anything except exactly
9746      what was requested.  */
9747
9748   if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9749     return NULL_RTX;
9750
9751   count = orig_count;
9752
9753   /* Unless one of the branches of the `if' in this loop does a `continue',
9754      we will `break' the loop after the `if'.  */
9755
9756   while (count != 0)
9757     {
9758       /* If we have an operand of (clobber (const_int 0)), fail.  */
9759       if (GET_CODE (varop) == CLOBBER)
9760         return NULL_RTX;
9761
9762       /* Convert ROTATERT to ROTATE.  */
9763       if (code == ROTATERT)
9764         {
9765           unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9766           code = ROTATE;
9767           if (VECTOR_MODE_P (result_mode))
9768             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9769           else
9770             count = bitsize - count;
9771         }
9772
9773       shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9774                                          mode, outer_op, outer_const);
9775
9776       /* Handle cases where the count is greater than the size of the mode
9777          minus 1.  For ASHIFT, use the size minus one as the count (this can
9778          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9779          take the count modulo the size.  For other shifts, the result is
9780          zero.
9781
9782          Since these shifts are being produced by the compiler by combining
9783          multiple operations, each of which are defined, we know what the
9784          result is supposed to be.  */
9785
9786       if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9787         {
9788           if (code == ASHIFTRT)
9789             count = GET_MODE_PRECISION (shift_mode) - 1;
9790           else if (code == ROTATE || code == ROTATERT)
9791             count %= GET_MODE_PRECISION (shift_mode);
9792           else
9793             {
9794               /* We can't simply return zero because there may be an
9795                  outer op.  */
9796               varop = const0_rtx;
9797               count = 0;
9798               break;
9799             }
9800         }
9801
9802       /* If we discovered we had to complement VAROP, leave.  Making a NOT
9803          here would cause an infinite loop.  */
9804       if (complement_p)
9805         break;
9806
9807       /* An arithmetic right shift of a quantity known to be -1 or 0
9808          is a no-op.  */
9809       if (code == ASHIFTRT
9810           && (num_sign_bit_copies (varop, shift_mode)
9811               == GET_MODE_PRECISION (shift_mode)))
9812         {
9813           count = 0;
9814           break;
9815         }
9816
9817       /* If we are doing an arithmetic right shift and discarding all but
9818          the sign bit copies, this is equivalent to doing a shift by the
9819          bitsize minus one.  Convert it into that shift because it will often
9820          allow other simplifications.  */
9821
9822       if (code == ASHIFTRT
9823           && (count + num_sign_bit_copies (varop, shift_mode)
9824               >= GET_MODE_PRECISION (shift_mode)))
9825         count = GET_MODE_PRECISION (shift_mode) - 1;
9826
9827       /* We simplify the tests below and elsewhere by converting
9828          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9829          `make_compound_operation' will convert it to an ASHIFTRT for
9830          those machines (such as VAX) that don't have an LSHIFTRT.  */
9831       if (code == ASHIFTRT
9832           && val_signbit_known_clear_p (shift_mode,
9833                                         nonzero_bits (varop, shift_mode)))
9834         code = LSHIFTRT;
9835
9836       if (((code == LSHIFTRT
9837             && HWI_COMPUTABLE_MODE_P (shift_mode)
9838             && !(nonzero_bits (varop, shift_mode) >> count))
9839            || (code == ASHIFT
9840                && HWI_COMPUTABLE_MODE_P (shift_mode)
9841                && !((nonzero_bits (varop, shift_mode) << count)
9842                     & GET_MODE_MASK (shift_mode))))
9843           && !side_effects_p (varop))
9844         varop = const0_rtx;
9845
9846       switch (GET_CODE (varop))
9847         {
9848         case SIGN_EXTEND:
9849         case ZERO_EXTEND:
9850         case SIGN_EXTRACT:
9851         case ZERO_EXTRACT:
9852           new_rtx = expand_compound_operation (varop);
9853           if (new_rtx != varop)
9854             {
9855               varop = new_rtx;
9856               continue;
9857             }
9858           break;
9859
9860         case MEM:
9861           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9862              minus the width of a smaller mode, we can do this with a
9863              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
9864           if ((code == ASHIFTRT || code == LSHIFTRT)
9865               && ! mode_dependent_address_p (XEXP (varop, 0),
9866                                              MEM_ADDR_SPACE (varop))
9867               && ! MEM_VOLATILE_P (varop)
9868               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9869                                          MODE_INT, 1)) != BLKmode)
9870             {
9871               new_rtx = adjust_address_nv (varop, tmode,
9872                                        BYTES_BIG_ENDIAN ? 0
9873                                        : count / BITS_PER_UNIT);
9874
9875               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9876                                      : ZERO_EXTEND, mode, new_rtx);
9877               count = 0;
9878               continue;
9879             }
9880           break;
9881
9882         case SUBREG:
9883           /* If VAROP is a SUBREG, strip it as long as the inner operand has
9884              the same number of words as what we've seen so far.  Then store
9885              the widest mode in MODE.  */
9886           if (subreg_lowpart_p (varop)
9887               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9888                   > GET_MODE_SIZE (GET_MODE (varop)))
9889               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9890                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9891                  == mode_words
9892               && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9893               && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9894             {
9895               varop = SUBREG_REG (varop);
9896               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9897                 mode = GET_MODE (varop);
9898               continue;
9899             }
9900           break;
9901
9902         case MULT:
9903           /* Some machines use MULT instead of ASHIFT because MULT
9904              is cheaper.  But it is still better on those machines to
9905              merge two shifts into one.  */
9906           if (CONST_INT_P (XEXP (varop, 1))
9907               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9908             {
9909               varop
9910                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9911                                        XEXP (varop, 0),
9912                                        GEN_INT (exact_log2 (
9913                                                 UINTVAL (XEXP (varop, 1)))));
9914               continue;
9915             }
9916           break;
9917
9918         case UDIV:
9919           /* Similar, for when divides are cheaper.  */
9920           if (CONST_INT_P (XEXP (varop, 1))
9921               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9922             {
9923               varop
9924                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9925                                        XEXP (varop, 0),
9926                                        GEN_INT (exact_log2 (
9927                                                 UINTVAL (XEXP (varop, 1)))));
9928               continue;
9929             }
9930           break;
9931
9932         case ASHIFTRT:
9933           /* If we are extracting just the sign bit of an arithmetic
9934              right shift, that shift is not needed.  However, the sign
9935              bit of a wider mode may be different from what would be
9936              interpreted as the sign bit in a narrower mode, so, if
9937              the result is narrower, don't discard the shift.  */
9938           if (code == LSHIFTRT
9939               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9940               && (GET_MODE_BITSIZE (result_mode)
9941                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
9942             {
9943               varop = XEXP (varop, 0);
9944               continue;
9945             }
9946
9947           /* ... fall through ...  */
9948
9949         case LSHIFTRT:
9950         case ASHIFT:
9951         case ROTATE:
9952           /* Here we have two nested shifts.  The result is usually the
9953              AND of a new shift with a mask.  We compute the result below.  */
9954           if (CONST_INT_P (XEXP (varop, 1))
9955               && INTVAL (XEXP (varop, 1)) >= 0
9956               && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
9957               && HWI_COMPUTABLE_MODE_P (result_mode)
9958               && HWI_COMPUTABLE_MODE_P (mode)
9959               && !VECTOR_MODE_P (result_mode))
9960             {
9961               enum rtx_code first_code = GET_CODE (varop);
9962               unsigned int first_count = INTVAL (XEXP (varop, 1));
9963               unsigned HOST_WIDE_INT mask;
9964               rtx mask_rtx;
9965
9966               /* We have one common special case.  We can't do any merging if
9967                  the inner code is an ASHIFTRT of a smaller mode.  However, if
9968                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9969                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9970                  we can convert it to
9971                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
9972                  This simplifies certain SIGN_EXTEND operations.  */
9973               if (code == ASHIFT && first_code == ASHIFTRT
9974                   && count == (GET_MODE_PRECISION (result_mode)
9975                                - GET_MODE_PRECISION (GET_MODE (varop))))
9976                 {
9977                   /* C3 has the low-order C1 bits zero.  */
9978
9979                   mask = GET_MODE_MASK (mode)
9980                          & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
9981
9982                   varop = simplify_and_const_int (NULL_RTX, result_mode,
9983                                                   XEXP (varop, 0), mask);
9984                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9985                                                 varop, count);
9986                   count = first_count;
9987                   code = ASHIFTRT;
9988                   continue;
9989                 }
9990
9991               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9992                  than C1 high-order bits equal to the sign bit, we can convert
9993                  this to either an ASHIFT or an ASHIFTRT depending on the
9994                  two counts.
9995
9996                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
9997
9998               if (code == ASHIFTRT && first_code == ASHIFT
9999                   && GET_MODE (varop) == shift_mode
10000                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10001                       > first_count))
10002                 {
10003                   varop = XEXP (varop, 0);
10004                   count -= first_count;
10005                   if (count < 0)
10006                     {
10007                       count = -count;
10008                       code = ASHIFT;
10009                     }
10010
10011                   continue;
10012                 }
10013
10014               /* There are some cases we can't do.  If CODE is ASHIFTRT,
10015                  we can only do this if FIRST_CODE is also ASHIFTRT.
10016
10017                  We can't do the case when CODE is ROTATE and FIRST_CODE is
10018                  ASHIFTRT.
10019
10020                  If the mode of this shift is not the mode of the outer shift,
10021                  we can't do this if either shift is a right shift or ROTATE.
10022
10023                  Finally, we can't do any of these if the mode is too wide
10024                  unless the codes are the same.
10025
10026                  Handle the case where the shift codes are the same
10027                  first.  */
10028
10029               if (code == first_code)
10030                 {
10031                   if (GET_MODE (varop) != result_mode
10032                       && (code == ASHIFTRT || code == LSHIFTRT
10033                           || code == ROTATE))
10034                     break;
10035
10036                   count += first_count;
10037                   varop = XEXP (varop, 0);
10038                   continue;
10039                 }
10040
10041               if (code == ASHIFTRT
10042                   || (code == ROTATE && first_code == ASHIFTRT)
10043                   || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10044                   || (GET_MODE (varop) != result_mode
10045                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
10046                           || first_code == ROTATE
10047                           || code == ROTATE)))
10048                 break;
10049
10050               /* To compute the mask to apply after the shift, shift the
10051                  nonzero bits of the inner shift the same way the
10052                  outer shift will.  */
10053
10054               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10055
10056               mask_rtx
10057                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10058                                                    GEN_INT (count));
10059
10060               /* Give up if we can't compute an outer operation to use.  */
10061               if (mask_rtx == 0
10062                   || !CONST_INT_P (mask_rtx)
10063                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
10064                                         INTVAL (mask_rtx),
10065                                         result_mode, &complement_p))
10066                 break;
10067
10068               /* If the shifts are in the same direction, we add the
10069                  counts.  Otherwise, we subtract them.  */
10070               if ((code == ASHIFTRT || code == LSHIFTRT)
10071                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10072                 count += first_count;
10073               else
10074                 count -= first_count;
10075
10076               /* If COUNT is positive, the new shift is usually CODE,
10077                  except for the two exceptions below, in which case it is
10078                  FIRST_CODE.  If the count is negative, FIRST_CODE should
10079                  always be used  */
10080               if (count > 0
10081                   && ((first_code == ROTATE && code == ASHIFT)
10082                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
10083                 code = first_code;
10084               else if (count < 0)
10085                 code = first_code, count = -count;
10086
10087               varop = XEXP (varop, 0);
10088               continue;
10089             }
10090
10091           /* If we have (A << B << C) for any shift, we can convert this to
10092              (A << C << B).  This wins if A is a constant.  Only try this if
10093              B is not a constant.  */
10094
10095           else if (GET_CODE (varop) == code
10096                    && CONST_INT_P (XEXP (varop, 0))
10097                    && !CONST_INT_P (XEXP (varop, 1)))
10098             {
10099               rtx new_rtx = simplify_const_binary_operation (code, mode,
10100                                                          XEXP (varop, 0),
10101                                                          GEN_INT (count));
10102               varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10103               count = 0;
10104               continue;
10105             }
10106           break;
10107
10108         case NOT:
10109           if (VECTOR_MODE_P (mode))
10110             break;
10111
10112           /* Make this fit the case below.  */
10113           varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10114           continue;
10115
10116         case IOR:
10117         case AND:
10118         case XOR:
10119           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10120              with C the size of VAROP - 1 and the shift is logical if
10121              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10122              we have an (le X 0) operation.   If we have an arithmetic shift
10123              and STORE_FLAG_VALUE is 1 or we have a logical shift with
10124              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
10125
10126           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10127               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10128               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10129               && (code == LSHIFTRT || code == ASHIFTRT)
10130               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10131               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10132             {
10133               count = 0;
10134               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10135                                   const0_rtx);
10136
10137               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10138                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10139
10140               continue;
10141             }
10142
10143           /* If we have (shift (logical)), move the logical to the outside
10144              to allow it to possibly combine with another logical and the
10145              shift to combine with another shift.  This also canonicalizes to
10146              what a ZERO_EXTRACT looks like.  Also, some machines have
10147              (and (shift)) insns.  */
10148
10149           if (CONST_INT_P (XEXP (varop, 1))
10150               /* We can't do this if we have (ashiftrt (xor))  and the
10151                  constant has its sign bit set in shift_mode.  */
10152               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10153                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10154                                               shift_mode))
10155               && (new_rtx = simplify_const_binary_operation (code, result_mode,
10156                                                          XEXP (varop, 1),
10157                                                          GEN_INT (count))) != 0
10158               && CONST_INT_P (new_rtx)
10159               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10160                                   INTVAL (new_rtx), result_mode, &complement_p))
10161             {
10162               varop = XEXP (varop, 0);
10163               continue;
10164             }
10165
10166           /* If we can't do that, try to simplify the shift in each arm of the
10167              logical expression, make a new logical expression, and apply
10168              the inverse distributive law.  This also can't be done
10169              for some (ashiftrt (xor)).  */
10170           if (CONST_INT_P (XEXP (varop, 1))
10171              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10172                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10173                                              shift_mode)))
10174             {
10175               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10176                                               XEXP (varop, 0), count);
10177               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10178                                               XEXP (varop, 1), count);
10179
10180               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10181                                            lhs, rhs);
10182               varop = apply_distributive_law (varop);
10183
10184               count = 0;
10185               continue;
10186             }
10187           break;
10188
10189         case EQ:
10190           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10191              says that the sign bit can be tested, FOO has mode MODE, C is
10192              GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10193              that may be nonzero.  */
10194           if (code == LSHIFTRT
10195               && XEXP (varop, 1) == const0_rtx
10196               && GET_MODE (XEXP (varop, 0)) == result_mode
10197               && count == (GET_MODE_PRECISION (result_mode) - 1)
10198               && HWI_COMPUTABLE_MODE_P (result_mode)
10199               && STORE_FLAG_VALUE == -1
10200               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10201               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10202                                   &complement_p))
10203             {
10204               varop = XEXP (varop, 0);
10205               count = 0;
10206               continue;
10207             }
10208           break;
10209
10210         case NEG:
10211           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10212              than the number of bits in the mode is equivalent to A.  */
10213           if (code == LSHIFTRT
10214               && count == (GET_MODE_PRECISION (result_mode) - 1)
10215               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10216             {
10217               varop = XEXP (varop, 0);
10218               count = 0;
10219               continue;
10220             }
10221
10222           /* NEG commutes with ASHIFT since it is multiplication.  Move the
10223              NEG outside to allow shifts to combine.  */
10224           if (code == ASHIFT
10225               && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10226                                   &complement_p))
10227             {
10228               varop = XEXP (varop, 0);
10229               continue;
10230             }
10231           break;
10232
10233         case PLUS:
10234           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10235              is one less than the number of bits in the mode is
10236              equivalent to (xor A 1).  */
10237           if (code == LSHIFTRT
10238               && count == (GET_MODE_PRECISION (result_mode) - 1)
10239               && XEXP (varop, 1) == constm1_rtx
10240               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10241               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10242                                   &complement_p))
10243             {
10244               count = 0;
10245               varop = XEXP (varop, 0);
10246               continue;
10247             }
10248
10249           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10250              that might be nonzero in BAR are those being shifted out and those
10251              bits are known zero in FOO, we can replace the PLUS with FOO.
10252              Similarly in the other operand order.  This code occurs when
10253              we are computing the size of a variable-size array.  */
10254
10255           if ((code == ASHIFTRT || code == LSHIFTRT)
10256               && count < HOST_BITS_PER_WIDE_INT
10257               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10258               && (nonzero_bits (XEXP (varop, 1), result_mode)
10259                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10260             {
10261               varop = XEXP (varop, 0);
10262               continue;
10263             }
10264           else if ((code == ASHIFTRT || code == LSHIFTRT)
10265                    && count < HOST_BITS_PER_WIDE_INT
10266                    && HWI_COMPUTABLE_MODE_P (result_mode)
10267                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10268                             >> count)
10269                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10270                             & nonzero_bits (XEXP (varop, 1),
10271                                                  result_mode)))
10272             {
10273               varop = XEXP (varop, 1);
10274               continue;
10275             }
10276
10277           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
10278           if (code == ASHIFT
10279               && CONST_INT_P (XEXP (varop, 1))
10280               && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10281                                                          XEXP (varop, 1),
10282                                                          GEN_INT (count))) != 0
10283               && CONST_INT_P (new_rtx)
10284               && merge_outer_ops (&outer_op, &outer_const, PLUS,
10285                                   INTVAL (new_rtx), result_mode, &complement_p))
10286             {
10287               varop = XEXP (varop, 0);
10288               continue;
10289             }
10290
10291           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10292              signbit', and attempt to change the PLUS to an XOR and move it to
10293              the outer operation as is done above in the AND/IOR/XOR case
10294              leg for shift(logical). See details in logical handling above
10295              for reasoning in doing so.  */
10296           if (code == LSHIFTRT
10297               && CONST_INT_P (XEXP (varop, 1))
10298               && mode_signbit_p (result_mode, XEXP (varop, 1))
10299               && (new_rtx = simplify_const_binary_operation (code, result_mode,
10300                                                          XEXP (varop, 1),
10301                                                          GEN_INT (count))) != 0
10302               && CONST_INT_P (new_rtx)
10303               && merge_outer_ops (&outer_op, &outer_const, XOR,
10304                                   INTVAL (new_rtx), result_mode, &complement_p))
10305             {
10306               varop = XEXP (varop, 0);
10307               continue;
10308             }
10309
10310           break;
10311
10312         case MINUS:
10313           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10314              with C the size of VAROP - 1 and the shift is logical if
10315              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10316              we have a (gt X 0) operation.  If the shift is arithmetic with
10317              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10318              we have a (neg (gt X 0)) operation.  */
10319
10320           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10321               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10322               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10323               && (code == LSHIFTRT || code == ASHIFTRT)
10324               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10325               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10326               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10327             {
10328               count = 0;
10329               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10330                                   const0_rtx);
10331
10332               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10333                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10334
10335               continue;
10336             }
10337           break;
10338
10339         case TRUNCATE:
10340           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10341              if the truncate does not affect the value.  */
10342           if (code == LSHIFTRT
10343               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10344               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10345               && (INTVAL (XEXP (XEXP (varop, 0), 1))
10346                   >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10347                       - GET_MODE_PRECISION (GET_MODE (varop)))))
10348             {
10349               rtx varop_inner = XEXP (varop, 0);
10350
10351               varop_inner
10352                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10353                                     XEXP (varop_inner, 0),
10354                                     GEN_INT
10355                                     (count + INTVAL (XEXP (varop_inner, 1))));
10356               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10357               count = 0;
10358               continue;
10359             }
10360           break;
10361
10362         default:
10363           break;
10364         }
10365
10366       break;
10367     }
10368
10369   shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10370                                      outer_op, outer_const);
10371
10372   /* We have now finished analyzing the shift.  The result should be
10373      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
10374      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10375      to the result of the shift.  OUTER_CONST is the relevant constant,
10376      but we must turn off all bits turned off in the shift.  */
10377
10378   if (outer_op == UNKNOWN
10379       && orig_code == code && orig_count == count
10380       && varop == orig_varop
10381       && shift_mode == GET_MODE (varop))
10382     return NULL_RTX;
10383
10384   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10385   varop = gen_lowpart (shift_mode, varop);
10386   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10387     return NULL_RTX;
10388
10389   /* If we have an outer operation and we just made a shift, it is
10390      possible that we could have simplified the shift were it not
10391      for the outer operation.  So try to do the simplification
10392      recursively.  */
10393
10394   if (outer_op != UNKNOWN)
10395     x = simplify_shift_const_1 (code, shift_mode, varop, count);
10396   else
10397     x = NULL_RTX;
10398
10399   if (x == NULL_RTX)
10400     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10401
10402   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10403      turn off all the bits that the shift would have turned off.  */
10404   if (orig_code == LSHIFTRT && result_mode != shift_mode)
10405     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10406                                 GET_MODE_MASK (result_mode) >> orig_count);
10407
10408   /* Do the remainder of the processing in RESULT_MODE.  */
10409   x = gen_lowpart_or_truncate (result_mode, x);
10410
10411   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10412      operation.  */
10413   if (complement_p)
10414     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10415
10416   if (outer_op != UNKNOWN)
10417     {
10418       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10419           && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10420         outer_const = trunc_int_for_mode (outer_const, result_mode);
10421
10422       if (outer_op == AND)
10423         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10424       else if (outer_op == SET)
10425         {
10426           /* This means that we have determined that the result is
10427              equivalent to a constant.  This should be rare.  */
10428           if (!side_effects_p (x))
10429             x = GEN_INT (outer_const);
10430         }
10431       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10432         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10433       else
10434         x = simplify_gen_binary (outer_op, result_mode, x,
10435                                  GEN_INT (outer_const));
10436     }
10437
10438   return x;
10439 }
10440
10441 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
10442    The result of the shift is RESULT_MODE.  If we cannot simplify it,
10443    return X or, if it is NULL, synthesize the expression with
10444    simplify_gen_binary.  Otherwise, return a simplified value.
10445
10446    The shift is normally computed in the widest mode we find in VAROP, as
10447    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10448    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10449
10450 static rtx
10451 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10452                       rtx varop, int count)
10453 {
10454   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10455   if (tem)
10456     return tem;
10457
10458   if (!x)
10459     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10460   if (GET_MODE (x) != result_mode)
10461     x = gen_lowpart (result_mode, x);
10462   return x;
10463 }
10464
10465 \f
10466 /* Like recog, but we receive the address of a pointer to a new pattern.
10467    We try to match the rtx that the pointer points to.
10468    If that fails, we may try to modify or replace the pattern,
10469    storing the replacement into the same pointer object.
10470
10471    Modifications include deletion or addition of CLOBBERs.
10472
10473    PNOTES is a pointer to a location where any REG_UNUSED notes added for
10474    the CLOBBERs are placed.
10475
10476    The value is the final insn code from the pattern ultimately matched,
10477    or -1.  */
10478
10479 static int
10480 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10481 {
10482   rtx pat = *pnewpat;
10483   rtx pat_without_clobbers;
10484   int insn_code_number;
10485   int num_clobbers_to_add = 0;
10486   int i;
10487   rtx notes = NULL_RTX;
10488   rtx old_notes, old_pat;
10489   int old_icode;
10490
10491   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10492      we use to indicate that something didn't match.  If we find such a
10493      thing, force rejection.  */
10494   if (GET_CODE (pat) == PARALLEL)
10495     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10496       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10497           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10498         return -1;
10499
10500   old_pat = PATTERN (insn);
10501   old_notes = REG_NOTES (insn);
10502   PATTERN (insn) = pat;
10503   REG_NOTES (insn) = NULL_RTX;
10504
10505   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10506   if (dump_file && (dump_flags & TDF_DETAILS))
10507     {
10508       if (insn_code_number < 0)
10509         fputs ("Failed to match this instruction:\n", dump_file);
10510       else
10511         fputs ("Successfully matched this instruction:\n", dump_file);
10512       print_rtl_single (dump_file, pat);
10513     }
10514
10515   /* If it isn't, there is the possibility that we previously had an insn
10516      that clobbered some register as a side effect, but the combined
10517      insn doesn't need to do that.  So try once more without the clobbers
10518      unless this represents an ASM insn.  */
10519
10520   if (insn_code_number < 0 && ! check_asm_operands (pat)
10521       && GET_CODE (pat) == PARALLEL)
10522     {
10523       int pos;
10524
10525       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10526         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10527           {
10528             if (i != pos)
10529               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10530             pos++;
10531           }
10532
10533       SUBST_INT (XVECLEN (pat, 0), pos);
10534
10535       if (pos == 1)
10536         pat = XVECEXP (pat, 0, 0);
10537
10538       PATTERN (insn) = pat;
10539       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10540       if (dump_file && (dump_flags & TDF_DETAILS))
10541         {
10542           if (insn_code_number < 0)
10543             fputs ("Failed to match this instruction:\n", dump_file);
10544           else
10545             fputs ("Successfully matched this instruction:\n", dump_file);
10546           print_rtl_single (dump_file, pat);
10547         }
10548     }
10549
10550   pat_without_clobbers = pat;
10551
10552   PATTERN (insn) = old_pat;
10553   REG_NOTES (insn) = old_notes;
10554
10555   /* Recognize all noop sets, these will be killed by followup pass.  */
10556   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10557     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10558
10559   /* If we had any clobbers to add, make a new pattern than contains
10560      them.  Then check to make sure that all of them are dead.  */
10561   if (num_clobbers_to_add)
10562     {
10563       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10564                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
10565                                                   ? (XVECLEN (pat, 0)
10566                                                      + num_clobbers_to_add)
10567                                                   : num_clobbers_to_add + 1));
10568
10569       if (GET_CODE (pat) == PARALLEL)
10570         for (i = 0; i < XVECLEN (pat, 0); i++)
10571           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10572       else
10573         XVECEXP (newpat, 0, 0) = pat;
10574
10575       add_clobbers (newpat, insn_code_number);
10576
10577       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10578            i < XVECLEN (newpat, 0); i++)
10579         {
10580           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10581               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10582             return -1;
10583           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10584             {
10585               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10586               notes = alloc_reg_note (REG_UNUSED,
10587                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
10588             }
10589         }
10590       pat = newpat;
10591     }
10592
10593   if (insn_code_number >= 0
10594       && insn_code_number != NOOP_MOVE_INSN_CODE)
10595     {
10596       old_pat = PATTERN (insn);
10597       old_notes = REG_NOTES (insn);
10598       old_icode = INSN_CODE (insn);
10599       PATTERN (insn) = pat;
10600       REG_NOTES (insn) = notes;
10601
10602       /* Allow targets to reject combined insn.  */
10603       if (!targetm.legitimate_combined_insn (insn))
10604         {
10605           if (dump_file && (dump_flags & TDF_DETAILS))
10606             fputs ("Instruction not appropriate for target.",
10607                    dump_file);
10608
10609           /* Callers expect recog_for_combine to strip
10610              clobbers from the pattern on failure.  */
10611           pat = pat_without_clobbers;
10612           notes = NULL_RTX;
10613
10614           insn_code_number = -1;
10615         }
10616
10617       PATTERN (insn) = old_pat;
10618       REG_NOTES (insn) = old_notes;
10619       INSN_CODE (insn) = old_icode;
10620     }
10621
10622   *pnewpat = pat;
10623   *pnotes = notes;
10624
10625   return insn_code_number;
10626 }
10627 \f
10628 /* Like gen_lowpart_general but for use by combine.  In combine it
10629    is not possible to create any new pseudoregs.  However, it is
10630    safe to create invalid memory addresses, because combine will
10631    try to recognize them and all they will do is make the combine
10632    attempt fail.
10633
10634    If for some reason this cannot do its job, an rtx
10635    (clobber (const_int 0)) is returned.
10636    An insn containing that will not be recognized.  */
10637
10638 static rtx
10639 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10640 {
10641   enum machine_mode imode = GET_MODE (x);
10642   unsigned int osize = GET_MODE_SIZE (omode);
10643   unsigned int isize = GET_MODE_SIZE (imode);
10644   rtx result;
10645
10646   if (omode == imode)
10647     return x;
10648
10649   /* We can only support MODE being wider than a word if X is a
10650      constant integer or has a mode the same size.  */
10651   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10652       && ! (CONST_SCALAR_INT_P (x) || isize == osize))
10653     goto fail;
10654
10655   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
10656      won't know what to do.  So we will strip off the SUBREG here and
10657      process normally.  */
10658   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10659     {
10660       x = SUBREG_REG (x);
10661
10662       /* For use in case we fall down into the address adjustments
10663          further below, we need to adjust the known mode and size of
10664          x; imode and isize, since we just adjusted x.  */
10665       imode = GET_MODE (x);
10666
10667       if (imode == omode)
10668         return x;
10669
10670       isize = GET_MODE_SIZE (imode);
10671     }
10672
10673   result = gen_lowpart_common (omode, x);
10674
10675   if (result)
10676     return result;
10677
10678   if (MEM_P (x))
10679     {
10680       int offset = 0;
10681
10682       /* Refuse to work on a volatile memory ref or one with a mode-dependent
10683          address.  */
10684       if (MEM_VOLATILE_P (x)
10685           || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
10686         goto fail;
10687
10688       /* If we want to refer to something bigger than the original memref,
10689          generate a paradoxical subreg instead.  That will force a reload
10690          of the original memref X.  */
10691       if (isize < osize)
10692         return gen_rtx_SUBREG (omode, x, 0);
10693
10694       if (WORDS_BIG_ENDIAN)
10695         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10696
10697       /* Adjust the address so that the address-after-the-data is
10698          unchanged.  */
10699       if (BYTES_BIG_ENDIAN)
10700         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10701
10702       return adjust_address_nv (x, omode, offset);
10703     }
10704
10705   /* If X is a comparison operator, rewrite it in a new mode.  This
10706      probably won't match, but may allow further simplifications.  */
10707   else if (COMPARISON_P (x))
10708     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10709
10710   /* If we couldn't simplify X any other way, just enclose it in a
10711      SUBREG.  Normally, this SUBREG won't match, but some patterns may
10712      include an explicit SUBREG or we may simplify it further in combine.  */
10713   else
10714     {
10715       int offset = 0;
10716       rtx res;
10717
10718       offset = subreg_lowpart_offset (omode, imode);
10719       if (imode == VOIDmode)
10720         {
10721           imode = int_mode_for_mode (omode);
10722           x = gen_lowpart_common (imode, x);
10723           if (x == NULL)
10724             goto fail;
10725         }
10726       res = simplify_gen_subreg (omode, x, imode, offset);
10727       if (res)
10728         return res;
10729     }
10730
10731  fail:
10732   return gen_rtx_CLOBBER (omode, const0_rtx);
10733 }
10734 \f
10735 /* Try to simplify a comparison between OP0 and a constant OP1,
10736    where CODE is the comparison code that will be tested, into a
10737    (CODE OP0 const0_rtx) form.
10738
10739    The result is a possibly different comparison code to use.
10740    *POP1 may be updated.  */
10741
10742 static enum rtx_code
10743 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10744 {
10745   enum machine_mode mode = GET_MODE (op0);
10746   unsigned int mode_width = GET_MODE_PRECISION (mode);
10747   HOST_WIDE_INT const_op = INTVAL (*pop1);
10748
10749   /* Get the constant we are comparing against and turn off all bits
10750      not on in our mode.  */
10751   if (mode != VOIDmode)
10752     const_op = trunc_int_for_mode (const_op, mode);
10753
10754   /* If we are comparing against a constant power of two and the value
10755      being compared can only have that single bit nonzero (e.g., it was
10756      `and'ed with that bit), we can replace this with a comparison
10757      with zero.  */
10758   if (const_op
10759       && (code == EQ || code == NE || code == GE || code == GEU
10760           || code == LT || code == LTU)
10761       && mode_width <= HOST_BITS_PER_WIDE_INT
10762       && exact_log2 (const_op & GET_MODE_MASK (mode)) >= 0
10763       && (nonzero_bits (op0, mode)
10764           == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode))))
10765     {
10766       code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10767       const_op = 0;
10768     }
10769
10770   /* Similarly, if we are comparing a value known to be either -1 or
10771      0 with -1, change it to the opposite comparison against zero.  */
10772   if (const_op == -1
10773       && (code == EQ || code == NE || code == GT || code == LE
10774           || code == GEU || code == LTU)
10775       && num_sign_bit_copies (op0, mode) == mode_width)
10776     {
10777       code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10778       const_op = 0;
10779     }
10780
10781   /* Do some canonicalizations based on the comparison code.  We prefer
10782      comparisons against zero and then prefer equality comparisons.
10783      If we can reduce the size of a constant, we will do that too.  */
10784   switch (code)
10785     {
10786     case LT:
10787       /* < C is equivalent to <= (C - 1) */
10788       if (const_op > 0)
10789         {
10790           const_op -= 1;
10791           code = LE;
10792           /* ... fall through to LE case below.  */
10793         }
10794       else
10795         break;
10796
10797     case LE:
10798       /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10799       if (const_op < 0)
10800         {
10801           const_op += 1;
10802           code = LT;
10803         }
10804
10805       /* If we are doing a <= 0 comparison on a value known to have
10806          a zero sign bit, we can replace this with == 0.  */
10807       else if (const_op == 0
10808                && mode_width <= HOST_BITS_PER_WIDE_INT
10809                && (nonzero_bits (op0, mode)
10810                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10811                == 0)
10812         code = EQ;
10813       break;
10814
10815     case GE:
10816       /* >= C is equivalent to > (C - 1).  */
10817       if (const_op > 0)
10818         {
10819           const_op -= 1;
10820           code = GT;
10821           /* ... fall through to GT below.  */
10822         }
10823       else
10824         break;
10825
10826     case GT:
10827       /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10828       if (const_op < 0)
10829         {
10830           const_op += 1;
10831           code = GE;
10832         }
10833
10834       /* If we are doing a > 0 comparison on a value known to have
10835          a zero sign bit, we can replace this with != 0.  */
10836       else if (const_op == 0
10837                && mode_width <= HOST_BITS_PER_WIDE_INT
10838                && (nonzero_bits (op0, mode)
10839                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10840                == 0)
10841         code = NE;
10842       break;
10843
10844     case LTU:
10845       /* < C is equivalent to <= (C - 1).  */
10846       if (const_op > 0)
10847         {
10848           const_op -= 1;
10849           code = LEU;
10850           /* ... fall through ...  */
10851         }
10852       /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10853       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10854                && (unsigned HOST_WIDE_INT) const_op
10855                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10856         {
10857           const_op = 0;
10858           code = GE;
10859           break;
10860         }
10861       else
10862         break;
10863
10864     case LEU:
10865       /* unsigned <= 0 is equivalent to == 0 */
10866       if (const_op == 0)
10867         code = EQ;
10868       /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10869       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10870                && (unsigned HOST_WIDE_INT) const_op
10871                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10872         {
10873           const_op = 0;
10874           code = GE;
10875         }
10876       break;
10877
10878     case GEU:
10879       /* >= C is equivalent to > (C - 1).  */
10880       if (const_op > 1)
10881         {
10882           const_op -= 1;
10883           code = GTU;
10884           /* ... fall through ...  */
10885         }
10886
10887       /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
10888       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10889                && (unsigned HOST_WIDE_INT) const_op
10890                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10891         {
10892           const_op = 0;
10893           code = LT;
10894           break;
10895         }
10896       else
10897         break;
10898
10899     case GTU:
10900       /* unsigned > 0 is equivalent to != 0 */
10901       if (const_op == 0)
10902         code = NE;
10903       /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
10904       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10905                && (unsigned HOST_WIDE_INT) const_op
10906                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10907         {
10908           const_op = 0;
10909           code = LT;
10910         }
10911       break;
10912
10913     default:
10914       break;
10915     }
10916
10917   *pop1 = GEN_INT (const_op);
10918   return code;
10919 }
10920 \f
10921 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10922    comparison code that will be tested.
10923
10924    The result is a possibly different comparison code to use.  *POP0 and
10925    *POP1 may be updated.
10926
10927    It is possible that we might detect that a comparison is either always
10928    true or always false.  However, we do not perform general constant
10929    folding in combine, so this knowledge isn't useful.  Such tautologies
10930    should have been detected earlier.  Hence we ignore all such cases.  */
10931
10932 static enum rtx_code
10933 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10934 {
10935   rtx op0 = *pop0;
10936   rtx op1 = *pop1;
10937   rtx tem, tem1;
10938   int i;
10939   enum machine_mode mode, tmode;
10940
10941   /* Try a few ways of applying the same transformation to both operands.  */
10942   while (1)
10943     {
10944 #ifndef WORD_REGISTER_OPERATIONS
10945       /* The test below this one won't handle SIGN_EXTENDs on these machines,
10946          so check specially.  */
10947       if (code != GTU && code != GEU && code != LTU && code != LEU
10948           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10949           && GET_CODE (XEXP (op0, 0)) == ASHIFT
10950           && GET_CODE (XEXP (op1, 0)) == ASHIFT
10951           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10952           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10953           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10954               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10955           && CONST_INT_P (XEXP (op0, 1))
10956           && XEXP (op0, 1) == XEXP (op1, 1)
10957           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10958           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10959           && (INTVAL (XEXP (op0, 1))
10960               == (GET_MODE_PRECISION (GET_MODE (op0))
10961                   - (GET_MODE_PRECISION
10962                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10963         {
10964           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10965           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10966         }
10967 #endif
10968
10969       /* If both operands are the same constant shift, see if we can ignore the
10970          shift.  We can if the shift is a rotate or if the bits shifted out of
10971          this shift are known to be zero for both inputs and if the type of
10972          comparison is compatible with the shift.  */
10973       if (GET_CODE (op0) == GET_CODE (op1)
10974           && HWI_COMPUTABLE_MODE_P (GET_MODE(op0))
10975           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10976               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10977                   && (code != GT && code != LT && code != GE && code != LE))
10978               || (GET_CODE (op0) == ASHIFTRT
10979                   && (code != GTU && code != LTU
10980                       && code != GEU && code != LEU)))
10981           && CONST_INT_P (XEXP (op0, 1))
10982           && INTVAL (XEXP (op0, 1)) >= 0
10983           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10984           && XEXP (op0, 1) == XEXP (op1, 1))
10985         {
10986           enum machine_mode mode = GET_MODE (op0);
10987           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10988           int shift_count = INTVAL (XEXP (op0, 1));
10989
10990           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10991             mask &= (mask >> shift_count) << shift_count;
10992           else if (GET_CODE (op0) == ASHIFT)
10993             mask = (mask & (mask << shift_count)) >> shift_count;
10994
10995           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10996               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10997             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10998           else
10999             break;
11000         }
11001
11002       /* If both operands are AND's of a paradoxical SUBREG by constant, the
11003          SUBREGs are of the same mode, and, in both cases, the AND would
11004          be redundant if the comparison was done in the narrower mode,
11005          do the comparison in the narrower mode (e.g., we are AND'ing with 1
11006          and the operand's possibly nonzero bits are 0xffffff01; in that case
11007          if we only care about QImode, we don't need the AND).  This case
11008          occurs if the output mode of an scc insn is not SImode and
11009          STORE_FLAG_VALUE == 1 (e.g., the 386).
11010
11011          Similarly, check for a case where the AND's are ZERO_EXTEND
11012          operations from some narrower mode even though a SUBREG is not
11013          present.  */
11014
11015       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11016                && CONST_INT_P (XEXP (op0, 1))
11017                && CONST_INT_P (XEXP (op1, 1)))
11018         {
11019           rtx inner_op0 = XEXP (op0, 0);
11020           rtx inner_op1 = XEXP (op1, 0);
11021           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11022           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11023           int changed = 0;
11024
11025           if (paradoxical_subreg_p (inner_op0)
11026               && GET_CODE (inner_op1) == SUBREG
11027               && (GET_MODE (SUBREG_REG (inner_op0))
11028                   == GET_MODE (SUBREG_REG (inner_op1)))
11029               && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11030                   <= HOST_BITS_PER_WIDE_INT)
11031               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11032                                              GET_MODE (SUBREG_REG (inner_op0)))))
11033               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11034                                              GET_MODE (SUBREG_REG (inner_op1))))))
11035             {
11036               op0 = SUBREG_REG (inner_op0);
11037               op1 = SUBREG_REG (inner_op1);
11038
11039               /* The resulting comparison is always unsigned since we masked
11040                  off the original sign bit.  */
11041               code = unsigned_condition (code);
11042
11043               changed = 1;
11044             }
11045
11046           else if (c0 == c1)
11047             for (tmode = GET_CLASS_NARROWEST_MODE
11048                  (GET_MODE_CLASS (GET_MODE (op0)));
11049                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11050               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11051                 {
11052                   op0 = gen_lowpart (tmode, inner_op0);
11053                   op1 = gen_lowpart (tmode, inner_op1);
11054                   code = unsigned_condition (code);
11055                   changed = 1;
11056                   break;
11057                 }
11058
11059           if (! changed)
11060             break;
11061         }
11062
11063       /* If both operands are NOT, we can strip off the outer operation
11064          and adjust the comparison code for swapped operands; similarly for
11065          NEG, except that this must be an equality comparison.  */
11066       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11067                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11068                    && (code == EQ || code == NE)))
11069         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11070
11071       else
11072         break;
11073     }
11074
11075   /* If the first operand is a constant, swap the operands and adjust the
11076      comparison code appropriately, but don't do this if the second operand
11077      is already a constant integer.  */
11078   if (swap_commutative_operands_p (op0, op1))
11079     {
11080       tem = op0, op0 = op1, op1 = tem;
11081       code = swap_condition (code);
11082     }
11083
11084   /* We now enter a loop during which we will try to simplify the comparison.
11085      For the most part, we only are concerned with comparisons with zero,
11086      but some things may really be comparisons with zero but not start
11087      out looking that way.  */
11088
11089   while (CONST_INT_P (op1))
11090     {
11091       enum machine_mode mode = GET_MODE (op0);
11092       unsigned int mode_width = GET_MODE_PRECISION (mode);
11093       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11094       int equality_comparison_p;
11095       int sign_bit_comparison_p;
11096       int unsigned_comparison_p;
11097       HOST_WIDE_INT const_op;
11098
11099       /* We only want to handle integral modes.  This catches VOIDmode,
11100          CCmode, and the floating-point modes.  An exception is that we
11101          can handle VOIDmode if OP0 is a COMPARE or a comparison
11102          operation.  */
11103
11104       if (GET_MODE_CLASS (mode) != MODE_INT
11105           && ! (mode == VOIDmode
11106                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11107         break;
11108
11109       /* Try to simplify the compare to constant, possibly changing the
11110          comparison op, and/or changing op1 to zero.  */
11111       code = simplify_compare_const (code, op0, &op1);
11112       const_op = INTVAL (op1);
11113
11114       /* Compute some predicates to simplify code below.  */
11115
11116       equality_comparison_p = (code == EQ || code == NE);
11117       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11118       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11119                                || code == GEU);
11120
11121       /* If this is a sign bit comparison and we can do arithmetic in
11122          MODE, say that we will only be needing the sign bit of OP0.  */
11123       if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11124         op0 = force_to_mode (op0, mode,
11125                              (unsigned HOST_WIDE_INT) 1
11126                              << (GET_MODE_PRECISION (mode) - 1),
11127                              0);
11128
11129       /* Now try cases based on the opcode of OP0.  If none of the cases
11130          does a "continue", we exit this loop immediately after the
11131          switch.  */
11132
11133       switch (GET_CODE (op0))
11134         {
11135         case ZERO_EXTRACT:
11136           /* If we are extracting a single bit from a variable position in
11137              a constant that has only a single bit set and are comparing it
11138              with zero, we can convert this into an equality comparison
11139              between the position and the location of the single bit.  */
11140           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11141              have already reduced the shift count modulo the word size.  */
11142           if (!SHIFT_COUNT_TRUNCATED
11143               && CONST_INT_P (XEXP (op0, 0))
11144               && XEXP (op0, 1) == const1_rtx
11145               && equality_comparison_p && const_op == 0
11146               && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11147             {
11148               if (BITS_BIG_ENDIAN)
11149                 i = BITS_PER_WORD - 1 - i;
11150
11151               op0 = XEXP (op0, 2);
11152               op1 = GEN_INT (i);
11153               const_op = i;
11154
11155               /* Result is nonzero iff shift count is equal to I.  */
11156               code = reverse_condition (code);
11157               continue;
11158             }
11159
11160           /* ... fall through ...  */
11161
11162         case SIGN_EXTRACT:
11163           tem = expand_compound_operation (op0);
11164           if (tem != op0)
11165             {
11166               op0 = tem;
11167               continue;
11168             }
11169           break;
11170
11171         case NOT:
11172           /* If testing for equality, we can take the NOT of the constant.  */
11173           if (equality_comparison_p
11174               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11175             {
11176               op0 = XEXP (op0, 0);
11177               op1 = tem;
11178               continue;
11179             }
11180
11181           /* If just looking at the sign bit, reverse the sense of the
11182              comparison.  */
11183           if (sign_bit_comparison_p)
11184             {
11185               op0 = XEXP (op0, 0);
11186               code = (code == GE ? LT : GE);
11187               continue;
11188             }
11189           break;
11190
11191         case NEG:
11192           /* If testing for equality, we can take the NEG of the constant.  */
11193           if (equality_comparison_p
11194               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11195             {
11196               op0 = XEXP (op0, 0);
11197               op1 = tem;
11198               continue;
11199             }
11200
11201           /* The remaining cases only apply to comparisons with zero.  */
11202           if (const_op != 0)
11203             break;
11204
11205           /* When X is ABS or is known positive,
11206              (neg X) is < 0 if and only if X != 0.  */
11207
11208           if (sign_bit_comparison_p
11209               && (GET_CODE (XEXP (op0, 0)) == ABS
11210                   || (mode_width <= HOST_BITS_PER_WIDE_INT
11211                       && (nonzero_bits (XEXP (op0, 0), mode)
11212                           & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11213                          == 0)))
11214             {
11215               op0 = XEXP (op0, 0);
11216               code = (code == LT ? NE : EQ);
11217               continue;
11218             }
11219
11220           /* If we have NEG of something whose two high-order bits are the
11221              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
11222           if (num_sign_bit_copies (op0, mode) >= 2)
11223             {
11224               op0 = XEXP (op0, 0);
11225               code = swap_condition (code);
11226               continue;
11227             }
11228           break;
11229
11230         case ROTATE:
11231           /* If we are testing equality and our count is a constant, we
11232              can perform the inverse operation on our RHS.  */
11233           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11234               && (tem = simplify_binary_operation (ROTATERT, mode,
11235                                                    op1, XEXP (op0, 1))) != 0)
11236             {
11237               op0 = XEXP (op0, 0);
11238               op1 = tem;
11239               continue;
11240             }
11241
11242           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11243              a particular bit.  Convert it to an AND of a constant of that
11244              bit.  This will be converted into a ZERO_EXTRACT.  */
11245           if (const_op == 0 && sign_bit_comparison_p
11246               && CONST_INT_P (XEXP (op0, 1))
11247               && mode_width <= HOST_BITS_PER_WIDE_INT)
11248             {
11249               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11250                                             ((unsigned HOST_WIDE_INT) 1
11251                                              << (mode_width - 1
11252                                                  - INTVAL (XEXP (op0, 1)))));
11253               code = (code == LT ? NE : EQ);
11254               continue;
11255             }
11256
11257           /* Fall through.  */
11258
11259         case ABS:
11260           /* ABS is ignorable inside an equality comparison with zero.  */
11261           if (const_op == 0 && equality_comparison_p)
11262             {
11263               op0 = XEXP (op0, 0);
11264               continue;
11265             }
11266           break;
11267
11268         case SIGN_EXTEND:
11269           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11270              (compare FOO CONST) if CONST fits in FOO's mode and we
11271              are either testing inequality or have an unsigned
11272              comparison with ZERO_EXTEND or a signed comparison with
11273              SIGN_EXTEND.  But don't do it if we don't have a compare
11274              insn of the given mode, since we'd have to revert it
11275              later on, and then we wouldn't know whether to sign- or
11276              zero-extend.  */
11277           mode = GET_MODE (XEXP (op0, 0));
11278           if (GET_MODE_CLASS (mode) == MODE_INT
11279               && ! unsigned_comparison_p
11280               && HWI_COMPUTABLE_MODE_P (mode)
11281               && trunc_int_for_mode (const_op, mode) == const_op
11282               && have_insn_for (COMPARE, mode))
11283             {
11284               op0 = XEXP (op0, 0);
11285               continue;
11286             }
11287           break;
11288
11289         case SUBREG:
11290           /* Check for the case where we are comparing A - C1 with C2, that is
11291
11292                (subreg:MODE (plus (A) (-C1))) op (C2)
11293
11294              with C1 a constant, and try to lift the SUBREG, i.e. to do the
11295              comparison in the wider mode.  One of the following two conditions
11296              must be true in order for this to be valid:
11297
11298                1. The mode extension results in the same bit pattern being added
11299                   on both sides and the comparison is equality or unsigned.  As
11300                   C2 has been truncated to fit in MODE, the pattern can only be
11301                   all 0s or all 1s.
11302
11303                2. The mode extension results in the sign bit being copied on
11304                   each side.
11305
11306              The difficulty here is that we have predicates for A but not for
11307              (A - C1) so we need to check that C1 is within proper bounds so
11308              as to perturbate A as little as possible.  */
11309
11310           if (mode_width <= HOST_BITS_PER_WIDE_INT
11311               && subreg_lowpart_p (op0)
11312               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11313               && GET_CODE (SUBREG_REG (op0)) == PLUS
11314               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11315             {
11316               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11317               rtx a = XEXP (SUBREG_REG (op0), 0);
11318               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11319
11320               if ((c1 > 0
11321                    && (unsigned HOST_WIDE_INT) c1
11322                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11323                    && (equality_comparison_p || unsigned_comparison_p)
11324                    /* (A - C1) zero-extends if it is positive and sign-extends
11325                       if it is negative, C2 both zero- and sign-extends.  */
11326                    && ((0 == (nonzero_bits (a, inner_mode)
11327                               & ~GET_MODE_MASK (mode))
11328                         && const_op >= 0)
11329                        /* (A - C1) sign-extends if it is positive and 1-extends
11330                           if it is negative, C2 both sign- and 1-extends.  */
11331                        || (num_sign_bit_copies (a, inner_mode)
11332                            > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11333                                              - mode_width)
11334                            && const_op < 0)))
11335                   || ((unsigned HOST_WIDE_INT) c1
11336                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11337                       /* (A - C1) always sign-extends, like C2.  */
11338                       && num_sign_bit_copies (a, inner_mode)
11339                          > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11340                                            - (mode_width - 1))))
11341                 {
11342                   op0 = SUBREG_REG (op0);
11343                   continue;
11344                 }
11345             }
11346
11347           /* If the inner mode is narrower and we are extracting the low part,
11348              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
11349           if (subreg_lowpart_p (op0)
11350               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11351             /* Fall through */ ;
11352           else
11353             break;
11354
11355           /* ... fall through ...  */
11356
11357         case ZERO_EXTEND:
11358           mode = GET_MODE (XEXP (op0, 0));
11359           if (GET_MODE_CLASS (mode) == MODE_INT
11360               && (unsigned_comparison_p || equality_comparison_p)
11361               && HWI_COMPUTABLE_MODE_P (mode)
11362               && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11363               && const_op >= 0
11364               && have_insn_for (COMPARE, mode))
11365             {
11366               op0 = XEXP (op0, 0);
11367               continue;
11368             }
11369           break;
11370
11371         case PLUS:
11372           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
11373              this for equality comparisons due to pathological cases involving
11374              overflows.  */
11375           if (equality_comparison_p
11376               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11377                                                         op1, XEXP (op0, 1))))
11378             {
11379               op0 = XEXP (op0, 0);
11380               op1 = tem;
11381               continue;
11382             }
11383
11384           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
11385           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11386               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11387             {
11388               op0 = XEXP (XEXP (op0, 0), 0);
11389               code = (code == LT ? EQ : NE);
11390               continue;
11391             }
11392           break;
11393
11394         case MINUS:
11395           /* We used to optimize signed comparisons against zero, but that
11396              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
11397              arrive here as equality comparisons, or (GEU, LTU) are
11398              optimized away.  No need to special-case them.  */
11399
11400           /* (eq (minus A B) C) -> (eq A (plus B C)) or
11401              (eq B (minus A C)), whichever simplifies.  We can only do
11402              this for equality comparisons due to pathological cases involving
11403              overflows.  */
11404           if (equality_comparison_p
11405               && 0 != (tem = simplify_binary_operation (PLUS, mode,
11406                                                         XEXP (op0, 1), op1)))
11407             {
11408               op0 = XEXP (op0, 0);
11409               op1 = tem;
11410               continue;
11411             }
11412
11413           if (equality_comparison_p
11414               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11415                                                         XEXP (op0, 0), op1)))
11416             {
11417               op0 = XEXP (op0, 1);
11418               op1 = tem;
11419               continue;
11420             }
11421
11422           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11423              of bits in X minus 1, is one iff X > 0.  */
11424           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11425               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11426               && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11427               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11428             {
11429               op0 = XEXP (op0, 1);
11430               code = (code == GE ? LE : GT);
11431               continue;
11432             }
11433           break;
11434
11435         case XOR:
11436           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
11437              if C is zero or B is a constant.  */
11438           if (equality_comparison_p
11439               && 0 != (tem = simplify_binary_operation (XOR, mode,
11440                                                         XEXP (op0, 1), op1)))
11441             {
11442               op0 = XEXP (op0, 0);
11443               op1 = tem;
11444               continue;
11445             }
11446           break;
11447
11448         case EQ:  case NE:
11449         case UNEQ:  case LTGT:
11450         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
11451         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
11452         case UNORDERED: case ORDERED:
11453           /* We can't do anything if OP0 is a condition code value, rather
11454              than an actual data value.  */
11455           if (const_op != 0
11456               || CC0_P (XEXP (op0, 0))
11457               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11458             break;
11459
11460           /* Get the two operands being compared.  */
11461           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11462             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11463           else
11464             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11465
11466           /* Check for the cases where we simply want the result of the
11467              earlier test or the opposite of that result.  */
11468           if (code == NE || code == EQ
11469               || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11470                   && (code == LT || code == GE)))
11471             {
11472               enum rtx_code new_code;
11473               if (code == LT || code == NE)
11474                 new_code = GET_CODE (op0);
11475               else
11476                 new_code = reversed_comparison_code (op0, NULL);
11477
11478               if (new_code != UNKNOWN)
11479                 {
11480                   code = new_code;
11481                   op0 = tem;
11482                   op1 = tem1;
11483                   continue;
11484                 }
11485             }
11486           break;
11487
11488         case IOR:
11489           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11490              iff X <= 0.  */
11491           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11492               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11493               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11494             {
11495               op0 = XEXP (op0, 1);
11496               code = (code == GE ? GT : LE);
11497               continue;
11498             }
11499           break;
11500
11501         case AND:
11502           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
11503              will be converted to a ZERO_EXTRACT later.  */
11504           if (const_op == 0 && equality_comparison_p
11505               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11506               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11507             {
11508               op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11509                                       XEXP (XEXP (op0, 0), 1));
11510               op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11511               continue;
11512             }
11513
11514           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11515              zero and X is a comparison and C1 and C2 describe only bits set
11516              in STORE_FLAG_VALUE, we can compare with X.  */
11517           if (const_op == 0 && equality_comparison_p
11518               && mode_width <= HOST_BITS_PER_WIDE_INT
11519               && CONST_INT_P (XEXP (op0, 1))
11520               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11521               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11522               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11523               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11524             {
11525               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11526                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
11527               if ((~STORE_FLAG_VALUE & mask) == 0
11528                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11529                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11530                           && COMPARISON_P (tem))))
11531                 {
11532                   op0 = XEXP (XEXP (op0, 0), 0);
11533                   continue;
11534                 }
11535             }
11536
11537           /* If we are doing an equality comparison of an AND of a bit equal
11538              to the sign bit, replace this with a LT or GE comparison of
11539              the underlying value.  */
11540           if (equality_comparison_p
11541               && const_op == 0
11542               && CONST_INT_P (XEXP (op0, 1))
11543               && mode_width <= HOST_BITS_PER_WIDE_INT
11544               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11545                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11546             {
11547               op0 = XEXP (op0, 0);
11548               code = (code == EQ ? GE : LT);
11549               continue;
11550             }
11551
11552           /* If this AND operation is really a ZERO_EXTEND from a narrower
11553              mode, the constant fits within that mode, and this is either an
11554              equality or unsigned comparison, try to do this comparison in
11555              the narrower mode.
11556
11557              Note that in:
11558
11559              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11560              -> (ne:DI (reg:SI 4) (const_int 0))
11561
11562              unless TRULY_NOOP_TRUNCATION allows it or the register is
11563              known to hold a value of the required mode the
11564              transformation is invalid.  */
11565           if ((equality_comparison_p || unsigned_comparison_p)
11566               && CONST_INT_P (XEXP (op0, 1))
11567               && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11568                                    & GET_MODE_MASK (mode))
11569                                   + 1)) >= 0
11570               && const_op >> i == 0
11571               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11572               && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11573                   || (REG_P (XEXP (op0, 0))
11574                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11575             {
11576               op0 = gen_lowpart (tmode, XEXP (op0, 0));
11577               continue;
11578             }
11579
11580           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11581              fits in both M1 and M2 and the SUBREG is either paradoxical
11582              or represents the low part, permute the SUBREG and the AND
11583              and try again.  */
11584           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11585             {
11586               unsigned HOST_WIDE_INT c1;
11587               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11588               /* Require an integral mode, to avoid creating something like
11589                  (AND:SF ...).  */
11590               if (SCALAR_INT_MODE_P (tmode)
11591                   /* It is unsafe to commute the AND into the SUBREG if the
11592                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11593                      not defined.  As originally written the upper bits
11594                      have a defined value due to the AND operation.
11595                      However, if we commute the AND inside the SUBREG then
11596                      they no longer have defined values and the meaning of
11597                      the code has been changed.  */
11598                   && (0
11599 #ifdef WORD_REGISTER_OPERATIONS
11600                       || (mode_width > GET_MODE_PRECISION (tmode)
11601                           && mode_width <= BITS_PER_WORD)
11602 #endif
11603                       || (mode_width <= GET_MODE_PRECISION (tmode)
11604                           && subreg_lowpart_p (XEXP (op0, 0))))
11605                   && CONST_INT_P (XEXP (op0, 1))
11606                   && mode_width <= HOST_BITS_PER_WIDE_INT
11607                   && HWI_COMPUTABLE_MODE_P (tmode)
11608                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11609                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
11610                   && c1 != mask
11611                   && c1 != GET_MODE_MASK (tmode))
11612                 {
11613                   op0 = simplify_gen_binary (AND, tmode,
11614                                              SUBREG_REG (XEXP (op0, 0)),
11615                                              gen_int_mode (c1, tmode));
11616                   op0 = gen_lowpart (mode, op0);
11617                   continue;
11618                 }
11619             }
11620
11621           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
11622           if (const_op == 0 && equality_comparison_p
11623               && XEXP (op0, 1) == const1_rtx
11624               && GET_CODE (XEXP (op0, 0)) == NOT)
11625             {
11626               op0 = simplify_and_const_int (NULL_RTX, mode,
11627                                             XEXP (XEXP (op0, 0), 0), 1);
11628               code = (code == NE ? EQ : NE);
11629               continue;
11630             }
11631
11632           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11633              (eq (and (lshiftrt X) 1) 0).
11634              Also handle the case where (not X) is expressed using xor.  */
11635           if (const_op == 0 && equality_comparison_p
11636               && XEXP (op0, 1) == const1_rtx
11637               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11638             {
11639               rtx shift_op = XEXP (XEXP (op0, 0), 0);
11640               rtx shift_count = XEXP (XEXP (op0, 0), 1);
11641
11642               if (GET_CODE (shift_op) == NOT
11643                   || (GET_CODE (shift_op) == XOR
11644                       && CONST_INT_P (XEXP (shift_op, 1))
11645                       && CONST_INT_P (shift_count)
11646                       && HWI_COMPUTABLE_MODE_P (mode)
11647                       && (UINTVAL (XEXP (shift_op, 1))
11648                           == (unsigned HOST_WIDE_INT) 1
11649                                << INTVAL (shift_count))))
11650                 {
11651                   op0
11652                     = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11653                   op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11654                   code = (code == NE ? EQ : NE);
11655                   continue;
11656                 }
11657             }
11658           break;
11659
11660         case ASHIFT:
11661           /* If we have (compare (ashift FOO N) (const_int C)) and
11662              the high order N bits of FOO (N+1 if an inequality comparison)
11663              are known to be zero, we can do this by comparing FOO with C
11664              shifted right N bits so long as the low-order N bits of C are
11665              zero.  */
11666           if (CONST_INT_P (XEXP (op0, 1))
11667               && INTVAL (XEXP (op0, 1)) >= 0
11668               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11669                   < HOST_BITS_PER_WIDE_INT)
11670               && (((unsigned HOST_WIDE_INT) const_op
11671                    & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11672                       - 1)) == 0)
11673               && mode_width <= HOST_BITS_PER_WIDE_INT
11674               && (nonzero_bits (XEXP (op0, 0), mode)
11675                   & ~(mask >> (INTVAL (XEXP (op0, 1))
11676                                + ! equality_comparison_p))) == 0)
11677             {
11678               /* We must perform a logical shift, not an arithmetic one,
11679                  as we want the top N bits of C to be zero.  */
11680               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11681
11682               temp >>= INTVAL (XEXP (op0, 1));
11683               op1 = gen_int_mode (temp, mode);
11684               op0 = XEXP (op0, 0);
11685               continue;
11686             }
11687
11688           /* If we are doing a sign bit comparison, it means we are testing
11689              a particular bit.  Convert it to the appropriate AND.  */
11690           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11691               && mode_width <= HOST_BITS_PER_WIDE_INT)
11692             {
11693               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11694                                             ((unsigned HOST_WIDE_INT) 1
11695                                              << (mode_width - 1
11696                                                  - INTVAL (XEXP (op0, 1)))));
11697               code = (code == LT ? NE : EQ);
11698               continue;
11699             }
11700
11701           /* If this an equality comparison with zero and we are shifting
11702              the low bit to the sign bit, we can convert this to an AND of the
11703              low-order bit.  */
11704           if (const_op == 0 && equality_comparison_p
11705               && CONST_INT_P (XEXP (op0, 1))
11706               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11707             {
11708               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11709               continue;
11710             }
11711           break;
11712
11713         case ASHIFTRT:
11714           /* If this is an equality comparison with zero, we can do this
11715              as a logical shift, which might be much simpler.  */
11716           if (equality_comparison_p && const_op == 0
11717               && CONST_INT_P (XEXP (op0, 1)))
11718             {
11719               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11720                                           XEXP (op0, 0),
11721                                           INTVAL (XEXP (op0, 1)));
11722               continue;
11723             }
11724
11725           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11726              do the comparison in a narrower mode.  */
11727           if (! unsigned_comparison_p
11728               && CONST_INT_P (XEXP (op0, 1))
11729               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11730               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11731               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11732                                          MODE_INT, 1)) != BLKmode
11733               && (((unsigned HOST_WIDE_INT) const_op
11734                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11735                   <= GET_MODE_MASK (tmode)))
11736             {
11737               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11738               continue;
11739             }
11740
11741           /* Likewise if OP0 is a PLUS of a sign extension with a
11742              constant, which is usually represented with the PLUS
11743              between the shifts.  */
11744           if (! unsigned_comparison_p
11745               && CONST_INT_P (XEXP (op0, 1))
11746               && GET_CODE (XEXP (op0, 0)) == PLUS
11747               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11748               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11749               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11750               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11751                                          MODE_INT, 1)) != BLKmode
11752               && (((unsigned HOST_WIDE_INT) const_op
11753                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11754                   <= GET_MODE_MASK (tmode)))
11755             {
11756               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11757               rtx add_const = XEXP (XEXP (op0, 0), 1);
11758               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11759                                                    add_const, XEXP (op0, 1));
11760
11761               op0 = simplify_gen_binary (PLUS, tmode,
11762                                          gen_lowpart (tmode, inner),
11763                                          new_const);
11764               continue;
11765             }
11766
11767           /* ... fall through ...  */
11768         case LSHIFTRT:
11769           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11770              the low order N bits of FOO are known to be zero, we can do this
11771              by comparing FOO with C shifted left N bits so long as no
11772              overflow occurs.  Even if the low order N bits of FOO aren't known
11773              to be zero, if the comparison is >= or < we can use the same
11774              optimization and for > or <= by setting all the low
11775              order N bits in the comparison constant.  */
11776           if (CONST_INT_P (XEXP (op0, 1))
11777               && INTVAL (XEXP (op0, 1)) > 0
11778               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11779               && mode_width <= HOST_BITS_PER_WIDE_INT
11780               && (((unsigned HOST_WIDE_INT) const_op
11781                    + (GET_CODE (op0) != LSHIFTRT
11782                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11783                          + 1)
11784                       : 0))
11785                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11786             {
11787               unsigned HOST_WIDE_INT low_bits
11788                 = (nonzero_bits (XEXP (op0, 0), mode)
11789                    & (((unsigned HOST_WIDE_INT) 1
11790                        << INTVAL (XEXP (op0, 1))) - 1));
11791               if (low_bits == 0 || !equality_comparison_p)
11792                 {
11793                   /* If the shift was logical, then we must make the condition
11794                      unsigned.  */
11795                   if (GET_CODE (op0) == LSHIFTRT)
11796                     code = unsigned_condition (code);
11797
11798                   const_op <<= INTVAL (XEXP (op0, 1));
11799                   if (low_bits != 0
11800                       && (code == GT || code == GTU
11801                           || code == LE || code == LEU))
11802                     const_op
11803                       |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11804                   op1 = GEN_INT (const_op);
11805                   op0 = XEXP (op0, 0);
11806                   continue;
11807                 }
11808             }
11809
11810           /* If we are using this shift to extract just the sign bit, we
11811              can replace this with an LT or GE comparison.  */
11812           if (const_op == 0
11813               && (equality_comparison_p || sign_bit_comparison_p)
11814               && CONST_INT_P (XEXP (op0, 1))
11815               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11816             {
11817               op0 = XEXP (op0, 0);
11818               code = (code == NE || code == GT ? LT : GE);
11819               continue;
11820             }
11821           break;
11822
11823         default:
11824           break;
11825         }
11826
11827       break;
11828     }
11829
11830   /* Now make any compound operations involved in this comparison.  Then,
11831      check for an outmost SUBREG on OP0 that is not doing anything or is
11832      paradoxical.  The latter transformation must only be performed when
11833      it is known that the "extra" bits will be the same in op0 and op1 or
11834      that they don't matter.  There are three cases to consider:
11835
11836      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11837      care bits and we can assume they have any convenient value.  So
11838      making the transformation is safe.
11839
11840      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11841      In this case the upper bits of op0 are undefined.  We should not make
11842      the simplification in that case as we do not know the contents of
11843      those bits.
11844
11845      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11846      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
11847      also be sure that they are the same as the upper bits of op1.
11848
11849      We can never remove a SUBREG for a non-equality comparison because
11850      the sign bit is in a different place in the underlying object.  */
11851
11852   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11853   op1 = make_compound_operation (op1, SET);
11854
11855   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11856       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11857       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11858       && (code == NE || code == EQ))
11859     {
11860       if (paradoxical_subreg_p (op0))
11861         {
11862           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
11863              implemented.  */
11864           if (REG_P (SUBREG_REG (op0)))
11865             {
11866               op0 = SUBREG_REG (op0);
11867               op1 = gen_lowpart (GET_MODE (op0), op1);
11868             }
11869         }
11870       else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
11871                 <= HOST_BITS_PER_WIDE_INT)
11872                && (nonzero_bits (SUBREG_REG (op0),
11873                                  GET_MODE (SUBREG_REG (op0)))
11874                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11875         {
11876           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11877
11878           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11879                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11880             op0 = SUBREG_REG (op0), op1 = tem;
11881         }
11882     }
11883
11884   /* We now do the opposite procedure: Some machines don't have compare
11885      insns in all modes.  If OP0's mode is an integer mode smaller than a
11886      word and we can't do a compare in that mode, see if there is a larger
11887      mode for which we can do the compare.  There are a number of cases in
11888      which we can use the wider mode.  */
11889
11890   mode = GET_MODE (op0);
11891   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11892       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11893       && ! have_insn_for (COMPARE, mode))
11894     for (tmode = GET_MODE_WIDER_MODE (mode);
11895          (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
11896          tmode = GET_MODE_WIDER_MODE (tmode))
11897       if (have_insn_for (COMPARE, tmode))
11898         {
11899           int zero_extended;
11900
11901           /* If this is a test for negative, we can make an explicit
11902              test of the sign bit.  Test this first so we can use
11903              a paradoxical subreg to extend OP0.  */
11904
11905           if (op1 == const0_rtx && (code == LT || code == GE)
11906               && HWI_COMPUTABLE_MODE_P (mode))
11907             {
11908               op0 = simplify_gen_binary (AND, tmode,
11909                                          gen_lowpart (tmode, op0),
11910                                          GEN_INT ((unsigned HOST_WIDE_INT) 1
11911                                                   << (GET_MODE_BITSIZE (mode)
11912                                                       - 1)));
11913               code = (code == LT) ? NE : EQ;
11914               break;
11915             }
11916
11917           /* If the only nonzero bits in OP0 and OP1 are those in the
11918              narrower mode and this is an equality or unsigned comparison,
11919              we can use the wider mode.  Similarly for sign-extended
11920              values, in which case it is true for all comparisons.  */
11921           zero_extended = ((code == EQ || code == NE
11922                             || code == GEU || code == GTU
11923                             || code == LEU || code == LTU)
11924                            && (nonzero_bits (op0, tmode)
11925                                & ~GET_MODE_MASK (mode)) == 0
11926                            && ((CONST_INT_P (op1)
11927                                 || (nonzero_bits (op1, tmode)
11928                                     & ~GET_MODE_MASK (mode)) == 0)));
11929
11930           if (zero_extended
11931               || ((num_sign_bit_copies (op0, tmode)
11932                    > (unsigned int) (GET_MODE_PRECISION (tmode)
11933                                      - GET_MODE_PRECISION (mode)))
11934                   && (num_sign_bit_copies (op1, tmode)
11935                       > (unsigned int) (GET_MODE_PRECISION (tmode)
11936                                         - GET_MODE_PRECISION (mode)))))
11937             {
11938               /* If OP0 is an AND and we don't have an AND in MODE either,
11939                  make a new AND in the proper mode.  */
11940               if (GET_CODE (op0) == AND
11941                   && !have_insn_for (AND, mode))
11942                 op0 = simplify_gen_binary (AND, tmode,
11943                                            gen_lowpart (tmode,
11944                                                         XEXP (op0, 0)),
11945                                            gen_lowpart (tmode,
11946                                                         XEXP (op0, 1)));
11947               else
11948                 {
11949                   if (zero_extended)
11950                     {
11951                       op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11952                       op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11953                     }
11954                   else
11955                     {
11956                       op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11957                       op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11958                     }
11959                   break;
11960                 }
11961             }
11962         }
11963
11964   /* If this machine only supports a subset of valid comparisons, see if we
11965      can convert an unsupported one into a supported one.  */
11966   target_canonicalize_comparison (&code, &op0, &op1, 0);
11967
11968   *pop0 = op0;
11969   *pop1 = op1;
11970
11971   return code;
11972 }
11973 \f
11974 /* Utility function for record_value_for_reg.  Count number of
11975    rtxs in X.  */
11976 static int
11977 count_rtxs (rtx x)
11978 {
11979   enum rtx_code code = GET_CODE (x);
11980   const char *fmt;
11981   int i, j, ret = 1;
11982
11983   if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
11984       || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
11985     {
11986       rtx x0 = XEXP (x, 0);
11987       rtx x1 = XEXP (x, 1);
11988
11989       if (x0 == x1)
11990         return 1 + 2 * count_rtxs (x0);
11991
11992       if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
11993            || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
11994           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11995         return 2 + 2 * count_rtxs (x0)
11996                + count_rtxs (x == XEXP (x1, 0)
11997                              ? XEXP (x1, 1) : XEXP (x1, 0));
11998
11999       if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
12000            || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
12001           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12002         return 2 + 2 * count_rtxs (x1)
12003                + count_rtxs (x == XEXP (x0, 0)
12004                              ? XEXP (x0, 1) : XEXP (x0, 0));
12005     }
12006
12007   fmt = GET_RTX_FORMAT (code);
12008   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12009     if (fmt[i] == 'e')
12010       ret += count_rtxs (XEXP (x, i));
12011     else if (fmt[i] == 'E')
12012       for (j = 0; j < XVECLEN (x, i); j++)
12013         ret += count_rtxs (XVECEXP (x, i, j));
12014
12015   return ret;
12016 }
12017 \f
12018 /* Utility function for following routine.  Called when X is part of a value
12019    being stored into last_set_value.  Sets last_set_table_tick
12020    for each register mentioned.  Similar to mention_regs in cse.c  */
12021
12022 static void
12023 update_table_tick (rtx x)
12024 {
12025   enum rtx_code code = GET_CODE (x);
12026   const char *fmt = GET_RTX_FORMAT (code);
12027   int i, j;
12028
12029   if (code == REG)
12030     {
12031       unsigned int regno = REGNO (x);
12032       unsigned int endregno = END_REGNO (x);
12033       unsigned int r;
12034
12035       for (r = regno; r < endregno; r++)
12036         {
12037           reg_stat_type *rsp = &reg_stat[r];
12038           rsp->last_set_table_tick = label_tick;
12039         }
12040
12041       return;
12042     }
12043
12044   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12045     if (fmt[i] == 'e')
12046       {
12047         /* Check for identical subexpressions.  If x contains
12048            identical subexpression we only have to traverse one of
12049            them.  */
12050         if (i == 0 && ARITHMETIC_P (x))
12051           {
12052             /* Note that at this point x1 has already been
12053                processed.  */
12054             rtx x0 = XEXP (x, 0);
12055             rtx x1 = XEXP (x, 1);
12056
12057             /* If x0 and x1 are identical then there is no need to
12058                process x0.  */
12059             if (x0 == x1)
12060               break;
12061
12062             /* If x0 is identical to a subexpression of x1 then while
12063                processing x1, x0 has already been processed.  Thus we
12064                are done with x.  */
12065             if (ARITHMETIC_P (x1)
12066                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12067               break;
12068
12069             /* If x1 is identical to a subexpression of x0 then we
12070                still have to process the rest of x0.  */
12071             if (ARITHMETIC_P (x0)
12072                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12073               {
12074                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12075                 break;
12076               }
12077           }
12078
12079         update_table_tick (XEXP (x, i));
12080       }
12081     else if (fmt[i] == 'E')
12082       for (j = 0; j < XVECLEN (x, i); j++)
12083         update_table_tick (XVECEXP (x, i, j));
12084 }
12085
12086 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
12087    are saying that the register is clobbered and we no longer know its
12088    value.  If INSN is zero, don't update reg_stat[].last_set; this is
12089    only permitted with VALUE also zero and is used to invalidate the
12090    register.  */
12091
12092 static void
12093 record_value_for_reg (rtx reg, rtx insn, rtx value)
12094 {
12095   unsigned int regno = REGNO (reg);
12096   unsigned int endregno = END_REGNO (reg);
12097   unsigned int i;
12098   reg_stat_type *rsp;
12099
12100   /* If VALUE contains REG and we have a previous value for REG, substitute
12101      the previous value.  */
12102   if (value && insn && reg_overlap_mentioned_p (reg, value))
12103     {
12104       rtx tem;
12105
12106       /* Set things up so get_last_value is allowed to see anything set up to
12107          our insn.  */
12108       subst_low_luid = DF_INSN_LUID (insn);
12109       tem = get_last_value (reg);
12110
12111       /* If TEM is simply a binary operation with two CLOBBERs as operands,
12112          it isn't going to be useful and will take a lot of time to process,
12113          so just use the CLOBBER.  */
12114
12115       if (tem)
12116         {
12117           if (ARITHMETIC_P (tem)
12118               && GET_CODE (XEXP (tem, 0)) == CLOBBER
12119               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12120             tem = XEXP (tem, 0);
12121           else if (count_occurrences (value, reg, 1) >= 2)
12122             {
12123               /* If there are two or more occurrences of REG in VALUE,
12124                  prevent the value from growing too much.  */
12125               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12126                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12127             }
12128
12129           value = replace_rtx (copy_rtx (value), reg, tem);
12130         }
12131     }
12132
12133   /* For each register modified, show we don't know its value, that
12134      we don't know about its bitwise content, that its value has been
12135      updated, and that we don't know the location of the death of the
12136      register.  */
12137   for (i = regno; i < endregno; i++)
12138     {
12139       rsp = &reg_stat[i];
12140
12141       if (insn)
12142         rsp->last_set = insn;
12143
12144       rsp->last_set_value = 0;
12145       rsp->last_set_mode = VOIDmode;
12146       rsp->last_set_nonzero_bits = 0;
12147       rsp->last_set_sign_bit_copies = 0;
12148       rsp->last_death = 0;
12149       rsp->truncated_to_mode = VOIDmode;
12150     }
12151
12152   /* Mark registers that are being referenced in this value.  */
12153   if (value)
12154     update_table_tick (value);
12155
12156   /* Now update the status of each register being set.
12157      If someone is using this register in this block, set this register
12158      to invalid since we will get confused between the two lives in this
12159      basic block.  This makes using this register always invalid.  In cse, we
12160      scan the table to invalidate all entries using this register, but this
12161      is too much work for us.  */
12162
12163   for (i = regno; i < endregno; i++)
12164     {
12165       rsp = &reg_stat[i];
12166       rsp->last_set_label = label_tick;
12167       if (!insn
12168           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12169         rsp->last_set_invalid = 1;
12170       else
12171         rsp->last_set_invalid = 0;
12172     }
12173
12174   /* The value being assigned might refer to X (like in "x++;").  In that
12175      case, we must replace it with (clobber (const_int 0)) to prevent
12176      infinite loops.  */
12177   rsp = &reg_stat[regno];
12178   if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12179     {
12180       value = copy_rtx (value);
12181       if (!get_last_value_validate (&value, insn, label_tick, 1))
12182         value = 0;
12183     }
12184
12185   /* For the main register being modified, update the value, the mode, the
12186      nonzero bits, and the number of sign bit copies.  */
12187
12188   rsp->last_set_value = value;
12189
12190   if (value)
12191     {
12192       enum machine_mode mode = GET_MODE (reg);
12193       subst_low_luid = DF_INSN_LUID (insn);
12194       rsp->last_set_mode = mode;
12195       if (GET_MODE_CLASS (mode) == MODE_INT
12196           && HWI_COMPUTABLE_MODE_P (mode))
12197         mode = nonzero_bits_mode;
12198       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12199       rsp->last_set_sign_bit_copies
12200         = num_sign_bit_copies (value, GET_MODE (reg));
12201     }
12202 }
12203
12204 /* Called via note_stores from record_dead_and_set_regs to handle one
12205    SET or CLOBBER in an insn.  DATA is the instruction in which the
12206    set is occurring.  */
12207
12208 static void
12209 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12210 {
12211   rtx record_dead_insn = (rtx) data;
12212
12213   if (GET_CODE (dest) == SUBREG)
12214     dest = SUBREG_REG (dest);
12215
12216   if (!record_dead_insn)
12217     {
12218       if (REG_P (dest))
12219         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12220       return;
12221     }
12222
12223   if (REG_P (dest))
12224     {
12225       /* If we are setting the whole register, we know its value.  Otherwise
12226          show that we don't know the value.  We can handle SUBREG in
12227          some cases.  */
12228       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12229         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12230       else if (GET_CODE (setter) == SET
12231                && GET_CODE (SET_DEST (setter)) == SUBREG
12232                && SUBREG_REG (SET_DEST (setter)) == dest
12233                && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12234                && subreg_lowpart_p (SET_DEST (setter)))
12235         record_value_for_reg (dest, record_dead_insn,
12236                               gen_lowpart (GET_MODE (dest),
12237                                                        SET_SRC (setter)));
12238       else
12239         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12240     }
12241   else if (MEM_P (dest)
12242            /* Ignore pushes, they clobber nothing.  */
12243            && ! push_operand (dest, GET_MODE (dest)))
12244     mem_last_set = DF_INSN_LUID (record_dead_insn);
12245 }
12246
12247 /* Update the records of when each REG was most recently set or killed
12248    for the things done by INSN.  This is the last thing done in processing
12249    INSN in the combiner loop.
12250
12251    We update reg_stat[], in particular fields last_set, last_set_value,
12252    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12253    last_death, and also the similar information mem_last_set (which insn
12254    most recently modified memory) and last_call_luid (which insn was the
12255    most recent subroutine call).  */
12256
12257 static void
12258 record_dead_and_set_regs (rtx insn)
12259 {
12260   rtx link;
12261   unsigned int i;
12262
12263   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12264     {
12265       if (REG_NOTE_KIND (link) == REG_DEAD
12266           && REG_P (XEXP (link, 0)))
12267         {
12268           unsigned int regno = REGNO (XEXP (link, 0));
12269           unsigned int endregno = END_REGNO (XEXP (link, 0));
12270
12271           for (i = regno; i < endregno; i++)
12272             {
12273               reg_stat_type *rsp;
12274
12275               rsp = &reg_stat[i];
12276               rsp->last_death = insn;
12277             }
12278         }
12279       else if (REG_NOTE_KIND (link) == REG_INC)
12280         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12281     }
12282
12283   if (CALL_P (insn))
12284     {
12285       hard_reg_set_iterator hrsi;
12286       EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
12287         {
12288           reg_stat_type *rsp;
12289
12290           rsp = &reg_stat[i];
12291           rsp->last_set_invalid = 1;
12292           rsp->last_set = insn;
12293           rsp->last_set_value = 0;
12294           rsp->last_set_mode = VOIDmode;
12295           rsp->last_set_nonzero_bits = 0;
12296           rsp->last_set_sign_bit_copies = 0;
12297           rsp->last_death = 0;
12298           rsp->truncated_to_mode = VOIDmode;
12299         }
12300
12301       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12302
12303       /* We can't combine into a call pattern.  Remember, though, that
12304          the return value register is set at this LUID.  We could
12305          still replace a register with the return value from the
12306          wrong subroutine call!  */
12307       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12308     }
12309   else
12310     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12311 }
12312
12313 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12314    register present in the SUBREG, so for each such SUBREG go back and
12315    adjust nonzero and sign bit information of the registers that are
12316    known to have some zero/sign bits set.
12317
12318    This is needed because when combine blows the SUBREGs away, the
12319    information on zero/sign bits is lost and further combines can be
12320    missed because of that.  */
12321
12322 static void
12323 record_promoted_value (rtx insn, rtx subreg)
12324 {
12325   struct insn_link *links;
12326   rtx set;
12327   unsigned int regno = REGNO (SUBREG_REG (subreg));
12328   enum machine_mode mode = GET_MODE (subreg);
12329
12330   if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12331     return;
12332
12333   for (links = LOG_LINKS (insn); links;)
12334     {
12335       reg_stat_type *rsp;
12336
12337       insn = links->insn;
12338       set = single_set (insn);
12339
12340       if (! set || !REG_P (SET_DEST (set))
12341           || REGNO (SET_DEST (set)) != regno
12342           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12343         {
12344           links = links->next;
12345           continue;
12346         }
12347
12348       rsp = &reg_stat[regno];
12349       if (rsp->last_set == insn)
12350         {
12351           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12352             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12353         }
12354
12355       if (REG_P (SET_SRC (set)))
12356         {
12357           regno = REGNO (SET_SRC (set));
12358           links = LOG_LINKS (insn);
12359         }
12360       else
12361         break;
12362     }
12363 }
12364
12365 /* Check if X, a register, is known to contain a value already
12366    truncated to MODE.  In this case we can use a subreg to refer to
12367    the truncated value even though in the generic case we would need
12368    an explicit truncation.  */
12369
12370 static bool
12371 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12372 {
12373   reg_stat_type *rsp = &reg_stat[REGNO (x)];
12374   enum machine_mode truncated = rsp->truncated_to_mode;
12375
12376   if (truncated == 0
12377       || rsp->truncation_label < label_tick_ebb_start)
12378     return false;
12379   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12380     return true;
12381   if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12382     return true;
12383   return false;
12384 }
12385
12386 /* Callback for for_each_rtx.  If *P is a hard reg or a subreg record the mode
12387    that the register is accessed in.  For non-TRULY_NOOP_TRUNCATION targets we
12388    might be able to turn a truncate into a subreg using this information.
12389    Return -1 if traversing *P is complete or 0 otherwise.  */
12390
12391 static int
12392 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12393 {
12394   rtx x = *p;
12395   enum machine_mode truncated_mode;
12396   reg_stat_type *rsp;
12397
12398   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12399     {
12400       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12401       truncated_mode = GET_MODE (x);
12402
12403       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12404         return -1;
12405
12406       if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12407         return -1;
12408
12409       x = SUBREG_REG (x);
12410     }
12411   /* ??? For hard-regs we now record everything.  We might be able to
12412      optimize this using last_set_mode.  */
12413   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12414     truncated_mode = GET_MODE (x);
12415   else
12416     return 0;
12417
12418   rsp = &reg_stat[REGNO (x)];
12419   if (rsp->truncated_to_mode == 0
12420       || rsp->truncation_label < label_tick_ebb_start
12421       || (GET_MODE_SIZE (truncated_mode)
12422           < GET_MODE_SIZE (rsp->truncated_to_mode)))
12423     {
12424       rsp->truncated_to_mode = truncated_mode;
12425       rsp->truncation_label = label_tick;
12426     }
12427
12428   return -1;
12429 }
12430
12431 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
12432    the modes they are used in.  This can help truning TRUNCATEs into
12433    SUBREGs.  */
12434
12435 static void
12436 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12437 {
12438   for_each_rtx (x, record_truncated_value, NULL);
12439 }
12440
12441 /* Scan X for promoted SUBREGs.  For each one found,
12442    note what it implies to the registers used in it.  */
12443
12444 static void
12445 check_promoted_subreg (rtx insn, rtx x)
12446 {
12447   if (GET_CODE (x) == SUBREG
12448       && SUBREG_PROMOTED_VAR_P (x)
12449       && REG_P (SUBREG_REG (x)))
12450     record_promoted_value (insn, x);
12451   else
12452     {
12453       const char *format = GET_RTX_FORMAT (GET_CODE (x));
12454       int i, j;
12455
12456       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12457         switch (format[i])
12458           {
12459           case 'e':
12460             check_promoted_subreg (insn, XEXP (x, i));
12461             break;
12462           case 'V':
12463           case 'E':
12464             if (XVEC (x, i) != 0)
12465               for (j = 0; j < XVECLEN (x, i); j++)
12466                 check_promoted_subreg (insn, XVECEXP (x, i, j));
12467             break;
12468           }
12469     }
12470 }
12471 \f
12472 /* Verify that all the registers and memory references mentioned in *LOC are
12473    still valid.  *LOC was part of a value set in INSN when label_tick was
12474    equal to TICK.  Return 0 if some are not.  If REPLACE is nonzero, replace
12475    the invalid references with (clobber (const_int 0)) and return 1.  This
12476    replacement is useful because we often can get useful information about
12477    the form of a value (e.g., if it was produced by a shift that always
12478    produces -1 or 0) even though we don't know exactly what registers it
12479    was produced from.  */
12480
12481 static int
12482 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12483 {
12484   rtx x = *loc;
12485   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12486   int len = GET_RTX_LENGTH (GET_CODE (x));
12487   int i, j;
12488
12489   if (REG_P (x))
12490     {
12491       unsigned int regno = REGNO (x);
12492       unsigned int endregno = END_REGNO (x);
12493       unsigned int j;
12494
12495       for (j = regno; j < endregno; j++)
12496         {
12497           reg_stat_type *rsp = &reg_stat[j];
12498           if (rsp->last_set_invalid
12499               /* If this is a pseudo-register that was only set once and not
12500                  live at the beginning of the function, it is always valid.  */
12501               || (! (regno >= FIRST_PSEUDO_REGISTER
12502                      && REG_N_SETS (regno) == 1
12503                      && (!REGNO_REG_SET_P
12504                          (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12505                   && rsp->last_set_label > tick))
12506           {
12507             if (replace)
12508               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12509             return replace;
12510           }
12511         }
12512
12513       return 1;
12514     }
12515   /* If this is a memory reference, make sure that there were no stores after
12516      it that might have clobbered the value.  We don't have alias info, so we
12517      assume any store invalidates it.  Moreover, we only have local UIDs, so
12518      we also assume that there were stores in the intervening basic blocks.  */
12519   else if (MEM_P (x) && !MEM_READONLY_P (x)
12520            && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12521     {
12522       if (replace)
12523         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12524       return replace;
12525     }
12526
12527   for (i = 0; i < len; i++)
12528     {
12529       if (fmt[i] == 'e')
12530         {
12531           /* Check for identical subexpressions.  If x contains
12532              identical subexpression we only have to traverse one of
12533              them.  */
12534           if (i == 1 && ARITHMETIC_P (x))
12535             {
12536               /* Note that at this point x0 has already been checked
12537                  and found valid.  */
12538               rtx x0 = XEXP (x, 0);
12539               rtx x1 = XEXP (x, 1);
12540
12541               /* If x0 and x1 are identical then x is also valid.  */
12542               if (x0 == x1)
12543                 return 1;
12544
12545               /* If x1 is identical to a subexpression of x0 then
12546                  while checking x0, x1 has already been checked.  Thus
12547                  it is valid and so as x.  */
12548               if (ARITHMETIC_P (x0)
12549                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12550                 return 1;
12551
12552               /* If x0 is identical to a subexpression of x1 then x is
12553                  valid iff the rest of x1 is valid.  */
12554               if (ARITHMETIC_P (x1)
12555                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12556                 return
12557                   get_last_value_validate (&XEXP (x1,
12558                                                   x0 == XEXP (x1, 0) ? 1 : 0),
12559                                            insn, tick, replace);
12560             }
12561
12562           if (get_last_value_validate (&XEXP (x, i), insn, tick,
12563                                        replace) == 0)
12564             return 0;
12565         }
12566       else if (fmt[i] == 'E')
12567         for (j = 0; j < XVECLEN (x, i); j++)
12568           if (get_last_value_validate (&XVECEXP (x, i, j),
12569                                        insn, tick, replace) == 0)
12570             return 0;
12571     }
12572
12573   /* If we haven't found a reason for it to be invalid, it is valid.  */
12574   return 1;
12575 }
12576
12577 /* Get the last value assigned to X, if known.  Some registers
12578    in the value may be replaced with (clobber (const_int 0)) if their value
12579    is known longer known reliably.  */
12580
12581 static rtx
12582 get_last_value (const_rtx x)
12583 {
12584   unsigned int regno;
12585   rtx value;
12586   reg_stat_type *rsp;
12587
12588   /* If this is a non-paradoxical SUBREG, get the value of its operand and
12589      then convert it to the desired mode.  If this is a paradoxical SUBREG,
12590      we cannot predict what values the "extra" bits might have.  */
12591   if (GET_CODE (x) == SUBREG
12592       && subreg_lowpart_p (x)
12593       && !paradoxical_subreg_p (x)
12594       && (value = get_last_value (SUBREG_REG (x))) != 0)
12595     return gen_lowpart (GET_MODE (x), value);
12596
12597   if (!REG_P (x))
12598     return 0;
12599
12600   regno = REGNO (x);
12601   rsp = &reg_stat[regno];
12602   value = rsp->last_set_value;
12603
12604   /* If we don't have a value, or if it isn't for this basic block and
12605      it's either a hard register, set more than once, or it's a live
12606      at the beginning of the function, return 0.
12607
12608      Because if it's not live at the beginning of the function then the reg
12609      is always set before being used (is never used without being set).
12610      And, if it's set only once, and it's always set before use, then all
12611      uses must have the same last value, even if it's not from this basic
12612      block.  */
12613
12614   if (value == 0
12615       || (rsp->last_set_label < label_tick_ebb_start
12616           && (regno < FIRST_PSEUDO_REGISTER
12617               || REG_N_SETS (regno) != 1
12618               || REGNO_REG_SET_P
12619                  (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12620     return 0;
12621
12622   /* If the value was set in a later insn than the ones we are processing,
12623      we can't use it even if the register was only set once.  */
12624   if (rsp->last_set_label == label_tick
12625       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12626     return 0;
12627
12628   /* If the value has all its registers valid, return it.  */
12629   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12630     return value;
12631
12632   /* Otherwise, make a copy and replace any invalid register with
12633      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
12634
12635   value = copy_rtx (value);
12636   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12637     return value;
12638
12639   return 0;
12640 }
12641 \f
12642 /* Return nonzero if expression X refers to a REG or to memory
12643    that is set in an instruction more recent than FROM_LUID.  */
12644
12645 static int
12646 use_crosses_set_p (const_rtx x, int from_luid)
12647 {
12648   const char *fmt;
12649   int i;
12650   enum rtx_code code = GET_CODE (x);
12651
12652   if (code == REG)
12653     {
12654       unsigned int regno = REGNO (x);
12655       unsigned endreg = END_REGNO (x);
12656
12657 #ifdef PUSH_ROUNDING
12658       /* Don't allow uses of the stack pointer to be moved,
12659          because we don't know whether the move crosses a push insn.  */
12660       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12661         return 1;
12662 #endif
12663       for (; regno < endreg; regno++)
12664         {
12665           reg_stat_type *rsp = &reg_stat[regno];
12666           if (rsp->last_set
12667               && rsp->last_set_label == label_tick
12668               && DF_INSN_LUID (rsp->last_set) > from_luid)
12669             return 1;
12670         }
12671       return 0;
12672     }
12673
12674   if (code == MEM && mem_last_set > from_luid)
12675     return 1;
12676
12677   fmt = GET_RTX_FORMAT (code);
12678
12679   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12680     {
12681       if (fmt[i] == 'E')
12682         {
12683           int j;
12684           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12685             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12686               return 1;
12687         }
12688       else if (fmt[i] == 'e'
12689                && use_crosses_set_p (XEXP (x, i), from_luid))
12690         return 1;
12691     }
12692   return 0;
12693 }
12694 \f
12695 /* Define three variables used for communication between the following
12696    routines.  */
12697
12698 static unsigned int reg_dead_regno, reg_dead_endregno;
12699 static int reg_dead_flag;
12700
12701 /* Function called via note_stores from reg_dead_at_p.
12702
12703    If DEST is within [reg_dead_regno, reg_dead_endregno), set
12704    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
12705
12706 static void
12707 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12708 {
12709   unsigned int regno, endregno;
12710
12711   if (!REG_P (dest))
12712     return;
12713
12714   regno = REGNO (dest);
12715   endregno = END_REGNO (dest);
12716   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12717     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12718 }
12719
12720 /* Return nonzero if REG is known to be dead at INSN.
12721
12722    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
12723    referencing REG, it is dead.  If we hit a SET referencing REG, it is
12724    live.  Otherwise, see if it is live or dead at the start of the basic
12725    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
12726    must be assumed to be always live.  */
12727
12728 static int
12729 reg_dead_at_p (rtx reg, rtx insn)
12730 {
12731   basic_block block;
12732   unsigned int i;
12733
12734   /* Set variables for reg_dead_at_p_1.  */
12735   reg_dead_regno = REGNO (reg);
12736   reg_dead_endregno = END_REGNO (reg);
12737
12738   reg_dead_flag = 0;
12739
12740   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
12741      we allow the machine description to decide whether use-and-clobber
12742      patterns are OK.  */
12743   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12744     {
12745       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12746         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12747           return 0;
12748     }
12749
12750   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12751      beginning of basic block.  */
12752   block = BLOCK_FOR_INSN (insn);
12753   for (;;)
12754     {
12755       if (INSN_P (insn))
12756         {
12757           note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12758           if (reg_dead_flag)
12759             return reg_dead_flag == 1 ? 1 : 0;
12760
12761           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12762             return 1;
12763         }
12764
12765       if (insn == BB_HEAD (block))
12766         break;
12767
12768       insn = PREV_INSN (insn);
12769     }
12770
12771   /* Look at live-in sets for the basic block that we were in.  */
12772   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12773     if (REGNO_REG_SET_P (df_get_live_in (block), i))
12774       return 0;
12775
12776   return 1;
12777 }
12778 \f
12779 /* Note hard registers in X that are used.  */
12780
12781 static void
12782 mark_used_regs_combine (rtx x)
12783 {
12784   RTX_CODE code = GET_CODE (x);
12785   unsigned int regno;
12786   int i;
12787
12788   switch (code)
12789     {
12790     case LABEL_REF:
12791     case SYMBOL_REF:
12792     case CONST:
12793     CASE_CONST_ANY:
12794     case PC:
12795     case ADDR_VEC:
12796     case ADDR_DIFF_VEC:
12797     case ASM_INPUT:
12798 #ifdef HAVE_cc0
12799     /* CC0 must die in the insn after it is set, so we don't need to take
12800        special note of it here.  */
12801     case CC0:
12802 #endif
12803       return;
12804
12805     case CLOBBER:
12806       /* If we are clobbering a MEM, mark any hard registers inside the
12807          address as used.  */
12808       if (MEM_P (XEXP (x, 0)))
12809         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12810       return;
12811
12812     case REG:
12813       regno = REGNO (x);
12814       /* A hard reg in a wide mode may really be multiple registers.
12815          If so, mark all of them just like the first.  */
12816       if (regno < FIRST_PSEUDO_REGISTER)
12817         {
12818           /* None of this applies to the stack, frame or arg pointers.  */
12819           if (regno == STACK_POINTER_REGNUM
12820 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12821               || regno == HARD_FRAME_POINTER_REGNUM
12822 #endif
12823 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12824               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12825 #endif
12826               || regno == FRAME_POINTER_REGNUM)
12827             return;
12828
12829           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12830         }
12831       return;
12832
12833     case SET:
12834       {
12835         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12836            the address.  */
12837         rtx testreg = SET_DEST (x);
12838
12839         while (GET_CODE (testreg) == SUBREG
12840                || GET_CODE (testreg) == ZERO_EXTRACT
12841                || GET_CODE (testreg) == STRICT_LOW_PART)
12842           testreg = XEXP (testreg, 0);
12843
12844         if (MEM_P (testreg))
12845           mark_used_regs_combine (XEXP (testreg, 0));
12846
12847         mark_used_regs_combine (SET_SRC (x));
12848       }
12849       return;
12850
12851     default:
12852       break;
12853     }
12854
12855   /* Recursively scan the operands of this expression.  */
12856
12857   {
12858     const char *fmt = GET_RTX_FORMAT (code);
12859
12860     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12861       {
12862         if (fmt[i] == 'e')
12863           mark_used_regs_combine (XEXP (x, i));
12864         else if (fmt[i] == 'E')
12865           {
12866             int j;
12867
12868             for (j = 0; j < XVECLEN (x, i); j++)
12869               mark_used_regs_combine (XVECEXP (x, i, j));
12870           }
12871       }
12872   }
12873 }
12874 \f
12875 /* Remove register number REGNO from the dead registers list of INSN.
12876
12877    Return the note used to record the death, if there was one.  */
12878
12879 rtx
12880 remove_death (unsigned int regno, rtx insn)
12881 {
12882   rtx note = find_regno_note (insn, REG_DEAD, regno);
12883
12884   if (note)
12885     remove_note (insn, note);
12886
12887   return note;
12888 }
12889
12890 /* For each register (hardware or pseudo) used within expression X, if its
12891    death is in an instruction with luid between FROM_LUID (inclusive) and
12892    TO_INSN (exclusive), put a REG_DEAD note for that register in the
12893    list headed by PNOTES.
12894
12895    That said, don't move registers killed by maybe_kill_insn.
12896
12897    This is done when X is being merged by combination into TO_INSN.  These
12898    notes will then be distributed as needed.  */
12899
12900 static void
12901 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12902              rtx *pnotes)
12903 {
12904   const char *fmt;
12905   int len, i;
12906   enum rtx_code code = GET_CODE (x);
12907
12908   if (code == REG)
12909     {
12910       unsigned int regno = REGNO (x);
12911       rtx where_dead = reg_stat[regno].last_death;
12912
12913       /* Don't move the register if it gets killed in between from and to.  */
12914       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12915           && ! reg_referenced_p (x, maybe_kill_insn))
12916         return;
12917
12918       if (where_dead
12919           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12920           && DF_INSN_LUID (where_dead) >= from_luid
12921           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12922         {
12923           rtx note = remove_death (regno, where_dead);
12924
12925           /* It is possible for the call above to return 0.  This can occur
12926              when last_death points to I2 or I1 that we combined with.
12927              In that case make a new note.
12928
12929              We must also check for the case where X is a hard register
12930              and NOTE is a death note for a range of hard registers
12931              including X.  In that case, we must put REG_DEAD notes for
12932              the remaining registers in place of NOTE.  */
12933
12934           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12935               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12936                   > GET_MODE_SIZE (GET_MODE (x))))
12937             {
12938               unsigned int deadregno = REGNO (XEXP (note, 0));
12939               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12940               unsigned int ourend = END_HARD_REGNO (x);
12941               unsigned int i;
12942
12943               for (i = deadregno; i < deadend; i++)
12944                 if (i < regno || i >= ourend)
12945                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12946             }
12947
12948           /* If we didn't find any note, or if we found a REG_DEAD note that
12949              covers only part of the given reg, and we have a multi-reg hard
12950              register, then to be safe we must check for REG_DEAD notes
12951              for each register other than the first.  They could have
12952              their own REG_DEAD notes lying around.  */
12953           else if ((note == 0
12954                     || (note != 0
12955                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12956                             < GET_MODE_SIZE (GET_MODE (x)))))
12957                    && regno < FIRST_PSEUDO_REGISTER
12958                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12959             {
12960               unsigned int ourend = END_HARD_REGNO (x);
12961               unsigned int i, offset;
12962               rtx oldnotes = 0;
12963
12964               if (note)
12965                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12966               else
12967                 offset = 1;
12968
12969               for (i = regno + offset; i < ourend; i++)
12970                 move_deaths (regno_reg_rtx[i],
12971                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
12972             }
12973
12974           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12975             {
12976               XEXP (note, 1) = *pnotes;
12977               *pnotes = note;
12978             }
12979           else
12980             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12981         }
12982
12983       return;
12984     }
12985
12986   else if (GET_CODE (x) == SET)
12987     {
12988       rtx dest = SET_DEST (x);
12989
12990       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12991
12992       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12993          that accesses one word of a multi-word item, some
12994          piece of everything register in the expression is used by
12995          this insn, so remove any old death.  */
12996       /* ??? So why do we test for equality of the sizes?  */
12997
12998       if (GET_CODE (dest) == ZERO_EXTRACT
12999           || GET_CODE (dest) == STRICT_LOW_PART
13000           || (GET_CODE (dest) == SUBREG
13001               && (((GET_MODE_SIZE (GET_MODE (dest))
13002                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13003                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13004                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13005         {
13006           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13007           return;
13008         }
13009
13010       /* If this is some other SUBREG, we know it replaces the entire
13011          value, so use that as the destination.  */
13012       if (GET_CODE (dest) == SUBREG)
13013         dest = SUBREG_REG (dest);
13014
13015       /* If this is a MEM, adjust deaths of anything used in the address.
13016          For a REG (the only other possibility), the entire value is
13017          being replaced so the old value is not used in this insn.  */
13018
13019       if (MEM_P (dest))
13020         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13021                      to_insn, pnotes);
13022       return;
13023     }
13024
13025   else if (GET_CODE (x) == CLOBBER)
13026     return;
13027
13028   len = GET_RTX_LENGTH (code);
13029   fmt = GET_RTX_FORMAT (code);
13030
13031   for (i = 0; i < len; i++)
13032     {
13033       if (fmt[i] == 'E')
13034         {
13035           int j;
13036           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13037             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13038                          to_insn, pnotes);
13039         }
13040       else if (fmt[i] == 'e')
13041         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13042     }
13043 }
13044 \f
13045 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13046    pattern of an insn.  X must be a REG.  */
13047
13048 static int
13049 reg_bitfield_target_p (rtx x, rtx body)
13050 {
13051   int i;
13052
13053   if (GET_CODE (body) == SET)
13054     {
13055       rtx dest = SET_DEST (body);
13056       rtx target;
13057       unsigned int regno, tregno, endregno, endtregno;
13058
13059       if (GET_CODE (dest) == ZERO_EXTRACT)
13060         target = XEXP (dest, 0);
13061       else if (GET_CODE (dest) == STRICT_LOW_PART)
13062         target = SUBREG_REG (XEXP (dest, 0));
13063       else
13064         return 0;
13065
13066       if (GET_CODE (target) == SUBREG)
13067         target = SUBREG_REG (target);
13068
13069       if (!REG_P (target))
13070         return 0;
13071
13072       tregno = REGNO (target), regno = REGNO (x);
13073       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13074         return target == x;
13075
13076       endtregno = end_hard_regno (GET_MODE (target), tregno);
13077       endregno = end_hard_regno (GET_MODE (x), regno);
13078
13079       return endregno > tregno && regno < endtregno;
13080     }
13081
13082   else if (GET_CODE (body) == PARALLEL)
13083     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13084       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13085         return 1;
13086
13087   return 0;
13088 }
13089 \f
13090 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13091    as appropriate.  I3 and I2 are the insns resulting from the combination
13092    insns including FROM (I2 may be zero).
13093
13094    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13095    not need REG_DEAD notes because they are being substituted for.  This
13096    saves searching in the most common cases.
13097
13098    Each note in the list is either ignored or placed on some insns, depending
13099    on the type of note.  */
13100
13101 static void
13102 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13103                   rtx elim_i1, rtx elim_i0)
13104 {
13105   rtx note, next_note;
13106   rtx tem;
13107
13108   for (note = notes; note; note = next_note)
13109     {
13110       rtx place = 0, place2 = 0;
13111
13112       next_note = XEXP (note, 1);
13113       switch (REG_NOTE_KIND (note))
13114         {
13115         case REG_BR_PROB:
13116         case REG_BR_PRED:
13117           /* Doesn't matter much where we put this, as long as it's somewhere.
13118              It is preferable to keep these notes on branches, which is most
13119              likely to be i3.  */
13120           place = i3;
13121           break;
13122
13123         case REG_NON_LOCAL_GOTO:
13124           if (JUMP_P (i3))
13125             place = i3;
13126           else
13127             {
13128               gcc_assert (i2 && JUMP_P (i2));
13129               place = i2;
13130             }
13131           break;
13132
13133         case REG_EH_REGION:
13134           /* These notes must remain with the call or trapping instruction.  */
13135           if (CALL_P (i3))
13136             place = i3;
13137           else if (i2 && CALL_P (i2))
13138             place = i2;
13139           else
13140             {
13141               gcc_assert (cfun->can_throw_non_call_exceptions);
13142               if (may_trap_p (i3))
13143                 place = i3;
13144               else if (i2 && may_trap_p (i2))
13145                 place = i2;
13146               /* ??? Otherwise assume we've combined things such that we
13147                  can now prove that the instructions can't trap.  Drop the
13148                  note in this case.  */
13149             }
13150           break;
13151
13152         case REG_ARGS_SIZE:
13153           /* ??? How to distribute between i3-i1.  Assume i3 contains the
13154              entire adjustment.  Assert i3 contains at least some adjust.  */
13155           if (!noop_move_p (i3))
13156             {
13157               int old_size, args_size = INTVAL (XEXP (note, 0));
13158               /* fixup_args_size_notes looks at REG_NORETURN note,
13159                  so ensure the note is placed there first.  */
13160               if (CALL_P (i3))
13161                 {
13162                   rtx *np;
13163                   for (np = &next_note; *np; np = &XEXP (*np, 1))
13164                     if (REG_NOTE_KIND (*np) == REG_NORETURN)
13165                       {
13166                         rtx n = *np;
13167                         *np = XEXP (n, 1);
13168                         XEXP (n, 1) = REG_NOTES (i3);
13169                         REG_NOTES (i3) = n;
13170                         break;
13171                       }
13172                 }
13173               old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13174               /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13175                  REG_ARGS_SIZE note to all noreturn calls, allow that here.  */
13176               gcc_assert (old_size != args_size
13177                           || (CALL_P (i3)
13178                               && !ACCUMULATE_OUTGOING_ARGS
13179                               && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13180             }
13181           break;
13182
13183         case REG_NORETURN:
13184         case REG_SETJMP:
13185         case REG_TM:
13186           /* These notes must remain with the call.  It should not be
13187              possible for both I2 and I3 to be a call.  */
13188           if (CALL_P (i3))
13189             place = i3;
13190           else
13191             {
13192               gcc_assert (i2 && CALL_P (i2));
13193               place = i2;
13194             }
13195           break;
13196
13197         case REG_UNUSED:
13198           /* Any clobbers for i3 may still exist, and so we must process
13199              REG_UNUSED notes from that insn.
13200
13201              Any clobbers from i2 or i1 can only exist if they were added by
13202              recog_for_combine.  In that case, recog_for_combine created the
13203              necessary REG_UNUSED notes.  Trying to keep any original
13204              REG_UNUSED notes from these insns can cause incorrect output
13205              if it is for the same register as the original i3 dest.
13206              In that case, we will notice that the register is set in i3,
13207              and then add a REG_UNUSED note for the destination of i3, which
13208              is wrong.  However, it is possible to have REG_UNUSED notes from
13209              i2 or i1 for register which were both used and clobbered, so
13210              we keep notes from i2 or i1 if they will turn into REG_DEAD
13211              notes.  */
13212
13213           /* If this register is set or clobbered in I3, put the note there
13214              unless there is one already.  */
13215           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13216             {
13217               if (from_insn != i3)
13218                 break;
13219
13220               if (! (REG_P (XEXP (note, 0))
13221                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13222                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13223                 place = i3;
13224             }
13225           /* Otherwise, if this register is used by I3, then this register
13226              now dies here, so we must put a REG_DEAD note here unless there
13227              is one already.  */
13228           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13229                    && ! (REG_P (XEXP (note, 0))
13230                          ? find_regno_note (i3, REG_DEAD,
13231                                             REGNO (XEXP (note, 0)))
13232                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13233             {
13234               PUT_REG_NOTE_KIND (note, REG_DEAD);
13235               place = i3;
13236             }
13237           break;
13238
13239         case REG_EQUAL:
13240         case REG_EQUIV:
13241         case REG_NOALIAS:
13242           /* These notes say something about results of an insn.  We can
13243              only support them if they used to be on I3 in which case they
13244              remain on I3.  Otherwise they are ignored.
13245
13246              If the note refers to an expression that is not a constant, we
13247              must also ignore the note since we cannot tell whether the
13248              equivalence is still true.  It might be possible to do
13249              slightly better than this (we only have a problem if I2DEST
13250              or I1DEST is present in the expression), but it doesn't
13251              seem worth the trouble.  */
13252
13253           if (from_insn == i3
13254               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13255             place = i3;
13256           break;
13257
13258         case REG_INC:
13259           /* These notes say something about how a register is used.  They must
13260              be present on any use of the register in I2 or I3.  */
13261           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13262             place = i3;
13263
13264           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13265             {
13266               if (place)
13267                 place2 = i2;
13268               else
13269                 place = i2;
13270             }
13271           break;
13272
13273         case REG_LABEL_TARGET:
13274         case REG_LABEL_OPERAND:
13275           /* This can show up in several ways -- either directly in the
13276              pattern, or hidden off in the constant pool with (or without?)
13277              a REG_EQUAL note.  */
13278           /* ??? Ignore the without-reg_equal-note problem for now.  */
13279           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13280               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13281                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13282                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13283             place = i3;
13284
13285           if (i2
13286               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13287                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13288                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13289                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13290             {
13291               if (place)
13292                 place2 = i2;
13293               else
13294                 place = i2;
13295             }
13296
13297           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13298              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13299              there.  */
13300           if (place && JUMP_P (place)
13301               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13302               && (JUMP_LABEL (place) == NULL
13303                   || JUMP_LABEL (place) == XEXP (note, 0)))
13304             {
13305               rtx label = JUMP_LABEL (place);
13306
13307               if (!label)
13308                 JUMP_LABEL (place) = XEXP (note, 0);
13309               else if (LABEL_P (label))
13310                 LABEL_NUSES (label)--;
13311             }
13312
13313           if (place2 && JUMP_P (place2)
13314               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13315               && (JUMP_LABEL (place2) == NULL
13316                   || JUMP_LABEL (place2) == XEXP (note, 0)))
13317             {
13318               rtx label = JUMP_LABEL (place2);
13319
13320               if (!label)
13321                 JUMP_LABEL (place2) = XEXP (note, 0);
13322               else if (LABEL_P (label))
13323                 LABEL_NUSES (label)--;
13324               place2 = 0;
13325             }
13326           break;
13327
13328         case REG_NONNEG:
13329           /* This note says something about the value of a register prior
13330              to the execution of an insn.  It is too much trouble to see
13331              if the note is still correct in all situations.  It is better
13332              to simply delete it.  */
13333           break;
13334
13335         case REG_DEAD:
13336           /* If we replaced the right hand side of FROM_INSN with a
13337              REG_EQUAL note, the original use of the dying register
13338              will not have been combined into I3 and I2.  In such cases,
13339              FROM_INSN is guaranteed to be the first of the combined
13340              instructions, so we simply need to search back before
13341              FROM_INSN for the previous use or set of this register,
13342              then alter the notes there appropriately.
13343
13344              If the register is used as an input in I3, it dies there.
13345              Similarly for I2, if it is nonzero and adjacent to I3.
13346
13347              If the register is not used as an input in either I3 or I2
13348              and it is not one of the registers we were supposed to eliminate,
13349              there are two possibilities.  We might have a non-adjacent I2
13350              or we might have somehow eliminated an additional register
13351              from a computation.  For example, we might have had A & B where
13352              we discover that B will always be zero.  In this case we will
13353              eliminate the reference to A.
13354
13355              In both cases, we must search to see if we can find a previous
13356              use of A and put the death note there.  */
13357
13358           if (from_insn
13359               && from_insn == i2mod
13360               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13361             tem = from_insn;
13362           else
13363             {
13364               if (from_insn
13365                   && CALL_P (from_insn)
13366                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13367                 place = from_insn;
13368               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13369                 place = i3;
13370               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13371                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13372                 place = i2;
13373               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13374                         && !(i2mod
13375                              && reg_overlap_mentioned_p (XEXP (note, 0),
13376                                                          i2mod_old_rhs)))
13377                        || rtx_equal_p (XEXP (note, 0), elim_i1)
13378                        || rtx_equal_p (XEXP (note, 0), elim_i0))
13379                 break;
13380               tem = i3;
13381             }
13382
13383           if (place == 0)
13384             {
13385               basic_block bb = this_basic_block;
13386
13387               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13388                 {
13389                   if (!NONDEBUG_INSN_P (tem))
13390                     {
13391                       if (tem == BB_HEAD (bb))
13392                         break;
13393                       continue;
13394                     }
13395
13396                   /* If the register is being set at TEM, see if that is all
13397                      TEM is doing.  If so, delete TEM.  Otherwise, make this
13398                      into a REG_UNUSED note instead. Don't delete sets to
13399                      global register vars.  */
13400                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13401                        || !global_regs[REGNO (XEXP (note, 0))])
13402                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13403                     {
13404                       rtx set = single_set (tem);
13405                       rtx inner_dest = 0;
13406 #ifdef HAVE_cc0
13407                       rtx cc0_setter = NULL_RTX;
13408 #endif
13409
13410                       if (set != 0)
13411                         for (inner_dest = SET_DEST (set);
13412                              (GET_CODE (inner_dest) == STRICT_LOW_PART
13413                               || GET_CODE (inner_dest) == SUBREG
13414                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
13415                              inner_dest = XEXP (inner_dest, 0))
13416                           ;
13417
13418                       /* Verify that it was the set, and not a clobber that
13419                          modified the register.
13420
13421                          CC0 targets must be careful to maintain setter/user
13422                          pairs.  If we cannot delete the setter due to side
13423                          effects, mark the user with an UNUSED note instead
13424                          of deleting it.  */
13425
13426                       if (set != 0 && ! side_effects_p (SET_SRC (set))
13427                           && rtx_equal_p (XEXP (note, 0), inner_dest)
13428 #ifdef HAVE_cc0
13429                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13430                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13431                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13432 #endif
13433                           )
13434                         {
13435                           /* Move the notes and links of TEM elsewhere.
13436                              This might delete other dead insns recursively.
13437                              First set the pattern to something that won't use
13438                              any register.  */
13439                           rtx old_notes = REG_NOTES (tem);
13440
13441                           PATTERN (tem) = pc_rtx;
13442                           REG_NOTES (tem) = NULL;
13443
13444                           distribute_notes (old_notes, tem, tem, NULL_RTX,
13445                                             NULL_RTX, NULL_RTX, NULL_RTX);
13446                           distribute_links (LOG_LINKS (tem));
13447
13448                           SET_INSN_DELETED (tem);
13449                           if (tem == i2)
13450                             i2 = NULL_RTX;
13451
13452 #ifdef HAVE_cc0
13453                           /* Delete the setter too.  */
13454                           if (cc0_setter)
13455                             {
13456                               PATTERN (cc0_setter) = pc_rtx;
13457                               old_notes = REG_NOTES (cc0_setter);
13458                               REG_NOTES (cc0_setter) = NULL;
13459
13460                               distribute_notes (old_notes, cc0_setter,
13461                                                 cc0_setter, NULL_RTX,
13462                                                 NULL_RTX, NULL_RTX, NULL_RTX);
13463                               distribute_links (LOG_LINKS (cc0_setter));
13464
13465                               SET_INSN_DELETED (cc0_setter);
13466                               if (cc0_setter == i2)
13467                                 i2 = NULL_RTX;
13468                             }
13469 #endif
13470                         }
13471                       else
13472                         {
13473                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
13474
13475                           /*  If there isn't already a REG_UNUSED note, put one
13476                               here.  Do not place a REG_DEAD note, even if
13477                               the register is also used here; that would not
13478                               match the algorithm used in lifetime analysis
13479                               and can cause the consistency check in the
13480                               scheduler to fail.  */
13481                           if (! find_regno_note (tem, REG_UNUSED,
13482                                                  REGNO (XEXP (note, 0))))
13483                             place = tem;
13484                           break;
13485                         }
13486                     }
13487                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13488                            || (CALL_P (tem)
13489                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
13490                     {
13491                       place = tem;
13492
13493                       /* If we are doing a 3->2 combination, and we have a
13494                          register which formerly died in i3 and was not used
13495                          by i2, which now no longer dies in i3 and is used in
13496                          i2 but does not die in i2, and place is between i2
13497                          and i3, then we may need to move a link from place to
13498                          i2.  */
13499                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13500                           && from_insn
13501                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13502                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13503                         {
13504                           struct insn_link *links = LOG_LINKS (place);
13505                           LOG_LINKS (place) = NULL;
13506                           distribute_links (links);
13507                         }
13508                       break;
13509                     }
13510
13511                   if (tem == BB_HEAD (bb))
13512                     break;
13513                 }
13514
13515             }
13516
13517           /* If the register is set or already dead at PLACE, we needn't do
13518              anything with this note if it is still a REG_DEAD note.
13519              We check here if it is set at all, not if is it totally replaced,
13520              which is what `dead_or_set_p' checks, so also check for it being
13521              set partially.  */
13522
13523           if (place && REG_NOTE_KIND (note) == REG_DEAD)
13524             {
13525               unsigned int regno = REGNO (XEXP (note, 0));
13526               reg_stat_type *rsp = &reg_stat[regno];
13527
13528               if (dead_or_set_p (place, XEXP (note, 0))
13529                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13530                 {
13531                   /* Unless the register previously died in PLACE, clear
13532                      last_death.  [I no longer understand why this is
13533                      being done.] */
13534                   if (rsp->last_death != place)
13535                     rsp->last_death = 0;
13536                   place = 0;
13537                 }
13538               else
13539                 rsp->last_death = place;
13540
13541               /* If this is a death note for a hard reg that is occupying
13542                  multiple registers, ensure that we are still using all
13543                  parts of the object.  If we find a piece of the object
13544                  that is unused, we must arrange for an appropriate REG_DEAD
13545                  note to be added for it.  However, we can't just emit a USE
13546                  and tag the note to it, since the register might actually
13547                  be dead; so we recourse, and the recursive call then finds
13548                  the previous insn that used this register.  */
13549
13550               if (place && regno < FIRST_PSEUDO_REGISTER
13551                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13552                 {
13553                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13554                   int all_used = 1;
13555                   unsigned int i;
13556
13557                   for (i = regno; i < endregno; i++)
13558                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13559                          && ! find_regno_fusage (place, USE, i))
13560                         || dead_or_set_regno_p (place, i))
13561                       all_used = 0;
13562
13563                   if (! all_used)
13564                     {
13565                       /* Put only REG_DEAD notes for pieces that are
13566                          not already dead or set.  */
13567
13568                       for (i = regno; i < endregno;
13569                            i += hard_regno_nregs[i][reg_raw_mode[i]])
13570                         {
13571                           rtx piece = regno_reg_rtx[i];
13572                           basic_block bb = this_basic_block;
13573
13574                           if (! dead_or_set_p (place, piece)
13575                               && ! reg_bitfield_target_p (piece,
13576                                                           PATTERN (place)))
13577                             {
13578                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
13579                                                              NULL_RTX);
13580
13581                               distribute_notes (new_note, place, place,
13582                                                 NULL_RTX, NULL_RTX, NULL_RTX,
13583                                                 NULL_RTX);
13584                             }
13585                           else if (! refers_to_regno_p (i, i + 1,
13586                                                         PATTERN (place), 0)
13587                                    && ! find_regno_fusage (place, USE, i))
13588                             for (tem = PREV_INSN (place); ;
13589                                  tem = PREV_INSN (tem))
13590                               {
13591                                 if (!NONDEBUG_INSN_P (tem))
13592                                   {
13593                                     if (tem == BB_HEAD (bb))
13594                                       break;
13595                                     continue;
13596                                   }
13597                                 if (dead_or_set_p (tem, piece)
13598                                     || reg_bitfield_target_p (piece,
13599                                                               PATTERN (tem)))
13600                                   {
13601                                     add_reg_note (tem, REG_UNUSED, piece);
13602                                     break;
13603                                   }
13604                               }
13605
13606                         }
13607
13608                       place = 0;
13609                     }
13610                 }
13611             }
13612           break;
13613
13614         default:
13615           /* Any other notes should not be present at this point in the
13616              compilation.  */
13617           gcc_unreachable ();
13618         }
13619
13620       if (place)
13621         {
13622           XEXP (note, 1) = REG_NOTES (place);
13623           REG_NOTES (place) = note;
13624         }
13625
13626       if (place2)
13627         add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13628     }
13629 }
13630 \f
13631 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13632    I3, I2, and I1 to new locations.  This is also called to add a link
13633    pointing at I3 when I3's destination is changed.  */
13634
13635 static void
13636 distribute_links (struct insn_link *links)
13637 {
13638   struct insn_link *link, *next_link;
13639
13640   for (link = links; link; link = next_link)
13641     {
13642       rtx place = 0;
13643       rtx insn;
13644       rtx set, reg;
13645
13646       next_link = link->next;
13647
13648       /* If the insn that this link points to is a NOTE or isn't a single
13649          set, ignore it.  In the latter case, it isn't clear what we
13650          can do other than ignore the link, since we can't tell which
13651          register it was for.  Such links wouldn't be used by combine
13652          anyway.
13653
13654          It is not possible for the destination of the target of the link to
13655          have been changed by combine.  The only potential of this is if we
13656          replace I3, I2, and I1 by I3 and I2.  But in that case the
13657          destination of I2 also remains unchanged.  */
13658
13659       if (NOTE_P (link->insn)
13660           || (set = single_set (link->insn)) == 0)
13661         continue;
13662
13663       reg = SET_DEST (set);
13664       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13665              || GET_CODE (reg) == STRICT_LOW_PART)
13666         reg = XEXP (reg, 0);
13667
13668       /* A LOG_LINK is defined as being placed on the first insn that uses
13669          a register and points to the insn that sets the register.  Start
13670          searching at the next insn after the target of the link and stop
13671          when we reach a set of the register or the end of the basic block.
13672
13673          Note that this correctly handles the link that used to point from
13674          I3 to I2.  Also note that not much searching is typically done here
13675          since most links don't point very far away.  */
13676
13677       for (insn = NEXT_INSN (link->insn);
13678            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13679                      || BB_HEAD (this_basic_block->next_bb) != insn));
13680            insn = NEXT_INSN (insn))
13681         if (DEBUG_INSN_P (insn))
13682           continue;
13683         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13684           {
13685             if (reg_referenced_p (reg, PATTERN (insn)))
13686               place = insn;
13687             break;
13688           }
13689         else if (CALL_P (insn)
13690                  && find_reg_fusage (insn, USE, reg))
13691           {
13692             place = insn;
13693             break;
13694           }
13695         else if (INSN_P (insn) && reg_set_p (reg, insn))
13696           break;
13697
13698       /* If we found a place to put the link, place it there unless there
13699          is already a link to the same insn as LINK at that point.  */
13700
13701       if (place)
13702         {
13703           struct insn_link *link2;
13704
13705           FOR_EACH_LOG_LINK (link2, place)
13706             if (link2->insn == link->insn)
13707               break;
13708
13709           if (link2 == NULL)
13710             {
13711               link->next = LOG_LINKS (place);
13712               LOG_LINKS (place) = link;
13713
13714               /* Set added_links_insn to the earliest insn we added a
13715                  link to.  */
13716               if (added_links_insn == 0
13717                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13718                 added_links_insn = place;
13719             }
13720         }
13721     }
13722 }
13723 \f
13724 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13725    Check whether the expression pointer to by LOC is a register or
13726    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13727    Otherwise return zero.  */
13728
13729 static int
13730 unmentioned_reg_p_1 (rtx *loc, void *expr)
13731 {
13732   rtx x = *loc;
13733
13734   if (x != NULL_RTX
13735       && (REG_P (x) || MEM_P (x))
13736       && ! reg_mentioned_p (x, (rtx) expr))
13737     return 1;
13738   return 0;
13739 }
13740
13741 /* Check for any register or memory mentioned in EQUIV that is not
13742    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
13743    of EXPR where some registers may have been replaced by constants.  */
13744
13745 static bool
13746 unmentioned_reg_p (rtx equiv, rtx expr)
13747 {
13748   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13749 }
13750 \f
13751 DEBUG_FUNCTION void
13752 dump_combine_stats (FILE *file)
13753 {
13754   fprintf
13755     (file,
13756      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13757      combine_attempts, combine_merges, combine_extras, combine_successes);
13758 }
13759
13760 void
13761 dump_combine_total_stats (FILE *file)
13762 {
13763   fprintf
13764     (file,
13765      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13766      total_attempts, total_merges, total_extras, total_successes);
13767 }
13768 \f
13769 static bool
13770 gate_handle_combine (void)
13771 {
13772   return (optimize > 0);
13773 }
13774
13775 /* Try combining insns through substitution.  */
13776 static unsigned int
13777 rest_of_handle_combine (void)
13778 {
13779   int rebuild_jump_labels_after_combine;
13780
13781   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13782   df_note_add_problem ();
13783   df_analyze ();
13784
13785   regstat_init_n_sets_and_refs ();
13786
13787   rebuild_jump_labels_after_combine
13788     = combine_instructions (get_insns (), max_reg_num ());
13789
13790   /* Combining insns may have turned an indirect jump into a
13791      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13792      instructions.  */
13793   if (rebuild_jump_labels_after_combine)
13794     {
13795       timevar_push (TV_JUMP);
13796       rebuild_jump_labels (get_insns ());
13797       cleanup_cfg (0);
13798       timevar_pop (TV_JUMP);
13799     }
13800
13801   regstat_free_n_sets_and_refs ();
13802   return 0;
13803 }
13804
13805 struct rtl_opt_pass pass_combine =
13806 {
13807  {
13808   RTL_PASS,
13809   "combine",                            /* name */
13810   OPTGROUP_NONE,                        /* optinfo_flags */
13811   gate_handle_combine,                  /* gate */
13812   rest_of_handle_combine,               /* execute */
13813   NULL,                                 /* sub */
13814   NULL,                                 /* next */
13815   0,                                    /* static_pass_number */
13816   TV_COMBINE,                           /* tv_id */
13817   PROP_cfglayout,                       /* properties_required */
13818   0,                                    /* properties_provided */
13819   0,                                    /* properties_destroyed */
13820   0,                                    /* todo_flags_start */
13821   TODO_df_finish | TODO_verify_rtl_sharing /* todo_flags_finish */
13822  }
13823 };