| blob | f8ed145350e51a0bff99527dccbedca17931b661 |
1 ;; AltiVec patterns.
2 ;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 (define_constants
23 [(UNSPEC_VCMPBFP 50)
24 (UNSPEC_VCMPEQUB 51)
25 (UNSPEC_VCMPEQUH 52)
26 (UNSPEC_VCMPEQUW 53)
27 (UNSPEC_VCMPEQFP 54)
28 (UNSPEC_VCMPGEFP 55)
29 (UNSPEC_VCMPGTUB 56)
30 (UNSPEC_VCMPGTSB 57)
31 (UNSPEC_VCMPGTUH 58)
32 (UNSPEC_VCMPGTSH 59)
33 (UNSPEC_VCMPGTUW 60)
34 (UNSPEC_VCMPGTSW 61)
35 (UNSPEC_VCMPGTFP 62)
36 (UNSPEC_VMSUMU 65)
37 (UNSPEC_VMSUMM 66)
38 (UNSPEC_VMSUMSHM 68)
39 (UNSPEC_VMSUMUHS 69)
40 (UNSPEC_VMSUMSHS 70)
41 (UNSPEC_VMHADDSHS 71)
42 (UNSPEC_VMHRADDSHS 72)
43 (UNSPEC_VMLADDUHM 73)
44 (UNSPEC_VADDCUW 75)
45 (UNSPEC_VADDU 76)
46 (UNSPEC_VADDS 77)
47 (UNSPEC_VAVGU 80)
48 (UNSPEC_VAVGS 81)
49 (UNSPEC_VMULEUB 83)
50 (UNSPEC_VMULESB 84)
51 (UNSPEC_VMULEUH 85)
52 (UNSPEC_VMULESH 86)
53 (UNSPEC_VMULOUB 87)
54 (UNSPEC_VMULOSB 88)
55 (UNSPEC_VMULOUH 89)
56 (UNSPEC_VMULOSH 90)
57 (UNSPEC_VPKUHUM 93)
58 (UNSPEC_VPKUWUM 94)
59 (UNSPEC_VPKPX 95)
60 (UNSPEC_VPKSHSS 97)
61 (UNSPEC_VPKSWSS 99)
62 (UNSPEC_VPKUHUS 100)
63 (UNSPEC_VPKSHUS 101)
64 (UNSPEC_VPKUWUS 102)
65 (UNSPEC_VPKSWUS 103)
66 (UNSPEC_VRL 104)
67 (UNSPEC_VSLV4SI 110)
68 (UNSPEC_VSLO 111)
69 (UNSPEC_VSR 118)
70 (UNSPEC_VSRO 119)
71 (UNSPEC_VSUBCUW 124)
72 (UNSPEC_VSUBU 125)
73 (UNSPEC_VSUBS 126)
74 (UNSPEC_VSUM4UBS 131)
75 (UNSPEC_VSUM4S 132)
76 (UNSPEC_VSUM2SWS 134)
77 (UNSPEC_VSUMSWS 135)
78 (UNSPEC_VPERM 144)
79 (UNSPEC_VRFIP 148)
80 (UNSPEC_VRFIN 149)
81 (UNSPEC_VRFIM 150)
82 (UNSPEC_VCFUX 151)
83 (UNSPEC_VCFSX 152)
84 (UNSPEC_VCTUXS 153)
85 (UNSPEC_VCTSXS 154)
86 (UNSPEC_VLOGEFP 155)
87 (UNSPEC_VEXPTEFP 156)
88 (UNSPEC_VRSQRTEFP 157)
89 (UNSPEC_VREFP 158)
90 (UNSPEC_VSEL4SI 159)
91 (UNSPEC_VSEL4SF 160)
92 (UNSPEC_VSEL8HI 161)
93 (UNSPEC_VSEL16QI 162)
94 (UNSPEC_VLSDOI 163)
95 (UNSPEC_VUPKHSB 167)
96 (UNSPEC_VUPKHPX 168)
97 (UNSPEC_VUPKHSH 169)
98 (UNSPEC_VUPKLSB 170)
99 (UNSPEC_VUPKLPX 171)
100 (UNSPEC_VUPKLSH 172)
101 (UNSPEC_PREDICATE 173)
102 (UNSPEC_DST 190)
103 (UNSPEC_DSTT 191)
104 (UNSPEC_DSTST 192)
105 (UNSPEC_DSTSTT 193)
106 (UNSPEC_LVSL 194)
107 (UNSPEC_LVSR 195)
108 (UNSPEC_LVE 196)
109 (UNSPEC_STVX 201)
110 (UNSPEC_STVXL 202)
111 (UNSPEC_STVE 203)
112 (UNSPEC_SET_VSCR 213)
113 (UNSPEC_GET_VRSAVE 214)
114 (UNSPEC_REALIGN_LOAD 215)
115 (UNSPEC_REDUC_PLUS 217)
116 (UNSPEC_VECSH 219)
117 (UNSPEC_EXTEVEN_V4SI 220)
118 (UNSPEC_EXTEVEN_V8HI 221)
119 (UNSPEC_EXTEVEN_V16QI 222)
120 (UNSPEC_EXTEVEN_V4SF 223)
121 (UNSPEC_EXTODD_V4SI 224)
122 (UNSPEC_EXTODD_V8HI 225)
123 (UNSPEC_EXTODD_V16QI 226)
124 (UNSPEC_EXTODD_V4SF 227)
125 (UNSPEC_INTERHI_V4SI 228)
126 (UNSPEC_INTERHI_V8HI 229)
127 (UNSPEC_INTERHI_V16QI 230)
128 (UNSPEC_INTERHI_V4SF 231)
129 (UNSPEC_INTERLO_V4SI 232)
130 (UNSPEC_INTERLO_V8HI 233)
131 (UNSPEC_INTERLO_V16QI 234)
132 (UNSPEC_INTERLO_V4SF 235)
133 (UNSPEC_VMULWHUB 308)
134 (UNSPEC_VMULWLUB 309)
135 (UNSPEC_VMULWHSB 310)
136 (UNSPEC_VMULWLSB 311)
137 (UNSPEC_VMULWHUH 312)
138 (UNSPEC_VMULWLUH 313)
139 (UNSPEC_VMULWHSH 314)
140 (UNSPEC_VMULWLSH 315)
141 (UNSPEC_VUPKHUB 316)
142 (UNSPEC_VUPKHUH 317)
143 (UNSPEC_VUPKLUB 318)
144 (UNSPEC_VUPKLUH 319)
145 (UNSPEC_VPERMSI 320)
146 (UNSPEC_VPERMHI 321)
147 (UNSPEC_INTERHI 322)
148 (UNSPEC_INTERLO 323)
149 (UNSPEC_VUPKHS_V4SF 324)
150 (UNSPEC_VUPKLS_V4SF 325)
151 (UNSPEC_VUPKHU_V4SF 326)
152 (UNSPEC_VUPKLU_V4SF 327)
153 ])
155 (define_constants
156 [(UNSPECV_SET_VRSAVE 30)
157 (UNSPECV_MTVSCR 186)
158 (UNSPECV_MFVSCR 187)
159 (UNSPECV_DSSALL 188)
160 (UNSPECV_DSS 189)
161 ])
163 ;; Vec int modes
164 (define_mode_iterator VI [V4SI V8HI V16QI])
165 ;; Short vec in modes
166 (define_mode_iterator VIshort [V8HI V16QI])
167 ;; Vec float modes
168 (define_mode_iterator VF [V4SF])
169 ;; Vec modes, pity mode iterators are not composable
170 (define_mode_iterator V [V4SI V8HI V16QI V4SF])
172 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
174 ;; Generic LVX load instruction.
175 (define_insn "altivec_lvx_<mode>"
176 [(set (match_operand:V 0 "altivec_register_operand" "=v")
177 (match_operand:V 1 "memory_operand" "Z"))]
178 "TARGET_ALTIVEC"
179 "lvx %0,%y1"
180 [(set_attr "type" "vecload")])
182 ;; Generic STVX store instruction.
183 (define_insn "altivec_stvx_<mode>"
184 [(set (match_operand:V 0 "memory_operand" "=Z")
185 (match_operand:V 1 "altivec_register_operand" "v"))]
186 "TARGET_ALTIVEC"
187 "stvx %1,%y0"
188 [(set_attr "type" "vecstore")])
190 ;; Vector move instructions.
191 (define_expand "mov<mode>"
192 [(set (match_operand:V 0 "nonimmediate_operand" "")
193 (match_operand:V 1 "any_operand" ""))]
194 "TARGET_ALTIVEC"
195 {
196 rs6000_emit_move (operands[0], operands[1], <MODE>mode);
197 DONE;
198 })
200 (define_insn "*mov<mode>_internal"
201 [(set (match_operand:V 0 "nonimmediate_operand" "=Z,v,v,o,r,r,v")
202 (match_operand:V 1 "input_operand" "v,Z,v,r,o,r,W"))]
203 "TARGET_ALTIVEC
204 && (register_operand (operands[0], <MODE>mode)
205 || register_operand (operands[1], <MODE>mode))"
206 {
207 switch (which_alternative)
208 {
209 case 0: return "stvx %1,%y0";
210 case 1: return "lvx %0,%y1";
211 case 2: return "vor %0,%1,%1";
212 case 3: return "#";
213 case 4: return "#";
214 case 5: return "#";
215 case 6: return output_vec_const_move (operands);
216 default: gcc_unreachable ();
217 }
218 }
219 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
221 (define_split
222 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
223 (match_operand:V4SI 1 "input_operand" ""))]
224 "TARGET_ALTIVEC && reload_completed
225 && gpr_or_gpr_p (operands[0], operands[1])"
226 [(pc)]
227 {
228 rs6000_split_multireg_move (operands[0], operands[1]); DONE;
229 })
231 (define_split
232 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
233 (match_operand:V8HI 1 "input_operand" ""))]
234 "TARGET_ALTIVEC && reload_completed
235 && gpr_or_gpr_p (operands[0], operands[1])"
236 [(pc)]
237 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
239 (define_split
240 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
241 (match_operand:V16QI 1 "input_operand" ""))]
242 "TARGET_ALTIVEC && reload_completed
243 && gpr_or_gpr_p (operands[0], operands[1])"
244 [(pc)]
245 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
247 (define_split
248 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
249 (match_operand:V4SF 1 "input_operand" ""))]
250 "TARGET_ALTIVEC && reload_completed
251 && gpr_or_gpr_p (operands[0], operands[1])"
252 [(pc)]
253 {
254 rs6000_split_multireg_move (operands[0], operands[1]); DONE;
255 })
257 (define_split
258 [(set (match_operand:VI 0 "altivec_register_operand" "")
259 (match_operand:VI 1 "easy_vector_constant_add_self" ""))]
260 "TARGET_ALTIVEC && reload_completed"
261 [(set (match_dup 0) (match_dup 3))
262 (set (match_dup 0) (plus:VI (match_dup 0)
263 (match_dup 0)))]
264 {
265 rtx dup = gen_easy_altivec_constant (operands[1]);
266 rtx const_vec;
268 /* Divide the operand of the resulting VEC_DUPLICATE, and use
269 simplify_rtx to make a CONST_VECTOR. */
270 XEXP (dup, 0) = simplify_const_binary_operation (ASHIFTRT, QImode,
271 XEXP (dup, 0), const1_rtx);
272 const_vec = simplify_rtx (dup);
274 if (GET_MODE (const_vec) == <MODE>mode)
275 operands[3] = const_vec;
276 else
277 operands[3] = gen_lowpart (<MODE>mode, const_vec);
278 })
280 (define_insn "get_vrsave_internal"
281 [(set (match_operand:SI 0 "register_operand" "=r")
282 (unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))]
283 "TARGET_ALTIVEC"
284 {
285 if (TARGET_MACHO)
286 return "mfspr %0,256";
287 else
288 return "mfvrsave %0";
289 }
290 [(set_attr "type" "*")])
292 (define_insn "*set_vrsave_internal"
293 [(match_parallel 0 "vrsave_operation"
294 [(set (reg:SI 109)
295 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
296 (reg:SI 109)] UNSPECV_SET_VRSAVE))])]
297 "TARGET_ALTIVEC"
298 {
299 if (TARGET_MACHO)
300 return "mtspr 256,%1";
301 else
302 return "mtvrsave %1";
303 }
304 [(set_attr "type" "*")])
306 (define_insn "*save_world"
307 [(match_parallel 0 "save_world_operation"
308 [(clobber (reg:SI 65))
309 (use (match_operand:SI 1 "call_operand" "s"))])]
310 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
311 "bl %z1"
312 [(set_attr "type" "branch")
313 (set_attr "length" "4")])
315 (define_insn "*restore_world"
316 [(match_parallel 0 "restore_world_operation"
317 [(return)
318 (use (reg:SI 65))
319 (use (match_operand:SI 1 "call_operand" "s"))
320 (clobber (match_operand:SI 2 "gpc_reg_operand" "=r"))])]
321 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
322 "b %z1")
324 ;; Simple binary operations.
326 ;; add
327 (define_insn "add<mode>3"
328 [(set (match_operand:VI 0 "register_operand" "=v")
329 (plus:VI (match_operand:VI 1 "register_operand" "v")
330 (match_operand:VI 2 "register_operand" "v")))]
331 "TARGET_ALTIVEC"
332 "vaddu<VI_char>m %0,%1,%2"
333 [(set_attr "type" "vecsimple")])
335 (define_insn "addv4sf3"
336 [(set (match_operand:V4SF 0 "register_operand" "=v")
337 (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
338 (match_operand:V4SF 2 "register_operand" "v")))]
339 "TARGET_ALTIVEC"
340 "vaddfp %0,%1,%2"
341 [(set_attr "type" "vecfloat")])
343 (define_insn "altivec_vaddcuw"
344 [(set (match_operand:V4SI 0 "register_operand" "=v")
345 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
346 (match_operand:V4SI 2 "register_operand" "v")]
347 UNSPEC_VADDCUW))]
348 "TARGET_ALTIVEC"
349 "vaddcuw %0,%1,%2"
350 [(set_attr "type" "vecsimple")])
352 (define_insn "altivec_vaddu<VI_char>s"
353 [(set (match_operand:VI 0 "register_operand" "=v")
354 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
355 (match_operand:VI 2 "register_operand" "v")]
356 UNSPEC_VADDU))
357 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
358 "TARGET_ALTIVEC"
359 "vaddu<VI_char>s %0,%1,%2"
360 [(set_attr "type" "vecsimple")])
362 (define_insn "altivec_vadds<VI_char>s"
363 [(set (match_operand:VI 0 "register_operand" "=v")
364 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
365 (match_operand:VI 2 "register_operand" "v")]
366 UNSPEC_VADDS))
367 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
368 "TARGET_ALTIVEC"
369 "vadds<VI_char>s %0,%1,%2"
370 [(set_attr "type" "vecsimple")])
372 ;; sub
373 (define_insn "sub<mode>3"
374 [(set (match_operand:VI 0 "register_operand" "=v")
375 (minus:VI (match_operand:VI 1 "register_operand" "v")
376 (match_operand:VI 2 "register_operand" "v")))]
377 "TARGET_ALTIVEC"
378 "vsubu<VI_char>m %0,%1,%2"
379 [(set_attr "type" "vecsimple")])
381 (define_insn "subv4sf3"
382 [(set (match_operand:V4SF 0 "register_operand" "=v")
383 (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
384 (match_operand:V4SF 2 "register_operand" "v")))]
385 "TARGET_ALTIVEC"
386 "vsubfp %0,%1,%2"
387 [(set_attr "type" "vecfloat")])
389 (define_insn "altivec_vsubcuw"
390 [(set (match_operand:V4SI 0 "register_operand" "=v")
391 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
392 (match_operand:V4SI 2 "register_operand" "v")]
393 UNSPEC_VSUBCUW))]
394 "TARGET_ALTIVEC"
395 "vsubcuw %0,%1,%2"
396 [(set_attr "type" "vecsimple")])
398 (define_insn "altivec_vsubu<VI_char>s"
399 [(set (match_operand:VI 0 "register_operand" "=v")
400 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
401 (match_operand:VI 2 "register_operand" "v")]
402 UNSPEC_VSUBU))
403 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
404 "TARGET_ALTIVEC"
405 "vsubu<VI_char>s %0,%1,%2"
406 [(set_attr "type" "vecsimple")])
408 (define_insn "altivec_vsubs<VI_char>s"
409 [(set (match_operand:VI 0 "register_operand" "=v")
410 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
411 (match_operand:VI 2 "register_operand" "v")]
412 UNSPEC_VSUBS))
413 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
414 "TARGET_ALTIVEC"
415 "vsubs<VI_char>s %0,%1,%2"
416 [(set_attr "type" "vecsimple")])
418 ;;
419 (define_insn "altivec_vavgu<VI_char>"
420 [(set (match_operand:VI 0 "register_operand" "=v")
421 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
422 (match_operand:VI 2 "register_operand" "v")]
423 UNSPEC_VAVGU))]
424 "TARGET_ALTIVEC"
425 "vavgu<VI_char> %0,%1,%2"
426 [(set_attr "type" "vecsimple")])
428 (define_insn "altivec_vavgs<VI_char>"
429 [(set (match_operand:VI 0 "register_operand" "=v")
430 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
431 (match_operand:VI 2 "register_operand" "v")]
432 UNSPEC_VAVGS))]
433 "TARGET_ALTIVEC"
434 "vavgs<VI_char> %0,%1,%2"
435 [(set_attr "type" "vecsimple")])
437 (define_insn "altivec_vcmpbfp"
438 [(set (match_operand:V4SI 0 "register_operand" "=v")
439 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
440 (match_operand:V4SF 2 "register_operand" "v")]
441 UNSPEC_VCMPBFP))]
442 "TARGET_ALTIVEC"
443 "vcmpbfp %0,%1,%2"
444 [(set_attr "type" "veccmp")])
446 (define_insn "altivec_vcmpequb"
447 [(set (match_operand:V16QI 0 "register_operand" "=v")
448 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
449 (match_operand:V16QI 2 "register_operand" "v")]
450 UNSPEC_VCMPEQUB))]
451 "TARGET_ALTIVEC"
452 "vcmpequb %0,%1,%2"
453 [(set_attr "type" "vecsimple")])
455 (define_insn "altivec_vcmpequh"
456 [(set (match_operand:V8HI 0 "register_operand" "=v")
457 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
458 (match_operand:V8HI 2 "register_operand" "v")]
459 UNSPEC_VCMPEQUH))]
460 "TARGET_ALTIVEC"
461 "vcmpequh %0,%1,%2"
462 [(set_attr "type" "vecsimple")])
464 (define_insn "altivec_vcmpequw"
465 [(set (match_operand:V4SI 0 "register_operand" "=v")
466 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
467 (match_operand:V4SI 2 "register_operand" "v")]
468 UNSPEC_VCMPEQUW))]
469 "TARGET_ALTIVEC"
470 "vcmpequw %0,%1,%2"
471 [(set_attr "type" "vecsimple")])
473 (define_insn "altivec_vcmpeqfp"
474 [(set (match_operand:V4SI 0 "register_operand" "=v")
475 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
476 (match_operand:V4SF 2 "register_operand" "v")]
477 UNSPEC_VCMPEQFP))]
478 "TARGET_ALTIVEC"
479 "vcmpeqfp %0,%1,%2"
480 [(set_attr "type" "veccmp")])
482 (define_insn "altivec_vcmpgefp"
483 [(set (match_operand:V4SI 0 "register_operand" "=v")
484 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
485 (match_operand:V4SF 2 "register_operand" "v")]
486 UNSPEC_VCMPGEFP))]
487 "TARGET_ALTIVEC"
488 "vcmpgefp %0,%1,%2"
489 [(set_attr "type" "veccmp")])
491 (define_insn "altivec_vcmpgtub"
492 [(set (match_operand:V16QI 0 "register_operand" "=v")
493 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
494 (match_operand:V16QI 2 "register_operand" "v")]
495 UNSPEC_VCMPGTUB))]
496 "TARGET_ALTIVEC"
497 "vcmpgtub %0,%1,%2"
498 [(set_attr "type" "vecsimple")])
500 (define_insn "altivec_vcmpgtsb"
501 [(set (match_operand:V16QI 0 "register_operand" "=v")
502 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
503 (match_operand:V16QI 2 "register_operand" "v")]
504 UNSPEC_VCMPGTSB))]
505 "TARGET_ALTIVEC"
506 "vcmpgtsb %0,%1,%2"
507 [(set_attr "type" "vecsimple")])
509 (define_insn "altivec_vcmpgtuh"
510 [(set (match_operand:V8HI 0 "register_operand" "=v")
511 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
512 (match_operand:V8HI 2 "register_operand" "v")]
513 UNSPEC_VCMPGTUH))]
514 "TARGET_ALTIVEC"
515 "vcmpgtuh %0,%1,%2"
516 [(set_attr "type" "vecsimple")])
518 (define_insn "altivec_vcmpgtsh"
519 [(set (match_operand:V8HI 0 "register_operand" "=v")
520 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
521 (match_operand:V8HI 2 "register_operand" "v")]
522 UNSPEC_VCMPGTSH))]
523 "TARGET_ALTIVEC"
524 "vcmpgtsh %0,%1,%2"
525 [(set_attr "type" "vecsimple")])
527 (define_insn "altivec_vcmpgtuw"
528 [(set (match_operand:V4SI 0 "register_operand" "=v")
529 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
530 (match_operand:V4SI 2 "register_operand" "v")]
531 UNSPEC_VCMPGTUW))]
532 "TARGET_ALTIVEC"
533 "vcmpgtuw %0,%1,%2"
534 [(set_attr "type" "vecsimple")])
536 (define_insn "altivec_vcmpgtsw"
537 [(set (match_operand:V4SI 0 "register_operand" "=v")
538 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
539 (match_operand:V4SI 2 "register_operand" "v")]
540 UNSPEC_VCMPGTSW))]
541 "TARGET_ALTIVEC"
542 "vcmpgtsw %0,%1,%2"
543 [(set_attr "type" "vecsimple")])
545 (define_insn "altivec_vcmpgtfp"
546 [(set (match_operand:V4SI 0 "register_operand" "=v")
547 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
548 (match_operand:V4SF 2 "register_operand" "v")]
549 UNSPEC_VCMPGTFP))]
550 "TARGET_ALTIVEC"
551 "vcmpgtfp %0,%1,%2"
552 [(set_attr "type" "veccmp")])
554 ;; Fused multiply add
555 (define_insn "altivec_vmaddfp"
556 [(set (match_operand:V4SF 0 "register_operand" "=v")
557 (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
558 (match_operand:V4SF 2 "register_operand" "v"))
559 (match_operand:V4SF 3 "register_operand" "v")))]
560 "TARGET_ALTIVEC"
561 "vmaddfp %0,%1,%2,%3"
562 [(set_attr "type" "vecfloat")])
564 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
566 (define_expand "mulv4sf3"
567 [(use (match_operand:V4SF 0 "register_operand" ""))
568 (use (match_operand:V4SF 1 "register_operand" ""))
569 (use (match_operand:V4SF 2 "register_operand" ""))]
570 "TARGET_ALTIVEC && TARGET_FUSED_MADD"
571 "
572 {
573 rtx neg0;
575 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
576 neg0 = gen_reg_rtx (V4SImode);
577 emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
578 emit_insn (gen_vashlv4si3 (neg0, neg0, neg0));
580 /* Use the multiply-add. */
581 emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
582 gen_lowpart (V4SFmode, neg0)));
583 DONE;
584 }")
586 ;; 32-bit integer multiplication
587 ;; A_high = Operand_0 & 0xFFFF0000 >> 16
588 ;; A_low = Operand_0 & 0xFFFF
589 ;; B_high = Operand_1 & 0xFFFF0000 >> 16
590 ;; B_low = Operand_1 & 0xFFFF
591 ;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16
593 ;; (define_insn "mulv4si3"
594 ;; [(set (match_operand:V4SI 0 "register_operand" "=v")
595 ;; (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
596 ;; (match_operand:V4SI 2 "register_operand" "v")))]
597 (define_expand "mulv4si3"
598 [(use (match_operand:V4SI 0 "register_operand" ""))
599 (use (match_operand:V4SI 1 "register_operand" ""))
600 (use (match_operand:V4SI 2 "register_operand" ""))]
601 "TARGET_ALTIVEC"
602 "
603 {
604 rtx zero;
605 rtx swap;
606 rtx small_swap;
607 rtx sixteen;
608 rtx one;
609 rtx two;
610 rtx low_product;
611 rtx high_product;
613 zero = gen_reg_rtx (V4SImode);
614 emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
616 sixteen = gen_reg_rtx (V4SImode);
617 emit_insn (gen_altivec_vspltisw (sixteen, gen_rtx_CONST_INT (V4SImode, -16)));
619 swap = gen_reg_rtx (V4SImode);
620 emit_insn (gen_altivec_vrlw (swap, operands[2], sixteen));
622 one = gen_reg_rtx (V8HImode);
623 convert_move (one, operands[1], 0);
625 two = gen_reg_rtx (V8HImode);
626 convert_move (two, operands[2], 0);
628 small_swap = gen_reg_rtx (V8HImode);
629 convert_move (small_swap, swap, 0);
631 low_product = gen_reg_rtx (V4SImode);
632 emit_insn (gen_altivec_vmulouh (low_product, one, two));
634 high_product = gen_reg_rtx (V4SImode);
635 emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
637 emit_insn (gen_vashlv4si3 (high_product, high_product, sixteen));
639 emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
641 DONE;
642 }")
645 ;; Fused multiply subtract
646 (define_insn "altivec_vnmsubfp"
647 [(set (match_operand:V4SF 0 "register_operand" "=v")
648 (neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
649 (match_operand:V4SF 2 "register_operand" "v"))
650 (match_operand:V4SF 3 "register_operand" "v"))))]
651 "TARGET_ALTIVEC"
652 "vnmsubfp %0,%1,%2,%3"
653 [(set_attr "type" "vecfloat")])
655 (define_insn "altivec_vmsumu<VI_char>m"
656 [(set (match_operand:V4SI 0 "register_operand" "=v")
657 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
658 (match_operand:VIshort 2 "register_operand" "v")
659 (match_operand:V4SI 3 "register_operand" "v")]
660 UNSPEC_VMSUMU))]
661 "TARGET_ALTIVEC"
662 "vmsumu<VI_char>m %0,%1,%2,%3"
663 [(set_attr "type" "veccomplex")])
665 (define_insn "altivec_vmsumm<VI_char>m"
666 [(set (match_operand:V4SI 0 "register_operand" "=v")
667 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
668 (match_operand:VIshort 2 "register_operand" "v")
669 (match_operand:V4SI 3 "register_operand" "v")]
670 UNSPEC_VMSUMM))]
671 "TARGET_ALTIVEC"
672 "vmsumm<VI_char>m %0,%1,%2,%3"
673 [(set_attr "type" "veccomplex")])
675 (define_insn "altivec_vmsumshm"
676 [(set (match_operand:V4SI 0 "register_operand" "=v")
677 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
678 (match_operand:V8HI 2 "register_operand" "v")
679 (match_operand:V4SI 3 "register_operand" "v")]
680 UNSPEC_VMSUMSHM))]
681 "TARGET_ALTIVEC"
682 "vmsumshm %0,%1,%2,%3"
683 [(set_attr "type" "veccomplex")])
685 (define_insn "altivec_vmsumuhs"
686 [(set (match_operand:V4SI 0 "register_operand" "=v")
687 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
688 (match_operand:V8HI 2 "register_operand" "v")
689 (match_operand:V4SI 3 "register_operand" "v")]
690 UNSPEC_VMSUMUHS))
691 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
692 "TARGET_ALTIVEC"
693 "vmsumuhs %0,%1,%2,%3"
694 [(set_attr "type" "veccomplex")])
696 (define_insn "altivec_vmsumshs"
697 [(set (match_operand:V4SI 0 "register_operand" "=v")
698 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
699 (match_operand:V8HI 2 "register_operand" "v")
700 (match_operand:V4SI 3 "register_operand" "v")]
701 UNSPEC_VMSUMSHS))
702 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
703 "TARGET_ALTIVEC"
704 "vmsumshs %0,%1,%2,%3"
705 [(set_attr "type" "veccomplex")])
707 ;; max
709 (define_insn "umax<mode>3"
710 [(set (match_operand:VI 0 "register_operand" "=v")
711 (umax:VI (match_operand:VI 1 "register_operand" "v")
712 (match_operand:VI 2 "register_operand" "v")))]
713 "TARGET_ALTIVEC"
714 "vmaxu<VI_char> %0,%1,%2"
715 [(set_attr "type" "vecsimple")])
717 (define_insn "smax<mode>3"
718 [(set (match_operand:VI 0 "register_operand" "=v")
719 (smax:VI (match_operand:VI 1 "register_operand" "v")
720 (match_operand:VI 2 "register_operand" "v")))]
721 "TARGET_ALTIVEC"
722 "vmaxs<VI_char> %0,%1,%2"
723 [(set_attr "type" "vecsimple")])
725 (define_insn "smaxv4sf3"
726 [(set (match_operand:V4SF 0 "register_operand" "=v")
727 (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
728 (match_operand:V4SF 2 "register_operand" "v")))]
729 "TARGET_ALTIVEC"
730 "vmaxfp %0,%1,%2"
731 [(set_attr "type" "veccmp")])
733 (define_insn "umin<mode>3"
734 [(set (match_operand:VI 0 "register_operand" "=v")
735 (umin:VI (match_operand:VI 1 "register_operand" "v")
736 (match_operand:VI 2 "register_operand" "v")))]
737 "TARGET_ALTIVEC"
738 "vminu<VI_char> %0,%1,%2"
739 [(set_attr "type" "vecsimple")])
741 (define_insn "smin<mode>3"
742 [(set (match_operand:VI 0 "register_operand" "=v")
743 (smin:VI (match_operand:VI 1 "register_operand" "v")
744 (match_operand:VI 2 "register_operand" "v")))]
745 "TARGET_ALTIVEC"
746 "vmins<VI_char> %0,%1,%2"
747 [(set_attr "type" "vecsimple")])
749 (define_insn "sminv4sf3"
750 [(set (match_operand:V4SF 0 "register_operand" "=v")
751 (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
752 (match_operand:V4SF 2 "register_operand" "v")))]
753 "TARGET_ALTIVEC"
754 "vminfp %0,%1,%2"
755 [(set_attr "type" "veccmp")])
757 (define_insn "altivec_vmhaddshs"
758 [(set (match_operand:V8HI 0 "register_operand" "=v")
759 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
760 (match_operand:V8HI 2 "register_operand" "v")
761 (match_operand:V8HI 3 "register_operand" "v")]
762 UNSPEC_VMHADDSHS))
763 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
764 "TARGET_ALTIVEC"
765 "vmhaddshs %0,%1,%2,%3"
766 [(set_attr "type" "veccomplex")])
768 (define_insn "altivec_vmhraddshs"
769 [(set (match_operand:V8HI 0 "register_operand" "=v")
770 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
771 (match_operand:V8HI 2 "register_operand" "v")
772 (match_operand:V8HI 3 "register_operand" "v")]
773 UNSPEC_VMHRADDSHS))
774 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
775 "TARGET_ALTIVEC"
776 "vmhraddshs %0,%1,%2,%3"
777 [(set_attr "type" "veccomplex")])
779 (define_insn "altivec_vmladduhm"
780 [(set (match_operand:V8HI 0 "register_operand" "=v")
781 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
782 (match_operand:V8HI 2 "register_operand" "v")
783 (match_operand:V8HI 3 "register_operand" "v")]
784 UNSPEC_VMLADDUHM))]
785 "TARGET_ALTIVEC"
786 "vmladduhm %0,%1,%2,%3"
787 [(set_attr "type" "veccomplex")])
789 (define_insn "altivec_vmrghb"
790 [(set (match_operand:V16QI 0 "register_operand" "=v")
791 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
792 (parallel [(const_int 0)
793 (const_int 8)
794 (const_int 1)
795 (const_int 9)
796 (const_int 2)
797 (const_int 10)
798 (const_int 3)
799 (const_int 11)
800 (const_int 4)
801 (const_int 12)
802 (const_int 5)
803 (const_int 13)
804 (const_int 6)
805 (const_int 14)
806 (const_int 7)
807 (const_int 15)]))
808 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
809 (parallel [(const_int 8)
810 (const_int 0)
811 (const_int 9)
812 (const_int 1)
813 (const_int 10)
814 (const_int 2)
815 (const_int 11)
816 (const_int 3)
817 (const_int 12)
818 (const_int 4)
819 (const_int 13)
820 (const_int 5)
821 (const_int 14)
822 (const_int 6)
823 (const_int 15)
824 (const_int 7)]))
825 (const_int 21845)))]
826 "TARGET_ALTIVEC"
827 "vmrghb %0,%1,%2"
828 [(set_attr "type" "vecperm")])
830 (define_insn "altivec_vmrghh"
831 [(set (match_operand:V8HI 0 "register_operand" "=v")
832 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
833 (parallel [(const_int 0)
834 (const_int 4)
835 (const_int 1)
836 (const_int 5)
837 (const_int 2)
838 (const_int 6)
839 (const_int 3)
840 (const_int 7)]))
841 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
842 (parallel [(const_int 4)
843 (const_int 0)
844 (const_int 5)
845 (const_int 1)
846 (const_int 6)
847 (const_int 2)
848 (const_int 7)
849 (const_int 3)]))
850 (const_int 85)))]
851 "TARGET_ALTIVEC"
852 "vmrghh %0,%1,%2"
853 [(set_attr "type" "vecperm")])
855 (define_insn "altivec_vmrghw"
856 [(set (match_operand:V4SI 0 "register_operand" "=v")
857 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
858 (parallel [(const_int 0)
859 (const_int 2)
860 (const_int 1)
861 (const_int 3)]))
862 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
863 (parallel [(const_int 2)
864 (const_int 0)
865 (const_int 3)
866 (const_int 1)]))
867 (const_int 5)))]
868 "TARGET_ALTIVEC"
869 "vmrghw %0,%1,%2"
870 [(set_attr "type" "vecperm")])
872 (define_insn "altivec_vmrghsf"
873 [(set (match_operand:V4SF 0 "register_operand" "=v")
874 (vec_merge:V4SF (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "v")
875 (parallel [(const_int 0)
876 (const_int 2)
877 (const_int 1)
878 (const_int 3)]))
879 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "v")
880 (parallel [(const_int 2)
881 (const_int 0)
882 (const_int 3)
883 (const_int 1)]))
884 (const_int 5)))]
885 "TARGET_ALTIVEC"
886 "vmrghw %0,%1,%2"
887 [(set_attr "type" "vecperm")])
889 (define_insn "altivec_vmrglb"
890 [(set (match_operand:V16QI 0 "register_operand" "=v")
891 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
892 (parallel [(const_int 8)
893 (const_int 0)
894 (const_int 9)
895 (const_int 1)
896 (const_int 10)
897 (const_int 2)
898 (const_int 11)
899 (const_int 3)
900 (const_int 12)
901 (const_int 4)
902 (const_int 13)
903 (const_int 5)
904 (const_int 14)
905 (const_int 6)
906 (const_int 15)
907 (const_int 7)]))
908 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
909 (parallel [(const_int 0)
910 (const_int 8)
911 (const_int 1)
912 (const_int 9)
913 (const_int 2)
914 (const_int 10)
915 (const_int 3)
916 (const_int 11)
917 (const_int 4)
918 (const_int 12)
919 (const_int 5)
920 (const_int 13)
921 (const_int 6)
922 (const_int 14)
923 (const_int 7)
924 (const_int 15)]))
925 (const_int 21845)))]
926 "TARGET_ALTIVEC"
927 "vmrglb %0,%1,%2"
928 [(set_attr "type" "vecperm")])
930 (define_insn "altivec_vmrglh"
931 [(set (match_operand:V8HI 0 "register_operand" "=v")
932 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
933 (parallel [(const_int 4)
934 (const_int 0)
935 (const_int 5)
936 (const_int 1)
937 (const_int 6)
938 (const_int 2)
939 (const_int 7)
940 (const_int 3)]))
941 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
942 (parallel [(const_int 0)
943 (const_int 4)
944 (const_int 1)
945 (const_int 5)
946 (const_int 2)
947 (const_int 6)
948 (const_int 3)
949 (const_int 7)]))
950 (const_int 85)))]
951 "TARGET_ALTIVEC"
952 "vmrglh %0,%1,%2"
953 [(set_attr "type" "vecperm")])
955 (define_insn "altivec_vmrglw"
956 [(set (match_operand:V4SI 0 "register_operand" "=v")
957 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
958 (parallel [(const_int 2)
959 (const_int 0)
960 (const_int 3)
961 (const_int 1)]))
962 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
963 (parallel [(const_int 0)
964 (const_int 2)
965 (const_int 1)
966 (const_int 3)]))
967 (const_int 5)))]
968 "TARGET_ALTIVEC"
969 "vmrglw %0,%1,%2"
970 [(set_attr "type" "vecperm")])
972 (define_insn "altivec_vmrglsf"
973 [(set (match_operand:V4SF 0 "register_operand" "=v")
974 (vec_merge:V4SF (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "v")
975 (parallel [(const_int 2)
976 (const_int 0)
977 (const_int 3)
978 (const_int 1)]))
979 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "v")
980 (parallel [(const_int 0)
981 (const_int 2)
982 (const_int 1)
983 (const_int 3)]))
984 (const_int 5)))]
985 "TARGET_ALTIVEC"
986 "vmrglw %0,%1,%2"
987 [(set_attr "type" "vecperm")])
989 (define_insn "altivec_vmuleub"
990 [(set (match_operand:V8HI 0 "register_operand" "=v")
991 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
992 (match_operand:V16QI 2 "register_operand" "v")]
993 UNSPEC_VMULEUB))]
994 "TARGET_ALTIVEC"
995 "vmuleub %0,%1,%2"
996 [(set_attr "type" "veccomplex")])
998 (define_insn "altivec_vmulesb"
999 [(set (match_operand:V8HI 0 "register_operand" "=v")
1000 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1001 (match_operand:V16QI 2 "register_operand" "v")]
1002 UNSPEC_VMULESB))]
1003 "TARGET_ALTIVEC"
1004 "vmulesb %0,%1,%2"
1005 [(set_attr "type" "veccomplex")])
1007 (define_insn "altivec_vmuleuh"
1008 [(set (match_operand:V4SI 0 "register_operand" "=v")
1009 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1010 (match_operand:V8HI 2 "register_operand" "v")]
1011 UNSPEC_VMULEUH))]
1012 "TARGET_ALTIVEC"
1013 "vmuleuh %0,%1,%2"
1014 [(set_attr "type" "veccomplex")])
1016 (define_insn "altivec_vmulesh"
1017 [(set (match_operand:V4SI 0 "register_operand" "=v")
1018 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1019 (match_operand:V8HI 2 "register_operand" "v")]
1020 UNSPEC_VMULESH))]
1021 "TARGET_ALTIVEC"
1022 "vmulesh %0,%1,%2"
1023 [(set_attr "type" "veccomplex")])
1025 (define_insn "altivec_vmuloub"
1026 [(set (match_operand:V8HI 0 "register_operand" "=v")
1027 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1028 (match_operand:V16QI 2 "register_operand" "v")]
1029 UNSPEC_VMULOUB))]
1030 "TARGET_ALTIVEC"
1031 "vmuloub %0,%1,%2"
1032 [(set_attr "type" "veccomplex")])
1034 (define_insn "altivec_vmulosb"
1035 [(set (match_operand:V8HI 0 "register_operand" "=v")
1036 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1037 (match_operand:V16QI 2 "register_operand" "v")]
1038 UNSPEC_VMULOSB))]
1039 "TARGET_ALTIVEC"
1040 "vmulosb %0,%1,%2"
1041 [(set_attr "type" "veccomplex")])
1043 (define_insn "altivec_vmulouh"
1044 [(set (match_operand:V4SI 0 "register_operand" "=v")
1045 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1046 (match_operand:V8HI 2 "register_operand" "v")]
1047 UNSPEC_VMULOUH))]
1048 "TARGET_ALTIVEC"
1049 "vmulouh %0,%1,%2"
1050 [(set_attr "type" "veccomplex")])
1052 (define_insn "altivec_vmulosh"
1053 [(set (match_operand:V4SI 0 "register_operand" "=v")
1054 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1055 (match_operand:V8HI 2 "register_operand" "v")]
1056 UNSPEC_VMULOSH))]
1057 "TARGET_ALTIVEC"
1058 "vmulosh %0,%1,%2"
1059 [(set_attr "type" "veccomplex")])
1062 ;; logical ops
1064 (define_insn "and<mode>3"
1065 [(set (match_operand:VI 0 "register_operand" "=v")
1066 (and:VI (match_operand:VI 1 "register_operand" "v")
1067 (match_operand:VI 2 "register_operand" "v")))]
1068 "TARGET_ALTIVEC"
1069 "vand %0,%1,%2"
1070 [(set_attr "type" "vecsimple")])
1072 (define_insn "ior<mode>3"
1073 [(set (match_operand:VI 0 "register_operand" "=v")
1074 (ior:VI (match_operand:VI 1 "register_operand" "v")
1075 (match_operand:VI 2 "register_operand" "v")))]
1076 "TARGET_ALTIVEC"
1077 "vor %0,%1,%2"
1078 [(set_attr "type" "vecsimple")])
1080 (define_insn "xor<mode>3"
1081 [(set (match_operand:VI 0 "register_operand" "=v")
1082 (xor:VI (match_operand:VI 1 "register_operand" "v")
1083 (match_operand:VI 2 "register_operand" "v")))]
1084 "TARGET_ALTIVEC"
1085 "vxor %0,%1,%2"
1086 [(set_attr "type" "vecsimple")])
1088 (define_insn "xorv4sf3"
1089 [(set (match_operand:V4SF 0 "register_operand" "=v")
1090 (xor:V4SF (match_operand:V4SF 1 "register_operand" "v")
1091 (match_operand:V4SF 2 "register_operand" "v")))]
1092 "TARGET_ALTIVEC"
1093 "vxor %0,%1,%2"
1094 [(set_attr "type" "vecsimple")])
1096 (define_insn "one_cmpl<mode>2"
1097 [(set (match_operand:VI 0 "register_operand" "=v")
1098 (not:VI (match_operand:VI 1 "register_operand" "v")))]
1099 "TARGET_ALTIVEC"
1100 "vnor %0,%1,%1"
1101 [(set_attr "type" "vecsimple")])
1103 (define_insn "altivec_nor<mode>3"
1104 [(set (match_operand:VI 0 "register_operand" "=v")
1105 (not:VI (ior:VI (match_operand:VI 1 "register_operand" "v")
1106 (match_operand:VI 2 "register_operand" "v"))))]
1107 "TARGET_ALTIVEC"
1108 "vnor %0,%1,%2"
1109 [(set_attr "type" "vecsimple")])
1111 (define_insn "andc<mode>3"
1112 [(set (match_operand:VI 0 "register_operand" "=v")
1113 (and:VI (not:VI (match_operand:VI 2 "register_operand" "v"))
1114 (match_operand:VI 1 "register_operand" "v")))]
1115 "TARGET_ALTIVEC"
1116 "vandc %0,%1,%2"
1117 [(set_attr "type" "vecsimple")])
1119 (define_insn "*andc3_v4sf"
1120 [(set (match_operand:V4SF 0 "register_operand" "=v")
1121 (and:V4SF (not:V4SF (match_operand:V4SF 2 "register_operand" "v"))
1122 (match_operand:V4SF 1 "register_operand" "v")))]
1123 "TARGET_ALTIVEC"
1124 "vandc %0,%1,%2"
1125 [(set_attr "type" "vecsimple")])
1127 (define_insn "altivec_vpkuhum"
1128 [(set (match_operand:V16QI 0 "register_operand" "=v")
1129 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1130 (match_operand:V8HI 2 "register_operand" "v")]
1131 UNSPEC_VPKUHUM))]
1132 "TARGET_ALTIVEC"
1133 "vpkuhum %0,%1,%2"
1134 [(set_attr "type" "vecperm")])
1136 (define_insn "altivec_vpkuwum"
1137 [(set (match_operand:V8HI 0 "register_operand" "=v")
1138 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1139 (match_operand:V4SI 2 "register_operand" "v")]
1140 UNSPEC_VPKUWUM))]
1141 "TARGET_ALTIVEC"
1142 "vpkuwum %0,%1,%2"
1143 [(set_attr "type" "vecperm")])
1145 (define_insn "altivec_vpkpx"
1146 [(set (match_operand:V8HI 0 "register_operand" "=v")
1147 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1148 (match_operand:V4SI 2 "register_operand" "v")]
1149 UNSPEC_VPKPX))]
1150 "TARGET_ALTIVEC"
1151 "vpkpx %0,%1,%2"
1152 [(set_attr "type" "vecperm")])
1154 (define_insn "altivec_vpkshss"
1155 [(set (match_operand:V16QI 0 "register_operand" "=v")
1156 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1157 (match_operand:V8HI 2 "register_operand" "v")]
1158 UNSPEC_VPKSHSS))
1159 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1160 "TARGET_ALTIVEC"
1161 "vpkshss %0,%1,%2"
1162 [(set_attr "type" "vecperm")])
1164 (define_insn "altivec_vpkswss"
1165 [(set (match_operand:V8HI 0 "register_operand" "=v")
1166 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1167 (match_operand:V4SI 2 "register_operand" "v")]
1168 UNSPEC_VPKSWSS))
1169 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1170 "TARGET_ALTIVEC"
1171 "vpkswss %0,%1,%2"
1172 [(set_attr "type" "vecperm")])
1174 (define_insn "altivec_vpkuhus"
1175 [(set (match_operand:V16QI 0 "register_operand" "=v")
1176 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1177 (match_operand:V8HI 2 "register_operand" "v")]
1178 UNSPEC_VPKUHUS))
1179 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1180 "TARGET_ALTIVEC"
1181 "vpkuhus %0,%1,%2"
1182 [(set_attr "type" "vecperm")])
1184 (define_insn "altivec_vpkshus"
1185 [(set (match_operand:V16QI 0 "register_operand" "=v")
1186 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1187 (match_operand:V8HI 2 "register_operand" "v")]
1188 UNSPEC_VPKSHUS))
1189 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1190 "TARGET_ALTIVEC"
1191 "vpkshus %0,%1,%2"
1192 [(set_attr "type" "vecperm")])
1194 (define_insn "altivec_vpkuwus"
1195 [(set (match_operand:V8HI 0 "register_operand" "=v")
1196 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1197 (match_operand:V4SI 2 "register_operand" "v")]
1198 UNSPEC_VPKUWUS))
1199 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1200 "TARGET_ALTIVEC"
1201 "vpkuwus %0,%1,%2"
1202 [(set_attr "type" "vecperm")])
1204 (define_insn "altivec_vpkswus"
1205 [(set (match_operand:V8HI 0 "register_operand" "=v")
1206 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1207 (match_operand:V4SI 2 "register_operand" "v")]
1208 UNSPEC_VPKSWUS))
1209 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1210 "TARGET_ALTIVEC"
1211 "vpkswus %0,%1,%2"
1212 [(set_attr "type" "vecperm")])
1214 (define_insn "altivec_vrl<VI_char>"
1215 [(set (match_operand:VI 0 "register_operand" "=v")
1216 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1217 (match_operand:VI 2 "register_operand" "v")]
1218 UNSPEC_VRL))]
1219 "TARGET_ALTIVEC"
1220 "vrl<VI_char> %0,%1,%2"
1221 [(set_attr "type" "vecsimple")])
1223 (define_insn "altivec_vsl"
1224 [(set (match_operand:V4SI 0 "register_operand" "=v")
1225 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1226 (match_operand:V4SI 2 "register_operand" "v")]
1227 UNSPEC_VSLV4SI))]
1228 "TARGET_ALTIVEC"
1229 "vsl %0,%1,%2"
1230 [(set_attr "type" "vecperm")])
1232 (define_insn "altivec_vslo"
1233 [(set (match_operand:V4SI 0 "register_operand" "=v")
1234 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1235 (match_operand:V4SI 2 "register_operand" "v")]
1236 UNSPEC_VSLO))]
1237 "TARGET_ALTIVEC"
1238 "vslo %0,%1,%2"
1239 [(set_attr "type" "vecperm")])
1241 (define_insn "vashl<mode>3"
1242 [(set (match_operand:VI 0 "register_operand" "=v")
1243 (ashift:VI (match_operand:VI 1 "register_operand" "v")
1244 (match_operand:VI 2 "register_operand" "v") ))]
1245 "TARGET_ALTIVEC"
1246 "vsl<VI_char> %0,%1,%2"
1247 [(set_attr "type" "vecsimple")])
1249 (define_insn "vlshr<mode>3"
1250 [(set (match_operand:VI 0 "register_operand" "=v")
1251 (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
1252 (match_operand:VI 2 "register_operand" "v") ))]
1253 "TARGET_ALTIVEC"
1254 "vsr<VI_char> %0,%1,%2"
1255 [(set_attr "type" "vecsimple")])
1257 (define_insn "vashr<mode>3"
1258 [(set (match_operand:VI 0 "register_operand" "=v")
1259 (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
1260 (match_operand:VI 2 "register_operand" "v") ))]
1261 "TARGET_ALTIVEC"
1262 "vsra<VI_char> %0,%1,%2"
1263 [(set_attr "type" "vecsimple")])
1265 (define_insn "altivec_vsr"
1266 [(set (match_operand:V4SI 0 "register_operand" "=v")
1267 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1268 (match_operand:V4SI 2 "register_operand" "v")]
1269 UNSPEC_VSR))]
1270 "TARGET_ALTIVEC"
1271 "vsr %0,%1,%2"
1272 [(set_attr "type" "vecperm")])
1274 (define_insn "altivec_vsro"
1275 [(set (match_operand:V4SI 0 "register_operand" "=v")
1276 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1277 (match_operand:V4SI 2 "register_operand" "v")]
1278 UNSPEC_VSRO))]
1279 "TARGET_ALTIVEC"
1280 "vsro %0,%1,%2"
1281 [(set_attr "type" "vecperm")])
1283 (define_insn "altivec_vsum4ubs"
1284 [(set (match_operand:V4SI 0 "register_operand" "=v")
1285 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1286 (match_operand:V4SI 2 "register_operand" "v")]
1287 UNSPEC_VSUM4UBS))
1288 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1289 "TARGET_ALTIVEC"
1290 "vsum4ubs %0,%1,%2"
1291 [(set_attr "type" "veccomplex")])
1293 (define_insn "altivec_vsum4s<VI_char>s"
1294 [(set (match_operand:V4SI 0 "register_operand" "=v")
1295 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1296 (match_operand:V4SI 2 "register_operand" "v")]
1297 UNSPEC_VSUM4S))
1298 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1299 "TARGET_ALTIVEC"
1300 "vsum4s<VI_char>s %0,%1,%2"
1301 [(set_attr "type" "veccomplex")])
1303 (define_insn "altivec_vsum2sws"
1304 [(set (match_operand:V4SI 0 "register_operand" "=v")
1305 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1306 (match_operand:V4SI 2 "register_operand" "v")]
1307 UNSPEC_VSUM2SWS))
1308 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1309 "TARGET_ALTIVEC"
1310 "vsum2sws %0,%1,%2"
1311 [(set_attr "type" "veccomplex")])
1313 (define_insn "altivec_vsumsws"
1314 [(set (match_operand:V4SI 0 "register_operand" "=v")
1315 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1316 (match_operand:V4SI 2 "register_operand" "v")]
1317 UNSPEC_VSUMSWS))
1318 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1319 "TARGET_ALTIVEC"
1320 "vsumsws %0,%1,%2"
1321 [(set_attr "type" "veccomplex")])
1323 (define_insn "altivec_vspltb"
1324 [(set (match_operand:V16QI 0 "register_operand" "=v")
1325 (vec_duplicate:V16QI
1326 (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
1327 (parallel
1328 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1329 "TARGET_ALTIVEC"
1330 "vspltb %0,%1,%2"
1331 [(set_attr "type" "vecperm")])
1333 (define_insn "altivec_vsplth"
1334 [(set (match_operand:V8HI 0 "register_operand" "=v")
1335 (vec_duplicate:V8HI
1336 (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
1337 (parallel
1338 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1339 "TARGET_ALTIVEC"
1340 "vsplth %0,%1,%2"
1341 [(set_attr "type" "vecperm")])
1343 (define_insn "altivec_vspltw"
1344 [(set (match_operand:V4SI 0 "register_operand" "=v")
1345 (vec_duplicate:V4SI
1346 (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
1347 (parallel
1348 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1349 "TARGET_ALTIVEC"
1350 "vspltw %0,%1,%2"
1351 [(set_attr "type" "vecperm")])
1353 (define_insn "*altivec_vspltsf"
1354 [(set (match_operand:V4SF 0 "register_operand" "=v")
1355 (vec_duplicate:V4SF
1356 (vec_select:SF (match_operand:V4SF 1 "register_operand" "v")
1357 (parallel
1358 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1359 "TARGET_ALTIVEC"
1360 "vspltw %0,%1,%2"
1361 [(set_attr "type" "vecperm")])
1363 (define_insn "altivec_vspltis<VI_char>"
1364 [(set (match_operand:VI 0 "register_operand" "=v")
1365 (vec_duplicate:VI
1366 (match_operand:QI 1 "s5bit_cint_operand" "i")))]
1367 "TARGET_ALTIVEC"
1368 "vspltis<VI_char> %0,%1"
1369 [(set_attr "type" "vecperm")])
1371 (define_insn "ftruncv4sf2"
1372 [(set (match_operand:V4SF 0 "register_operand" "=v")
1373 (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1374 "TARGET_ALTIVEC"
1375 "vrfiz %0,%1"
1376 [(set_attr "type" "vecfloat")])
1378 (define_insn "altivec_vperm_<mode>"
1379 [(set (match_operand:V 0 "register_operand" "=v")
1380 (unspec:V [(match_operand:V 1 "register_operand" "v")
1381 (match_operand:V 2 "register_operand" "v")
1382 (match_operand:V16QI 3 "register_operand" "v")]
1383 UNSPEC_VPERM))]
1384 "TARGET_ALTIVEC"
1385 "vperm %0,%1,%2,%3"
1386 [(set_attr "type" "vecperm")])
1388 (define_insn "altivec_vrfip"
1389 [(set (match_operand:V4SF 0 "register_operand" "=v")
1390 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1391 UNSPEC_VRFIP))]
1392 "TARGET_ALTIVEC"
1393 "vrfip %0,%1"
1394 [(set_attr "type" "vecfloat")])
1396 (define_insn "altivec_vrfin"
1397 [(set (match_operand:V4SF 0 "register_operand" "=v")
1398 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1399 UNSPEC_VRFIN))]
1400 "TARGET_ALTIVEC"
1401 "vrfin %0,%1"
1402 [(set_attr "type" "vecfloat")])
1404 (define_insn "altivec_vrfim"
1405 [(set (match_operand:V4SF 0 "register_operand" "=v")
1406 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1407 UNSPEC_VRFIM))]
1408 "TARGET_ALTIVEC"
1409 "vrfim %0,%1"
1410 [(set_attr "type" "vecfloat")])
1412 (define_insn "altivec_vcfux"
1413 [(set (match_operand:V4SF 0 "register_operand" "=v")
1414 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1415 (match_operand:QI 2 "immediate_operand" "i")]
1416 UNSPEC_VCFUX))]
1417 "TARGET_ALTIVEC"
1418 "vcfux %0,%1,%2"
1419 [(set_attr "type" "vecfloat")])
1421 (define_insn "altivec_vcfsx"
1422 [(set (match_operand:V4SF 0 "register_operand" "=v")
1423 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1424 (match_operand:QI 2 "immediate_operand" "i")]
1425 UNSPEC_VCFSX))]
1426 "TARGET_ALTIVEC"
1427 "vcfsx %0,%1,%2"
1428 [(set_attr "type" "vecfloat")])
1430 (define_insn "altivec_vctuxs"
1431 [(set (match_operand:V4SI 0 "register_operand" "=v")
1432 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1433 (match_operand:QI 2 "immediate_operand" "i")]
1434 UNSPEC_VCTUXS))
1435 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1436 "TARGET_ALTIVEC"
1437 "vctuxs %0,%1,%2"
1438 [(set_attr "type" "vecfloat")])
1440 (define_insn "altivec_vctsxs"
1441 [(set (match_operand:V4SI 0 "register_operand" "=v")
1442 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1443 (match_operand:QI 2 "immediate_operand" "i")]
1444 UNSPEC_VCTSXS))
1445 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1446 "TARGET_ALTIVEC"
1447 "vctsxs %0,%1,%2"
1448 [(set_attr "type" "vecfloat")])
1450 (define_insn "altivec_vlogefp"
1451 [(set (match_operand:V4SF 0 "register_operand" "=v")
1452 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1453 UNSPEC_VLOGEFP))]
1454 "TARGET_ALTIVEC"
1455 "vlogefp %0,%1"
1456 [(set_attr "type" "vecfloat")])
1458 (define_insn "altivec_vexptefp"
1459 [(set (match_operand:V4SF 0 "register_operand" "=v")
1460 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1461 UNSPEC_VEXPTEFP))]
1462 "TARGET_ALTIVEC"
1463 "vexptefp %0,%1"
1464 [(set_attr "type" "vecfloat")])
1466 (define_insn "altivec_vrsqrtefp"
1467 [(set (match_operand:V4SF 0 "register_operand" "=v")
1468 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1469 UNSPEC_VRSQRTEFP))]
1470 "TARGET_ALTIVEC"
1471 "vrsqrtefp %0,%1"
1472 [(set_attr "type" "vecfloat")])
1474 (define_insn "altivec_vrefp"
1475 [(set (match_operand:V4SF 0 "register_operand" "=v")
1476 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1477 UNSPEC_VREFP))]
1478 "TARGET_ALTIVEC"
1479 "vrefp %0,%1"
1480 [(set_attr "type" "vecfloat")])
1482 (define_expand "vcondv4si"
1483 [(set (match_operand:V4SI 0 "register_operand" "=v")
1484 (if_then_else:V4SI
1485 (match_operator 3 "comparison_operator"
1486 [(match_operand:V4SI 4 "register_operand" "v")
1487 (match_operand:V4SI 5 "register_operand" "v")])
1488 (match_operand:V4SI 1 "register_operand" "v")
1489 (match_operand:V4SI 2 "register_operand" "v")))]
1490 "TARGET_ALTIVEC"
1491 "
1492 {
1493 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1494 operands[3], operands[4], operands[5]))
1495 DONE;
1496 else
1497 FAIL;
1498 }
1499 ")
1501 (define_expand "vconduv4si"
1502 [(set (match_operand:V4SI 0 "register_operand" "=v")
1503 (if_then_else:V4SI
1504 (match_operator 3 "comparison_operator"
1505 [(match_operand:V4SI 4 "register_operand" "v")
1506 (match_operand:V4SI 5 "register_operand" "v")])
1507 (match_operand:V4SI 1 "register_operand" "v")
1508 (match_operand:V4SI 2 "register_operand" "v")))]
1509 "TARGET_ALTIVEC"
1510 "
1511 {
1512 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1513 operands[3], operands[4], operands[5]))
1514 DONE;
1515 else
1516 FAIL;
1517 }
1518 ")
1520 (define_expand "vcondv4sf"
1521 [(set (match_operand:V4SF 0 "register_operand" "=v")
1522 (if_then_else:V4SF
1523 (match_operator 3 "comparison_operator"
1524 [(match_operand:V4SF 4 "register_operand" "v")
1525 (match_operand:V4SF 5 "register_operand" "v")])
1526 (match_operand:V4SF 1 "register_operand" "v")
1527 (match_operand:V4SF 2 "register_operand" "v")))]
1528 "TARGET_ALTIVEC"
1529 "
1530 {
1531 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1532 operands[3], operands[4], operands[5]))
1533 DONE;
1534 else
1535 FAIL;
1536 }
1537 ")
1539 (define_expand "vcondv8hi"
1540 [(set (match_operand:V8HI 0 "register_operand" "=v")
1541 (if_then_else:V8HI
1542 (match_operator 3 "comparison_operator"
1543 [(match_operand:V8HI 4 "register_operand" "v")
1544 (match_operand:V8HI 5 "register_operand" "v")])
1545 (match_operand:V8HI 1 "register_operand" "v")
1546 (match_operand:V8HI 2 "register_operand" "v")))]
1547 "TARGET_ALTIVEC"
1548 "
1549 {
1550 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1551 operands[3], operands[4], operands[5]))
1552 DONE;
1553 else
1554 FAIL;
1555 }
1556 ")
1558 (define_expand "vconduv8hi"
1559 [(set (match_operand:V8HI 0 "register_operand" "=v")
1560 (if_then_else:V8HI
1561 (match_operator 3 "comparison_operator"
1562 [(match_operand:V8HI 4 "register_operand" "v")
1563 (match_operand:V8HI 5 "register_operand" "v")])
1564 (match_operand:V8HI 1 "register_operand" "v")
1565 (match_operand:V8HI 2 "register_operand" "v")))]
1566 "TARGET_ALTIVEC"
1567 "
1568 {
1569 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1570 operands[3], operands[4], operands[5]))
1571 DONE;
1572 else
1573 FAIL;
1574 }
1575 ")
1577 (define_expand "vcondv16qi"
1578 [(set (match_operand:V16QI 0 "register_operand" "=v")
1579 (if_then_else:V16QI
1580 (match_operator 3 "comparison_operator"
1581 [(match_operand:V16QI 4 "register_operand" "v")
1582 (match_operand:V16QI 5 "register_operand" "v")])
1583 (match_operand:V16QI 1 "register_operand" "v")
1584 (match_operand:V16QI 2 "register_operand" "v")))]
1585 "TARGET_ALTIVEC"
1586 "
1587 {
1588 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1589 operands[3], operands[4], operands[5]))
1590 DONE;
1591 else
1592 FAIL;
1593 }
1594 ")
1596 (define_expand "vconduv16qi"
1597 [(set (match_operand:V16QI 0 "register_operand" "=v")
1598 (if_then_else:V16QI
1599 (match_operator 3 "comparison_operator"
1600 [(match_operand:V16QI 4 "register_operand" "v")
1601 (match_operand:V16QI 5 "register_operand" "v")])
1602 (match_operand:V16QI 1 "register_operand" "v")
1603 (match_operand:V16QI 2 "register_operand" "v")))]
1604 "TARGET_ALTIVEC"
1605 "
1606 {
1607 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1608 operands[3], operands[4], operands[5]))
1609 DONE;
1610 else
1611 FAIL;
1612 }
1613 ")
1616 (define_insn "altivec_vsel_v4si"
1617 [(set (match_operand:V4SI 0 "register_operand" "=v")
1618 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1619 (match_operand:V4SI 2 "register_operand" "v")
1620 (match_operand:V4SI 3 "register_operand" "v")]
1621 UNSPEC_VSEL4SI))]
1622 "TARGET_ALTIVEC"
1623 "vsel %0,%1,%2,%3"
1624 [(set_attr "type" "vecperm")])
1626 (define_insn "altivec_vsel_v4sf"
1627 [(set (match_operand:V4SF 0 "register_operand" "=v")
1628 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1629 (match_operand:V4SF 2 "register_operand" "v")
1630 (match_operand:V4SI 3 "register_operand" "v")]
1631 UNSPEC_VSEL4SF))]
1632 "TARGET_ALTIVEC"
1633 "vsel %0,%1,%2,%3"
1634 [(set_attr "type" "vecperm")])
1636 (define_insn "altivec_vsel_v8hi"
1637 [(set (match_operand:V8HI 0 "register_operand" "=v")
1638 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1639 (match_operand:V8HI 2 "register_operand" "v")
1640 (match_operand:V8HI 3 "register_operand" "v")]
1641 UNSPEC_VSEL8HI))]
1642 "TARGET_ALTIVEC"
1643 "vsel %0,%1,%2,%3"
1644 [(set_attr "type" "vecperm")])
1646 (define_insn "altivec_vsel_v16qi"
1647 [(set (match_operand:V16QI 0 "register_operand" "=v")
1648 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1649 (match_operand:V16QI 2 "register_operand" "v")
1650 (match_operand:V16QI 3 "register_operand" "v")]
1651 UNSPEC_VSEL16QI))]
1652 "TARGET_ALTIVEC"
1653 "vsel %0,%1,%2,%3"
1654 [(set_attr "type" "vecperm")])
1656 (define_insn "altivec_vsldoi_<mode>"
1657 [(set (match_operand:V 0 "register_operand" "=v")
1658 (unspec:V [(match_operand:V 1 "register_operand" "v")
1659 (match_operand:V 2 "register_operand" "v")
1660 (match_operand:QI 3 "immediate_operand" "i")]
1661 UNSPEC_VLSDOI))]
1662 "TARGET_ALTIVEC"
1663 "vsldoi %0,%1,%2,%3"
1664 [(set_attr "type" "vecperm")])
1666 (define_insn "altivec_vupkhsb"
1667 [(set (match_operand:V8HI 0 "register_operand" "=v")
1668 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1669 UNSPEC_VUPKHSB))]
1670 "TARGET_ALTIVEC"
1671 "vupkhsb %0,%1"
1672 [(set_attr "type" "vecperm")])
1674 (define_insn "altivec_vupkhpx"
1675 [(set (match_operand:V4SI 0 "register_operand" "=v")
1676 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1677 UNSPEC_VUPKHPX))]
1678 "TARGET_ALTIVEC"
1679 "vupkhpx %0,%1"
1680 [(set_attr "type" "vecperm")])
1682 (define_insn "altivec_vupkhsh"
1683 [(set (match_operand:V4SI 0 "register_operand" "=v")
1684 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1685 UNSPEC_VUPKHSH))]
1686 "TARGET_ALTIVEC"
1687 "vupkhsh %0,%1"
1688 [(set_attr "type" "vecperm")])
1690 (define_insn "altivec_vupklsb"
1691 [(set (match_operand:V8HI 0 "register_operand" "=v")
1692 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1693 UNSPEC_VUPKLSB))]
1694 "TARGET_ALTIVEC"
1695 "vupklsb %0,%1"
1696 [(set_attr "type" "vecperm")])
1698 (define_insn "altivec_vupklpx"
1699 [(set (match_operand:V4SI 0 "register_operand" "=v")
1700 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1701 UNSPEC_VUPKLPX))]
1702 "TARGET_ALTIVEC"
1703 "vupklpx %0,%1"
1704 [(set_attr "type" "vecperm")])
1706 (define_insn "altivec_vupklsh"
1707 [(set (match_operand:V4SI 0 "register_operand" "=v")
1708 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1709 UNSPEC_VUPKLSH))]
1710 "TARGET_ALTIVEC"
1711 "vupklsh %0,%1"
1712 [(set_attr "type" "vecperm")])
1714 ;; AltiVec predicates.
1716 (define_expand "cr6_test_for_zero"
1717 [(set (match_operand:SI 0 "register_operand" "=r")
1718 (eq:SI (reg:CC 74)
1719 (const_int 0)))]
1720 "TARGET_ALTIVEC"
1721 "")
1723 (define_expand "cr6_test_for_zero_reverse"
1724 [(set (match_operand:SI 0 "register_operand" "=r")
1725 (eq:SI (reg:CC 74)
1726 (const_int 0)))
1727 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1728 "TARGET_ALTIVEC"
1729 "")
1731 (define_expand "cr6_test_for_lt"
1732 [(set (match_operand:SI 0 "register_operand" "=r")
1733 (lt:SI (reg:CC 74)
1734 (const_int 0)))]
1735 "TARGET_ALTIVEC"
1736 "")
1738 (define_expand "cr6_test_for_lt_reverse"
1739 [(set (match_operand:SI 0 "register_operand" "=r")
1740 (lt:SI (reg:CC 74)
1741 (const_int 0)))
1742 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1743 "TARGET_ALTIVEC"
1744 "")
1746 ;; We can get away with generating the opcode on the fly (%3 below)
1747 ;; because all the predicates have the same scheduling parameters.
1749 (define_insn "altivec_predicate_<mode>"
1750 [(set (reg:CC 74)
1751 (unspec:CC [(match_operand:V 1 "register_operand" "v")
1752 (match_operand:V 2 "register_operand" "v")
1753 (match_operand 3 "any_operand" "")] UNSPEC_PREDICATE))
1754 (clobber (match_scratch:V 0 "=v"))]
1755 "TARGET_ALTIVEC"
1756 "%3 %0,%1,%2"
1757 [(set_attr "type" "veccmp")])
1759 (define_insn "altivec_mtvscr"
1760 [(set (reg:SI 110)
1761 (unspec_volatile:SI
1762 [(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
1763 "TARGET_ALTIVEC"
1764 "mtvscr %0"
1765 [(set_attr "type" "vecsimple")])
1767 (define_insn "altivec_mfvscr"
1768 [(set (match_operand:V8HI 0 "register_operand" "=v")
1769 (unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
1770 "TARGET_ALTIVEC"
1771 "mfvscr %0"
1772 [(set_attr "type" "vecsimple")])
1774 (define_insn "altivec_dssall"
1775 [(unspec_volatile [(const_int 0)] UNSPECV_DSSALL)]
1776 "TARGET_ALTIVEC"
1777 "dssall"
1778 [(set_attr "type" "vecsimple")])
1780 (define_insn "altivec_dss"
1781 [(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")]
1782 UNSPECV_DSS)]
1783 "TARGET_ALTIVEC"
1784 "dss %0"
1785 [(set_attr "type" "vecsimple")])
1787 (define_insn "altivec_dst"
1788 [(unspec [(match_operand 0 "register_operand" "b")
1789 (match_operand:SI 1 "register_operand" "r")
1790 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DST)]
1791 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1792 "dst %0,%1,%2"
1793 [(set_attr "type" "vecsimple")])
1795 (define_insn "altivec_dstt"
1796 [(unspec [(match_operand 0 "register_operand" "b")
1797 (match_operand:SI 1 "register_operand" "r")
1798 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTT)]
1799 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1800 "dstt %0,%1,%2"
1801 [(set_attr "type" "vecsimple")])
1803 (define_insn "altivec_dstst"
1804 [(unspec [(match_operand 0 "register_operand" "b")
1805 (match_operand:SI 1 "register_operand" "r")
1806 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTST)]
1807 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1808 "dstst %0,%1,%2"
1809 [(set_attr "type" "vecsimple")])
1811 (define_insn "altivec_dststt"
1812 [(unspec [(match_operand 0 "register_operand" "b")
1813 (match_operand:SI 1 "register_operand" "r")
1814 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTSTT)]
1815 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1816 "dststt %0,%1,%2"
1817 [(set_attr "type" "vecsimple")])
1819 (define_insn "altivec_lvsl"
1820 [(set (match_operand:V16QI 0 "register_operand" "=v")
1821 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSL))]
1822 "TARGET_ALTIVEC"
1823 "lvsl %0,%y1"
1824 [(set_attr "type" "vecload")])
1826 (define_insn "altivec_lvsr"
1827 [(set (match_operand:V16QI 0 "register_operand" "=v")
1828 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSR))]
1829 "TARGET_ALTIVEC"
1830 "lvsr %0,%y1"
1831 [(set_attr "type" "vecload")])
1833 (define_expand "build_vector_mask_for_load"
1834 [(set (match_operand:V16QI 0 "register_operand" "")
1835 (unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
1836 "TARGET_ALTIVEC"
1837 "
1838 {
1839 rtx addr;
1840 rtx temp;
1842 gcc_assert (GET_CODE (operands[1]) == MEM);
1844 addr = XEXP (operands[1], 0);
1845 temp = gen_reg_rtx (GET_MODE (addr));
1846 emit_insn (gen_rtx_SET (VOIDmode, temp,
1847 gen_rtx_NEG (GET_MODE (addr), addr)));
1848 emit_insn (gen_altivec_lvsr (operands[0],
1849 replace_equiv_address (operands[1], temp)));
1850 DONE;
1851 }")
1853 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1854 ;; identical rtl but different instructions-- and gcc gets confused.
1856 (define_insn "altivec_lve<VI_char>x"
1857 [(parallel
1858 [(set (match_operand:VI 0 "register_operand" "=v")
1859 (match_operand:VI 1 "memory_operand" "Z"))
1860 (unspec [(const_int 0)] UNSPEC_LVE)])]
1861 "TARGET_ALTIVEC"
1862 "lve<VI_char>x %0,%y1"
1863 [(set_attr "type" "vecload")])
1865 (define_insn "*altivec_lvesfx"
1866 [(parallel
1867 [(set (match_operand:V4SF 0 "register_operand" "=v")
1868 (match_operand:V4SF 1 "memory_operand" "Z"))
1869 (unspec [(const_int 0)] UNSPEC_LVE)])]
1870 "TARGET_ALTIVEC"
1871 "lvewx %0,%y1"
1872 [(set_attr "type" "vecload")])
1874 (define_insn "altivec_lvxl"
1875 [(parallel
1876 [(set (match_operand:V4SI 0 "register_operand" "=v")
1877 (match_operand:V4SI 1 "memory_operand" "Z"))
1878 (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
1879 "TARGET_ALTIVEC"
1880 "lvxl %0,%y1"
1881 [(set_attr "type" "vecload")])
1883 (define_insn "altivec_lvx"
1884 [(set (match_operand:V4SI 0 "register_operand" "=v")
1885 (match_operand:V4SI 1 "memory_operand" "Z"))]
1886 "TARGET_ALTIVEC"
1887 "lvx %0,%y1"
1888 [(set_attr "type" "vecload")])
1890 (define_insn "altivec_stvx"
1891 [(parallel
1892 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1893 (match_operand:V4SI 1 "register_operand" "v"))
1894 (unspec [(const_int 0)] UNSPEC_STVX)])]
1895 "TARGET_ALTIVEC"
1896 "stvx %1,%y0"
1897 [(set_attr "type" "vecstore")])
1899 (define_insn "altivec_stvxl"
1900 [(parallel
1901 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1902 (match_operand:V4SI 1 "register_operand" "v"))
1903 (unspec [(const_int 0)] UNSPEC_STVXL)])]
1904 "TARGET_ALTIVEC"
1905 "stvxl %1,%y0"
1906 [(set_attr "type" "vecstore")])
1908 (define_insn "altivec_stve<VI_char>x"
1909 [(parallel
1910 [(set (match_operand:VI 0 "memory_operand" "=Z")
1911 (match_operand:VI 1 "register_operand" "v"))
1912 (unspec [(const_int 0)] UNSPEC_STVE)])]
1913 "TARGET_ALTIVEC"
1914 "stve<VI_char>x %1,%y0"
1915 [(set_attr "type" "vecstore")])
1917 (define_insn "*altivec_stvesfx"
1918 [(parallel
1919 [(set (match_operand:V4SF 0 "memory_operand" "=Z")
1920 (match_operand:V4SF 1 "register_operand" "v"))
1921 (unspec [(const_int 0)] UNSPEC_STVE)])]
1922 "TARGET_ALTIVEC"
1923 "stvewx %1,%y0"
1924 [(set_attr "type" "vecstore")])
1926 (define_expand "vec_init<mode>"
1927 [(match_operand:V 0 "register_operand" "")
1928 (match_operand 1 "" "")]
1929 "TARGET_ALTIVEC"
1930 {
1931 rs6000_expand_vector_init (operands[0], operands[1]);
1932 DONE;
1933 })
1935 (define_expand "vec_setv4si"
1936 [(match_operand:V4SI 0 "register_operand" "")
1937 (match_operand:SI 1 "register_operand" "")
1938 (match_operand 2 "const_int_operand" "")]
1939 "TARGET_ALTIVEC"
1940 {
1941 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1942 DONE;
1943 })
1945 (define_expand "vec_setv8hi"
1946 [(match_operand:V8HI 0 "register_operand" "")
1947 (match_operand:HI 1 "register_operand" "")
1948 (match_operand 2 "const_int_operand" "")]
1949 "TARGET_ALTIVEC"
1950 {
1951 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1952 DONE;
1953 })
1955 (define_expand "vec_setv16qi"
1956 [(match_operand:V16QI 0 "register_operand" "")
1957 (match_operand:QI 1 "register_operand" "")
1958 (match_operand 2 "const_int_operand" "")]
1959 "TARGET_ALTIVEC"
1960 {
1961 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1962 DONE;
1963 })
1965 (define_expand "vec_setv4sf"
1966 [(match_operand:V4SF 0 "register_operand" "")
1967 (match_operand:SF 1 "register_operand" "")
1968 (match_operand 2 "const_int_operand" "")]
1969 "TARGET_ALTIVEC"
1970 {
1971 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1972 DONE;
1973 })
1975 (define_expand "vec_extractv4si"
1976 [(match_operand:SI 0 "register_operand" "")
1977 (match_operand:V4SI 1 "register_operand" "")
1978 (match_operand 2 "const_int_operand" "")]
1979 "TARGET_ALTIVEC"
1980 {
1981 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
1982 DONE;
1983 })
1985 (define_expand "vec_extractv8hi"
1986 [(match_operand:HI 0 "register_operand" "")
1987 (match_operand:V8HI 1 "register_operand" "")
1988 (match_operand 2 "const_int_operand" "")]
1989 "TARGET_ALTIVEC"
1990 {
1991 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
1992 DONE;
1993 })
1995 (define_expand "vec_extractv16qi"
1996 [(match_operand:QI 0 "register_operand" "")
1997 (match_operand:V16QI 1 "register_operand" "")
1998 (match_operand 2 "const_int_operand" "")]
1999 "TARGET_ALTIVEC"
2000 {
2001 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
2002 DONE;
2003 })
2005 (define_expand "vec_extractv4sf"
2006 [(match_operand:SF 0 "register_operand" "")
2007 (match_operand:V4SF 1 "register_operand" "")
2008 (match_operand 2 "const_int_operand" "")]
2009 "TARGET_ALTIVEC"
2010 {
2011 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
2012 DONE;
2013 })
2015 ;; Generate
2016 ;; vspltis? SCRATCH0,0
2017 ;; vsubu?m SCRATCH2,SCRATCH1,%1
2018 ;; vmaxs? %0,%1,SCRATCH2"
2019 (define_expand "abs<mode>2"
2020 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
2021 (set (match_dup 3)
2022 (minus:VI (match_dup 2)
2023 (match_operand:VI 1 "register_operand" "v")))
2024 (set (match_operand:VI 0 "register_operand" "=v")
2025 (smax:VI (match_dup 1) (match_dup 3)))]
2026 "TARGET_ALTIVEC"
2027 {
2028 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
2029 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
2030 })
2032 ;; Generate
2033 ;; vspltisw SCRATCH1,-1
2034 ;; vslw SCRATCH2,SCRATCH1,SCRATCH1
2035 ;; vandc %0,%1,SCRATCH2
2036 (define_expand "absv4sf2"
2037 [(set (match_dup 2)
2038 (vec_duplicate:V4SI (const_int -1)))
2039 (set (match_dup 3)
2040 (ashift:V4SI (match_dup 2) (match_dup 2)))
2041 (set (match_operand:V4SF 0 "register_operand" "=v")
2042 (and:V4SF (not:V4SF (subreg:V4SF (match_dup 3) 0))
2043 (match_operand:V4SF 1 "register_operand" "v")))]
2044 "TARGET_ALTIVEC"
2045 {
2046 operands[2] = gen_reg_rtx (V4SImode);
2047 operands[3] = gen_reg_rtx (V4SImode);
2048 })
2050 ;; Generate
2051 ;; vspltis? SCRATCH0,0
2052 ;; vsubs?s SCRATCH2,SCRATCH1,%1
2053 ;; vmaxs? %0,%1,SCRATCH2"
2054 (define_expand "altivec_abss_<mode>"
2055 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
2056 (parallel [(set (match_dup 3)
2057 (unspec:VI [(match_dup 2)
2058 (match_operand:VI 1 "register_operand" "v")]
2059 UNSPEC_VSUBS))
2060 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
2061 (set (match_operand:VI 0 "register_operand" "=v")
2062 (smax:VI (match_dup 1) (match_dup 3)))]
2063 "TARGET_ALTIVEC"
2064 {
2065 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
2066 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
2067 })
2069 ;; Vector shift left in bits. Currently supported ony for shift
2070 ;; amounts that can be expressed as byte shifts (divisible by 8).
2071 ;; General shift amounts can be supported using vslo + vsl. We're
2072 ;; not expecting to see these yet (the vectorizer currently
2073 ;; generates only shifts divisible by byte_size).
2074 (define_expand "vec_shl_<mode>"
2075 [(set (match_operand:V 0 "register_operand" "=v")
2076 (unspec:V [(match_operand:V 1 "register_operand" "v")
2077 (match_operand:QI 2 "reg_or_short_operand" "")]
2078 UNSPEC_VECSH))]
2079 "TARGET_ALTIVEC"
2080 "
2081 {
2082 rtx bitshift = operands[2];
2083 rtx byteshift = gen_reg_rtx (QImode);
2084 HOST_WIDE_INT bitshift_val;
2085 HOST_WIDE_INT byteshift_val;
2087 if (! CONSTANT_P (bitshift))
2088 FAIL;
2089 bitshift_val = INTVAL (bitshift);
2090 if (bitshift_val & 0x7)
2091 FAIL;
2092 byteshift_val = bitshift_val >> 3;
2093 byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
2094 emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
2095 byteshift));
2096 DONE;
2097 }")
2099 ;; Vector shift left in bits. Currently supported ony for shift
2100 ;; amounts that can be expressed as byte shifts (divisible by 8).
2101 ;; General shift amounts can be supported using vsro + vsr. We're
2102 ;; not expecting to see these yet (the vectorizer currently
2103 ;; generates only shifts divisible by byte_size).
2104 (define_expand "vec_shr_<mode>"
2105 [(set (match_operand:V 0 "register_operand" "=v")
2106 (unspec:V [(match_operand:V 1 "register_operand" "v")
2107 (match_operand:QI 2 "reg_or_short_operand" "")]
2108 UNSPEC_VECSH))]
2109 "TARGET_ALTIVEC"
2110 "
2111 {
2112 rtx bitshift = operands[2];
2113 rtx byteshift = gen_reg_rtx (QImode);
2114 HOST_WIDE_INT bitshift_val;
2115 HOST_WIDE_INT byteshift_val;
2117 if (! CONSTANT_P (bitshift))
2118 FAIL;
2119 bitshift_val = INTVAL (bitshift);
2120 if (bitshift_val & 0x7)
2121 FAIL;
2122 byteshift_val = 16 - (bitshift_val >> 3);
2123 byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
2124 emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
2125 byteshift));
2126 DONE;
2127 }")
2129 (define_insn "altivec_vsumsws_nomode"
2130 [(set (match_operand 0 "register_operand" "=v")
2131 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
2132 (match_operand:V4SI 2 "register_operand" "v")]
2133 UNSPEC_VSUMSWS))
2134 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
2135 "TARGET_ALTIVEC"
2136 "vsumsws %0,%1,%2"
2137 [(set_attr "type" "veccomplex")])
2139 (define_expand "reduc_splus_<mode>"
2140 [(set (match_operand:VIshort 0 "register_operand" "=v")
2141 (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
2142 UNSPEC_REDUC_PLUS))]
2143 "TARGET_ALTIVEC"
2144 "
2145 {
2146 rtx vzero = gen_reg_rtx (V4SImode);
2147 rtx vtmp1 = gen_reg_rtx (V4SImode);
2149 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2150 emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
2151 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2152 DONE;
2153 }")
2155 (define_expand "reduc_uplus_v16qi"
2156 [(set (match_operand:V16QI 0 "register_operand" "=v")
2157 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
2158 UNSPEC_REDUC_PLUS))]
2159 "TARGET_ALTIVEC"
2160 "
2161 {
2162 rtx vzero = gen_reg_rtx (V4SImode);
2163 rtx vtmp1 = gen_reg_rtx (V4SImode);
2165 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2166 emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
2167 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2168 DONE;
2169 }")
2171 (define_insn "vec_realign_load_<mode>"
2172 [(set (match_operand:V 0 "register_operand" "=v")
2173 (unspec:V [(match_operand:V 1 "register_operand" "v")
2174 (match_operand:V 2 "register_operand" "v")
2175 (match_operand:V16QI 3 "register_operand" "v")]
2176 UNSPEC_REALIGN_LOAD))]
2177 "TARGET_ALTIVEC"
2178 "vperm %0,%1,%2,%3"
2179 [(set_attr "type" "vecperm")])
2181 (define_expand "neg<mode>2"
2182 [(use (match_operand:VI 0 "register_operand" ""))
2183 (use (match_operand:VI 1 "register_operand" ""))]
2184 "TARGET_ALTIVEC"
2185 "
2186 {
2187 rtx vzero;
2189 vzero = gen_reg_rtx (GET_MODE (operands[0]));
2190 emit_insn (gen_altivec_vspltis<VI_char> (vzero, const0_rtx));
2191 emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1]));
2193 DONE;
2194 }")
2196 (define_expand "udot_prod<mode>"
2197 [(set (match_operand:V4SI 0 "register_operand" "=v")
2198 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
2199 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
2200 (match_operand:VIshort 2 "register_operand" "v")]
2201 UNSPEC_VMSUMU)))]
2202 "TARGET_ALTIVEC"
2203 "
2204 {
2205 emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], operands[2], operands[3]));
2206 DONE;
2207 }")
2209 (define_expand "sdot_prodv8hi"
2210 [(set (match_operand:V4SI 0 "register_operand" "=v")
2211 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
2212 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2213 (match_operand:V8HI 2 "register_operand" "v")]
2214 UNSPEC_VMSUMSHM)))]
2215 "TARGET_ALTIVEC"
2216 "
2217 {
2218 emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3]));
2219 DONE;
2220 }")
2222 (define_expand "widen_usum<mode>3"
2223 [(set (match_operand:V4SI 0 "register_operand" "=v")
2224 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2225 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
2226 UNSPEC_VMSUMU)))]
2227 "TARGET_ALTIVEC"
2228 "
2229 {
2230 rtx vones = gen_reg_rtx (GET_MODE (operands[1]));
2232 emit_insn (gen_altivec_vspltis<VI_char> (vones, const1_rtx));
2233 emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], vones, operands[2]));
2234 DONE;
2235 }")
2237 (define_expand "widen_ssumv16qi3"
2238 [(set (match_operand:V4SI 0 "register_operand" "=v")
2239 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2240 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
2241 UNSPEC_VMSUMM)))]
2242 "TARGET_ALTIVEC"
2243 "
2244 {
2245 rtx vones = gen_reg_rtx (V16QImode);
2247 emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
2248 emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2]));
2249 DONE;
2250 }")
2252 (define_expand "widen_ssumv8hi3"
2253 [(set (match_operand:V4SI 0 "register_operand" "=v")
2254 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2255 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2256 UNSPEC_VMSUMSHM)))]
2257 "TARGET_ALTIVEC"
2258 "
2259 {
2260 rtx vones = gen_reg_rtx (V8HImode);
2262 emit_insn (gen_altivec_vspltish (vones, const1_rtx));
2263 emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2]));
2264 DONE;
2265 }")
2267 (define_expand "vec_unpacks_hi_v16qi"
2268 [(set (match_operand:V8HI 0 "register_operand" "=v")
2269 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2270 UNSPEC_VUPKHSB))]
2271 "TARGET_ALTIVEC"
2272 "
2273 {
2274 emit_insn (gen_altivec_vupkhsb (operands[0], operands[1]));
2275 DONE;
2276 }")
2278 (define_expand "vec_unpacks_hi_v8hi"
2279 [(set (match_operand:V4SI 0 "register_operand" "=v")
2280 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2281 UNSPEC_VUPKHSH))]
2282 "TARGET_ALTIVEC"
2283 "
2284 {
2285 emit_insn (gen_altivec_vupkhsh (operands[0], operands[1]));
2286 DONE;
2287 }")
2289 (define_expand "vec_unpacks_lo_v16qi"
2290 [(set (match_operand:V8HI 0 "register_operand" "=v")
2291 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2292 UNSPEC_VUPKLSB))]
2293 "TARGET_ALTIVEC"
2294 "
2295 {
2296 emit_insn (gen_altivec_vupklsb (operands[0], operands[1]));
2297 DONE;
2298 }")
2300 (define_expand "vec_unpacks_lo_v8hi"
2301 [(set (match_operand:V4SI 0 "register_operand" "=v")
2302 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2303 UNSPEC_VUPKLSH))]
2304 "TARGET_ALTIVEC"
2305 "
2306 {
2307 emit_insn (gen_altivec_vupklsh (operands[0], operands[1]));
2308 DONE;
2309 }")
2311 (define_insn "vperm_v8hiv4si"
2312 [(set (match_operand:V4SI 0 "register_operand" "=v")
2313 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2314 (match_operand:V4SI 2 "register_operand" "v")
2315 (match_operand:V16QI 3 "register_operand" "v")]
2316 UNSPEC_VPERMSI))]
2317 "TARGET_ALTIVEC"
2318 "vperm %0,%1,%2,%3"
2319 [(set_attr "type" "vecperm")])
2321 (define_insn "vperm_v16qiv8hi"
2322 [(set (match_operand:V8HI 0 "register_operand" "=v")
2323 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2324 (match_operand:V8HI 2 "register_operand" "v")
2325 (match_operand:V16QI 3 "register_operand" "v")]
2326 UNSPEC_VPERMHI))]
2327 "TARGET_ALTIVEC"
2328 "vperm %0,%1,%2,%3"
2329 [(set_attr "type" "vecperm")])
2332 (define_expand "vec_unpacku_hi_v16qi"
2333 [(set (match_operand:V8HI 0 "register_operand" "=v")
2334 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2335 UNSPEC_VUPKHUB))]
2336 "TARGET_ALTIVEC"
2337 "
2338 {
2339 rtx vzero = gen_reg_rtx (V8HImode);
2340 rtx mask = gen_reg_rtx (V16QImode);
2341 rtvec v = rtvec_alloc (16);
2343 emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2345 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2346 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 0);
2347 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2348 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2349 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2350 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 2);
2351 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2352 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2353 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2354 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 4);
2355 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2356 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2357 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2358 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 6);
2359 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2360 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2362 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2363 emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2364 DONE;
2365 }")
2367 (define_expand "vec_unpacku_hi_v8hi"
2368 [(set (match_operand:V4SI 0 "register_operand" "=v")
2369 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2370 UNSPEC_VUPKHUH))]
2371 "TARGET_ALTIVEC"
2372 "
2373 {
2374 rtx vzero = gen_reg_rtx (V4SImode);
2375 rtx mask = gen_reg_rtx (V16QImode);
2376 rtvec v = rtvec_alloc (16);
2378 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2380 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2381 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2382 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 0);
2383 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2384 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2385 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2386 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 2);
2387 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2388 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2389 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2390 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 4);
2391 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2392 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2393 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2394 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 6);
2395 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2397 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2398 emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2399 DONE;
2400 }")
2402 (define_expand "vec_unpacku_lo_v16qi"
2403 [(set (match_operand:V8HI 0 "register_operand" "=v")
2404 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2405 UNSPEC_VUPKLUB))]
2406 "TARGET_ALTIVEC"
2407 "
2408 {
2409 rtx vzero = gen_reg_rtx (V8HImode);
2410 rtx mask = gen_reg_rtx (V16QImode);
2411 rtvec v = rtvec_alloc (16);
2413 emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2415 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2416 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 8);
2417 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2418 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2419 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2420 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
2421 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2422 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2423 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2424 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 12);
2425 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2426 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2427 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2428 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 14);
2429 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2430 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2432 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2433 emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2434 DONE;
2435 }")
2437 (define_expand "vec_unpacku_lo_v8hi"
2438 [(set (match_operand:V4SI 0 "register_operand" "=v")
2439 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2440 UNSPEC_VUPKLUH))]
2441 "TARGET_ALTIVEC"
2442 "
2443 {
2444 rtx vzero = gen_reg_rtx (V4SImode);
2445 rtx mask = gen_reg_rtx (V16QImode);
2446 rtvec v = rtvec_alloc (16);
2448 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2450 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2451 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2452 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 8);
2453 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2454 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2455 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2456 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2457 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2458 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2459 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2460 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 12);
2461 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2462 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2463 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2464 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 14);
2465 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2467 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2468 emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2469 DONE;
2470 }")
2472 (define_expand "vec_widen_umult_hi_v16qi"
2473 [(set (match_operand:V8HI 0 "register_operand" "=v")
2474 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2475 (match_operand:V16QI 2 "register_operand" "v")]
2476 UNSPEC_VMULWHUB))]
2477 "TARGET_ALTIVEC"
2478 "
2479 {
2480 rtx ve = gen_reg_rtx (V8HImode);
2481 rtx vo = gen_reg_rtx (V8HImode);
2483 emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2484 emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2485 emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2486 DONE;
2487 }")
2489 (define_expand "vec_widen_umult_lo_v16qi"
2490 [(set (match_operand:V8HI 0 "register_operand" "=v")
2491 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2492 (match_operand:V16QI 2 "register_operand" "v")]
2493 UNSPEC_VMULWLUB))]
2494 "TARGET_ALTIVEC"
2495 "
2496 {
2497 rtx ve = gen_reg_rtx (V8HImode);
2498 rtx vo = gen_reg_rtx (V8HImode);
2500 emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2501 emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2502 emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2503 DONE;
2504 }")
2506 (define_expand "vec_widen_smult_hi_v16qi"
2507 [(set (match_operand:V8HI 0 "register_operand" "=v")
2508 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2509 (match_operand:V16QI 2 "register_operand" "v")]
2510 UNSPEC_VMULWHSB))]
2511 "TARGET_ALTIVEC"
2512 "
2513 {
2514 rtx ve = gen_reg_rtx (V8HImode);
2515 rtx vo = gen_reg_rtx (V8HImode);
2517 emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2518 emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2519 emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2520 DONE;
2521 }")
2523 (define_expand "vec_widen_smult_lo_v16qi"
2524 [(set (match_operand:V8HI 0 "register_operand" "=v")
2525 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2526 (match_operand:V16QI 2 "register_operand" "v")]
2527 UNSPEC_VMULWLSB))]
2528 "TARGET_ALTIVEC"
2529 "
2530 {
2531 rtx ve = gen_reg_rtx (V8HImode);
2532 rtx vo = gen_reg_rtx (V8HImode);
2534 emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2535 emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2536 emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2537 DONE;
2538 }")
2540 (define_expand "vec_widen_umult_hi_v8hi"
2541 [(set (match_operand:V4SI 0 "register_operand" "=v")
2542 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2543 (match_operand:V8HI 2 "register_operand" "v")]
2544 UNSPEC_VMULWHUH))]
2545 "TARGET_ALTIVEC"
2546 "
2547 {
2548 rtx ve = gen_reg_rtx (V4SImode);
2549 rtx vo = gen_reg_rtx (V4SImode);
2551 emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2552 emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2553 emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2554 DONE;
2555 }")
2557 (define_expand "vec_widen_umult_lo_v8hi"
2558 [(set (match_operand:V4SI 0 "register_operand" "=v")
2559 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2560 (match_operand:V8HI 2 "register_operand" "v")]
2561 UNSPEC_VMULWLUH))]
2562 "TARGET_ALTIVEC"
2563 "
2564 {
2565 rtx ve = gen_reg_rtx (V4SImode);
2566 rtx vo = gen_reg_rtx (V4SImode);
2568 emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2569 emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2570 emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2571 DONE;
2572 }")
2574 (define_expand "vec_widen_smult_hi_v8hi"
2575 [(set (match_operand:V4SI 0 "register_operand" "=v")
2576 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2577 (match_operand:V8HI 2 "register_operand" "v")]
2578 UNSPEC_VMULWHSH))]
2579 "TARGET_ALTIVEC"
2580 "
2581 {
2582 rtx ve = gen_reg_rtx (V4SImode);
2583 rtx vo = gen_reg_rtx (V4SImode);
2585 emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2586 emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2587 emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2588 DONE;
2589 }")
2591 (define_expand "vec_widen_smult_lo_v8hi"
2592 [(set (match_operand:V4SI 0 "register_operand" "=v")
2593 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2594 (match_operand:V8HI 2 "register_operand" "v")]
2595 UNSPEC_VMULWLSH))]
2596 "TARGET_ALTIVEC"
2597 "
2598 {
2599 rtx ve = gen_reg_rtx (V4SImode);
2600 rtx vo = gen_reg_rtx (V4SImode);
2602 emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2603 emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2604 emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2605 DONE;
2606 }")
2608 (define_expand "vec_pack_trunc_v8hi"
2609 [(set (match_operand:V16QI 0 "register_operand" "=v")
2610 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
2611 (match_operand:V8HI 2 "register_operand" "v")]
2612 UNSPEC_VPKUHUM))]
2613 "TARGET_ALTIVEC"
2614 "
2615 {
2616 emit_insn (gen_altivec_vpkuhum (operands[0], operands[1], operands[2]));
2617 DONE;
2618 }")
2620 (define_expand "vec_pack_trunc_v4si"
2621 [(set (match_operand:V8HI 0 "register_operand" "=v")
2622 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
2623 (match_operand:V4SI 2 "register_operand" "v")]
2624 UNSPEC_VPKUWUM))]
2625 "TARGET_ALTIVEC"
2626 "
2627 {
2628 emit_insn (gen_altivec_vpkuwum (operands[0], operands[1], operands[2]));
2629 DONE;
2630 }")
2632 (define_expand "negv4sf2"
2633 [(use (match_operand:V4SF 0 "register_operand" ""))
2634 (use (match_operand:V4SF 1 "register_operand" ""))]
2635 "TARGET_ALTIVEC"
2636 "
2637 {
2638 rtx neg0;
2640 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
2641 neg0 = gen_reg_rtx (V4SImode);
2642 emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
2643 emit_insn (gen_vashlv4si3 (neg0, neg0, neg0));
2645 /* XOR */
2646 emit_insn (gen_xorv4sf3 (operands[0],
2647 gen_lowpart (V4SFmode, neg0), operands[1]));
2649 DONE;
2650 }")
2652 (define_expand "vec_extract_evenv4si"
2653 [(set (match_operand:V4SI 0 "register_operand" "")
2654 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
2655 (match_operand:V4SI 2 "register_operand" "")]
2656 UNSPEC_EXTEVEN_V4SI))]
2657 "TARGET_ALTIVEC"
2658 "
2659 {
2660 rtx mask = gen_reg_rtx (V16QImode);
2661 rtvec v = rtvec_alloc (16);
2663 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2664 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2665 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
2666 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
2667 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2668 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2669 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2670 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2671 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2672 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2673 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
2674 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
2675 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2676 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2677 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
2678 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
2679 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2680 emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
2682 DONE;
2683 }")
2685 (define_expand "vec_extract_evenv4sf"
2686 [(set (match_operand:V4SF 0 "register_operand" "")
2687 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
2688 (match_operand:V4SF 2 "register_operand" "")]
2689 UNSPEC_EXTEVEN_V4SF))]
2690 "TARGET_ALTIVEC"
2691 "
2692 {
2693 rtx mask = gen_reg_rtx (V16QImode);
2694 rtvec v = rtvec_alloc (16);
2696 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2697 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2698 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
2699 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
2700 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2701 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2702 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2703 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2704 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2705 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2706 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
2707 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
2708 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2709 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2710 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
2711 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
2712 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2713 emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
2715 DONE;
2716 }")
2718 (define_expand "vec_extract_evenv8hi"
2719 [(set (match_operand:V4SI 0 "register_operand" "")
2720 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
2721 (match_operand:V8HI 2 "register_operand" "")]
2722 UNSPEC_EXTEVEN_V8HI))]
2723 "TARGET_ALTIVEC"
2724 "
2725 {
2726 rtx mask = gen_reg_rtx (V16QImode);
2727 rtvec v = rtvec_alloc (16);
2729 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2730 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2731 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
2732 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 5);
2733 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2734 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2735 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
2736 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 13);
2737 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2738 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2739 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
2740 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 21);
2741 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2742 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2743 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
2744 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 29);
2745 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2746 emit_insn (gen_altivec_vperm_v8hi (operands[0], operands[1], operands[2], mask));
2748 DONE;
2749 }")
2751 (define_expand "vec_extract_evenv16qi"
2752 [(set (match_operand:V4SI 0 "register_operand" "")
2753 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "")
2754 (match_operand:V16QI 2 "register_operand" "")]
2755 UNSPEC_EXTEVEN_V16QI))]
2756 "TARGET_ALTIVEC"
2757 "
2758 {
2759 rtx mask = gen_reg_rtx (V16QImode);
2760 rtvec v = rtvec_alloc (16);
2762 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2763 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 2);
2764 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
2765 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 6);
2766 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2767 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
2768 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
2769 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 14);
2770 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2771 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 18);
2772 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
2773 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 22);
2774 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2775 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 26);
2776 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
2777 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 30);
2778 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2779 emit_insn (gen_altivec_vperm_v16qi (operands[0], operands[1], operands[2], mask));
2781 DONE;
2782 }")
2784 (define_expand "vec_extract_oddv4si"
2785 [(set (match_operand:V4SI 0 "register_operand" "")
2786 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
2787 (match_operand:V4SI 2 "register_operand" "")]
2788 UNSPEC_EXTODD_V4SI))]
2789 "TARGET_ALTIVEC"
2790 "
2791 {
2792 rtx mask = gen_reg_rtx (V16QImode);
2793 rtvec v = rtvec_alloc (16);
2795 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
2796 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
2797 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
2798 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
2799 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
2800 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
2801 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
2802 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
2803 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
2804 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
2805 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
2806 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
2807 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
2808 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
2809 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
2810 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
2811 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2812 emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
2814 DONE;
2815 }")
2817 (define_expand "vec_extract_oddv4sf"
2818 [(set (match_operand:V4SF 0 "register_operand" "")
2819 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
2820 (match_operand:V4SF 2 "register_operand" "")]
2821 UNSPEC_EXTODD_V4SF))]
2822 "TARGET_ALTIVEC"
2823 "
2824 {
2825 rtx mask = gen_reg_rtx (V16QImode);
2826 rtvec v = rtvec_alloc (16);
2828 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
2829 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
2830 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
2831 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
2832 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
2833 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
2834 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
2835 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
2836 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
2837 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
2838 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
2839 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
2840 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
2841 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
2842 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
2843 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
2844 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2845 emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
2847 DONE;
2848 }")
2850 (define_insn "vpkuhum_nomode"
2851 [(set (match_operand:V16QI 0 "register_operand" "=v")
2852 (unspec:V16QI [(match_operand 1 "register_operand" "v")
2853 (match_operand 2 "register_operand" "v")]
2854 UNSPEC_VPKUHUM))]
2855 "TARGET_ALTIVEC"
2856 "vpkuhum %0,%1,%2"
2857 [(set_attr "type" "vecperm")])
2859 (define_insn "vpkuwum_nomode"
2860 [(set (match_operand:V8HI 0 "register_operand" "=v")
2861 (unspec:V8HI [(match_operand 1 "register_operand" "v")
2862 (match_operand 2 "register_operand" "v")]
2863 UNSPEC_VPKUWUM))]
2864 "TARGET_ALTIVEC"
2865 "vpkuwum %0,%1,%2"
2866 [(set_attr "type" "vecperm")])
2868 (define_expand "vec_extract_oddv8hi"
2869 [(set (match_operand:V8HI 0 "register_operand" "")
2870 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
2871 (match_operand:V8HI 2 "register_operand" "")]
2872 UNSPEC_EXTODD_V8HI))]
2873 "TARGET_ALTIVEC"
2874 "
2875 {
2876 emit_insn (gen_vpkuwum_nomode (operands[0], operands[1], operands[2]));
2877 DONE;
2878 }")
2880 (define_expand "vec_extract_oddv16qi"
2881 [(set (match_operand:V16QI 0 "register_operand" "")
2882 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
2883 (match_operand:V16QI 2 "register_operand" "")]
2884 UNSPEC_EXTODD_V16QI))]
2885 "TARGET_ALTIVEC"
2886 "
2887 {
2888 emit_insn (gen_vpkuhum_nomode (operands[0], operands[1], operands[2]));
2889 DONE;
2890 }")
2891 (define_expand "vec_interleave_highv4sf"
2892 [(set (match_operand:V4SF 0 "register_operand" "")
2893 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
2894 (match_operand:V4SF 2 "register_operand" "")]
2895 UNSPEC_INTERHI_V4SF))]
2896 "TARGET_ALTIVEC"
2897 "
2898 {
2899 emit_insn (gen_altivec_vmrghsf (operands[0], operands[1], operands[2]));
2900 DONE;
2901 }")
2903 (define_expand "vec_interleave_lowv4sf"
2904 [(set (match_operand:V4SF 0 "register_operand" "")
2905 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
2906 (match_operand:V4SF 2 "register_operand" "")]
2907 UNSPEC_INTERLO_V4SF))]
2908 "TARGET_ALTIVEC"
2909 "
2910 {
2911 emit_insn (gen_altivec_vmrglsf (operands[0], operands[1], operands[2]));
2912 DONE;
2913 }")
2915 (define_expand "vec_interleave_high<mode>"
2916 [(set (match_operand:VI 0 "register_operand" "")
2917 (unspec:VI [(match_operand:VI 1 "register_operand" "")
2918 (match_operand:VI 2 "register_operand" "")]
2919 UNSPEC_INTERHI))]
2920 "TARGET_ALTIVEC"
2921 "
2922 {
2923 emit_insn (gen_altivec_vmrgh<VI_char> (operands[0], operands[1], operands[2]));
2924 DONE;
2925 }")
2927 (define_expand "vec_interleave_low<mode>"
2928 [(set (match_operand:VI 0 "register_operand" "")
2929 (unspec:VI [(match_operand:VI 1 "register_operand" "")
2930 (match_operand:VI 2 "register_operand" "")]
2931 UNSPEC_INTERLO))]
2932 "TARGET_ALTIVEC"
2933 "
2934 {
2935 emit_insn (gen_altivec_vmrgl<VI_char> (operands[0], operands[1], operands[2]));
2936 DONE;
2937 }")
2939 (define_expand "vec_unpacks_float_hi_v8hi"
2940 [(set (match_operand:V4SF 0 "register_operand" "")
2941 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
2942 UNSPEC_VUPKHS_V4SF))]
2943 "TARGET_ALTIVEC"
2944 "
2945 {
2946 rtx tmp = gen_reg_rtx (V4SImode);
2948 emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1]));
2949 emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
2950 DONE;
2951 }")
2953 (define_expand "vec_unpacks_float_lo_v8hi"
2954 [(set (match_operand:V4SF 0 "register_operand" "")
2955 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
2956 UNSPEC_VUPKLS_V4SF))]
2957 "TARGET_ALTIVEC"
2958 "
2959 {
2960 rtx tmp = gen_reg_rtx (V4SImode);
2962 emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1]));
2963 emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
2964 DONE;
2965 }")
2967 (define_expand "vec_unpacku_float_hi_v8hi"
2968 [(set (match_operand:V4SF 0 "register_operand" "")
2969 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
2970 UNSPEC_VUPKHU_V4SF))]
2971 "TARGET_ALTIVEC"
2972 "
2973 {
2974 rtx tmp = gen_reg_rtx (V4SImode);
2976 emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1]));
2977 emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
2978 DONE;
2979 }")
2981 (define_expand "vec_unpacku_float_lo_v8hi"
2982 [(set (match_operand:V4SF 0 "register_operand" "")
2983 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
2984 UNSPEC_VUPKLU_V4SF))]
2985 "TARGET_ALTIVEC"
2986 "
2987 {
2988 rtx tmp = gen_reg_rtx (V4SImode);
2990 emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1]));
2991 emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
2992 DONE;
2993 }")