1 ;; GCC machine description for CRIS cpu cores.
2 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Axis Communications.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
25 ;; See files "md.texi" and "rtl.def" for documentation on define_insn,
28 ;; The function cris_notice_update_cc in cris.c handles condition code
29 ;; updates for most instructions, helped by the "cc" attribute.
31 ;; There are several instructions that are orthogonal in size, and seems
32 ;; they could be matched by a single pattern without a specified size
33 ;; for the operand that is orthogonal. However, this did not work on
34 ;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a
35 ;; constant is substituted into an operand, the actual mode must be
36 ;; deduced from the pattern. There is reasonable hope that that has been
37 ;; fixed, so FIXME: try again.
39 ;; You will notice that three-operand alternatives ("=r", "r", "!To")
40 ;; are marked with a "!" constraint modifier to avoid being reloaded
41 ;; into. This is because gcc would otherwise prefer to use the constant
42 ;; pool and its offsettable address instead of reloading to an
43 ;; ("=r", "0", "i") alternative. Also, the constant-pool support was not
44 ;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3.
46 ;; All insns that look like (set (...) (plus (...) (reg:SI 8)))
47 ;; get problems when reloading r8 (frame pointer) to r14 + offs (stack
48 ;; pointer). Thus the instructions that get into trouble have specific
49 ;; checks against matching frame_pointer_rtx.
50 ;; ??? But it should be re-checked for gcc > 2.7.2
51 ;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x.
53 ;; FIXME: When PIC, all [rX=rY+S] could be enabled to match
54 ;; [rX=gotless_symbol].
55 ;; The movsi for a gotless symbol could be split (post reload).
60 ;; PLT reference from call expansion: operand 0 is the address,
61 ;; the mode is VOIDmode. Always wrapped in CONST.
62 ;; The value is relative to the GOT.
63 (CRIS_UNSPEC_PLT_GOTREL 0)
65 ;; PLT reference from call expansion: operand 0 is the address,
66 ;; the mode is VOIDmode. Always wrapped in CONST.
67 ;; The value is relative to the PC. It's arch-dependent whether
68 ;; the offset counts from the start or the end of the current item.
69 (CRIS_UNSPEC_PLT_PCREL 1)
71 ;; The address of the global offset table as a source operand.
74 ;; The offset from the global offset table to the operand.
75 (CRIS_UNSPEC_GOTREL 3)
77 ;; The PC-relative offset to the operand. It's arch-dependent whether
78 ;; the offset counts from the start or the end of the current item.
81 ;; The index into the global offset table of a symbol, while
82 ;; also generating a GOT entry for the symbol.
83 (CRIS_UNSPEC_GOTREAD 5)
85 ;; Similar to CRIS_UNSPEC_GOTREAD, but also generating a PLT entry.
86 (CRIS_UNSPEC_PLTGOTREAD 6)
88 ;; Condition for v32 casesi jump, since it needs to have if_then_else
89 ;; form with register as one branch and default label as other.
90 ;; Operand 0 is const_int 0.
91 (CRIS_UNSPEC_CASESI 7)
93 ;; Stack frame deallocation barrier.
94 (CRIS_UNSPEC_FRAME_DEALLOC 8)
96 ;; Swap all 32 bits of the operand; 31 <=> 0, 30 <=> 1...
97 (CRIS_UNSPEC_SWAP_BITS 9)
103 (CRIS_STATIC_CHAIN_REGNUM 7)
110 (CRIS_CC0_REGNUM 19)]
113 ;; We need an attribute to define whether an instruction can be put in
114 ;; a branch-delay slot or not, and whether it has a delay slot.
116 ;; Branches and return instructions have a delay slot, and cannot
117 ;; themselves be put in a delay slot. This has changed *for short
118 ;; branches only* between architecture variants, but the possible win
119 ;; is presumed negligible compared to the added complexity of the machine
120 ;; description: one would have to add always-correct infrastructure to
121 ;; distinguish short branches.
123 ;; Whether an instruction can be put in a delay slot depends on the
124 ;; instruction (all short instructions except jumps and branches)
125 ;; and the addressing mode (must not be prefixed or referring to pc).
126 ;; In short, any "slottable" instruction must be 16 bit and not refer
127 ;; to pc, or alter it.
129 ;; The possible values are "yes", "no", "has_slot", "has_return_slot"
130 ;; and "has_call_slot".
131 ;; Yes/no tells whether the insn is slottable or not. Has_call_slot means
132 ;; that the insn is a call insn, which for CRIS v32 has a delay-slot.
133 ;; Of special concern is that no RTX_FRAME_RELATED insn must go in that
134 ;; call delay slot, as it's located in the address *after* the call insn,
135 ;; and the unwind machinery doesn't know about delay slots.
136 ;; Has_slot means that the insn is a branch insn (which are
137 ;; not considered slottable since that is generally true). Having the
138 ;; seemingly illogical value "has_slot" means we do not have to add
139 ;; another attribute just to say that an insn has a delay-slot, since it
140 ;; also infers that it is not slottable. Better names for the attribute
141 ;; were found to be longer and not add readability to the machine
143 ;; Has_return_slot is similar, for the return insn.
145 ;; The default that is defined here for this attribute is "no", not
146 ;; slottable, not having a delay-slot, so there's no need to worry about
147 ;; it being wrong for non-branch and return instructions.
148 ;; The default could depend on the kind of insn and the addressing
149 ;; mode, but that would need more attributes and hairier, more error
152 ;; There is an extra memory constraint, 'Q', which recognizes an indirect
153 ;; register. The constraints 'Q' and '>' together match all possible
154 ;; memory operands that are slottable.
155 ;; For other operands, you need to check if it has a valid "slottable"
156 ;; quick-immediate operand, where the particular signedness-variation
157 ;; may match the constraints 'I' or 'J'.), and include it in the
158 ;; constraint pattern for the slottable pattern. An alternative using
159 ;; only "r" constraints is most often slottable.
161 (define_attr "slottable" "no,yes,has_slot,has_return_slot,has_call_slot"
164 ;; We also need attributes to sanely determine the condition code
165 ;; state. See cris_notice_update_cc for how this is used.
167 (define_attr "cc" "none,clobber,normal,noov32,rev" (const_string "normal"))
169 ;; At the moment, this attribute is just used to help bb-reorder do its
170 ;; work; the default 0 doesn't help it. Many insns have other lengths,
171 ;; though none are shorter.
172 (define_attr "length" "" (const_int 2))
174 ;; A branch has one delay-slot. The instruction in the
175 ;; delay-slot is always executed, independent of whether the branch is
176 ;; taken or not. Note that besides setting "slottable" to "has_slot",
177 ;; there also has to be a "%#" at the end of a "delayed" instruction
178 ;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can
179 ;; catch it and print a "nop" if necessary. This method was stolen from
182 (define_delay (eq_attr "slottable" "has_slot")
183 [(eq_attr "slottable" "yes") (nil) (nil)])
185 ;; We can't put prologue insns in call-insn delay-slots when
186 ;; DWARF2 unwind info is emitted, because the unwinder matches the
187 ;; address after the insn. It must see the return address of a call at
188 ;; a position at least *one byte after* the insn, or it'll think that
189 ;; the insn hasn't been executed. If the insn is in a delay-slot of a
190 ;; call, it's just *exactly* after the insn.
192 (define_delay (eq_attr "slottable" "has_call_slot")
193 [(and (eq_attr "slottable" "yes")
194 (ior (eq (symbol_ref "RTX_FRAME_RELATED_P (insn)")
196 (eq (symbol_ref "flag_exceptions")
200 ;; The insn in the return insn slot must not be the
201 ;; return-address-register restore. FIXME: Use has_slot and express
202 ;; as a parallel with a use of the return-address-register (currently
203 ;; only SRP). However, this requires an amount of fixing tests for
204 ;; naked RETURN in middle-end.
205 (define_delay (eq_attr "slottable" "has_return_slot")
206 [(and (eq_attr "slottable" "yes")
207 (eq (symbol_ref "dead_or_set_regno_p (insn, CRIS_SRP_REGNUM)")
212 ;; Iterator definitions.
214 ;; For the "usual" pattern size alternatives.
215 (define_mode_iterator BWD [SI HI QI])
216 (define_mode_iterator WD [SI HI])
217 (define_mode_iterator BW [HI QI])
218 (define_mode_attr S [(SI "HI") (HI "QI")])
219 (define_mode_attr s [(SI "hi") (HI "qi")])
220 (define_mode_attr m [(SI ".d") (HI ".w") (QI ".b")])
221 (define_mode_attr mm [(SI ".w") (HI ".b")])
222 (define_mode_attr nbitsm1 [(SI "31") (HI "15") (QI "7")])
224 ;; For the sign_extend+zero_extend variants.
225 (define_code_iterator szext [sign_extend zero_extend])
226 (define_code_attr u [(sign_extend "") (zero_extend "u")])
227 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
229 ;; For the shift variants.
230 (define_code_iterator shift [ashiftrt lshiftrt ashift])
231 (define_code_iterator shiftrt [ashiftrt lshiftrt])
232 (define_code_attr shlr [(ashiftrt "ashr") (lshiftrt "lshr") (ashift "ashl")])
233 (define_code_attr slr [(ashiftrt "asr") (lshiftrt "lsr") (ashift "lsl")])
235 (define_code_iterator ncond [eq ne gtu ltu geu leu])
236 (define_code_iterator ocond [gt le])
237 (define_code_iterator rcond [lt ge])
238 (define_code_attr CC [(eq "eq") (ne "ne") (gt "gt") (gtu "hi") (lt "lt")
239 (ltu "lo") (ge "ge") (geu "hs") (le "le") (leu "ls")])
240 (define_code_attr rCC [(eq "ne") (ne "eq") (gt "le") (gtu "ls") (lt "ge")
241 (ltu "hs") (ge "lt") (geu "lo") (le "gt") (leu "hi")])
242 (define_code_attr oCC [(lt "mi") (ge "pl")])
243 (define_code_attr roCC [(lt "pl") (ge "mi")])
245 ;; Operand and operator predicates.
247 (include "predicates.md")
253 ;; Allow register and offsettable mem operands only; post-increment is
254 ;; not worth the trouble.
256 (define_expand "tstdi"
257 [(set (cc0) (match_operand:DI 0 "nonimmediate_operand"))]
260 if (TARGET_V32 && MEM_P (operands[0]))
261 operands[0] = force_reg (DImode, operands[0]);
264 (define_insn "*tstdi_non_v32"
266 (match_operand:DI 0 "nonimmediate_operand" "r,o"))]
268 "test.d %M0\;ax\;test.d %H0")
270 (define_insn "*tstdi_v32"
272 (match_operand:DI 0 "register_operand" "r"))]
274 "cmpq 0,%M0\;ax\;cmpq 0,%H0")
276 ;; No test insns with side-effect on the mem addressing.
278 ;; See note on cmp-insns with side-effects (or lack of them)
280 ;; Normal named test patterns from SI on.
284 (match_operand:SI 0 "nonimmediate_operand" "r,Q>,m"))]
287 if (which_alternative == 0 && TARGET_V32)
291 [(set_attr "slottable" "yes,yes,no")])
293 (define_expand "tst<mode>"
295 (match_operand:BW 0 "nonimmediate_operand"))]
299 (define_insn "*tst<mode>_cmp"
301 (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m"))]
302 "cris_cc0_user_requires_cmp (insn)"
307 [(set_attr "slottable" "no,yes,no")])
309 (define_insn "*tst<mode>_non_cmp"
311 (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m"))]
312 "!cris_cc0_user_requires_cmp (insn)"
317 [(set_attr "slottable" "yes,yes,no")
318 (set_attr "cc" "noov32,*,*")])
320 ;; It seems that the position of the sign-bit and the fact that 0.0 is
321 ;; all 0-bits would make "tstsf" a straight-forward implementation;
322 ;; either "test.d" it for positive/negative or "btstq 30,r" it for
325 ;; FIXME: Do that some time; check next_cc0_user to determine if
326 ;; zero or negative is tested for.
330 ;; We could optimize the sizes of the immediate operands for various
331 ;; cases, but that is not worth it because of the very little usage of
332 ;; DImode for anything else but a structure/block-mode. Just do the
333 ;; obvious stuff for the straight-forward constraint letters.
335 (define_expand "cmpdi"
337 (compare (match_operand:DI 0 "nonimmediate_operand" "")
338 (match_operand:DI 1 "general_operand" "")))]
341 if (TARGET_V32 && !REG_P (operands[0]))
342 operands[0] = force_reg (DImode, operands[0]);
343 if (TARGET_V32 && MEM_P (operands[1]))
344 operands[1] = force_reg (DImode, operands[1]);
347 (define_insn "*cmpdi_non_v32"
349 (compare (match_operand:DI 0 "nonimmediate_operand" "r,r,r,r,r,r,o")
350 (match_operand:DI 1 "general_operand" "K,I,P,n,r,o,r")))]
353 cmpq %1,%M0\;ax\;cmpq 0,%H0
354 cmpq %1,%M0\;ax\;cmpq -1,%H0
355 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
356 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
357 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
358 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
359 cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1")
361 (define_insn "*cmpdi_v32"
363 (compare (match_operand:DI 0 "register_operand" "r,r,r,r,r")
364 (match_operand:DI 1 "nonmemory_operand" "K,I,P,n,r")))]
367 cmpq %1,%M0\;ax\;cmpq 0,%H0
368 cmpq %1,%M0\;ax\;cmpq -1,%H0
369 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
370 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
371 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0")
373 ;; Note that compare insns with side effect addressing mode (e.g.):
375 ;; cmp.S [rx=ry+i],rz;
376 ;; cmp.S [%3=%1+%2],%0
378 ;; are *not* usable for gcc since the reloader *does not accept*
379 ;; cc0-changing insns with side-effects other than setting the condition
380 ;; codes. The reason is that the reload stage *may* cause another insn to
381 ;; be output after the main instruction, in turn invalidating cc0 for the
382 ;; insn using the test. (This does not apply to the CRIS case, since a
383 ;; reload for output -- move to memory -- does not change the condition
384 ;; code. Unfortunately we have no way to describe that at the moment. I
385 ;; think code would improve being in the order of one percent faster.
387 ;; We have cmps and cmpu (compare reg w. sign/zero extended mem).
388 ;; These are mostly useful for compares in SImode, using 8 or 16-bit
389 ;; constants, but sometimes gcc will find its way to use it for other
390 ;; (memory) operands. Avoid side-effect patterns, though (see above).
392 (define_insn "*cmp_ext<mode>"
395 (match_operand:SI 0 "register_operand" "r,r")
396 (match_operator:SI 2 "cris_extend_operator"
397 [(match_operand:BW 1 "memory_operand" "Q>,m")])))]
400 [(set_attr "slottable" "yes,no")])
402 ;; Swap operands; it seems the canonical look (if any) is not enforced.
404 ;; FIXME: Investigate that.
406 (define_insn "*cmp_swapext<mode>"
409 (match_operator:SI 2 "cris_extend_operator"
410 [(match_operand:BW 0 "memory_operand" "Q>,m")])
411 (match_operand:SI 1 "register_operand" "r,r")))]
414 [(set_attr "slottable" "yes,no")
415 (set_attr "cc" "rev")])
417 ;; The "normal" compare patterns, from SI on. Special-cases with zero
418 ;; should not happen.
423 (match_operand:SI 0 "nonimmediate_operand" "r,r,r, Q>,r,r,m")
424 (match_operand:SI 1 "general_operand" "I,r,Q>,r, P,g,r")))]
434 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")
435 (set_attr "cc" "normal,normal,normal,rev,normal,normal,rev")])
437 (define_insn "cmp<mode>"
439 (compare (match_operand:BW 0 "nonimmediate_operand" "r,r, Q>,r,m")
440 (match_operand:BW 1 "general_operand" "r,Q>,r, g,r")))]
448 [(set_attr "slottable" "yes,yes,yes,no,no")
449 (set_attr "cc" "normal,normal,rev,normal,rev")])
451 ;; Pattern matching the BTST insn.
452 ;; It is useful for "if (i & val)" constructs, where val is an exact
453 ;; power of 2, or if val + 1 is a power of two, where we check for a bunch
454 ;; of zeros starting at bit 0).
456 ;; SImode. This mode is the only one needed, since gcc automatically
457 ;; extends subregs for lower-size modes. FIXME: Add testcase.
461 (match_operand:SI 0 "nonmemory_operand" "r,r,r,r,r,r,n")
462 (match_operand:SI 1 "const_int_operand" "K,n,K,n,K,n,n")
463 (match_operand:SI 2 "nonmemory_operand" "M,M,K,n,r,r,r")))]
464 ;; Either it is a single bit, or consecutive ones starting at 0.
465 ;; The btst ones depend on stuff in NOTICE_UPDATE_CC.
466 "CONST_INT_P (operands[1])
467 && (operands[1] == const1_rtx || operands[2] == const0_rtx)
468 && (REG_S_P (operands[0])
469 || (operands[1] == const1_rtx
470 && REG_S_P (operands[2])
471 && CONST_INT_P (operands[0])
472 && exact_log2 (INTVAL (operands[0])) >= 0))
475 ;; The next-to-last "&&" condition above should be caught by some kind of
476 ;; canonicalization in gcc, but we can easily help with it here.
477 ;; It results from expressions of the type
478 ;; "power_of_2_value & (1 << y)".
480 ;; Since there may be codes with tests in on bits (in constant position)
481 ;; beyond the size of a word, handle that by assuming those bits are 0.
482 ;; GCC should handle that, but it's a matter of easily-added belts while
483 ;; having suspenders.
493 [(set_attr "slottable" "yes")
494 (set_attr "cc" "noov32")])
498 ;; The whole mandatory movdi family is here; expander, "anonymous"
499 ;; recognizer and splitter. We're forced to have a movdi pattern,
500 ;; although GCC should be able to split it up itself. Normally it can,
501 ;; but if other insns have DI operands (as is the case here), reload
502 ;; must be able to generate or match a movdi. many testcases fail at
503 ;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See
504 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00104.html>.
505 ;; However, a patch from Richard Kenner (similar to the cause of
506 ;; discussion at the URL above), indicates otherwise. See
507 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00554.html>.
508 ;; The truth has IMO is not been decided yet, so check from time to
509 ;; time by disabling the movdi patterns.
511 ;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at
512 ;; -O0, we need a movdi as a temporary measure. Here's how things fail:
513 ;; A cmpdi RTX needs reloading (global):
514 ;; (insn 185 326 186 (set (cc0)
515 ;; (compare (mem/f:DI (reg/v:SI 22) 0)
516 ;; (const_int 1 [0x1]))) 4 {cmpdi} (nil)
518 ;; Now, reg 22 is reloaded for input address, and the mem is also moved
519 ;; out of the instruction (into a register), since one of the operands
520 ;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is
521 ;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok
522 ;; wrt. overlap). The bad things happen with the synthesis in
523 ;; emit_move_insn_1; the location where to substitute reg 10 is lost into
524 ;; two new RTX:es, both still having reg 22. Later on, the left-over reg
525 ;; 22 is recognized to have an equivalent in memory which is substituted
526 ;; straight in, and we end up with an unrecognizable insn:
527 ;; (insn 325 324 326 (set (reg:SI 9 r9)
528 ;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8)
529 ;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil)
531 ;; which is the first part of the reloaded synthesized "movdi".
532 ;; The right thing would be to add equivalent replacement locations for
533 ;; insn with pseudos that need more reloading. The question is where.
535 (define_expand "movdi"
536 [(set (match_operand:DI 0 "nonimmediate_operand" "")
537 (match_operand:DI 1 "general_operand" ""))]
540 if (MEM_P (operands[0])
541 && operands[1] != const0_rtx
542 && (!TARGET_V32 || (!REG_P (operands[1]) && can_create_pseudo_p ())))
543 operands[1] = copy_to_mode_reg (DImode, operands[1]);
545 /* Some other ports (as of 2001-09-10 for example mcore and romp) also
546 prefer to split up constants early, like this. The testcase in
547 gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the
548 resulting subreg sets when using the construct from mcore (as of FSF
549 CVS, version -r 1.5), and it believes that the high part (the last one
550 emitted) is the final value. */
551 if ((CONST_INT_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
552 && ! reload_completed
553 && ! reload_in_progress)
556 rtx op0 = operands[0];
557 rtx op1 = operands[1];
560 emit_move_insn (operand_subword (op0, 0, 1, DImode),
561 operand_subword (op1, 0, 1, DImode));
562 emit_move_insn (operand_subword (op0, 1, 1, DImode),
563 operand_subword (op1, 1, 1, DImode));
564 insns = get_insns ();
572 (define_insn_and_split "*movdi_insn_non_v32"
573 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rx,m")
574 (match_operand:DI 1 "general_operand" "rx,g,rxM"))]
575 "(register_operand (operands[0], DImode)
576 || register_operand (operands[1], DImode)
577 || operands[1] == const0_rtx)
580 "&& reload_completed"
582 "operands[2] = cris_split_movdx (operands);")
584 ;; Overlapping (but non-identical) source memory address and destination
585 ;; register would be a compiler bug, so we don't have to specify that.
586 (define_insn "*movdi_v32"
588 (match_operand:DI 0 "nonimmediate_operand" "=r,rx,&r,>, m,r,x,m")
589 (match_operand:DI 1 "general_operand" "rxi,r>,m, rx,r,m,m,x"))]
592 switch (which_alternative)
594 /* FIXME: 1) Use autoincrement where possible. 2) Have peephole2,
595 particularly for cases where the address register is dead. */
597 if (REGNO (operands[0]) == REGNO (XEXP (operands[1], 0)))
598 return "addq 4,%L1\;move.d %1,%H0\;subq 4,%L1\;move.d %1,%M0";
599 gcc_assert (REGNO (operands[0]) + 1 == REGNO (XEXP (operands[1], 0)));
600 return "move.d [%L1+],%M0\;move.d [%L1],%H0";
602 /* We could do away with the addq if we knew the address-register
603 isn't ACR. If we knew the address-register is dead, we could do
604 away with the subq too. */
605 return "move.d [%L1],%M0\;addq 4,%L1\;move.d [%L1],%H0\;subq 4,%L1";
607 return "move.d %M1,[%L0]\;addq 4,%L0\;move.d %H1,[%L0]\;subq 4,%L0";
609 return "move [%L1],%M0\;addq 4,%L1\;move [%L1],%H0\;subq 4,%L1";
611 return "move %M1,[%L0]\;addq 4,%L0\;move %H1,[%L0]\;subq 4,%L0";
617 ;; The non-split cases clobber cc0 because of their adds and subs.
618 ;; Beware that NOTICE_UPDATE_CC is called before the forced split happens.
619 [(set_attr "cc" "*,*,clobber,*,clobber,clobber,*,*")])
621 ;; Much like "*movdi_insn_non_v32". Overlapping registers and constants
622 ;; is handled so much better in cris_split_movdx.
624 [(set (match_operand:DI 0 "nonimmediate_operand" "")
625 (match_operand:DI 1 "general_operand" ""))]
628 && (!MEM_P (operands[0]) || !REG_P (XEXP (operands[0], 0)))
629 && (!MEM_P (operands[1]) || !REG_P (XEXP (operands[1], 0)))"
631 "operands[2] = cris_split_movdx (operands);")
633 ;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw
634 ;; and move.S1 [rx=ry+i],rz
635 ;; Then movs.S1 and movu.S1 for both modes.
637 ;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx
638 ;; FIXME: These could have anonymous mode for operand 0.
639 ;; FIXME: Special registers' alternatives too.
641 (define_insn "*mov_side<mode>_biap"
642 [(set (match_operand:BW 0 "register_operand" "=r,r")
644 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
645 (match_operand:SI 2 "const_int_operand" "n,n"))
646 (match_operand:SI 3 "register_operand" "r,r"))))
647 (set (match_operand:SI 4 "register_operand" "=*3,r")
648 (plus:SI (mult:SI (match_dup 1)
651 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
654 move<m> [%4=%3+%1%T2],%0")
656 (define_insn "*mov_sidesisf_biap"
657 [(set (match_operand 0 "register_operand" "=r,r,x,x")
659 (mult:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
660 (match_operand:SI 2 "const_int_operand" "n,n,n,n"))
661 (match_operand:SI 3 "register_operand" "r,r,r,r"))))
662 (set (match_operand:SI 4 "register_operand" "=*3,r,*3,r")
663 (plus:SI (mult:SI (match_dup 1)
666 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
667 && cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
670 move.%s0 [%4=%3+%1%T2],%0
672 move [%4=%3+%1%T2],%0")
674 ;; move.S1 [rx=ry+i],rz
675 ;; avoiding move.S1 [ry=ry+i],rz
676 ;; and move.S1 [rz=ry+i],rz
677 ;; Note that "i" is allowed to be a register.
679 (define_insn "*mov_side<mode>"
680 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r")
682 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
683 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r"))))
684 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
685 (plus:SI (match_dup 1)
687 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
689 if ((which_alternative == 0 || which_alternative == 3)
690 && (!CONST_INT_P (operands[2])
691 || INTVAL (operands[2]) > 127
692 || INTVAL (operands[2]) < -128
693 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
694 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
696 if (which_alternative == 4)
697 return "move<m> [%3=%2%S1],%0";
698 return "move<m> [%3=%1%S2],%0";
701 (define_insn "*mov_sidesisf"
702 [(set (match_operand 0 "register_operand" "=r,r,r,x,x,x,r,r,x,x")
705 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,r,r,r,R,R,R,R")
706 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r>Rn,r,>Rn,r,r,r,r"))))
707 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*1,r,r,*2,r,*2,r")
708 (plus:SI (match_dup 1)
710 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
711 && cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
713 if ((which_alternative == 0
714 || which_alternative == 3
715 || which_alternative == 6
716 || which_alternative == 8)
717 && (!CONST_INT_P (operands[2])
718 || INTVAL (operands[2]) > 127
719 || INTVAL (operands[2]) < -128
720 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
721 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
723 if (which_alternative < 3)
724 return "move.%s0 [%3=%1%S2],%0";
725 if (which_alternative == 7)
726 return "move.%s0 [%3=%2%S1],%0";
727 if (which_alternative == 9)
728 return "move [%3=%2%S1],%0";
729 return "move [%3=%1%S2],%0";
732 ;; Other way around; move to memory.
734 ;; Note that the condition (which for side-effect patterns is usually a
735 ;; call to cris_side_effect_mode_ok), isn't consulted for register
736 ;; allocation preferences -- constraints is the method for that. The
737 ;; drawback is that we can't exclude register allocation to cause
738 ;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or
739 ;; rx==rz if we use an earlyclobber modifier for the constraint for rx.
740 ;; Instead of that, we recognize and split the cases where dangerous
741 ;; register combinations are spotted: where a register is set in the
742 ;; side-effect, and used in the main insn. We don't handle the case where
743 ;; the set in the main insn overlaps the set in the side-effect; that case
744 ;; must be handled in gcc. We handle just the case where the set in the
745 ;; side-effect overlaps the input operand of the main insn (i.e. just
749 ;; move.s rz,[ry=rx+rw.S]
751 (define_insn "*mov_side<mode>_biap_mem"
752 [(set (mem:BW (plus:SI
753 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
754 (match_operand:SI 1 "const_int_operand" "n,n,n"))
755 (match_operand:SI 2 "register_operand" "r,r,r")))
756 (match_operand:BW 3 "register_operand" "r,r,r"))
757 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
758 (plus:SI (mult:SI (match_dup 0)
761 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
765 move<m> %3,[%4=%2+%0%T1]")
767 (define_insn "*mov_sidesisf_biap_mem"
769 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r,r,r,r")
770 (match_operand:SI 1 "const_int_operand" "n,n,n,n,n,n"))
771 (match_operand:SI 2 "register_operand" "r,r,r,r,r,r")))
772 (match_operand 3 "register_operand" "r,r,r,x,x,x"))
773 (set (match_operand:SI 4 "register_operand" "=*2,!3,r,*2,!3,r")
774 (plus:SI (mult:SI (match_dup 0)
777 "GET_MODE_SIZE (GET_MODE (operands[3])) == UNITS_PER_WORD
778 && cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
782 move.%s3 %3,[%4=%2+%0%T1]
785 move %3,[%4=%2+%0%T1]")
787 ;; Split for the case above where we're out of luck with register
788 ;; allocation (again, the condition isn't checked for that), and we end up
789 ;; with the set in the side-effect getting the same register as the input
794 [(set (match_operator
797 (mult:SI (match_operand:SI 0 "register_operand" "")
798 (match_operand:SI 1 "const_int_operand" ""))
799 (match_operand:SI 2 "register_operand" ""))])
800 (match_operand 3 "register_operand" ""))
801 (set (match_operand:SI 4 "register_operand" "")
802 (plus:SI (mult:SI (match_dup 0)
805 "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])"
806 [(set (match_dup 5) (match_dup 3))
807 (set (match_dup 4) (match_dup 2))
809 (plus:SI (mult:SI (match_dup 0)
813 = replace_equiv_address (operands[6],
814 gen_rtx_PLUS (SImode,
815 gen_rtx_MULT (SImode,
820 ;; move.s rx,[ry=rz+i]
821 ;; FIXME: These could have anonymous mode for operand 2.
825 (define_insn "*mov_side<mode>_mem"
827 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r,R,R,R")
828 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn,r,r,r")))
829 (match_operand:BW 2 "register_operand" "r,r,r,r,r,r,r"))
830 (set (match_operand:SI 3 "register_operand" "=*0,!*2,r,r,*1,!*2,r")
831 (plus:SI (match_dup 0)
833 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
835 if ((which_alternative == 0 || which_alternative == 4)
836 && (!CONST_INT_P (operands[1])
837 || INTVAL (operands[1]) > 127
838 || INTVAL (operands[1]) < -128
839 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
840 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
842 if (which_alternative == 1 || which_alternative == 5)
844 if (which_alternative == 6)
845 return "move.%s2 %2,[%3=%1%S0]";
846 return "move<m> %2,[%3=%0%S1]";
851 (define_insn "*mov_sidesisf_mem"
855 0 "cris_bdap_operand"
856 "%r, r, r,r, r, r,r, R,R, R,R, R")
858 1 "cris_bdap_operand"
859 "r>Rn,r>Rn,r,>Rn,r>Rn,r,>Rn,r,r, r,r, r")))
860 (match_operand 2 "register_operand"
861 "r, r, r,r, x, x,x, r,r, r,x, x"))
862 (set (match_operand:SI 3 "register_operand"
863 "=*0,!2, r,r, *0, r,r, *1,!*2,r,*1,r")
864 (plus:SI (match_dup 0)
866 "GET_MODE_SIZE (GET_MODE (operands[2])) == UNITS_PER_WORD
867 && cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
869 if ((which_alternative == 0 || which_alternative == 4)
870 && (!CONST_INT_P (operands[1])
871 || INTVAL (operands[1]) > 127
872 || INTVAL (operands[1]) < -128
873 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
874 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
876 if (which_alternative == 1
877 || which_alternative == 7
878 || which_alternative == 8
879 || which_alternative == 10)
881 if (which_alternative < 4)
882 return "move.%s2 %2,[%3=%0%S1]";
883 if (which_alternative == 9)
884 return "move.%s2 %2,[%3=%1%S0]";
885 if (which_alternative == 11)
886 return "move %2,[%3=%1%S0]";
887 return "move %2,[%3=%0%S1]";
890 ;; Like the biap case, a split where the set in the side-effect gets the
891 ;; same register as the input register to the main insn, since the
892 ;; condition isn't checked at register allocation.
896 [(set (match_operator
899 (match_operand:SI 0 "cris_bdap_operand" "")
900 (match_operand:SI 1 "cris_bdap_operand" ""))])
901 (match_operand 2 "register_operand" ""))
902 (set (match_operand:SI 3 "register_operand" "")
903 (plus:SI (match_dup 0) (match_dup 1)))])]
904 "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"
905 [(set (match_dup 4) (match_dup 2))
906 (set (match_dup 3) (match_dup 0))
907 (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))]
910 ;; Clear memory side-effect patterns. It is hard to get to the mode if
911 ;; the MEM was anonymous, so there will be one for each mode.
913 ;; clear.[bwd] [ry=rx+rw.s2]
915 (define_insn "*clear_side<mode>_biap"
916 [(set (mem:BWD (plus:SI
917 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
918 (match_operand:SI 1 "const_int_operand" "n,n"))
919 (match_operand:SI 2 "register_operand" "r,r")))
921 (set (match_operand:SI 3 "register_operand" "=*2,r")
922 (plus:SI (mult:SI (match_dup 0)
925 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
928 clear<m> [%3=%2+%0%T1]")
930 ;; clear.[bwd] [ry=rz+i]
932 (define_insn "*clear_side<mode>"
934 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,R,R")
935 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
937 (set (match_operand:SI 2 "register_operand" "=*0,r,r,*1,r")
938 (plus:SI (match_dup 0)
940 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
942 if ((which_alternative == 0 || which_alternative == 3)
943 && (!CONST_INT_P (operands[1])
944 || INTVAL (operands[1]) > 127
945 || INTVAL (operands[1]) < -128
946 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
947 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
949 if (which_alternative == 4)
950 return "clear<m> [%2=%1%S0]";
951 return "clear<m> [%2=%0%S1]";
954 ;; Normal move patterns from SI on.
956 (define_expand "movsi"
958 (match_operand:SI 0 "nonimmediate_operand" "")
959 (match_operand:SI 1 "cris_general_operand_or_symbol" ""))]
962 /* If the output goes to a MEM, make sure we have zero or a register as
964 if (MEM_P (operands[0])
965 && ! REG_S_P (operands[1])
966 && operands[1] != const0_rtx
967 && can_create_pseudo_p ())
968 operands[1] = force_reg (SImode, operands[1]);
970 /* If we're generating PIC and have an incoming symbol, validize it to a
971 general operand or something that will match a special pattern.
973 FIXME: Do we *have* to recognize anything that would normally be a
974 valid symbol? Can we exclude global PIC addresses with an added
977 && CONSTANT_ADDRESS_P (operands[1])
978 && !cris_valid_pic_const (operands[1], false))
980 enum cris_pic_symbol_type t = cris_pic_symbol_type_of (operands[1]);
982 gcc_assert (t != cris_no_symbol);
984 if (! REG_S_P (operands[0]))
986 /* We must have a register as destination for what we're about to
987 do, and for the patterns we generate. */
988 CRIS_ASSERT (can_create_pseudo_p ());
989 operands[1] = force_reg (SImode, operands[1]);
993 /* FIXME: add a REG_EQUAL (or is it REG_EQUIV) note to the
994 destination register for the symbol. It might not be
995 worth it. Measure. */
996 crtl->uses_pic_offset_table = 1;
997 if (t == cris_rel_symbol)
999 /* Change a "move.d sym(+offs),rN" into (allocate register rM)
1001 "move.d (const (plus (unspec [sym]
1002 CRIS_UNSPEC_GOTREL) offs)),rM" "add.d rPIC,rM,rN"
1004 "move.d (const (plus (unspec [sym]
1005 CRIS_UNSPEC_PCREL) offs)),rN". */
1006 rtx tem, rm, rn = operands[0];
1007 rtx sym = GET_CODE (operands[1]) != CONST
1008 ? operands[1] : get_related_value (operands[1]);
1009 HOST_WIDE_INT offs = get_integer_term (operands[1]);
1011 gcc_assert (can_create_pseudo_p ());
1015 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
1018 tem = plus_constant (tem, offs);
1020 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
1024 /* We still uses GOT-relative addressing for
1026 crtl->uses_pic_offset_table = 1;
1027 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
1028 CRIS_UNSPEC_GOTREL);
1030 tem = plus_constant (tem, offs);
1031 rm = gen_reg_rtx (Pmode);
1032 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
1033 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
1034 rn, 0, OPTAB_LIB_WIDEN) != rn)
1035 internal_error ("expand_binop failed in movsi gotrel");
1039 else if (t == cris_got_symbol)
1041 /* Change a "move.d sym,rN" into (allocate register rM, rO)
1042 "move.d (const (unspec [sym] CRIS_UNSPEC_GOTREAD)),rM"
1043 "add.d rPIC,rM,rO", "move.d [rO],rN" with
1044 the memory access marked as read-only. */
1045 rtx tem, mem, rm, ro, rn = operands[0];
1046 gcc_assert (can_create_pseudo_p ());
1047 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
1048 CRIS_UNSPEC_GOTREAD);
1049 rm = gen_reg_rtx (Pmode);
1050 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
1051 ro = gen_reg_rtx (Pmode);
1052 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
1053 ro, 0, OPTAB_LIB_WIDEN) != ro)
1054 internal_error ("expand_binop failed in movsi got");
1055 mem = gen_rtx_MEM (Pmode, ro);
1057 /* This MEM doesn't alias anything. Whether it
1058 aliases other same symbols is unimportant. */
1059 set_mem_alias_set (mem, new_alias_set ());
1060 MEM_NOTRAP_P (mem) = 1;
1062 /* We can set the GOT memory read of a non-called symbol
1063 to readonly, but not that of a call symbol, as those
1064 are subject to lazy evaluation and usually have the value
1065 changed from the first call to the second (but
1066 constant thereafter). */
1067 MEM_READONLY_P (mem) = 1;
1068 emit_move_insn (rn, mem);
1073 /* We get here when we have to change something that would
1074 be recognizable if it wasn't PIC. A ``sym'' is ok for
1075 PIC symbols both with and without a GOT entry. And ``sym
1076 + offset'' is ok for local symbols, so the only thing it
1077 could be, is a global symbol with an offset. Check and
1079 rtx reg = gen_reg_rtx (Pmode);
1080 rtx sym = get_related_value (operands[1]);
1081 HOST_WIDE_INT offs = get_integer_term (operands[1]);
1083 gcc_assert (can_create_pseudo_p ()
1084 && t == cris_got_symbol_needing_fixup
1085 && sym != NULL_RTX && offs != 0);
1087 emit_move_insn (reg, sym);
1088 if (expand_binop (SImode, add_optab, reg,
1089 GEN_INT (offs), operands[0], 0,
1090 OPTAB_LIB_WIDEN) != operands[0])
1091 internal_error ("expand_binop failed in movsi got+offs");
1098 (define_insn "*movsi_got_load"
1099 [(set (reg:SI CRIS_GOT_REGNUM) (unspec:SI [(const_int 0)] CRIS_UNSPEC_GOT))]
1103 ? "lapc _GLOBAL_OFFSET_TABLE_,%:"
1104 : "move.d $pc,%:\;sub.d .:GOTOFF,%:";
1106 [(set_attr "cc" "clobber")])
1108 (define_insn "*movsi_internal"
1110 (match_operand:SI 0 "nonimmediate_operand"
1111 "=r,r, r,Q>,r,Q>,g,r,r, r,g,rQ>,x, m,x")
1112 (match_operand:SI 1 "cris_general_operand_or_pic_source"
1113 "r,Q>,M,M, I,r, M,n,!S,g,r,x, rQ>,x,gi"))]
1114 ;; Note that we prefer not to use the S alternative (if for some reason
1115 ;; it competes with others) above, but g matches S.
1118 /* Better to have c-switch here; it is worth it to optimize the size of
1119 move insns. The alternative would be to try to find more constraint
1120 letters. FIXME: Check again. It seems this could shrink a bit. */
1121 switch (which_alternative)
1127 && (GET_CODE (operands[1]) == SYMBOL_REF
1128 || GET_CODE (operands[1]) == LABEL_REF
1129 || GET_CODE (operands[1]) == CONST))
1131 /* FIXME: Express this through (set_attr cc none) instead,
1132 since we can't express the ``none'' at this point. FIXME:
1133 Use lapc for everything except const_int and when next cc0
1134 user would want the flag setting. */
1136 return "lapc %1,%0";
1139 && GET_CODE (operands[1]) == CONST
1140 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
1141 && XINT (XEXP (operands[1], 0), 1) == CRIS_UNSPEC_GOTREAD)
1142 return "movu.w %1,%0";
1149 return "move.d %1,%0";
1155 return "move %d1,%0";
1160 return "clear.d %0";
1162 /* Constants -32..31 except 0. */
1164 return "moveq %1,%0";
1166 /* We can win a little on constants -32768..-33, 32..65535. */
1168 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536)
1170 if (INTVAL (operands[1]) < 256)
1171 return "movu.b %1,%0";
1172 return "movu.w %1,%0";
1174 else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768)
1176 if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128)
1177 return "movs.b %1,%0";
1178 return "movs.w %1,%0";
1180 return "move.d %1,%0";
1184 rtx tem = operands[1];
1185 gcc_assert (GET_CODE (tem) == CONST);
1186 tem = XEXP (tem, 0);
1187 if (GET_CODE (tem) == PLUS
1188 && GET_CODE (XEXP (tem, 0)) == UNSPEC
1189 && (XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL
1190 || XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_PCREL)
1191 && CONST_INT_P (XEXP (tem, 1)))
1192 tem = XEXP (tem, 0);
1193 gcc_assert (GET_CODE (tem) == UNSPEC);
1194 switch (XINT (tem, 1))
1196 case CRIS_UNSPEC_GOTREAD:
1197 case CRIS_UNSPEC_PLTGOTREAD:
1198 /* Using sign-extend mostly to be consistent with the
1199 indexed addressing mode. */
1201 return "movs.w %1,%0";
1202 return "move.d %1,%0";
1204 case CRIS_UNSPEC_GOTREL:
1205 case CRIS_UNSPEC_PLT_GOTREL:
1206 gcc_assert (!TARGET_V32);
1207 return "move.d %1,%0";
1209 case CRIS_UNSPEC_PCREL:
1210 case CRIS_UNSPEC_PLT_PCREL:
1211 gcc_assert (TARGET_V32);
1212 return "lapc %1,%0";
1219 return "BOGUS: %1 to %0";
1222 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no,yes,yes,no,no")
1223 (set_attr "cc" "*,*,*,*,*,*,*,*,*,*,*,none,none,none,none")])
1225 ;; Extend operations with side-effect from mem to register, using
1226 ;; MOVS/MOVU. These are from mem to register only.
1232 ;; FIXME: Can we omit extend to HImode, since GCC should truncate for
1233 ;; HImode by itself? Perhaps use only anonymous modes?
1235 (define_insn "*ext_sideqihi_biap"
1236 [(set (match_operand:HI 0 "register_operand" "=r,r")
1238 5 "cris_extend_operator"
1240 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1241 (match_operand:SI 2 "const_int_operand" "n,n"))
1242 (match_operand:SI 3 "register_operand" "r,r")))]))
1243 (set (match_operand:SI 4 "register_operand" "=*3,r")
1244 (plus:SI (mult:SI (match_dup 1)
1247 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1250 mov%e5.%m5 [%4=%3+%1%T2],%0")
1252 (define_insn "*ext_side<mode>si_biap"
1253 [(set (match_operand:SI 0 "register_operand" "=r,r")
1255 5 "cris_extend_operator"
1257 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1258 (match_operand:SI 2 "const_int_operand" "n,n"))
1259 (match_operand:SI 3 "register_operand" "r,r")))]))
1260 (set (match_operand:SI 4 "register_operand" "=*3,r")
1261 (plus:SI (mult:SI (match_dup 1)
1264 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1267 mov%e5<m> [%4=%3+%1%T2],%0")
1269 ;; Same but [rx=ry+i]
1273 (define_insn "*ext_sideqihi"
1274 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1276 4 "cris_extend_operator"
1278 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
1279 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1280 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
1281 (plus:SI (match_dup 1)
1283 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1285 if ((which_alternative == 0 || which_alternative == 3)
1286 && (!CONST_INT_P (operands[2])
1287 || INTVAL (operands[2]) > 127
1288 || INTVAL (operands[2]) < -128
1289 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1290 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1292 if (which_alternative == 4)
1293 return "mov%e4.%m4 [%3=%2%S1],%0";
1294 return "mov%e4.%m4 [%3=%1%S2],%0";
1297 (define_insn "*ext_side<mode>si"
1298 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
1300 4 "cris_extend_operator"
1302 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
1303 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1304 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
1305 (plus:SI (match_dup 1)
1307 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1309 if ((which_alternative == 0 || which_alternative == 3)
1310 && (!CONST_INT_P (operands[2])
1311 || INTVAL (operands[2]) > 127
1312 || INTVAL (operands[2]) < -128
1313 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1314 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1316 if (which_alternative == 4)
1317 return "mov%e4<m> [%3=%2%S1],%0";
1318 return "mov%e4<m> [%3=%1%S2],%0";
1321 ;; FIXME: See movsi.
1323 (define_insn "movhi"
1325 (match_operand:HI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,r,r,r,g,g,r,r,x")
1326 (match_operand:HI 1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g,x,r"))]
1329 switch (which_alternative)
1336 return "move.w %1,%0";
1339 return "move %1,%0";
1343 return "clear.w %0";
1345 return "moveq %1,%0";
1348 if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128)
1350 if (INTVAL (operands[1]) > 0)
1351 return "movu.b %1,%0";
1352 return "movs.b %1,%0";
1354 return "move.w %1,%0";
1356 return "movEq %b1,%0";
1358 return "BOGUS: %1 to %0";
1361 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no,yes,yes")
1362 (set_attr "cc" "*,*,none,none,*,none,*,clobber,*,none,none,*,none,none")])
1364 (define_insn "movstricthi"
1367 (match_operand:HI 0 "nonimmediate_operand" "+r,r, r,Q>,Q>,g,r,g"))
1368 (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, M,g,r"))]
1379 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1381 (define_expand "reload_in<mode>"
1382 [(set (match_operand:BW 2 "register_operand" "=r")
1383 (match_operand:BW 1 "memory_operand" "m"))
1384 (set (match_operand:BW 0 "register_operand" "=x")
1389 (define_expand "reload_out<mode>"
1390 [(set (match_operand:BW 2 "register_operand" "=&r")
1391 (match_operand:BW 1 "register_operand" "x"))
1392 (set (match_operand:BW 0 "memory_operand" "=m")
1397 (define_insn "movqi"
1398 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,r,g,g,r,r,r,x")
1399 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, I,M,r,O,g,x,r"))]
1414 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no,yes,yes")
1415 (set_attr "cc" "*,*,*,*,*,*,*,*,clobber,*,none,none")])
1417 (define_insn "movstrictqi"
1418 [(set (strict_low_part
1419 (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r, r,Q>,g,g,r"))
1420 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, M,r,g"))]
1431 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1433 ;; The valid "quick" bit-patterns are, except for 0.0, denormalized
1434 ;; values REALLY close to 0, and some NaN:s (I think; their exponent is
1435 ;; all ones); the worthwhile one is "0.0".
1436 ;; It will use clear, so we know ALL types of immediate 0 never change cc.
1438 (define_insn "movsf"
1439 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,g,g,r,r,x,Q>,m,x, x")
1440 (match_operand:SF 1 "general_operand" "r,r, Q>,G,G, G,r,g,x,r,x, x,Q>,g"))]
1457 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no,yes,yes,yes,no,yes,no")])
1459 ;; Movem patterns. Primarily for use in function prologue and epilogue.
1460 ;; The V32 variants have an ordering matching the expectations of the
1461 ;; standard names "load_multiple" and "store_multiple"; pre-v32 movem
1462 ;; store R0 in the highest memory location.
1464 (define_expand "load_multiple"
1465 [(match_operand:SI 0 "register_operand" "")
1466 (match_operand:SI 1 "memory_operand" "")
1467 (match_operand:SI 2 "const_int_operand" "")]
1472 /* Apparently the predicate isn't checked, so we need to do so
1473 manually. Once happened for libstdc++-v3 locale_facets.tcc. */
1474 if (!MEM_P (operands[1]))
1477 indreg = XEXP (operands[1], 0);
1479 if (GET_CODE (indreg) == POST_INC)
1480 indreg = XEXP (indreg, 0);
1482 || GET_CODE (operands[2]) != CONST_INT
1483 || !REG_P (operands[0])
1484 || REGNO (operands[0]) != 0
1485 || INTVAL (operands[2]) > CRIS_SP_REGNUM
1486 || (int) REGNO (indreg) < INTVAL (operands[2]))
1489 emit_insn (cris_gen_movem_load (operands[1], operands[2], 0));
1493 (define_expand "store_multiple"
1494 [(match_operand:SI 0 "memory_operand" "")
1495 (match_operand:SI 1 "register_operand" "")
1496 (match_operand:SI 2 "const_int_operand" "")]
1501 /* See load_multiple. */
1502 if (!MEM_P (operands[0]))
1505 indreg = XEXP (operands[0], 0);
1507 if (GET_CODE (indreg) == POST_INC)
1508 indreg = XEXP (indreg, 0);
1510 || GET_CODE (operands[2]) != CONST_INT
1511 || !REG_P (operands[1])
1512 || REGNO (operands[1]) != 0
1513 || INTVAL (operands[2]) > CRIS_SP_REGNUM
1514 || (int) REGNO (indreg) < INTVAL (operands[2]))
1517 cris_emit_movem_store (operands[0], operands[2], 0, false);
1521 (define_insn "*cris_load_multiple"
1522 [(match_parallel 0 "cris_load_multiple_op"
1523 [(set (match_operand:SI 1 "register_operand" "=r,r")
1524 (match_operand:SI 2 "memory_operand" "Q,m"))])]
1527 [(set_attr "cc" "none")
1528 (set_attr "slottable" "yes,no")
1529 ;; Not true, but setting the length to 0 causes return sequences (ret
1530 ;; movem) to have the cost they had when (return) included the movem
1531 ;; and reduces the performance penalty taken for needing to emit an
1532 ;; epilogue (in turn copied by bb-reorder) instead of return patterns.
1533 ;; FIXME: temporary change until all insn lengths are correctly
1534 ;; described. FIXME: have better target control over bb-reorder.
1535 (set_attr "length" "0")])
1537 (define_insn "*cris_store_multiple"
1538 [(match_parallel 0 "cris_store_multiple_op"
1539 [(set (match_operand:SI 2 "memory_operand" "=Q,m")
1540 (match_operand:SI 1 "register_operand" "r,r"))])]
1543 [(set_attr "cc" "none")
1544 (set_attr "slottable" "yes,no")])
1547 ;; Sign- and zero-extend insns with standard names.
1548 ;; Those for integer source operand are ordered with the widest source
1553 (define_insn "extendsidi2"
1554 [(set (match_operand:DI 0 "register_operand" "=r")
1555 (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
1557 "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0")
1559 (define_insn "extend<mode>di2"
1560 [(set (match_operand:DI 0 "register_operand" "=r")
1561 (sign_extend:DI (match_operand:BW 1 "general_operand" "g")))]
1563 "movs<m> %1,%M0\;smi %H0\;neg.d %H0,%H0")
1565 (define_insn "extend<mode>si2"
1566 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1567 (sign_extend:SI (match_operand:BW 1 "general_operand" "r,Q>,g")))]
1570 [(set_attr "slottable" "yes,yes,no")])
1572 ;; To do a byte->word extension, extend to dword, exept that the top half
1573 ;; of the register will be clobbered. FIXME: Perhaps this is not needed.
1575 (define_insn "extendqihi2"
1576 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1577 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))]
1580 [(set_attr "slottable" "yes,yes,no")])
1583 ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't
1584 ;; specify them here.
1586 (define_insn "zero_extend<mode>si2"
1587 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1589 (match_operand:BW 1 "nonimmediate_operand" "r,Q>,m")))]
1592 [(set_attr "slottable" "yes,yes,no")])
1594 ;; Same comment as sign-extend QImode to HImode above applies.
1596 (define_insn "zero_extendqihi2"
1597 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1599 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))]
1602 [(set_attr "slottable" "yes,yes,no")])
1604 ;; All kinds of arithmetic and logical instructions.
1606 ;; First, anonymous patterns to match addressing modes with
1609 ;; op.S [rx=ry+I],rz; (add, sub, or, and, bound).
1613 (define_insn "*op_side<mode>_biap"
1614 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1616 6 "cris_orthogonal_operator"
1617 [(match_operand:BWD 1 "register_operand" "0,0")
1619 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1620 (match_operand:SI 3 "const_int_operand" "n,n"))
1621 (match_operand:SI 4 "register_operand" "r,r")))]))
1622 (set (match_operand:SI 5 "register_operand" "=*4,r")
1623 (plus:SI (mult:SI (match_dup 2)
1626 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1629 %x6<m> [%5=%4+%2%T3],%0")
1631 ;; [rx=ry+i] ([%4=%2+%3])
1633 (define_insn "*op_side<mode>"
1634 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r")
1636 5 "cris_orthogonal_operator"
1637 [(match_operand:BWD 1 "register_operand" "0,0,0,0,0")
1639 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1640 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1641 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1642 (plus:SI (match_dup 2)
1644 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1646 if ((which_alternative == 0 || which_alternative == 3)
1647 && (!CONST_INT_P (operands[3])
1648 || INTVAL (operands[3]) > 127
1649 || INTVAL (operands[3]) < -128
1650 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1651 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1653 if (which_alternative == 4)
1654 return "%x5.%s0 [%4=%3%S2],%0";
1655 return "%x5<m> [%4=%2%S3],%0";
1658 ;; To match all cases for commutative operations we may have to have the
1659 ;; following pattern for add, or & and. I do not know really, but it does
1660 ;; not break anything.
1662 ;; FIXME: This really ought to be checked.
1664 ;; op.S [rx=ry+I],rz;
1668 (define_insn "*op_swap_side<mode>_biap"
1669 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1671 6 "cris_commutative_orth_op"
1673 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1674 (match_operand:SI 3 "const_int_operand" "n,n"))
1675 (match_operand:SI 4 "register_operand" "r,r")))
1676 (match_operand:BWD 1 "register_operand" "0,0")]))
1677 (set (match_operand:SI 5 "register_operand" "=*4,r")
1678 (plus:SI (mult:SI (match_dup 2)
1681 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1684 %x6<m> [%5=%4+%2%T3],%0")
1686 ;; [rx=ry+i] ([%4=%2+%3])
1687 ;; FIXME: These could have anonymous mode for operand 0.
1691 (define_insn "*op_swap_side<mode>"
1692 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r")
1694 5 "cris_commutative_orth_op"
1696 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1697 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
1698 (match_operand:BWD 1 "register_operand" "0,0,0,0,0")]))
1699 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1700 (plus:SI (match_dup 2)
1702 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1704 if ((which_alternative == 0 || which_alternative == 3)
1705 && (!CONST_INT_P (operands[3])
1706 || INTVAL (operands[3]) > 127
1707 || INTVAL (operands[3]) < -128
1708 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1709 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1711 if (which_alternative == 4)
1712 return "%x5<m> [%4=%3%S2],%0";
1713 return "%x5<m> [%4=%2%S3],%0";
1716 ;; Add operations, standard names.
1718 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1719 ;; output the insn through the 'A' output modifier as "adds.w" and "addq",
1721 (define_expand "adddi3"
1722 [(set (match_operand:DI 0 "register_operand")
1723 (plus:DI (match_operand:DI 1 "register_operand")
1724 (match_operand:DI 2 "general_operand")))]
1727 if (MEM_P (operands[2]) && TARGET_V32)
1728 operands[2] = force_reg (DImode, operands[2]);
1731 (define_insn "*adddi3_non_v32"
1732 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1733 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r")
1734 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1737 addq %2,%M0\;ax\;addq 0,%H0
1738 subq %n2,%M0\;ax\;subq 0,%H0
1739 add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0
1740 add.d %M2,%M0\;ax\;add.d %H2,%H0
1741 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
1743 ; It seems no use allowing a memory operand for this one, because we'd
1744 ; need a scratch register for incrementing the address.
1745 (define_insn "*adddi3_v32"
1746 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1747 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0")
1748 (match_operand:DI 2 "nonmemory_operand" "J,N,P,r,n")))]
1751 addq %2,%M0\;addc 0,%H0
1752 subq %n2,%M0\;ax\;subq 0,%H0
1753 add%e2.%z2 %2,%M0\;addc %H2,%H0
1754 add.d %M2,%M0\;addc %H2,%H0
1755 add.d %M2,%M0\;addc %H2,%H0")
1757 (define_expand "add<mode>3"
1758 [(set (match_operand:BWD 0 "register_operand")
1760 (match_operand:BWD 1 "register_operand")
1761 (match_operand:BWD 2 "general_operand")))]
1765 (define_insn "*addsi3_non_v32"
1766 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r, r,r, r")
1768 (match_operand:SI 1 "register_operand" "%0,0, 0,0,0,0, 0,r, r")
1769 (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,!S,g,!To,0")))]
1771 ;; The last constraint is due to that after reload, the '%' is not
1772 ;; honored, and canonicalization doesn't care about keeping the same
1773 ;; register as in destination. This will happen after insn splitting.
1774 ;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x
1778 switch (which_alternative)
1782 return "add.d %2,%0";
1784 return "addq %2,%0";
1786 return "subq %n2,%0";
1788 /* 'Known value', but not in -63..63.
1789 Check if addu/subu may be used. */
1790 if (INTVAL (operands[2]) > 0)
1792 if (INTVAL (operands[2]) < 256)
1793 return "addu.b %2,%0";
1794 if (INTVAL (operands[2]) < 65536)
1795 return "addu.w %2,%0";
1799 if (INTVAL (operands[2]) >= -255)
1800 return "subu.b %n2,%0";
1801 if (INTVAL (operands[2]) >= -65535)
1802 return "subu.w %n2,%0";
1804 return "add.d %2,%0";
1807 rtx tem = operands[2];
1808 gcc_assert (GET_CODE (tem) == CONST);
1809 tem = XEXP (tem, 0);
1810 if (GET_CODE (tem) == PLUS
1811 && GET_CODE (XEXP (tem, 0)) == UNSPEC
1812 /* We don't allow CRIS_UNSPEC_PCREL here; we can't have a
1813 pc-relative operand in an add insn. */
1814 && XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL
1815 && CONST_INT_P (XEXP (tem, 1)))
1816 tem = XEXP (tem, 0);
1817 gcc_assert (GET_CODE (tem) == UNSPEC);
1818 switch (XINT (tem, 1))
1820 case CRIS_UNSPEC_GOTREAD:
1821 case CRIS_UNSPEC_PLTGOTREAD:
1822 /* Using sign-extend mostly to be consistent with the
1823 indexed addressing mode. */
1825 return "adds.w %2,%0";
1826 return "add.d %2,%0";
1828 case CRIS_UNSPEC_PLT_GOTREL:
1829 case CRIS_UNSPEC_GOTREL:
1830 return "add.d %2,%0";
1836 return "add%u2 %2,%0";
1838 return "add.d %2,%1,%0";
1840 return "add.d %1,%0";
1842 return "BOGUS addsi %2+%1 to %0";
1845 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no,yes")])
1847 ; FIXME: Check what's best: having the three-operand ACR alternative
1848 ; before or after the corresponding-operand2 alternative. Check for
1849 ; *all* insns. FIXME: constant constraint letter for -128..127.
1850 (define_insn "*addsi3_v32"
1851 [(set (match_operand:SI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,!a,r,r,r,!a")
1853 (match_operand:SI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r, 0,0,0,r")
1854 (match_operand:SI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,L,L, P,n,g,g")))]
1870 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no,no,no,no,no")
1871 (set_attr "cc" "*,none,*,none,*,*,none,*,*,*,*,*,none")])
1873 (define_insn "*addhi3_non_v32"
1874 [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r")
1875 (plus:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
1876 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1885 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1886 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1888 (define_insn "*addhi3_v32"
1889 [(set (match_operand:HI 0 "register_operand" "=r, !a,r,!a, r,r,!a,r,!a")
1891 (match_operand:HI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r")
1892 (match_operand:HI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,g,g")))]
1904 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no")
1905 (set_attr "cc" "*,none,*,none,clobber,clobber,none,*,none")])
1907 (define_insn "*addqi3_non_v32"
1908 [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r,r")
1909 (plus:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,0,0,r")
1910 (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))]
1920 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
1921 (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")])
1923 (define_insn "*addqi3_v32"
1924 [(set (match_operand:QI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,r,!a")
1926 (match_operand:QI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,0,r")
1927 (match_operand:QI 2 "general_operand" "r,r, Q>,Q>,J,N,NJ,O,g,g")))]
1940 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,yes,no,no")
1941 (set_attr "cc" "*,none,*,none,clobber,clobber,none,clobber,*,none")])
1945 ;; Note that because of insn canonicalization these will *seldom* but
1946 ;; rarely be used with a known constant as an operand.
1948 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1949 ;; output the insn through the 'D' output modifier as "subs.w" and "subq",
1951 (define_expand "subdi3"
1952 [(set (match_operand:DI 0 "register_operand")
1953 (minus:DI (match_operand:DI 1 "register_operand")
1954 (match_operand:DI 2 "general_operand")))]
1957 if (TARGET_V32 && MEM_P (operands[2]))
1958 operands[2] = force_reg (DImode, operands[2]);
1961 (define_insn "*subdi3_non_v32"
1962 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1963 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r")
1964 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1967 subq %2,%M0\;ax\;subq 0,%H0
1968 addq %n2,%M0\;ax\;addq 0,%H0
1969 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1970 sub.d %M2,%M0\;ax\;sub.d %H2,%H0
1971 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
1973 (define_insn "*subdi3_v32"
1974 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r")
1975 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0")
1976 (match_operand:DI 2 "nonmemory_operand" "J,N,P,r")))]
1979 subq %2,%M0\;ax\;subq 0,%H0
1980 addq %n2,%M0\;ax\;addq 0,%H0
1981 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1982 sub.d %M2,%M0\;ax\;sub.d %H2,%H0")
1984 (define_expand "sub<mode>3"
1985 [(set (match_operand:BWD 0 "register_operand")
1987 (match_operand:BWD 1 "register_operand")
1988 (match_operand:BWD 2 "general_operand")))]
1992 (define_insn "*subsi3_non_v32"
1993 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r,r")
1995 (match_operand:SI 1 "register_operand" "0,0, 0,0,0,0,0,r")
1996 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
1999 ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
2000 ;; But then again, %2 should not be negative.
2011 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
2013 (define_insn "*subsi3_v32"
2014 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
2016 (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0")
2017 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g")))]
2027 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")])
2029 (define_insn "*sub<mode>3_nonv32"
2030 [(set (match_operand:BW 0 "register_operand" "=r,r, r,r,r,r")
2031 (minus:BW (match_operand:BW 1 "register_operand" "0,0, 0,0,0,r")
2032 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g,!To")))]
2041 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2042 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
2044 (define_insn "*sub<mode>3_v32"
2045 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r")
2046 (minus:BW (match_operand:BW 1 "register_operand" "0,0,0,0,0")
2047 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g")))]
2055 [(set_attr "slottable" "yes,yes,yes,yes,no")
2056 (set_attr "cc" "normal,normal,clobber,clobber,normal")])
2058 ;; CRIS has some add/sub-with-sign/zero-extend instructions.
2059 ;; Although these perform sign/zero-extension to SImode, they are
2060 ;; equally applicable for the HImode case.
2061 ;; FIXME: Check; GCC should handle the widening.
2062 ;; Note that these must be located after the normal add/sub patterns,
2063 ;; so not to get constants into any less specific operands.
2065 ;; Extend with add/sub and side-effect.
2067 ;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend
2069 ;; adds/subs/addu/subu bound [rx=ry+rz.S]
2072 ;; FIXME: GCC should widen.
2074 (define_insn "*extopqihi_side_biap"
2075 [(set (match_operand:HI 0 "register_operand" "=r,r")
2077 6 "cris_additive_operand_extend_operator"
2078 [(match_operand:HI 1 "register_operand" "0,0")
2080 7 "cris_extend_operator"
2082 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2083 (match_operand:SI 3 "const_int_operand" "n,n"))
2084 (match_operand:SI 4 "register_operand" "r,r")))])]))
2085 (set (match_operand:SI 5 "register_operand" "=*4,r")
2086 (plus:SI (mult:SI (match_dup 2)
2089 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2092 %x6%e7.%m7 [%5=%4+%2%T3],%0")
2094 (define_insn "*extop<mode>si_side_biap"
2095 [(set (match_operand:SI 0 "register_operand" "=r,r")
2097 6 "cris_operand_extend_operator"
2098 [(match_operand:SI 1 "register_operand" "0,0")
2100 7 "cris_extend_operator"
2102 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2103 (match_operand:SI 3 "const_int_operand" "n,n"))
2104 (match_operand:SI 4 "register_operand" "r,r")))])]))
2105 (set (match_operand:SI 5 "register_operand" "=*4,r")
2106 (plus:SI (mult:SI (match_dup 2)
2109 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
2110 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2113 %x6%e7<m> [%5=%4+%2%T3],%0")
2120 (define_insn "*extopqihi_side"
2121 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
2123 5 "cris_additive_operand_extend_operator"
2124 [(match_operand:HI 1 "register_operand" "0,0,0,0,0")
2126 6 "cris_extend_operator"
2128 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2129 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
2131 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2132 (plus:SI (match_dup 2)
2134 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2136 if ((which_alternative == 0 || which_alternative == 3)
2137 && (!CONST_INT_P (operands[3])
2138 || INTVAL (operands[3]) > 127
2139 || INTVAL (operands[3]) < -128
2140 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2141 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2143 if (which_alternative == 4)
2144 return "%x5%E6.%m6 [%4=%3%S2],%0";
2145 return "%x5%E6.%m6 [%4=%2%S3],%0";
2148 (define_insn "*extop<mode>si_side"
2149 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
2151 5 "cris_operand_extend_operator"
2152 [(match_operand:SI 1 "register_operand" "0,0,0,0,0")
2154 6 "cris_extend_operator"
2156 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2157 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
2159 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2160 (plus:SI (match_dup 2)
2162 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2163 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2165 if ((which_alternative == 0 || which_alternative == 3)
2166 && (!CONST_INT_P (operands[3])
2167 || INTVAL (operands[3]) > 127
2168 || INTVAL (operands[3]) < -128
2169 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2170 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2172 if (which_alternative == 4)
2173 return "%x5%E6<m> [%4=%3%S2],%0";
2174 return "%x5%E6<m> [%4=%2%S3],%0";
2178 ;; As with op.S we may have to add special pattern to match commuted
2179 ;; operands to adds/addu and bound
2181 ;; adds/addu/bound [rx=ry+rz.S]
2184 ;; FIXME: GCC should widen.
2186 (define_insn "*extopqihi_swap_side_biap"
2187 [(set (match_operand:HI 0 "register_operand" "=r,r")
2190 6 "cris_extend_operator"
2192 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2193 (match_operand:SI 3 "const_int_operand" "n,n"))
2194 (match_operand:SI 4 "register_operand" "r,r")))])
2195 (match_operand:HI 1 "register_operand" "0,0")))
2196 (set (match_operand:SI 5 "register_operand" "=*4,r")
2197 (plus:SI (mult:SI (match_dup 2)
2200 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2203 add%e6.b [%5=%4+%2%T3],%0")
2205 (define_insn "*extop<mode>si_swap_side_biap"
2206 [(set (match_operand:SI 0 "register_operand" "=r,r")
2208 7 "cris_plus_or_bound_operator"
2210 6 "cris_extend_operator"
2212 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2213 (match_operand:SI 3 "const_int_operand" "n,n"))
2214 (match_operand:SI 4 "register_operand" "r,r")))])
2215 (match_operand:SI 1 "register_operand" "0,0")]))
2216 (set (match_operand:SI 5 "register_operand" "=*4,r")
2217 (plus:SI (mult:SI (match_dup 2)
2220 "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2221 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2224 %x7%E6<m> [%5=%4+%2%T3],%0")
2227 ;; FIXME: GCC should widen.
2231 (define_insn "*extopqihi_swap_side"
2232 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
2235 5 "cris_extend_operator"
2237 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2238 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
2239 (match_operand:HI 1 "register_operand" "0,0,0,0,0")))
2240 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2241 (plus:SI (match_dup 2)
2243 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2245 if ((which_alternative == 0 || which_alternative == 3)
2246 && (!CONST_INT_P (operands[3])
2247 || INTVAL (operands[3]) > 127
2248 || INTVAL (operands[3]) < -128
2249 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2250 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2252 if (which_alternative == 4)
2253 return "add%e5.b [%4=%3%S2],%0";
2254 return "add%e5.b [%4=%2%S3],%0";
2257 (define_insn "*extop<mode>si_swap_side"
2258 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
2260 6 "cris_plus_or_bound_operator"
2262 5 "cris_extend_operator"
2264 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2265 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
2266 (match_operand:SI 1 "register_operand" "0,0,0,0,0")]))
2267 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2268 (plus:SI (match_dup 2)
2270 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
2271 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2273 if ((which_alternative == 0 || which_alternative == 3)
2274 && (!CONST_INT_P (operands[3])
2275 || INTVAL (operands[3]) > 127
2276 || INTVAL (operands[3]) < -128
2277 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2278 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2280 if (which_alternative == 4)
2281 return \"%x6%E5.%m5 [%4=%3%S2],%0\";
2282 return "%x6%E5<m> [%4=%2%S3],%0";
2285 ;; Extend versions (zero/sign) of normal add/sub (no side-effects).
2288 ;; FIXME: GCC should widen.
2290 (define_insn "*extopqihi_non_v32"
2291 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2293 3 "cris_additive_operand_extend_operator"
2294 [(match_operand:HI 1 "register_operand" "0,0,0,r")
2296 4 "cris_extend_operator"
2297 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2298 "!TARGET_V32 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2299 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2304 %x3%E4.%m4 %2,%1,%0"
2305 [(set_attr "slottable" "yes,yes,no,no")
2306 (set_attr "cc" "clobber")])
2308 (define_insn "*extopqihi_v32"
2309 [(set (match_operand:HI 0 "register_operand" "=r,r")
2311 3 "cris_additive_operand_extend_operator"
2312 [(match_operand:HI 1 "register_operand" "0,0")
2314 4 "cris_extend_operator"
2315 [(match_operand:QI 2 "nonimmediate_operand" "r,m")])]))]
2318 [(set_attr "slottable" "yes")
2319 (set_attr "cc" "clobber")])
2323 (define_insn "*extop<mode>si_non_v32"
2324 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2326 3 "cris_operand_extend_operator"
2327 [(match_operand:SI 1 "register_operand" "0,0,0,r")
2329 4 "cris_extend_operator"
2330 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2332 && (GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2333 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2334 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2340 [(set_attr "slottable" "yes,yes,no,no")])
2342 (define_insn "*extop<mode>si_v32"
2343 [(set (match_operand:SI 0 "register_operand" "=r,r")
2345 3 "cris_additive_operand_extend_operator"
2346 [(match_operand:SI 1 "register_operand" "0,0")
2348 4 "cris_extend_operator"
2349 [(match_operand:BW 2 "nonimmediate_operand" "r,m")])]))]
2352 [(set_attr "slottable" "yes")])
2354 ;; As with the side-effect patterns, may have to have swapped operands for add.
2355 ;; For commutative operands, these are the canonical forms.
2359 (define_insn "*addxqihi_swap_non_v32"
2360 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2363 3 "cris_extend_operator"
2364 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2365 (match_operand:HI 1 "register_operand" "0,0,0,r")))]
2366 "!TARGET_V32 && operands[1] != frame_pointer_rtx"
2372 [(set_attr "slottable" "yes,yes,no,no")
2373 (set_attr "cc" "clobber")])
2375 ;; A case for v32, to catch the "addo" insn in addition to "adds". We
2376 ;; only care to match the canonical form; there should be no other.
2378 (define_insn "*addsbw_v32"
2379 [(set (match_operand:HI 0 "register_operand" "=r,r,!a")
2382 (match_operand:QI 2 "nonimmediate_operand" "r,m,m"))
2383 (match_operand:HI 1 "register_operand" "0,0,r")))]
2389 [(set_attr "slottable" "yes")
2390 (set_attr "cc" "clobber,clobber,none")])
2392 (define_insn "*addubw_v32"
2393 [(set (match_operand:HI 0 "register_operand" "=r,r")
2396 (match_operand:QI 2 "nonimmediate_operand" "r,m"))
2397 (match_operand:HI 1 "register_operand" "0,0")))]
2400 [(set_attr "slottable" "yes")
2401 (set_attr "cc" "clobber")])
2403 (define_insn "*extop<mode>si_swap_non_v32"
2404 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2406 4 "cris_plus_or_bound_operator"
2408 3 "cris_extend_operator"
2409 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])
2410 (match_operand:SI 1 "register_operand" "0,0,0,r")]))]
2412 && (GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND)
2413 && operands[1] != frame_pointer_rtx"
2419 [(set_attr "slottable" "yes,yes,no,no")])
2421 (define_insn "*adds<mode>_v32"
2422 [(set (match_operand:SI 0 "register_operand" "=r,r,!a")
2425 (match_operand:BW 2 "nonimmediate_operand" "r,m,m"))
2426 (match_operand:SI 1 "register_operand" "0,0,r")))]
2432 [(set_attr "slottable" "yes")
2433 (set_attr "cc" "*,*,none")])
2435 (define_insn "*addu<mode>_v32"
2436 [(set (match_operand:SI 0 "register_operand" "=r,r")
2439 (match_operand:BW 2 "nonimmediate_operand" "r,m"))
2440 (match_operand:SI 1 "register_operand" "0,0")))]
2441 "TARGET_V32 && operands[1] != frame_pointer_rtx"
2443 [(set_attr "slottable" "yes")])
2445 (define_insn "*bound<mode>_v32"
2446 [(set (match_operand:SI 0 "register_operand" "=r")
2449 (match_operand:BW 2 "register_operand" "r"))
2450 (match_operand:SI 1 "register_operand" "0")))]
2451 "TARGET_V32 && operands[1] != frame_pointer_rtx"
2453 [(set_attr "slottable" "yes")])
2455 ;; This is the special case when we use what corresponds to the
2456 ;; instruction above in "casesi". Do *not* change it to use the generic
2457 ;; pattern and "REG 15" as pc; I did that and it led to madness and
2458 ;; maintenance problems: Instead of (as imagined) recognizing and removing
2459 ;; or replacing this pattern with something simpler, other variant
2460 ;; patterns were recognized or combined, including some prefix variants
2461 ;; where the value in pc is not that of the next instruction (which means
2462 ;; this instruction actually *is* special and *should* be marked as such).
2463 ;; When switching from the "generic pattern match" approach to this simpler
2464 ;; approach, there were insignificant differences in gcc, ipps and
2465 ;; product code, somehow due to scratching reload behind the ear or
2466 ;; something. Testcase "gcc" looked .01% slower and 4 bytes bigger;
2467 ;; product code became .001% smaller but "looked better". The testcase
2468 ;; "ipps" was just different at register allocation).
2470 ;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this
2471 ;; pattern with the default-label as the else, with the "if" being
2472 ;; index-is-less-than the max number of cases plus one. The default-label
2473 ;; is attached to the end of the case-table at time of output.
2475 (define_insn "*casesi_adds_w"
2478 (ltu (match_operand:SI 0 "register_operand" "r")
2479 (match_operand:SI 1 "const_int_operand" "n"))
2480 (plus:SI (sign_extend:SI
2482 (plus:SI (mult:SI (match_dup 0) (const_int 2))
2485 (label_ref (match_operand 2 "" ""))))
2486 (use (label_ref (match_operand 3 "" "")))]
2487 "!TARGET_V32 && operands[0] != frame_pointer_rtx"
2488 "adds.w [$pc+%0.w],$pc"
2489 [(set_attr "cc" "clobber")])
2491 ;; For V32, we just have a jump, but we need to mark the table as used,
2492 ;; and the jump insn must have the if_then_else form expected by core
2493 ;; GCC. Since we don't want to prolong the lifetime of the original
2494 ;; index value, we compare against "unspec 0". It's a pity we have to
2495 ;; jump through to get the default label in place and to keep the jump
2496 ;; table around. FIXME: Look into it some time.
2498 (define_insn "*casesi_jump_v32"
2501 (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI)
2502 (match_operand:SI 0 "const_int_operand" "n"))
2503 (match_operand:SI 1 "register_operand" "r")
2504 (label_ref (match_operand 2 "" ""))))
2505 (use (label_ref (match_operand 3 "" "")))]
2508 [(set_attr "cc" "clobber")
2509 (set_attr "slottable" "has_slot")])
2511 ;; Multiply instructions.
2513 ;; Sometimes powers of 2 (which are normally canonicalized to a
2514 ;; left-shift) appear here, as a result of address reloading.
2515 ;; As a special, for values 3 and 5, we can match with an addi, so add those.
2517 ;; FIXME: This may be unnecessary now.
2518 ;; Explicitly named for convenience of having a gen_... function.
2520 (define_insn "addi_mul"
2521 [(set (match_operand:SI 0 "register_operand" "=r")
2523 (match_operand:SI 1 "register_operand" "%0")
2524 (match_operand:SI 2 "const_int_operand" "n")))]
2525 "operands[0] != frame_pointer_rtx
2526 && operands[1] != frame_pointer_rtx
2527 && CONST_INT_P (operands[2])
2528 && (INTVAL (operands[2]) == 2
2529 || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3
2530 || INTVAL (operands[2]) == 5)"
2532 if (INTVAL (operands[2]) == 2)
2534 else if (INTVAL (operands[2]) == 4)
2536 else if (INTVAL (operands[2]) == 3)
2537 return "addi %0.w,%0";
2538 else if (INTVAL (operands[2]) == 5)
2539 return "addi %0.d,%0";
2540 return "BAD: adr_mulsi: %0=%1*%2";
2542 [(set_attr "slottable" "yes")
2543 ;; No flags are changed if this insn is "addi", but it does not seem
2544 ;; worth the trouble to distinguish that to the lslq cases.
2545 (set_attr "cc" "clobber")])
2547 ;; The addi insn as it is normally used.
2549 ;; Make the the ACR alternative taste bad enough to not choose it as a
2550 ;; preference to avoid spilling problems (unwind-dw2-fde.c at build).
2551 ;; FIXME: Revisit for new register allocator.
2553 (define_insn "*addi"
2554 [(set (match_operand:SI 0 "register_operand" "=r,!a")
2556 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2557 (match_operand:SI 3 "const_int_operand" "n,n"))
2558 (match_operand:SI 1 "register_operand" "0,r")))]
2559 "operands[0] != frame_pointer_rtx
2560 && operands[1] != frame_pointer_rtx
2561 && CONST_INT_P (operands[3])
2562 && (INTVAL (operands[3]) == 1
2563 || INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)"
2567 [(set_attr "slottable" "yes")
2568 (set_attr "cc" "none")])
2570 ;; The mstep instruction. Probably not useful by itself; it's to
2571 ;; non-linear wrt. the other insns. We used to expand to it, so at least
2574 (define_insn "mstep_shift"
2575 [(set (match_operand:SI 0 "register_operand" "=r")
2577 (lt:SI (cc0) (const_int 0))
2578 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2580 (match_operand:SI 2 "register_operand" "r"))
2581 (ashift:SI (match_operand:SI 3 "register_operand" "0")
2585 [(set_attr "slottable" "yes")])
2587 ;; When illegitimate addresses are legitimized, sometimes gcc forgets
2588 ;; to canonicalize the multiplications.
2590 ;; FIXME: Check gcc > 2.7.2, remove and possibly fix in gcc.
2592 (define_insn "mstep_mul"
2593 [(set (match_operand:SI 0 "register_operand" "=r")
2595 (lt:SI (cc0) (const_int 0))
2596 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2598 (match_operand:SI 2 "register_operand" "r"))
2599 (mult:SI (match_operand:SI 3 "register_operand" "0")
2602 && operands[0] != frame_pointer_rtx
2603 && operands[1] != frame_pointer_rtx
2604 && operands[2] != frame_pointer_rtx
2605 && operands[3] != frame_pointer_rtx"
2607 [(set_attr "slottable" "yes")])
2609 (define_insn "<u>mul<s><mode>3"
2610 [(set (match_operand:WD 0 "register_operand" "=r")
2612 (szext:WD (match_operand:<S> 1 "register_operand" "%0"))
2613 (szext:WD (match_operand:<S> 2 "register_operand" "r"))))
2614 (clobber (match_scratch:SI 3 "=h"))]
2615 "TARGET_HAS_MUL_INSNS"
2616 "%!mul<su><mm> %2,%0"
2617 [(set (attr "slottable")
2618 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
2620 (const_string "yes")))
2621 ;; For umuls.[bwd] it's just N unusable here, but let's be safe.
2622 ;; For muls.b, this really extends to SImode, so cc should be
2623 ;; considered clobbered.
2624 ;; For muls.w, it's just N unusable here, but let's be safe.
2625 (set_attr "cc" "clobber")])
2627 ;; Note that gcc does not make use of such a thing as umulqisi3. It gets
2628 ;; confused and will erroneously use it instead of umulhisi3, failing (at
2629 ;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels.
2630 ;; Inspection of optab code shows that there must be only one widening
2631 ;; multiplication per mode widened to.
2633 (define_insn "mulsi3"
2634 [(set (match_operand:SI 0 "register_operand" "=r")
2635 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2636 (match_operand:SI 2 "register_operand" "r")))
2637 (clobber (match_scratch:SI 3 "=h"))]
2638 "TARGET_HAS_MUL_INSNS"
2640 [(set (attr "slottable")
2641 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
2643 (const_string "yes")))
2644 ;; Just N unusable here, but let's be safe.
2645 (set_attr "cc" "clobber")])
2647 ;; A few multiply variations.
2649 ;; When needed, we can get the high 32 bits from the overflow
2650 ;; register. We don't care to split and optimize these.
2652 ;; Note that cc0 is still valid after the move-from-overflow-register
2653 ;; insn; no special precaution need to be taken in cris_notice_update_cc.
2655 (define_insn "<u>mulsidi3"
2656 [(set (match_operand:DI 0 "register_operand" "=r")
2658 (szext:DI (match_operand:SI 1 "register_operand" "%0"))
2659 (szext:DI (match_operand:SI 2 "register_operand" "r"))))
2660 (clobber (match_scratch:SI 3 "=h"))]
2661 "TARGET_HAS_MUL_INSNS"
2662 "%!mul<su>.d %2,%M0\;move $mof,%H0")
2664 ;; These two patterns may be expressible by other means, perhaps by making
2665 ;; [u]?mulsidi3 a define_expand.
2667 ;; Due to register allocation braindamage, the clobber 1,2 alternatives
2668 ;; cause a move into the clobbered register *before* the insn, then
2669 ;; after the insn, mof is moved too, rather than the clobber assigned
2670 ;; the last mof target. This became apparent when making MOF and SRP
2671 ;; visible registers, with the necessary tweak to smulsi3_highpart.
2672 ;; Because these patterns are used in division by constants, that damage
2673 ;; is visible (ipps regression tests). Therefore the last two
2674 ;; alternatives, "helping" reload to avoid an unnecessary move, but
2675 ;; punished by force of one "?". Check code from "int d (int a) {return
2676 ;; a / 1000;}" and unsigned. FIXME: Comment above was for 3.2, revisit.
2678 (define_insn "<su>mulsi3_highpart"
2679 [(set (match_operand:SI 0 "register_operand" "=h,h,?r,?r")
2683 (szext:DI (match_operand:SI 1 "register_operand" "r,r,0,r"))
2684 (szext:DI (match_operand:SI 2 "register_operand" "r,r,r,0")))
2686 (clobber (match_scratch:SI 3 "=1,2,h,h"))]
2687 "TARGET_HAS_MUL_INSNS"
2691 %!mul<su>.d %2,%1\;move $mof,%0
2692 %!mul<su>.d %1,%2\;move $mof,%0"
2693 [(set_attr "slottable" "yes,yes,no,no")
2694 (set_attr "cc" "clobber")])
2696 ;; Divide and modulus instructions. CRIS only has a step instruction.
2698 (define_insn "dstep_shift"
2699 [(set (match_operand:SI 0 "register_operand" "=r")
2701 (geu:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2703 (match_operand:SI 2 "register_operand" "r"))
2704 (minus:SI (ashift:SI (match_operand:SI 3 "register_operand" "0")
2706 (match_operand:SI 4 "register_operand" "2"))
2707 (ashift:SI (match_operand:SI 5 "register_operand" "0")
2711 [(set_attr "slottable" "yes")
2712 (set_attr "cc" "noov32")])
2714 ;; Here's a variant with mult instead of ashift.
2716 ;; FIXME: This should be investigated. Which one matches through combination?
2718 (define_insn "dstep_mul"
2719 [(set (match_operand:SI 0 "register_operand" "=r")
2721 (geu:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2723 (match_operand:SI 2 "register_operand" "r"))
2724 (minus:SI (mult:SI (match_operand:SI 3 "register_operand" "0")
2726 (match_operand:SI 4 "register_operand" "2"))
2727 (mult:SI (match_operand:SI 5 "register_operand" "0")
2729 "operands[0] != frame_pointer_rtx
2730 && operands[1] != frame_pointer_rtx
2731 && operands[2] != frame_pointer_rtx
2732 && operands[3] != frame_pointer_rtx"
2734 [(set_attr "slottable" "yes")
2735 (set_attr "cc" "noov32")])
2737 ;; Logical operators.
2741 ;; There is no use in defining "anddi3", because gcc can expand this by
2742 ;; itself, and make reasonable code without interference.
2744 ;; If the first operand is memory or a register and is the same as the
2745 ;; second operand, and the third operand is -256 or -65536, we can use
2746 ;; CLEAR instead. Or, if the first operand is a register, and the third
2747 ;; operand is 255 or 65535, we can zero_extend.
2748 ;; GCC isn't smart enough to recognize these cases (yet), and they seem
2749 ;; to be common enough to be worthwhile.
2750 ;; FIXME: This should be made obsolete.
2752 (define_expand "andsi3"
2753 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2754 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2755 (match_operand:SI 2 "general_operand" "")))]
2758 if (! (CONST_INT_P (operands[2])
2759 && (((INTVAL (operands[2]) == -256
2760 || INTVAL (operands[2]) == -65536)
2761 && rtx_equal_p (operands[1], operands[0]))
2762 || ((INTVAL (operands[2]) == 255
2763 || INTVAL (operands[2]) == 65535)
2764 && REG_P (operands[0])))))
2766 /* Make intermediate steps if operand0 is not a register or
2767 operand1 is not a register, and hope that the reload pass will
2768 make something useful out of it. Note that the operands are
2769 *not* canonicalized. For the moment, I chicken out on this,
2770 because all or most ports do not describe 'and' with
2771 canonicalized operands, and I seem to remember magic in reload,
2772 checking that operand1 has constraint '%0', in which case
2773 operand0 and operand1 must have similar predicates.
2774 FIXME: Investigate. */
2775 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
2776 rtx reg1 = operands[1];
2780 emit_move_insn (reg0, reg1);
2784 emit_insn (gen_rtx_SET (SImode, reg0,
2785 gen_rtx_AND (SImode, reg1, operands[2])));
2787 /* Make sure we get the right *final* destination. */
2788 if (! REG_P (operands[0]))
2789 emit_move_insn (operands[0], reg0);
2795 ;; Some special cases of andsi3.
2797 (define_insn "*andsi_movu"
2798 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2799 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q,To")
2800 (match_operand:SI 2 "const_int_operand" "n,n,n")))]
2801 "(INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535)
2802 && !side_effects_p (operands[1])"
2804 [(set_attr "slottable" "yes,yes,no")])
2806 (define_insn "*andsi_clear"
2807 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q,Q,To,To")
2808 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
2809 (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))]
2810 "(INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256)
2811 && !side_effects_p (operands[0])"
2819 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2820 (set_attr "cc" "none")])
2822 ;; This is a catch-all pattern, taking care of everything that was not
2823 ;; matched in the insns above.
2825 ;; Sidenote: the tightening from "nonimmediate_operand" to
2826 ;; "register_operand" for operand 1 actually increased the register
2827 ;; pressure (worse code). That will hopefully change with an
2828 ;; improved reload pass.
2830 (define_insn "*expanded_andsi_non_v32"
2831 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r")
2832 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,r")
2833 (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))]
2841 [(set_attr "slottable" "yes,yes,yes,no,no")])
2843 (define_insn "*expanded_andsi_v32"
2844 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2845 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
2846 (match_operand:SI 2 "general_operand" "I,r,Q>,g")))]
2853 [(set_attr "slottable" "yes,yes,yes,no")
2854 (set_attr "cc" "noov32")])
2856 ;; For both QI and HI we may use the quick patterns. This results in
2857 ;; useless condition codes, but that is used rarely enough for it to
2858 ;; normally be a win (could check ahead for use of cc0, but seems to be
2859 ;; more pain than win).
2861 ;; FIXME: See note for andsi3
2863 (define_expand "andhi3"
2864 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2865 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
2866 (match_operand:HI 2 "general_operand" "")))]
2869 if (! (CONST_INT_P (operands[2])
2870 && (((INTVAL (operands[2]) == -256
2871 || INTVAL (operands[2]) == 65280)
2872 && rtx_equal_p (operands[1], operands[0]))
2873 || (INTVAL (operands[2]) == 255
2874 && REG_P (operands[0])))))
2876 /* See comment for andsi3. */
2877 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (HImode);
2878 rtx reg1 = operands[1];
2882 emit_move_insn (reg0, reg1);
2886 emit_insn (gen_rtx_SET (HImode, reg0,
2887 gen_rtx_AND (HImode, reg1, operands[2])));
2889 /* Make sure we get the right destination. */
2890 if (! REG_P (operands[0]))
2891 emit_move_insn (operands[0], reg0);
2897 ;; Some fast andhi3 special cases.
2899 (define_insn "*andhi_movu"
2900 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
2901 (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q,To")
2903 "!side_effects_p (operands[1])"
2905 [(set_attr "slottable" "yes,yes,no")])
2907 (define_insn "*andhi_clear"
2908 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q,To")
2909 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
2911 "!side_effects_p (operands[0])"
2913 [(set_attr "slottable" "yes,yes,no")
2914 (set_attr "cc" "none")])
2916 ;; Catch-all andhi3 pattern.
2918 (define_insn "*expanded_andhi_non_v32"
2919 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
2920 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
2921 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2923 ;; Sidenote: the tightening from "general_operand" to
2924 ;; "register_operand" for operand 1 actually increased the register
2925 ;; pressure (worse code). That will hopefully change with an
2926 ;; improved reload pass.
2937 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2938 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2940 (define_insn "*expanded_andhi_v32"
2941 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
2942 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
2943 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))]
2952 [(set_attr "slottable" "yes,yes,yes,no,yes,no")
2953 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")])
2955 ;; A strict_low_part pattern.
2957 (define_insn "*andhi_lowpart_non_v32"
2958 [(set (strict_low_part
2959 (match_operand:HI 0 "register_operand" "+r,r, r,r,r,r"))
2960 (and:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
2961 (match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
2970 [(set_attr "slottable" "yes,yes,no,yes,no,no")
2971 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
2973 (define_insn "*andhi_lowpart_v32"
2974 [(set (strict_low_part
2975 (match_operand:HI 0 "register_operand" "+r,r,r,r,r"))
2976 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
2977 (match_operand:HI 2 "general_operand" "r,Q>,L,O,g")))]
2985 [(set_attr "slottable" "yes,yes,no,yes,no")
2986 (set_attr "cc" "noov32,noov32,noov32,clobber,noov32")])
2988 (define_expand "andqi3"
2989 [(set (match_operand:QI 0 "register_operand")
2990 (and:QI (match_operand:QI 1 "register_operand")
2991 (match_operand:QI 2 "general_operand")))]
2995 (define_insn "*andqi3_non_v32"
2996 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
2997 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
2998 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
3007 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
3008 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
3010 (define_insn "*andqi3_v32"
3011 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
3012 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
3013 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))]
3021 [(set_attr "slottable" "yes,yes,yes,yes,no")
3022 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")])
3024 (define_insn "*andqi_lowpart_non_v32"
3025 [(set (strict_low_part
3026 (match_operand:QI 0 "register_operand" "+r,r, r,r,r"))
3027 (and:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,r")
3028 (match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
3036 [(set_attr "slottable" "yes,yes,yes,no,no")
3037 (set_attr "cc" "normal,normal,clobber,normal,normal")])
3039 (define_insn "*andqi_lowpart_v32"
3040 [(set (strict_low_part
3041 (match_operand:QI 0 "register_operand" "+r,r,r,r"))
3042 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
3043 (match_operand:QI 2 "general_operand" "r,Q>,O,g")))]
3050 [(set_attr "slottable" "yes,yes,yes,no")
3051 (set_attr "cc" "noov32,noov32,clobber,noov32")])
3055 ;; Same comment as anddi3 applies here - no need for such a pattern.
3057 ;; It seems there's no need to jump through hoops to get good code such as
3060 (define_expand "ior<mode>3"
3061 [(set (match_operand:BWD 0 "register_operand")
3062 (ior:BWD (match_operand:BWD 1 "register_operand")
3063 (match_operand:BWD 2 "general_operand")))]
3067 (define_insn "*iorsi3_non_v32"
3068 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r,r")
3069 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,0,r")
3070 (match_operand:SI 2 "general_operand" "I, r,Q>,n,g,!To")))]
3079 [(set_attr "slottable" "yes,yes,yes,no,no,no")
3080 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
3082 (define_insn "*iorsi3_v32"
3083 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
3084 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0")
3085 (match_operand:SI 2 "general_operand" "I,r,Q>,n,g")))]
3093 [(set_attr "slottable" "yes,yes,yes,no,no")
3094 (set_attr "cc" "noov32,noov32,noov32,clobber,noov32")])
3096 (define_insn "*iorhi3_non_v32"
3097 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
3098 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
3099 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
3109 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
3110 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
3112 (define_insn "*iorhi3_v32"
3113 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
3114 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
3115 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))]
3124 [(set_attr "slottable" "yes,yes,yes,no,yes,no")
3125 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")])
3127 (define_insn "*iorqi3_non_v32"
3128 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
3129 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
3130 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
3139 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
3140 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
3142 (define_insn "*iorqi3_v32"
3143 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
3144 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
3145 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))]
3153 [(set_attr "slottable" "yes,yes,yes,yes,no")
3154 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")])
3158 ;; See comment about "anddi3" for xordi3 - no need for such a pattern.
3159 ;; FIXME: Do we really need the shorter variants?
3161 (define_insn "xorsi3"
3162 [(set (match_operand:SI 0 "register_operand" "=r")
3163 (xor:SI (match_operand:SI 1 "register_operand" "%0")
3164 (match_operand:SI 2 "register_operand" "r")))]
3167 [(set_attr "slottable" "yes")
3168 (set_attr "cc" "noov32")])
3170 (define_insn "xor<mode>3"
3171 [(set (match_operand:BW 0 "register_operand" "=r")
3172 (xor:BW (match_operand:BW 1 "register_operand" "%0")
3173 (match_operand:BW 2 "register_operand" "r")))]
3176 [(set_attr "slottable" "yes")
3177 (set_attr "cc" "clobber")])
3181 ;; Questionable use, here mostly as a (slightly usable) define_expand
3184 (define_expand "negsf2"
3187 (parallel [(set (match_operand:SF 0 "register_operand" "=r")
3188 (neg:SF (match_operand:SF 1
3189 "register_operand" "0")))
3190 (use (match_dup 2))])]
3193 operands[2] = gen_reg_rtx (SImode);
3194 operands[3] = GEN_INT (1 << 31);
3197 (define_insn "*expanded_negsf2"
3198 [(set (match_operand:SF 0 "register_operand" "=r")
3199 (neg:SF (match_operand:SF 1 "register_operand" "0")))
3200 (use (match_operand:SI 2 "register_operand" "r"))]
3203 [(set_attr "slottable" "yes")])
3205 ;; No "negdi2" although we could make one up that may be faster than
3206 ;; the one in libgcc.
3208 (define_insn "neg<mode>2"
3209 [(set (match_operand:BWD 0 "register_operand" "=r")
3210 (neg:BWD (match_operand:BWD 1 "register_operand" "r")))]
3213 [(set_attr "slottable" "yes")])
3217 ;; See comment on anddi3 - no need for a DImode pattern.
3218 ;; See also xor comment.
3220 (define_insn "one_cmplsi2"
3221 [(set (match_operand:SI 0 "register_operand" "=r")
3222 (not:SI (match_operand:SI 1 "register_operand" "0")))]
3225 [(set_attr "slottable" "yes")
3226 (set_attr "cc" "noov32")])
3228 (define_insn "one_cmpl<mode>2"
3229 [(set (match_operand:BW 0 "register_operand" "=r")
3230 (not:BW (match_operand:BW 1 "register_operand" "0")))]
3233 [(set_attr "slottable" "yes")
3234 (set_attr "cc" "clobber")])
3236 ;; Arithmetic/Logical shift right (and SI left).
3238 (define_insn "<shlr>si3"
3239 [(set (match_operand:SI 0 "register_operand" "=r")
3240 (shift:SI (match_operand:SI 1 "register_operand" "0")
3241 (match_operand:SI 2 "nonmemory_operand" "Kr")))]
3244 if (REG_S_P (operands[2]))
3245 return "<slr>.d %2,%0";
3247 return "<slr>q %2,%0";
3249 [(set_attr "slottable" "yes")
3250 (set_attr "cc" "noov32")])
3252 ;; Since gcc gets lost, and forgets to zero-extend the source (or mask
3253 ;; the destination) when it changes shifts of lower modes into SImode,
3254 ;; it is better to make these expands an anonymous patterns instead of
3255 ;; the more correct define_insns. This occurs when gcc thinks that is
3256 ;; is better to widen to SImode and use immediate shift count.
3258 ;; FIXME: Is this legacy or still true for gcc >= 2.7.2?
3260 ;; FIXME: Can't parametrize sign_extend and zero_extend (before
3261 ;; mentioning "shiftrt"), so we need two patterns.
3262 (define_expand "ashr<mode>3"
3264 (sign_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
3266 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
3267 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
3268 (set (match_operand:BW 0 "general_operand" "")
3269 (subreg:BW (match_dup 5) 0))]
3274 for (i = 3; i < 6; i++)
3275 operands[i] = gen_reg_rtx (SImode);
3278 (define_expand "lshr<mode>3"
3280 (zero_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
3282 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
3283 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
3284 (set (match_operand:BW 0 "general_operand" "")
3285 (subreg:BW (match_dup 5) 0))]
3290 for (i = 3; i < 6; i++)
3291 operands[i] = gen_reg_rtx (SImode);
3294 (define_insn "*expanded_<shlr><mode>"
3295 [(set (match_operand:BW 0 "register_operand" "=r")
3296 (shiftrt:BW (match_operand:BW 1 "register_operand" "0")
3297 (match_operand:BW 2 "register_operand" "r")))]
3300 [(set_attr "slottable" "yes")
3301 (set_attr "cc" "noov32")])
3303 (define_insn "*<shlr><mode>_lowpart"
3304 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
3305 (shiftrt:BW (match_dup 0)
3306 (match_operand:BW 1 "register_operand" "r")))]
3309 [(set_attr "slottable" "yes")
3310 (set_attr "cc" "noov32")])
3312 ;; Arithmetic/logical shift left.
3314 ;; For narrower modes than SI, we can use lslq although it makes cc
3315 ;; unusable. The win is that we do not have to reload the shift-count
3318 (define_insn "ashl<mode>3"
3319 [(set (match_operand:BW 0 "register_operand" "=r,r")
3320 (ashift:BW (match_operand:BW 1 "register_operand" "0,0")
3321 (match_operand:BW 2 "nonmemory_operand" "r,K")))]
3325 (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > <nbitsm1>)
3327 : (CONSTANT_P (operands[2])
3328 ? "lslq %2,%0" : "lsl<m> %2,%0");
3330 [(set_attr "slottable" "yes")
3331 (set_attr "cc" "noov32,clobber")])
3333 ;; A strict_low_part matcher.
3335 (define_insn "*ashl<mode>_lowpart"
3336 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
3337 (ashift:BW (match_dup 0)
3338 (match_operand:HI 1 "register_operand" "r")))]
3341 [(set_attr "slottable" "yes")
3342 (set_attr "cc" "noov32")])
3344 ;; Various strange insns that gcc likes.
3346 ;; Fortunately, it is simple to construct an abssf (although it may not
3347 ;; be very much used in practice).
3349 (define_insn "abssf2"
3350 [(set (match_operand:SF 0 "register_operand" "=r")
3351 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
3353 "lslq 1,%0\;lsrq 1,%0")
3355 (define_insn "abssi2"
3356 [(set (match_operand:SI 0 "register_operand" "=r")
3357 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
3360 [(set_attr "slottable" "yes")
3361 (set_attr "cc" "noov32")])
3363 ;; FIXME: GCC should be able to do these expansions itself.
3365 (define_expand "abs<mode>2"
3367 (sign_extend:SI (match_operand:BW 1 "general_operand" "")))
3368 (set (match_dup 3) (abs:SI (match_dup 2)))
3369 (set (match_operand:BW 0 "register_operand" "")
3370 (subreg:BW (match_dup 3) 0))]
3372 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
3374 (define_insn "clzsi2"
3375 [(set (match_operand:SI 0 "register_operand" "=r")
3376 (clz:SI (match_operand:SI 1 "register_operand" "r")))]
3379 [(set_attr "slottable" "yes")
3380 (set_attr "cc" "noov32")])
3382 (define_insn "bswapsi2"
3383 [(set (match_operand:SI 0 "register_operand" "=r")
3384 (bswap:SI (match_operand:SI 1 "register_operand" "0")))]
3387 [(set_attr "slottable" "yes")
3388 (set_attr "cc" "noov32")])
3390 ;; This instruction swaps all bits in a register.
3391 ;; That means that the most significant bit is put in the place
3392 ;; of the least significant bit, and so on.
3394 (define_insn "cris_swap_bits"
3395 [(set (match_operand:SI 0 "register_operand" "=r")
3396 (unspec:SI [(match_operand:SI 1 "register_operand" "0")]
3397 CRIS_UNSPEC_SWAP_BITS))]
3400 [(set_attr "slottable" "yes")
3401 (set_attr "cc" "noov32")])
3403 ;; Implement ctz using two instructions, one for bit swap and one for clz.
3404 ;; Defines a scratch register to avoid clobbering input.
3406 (define_expand "ctzsi2"
3408 (match_operand:SI 1 "register_operand"))
3410 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_SWAP_BITS))
3411 (set (match_operand:SI 0 "register_operand")
3412 (clz:SI (match_dup 2)))]
3413 "TARGET_HAS_LZ && TARGET_HAS_SWAP"
3414 "operands[2] = gen_reg_rtx (SImode);")
3416 ;; Bound-insn. Defined to be the same as an unsigned minimum, which is an
3417 ;; operation supported by gcc. Used in casesi, but used now and then in
3420 (define_expand "uminsi3"
3421 [(set (match_operand:SI 0 "register_operand" "")
3422 (umin:SI (match_operand:SI 1 "register_operand" "")
3423 (match_operand:SI 2 "general_operand" "")))]
3426 if (MEM_P (operands[2]) && TARGET_V32)
3427 operands[2] = force_reg (SImode, operands[2]);
3430 (define_insn "*uminsi3_non_v32"
3431 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r")
3432 (umin:SI (match_operand:SI 1 "register_operand" "%0,0, 0,r")
3433 (match_operand:SI 2 "general_operand" "r,Q>,g,!To")))]
3436 if (CONST_INT_P (operands[2]))
3438 /* Constant operands are zero-extended, so only 32-bit operands
3440 if (INTVAL (operands[2]) >= 0)
3442 if (INTVAL (operands[2]) < 256)
3443 return "bound.b %2,%0";
3445 if (INTVAL (operands[2]) < 65536)
3446 return "bound.w %2,%0";
3449 else if (which_alternative == 3)
3450 return "bound.d %2,%1,%0";
3452 return "bound.d %2,%0";
3454 [(set_attr "slottable" "yes,yes,no,no")])
3456 (define_insn "*uminsi3_v32"
3457 [(set (match_operand:SI 0 "register_operand" "=r,r")
3458 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
3459 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
3462 if (GET_CODE (operands[2]) == CONST_INT)
3464 /* Constant operands are zero-extended, so only 32-bit operands
3466 if (INTVAL (operands[2]) >= 0)
3468 if (INTVAL (operands[2]) < 256)
3469 return "bound.b %2,%0";
3471 if (INTVAL (operands[2]) < 65536)
3472 return "bound.w %2,%0";
3476 return "bound.d %2,%0";
3478 [(set_attr "slottable" "yes,no")])
3480 ;; Jump and branch insns.
3484 (label_ref (match_operand 0 "" "")))]
3487 [(set_attr "slottable" "has_slot")])
3489 ;; Testcase gcc.c-torture/compile/991213-3.c fails if we allow a constant
3490 ;; here, since the insn is not recognized as an indirect jump by
3491 ;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to
3492 ;; change from general_operand to nonimmediate_operand (at least the docs
3493 ;; should be changed), but then again the pattern is called indirect_jump.
3494 (define_expand "indirect_jump"
3495 [(set (pc) (match_operand:SI 0 "nonimmediate_operand"))]
3498 if (TARGET_V32 && MEM_P (operands[0]))
3499 operands[0] = force_reg (SImode, operands[0]);
3502 (define_insn "*indirect_jump_non_v32"
3503 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
3507 (define_insn "*indirect_jump_v32"
3508 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
3511 [(set_attr "slottable" "has_slot")])
3513 ;; Return insn. Used whenever the epilogue is very simple; if it is only
3514 ;; a single ret or jump [sp+]. No allocated stack space or saved
3515 ;; registers are allowed.
3516 ;; Note that for this pattern, although named, it is ok to check the
3517 ;; context of the insn in the test, not only compiler switches.
3519 (define_expand "return"
3521 "cris_simple_epilogue ()"
3522 "cris_expand_return (cris_return_address_on_stack ()); DONE;")
3524 (define_insn "*return_expanded"
3528 return cris_return_address_on_stack_for_return ()
3529 ? "jump [$sp+]" : "ret%#";
3531 [(set (attr "slottable")
3534 "(cris_return_address_on_stack_for_return ())")
3537 (const_string "has_return_slot")))])
3539 (define_expand "prologue"
3541 "TARGET_PROLOGUE_EPILOGUE"
3542 "cris_expand_prologue (); DONE;")
3544 ;; Note that the (return) from the expander itself is always the last
3545 ;; insn in the epilogue.
3546 (define_expand "epilogue"
3548 "TARGET_PROLOGUE_EPILOGUE"
3549 "cris_expand_epilogue (); DONE;")
3551 ;; Conditional branches.
3553 ;; We suffer from the same overflow-bit-gets-in-the-way problem as
3554 ;; e.g. m68k, so we have to check if overflow bit is set on all "signed"
3557 (define_insn "b<ncond:code>"
3559 (if_then_else (ncond (cc0)
3561 (label_ref (match_operand 0 "" ""))
3565 [(set_attr "slottable" "has_slot")])
3567 (define_insn "b<ocond:code>"
3569 (if_then_else (ocond (cc0)
3571 (label_ref (match_operand 0 "" ""))
3576 (cc_prev_status.flags & CC_NO_OVERFLOW)
3577 ? 0 : "b<CC> %l0%#";
3579 [(set_attr "slottable" "has_slot")])
3581 (define_insn "b<rcond:code>"
3583 (if_then_else (rcond (cc0)
3585 (label_ref (match_operand 0 "" ""))
3590 (cc_prev_status.flags & CC_NO_OVERFLOW)
3591 ? "b<oCC> %l0%#" : "b<CC> %l0%#";
3593 [(set_attr "slottable" "has_slot")])
3595 ;; Reversed anonymous patterns to the ones above, as mandated.
3597 (define_insn "*b<ncond:code>_reversed"
3599 (if_then_else (ncond (cc0)
3602 (label_ref (match_operand 0 "" ""))))]
3605 [(set_attr "slottable" "has_slot")])
3607 (define_insn "*b<ocond:code>_reversed"
3609 (if_then_else (ocond (cc0)
3612 (label_ref (match_operand 0 "" ""))))]
3616 (cc_prev_status.flags & CC_NO_OVERFLOW)
3617 ? 0 : "b<rCC> %l0%#";
3619 [(set_attr "slottable" "has_slot")])
3621 (define_insn "*b<rcond:code>_reversed"
3623 (if_then_else (rcond (cc0)
3626 (label_ref (match_operand 0 "" ""))))]
3630 (cc_prev_status.flags & CC_NO_OVERFLOW)
3631 ? "b<roCC> %l0%#" : "b<rCC> %l0%#";
3633 [(set_attr "slottable" "has_slot")])
3635 ;; Set on condition: sCC.
3637 ;; Like bCC, we have to check the overflow bit for
3638 ;; signed conditions.
3640 (define_insn "s<ncond:code>"
3641 [(set (match_operand:SI 0 "register_operand" "=r")
3642 (ncond:SI (cc0) (const_int 0)))]
3645 [(set_attr "slottable" "yes")
3646 (set_attr "cc" "none")])
3648 (define_insn "s<rcond:code>"
3649 [(set (match_operand:SI 0 "register_operand" "=r")
3650 (rcond:SI (cc0) (const_int 0)))]
3654 (cc_prev_status.flags & CC_NO_OVERFLOW)
3655 ? "s<oCC> %0" : "s<CC> %0";
3657 [(set_attr "slottable" "yes")
3658 (set_attr "cc" "none")])
3660 (define_insn "s<ocond:code>"
3661 [(set (match_operand:SI 0 "register_operand" "=r")
3662 (ocond:SI (cc0) (const_int 0)))]
3666 (cc_prev_status.flags & CC_NO_OVERFLOW)
3669 [(set_attr "slottable" "yes")
3670 (set_attr "cc" "none")])
3674 ;; We need to make these patterns "expand", since the real operand is
3675 ;; hidden in a (mem:QI ) inside operand[0] (call_value: operand[1]),
3676 ;; and cannot be checked if it were a "normal" pattern.
3677 ;; Note that "call" and "call_value" are *always* called with a
3678 ;; mem-operand for operand 0 and 1 respective. What happens for combined
3679 ;; instructions is a different issue.
3681 (define_expand "call"
3682 [(parallel [(call (match_operand:QI 0 "cris_mem_call_operand" "")
3683 (match_operand 1 "general_operand" ""))
3684 (clobber (reg:SI CRIS_SRP_REGNUM))])]
3687 gcc_assert (MEM_P (operands[0]));
3689 cris_expand_pic_call_address (&operands[0]);
3692 ;; Accept *anything* as operand 1. Accept operands for operand 0 in
3693 ;; order of preference.
3695 (define_insn "*expanded_call_non_v32"
3696 [(call (mem:QI (match_operand:SI 0 "general_operand" "r,Q>,g"))
3697 (match_operand 1 "" ""))
3698 (clobber (reg:SI CRIS_SRP_REGNUM))]
3702 (define_insn "*expanded_call_v32"
3705 (match_operand:SI 0 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i"))
3706 (match_operand 1 "" ""))
3707 (clobber (reg:SI CRIS_SRP_REGNUM))]
3714 [(set_attr "slottable" "has_call_slot")])
3716 ;; Parallel when calculating and reusing address of indirect pointer
3717 ;; with simple offset. (Makes most sense with PIC.) It looks a bit
3718 ;; wrong not to have the clobber last, but that's the way combine
3719 ;; generates it (except it doesn' look into the *inner* mem, so this
3720 ;; just matches a peephole2). FIXME: investigate that.
3721 (define_insn "*expanded_call_side"
3724 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r, r,r")
3725 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn"))))
3726 (match_operand 2 "" ""))
3727 (clobber (reg:SI CRIS_SRP_REGNUM))
3728 (set (match_operand:SI 3 "register_operand" "=*0,r,r")
3729 (plus:SI (match_dup 0)
3731 "!TARGET_AVOID_GOTPLT && !TARGET_V32"
3734 (define_expand "call_value"
3735 [(parallel [(set (match_operand 0 "" "")
3736 (call (match_operand:QI 1 "cris_mem_call_operand" "")
3737 (match_operand 2 "" "")))
3738 (clobber (reg:SI CRIS_SRP_REGNUM))])]
3741 gcc_assert (MEM_P (operands[1]));
3743 cris_expand_pic_call_address (&operands[1]);
3746 ;; Accept *anything* as operand 2. The validity other than "general" of
3747 ;; operand 0 will be checked elsewhere. Accept operands for operand 1 in
3748 ;; order of preference (Q includes r, but r is shorter, faster).
3749 ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather
3750 ;; than requiring getting rPIC + sym:PLT into a register.
3752 (define_insn "*expanded_call_value_non_v32"
3753 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
3754 (call (mem:QI (match_operand:SI 1 "general_operand" "r,Q>,g"))
3755 (match_operand 2 "" "")))
3756 (clobber (reg:SI CRIS_SRP_REGNUM))]
3759 [(set_attr "cc" "clobber")])
3761 ;; See similar call special-case.
3762 (define_insn "*expanded_call_value_side"
3763 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
3767 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r, r,r")
3768 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
3769 (match_operand 3 "" "")))
3770 (clobber (reg:SI CRIS_SRP_REGNUM))
3771 (set (match_operand:SI 4 "register_operand" "=*1,r,r")
3772 (plus:SI (match_dup 1)
3774 "!TARGET_AVOID_GOTPLT && !TARGET_V32"
3776 [(set_attr "cc" "clobber")])
3778 (define_insn "*expanded_call_value_v32"
3780 (match_operand 0 "nonimmediate_operand" "=g,g,g,g")
3783 (match_operand:SI 1 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i"))
3784 (match_operand 2 "" "")))
3785 (clobber (reg:SI 16))]
3792 [(set_attr "cc" "clobber")
3793 (set_attr "slottable" "has_call_slot")])
3795 ;; Used in debugging. No use for the direct pattern; unfilled
3796 ;; delayed-branches are taken care of by other means.
3802 [(set_attr "cc" "none")])
3804 ;; We need to stop accesses to the stack after the memory is
3805 ;; deallocated. Unfortunately, reorg doesn't look at naked clobbers,
3806 ;; e.g. (insn ... (clobber (mem:BLK (stack_pointer_rtx)))) and we don't
3807 ;; want to use a naked (unspec_volatile) as that would stop any
3808 ;; scheduling in the epilogue. Hence we model it as a "real" insn that
3809 ;; sets the memory in an unspecified manner. FIXME: Unfortunately it
3810 ;; still has the effect of an unspec_volatile.
3811 (define_insn "cris_frame_deallocated_barrier"
3812 [(set (mem:BLK (reg:SI CRIS_SP_REGNUM))
3813 (unspec:BLK [(const_int 0)] CRIS_UNSPEC_FRAME_DEALLOC))]
3816 [(set_attr "length" "0")])
3818 ;; We expand on casesi so we can use "bound" and "add offset fetched from
3819 ;; a table to pc" (adds.w [pc+%0.w],pc).
3821 ;; Note: if you change the "parallel" (or add anything after it) in
3822 ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END
3823 ;; accordingly, to add the default case at the end of the jump-table.
3825 (define_expand "cris_casesi_non_v32"
3826 [(set (match_dup 5) (match_operand:SI 0 "general_operand" ""))
3828 (minus:SI (match_dup 5)
3829 (match_operand:SI 1 "const_int_operand" "n")))
3831 (umin:SI (match_dup 6)
3832 (match_operand:SI 2 "const_int_operand" "n")))
3836 (ltu (match_dup 7) (match_dup 2))
3837 (plus:SI (sign_extend:SI
3839 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3842 (label_ref (match_operand 4 "" ""))))
3843 (use (label_ref (match_operand 3 "" "")))])]
3846 operands[2] = plus_constant (operands[2], 1);
3847 operands[5] = gen_reg_rtx (SImode);
3848 operands[6] = gen_reg_rtx (SImode);
3849 operands[7] = gen_reg_rtx (SImode);
3852 ;; FIXME: Check effect of not JUMP_TABLES_IN_TEXT_SECTION.
3853 (define_expand "cris_casesi_v32"
3854 [(set (match_dup 5) (match_operand:SI 0 "general_operand"))
3856 (minus:SI (match_dup 5)
3857 (match_operand:SI 1 "const_int_operand")))
3859 (umin:SI (match_dup 6)
3860 (match_operand:SI 2 "const_int_operand")))
3861 (set (match_dup 8) (match_dup 11))
3863 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3866 (plus:SI (sign_extend:SI (mem:HI (match_dup 9)))
3871 (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI) (match_dup 2))
3873 (label_ref (match_operand 4 "" ""))))
3874 (use (label_ref (match_dup 3)))])]
3878 rtx xlabel = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
3879 for (i = 5; i <= 10; i++)
3880 operands[i] = gen_reg_rtx (SImode);
3881 operands[2] = plus_constant (operands[2], 1);
3883 /* Don't forget to decorate labels too, for PIC. */
3884 operands[11] = flag_pic
3885 ? gen_rtx_CONST (Pmode,
3886 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xlabel),
3891 (define_expand "casesi"
3892 [(match_operand:SI 0 "general_operand")
3893 (match_operand:SI 1 "const_int_operand")
3894 (match_operand:SI 2 "const_int_operand")
3895 (match_operand 3 "" "")
3896 (match_operand 4 "" "")]
3900 emit_insn (gen_cris_casesi_v32 (operands[0], operands[1], operands[2],
3901 operands[3], operands[4]));
3903 emit_insn (gen_cris_casesi_non_v32 (operands[0], operands[1], operands[2],
3904 operands[3], operands[4]));
3908 ;; Split-patterns. Some of them have modes unspecified. This
3909 ;; should always be ok; if for no other reason sparc.md has it as
3912 ;; When register_operand is specified for an operand, we can get a
3913 ;; subreg as well (Axis-990331), so don't just assume that REG_P is true
3914 ;; for a register_operand and that REGNO can be used as is. It is best to
3915 ;; guard with REG_P, unless it is worth it to adjust for the subreg case.
3917 ;; op [rx + 0],ry,rz
3918 ;; The index to rx is optimized into zero, and gone.
3920 ;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended,
3921 ;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx].
3925 ;; Lose if rz=ry or rx=rz.
3926 ;; Call this op-extend-split.
3927 ;; Do not match for V32; the addo and addi shouldn't be split
3931 [(set (match_operand 0 "register_operand" "")
3933 4 "cris_operand_extend_operator"
3934 [(match_operand 1 "register_operand" "")
3936 3 "cris_extend_operator"
3937 [(match_operand 2 "memory_operand" "")])]))]
3939 && REG_P (operands[0])
3940 && REG_P (operands[1])
3941 && REGNO (operands[1]) != REGNO (operands[0])
3942 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3943 && REG_P (XEXP (operands[2], 0))
3944 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
3950 (match_op_dup 3 [(match_dup 2)])]))]
3953 ;; As op-extend-split, but recognize and split op [rz],ry,rz into
3956 ;; Do this for plus or bound only, being commutative operations, since we
3957 ;; have swapped the operands.
3958 ;; Call this op-extend-split-rx=rz
3961 [(set (match_operand 0 "register_operand" "")
3963 4 "cris_plus_or_bound_operator"
3964 [(match_operand 1 "register_operand" "")
3966 3 "cris_extend_operator"
3967 [(match_operand 2 "memory_operand" "")])]))]
3969 && REG_P (operands[0])
3970 && REG_P (operands[1])
3971 && REGNO (operands[1]) != REGNO (operands[0])
3972 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3973 && REG_P (XEXP (operands[2], 0))
3974 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
3976 (match_op_dup 3 [(match_dup 2)]))
3983 ;; As the op-extend-split, but swapped operands, and only for
3984 ;; plus or bound, being the commutative extend-operators. FIXME: Why is
3985 ;; this needed? Is it?
3986 ;; Call this op-extend-split-swapped
3989 [(set (match_operand 0 "register_operand" "")
3991 4 "cris_plus_or_bound_operator"
3993 3 "cris_extend_operator"
3994 [(match_operand 2 "memory_operand" "")])
3995 (match_operand 1 "register_operand" "")]))]
3997 && REG_P (operands[0])
3998 && REG_P (operands[1])
3999 && REGNO (operands[1]) != REGNO (operands[0])
4000 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4001 && REG_P (XEXP (operands[2], 0))
4002 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4008 (match_op_dup 3 [(match_dup 2)])]))]
4011 ;; As op-extend-split-rx=rz, but swapped operands, only for plus or
4012 ;; bound. Call this op-extend-split-swapped-rx=rz.
4015 [(set (match_operand 0 "register_operand" "")
4017 4 "cris_plus_or_bound_operator"
4019 3 "cris_extend_operator"
4020 [(match_operand 2 "memory_operand" "")])
4021 (match_operand 1 "register_operand" "")]))]
4023 && REG_P (operands[0])
4024 && REG_P (operands[1])
4025 && REGNO (operands[1]) != REGNO (operands[0])
4026 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4027 && REG_P (XEXP (operands[2], 0))
4028 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4030 (match_op_dup 3 [(match_dup 2)]))
4037 ;; As op-extend-split, but the mem operand is not extended.
4039 ;; op [rx],ry,rz changed into
4042 ;; lose if ry=rz or rx=rz
4043 ;; Call this op-extend.
4046 [(set (match_operand 0 "register_operand" "")
4048 3 "cris_orthogonal_operator"
4049 [(match_operand 1 "register_operand" "")
4050 (match_operand 2 "memory_operand" "")]))]
4052 && REG_P (operands[0])
4053 && REG_P (operands[1])
4054 && REGNO (operands[1]) != REGNO (operands[0])
4055 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4056 && REG_P (XEXP (operands[2], 0))
4057 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4066 ;; As op-extend-split-rx=rz, non-extended.
4067 ;; Call this op-split-rx=rz
4070 [(set (match_operand 0 "register_operand" "")
4072 3 "cris_commutative_orth_op"
4073 [(match_operand 2 "memory_operand" "")
4074 (match_operand 1 "register_operand" "")]))]
4076 && REG_P (operands[0])
4077 && REG_P (operands[1])
4078 && REGNO (operands[1]) != REGNO (operands[0])
4079 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4080 && REG_P (XEXP (operands[2], 0))
4081 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4090 ;; As op-extend-split-swapped, nonextended.
4091 ;; Call this op-split-swapped.
4094 [(set (match_operand 0 "register_operand" "")
4096 3 "cris_commutative_orth_op"
4097 [(match_operand 1 "register_operand" "")
4098 (match_operand 2 "memory_operand" "")]))]
4100 && REG_P (operands[0]) && REG_P (operands[1])
4101 && REGNO (operands[1]) != REGNO (operands[0])
4102 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4103 && REG_P (XEXP (operands[2], 0))
4104 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4113 ;; As op-extend-split-swapped-rx=rz, non-extended.
4114 ;; Call this op-split-swapped-rx=rz.
4117 [(set (match_operand 0 "register_operand" "")
4119 3 "cris_orthogonal_operator"
4120 [(match_operand 2 "memory_operand" "")
4121 (match_operand 1 "register_operand" "")]))]
4123 && REG_P (operands[0]) && REG_P (operands[1])
4124 && REGNO (operands[1]) != REGNO (operands[0])
4125 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4126 && REG_P (XEXP (operands[2], 0))
4127 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4136 ;; Splits for all cases in side-effect insns where (possibly after reload
4137 ;; and register allocation) rx and ry in [rx=ry+i] are equal.
4139 ;; move.S1 [rx=rx+rz.S2],ry
4143 [(set (match_operand 0 "register_operand" "")
4147 (mult:SI (match_operand:SI 1 "register_operand" "")
4148 (match_operand:SI 2 "const_int_operand" ""))
4149 (match_operand:SI 3 "register_operand" ""))]))
4150 (set (match_operand:SI 4 "register_operand" "")
4151 (plus:SI (mult:SI (match_dup 1)
4154 "REG_P (operands[3]) && REG_P (operands[4])
4155 && REGNO (operands[3]) == REGNO (operands[4])"
4156 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4158 (set (match_dup 0) (match_dup 5))]
4159 "operands[5] = replace_equiv_address (operands[6], operands[3]);")
4161 ;; move.S1 [rx=rx+i],ry
4165 [(set (match_operand 0 "register_operand" "")
4168 [(plus:SI (match_operand:SI 1 "cris_bdap_operand" "")
4169 (match_operand:SI 2 "cris_bdap_operand" ""))]))
4170 (set (match_operand:SI 3 "register_operand" "")
4171 (plus:SI (match_dup 1)
4173 "(rtx_equal_p (operands[3], operands[1])
4174 || rtx_equal_p (operands[3], operands[2]))"
4175 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4176 (set (match_dup 0) (match_dup 4))]
4178 operands[4] = replace_equiv_address (operands[5], operands[3]);
4179 cris_order_for_addsi3 (operands, 1);
4182 ;; move.S1 ry,[rx=rx+rz.S2]
4186 [(set (match_operator
4189 (mult:SI (match_operand:SI 0 "register_operand" "")
4190 (match_operand:SI 1 "const_int_operand" ""))
4191 (match_operand:SI 2 "register_operand" ""))])
4192 (match_operand 3 "register_operand" ""))
4193 (set (match_operand:SI 4 "register_operand" "")
4194 (plus:SI (mult:SI (match_dup 0)
4197 "REG_P (operands[2]) && REG_P (operands[4])
4198 && REGNO (operands[4]) == REGNO (operands[2])"
4199 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4201 (set (match_dup 5) (match_dup 3))]
4202 "operands[5] = replace_equiv_address (operands[6], operands[4]);")
4204 ;; move.S1 ry,[rx=rx+i]
4208 [(set (match_operator
4210 [(plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4211 (match_operand:SI 1 "cris_bdap_operand" ""))])
4212 (match_operand 2 "register_operand" ""))
4213 (set (match_operand:SI 3 "register_operand" "")
4214 (plus:SI (match_dup 0)
4216 "(rtx_equal_p (operands[3], operands[0])
4217 || rtx_equal_p (operands[3], operands[1]))"
4218 [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1)))
4219 (set (match_dup 5) (match_dup 2))]
4221 operands[5] = replace_equiv_address (operands[6], operands[3]);
4222 cris_order_for_addsi3 (operands, 0);
4225 ;; clear.[bwd] [rx=rx+rz.S2]
4229 [(set (mem:BWD (plus:SI
4230 (mult:SI (match_operand:SI 0 "register_operand" "")
4231 (match_operand:SI 1 "const_int_operand" ""))
4232 (match_operand:SI 2 "register_operand" "")))
4234 (set (match_operand:SI 3 "register_operand" "")
4235 (plus:SI (mult:SI (match_dup 0)
4238 "REG_P (operands[2]) && REG_P (operands[3])
4239 && REGNO (operands[3]) == REGNO (operands[2])"
4240 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4242 (set (mem:BWD (match_dup 3)) (const_int 0))]
4245 ;; clear.[bwd] [rx=rx+i]
4250 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4251 (match_operand:SI 1 "cris_bdap_operand" "")))
4253 (set (match_operand:SI 2 "register_operand" "")
4254 (plus:SI (match_dup 0)
4256 "(rtx_equal_p (operands[0], operands[2])
4257 || rtx_equal_p (operands[2], operands[1]))"
4258 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4259 (set (mem:BWD (match_dup 2)) (const_int 0))]
4260 "cris_order_for_addsi3 (operands, 0);")
4262 ;; mov(s|u).S1 [rx=rx+rz.S2],ry
4266 [(set (match_operand 0 "register_operand" "")
4268 5 "cris_extend_operator"
4270 (mult:SI (match_operand:SI 1 "register_operand" "")
4271 (match_operand:SI 2 "const_int_operand" ""))
4272 (match_operand:SI 3 "register_operand" "")))]))
4273 (set (match_operand:SI 4 "register_operand" "")
4274 (plus:SI (mult:SI (match_dup 1)
4277 "REG_P (operands[3])
4278 && REG_P (operands[4])
4279 && REGNO (operands[3]) == REGNO (operands[4])"
4280 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4282 (set (match_dup 0) (match_op_dup 5 [(match_dup 6)]))]
4283 "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);")
4285 ;; mov(s|u).S1 [rx=rx+i],ry
4289 [(set (match_operand 0 "register_operand" "")
4291 4 "cris_extend_operator"
4293 (match_operand:SI 1 "cris_bdap_operand" "")
4294 (match_operand:SI 2 "cris_bdap_operand" "")))]))
4295 (set (match_operand:SI 3 "register_operand" "")
4296 (plus:SI (match_dup 1)
4298 "(rtx_equal_p (operands[1], operands[3])
4299 || rtx_equal_p (operands[2], operands[3]))"
4300 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4301 (set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))]
4303 operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]);
4304 cris_order_for_addsi3 (operands, 1);
4307 ;; op.S1 [rx=rx+i],ry
4311 [(set (match_operand 0 "register_operand" "")
4313 5 "cris_orthogonal_operator"
4314 [(match_operand 1 "register_operand" "")
4316 (match_operand:SI 2 "cris_bdap_operand" "")
4317 (match_operand:SI 3 "cris_bdap_operand" "")))]))
4318 (set (match_operand:SI 4 "register_operand" "")
4319 (plus:SI (match_dup 2)
4321 "(rtx_equal_p (operands[4], operands[2])
4322 || rtx_equal_p (operands[4], operands[3]))"
4323 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4324 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))]
4326 operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]);
4327 cris_order_for_addsi3 (operands, 2);
4330 ;; op.S1 [rx=rx+rz.S2],ry
4334 [(set (match_operand 0 "register_operand" "")
4336 6 "cris_orthogonal_operator"
4337 [(match_operand 1 "register_operand" "")
4339 (mult:SI (match_operand:SI 2 "register_operand" "")
4340 (match_operand:SI 3 "const_int_operand" ""))
4341 (match_operand:SI 4 "register_operand" "")))]))
4342 (set (match_operand:SI 5 "register_operand" "")
4343 (plus:SI (mult:SI (match_dup 2)
4346 "REG_P (operands[4])
4347 && REG_P (operands[5])
4348 && REGNO (operands[5]) == REGNO (operands[4])"
4349 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4351 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 7)]))]
4352 "operands[7] = replace_equiv_address (XEXP (operands[6], 1), operands[5]);")
4354 ;; op.S1 [rx=rx+rz.S2],ry (swapped)
4358 [(set (match_operand 0 "register_operand" "")
4360 6 "cris_commutative_orth_op"
4362 (mult:SI (match_operand:SI 2 "register_operand" "")
4363 (match_operand:SI 3 "const_int_operand" ""))
4364 (match_operand:SI 4 "register_operand" "")))
4365 (match_operand 1 "register_operand" "")]))
4366 (set (match_operand:SI 5 "register_operand" "")
4367 (plus:SI (mult:SI (match_dup 2)
4370 "REG_P (operands[4])
4371 && REG_P (operands[5])
4372 && REGNO (operands[5]) == REGNO (operands[4])"
4373 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4375 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4376 "operands[7] = replace_equiv_address (XEXP (operands[6], 0), operands[5]);")
4378 ;; op.S1 [rx=rx+i],ry (swapped)
4382 [(set (match_operand 0 "register_operand" "")
4384 5 "cris_commutative_orth_op"
4386 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4387 (match_operand:SI 3 "cris_bdap_operand" "")))
4388 (match_operand 1 "register_operand" "")]))
4389 (set (match_operand:SI 4 "register_operand" "")
4390 (plus:SI (match_dup 2)
4392 "(rtx_equal_p (operands[4], operands[2])
4393 || rtx_equal_p (operands[4], operands[3]))"
4394 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4395 (set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))]
4397 operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);
4398 cris_order_for_addsi3 (operands, 2);
4401 ;; op(s|u).S1 [rx=rx+rz.S2],ry
4405 [(set (match_operand 0 "register_operand" "")
4407 6 "cris_operand_extend_operator"
4408 [(match_operand 1 "register_operand" "")
4410 7 "cris_extend_operator"
4412 (mult:SI (match_operand:SI 2 "register_operand" "")
4413 (match_operand:SI 3 "const_int_operand" ""))
4414 (match_operand:SI 4 "register_operand" "")))])]))
4415 (set (match_operand:SI 5 "register_operand" "")
4416 (plus:SI (mult:SI (match_dup 2)
4419 "REG_P (operands[4])
4420 && REG_P (operands[5])
4421 && REGNO (operands[5]) == REGNO (operands[4])"
4422 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4424 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 8)]))]
4425 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[7]), GET_MODE (operands[7]),
4426 replace_equiv_address (XEXP (operands[7], 0),
4429 ;; op(s|u).S1 [rx=rx+i],ry
4433 [(set (match_operand 0 "register_operand" "")
4435 5 "cris_operand_extend_operator"
4436 [(match_operand 1 "register_operand" "")
4438 6 "cris_extend_operator"
4440 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4441 (match_operand:SI 3 "cris_bdap_operand" "")
4443 (set (match_operand:SI 4 "register_operand" "")
4444 (plus:SI (match_dup 2)
4446 "(rtx_equal_p (operands[4], operands[2])
4447 || rtx_equal_p (operands[4], operands[3]))"
4448 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4449 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))]
4451 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
4452 replace_equiv_address (XEXP (operands[6], 0),
4454 cris_order_for_addsi3 (operands, 2);
4457 ;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound)
4461 [(set (match_operand 0 "register_operand" "")
4463 7 "cris_plus_or_bound_operator"
4465 6 "cris_extend_operator"
4467 (mult:SI (match_operand:SI 2 "register_operand" "")
4468 (match_operand:SI 3 "const_int_operand" ""))
4469 (match_operand:SI 4 "register_operand" "")))])
4470 (match_operand 1 "register_operand" "")]))
4471 (set (match_operand:SI 5 "register_operand" "")
4472 (plus:SI (mult:SI (match_dup 2)
4475 "REG_P (operands[4]) && REG_P (operands[5])
4476 && REGNO (operands[5]) == REGNO (operands[4])"
4477 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4479 (set (match_dup 0) (match_op_dup 6 [(match_dup 8) (match_dup 1)]))]
4480 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
4481 replace_equiv_address (XEXP (operands[6], 0),
4484 ;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound)
4488 [(set (match_operand 0 "register_operand" "")
4490 6 "cris_plus_or_bound_operator"
4492 5 "cris_extend_operator"
4494 (match_operand:SI 2 "cris_bdap_operand" "")
4495 (match_operand:SI 3 "cris_bdap_operand" "")))])
4496 (match_operand 1 "register_operand" "")]))
4497 (set (match_operand:SI 4 "register_operand" "")
4498 (plus:SI (match_dup 2)
4500 "(rtx_equal_p (operands[4], operands[2])
4501 || rtx_equal_p (operands[4], operands[3]))"
4502 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4503 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4505 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[5]), GET_MODE (operands[5]),
4506 replace_equiv_address (XEXP (operands[5], 0),
4508 cris_order_for_addsi3 (operands, 2);
4511 ;; Splits for addressing prefixes that have no side-effects, so we can
4512 ;; fill a delay slot. Never split if we lose something, though.
4515 ;; move [indirect_ref],rx
4516 ;; where indirect ref = {const, [r+], [r]}, it costs as much as
4517 ;; move indirect_ref,rx
4519 ;; Take care not to allow indirect_ref = register.
4521 ;; We're not allowed to generate copies of registers with different mode
4522 ;; until after reload; copying pseudos upsets reload. CVS as of
4523 ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in
4524 ;; cselib_invalidate_regno.
4526 (define_split ; indir_to_reg_split
4527 [(set (match_operand 0 "register_operand" "")
4528 (match_operand 1 "indirect_operand" ""))]
4530 && REG_P (operands[0])
4531 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4532 && (MEM_P (XEXP (operands[1], 0)) || CONSTANT_P (XEXP (operands[1], 0)))
4533 && REGNO (operands[0]) < CRIS_LAST_GENERAL_REGISTER"
4534 [(set (match_dup 2) (match_dup 4))
4535 (set (match_dup 0) (match_dup 3))]
4536 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4537 operands[3] = replace_equiv_address (operands[1], operands[2]);
4538 operands[4] = XEXP (operands[1], 0);")
4540 ;; As the above, but MOVS and MOVU.
4543 [(set (match_operand 0 "register_operand" "")
4545 4 "cris_extend_operator"
4546 [(match_operand 1 "indirect_operand" "")]))]
4548 && REG_P (operands[0])
4549 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4550 && (MEM_P (XEXP (operands[1], 0))
4551 || CONSTANT_P (XEXP (operands[1], 0)))"
4552 [(set (match_dup 2) (match_dup 5))
4553 (set (match_dup 0) (match_op_dup 4 [(match_dup 3)]))]
4554 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4555 operands[3] = replace_equiv_address (XEXP (operands[4], 0), operands[2]);
4556 operands[5] = XEXP (operands[1], 0);")
4558 ;; Various peephole optimizations.
4560 ;; Watch out: when you exchange one set of instructions for another, the
4561 ;; condition codes setting must be the same, or you have to CC_INIT or
4562 ;; whatever is appropriate, in the pattern before you emit the
4563 ;; assembly text. This is best done here, not in cris_notice_update_cc,
4564 ;; to keep changes local to their cause.
4566 ;; Do not add patterns that you do not know will be matched.
4567 ;; Please also add a self-contained testcase.
4569 ;; We have trouble with and:s and shifts. Maybe something is broken in
4570 ;; gcc? Or it could just be that bit-field insn expansion is a bit
4571 ;; suboptimal when not having extzv insns.
4572 ;; Testcase for the following four peepholes: gcc.dg/cris-peep2-xsrand.c
4574 (define_peephole2 ; asrandb (peephole casesi+31)
4575 [(set (match_operand:SI 0 "register_operand" "")
4576 (ashiftrt:SI (match_dup 0)
4577 (match_operand:SI 1 "const_int_operand" "")))
4579 (and:SI (match_dup 0)
4580 (match_operand 2 "const_int_operand" "")))]
4581 "INTVAL (operands[2]) > 31
4582 && INTVAL (operands[2]) < 255
4583 && INTVAL (operands[1]) > 23
4584 /* Check that the and-operation enables us to use logical-shift. */
4585 && (INTVAL (operands[2])
4586 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
4587 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4588 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
4589 ;; FIXME: CC0 is valid except for the M bit.
4591 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
4592 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
4595 (define_peephole2 ; asrandw (peephole casesi+32)
4596 [(set (match_operand:SI 0 "register_operand" "")
4597 (ashiftrt:SI (match_dup 0)
4598 (match_operand:SI 1 "const_int_operand" "")))
4600 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4601 "INTVAL (operands[2]) > 31
4602 && INTVAL (operands[2]) < 65535
4603 && INTVAL (operands[2]) != 255
4604 && INTVAL (operands[1]) > 15
4605 /* Check that the and-operation enables us to use logical-shift. */
4606 && (INTVAL (operands[2])
4607 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
4608 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4609 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
4610 ;; FIXME: CC0 is valid except for the M bit.
4612 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4613 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
4616 (define_peephole2 ; lsrandb (peephole casesi+33)
4617 [(set (match_operand:SI 0 "register_operand" "")
4618 (lshiftrt:SI (match_dup 0)
4619 (match_operand:SI 1 "const_int_operand" "")))
4621 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4622 "INTVAL (operands[2]) > 31
4623 && INTVAL (operands[2]) < 255
4624 && INTVAL (operands[1]) > 23"
4625 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4626 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
4627 ;; FIXME: CC0 is valid except for the M bit.
4629 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
4630 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
4633 (define_peephole2 ; lsrandw (peephole casesi+34)
4634 [(set (match_operand:SI 0 "register_operand" "")
4635 (lshiftrt:SI (match_dup 0)
4636 (match_operand:SI 1 "const_int_operand" "")))
4638 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4639 "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535
4640 && INTVAL (operands[2]) != 255
4641 && INTVAL (operands[1]) > 15"
4642 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4643 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
4644 ;; FIXME: CC0 is valid except for the M bit.
4646 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4647 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
4655 ;; move [rx=rx+n],ry
4656 ;; when -128 <= n <= 127.
4657 ;; This will reduce the size of the assembler code for n = [-128..127],
4658 ;; and speed up accordingly. Don't match if the previous insn is
4659 ;; (set rx rz) because that combination is matched by another peephole.
4660 ;; No stable test-case.
4662 (define_peephole2 ; moversideqi (peephole casesi+35)
4663 [(set (match_operand:SI 0 "register_operand" "")
4664 (plus:SI (match_operand:SI 1 "register_operand" "")
4665 (match_operand:SI 2 "const_int_operand" "")))
4666 (set (match_operand 3 "register_operand" "")
4667 (match_operator 4 "cris_mem_op" [(match_dup 0)]))]
4668 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
4669 && REGNO (operands[3]) != REGNO (operands[0])
4670 && (BASE_P (operands[1]) || BASE_P (operands[2]))
4671 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4672 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4673 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)
4674 && TARGET_SIDE_EFFECT_PREFIXES"
4676 [(set (match_dup 3) (match_dup 5))
4677 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4678 ;; Checking the previous insn is a bit too awkward for the condition.
4680 rtx prev = prev_nonnote_insn (curr_insn);
4681 if (prev != NULL_RTX)
4683 rtx set = single_set (prev);
4685 && REG_S_P (SET_DEST (set))
4686 && REGNO (SET_DEST (set)) == REGNO (operands[0])
4687 && REG_S_P (SET_SRC (set)))
4691 = replace_equiv_address (operands[4],
4692 gen_rtx_PLUS (SImode,
4693 operands[1], operands[2]));
4696 ;; Vice versa: move ry,[rx=rx+n]
4698 (define_peephole2 ; movemsideqi (peephole casesi+36)
4699 [(set (match_operand:SI 0 "register_operand" "")
4700 (plus:SI (match_operand:SI 1 "register_operand" "")
4701 (match_operand:SI 2 "const_int_operand" "")))
4702 (set (match_operator 3 "cris_mem_op" [(match_dup 0)])
4703 (match_operand 4 "register_operand" ""))]
4704 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
4705 && REGNO (operands[4]) != REGNO (operands[0])
4706 && (BASE_P (operands[1]) || BASE_P (operands[2]))
4707 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4708 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4709 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)
4710 && TARGET_SIDE_EFFECT_PREFIXES"
4712 [(set (match_dup 5) (match_dup 4))
4713 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4715 = replace_equiv_address (operands[3],
4716 gen_rtx_PLUS (SImode,
4717 operands[1], operands[2]));")
4719 ;; As above, change:
4723 ;; op.d [rx=rx+n],ry
4724 ;; Saves when n = [-128..127].
4726 ;; Splitting and joining combinations for side-effect modes are slightly
4727 ;; out of hand. They probably will not save the time they take typing in,
4728 ;; not to mention the bugs that creep in. FIXME: Get rid of as many of
4729 ;; the splits and peepholes as possible.
4730 ;; No stable test-case.
4732 (define_peephole2 ; mover2side (peephole casesi+37)
4733 [(set (match_operand:SI 0 "register_operand" "")
4734 (plus:SI (match_operand:SI 1 "register_operand" "")
4735 (match_operand:SI 2 "const_int_operand" "")))
4736 (set (match_operand 3 "register_operand" "")
4737 (match_operator 4 "cris_orthogonal_operator"
4740 5 "cris_mem_op" [(match_dup 0)])]))]
4741 ;; FIXME: What about DFmode?
4742 ;; Change to GET_MODE_SIZE (GET_MODE (operands[3])) <= UNITS_PER_WORD?
4743 "GET_MODE (operands[3]) != DImode
4744 && REGNO (operands[0]) != REGNO (operands[3])
4745 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4746 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4747 && INTVAL (operands[2]) >= -128
4748 && INTVAL (operands[2]) <= 127
4749 && TARGET_SIDE_EFFECT_PREFIXES"
4751 [(set (match_dup 3) (match_op_dup 4 [(match_dup 3) (match_dup 6)]))
4752 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4754 = replace_equiv_address (operands[5],
4755 gen_rtx_PLUS (SImode,
4756 operands[1], operands[2]));")
4758 ;; Sometimes, for some reason the pattern
4762 ;; will occur. Solve this, and likewise for to-memory.
4763 ;; No stable test-case.
4765 (define_peephole2 ; moverside (peephole casesi+38)
4766 [(set (match_operand:SI 0 "register_operand" "")
4767 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
4769 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
4770 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
4771 (set (match_operand 4 "register_operand" "")
4772 (match_operator 5 "cris_mem_op" [(match_dup 0)]))]
4773 "(rtx_equal_p (operands[2], operands[0])
4774 || rtx_equal_p (operands[3], operands[0]))
4775 && cris_side_effect_mode_ok (PLUS, operands, 0,
4776 (REG_S_P (operands[1])
4778 : (rtx_equal_p (operands[2], operands[0])
4780 (! REG_S_P (operands[1])
4782 : (rtx_equal_p (operands[2], operands[0])
4786 [(set (match_dup 4) (match_dup 6))
4787 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
4790 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
4792 /* Make sure we have canonical RTX so we match the insn pattern -
4793 not a constant in the first operand. We also require the order
4794 (plus reg mem) to match the final pattern. */
4795 if (CONSTANT_P (otherop) || MEM_P (otherop))
4797 operands[7] = operands[1];
4798 operands[8] = otherop;
4802 operands[7] = otherop;
4803 operands[8] = operands[1];
4806 = replace_equiv_address (operands[5],
4807 gen_rtx_PLUS (SImode,
4808 operands[7], operands[8]));
4811 ;; As above but to memory.
4812 ;; FIXME: Split movemside and moverside into variants and prune
4813 ;; the ones that don't trig.
4814 ;; No stable test-case.
4816 (define_peephole2 ; movemside (peephole casesi+39)
4817 [(set (match_operand:SI 0 "register_operand" "")
4818 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
4820 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
4821 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
4822 (set (match_operator 4 "cris_mem_op" [(match_dup 0)])
4823 (match_operand 5 "register_operand" ""))]
4824 "(rtx_equal_p (operands[2], operands[0])
4825 || rtx_equal_p (operands[3], operands[0]))
4826 && cris_side_effect_mode_ok (PLUS, operands, 0,
4827 (REG_S_P (operands[1])
4829 : (rtx_equal_p (operands[2], operands[0])
4831 (! REG_S_P (operands[1])
4833 : (rtx_equal_p (operands[2], operands[0])
4837 [(set (match_dup 6) (match_dup 5))
4838 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
4841 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
4843 /* Make sure we have canonical RTX so we match the insn pattern -
4844 not a constant in the first operand. We also require the order
4845 (plus reg mem) to match the final pattern. */
4846 if (CONSTANT_P (otherop) || MEM_P (otherop))
4848 operands[7] = operands[1];
4849 operands[8] = otherop;
4853 operands[7] = otherop;
4854 operands[8] = operands[1];
4857 = replace_equiv_address (operands[4],
4858 gen_rtx_PLUS (SImode,
4859 operands[7], operands[8]));
4862 ;; Another spotted bad code:
4865 ;; No stable test-case.
4867 (define_peephole2 ; movei (peephole casesi+42)
4868 [(set (match_operand:SI 0 "register_operand" "")
4869 (match_operand:SI 1 "register_operand" ""))
4870 (set (match_operand 2 "register_operand" "")
4871 (match_operator 3 "cris_mem_op" [(match_dup 0)]))]
4872 "REGNO (operands[0]) == REGNO (operands[2])
4873 && (REGNO_REG_CLASS (REGNO (operands[0]))
4874 == REGNO_REG_CLASS (REGNO (operands[1])))
4875 && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD"
4876 [(set (match_dup 2) (match_dup 4))]
4877 "operands[4] = replace_equiv_address (operands[3], operands[1]);")
4879 ;; move.d [r10+16],r9
4882 ;; and.d [r10+16],r12,r9
4883 ;; With generalization of the operation, the size and the addressing mode.
4884 ;; This seems to be the result of a quirk in register allocation
4885 ;; missing the three-operand cases when having different predicates.
4886 ;; Maybe that it matters that it is a commutative operation.
4887 ;; This pattern helps that situation, but there's still the increased
4888 ;; register pressure.
4889 ;; Note that adding the noncommutative variant did not show any matches
4890 ;; in ipps and cc1, so it's not here.
4891 ;; No stable test-case.
4893 (define_peephole2 ; op3 (peephole casesi+44)
4894 [(set (match_operand 0 "register_operand" "")
4898 (match_operand:SI 1 "cris_bdap_biap_operand" "")
4899 (match_operand:SI 2 "cris_bdap_biap_operand" ""))]))
4902 5 "cris_commutative_orth_op"
4903 [(match_operand 3 "register_operand" "")
4904 (match_operand 4 "register_operand" "")]))]
4905 "(rtx_equal_p (operands[3], operands[0])
4906 || rtx_equal_p (operands[4], operands[0]))
4907 && ! rtx_equal_p (operands[3], operands[4])
4908 && (REG_S_P (operands[1]) || REG_S_P (operands[2]))
4909 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD"
4910 [(set (match_dup 0) (match_op_dup 5 [(match_dup 7) (match_dup 6)]))]
4912 = rtx_equal_p (operands[3], operands[0]) ? operands[4] : operands[3];")
4914 ;; I cannot tell GCC (2.1, 2.7.2) how to correctly reload an instruction
4916 ;; and.b some_byte,const,reg_32
4917 ;; where reg_32 is the destination of the "three-address" code optimally.
4919 ;; movu.b some_byte,reg_32
4920 ;; and.b const,reg_32
4921 ;; but is turns into:
4922 ;; move.b some_byte,reg_32
4923 ;; and.d const,reg_32
4925 ;; Testcases: gcc.dg/cris-peep2-andu1.c gcc.dg/cris-peep2-andu2.c
4927 (define_peephole2 ; andu (casesi+45)
4928 [(set (match_operand:SI 0 "register_operand" "")
4929 (match_operand:SI 1 "nonimmediate_operand" ""))
4930 (set (match_operand:SI 2 "register_operand" "")
4931 (and:SI (match_dup 0)
4932 (match_operand:SI 3 "const_int_operand" "")))]
4933 ;; Since the size of the memory access could be made different here,
4934 ;; don't do this for a mem-volatile access.
4935 "REGNO (operands[2]) == REGNO (operands[0])
4936 && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0
4937 && !CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'I')
4938 && !side_effects_p (operands[1])"
4939 ;; FIXME: CC0 valid except for M (i.e. CC_NOT_NEGATIVE).
4940 [(set (match_dup 0) (match_dup 4))
4941 (set (match_dup 5) (match_dup 6))]
4943 enum machine_mode zmode = INTVAL (operands[3]) <= 255 ? QImode : HImode;
4944 enum machine_mode amode
4945 = CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'O') ? SImode : zmode;
4947 = (REG_S_P (operands[1])
4948 ? gen_rtx_REG (zmode, REGNO (operands[1]))
4949 : adjust_address (operands[1], zmode, 0));
4951 = gen_rtx_ZERO_EXTEND (SImode, op1);
4952 operands[5] = gen_rtx_REG (amode, REGNO (operands[0]));
4954 = gen_rtx_AND (amode, gen_rtx_REG (amode, REGNO (operands[0])),
4955 GEN_INT (trunc_int_for_mode (INTVAL (operands[3]),
4957 ? QImode : amode)));
4960 ;; Try and avoid GOTPLT reads escaping a call: transform them into
4961 ;; PLT. Curiously (but thankfully), peepholes for instructions
4962 ;; *without side-effects* that just feed a call (or call_value) are
4963 ;; not matched neither in a build or test-suite, so those patterns are
4966 ;; A "normal" move where we don't check the consumer.
4968 (define_peephole2 ; gotplt-to-plt
4970 (match_operand:SI 0 "register_operand" "")
4974 (reg:SI CRIS_GOT_REGNUM)
4976 (unspec:SI [(match_operand:SI 2 "cris_general_operand_or_symbol" "")]
4977 CRIS_UNSPEC_PLTGOTREAD)))]))]
4979 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
4980 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)"
4981 [(set (match_dup 0) (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL)))
4982 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))]
4985 ;; And one set with a side-effect getting the PLTGOT offset.
4986 ;; First call and call_value variants.
4988 (define_peephole2 ; gotplt-to-plt-side-call
4991 (match_operand:SI 0 "register_operand" "")
4995 (reg:SI CRIS_GOT_REGNUM)
4997 (unspec:SI [(match_operand:SI
4998 2 "cris_general_operand_or_symbol" "")]
4999 CRIS_UNSPEC_PLTGOTREAD)))]))
5000 (set (match_operand:SI 3 "register_operand" "")
5001 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5003 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])
5004 (parallel [(call (mem:QI (match_dup 0))
5005 (match_operand 4 "" ""))
5006 (clobber (reg:SI CRIS_SRP_REGNUM))])]
5008 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5009 && peep2_reg_dead_p (2, operands[0])"
5010 [(parallel [(call (mem:QI (match_dup 1))
5012 (clobber (reg:SI CRIS_SRP_REGNUM))
5014 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5016 (unspec:SI [(match_dup 2)]
5017 CRIS_UNSPEC_PLTGOTREAD))))])]
5020 (define_peephole2 ; gotplt-to-plt-side-call-value
5023 (match_operand:SI 0 "register_operand" "")
5027 (reg:SI CRIS_GOT_REGNUM)
5029 (unspec:SI [(match_operand:SI
5030 2 "cris_general_operand_or_symbol" "")]
5031 CRIS_UNSPEC_PLTGOTREAD)))]))
5032 (set (match_operand:SI 3 "register_operand" "")
5033 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5035 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])
5036 (parallel [(set (match_operand 5 "" "")
5037 (call (mem:QI (match_dup 0))
5038 (match_operand 4 "" "")))
5039 (clobber (reg:SI CRIS_SRP_REGNUM))])]
5041 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5042 && peep2_reg_dead_p (2, operands[0])"
5043 [(parallel [(set (match_dup 5)
5044 (call (mem:QI (match_dup 1))
5046 (clobber (reg:SI CRIS_SRP_REGNUM))
5048 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5050 (unspec:SI [(match_dup 2)]
5051 CRIS_UNSPEC_PLTGOTREAD))))])]
5054 (define_peephole2 ; gotplt-to-plt-side
5057 (match_operand:SI 0 "register_operand" "")
5061 (reg:SI CRIS_GOT_REGNUM)
5063 (unspec:SI [(match_operand:SI
5064 2 "cris_general_operand_or_symbol" "")]
5065 CRIS_UNSPEC_PLTGOTREAD)))]))
5066 (set (match_operand:SI 3 "register_operand" "")
5067 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5069 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])]
5071 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5072 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)"
5074 (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD)))
5075 (set (match_dup 3) (plus:SI (match_dup 3) (reg:SI CRIS_GOT_REGNUM)))
5077 (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL)))
5078 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))]
5083 ;; comment-start: ";; "
5084 ;; eval: (set-syntax-table (copy-sequence (syntax-table)))
5085 ;; eval: (modify-syntax-entry ?[ "(]")
5086 ;; eval: (modify-syntax-entry ?] ")[")
5087 ;; eval: (modify-syntax-entry ?{ "(}")
5088 ;; eval: (modify-syntax-entry ?} "){")
5089 ;; eval: (setq indent-tabs-mode t)