1 ;; Predicate definitions for the Blackfin.
2 ;; Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc.
3 ;; Contributed by Analog Devices.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Return nonzero iff OP is one of the integer constants 1 or 2.
22 (define_predicate "pos_scale_operand"
23 (and (match_code "const_int")
24 (match_test "INTVAL (op) == 1 || INTVAL (op) == 2")))
26 ;; Return nonzero iff OP is one of the integer constants 2 or 4.
27 (define_predicate "scale_by_operand"
28 (and (match_code "const_int")
29 (match_test "INTVAL (op) == 2 || INTVAL (op) == 4")))
31 ;; Return nonzero if OP is a constant that consists of two parts; lower
32 ;; bits all zero and upper bits all ones. In this case, we can perform
33 ;; an AND operation with a sequence of two shifts. Don't return nonzero
34 ;; if the constant would be cheap to load.
35 (define_predicate "highbits_operand"
36 (and (match_code "const_int")
37 (match_test "log2constp (-INTVAL (op)) && !satisfies_constraint_Ks7 (op)")))
39 ;; Return nonzero if OP is suitable as a right-hand side operand for an
41 (define_predicate "rhs_andsi3_operand"
42 (ior (match_operand 0 "register_operand")
43 (and (match_code "const_int")
44 (match_test "log2constp (~INTVAL (op)) || INTVAL (op) == 255 || INTVAL (op) == 65535"))))
46 ;; Return nonzero if OP is a register or a constant with exactly one bit
48 (define_predicate "regorlog2_operand"
49 (ior (match_operand 0 "register_operand")
50 (and (match_code "const_int")
51 (match_test "log2constp (INTVAL (op))"))))
53 ;; Return nonzero if OP is a register or an integer constant.
54 (define_predicate "reg_or_const_int_operand"
55 (ior (match_operand 0 "register_operand")
56 (match_code "const_int")))
58 (define_predicate "const01_operand"
59 (and (match_code "const_int")
60 (match_test "op == const0_rtx || op == const1_rtx")))
62 (define_predicate "vec_shift_operand"
63 (ior (and (match_code "const_int")
64 (match_test "INTVAL (op) >= -16 && INTVAL (op) < 15"))
65 (match_operand 0 "register_operand")))
67 ;; Like register_operand, but make sure that hard regs have a valid mode.
68 (define_predicate "valid_reg_operand"
69 (match_operand 0 "register_operand")
71 if (GET_CODE (op) == SUBREG)
73 if (REGNO (op) < FIRST_PSEUDO_REGISTER)
74 return HARD_REGNO_MODE_OK (REGNO (op), mode);
78 ;; Return nonzero if OP is a D register.
79 (define_predicate "d_register_operand"
80 (and (match_code "reg")
81 (match_test "D_REGNO_P (REGNO (op))")))
83 ;; Return nonzero if OP is a LC register.
84 (define_predicate "lc_register_operand"
85 (and (match_code "reg")
86 (match_test "REGNO (op) == REG_LC0 || REGNO (op) == REG_LC1")))
88 ;; Return nonzero if OP is a LT register.
89 (define_predicate "lt_register_operand"
90 (and (match_code "reg")
91 (match_test "REGNO (op) == REG_LT0 || REGNO (op) == REG_LT1")))
93 ;; Return nonzero if OP is a LB register.
94 (define_predicate "lb_register_operand"
95 (and (match_code "reg")
96 (match_test "REGNO (op) == REG_LB0 || REGNO (op) == REG_LB1")))
98 ;; Return nonzero if OP is a register or a 7-bit signed constant.
99 (define_predicate "reg_or_7bit_operand"
100 (ior (match_operand 0 "register_operand")
101 (and (match_code "const_int")
102 (match_test "satisfies_constraint_Ks7 (op)"))))
104 ;; Return nonzero if OP is a register other than DREG and PREG.
105 (define_predicate "nondp_register_operand"
106 (match_operand 0 "register_operand")
109 if (GET_CODE (op) == SUBREG)
110 op = SUBREG_REG (op);
113 return (regno >= FIRST_PSEUDO_REGISTER || !DP_REGNO_P (regno));
116 ;; Return nonzero if OP is a register other than DREG and PREG, or MEM.
117 (define_predicate "nondp_reg_or_memory_operand"
118 (ior (match_operand 0 "nondp_register_operand")
119 (match_operand 0 "memory_operand")))
121 ;; Return nonzero if OP is a register or, when negated, a 7-bit signed
123 (define_predicate "reg_or_neg7bit_operand"
124 (ior (match_operand 0 "register_operand")
125 (and (match_code "const_int")
126 (match_test "satisfies_constraint_KN7 (op)"))))
128 ;; Used for secondary reloads, this function returns 1 if OP is of the
129 ;; form (plus (fp) (const_int)).
130 (define_predicate "fp_plus_const_operand"
138 && (REGNO (op1) == FRAME_POINTER_REGNUM
139 || REGNO (op1) == STACK_POINTER_REGNUM)
140 && GET_CODE (op2) == CONST_INT);
143 ;; Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
144 ;; possibly with an offset.
145 (define_predicate "symbolic_operand"
146 (ior (match_code "symbol_ref,label_ref")
147 (and (match_code "const")
148 (match_test "GET_CODE (XEXP (op,0)) == PLUS
149 && (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
150 || GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF)
151 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT"))))
153 ;; Returns 1 if OP is a plain constant or matched by symbolic_operand.
154 (define_predicate "symbolic_or_const_operand"
155 (ior (match_code "const_int,const_double")
156 (match_operand 0 "symbolic_operand")))
158 ;; Returns 1 if OP is a SYMBOL_REF.
159 (define_predicate "symbol_ref_operand"
160 (match_code "symbol_ref"))
162 ;; True for any non-virtual or eliminable register. Used in places where
163 ;; instantiation of such a register may cause the pattern to not be recognized.
164 (define_predicate "register_no_elim_operand"
165 (match_operand 0 "register_operand")
167 if (GET_CODE (op) == SUBREG)
168 op = SUBREG_REG (op);
169 return !(op == arg_pointer_rtx
170 || op == frame_pointer_rtx
171 || (REGNO (op) >= FIRST_PSEUDO_REGISTER
172 && REGNO (op) <= LAST_VIRTUAL_REGISTER));
175 ;; Test for an operator valid in a conditional branch
176 (define_predicate "bfin_cbranch_operator"
177 (match_code "eq,ne"))
179 ;; The following two are used to compute the addrtype attribute. They return
180 ;; true if passed a memory address usable for a 16-bit load or store using a
181 ;; P or I register, respectively. If neither matches, we know we have a
182 ;; 32-bit instruction.
183 (define_predicate "mem_p_address_operand"
186 if (effective_address_32bit_p (op, mode))
189 if (GET_CODE (op) == PLUS || GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
191 gcc_assert (REG_P (op));
195 (define_predicate "mem_i_address_operand"
198 if (effective_address_32bit_p (op, mode))
201 if (GET_CODE (op) == PLUS || GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
203 gcc_assert (REG_P (op));