| blob | fed9efee89eb0cb308ccfbb9feeeac5c234c6681 |
1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;;
6 ;; This file is part of GCC.
7 ;;
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; any later version.
12 ;;
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17 ;;
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ;; Uses of UNSPEC in this file:
26 (define_constants
27 [(UNSPEC_ARG_HOME 0)
28 (UNSPEC_LDGP1 1)
29 (UNSPEC_INSXH 2)
30 (UNSPEC_MSKXH 3)
31 (UNSPEC_CVTQL 4)
32 (UNSPEC_CVTLQ 5)
33 (UNSPEC_UMK_LAUM 6)
34 (UNSPEC_UMK_LALM 7)
35 (UNSPEC_UMK_LAL 8)
36 (UNSPEC_UMK_LOAD_CIW 9)
37 (UNSPEC_LDGP2 10)
38 (UNSPEC_LITERAL 11)
39 (UNSPEC_LITUSE 12)
40 (UNSPEC_SIBCALL 13)
41 (UNSPEC_SYMBOL 14)
43 ;; TLS Support
44 (UNSPEC_TLSGD_CALL 15)
45 (UNSPEC_TLSLDM_CALL 16)
46 (UNSPEC_TLSGD 17)
47 (UNSPEC_TLSLDM 18)
48 (UNSPEC_DTPREL 19)
49 (UNSPEC_TPREL 20)
50 (UNSPEC_TP 21)
52 ;; Builtins
53 (UNSPEC_CMPBGE 22)
54 (UNSPEC_ZAP 23)
55 (UNSPEC_AMASK 24)
56 (UNSPEC_IMPLVER 25)
57 (UNSPEC_PERR 26)
58 (UNSPEC_COPYSIGN 27)
60 ;; Atomic operations
61 (UNSPEC_MB 28)
62 (UNSPEC_ATOMIC 31)
63 (UNSPEC_CMPXCHG 32)
64 (UNSPEC_XCHG 33)
65 ])
67 ;; UNSPEC_VOLATILE:
69 (define_constants
70 [(UNSPECV_IMB 0)
71 (UNSPECV_BLOCKAGE 1)
72 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
73 (UNSPECV_LONGJMP 3) ; builtin_longjmp
74 (UNSPECV_TRAPB 4)
75 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
76 (UNSPECV_REALIGN 6)
77 (UNSPECV_EHR 7) ; exception_receiver
78 (UNSPECV_MCOUNT 8)
79 (UNSPECV_FORCE_MOV 9)
80 (UNSPECV_LDGP1 10)
81 (UNSPECV_PLDGP2 11) ; prologue ldgp
82 (UNSPECV_SET_TP 12)
83 (UNSPECV_RPCC 13)
84 (UNSPECV_SETJMPR_ER 14) ; builtin_setjmp_receiver fragment
85 (UNSPECV_LL 15) ; load-locked
86 (UNSPECV_SC 16) ; store-conditional
87 ])
89 ;; On non-BWX targets, CQImode must be handled the similarly to HImode
90 ;; when generating reloads.
91 (define_mode_iterator RELOAD12 [QI HI CQI])
92 (define_mode_attr reloadmode [(QI "qi") (HI "hi") (CQI "hi")])
94 ;; Other mode iterators
95 (define_mode_iterator I12MODE [QI HI])
96 (define_mode_iterator I48MODE [SI DI])
97 (define_mode_attr modesuffix [(SI "l") (DI "q")])
99 ;; Where necessary, the suffixes _le and _be are used to distinguish between
100 ;; little-endian and big-endian patterns.
101 ;;
102 ;; Note that the Unicos/Mk assembler does not support the following
103 ;; opcodes: mov, fmov, nop, fnop, unop.
104 \f
105 ;; Processor type -- this attribute must exactly match the processor_type
106 ;; enumeration in alpha.h.
108 (define_attr "tune" "ev4,ev5,ev6"
109 (const (symbol_ref "alpha_tune")))
111 ;; Define an insn type attribute. This is used in function unit delay
112 ;; computations, among other purposes. For the most part, we use the names
113 ;; defined in the EV4 documentation, but add a few that we have to know about
114 ;; separately.
116 (define_attr "type"
117 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,
118 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c,
119 multi,none"
120 (const_string "iadd"))
122 ;; Describe a user's asm statement.
123 (define_asm_attributes
124 [(set_attr "type" "multi")])
126 ;; Define the operand size an insn operates on. Used primarily by mul
127 ;; and div operations that have size dependent timings.
129 (define_attr "opsize" "si,di,udi"
130 (const_string "di"))
132 ;; The TRAP attribute marks instructions that may generate traps
133 ;; (which are imprecise and may need a trapb if software completion
134 ;; is desired).
136 (define_attr "trap" "no,yes"
137 (const_string "no"))
139 ;; The ROUND_SUFFIX attribute marks which instructions require a
140 ;; rounding-mode suffix. The value NONE indicates no suffix,
141 ;; the value NORMAL indicates a suffix controlled by alpha_fprm.
143 (define_attr "round_suffix" "none,normal,c"
144 (const_string "none"))
146 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
147 ;; NONE no suffix
148 ;; SU accepts only /su (cmpt et al)
149 ;; SUI accepts only /sui (cvtqt and cvtqs)
150 ;; V_SV accepts /v and /sv (cvtql only)
151 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
152 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
153 ;;
154 ;; The actual suffix emitted is controlled by alpha_fptm.
156 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
157 (const_string "none"))
159 ;; The length of an instruction sequence in bytes.
161 (define_attr "length" ""
162 (const_int 4))
164 ;; The USEGP attribute marks instructions that have relocations that use
165 ;; the GP.
167 (define_attr "usegp" "no,yes"
168 (cond [(eq_attr "type" "ldsym,jsr")
169 (const_string "yes")
170 (eq_attr "type" "ild,fld,ist,fst")
171 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
172 ]
173 (const_string "no")))
175 ;; The CANNOT_COPY attribute marks instructions with relocations that
176 ;; cannot easily be duplicated. This includes insns with gpdisp relocs
177 ;; since they have to stay in 1-1 correspondence with one another. This
178 ;; also includes jsr insns, since they must stay in correspondence with
179 ;; the immediately following gpdisp instructions.
181 (define_attr "cannot_copy" "false,true"
182 (const_string "false"))
183 \f
184 ;; Include scheduling descriptions.
186 (include "ev4.md")
187 (include "ev5.md")
188 (include "ev6.md")
190 \f
191 ;; Operand and operator predicates and constraints
193 (include "predicates.md")
194 (include "constraints.md")
196 \f
197 ;; First define the arithmetic insns. Note that the 32-bit forms also
198 ;; sign-extend.
200 ;; Handle 32-64 bit extension from memory to a floating point register
201 ;; specially, since this occurs frequently in int->double conversions.
202 ;;
203 ;; Note that while we must retain the =f case in the insn for reload's
204 ;; benefit, it should be eliminated after reload, so we should never emit
205 ;; code for that case. But we don't reject the possibility.
207 (define_expand "extendsidi2"
208 [(set (match_operand:DI 0 "register_operand" "")
209 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
210 ""
211 "")
213 (define_insn "*cvtlq"
214 [(set (match_operand:DI 0 "register_operand" "=f")
215 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
216 UNSPEC_CVTLQ))]
217 ""
218 "cvtlq %1,%0"
219 [(set_attr "type" "fadd")])
221 (define_insn "*extendsidi2_1"
222 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
223 (sign_extend:DI
224 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
225 ""
226 "@
227 addl $31,%1,%0
228 ldl %0,%1
229 lds %0,%1\;cvtlq %0,%0"
230 [(set_attr "type" "iadd,ild,fld")
231 (set_attr "length" "*,*,8")])
233 (define_split
234 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
235 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
236 "reload_completed"
237 [(set (match_dup 2) (match_dup 1))
238 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
239 {
240 operands[1] = adjust_address (operands[1], SFmode, 0);
241 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
242 })
244 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
245 ;; reload when converting fp->int.
247 (define_peephole2
248 [(set (match_operand:SI 0 "hard_int_register_operand" "")
249 (match_operand:SI 1 "memory_operand" ""))
250 (set (match_operand:DI 2 "hard_int_register_operand" "")
251 (sign_extend:DI (match_dup 0)))]
252 "true_regnum (operands[0]) == true_regnum (operands[2])
253 || peep2_reg_dead_p (2, operands[0])"
254 [(set (match_dup 2)
255 (sign_extend:DI (match_dup 1)))]
256 "")
258 ;; Don't say we have addsi3 if optimizing. This generates better code. We
259 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
260 (define_expand "addsi3"
261 [(set (match_operand:SI 0 "register_operand" "")
262 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
263 (match_operand:SI 2 "add_operand" "")))]
264 "! optimize"
265 "")
267 (define_insn "*addsi_internal"
268 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
269 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
270 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
271 ""
272 "@
273 addl %r1,%2,%0
274 subl %r1,%n2,%0
275 lda %0,%2(%r1)
276 ldah %0,%h2(%r1)")
278 (define_split
279 [(set (match_operand:SI 0 "register_operand" "")
280 (plus:SI (match_operand:SI 1 "register_operand" "")
281 (match_operand:SI 2 "const_int_operand" "")))]
282 "! add_operand (operands[2], SImode)"
283 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
284 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
285 {
286 HOST_WIDE_INT val = INTVAL (operands[2]);
287 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
288 HOST_WIDE_INT rest = val - low;
290 operands[3] = GEN_INT (rest);
291 operands[4] = GEN_INT (low);
292 })
294 (define_insn "*addsi_se"
295 [(set (match_operand:DI 0 "register_operand" "=r,r")
296 (sign_extend:DI
297 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
298 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
299 ""
300 "@
301 addl %r1,%2,%0
302 subl %r1,%n2,%0")
304 (define_insn "*addsi_se2"
305 [(set (match_operand:DI 0 "register_operand" "=r,r")
306 (sign_extend:DI
307 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
308 (match_operand:DI 2 "sext_add_operand" "rI,O"))
309 0)))]
310 ""
311 "@
312 addl %r1,%2,%0
313 subl %r1,%n2,%0")
315 (define_split
316 [(set (match_operand:DI 0 "register_operand" "")
317 (sign_extend:DI
318 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
319 (match_operand:SI 2 "const_int_operand" ""))))
320 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
321 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
322 && INTVAL (operands[2]) % 4 == 0"
323 [(set (match_dup 3) (match_dup 4))
324 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
325 (match_dup 5))
326 (match_dup 1))))]
327 {
328 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
329 int mult = 4;
331 if (val % 2 == 0)
332 val /= 2, mult = 8;
334 operands[4] = GEN_INT (val);
335 operands[5] = GEN_INT (mult);
336 })
338 (define_split
339 [(set (match_operand:DI 0 "register_operand" "")
340 (sign_extend:DI
341 (plus:SI (match_operator:SI 1 "comparison_operator"
342 [(match_operand 2 "" "")
343 (match_operand 3 "" "")])
344 (match_operand:SI 4 "add_operand" ""))))
345 (clobber (match_operand:DI 5 "register_operand" ""))]
346 ""
347 [(set (match_dup 5) (match_dup 6))
348 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
349 {
350 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
351 operands[2], operands[3]);
352 operands[7] = gen_lowpart (SImode, operands[5]);
353 })
355 (define_insn "addvsi3"
356 [(set (match_operand:SI 0 "register_operand" "=r,r")
357 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
358 (match_operand:SI 2 "sext_add_operand" "rI,O")))
359 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
360 (sign_extend:DI (match_dup 2)))
361 (sign_extend:DI (plus:SI (match_dup 1)
362 (match_dup 2))))
363 (const_int 0))]
364 ""
365 "@
366 addlv %r1,%2,%0
367 sublv %r1,%n2,%0")
369 (define_expand "adddi3"
370 [(set (match_operand:DI 0 "register_operand" "")
371 (plus:DI (match_operand:DI 1 "register_operand" "")
372 (match_operand:DI 2 "add_operand" "")))]
373 ""
374 "")
376 (define_insn "*adddi_er_lo16_dtp"
377 [(set (match_operand:DI 0 "register_operand" "=r")
378 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
379 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
380 "HAVE_AS_TLS"
381 "lda %0,%2(%1)\t\t!dtprel")
383 (define_insn "*adddi_er_hi32_dtp"
384 [(set (match_operand:DI 0 "register_operand" "=r")
385 (plus:DI (match_operand:DI 1 "register_operand" "r")
386 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
387 "HAVE_AS_TLS"
388 "ldah %0,%2(%1)\t\t!dtprelhi")
390 (define_insn "*adddi_er_lo32_dtp"
391 [(set (match_operand:DI 0 "register_operand" "=r")
392 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
393 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
394 "HAVE_AS_TLS"
395 "lda %0,%2(%1)\t\t!dtprello")
397 (define_insn "*adddi_er_lo16_tp"
398 [(set (match_operand:DI 0 "register_operand" "=r")
399 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
400 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
401 "HAVE_AS_TLS"
402 "lda %0,%2(%1)\t\t!tprel")
404 (define_insn "*adddi_er_hi32_tp"
405 [(set (match_operand:DI 0 "register_operand" "=r")
406 (plus:DI (match_operand:DI 1 "register_operand" "r")
407 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
408 "HAVE_AS_TLS"
409 "ldah %0,%2(%1)\t\t!tprelhi")
411 (define_insn "*adddi_er_lo32_tp"
412 [(set (match_operand:DI 0 "register_operand" "=r")
413 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
414 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
415 "HAVE_AS_TLS"
416 "lda %0,%2(%1)\t\t!tprello")
418 (define_insn "*adddi_er_high_l"
419 [(set (match_operand:DI 0 "register_operand" "=r")
420 (plus:DI (match_operand:DI 1 "register_operand" "r")
421 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
422 "TARGET_EXPLICIT_RELOCS && reload_completed"
423 "ldah %0,%2(%1)\t\t!gprelhigh"
424 [(set_attr "usegp" "yes")])
426 (define_split
427 [(set (match_operand:DI 0 "register_operand" "")
428 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
429 "TARGET_EXPLICIT_RELOCS && reload_completed"
430 [(set (match_dup 0)
431 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
432 "operands[2] = pic_offset_table_rtx;")
434 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
435 ;; With complications like
436 ;;
437 ;; The NT stack unwind code can't handle a subq to adjust the stack
438 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
439 ;; the exception handling code will loop if a subq is used and an
440 ;; exception occurs.
441 ;;
442 ;; The 19980616 change to emit prologues as RTL also confused some
443 ;; versions of GDB, which also interprets prologues. This has been
444 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
445 ;; use lda here.
446 ;;
447 ;; and the fact that the three insns schedule exactly the same, it's
448 ;; just not worth the effort.
450 (define_insn "*adddi_internal"
451 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
452 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
453 (match_operand:DI 2 "add_operand" "r,K,L")))]
454 ""
455 "@
456 addq %1,%2,%0
457 lda %0,%2(%1)
458 ldah %0,%h2(%1)")
460 ;; ??? Allow large constants when basing off the frame pointer or some
461 ;; virtual register that may eliminate to the frame pointer. This is
462 ;; done because register elimination offsets will change the hi/lo split,
463 ;; and if we split before reload, we will require additional instructions.
465 (define_insn "*adddi_fp_hack"
466 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
467 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r")
468 (match_operand:DI 2 "const_int_operand" "K,L,n")))]
469 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
470 && INTVAL (operands[2]) >= 0
471 /* This is the largest constant an lda+ldah pair can add, minus
472 an upper bound on the displacement between SP and AP during
473 register elimination. See INITIAL_ELIMINATION_OFFSET. */
474 && INTVAL (operands[2])
475 < (0x7fff8000
476 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
477 - ALPHA_ROUND(crtl->outgoing_args_size)
478 - (ALPHA_ROUND (get_frame_size ()
479 + max_reg_num () * UNITS_PER_WORD
480 + crtl->args.pretend_args_size)
481 - crtl->args.pretend_args_size))"
482 "@
483 lda %0,%2(%1)
484 ldah %0,%h2(%1)
485 #")
487 ;; Don't do this if we are adjusting SP since we don't want to do it
488 ;; in two steps. Don't split FP sources for the reason listed above.
489 (define_split
490 [(set (match_operand:DI 0 "register_operand" "")
491 (plus:DI (match_operand:DI 1 "register_operand" "")
492 (match_operand:DI 2 "const_int_operand" "")))]
493 "! add_operand (operands[2], DImode)
494 && operands[0] != stack_pointer_rtx
495 && operands[1] != frame_pointer_rtx
496 && operands[1] != arg_pointer_rtx"
497 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
498 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
499 {
500 HOST_WIDE_INT val = INTVAL (operands[2]);
501 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
502 HOST_WIDE_INT rest = val - low;
503 rtx rest_rtx = GEN_INT (rest);
505 operands[4] = GEN_INT (low);
506 if (satisfies_constraint_L (rest_rtx))
507 operands[3] = rest_rtx;
508 else if (can_create_pseudo_p ())
509 {
510 operands[3] = gen_reg_rtx (DImode);
511 emit_move_insn (operands[3], operands[2]);
512 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
513 DONE;
514 }
515 else
516 FAIL;
517 })
519 (define_insn "*saddl"
520 [(set (match_operand:SI 0 "register_operand" "=r,r")
521 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
522 (match_operand:SI 2 "const48_operand" "I,I"))
523 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
524 ""
525 "@
526 s%2addl %1,%3,%0
527 s%2subl %1,%n3,%0")
529 (define_insn "*saddl_se"
530 [(set (match_operand:DI 0 "register_operand" "=r,r")
531 (sign_extend:DI
532 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
533 (match_operand:SI 2 "const48_operand" "I,I"))
534 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
535 ""
536 "@
537 s%2addl %1,%3,%0
538 s%2subl %1,%n3,%0")
540 (define_split
541 [(set (match_operand:DI 0 "register_operand" "")
542 (sign_extend:DI
543 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
544 [(match_operand 2 "" "")
545 (match_operand 3 "" "")])
546 (match_operand:SI 4 "const48_operand" ""))
547 (match_operand:SI 5 "sext_add_operand" ""))))
548 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
549 ""
550 [(set (match_dup 6) (match_dup 7))
551 (set (match_dup 0)
552 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
553 (match_dup 5))))]
554 {
555 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
556 operands[2], operands[3]);
557 operands[8] = gen_lowpart (SImode, operands[6]);
558 })
560 (define_insn "*saddq"
561 [(set (match_operand:DI 0 "register_operand" "=r,r")
562 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
563 (match_operand:DI 2 "const48_operand" "I,I"))
564 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
565 ""
566 "@
567 s%2addq %1,%3,%0
568 s%2subq %1,%n3,%0")
570 (define_insn "addvdi3"
571 [(set (match_operand:DI 0 "register_operand" "=r,r")
572 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
573 (match_operand:DI 2 "sext_add_operand" "rI,O")))
574 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
575 (sign_extend:TI (match_dup 2)))
576 (sign_extend:TI (plus:DI (match_dup 1)
577 (match_dup 2))))
578 (const_int 0))]
579 ""
580 "@
581 addqv %r1,%2,%0
582 subqv %r1,%n2,%0")
584 (define_insn "negsi2"
585 [(set (match_operand:SI 0 "register_operand" "=r")
586 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
587 ""
588 "subl $31,%1,%0")
590 (define_insn "*negsi_se"
591 [(set (match_operand:DI 0 "register_operand" "=r")
592 (sign_extend:DI (neg:SI
593 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
594 ""
595 "subl $31,%1,%0")
597 (define_insn "negvsi2"
598 [(set (match_operand:SI 0 "register_operand" "=r")
599 (neg:SI (match_operand:SI 1 "register_operand" "r")))
600 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
601 (sign_extend:DI (neg:SI (match_dup 1))))
602 (const_int 0))]
603 ""
604 "sublv $31,%1,%0")
606 (define_insn "negdi2"
607 [(set (match_operand:DI 0 "register_operand" "=r")
608 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
609 ""
610 "subq $31,%1,%0")
612 (define_insn "negvdi2"
613 [(set (match_operand:DI 0 "register_operand" "=r")
614 (neg:DI (match_operand:DI 1 "register_operand" "r")))
615 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
616 (sign_extend:TI (neg:DI (match_dup 1))))
617 (const_int 0))]
618 ""
619 "subqv $31,%1,%0")
621 (define_expand "subsi3"
622 [(set (match_operand:SI 0 "register_operand" "")
623 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
624 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
625 "! optimize"
626 "")
628 (define_insn "*subsi_internal"
629 [(set (match_operand:SI 0 "register_operand" "=r")
630 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
631 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
632 ""
633 "subl %r1,%2,%0")
635 (define_insn "*subsi_se"
636 [(set (match_operand:DI 0 "register_operand" "=r")
637 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
638 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
639 ""
640 "subl %r1,%2,%0")
642 (define_insn "*subsi_se2"
643 [(set (match_operand:DI 0 "register_operand" "=r")
644 (sign_extend:DI
645 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
646 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
647 0)))]
648 ""
649 "subl %r1,%2,%0")
651 (define_insn "subvsi3"
652 [(set (match_operand:SI 0 "register_operand" "=r")
653 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
654 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
655 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
656 (sign_extend:DI (match_dup 2)))
657 (sign_extend:DI (minus:SI (match_dup 1)
658 (match_dup 2))))
659 (const_int 0))]
660 ""
661 "sublv %r1,%2,%0")
663 (define_insn "subdi3"
664 [(set (match_operand:DI 0 "register_operand" "=r")
665 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
666 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
667 ""
668 "subq %r1,%2,%0")
670 (define_insn "*ssubl"
671 [(set (match_operand:SI 0 "register_operand" "=r")
672 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
673 (match_operand:SI 2 "const48_operand" "I"))
674 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
675 ""
676 "s%2subl %1,%3,%0")
678 (define_insn "*ssubl_se"
679 [(set (match_operand:DI 0 "register_operand" "=r")
680 (sign_extend:DI
681 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
682 (match_operand:SI 2 "const48_operand" "I"))
683 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
684 ""
685 "s%2subl %1,%3,%0")
687 (define_insn "*ssubq"
688 [(set (match_operand:DI 0 "register_operand" "=r")
689 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
690 (match_operand:DI 2 "const48_operand" "I"))
691 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
692 ""
693 "s%2subq %1,%3,%0")
695 (define_insn "subvdi3"
696 [(set (match_operand:DI 0 "register_operand" "=r")
697 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
698 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
699 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
700 (sign_extend:TI (match_dup 2)))
701 (sign_extend:TI (minus:DI (match_dup 1)
702 (match_dup 2))))
703 (const_int 0))]
704 ""
705 "subqv %r1,%2,%0")
707 ;; The Unicos/Mk assembler doesn't support mull.
709 (define_insn "mulsi3"
710 [(set (match_operand:SI 0 "register_operand" "=r")
711 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
712 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
713 "!TARGET_ABI_UNICOSMK"
714 "mull %r1,%2,%0"
715 [(set_attr "type" "imul")
716 (set_attr "opsize" "si")])
718 (define_insn "*mulsi_se"
719 [(set (match_operand:DI 0 "register_operand" "=r")
720 (sign_extend:DI
721 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
722 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
723 "!TARGET_ABI_UNICOSMK"
724 "mull %r1,%2,%0"
725 [(set_attr "type" "imul")
726 (set_attr "opsize" "si")])
728 (define_insn "mulvsi3"
729 [(set (match_operand:SI 0 "register_operand" "=r")
730 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
731 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
732 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
733 (sign_extend:DI (match_dup 2)))
734 (sign_extend:DI (mult:SI (match_dup 1)
735 (match_dup 2))))
736 (const_int 0))]
737 "!TARGET_ABI_UNICOSMK"
738 "mullv %r1,%2,%0"
739 [(set_attr "type" "imul")
740 (set_attr "opsize" "si")])
742 (define_insn "muldi3"
743 [(set (match_operand:DI 0 "register_operand" "=r")
744 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
745 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
746 ""
747 "mulq %r1,%2,%0"
748 [(set_attr "type" "imul")])
750 (define_insn "mulvdi3"
751 [(set (match_operand:DI 0 "register_operand" "=r")
752 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
753 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
754 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
755 (sign_extend:TI (match_dup 2)))
756 (sign_extend:TI (mult:DI (match_dup 1)
757 (match_dup 2))))
758 (const_int 0))]
759 ""
760 "mulqv %r1,%2,%0"
761 [(set_attr "type" "imul")])
763 (define_expand "umuldi3_highpart"
764 [(set (match_operand:DI 0 "register_operand" "")
765 (truncate:DI
766 (lshiftrt:TI
767 (mult:TI (zero_extend:TI
768 (match_operand:DI 1 "register_operand" ""))
769 (match_operand:DI 2 "reg_or_8bit_operand" ""))
770 (const_int 64))))]
771 ""
772 {
773 if (REG_P (operands[2]))
774 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
775 })
777 (define_insn "*umuldi3_highpart_reg"
778 [(set (match_operand:DI 0 "register_operand" "=r")
779 (truncate:DI
780 (lshiftrt:TI
781 (mult:TI (zero_extend:TI
782 (match_operand:DI 1 "register_operand" "r"))
783 (zero_extend:TI
784 (match_operand:DI 2 "register_operand" "r")))
785 (const_int 64))))]
786 ""
787 "umulh %1,%2,%0"
788 [(set_attr "type" "imul")
789 (set_attr "opsize" "udi")])
791 (define_insn "*umuldi3_highpart_const"
792 [(set (match_operand:DI 0 "register_operand" "=r")
793 (truncate:DI
794 (lshiftrt:TI
795 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
796 (match_operand:TI 2 "cint8_operand" "I"))
797 (const_int 64))))]
798 ""
799 "umulh %1,%2,%0"
800 [(set_attr "type" "imul")
801 (set_attr "opsize" "udi")])
802 \f
803 ;; The divide and remainder operations take their inputs from r24 and
804 ;; r25, put their output in r27, and clobber r23 and r28 on all
805 ;; systems except Unicos/Mk. On Unicos, the standard library provides
806 ;; subroutines which use the standard calling convention and work on
807 ;; DImode operands.
809 ;; ??? Force sign-extension here because some versions of OSF/1 and
810 ;; Interix/NT don't do the right thing if the inputs are not properly
811 ;; sign-extended. But Linux, for instance, does not have this
812 ;; problem. Is it worth the complication here to eliminate the sign
813 ;; extension?
815 (define_expand "divsi3"
816 [(set (match_dup 3)
817 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
818 (set (match_dup 4)
819 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
820 (parallel [(set (match_dup 5)
821 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
822 (clobber (reg:DI 23))
823 (clobber (reg:DI 28))])
824 (set (match_operand:SI 0 "nonimmediate_operand" "")
825 (subreg:SI (match_dup 5) 0))]
826 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
827 {
828 operands[3] = gen_reg_rtx (DImode);
829 operands[4] = gen_reg_rtx (DImode);
830 operands[5] = gen_reg_rtx (DImode);
831 })
833 (define_expand "udivsi3"
834 [(set (match_dup 3)
835 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
836 (set (match_dup 4)
837 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
838 (parallel [(set (match_dup 5)
839 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
840 (clobber (reg:DI 23))
841 (clobber (reg:DI 28))])
842 (set (match_operand:SI 0 "nonimmediate_operand" "")
843 (subreg:SI (match_dup 5) 0))]
844 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
845 {
846 operands[3] = gen_reg_rtx (DImode);
847 operands[4] = gen_reg_rtx (DImode);
848 operands[5] = gen_reg_rtx (DImode);
849 })
851 (define_expand "modsi3"
852 [(set (match_dup 3)
853 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
854 (set (match_dup 4)
855 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
856 (parallel [(set (match_dup 5)
857 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
858 (clobber (reg:DI 23))
859 (clobber (reg:DI 28))])
860 (set (match_operand:SI 0 "nonimmediate_operand" "")
861 (subreg:SI (match_dup 5) 0))]
862 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
863 {
864 operands[3] = gen_reg_rtx (DImode);
865 operands[4] = gen_reg_rtx (DImode);
866 operands[5] = gen_reg_rtx (DImode);
867 })
869 (define_expand "umodsi3"
870 [(set (match_dup 3)
871 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
872 (set (match_dup 4)
873 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
874 (parallel [(set (match_dup 5)
875 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
876 (clobber (reg:DI 23))
877 (clobber (reg:DI 28))])
878 (set (match_operand:SI 0 "nonimmediate_operand" "")
879 (subreg:SI (match_dup 5) 0))]
880 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
881 {
882 operands[3] = gen_reg_rtx (DImode);
883 operands[4] = gen_reg_rtx (DImode);
884 operands[5] = gen_reg_rtx (DImode);
885 })
887 (define_expand "divdi3"
888 [(parallel [(set (match_operand:DI 0 "register_operand" "")
889 (div:DI (match_operand:DI 1 "register_operand" "")
890 (match_operand:DI 2 "register_operand" "")))
891 (clobber (reg:DI 23))
892 (clobber (reg:DI 28))])]
893 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
894 "")
896 (define_expand "udivdi3"
897 [(parallel [(set (match_operand:DI 0 "register_operand" "")
898 (udiv:DI (match_operand:DI 1 "register_operand" "")
899 (match_operand:DI 2 "register_operand" "")))
900 (clobber (reg:DI 23))
901 (clobber (reg:DI 28))])]
902 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
903 "")
905 (define_expand "moddi3"
906 [(use (match_operand:DI 0 "register_operand" ""))
907 (use (match_operand:DI 1 "register_operand" ""))
908 (use (match_operand:DI 2 "register_operand" ""))]
909 "!TARGET_ABI_OPEN_VMS"
910 {
911 if (TARGET_ABI_UNICOSMK)
912 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
913 else
914 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
915 DONE;
916 })
918 (define_expand "moddi3_dft"
919 [(parallel [(set (match_operand:DI 0 "register_operand" "")
920 (mod:DI (match_operand:DI 1 "register_operand" "")
921 (match_operand:DI 2 "register_operand" "")))
922 (clobber (reg:DI 23))
923 (clobber (reg:DI 28))])]
924 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
925 "")
927 ;; On Unicos/Mk, we do as the system's C compiler does:
928 ;; compute the quotient, multiply and subtract.
930 (define_expand "moddi3_umk"
931 [(use (match_operand:DI 0 "register_operand" ""))
932 (use (match_operand:DI 1 "register_operand" ""))
933 (use (match_operand:DI 2 "register_operand" ""))]
934 "TARGET_ABI_UNICOSMK"
935 {
936 rtx div, mul = gen_reg_rtx (DImode);
938 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
939 NULL_RTX, 0, OPTAB_LIB);
940 div = force_reg (DImode, div);
941 emit_insn (gen_muldi3 (mul, operands[2], div));
942 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
943 DONE;
944 })
946 (define_expand "umoddi3"
947 [(use (match_operand:DI 0 "register_operand" ""))
948 (use (match_operand:DI 1 "register_operand" ""))
949 (use (match_operand:DI 2 "register_operand" ""))]
950 "! TARGET_ABI_OPEN_VMS"
951 {
952 if (TARGET_ABI_UNICOSMK)
953 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
954 else
955 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
956 DONE;
957 })
959 (define_expand "umoddi3_dft"
960 [(parallel [(set (match_operand:DI 0 "register_operand" "")
961 (umod:DI (match_operand:DI 1 "register_operand" "")
962 (match_operand:DI 2 "register_operand" "")))
963 (clobber (reg:DI 23))
964 (clobber (reg:DI 28))])]
965 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
966 "")
968 (define_expand "umoddi3_umk"
969 [(use (match_operand:DI 0 "register_operand" ""))
970 (use (match_operand:DI 1 "register_operand" ""))
971 (use (match_operand:DI 2 "register_operand" ""))]
972 "TARGET_ABI_UNICOSMK"
973 {
974 rtx div, mul = gen_reg_rtx (DImode);
976 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
977 NULL_RTX, 1, OPTAB_LIB);
978 div = force_reg (DImode, div);
979 emit_insn (gen_muldi3 (mul, operands[2], div));
980 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
981 DONE;
982 })
984 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
985 ;; expanded by the assembler.
987 (define_insn_and_split "*divmodsi_internal_er"
988 [(set (match_operand:DI 0 "register_operand" "=c")
989 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
990 [(match_operand:DI 1 "register_operand" "a")
991 (match_operand:DI 2 "register_operand" "b")])))
992 (clobber (reg:DI 23))
993 (clobber (reg:DI 28))]
994 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
995 "#"
996 "&& reload_completed"
997 [(parallel [(set (match_dup 0)
998 (sign_extend:DI (match_dup 3)))
999 (use (match_dup 0))
1000 (use (match_dup 4))
1001 (clobber (reg:DI 23))
1002 (clobber (reg:DI 28))])]
1003 {
1004 const char *str;
1005 switch (GET_CODE (operands[3]))
1006 {
1007 case DIV:
1008 str = "__divl";
1009 break;
1010 case UDIV:
1011 str = "__divlu";
1012 break;
1013 case MOD:
1014 str = "__reml";
1015 break;
1016 case UMOD:
1017 str = "__remlu";
1018 break;
1019 default:
1020 gcc_unreachable ();
1021 }
1022 operands[4] = GEN_INT (alpha_next_sequence_number++);
1023 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1024 gen_rtx_SYMBOL_REF (DImode, str),
1025 operands[4]));
1026 }
1027 [(set_attr "type" "jsr")
1028 (set_attr "length" "8")])
1030 (define_insn "*divmodsi_internal_er_1"
1031 [(set (match_operand:DI 0 "register_operand" "=c")
1032 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1033 [(match_operand:DI 1 "register_operand" "a")
1034 (match_operand:DI 2 "register_operand" "b")])))
1035 (use (match_operand:DI 4 "register_operand" "c"))
1036 (use (match_operand 5 "const_int_operand" ""))
1037 (clobber (reg:DI 23))
1038 (clobber (reg:DI 28))]
1039 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1040 "jsr $23,($27),__%E3%j5"
1041 [(set_attr "type" "jsr")
1042 (set_attr "length" "4")])
1044 (define_insn "*divmodsi_internal"
1045 [(set (match_operand:DI 0 "register_operand" "=c")
1046 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1047 [(match_operand:DI 1 "register_operand" "a")
1048 (match_operand:DI 2 "register_operand" "b")])))
1049 (clobber (reg:DI 23))
1050 (clobber (reg:DI 28))]
1051 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1052 "%E3 %1,%2,%0"
1053 [(set_attr "type" "jsr")
1054 (set_attr "length" "8")])
1056 (define_insn_and_split "*divmoddi_internal_er"
1057 [(set (match_operand:DI 0 "register_operand" "=c")
1058 (match_operator:DI 3 "divmod_operator"
1059 [(match_operand:DI 1 "register_operand" "a")
1060 (match_operand:DI 2 "register_operand" "b")]))
1061 (clobber (reg:DI 23))
1062 (clobber (reg:DI 28))]
1063 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1064 "#"
1065 "&& reload_completed"
1066 [(parallel [(set (match_dup 0) (match_dup 3))
1067 (use (match_dup 0))
1068 (use (match_dup 4))
1069 (clobber (reg:DI 23))
1070 (clobber (reg:DI 28))])]
1071 {
1072 const char *str;
1073 switch (GET_CODE (operands[3]))
1074 {
1075 case DIV:
1076 str = "__divq";
1077 break;
1078 case UDIV:
1079 str = "__divqu";
1080 break;
1081 case MOD:
1082 str = "__remq";
1083 break;
1084 case UMOD:
1085 str = "__remqu";
1086 break;
1087 default:
1088 gcc_unreachable ();
1089 }
1090 operands[4] = GEN_INT (alpha_next_sequence_number++);
1091 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1092 gen_rtx_SYMBOL_REF (DImode, str),
1093 operands[4]));
1094 }
1095 [(set_attr "type" "jsr")
1096 (set_attr "length" "8")])
1098 (define_insn "*divmoddi_internal_er_1"
1099 [(set (match_operand:DI 0 "register_operand" "=c")
1100 (match_operator:DI 3 "divmod_operator"
1101 [(match_operand:DI 1 "register_operand" "a")
1102 (match_operand:DI 2 "register_operand" "b")]))
1103 (use (match_operand:DI 4 "register_operand" "c"))
1104 (use (match_operand 5 "const_int_operand" ""))
1105 (clobber (reg:DI 23))
1106 (clobber (reg:DI 28))]
1107 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1108 "jsr $23,($27),__%E3%j5"
1109 [(set_attr "type" "jsr")
1110 (set_attr "length" "4")])
1112 (define_insn "*divmoddi_internal"
1113 [(set (match_operand:DI 0 "register_operand" "=c")
1114 (match_operator:DI 3 "divmod_operator"
1115 [(match_operand:DI 1 "register_operand" "a")
1116 (match_operand:DI 2 "register_operand" "b")]))
1117 (clobber (reg:DI 23))
1118 (clobber (reg:DI 28))]
1119 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1120 "%E3 %1,%2,%0"
1121 [(set_attr "type" "jsr")
1122 (set_attr "length" "8")])
1123 \f
1124 ;; Next are the basic logical operations. We only expose the DImode operations
1125 ;; to the rtl expanders, but SImode versions exist for combine as well as for
1126 ;; the atomic operation splitters.
1128 (define_insn "*andsi_internal"
1129 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1130 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1131 (match_operand:SI 2 "and_operand" "rI,N,MH")))]
1132 ""
1133 "@
1134 and %r1,%2,%0
1135 bic %r1,%N2,%0
1136 zapnot %r1,%m2,%0"
1137 [(set_attr "type" "ilog,ilog,shift")])
1139 (define_insn "anddi3"
1140 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1141 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1142 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1143 ""
1144 "@
1145 and %r1,%2,%0
1146 bic %r1,%N2,%0
1147 zapnot %r1,%m2,%0"
1148 [(set_attr "type" "ilog,ilog,shift")])
1150 ;; There are times when we can split an AND into two AND insns. This occurs
1151 ;; when we can first clear any bytes and then clear anything else. For
1152 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1153 ;; Only do this when running on 64-bit host since the computations are
1154 ;; too messy otherwise.
1156 (define_split
1157 [(set (match_operand:DI 0 "register_operand" "")
1158 (and:DI (match_operand:DI 1 "register_operand" "")
1159 (match_operand:DI 2 "const_int_operand" "")))]
1160 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1161 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1162 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1163 {
1164 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1165 unsigned HOST_WIDE_INT mask2 = mask1;
1166 int i;
1168 /* For each byte that isn't all zeros, make it all ones. */
1169 for (i = 0; i < 64; i += 8)
1170 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1171 mask1 |= (HOST_WIDE_INT) 0xff << i;
1173 /* Now turn on any bits we've just turned off. */
1174 mask2 |= ~ mask1;
1176 operands[3] = GEN_INT (mask1);
1177 operands[4] = GEN_INT (mask2);
1178 })
1180 (define_expand "zero_extendqihi2"
1181 [(set (match_operand:HI 0 "register_operand" "")
1182 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1183 ""
1184 {
1185 if (! TARGET_BWX)
1186 operands[1] = force_reg (QImode, operands[1]);
1187 })
1189 (define_insn "*zero_extendqihi2_bwx"
1190 [(set (match_operand:HI 0 "register_operand" "=r,r")
1191 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1192 "TARGET_BWX"
1193 "@
1194 and %1,0xff,%0
1195 ldbu %0,%1"
1196 [(set_attr "type" "ilog,ild")])
1198 (define_insn "*zero_extendqihi2_nobwx"
1199 [(set (match_operand:HI 0 "register_operand" "=r")
1200 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1201 "! TARGET_BWX"
1202 "and %1,0xff,%0"
1203 [(set_attr "type" "ilog")])
1205 (define_expand "zero_extendqisi2"
1206 [(set (match_operand:SI 0 "register_operand" "")
1207 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1208 ""
1209 {
1210 if (! TARGET_BWX)
1211 operands[1] = force_reg (QImode, operands[1]);
1212 })
1214 (define_insn "*zero_extendqisi2_bwx"
1215 [(set (match_operand:SI 0 "register_operand" "=r,r")
1216 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1217 "TARGET_BWX"
1218 "@
1219 and %1,0xff,%0
1220 ldbu %0,%1"
1221 [(set_attr "type" "ilog,ild")])
1223 (define_insn "*zero_extendqisi2_nobwx"
1224 [(set (match_operand:SI 0 "register_operand" "=r")
1225 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1226 "! TARGET_BWX"
1227 "and %1,0xff,%0"
1228 [(set_attr "type" "ilog")])
1230 (define_expand "zero_extendqidi2"
1231 [(set (match_operand:DI 0 "register_operand" "")
1232 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1233 ""
1234 {
1235 if (! TARGET_BWX)
1236 operands[1] = force_reg (QImode, operands[1]);
1237 })
1239 (define_insn "*zero_extendqidi2_bwx"
1240 [(set (match_operand:DI 0 "register_operand" "=r,r")
1241 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1242 "TARGET_BWX"
1243 "@
1244 and %1,0xff,%0
1245 ldbu %0,%1"
1246 [(set_attr "type" "ilog,ild")])
1248 (define_insn "*zero_extendqidi2_nobwx"
1249 [(set (match_operand:DI 0 "register_operand" "=r")
1250 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1251 "! TARGET_BWX"
1252 "and %1,0xff,%0"
1253 [(set_attr "type" "ilog")])
1255 (define_expand "zero_extendhisi2"
1256 [(set (match_operand:SI 0 "register_operand" "")
1257 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1258 ""
1259 {
1260 if (! TARGET_BWX)
1261 operands[1] = force_reg (HImode, operands[1]);
1262 })
1264 (define_insn "*zero_extendhisi2_bwx"
1265 [(set (match_operand:SI 0 "register_operand" "=r,r")
1266 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1267 "TARGET_BWX"
1268 "@
1269 zapnot %1,3,%0
1270 ldwu %0,%1"
1271 [(set_attr "type" "shift,ild")])
1273 (define_insn "*zero_extendhisi2_nobwx"
1274 [(set (match_operand:SI 0 "register_operand" "=r")
1275 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1276 "! TARGET_BWX"
1277 "zapnot %1,3,%0"
1278 [(set_attr "type" "shift")])
1280 (define_expand "zero_extendhidi2"
1281 [(set (match_operand:DI 0 "register_operand" "")
1282 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1283 ""
1284 {
1285 if (! TARGET_BWX)
1286 operands[1] = force_reg (HImode, operands[1]);
1287 })
1289 (define_insn "*zero_extendhidi2_bwx"
1290 [(set (match_operand:DI 0 "register_operand" "=r,r")
1291 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1292 "TARGET_BWX"
1293 "@
1294 zapnot %1,3,%0
1295 ldwu %0,%1"
1296 [(set_attr "type" "shift,ild")])
1298 (define_insn "*zero_extendhidi2_nobwx"
1299 [(set (match_operand:DI 0 "register_operand" "=r")
1300 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1301 ""
1302 "zapnot %1,3,%0"
1303 [(set_attr "type" "shift")])
1305 (define_insn "zero_extendsidi2"
1306 [(set (match_operand:DI 0 "register_operand" "=r")
1307 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1308 ""
1309 "zapnot %1,15,%0"
1310 [(set_attr "type" "shift")])
1312 (define_insn "*andnotsi3"
1313 [(set (match_operand:SI 0 "register_operand" "=r")
1314 (and:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1315 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1316 ""
1317 "bic %r2,%1,%0"
1318 [(set_attr "type" "ilog")])
1320 (define_insn "andnotdi3"
1321 [(set (match_operand:DI 0 "register_operand" "=r")
1322 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1323 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1324 ""
1325 "bic %r2,%1,%0"
1326 [(set_attr "type" "ilog")])
1328 (define_insn "*iorsi_internal"
1329 [(set (match_operand:SI 0 "register_operand" "=r,r")
1330 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1331 (match_operand:SI 2 "or_operand" "rI,N")))]
1332 ""
1333 "@
1334 bis %r1,%2,%0
1335 ornot %r1,%N2,%0"
1336 [(set_attr "type" "ilog")])
1338 (define_insn "iordi3"
1339 [(set (match_operand:DI 0 "register_operand" "=r,r")
1340 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1341 (match_operand:DI 2 "or_operand" "rI,N")))]
1342 ""
1343 "@
1344 bis %r1,%2,%0
1345 ornot %r1,%N2,%0"
1346 [(set_attr "type" "ilog")])
1348 (define_insn "*one_cmplsi_internal"
1349 [(set (match_operand:SI 0 "register_operand" "=r")
1350 (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
1351 ""
1352 "ornot $31,%1,%0"
1353 [(set_attr "type" "ilog")])
1355 (define_insn "one_cmpldi2"
1356 [(set (match_operand:DI 0 "register_operand" "=r")
1357 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1358 ""
1359 "ornot $31,%1,%0"
1360 [(set_attr "type" "ilog")])
1362 (define_insn "*iornotsi3"
1363 [(set (match_operand:SI 0 "register_operand" "=r")
1364 (ior:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1365 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1366 ""
1367 "ornot %r2,%1,%0"
1368 [(set_attr "type" "ilog")])
1370 (define_insn "*iornotdi3"
1371 [(set (match_operand:DI 0 "register_operand" "=r")
1372 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1373 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1374 ""
1375 "ornot %r2,%1,%0"
1376 [(set_attr "type" "ilog")])
1378 (define_insn "*xorsi_internal"
1379 [(set (match_operand:SI 0 "register_operand" "=r,r")
1380 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1381 (match_operand:SI 2 "or_operand" "rI,N")))]
1382 ""
1383 "@
1384 xor %r1,%2,%0
1385 eqv %r1,%N2,%0"
1386 [(set_attr "type" "ilog")])
1388 (define_insn "xordi3"
1389 [(set (match_operand:DI 0 "register_operand" "=r,r")
1390 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1391 (match_operand:DI 2 "or_operand" "rI,N")))]
1392 ""
1393 "@
1394 xor %r1,%2,%0
1395 eqv %r1,%N2,%0"
1396 [(set_attr "type" "ilog")])
1398 (define_insn "*xornotsi3"
1399 [(set (match_operand:SI 0 "register_operand" "=r")
1400 (not:SI (xor:SI (match_operand:SI 1 "register_operand" "%rJ")
1401 (match_operand:SI 2 "register_operand" "rI"))))]
1402 ""
1403 "eqv %r1,%2,%0"
1404 [(set_attr "type" "ilog")])
1406 (define_insn "*xornotdi3"
1407 [(set (match_operand:DI 0 "register_operand" "=r")
1408 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1409 (match_operand:DI 2 "register_operand" "rI"))))]
1410 ""
1411 "eqv %r1,%2,%0"
1412 [(set_attr "type" "ilog")])
1413 \f
1414 ;; Handle FFS and related insns iff we support CIX.
1416 (define_expand "ffsdi2"
1417 [(set (match_dup 2)
1418 (ctz:DI (match_operand:DI 1 "register_operand" "")))
1419 (set (match_dup 3)
1420 (plus:DI (match_dup 2) (const_int 1)))
1421 (set (match_operand:DI 0 "register_operand" "")
1422 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1423 (const_int 0) (match_dup 3)))]
1424 "TARGET_CIX"
1425 {
1426 operands[2] = gen_reg_rtx (DImode);
1427 operands[3] = gen_reg_rtx (DImode);
1428 })
1430 (define_insn "clzdi2"
1431 [(set (match_operand:DI 0 "register_operand" "=r")
1432 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1433 "TARGET_CIX"
1434 "ctlz %1,%0"
1435 [(set_attr "type" "mvi")])
1437 (define_insn "ctzdi2"
1438 [(set (match_operand:DI 0 "register_operand" "=r")
1439 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1440 "TARGET_CIX"
1441 "cttz %1,%0"
1442 [(set_attr "type" "mvi")])
1444 (define_insn "popcountdi2"
1445 [(set (match_operand:DI 0 "register_operand" "=r")
1446 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1447 "TARGET_CIX"
1448 "ctpop %1,%0"
1449 [(set_attr "type" "mvi")])
1451 (define_expand "bswapsi2"
1452 [(set (match_operand:SI 0 "register_operand" "")
1453 (bswap:SI (match_operand:SI 1 "register_operand" "")))]
1454 "!optimize_size"
1455 {
1456 rtx t0, t1;
1458 t0 = gen_reg_rtx (DImode);
1459 t1 = gen_reg_rtx (DImode);
1461 emit_insn (gen_insxh (t0, gen_lowpart (DImode, operands[1]),
1462 GEN_INT (32), GEN_INT (WORDS_BIG_ENDIAN ? 0 : 7)));
1463 emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]),
1464 GEN_INT (24)));
1465 emit_insn (gen_iordi3 (t1, t0, t1));
1466 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16)));
1467 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x5)));
1468 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xa)));
1469 emit_insn (gen_addsi3 (operands[0], gen_lowpart (SImode, t0),
1470 gen_lowpart (SImode, t1)));
1471 DONE;
1472 })
1474 (define_expand "bswapdi2"
1475 [(set (match_operand:DI 0 "register_operand" "")
1476 (bswap:DI (match_operand:DI 1 "register_operand" "")))]
1477 "!optimize_size"
1478 {
1479 rtx t0, t1;
1481 t0 = gen_reg_rtx (DImode);
1482 t1 = gen_reg_rtx (DImode);
1484 /* This method of shifting and masking is not specific to Alpha, but
1485 is only profitable on Alpha because of our handy byte zap insn. */
1487 emit_insn (gen_lshrdi3 (t0, operands[1], GEN_INT (32)));
1488 emit_insn (gen_ashldi3 (t1, operands[1], GEN_INT (32)));
1489 emit_insn (gen_iordi3 (t1, t0, t1));
1491 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16)));
1492 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (16)));
1493 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xcc)));
1494 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x33)));
1495 emit_insn (gen_iordi3 (t1, t0, t1));
1497 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (8)));
1498 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (8)));
1499 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xaa)));
1500 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x55)));
1501 emit_insn (gen_iordi3 (operands[0], t0, t1));
1502 DONE;
1503 })
1504 \f
1505 ;; Next come the shifts and the various extract and insert operations.
1507 (define_insn "ashldi3"
1508 [(set (match_operand:DI 0 "register_operand" "=r,r")
1509 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1510 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1511 ""
1512 {
1513 switch (which_alternative)
1514 {
1515 case 0:
1516 if (operands[2] == const1_rtx)
1517 return "addq %r1,%r1,%0";
1518 else
1519 return "s%P2addq %r1,0,%0";
1520 case 1:
1521 return "sll %r1,%2,%0";
1522 default:
1523 gcc_unreachable ();
1524 }
1525 }
1526 [(set_attr "type" "iadd,shift")])
1528 (define_insn "*ashldi_se"
1529 [(set (match_operand:DI 0 "register_operand" "=r")
1530 (sign_extend:DI
1531 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1532 (match_operand:DI 2 "const_int_operand" "P"))
1533 0)))]
1534 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1535 {
1536 if (operands[2] == const1_rtx)
1537 return "addl %r1,%r1,%0";
1538 else
1539 return "s%P2addl %r1,0,%0";
1540 }
1541 [(set_attr "type" "iadd")])
1543 (define_insn "lshrdi3"
1544 [(set (match_operand:DI 0 "register_operand" "=r")
1545 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1546 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1547 ""
1548 "srl %r1,%2,%0"
1549 [(set_attr "type" "shift")])
1551 (define_insn "ashrdi3"
1552 [(set (match_operand:DI 0 "register_operand" "=r")
1553 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1554 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1555 ""
1556 "sra %r1,%2,%0"
1557 [(set_attr "type" "shift")])
1559 (define_expand "extendqihi2"
1560 [(set (match_dup 2)
1561 (ashift:DI (match_operand:QI 1 "some_operand" "")
1562 (const_int 56)))
1563 (set (match_operand:HI 0 "register_operand" "")
1564 (ashiftrt:DI (match_dup 2)
1565 (const_int 56)))]
1566 ""
1567 {
1568 if (TARGET_BWX)
1569 {
1570 emit_insn (gen_extendqihi2x (operands[0],
1571 force_reg (QImode, operands[1])));
1572 DONE;
1573 }
1575 /* If we have an unaligned MEM, extend to DImode (which we do
1576 specially) and then copy to the result. */
1577 if (unaligned_memory_operand (operands[1], HImode))
1578 {
1579 rtx temp = gen_reg_rtx (DImode);
1581 emit_insn (gen_extendqidi2 (temp, operands[1]));
1582 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1583 DONE;
1584 }
1586 operands[0] = gen_lowpart (DImode, operands[0]);
1587 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1588 operands[2] = gen_reg_rtx (DImode);
1589 })
1591 (define_insn "extendqidi2x"
1592 [(set (match_operand:DI 0 "register_operand" "=r")
1593 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1594 "TARGET_BWX"
1595 "sextb %1,%0"
1596 [(set_attr "type" "shift")])
1598 (define_insn "extendhidi2x"
1599 [(set (match_operand:DI 0 "register_operand" "=r")
1600 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1601 "TARGET_BWX"
1602 "sextw %1,%0"
1603 [(set_attr "type" "shift")])
1605 (define_insn "extendqisi2x"
1606 [(set (match_operand:SI 0 "register_operand" "=r")
1607 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1608 "TARGET_BWX"
1609 "sextb %1,%0"
1610 [(set_attr "type" "shift")])
1612 (define_insn "extendhisi2x"
1613 [(set (match_operand:SI 0 "register_operand" "=r")
1614 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1615 "TARGET_BWX"
1616 "sextw %1,%0"
1617 [(set_attr "type" "shift")])
1619 (define_insn "extendqihi2x"
1620 [(set (match_operand:HI 0 "register_operand" "=r")
1621 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1622 "TARGET_BWX"
1623 "sextb %1,%0"
1624 [(set_attr "type" "shift")])
1626 (define_expand "extendqisi2"
1627 [(set (match_dup 2)
1628 (ashift:DI (match_operand:QI 1 "some_operand" "")
1629 (const_int 56)))
1630 (set (match_operand:SI 0 "register_operand" "")
1631 (ashiftrt:DI (match_dup 2)
1632 (const_int 56)))]
1633 ""
1634 {
1635 if (TARGET_BWX)
1636 {
1637 emit_insn (gen_extendqisi2x (operands[0],
1638 force_reg (QImode, operands[1])));
1639 DONE;
1640 }
1642 /* If we have an unaligned MEM, extend to a DImode form of
1643 the result (which we do specially). */
1644 if (unaligned_memory_operand (operands[1], QImode))
1645 {
1646 rtx temp = gen_reg_rtx (DImode);
1648 emit_insn (gen_extendqidi2 (temp, operands[1]));
1649 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1650 DONE;
1651 }
1653 operands[0] = gen_lowpart (DImode, operands[0]);
1654 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1655 operands[2] = gen_reg_rtx (DImode);
1656 })
1658 (define_expand "extendqidi2"
1659 [(set (match_dup 2)
1660 (ashift:DI (match_operand:QI 1 "some_operand" "")
1661 (const_int 56)))
1662 (set (match_operand:DI 0 "register_operand" "")
1663 (ashiftrt:DI (match_dup 2)
1664 (const_int 56)))]
1665 ""
1666 {
1667 if (TARGET_BWX)
1668 {
1669 emit_insn (gen_extendqidi2x (operands[0],
1670 force_reg (QImode, operands[1])));
1671 DONE;
1672 }
1674 if (unaligned_memory_operand (operands[1], QImode))
1675 {
1676 rtx seq = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0));
1677 alpha_set_memflags (seq, operands[1]);
1678 emit_insn (seq);
1679 DONE;
1680 }
1682 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1683 operands[2] = gen_reg_rtx (DImode);
1684 })
1686 (define_expand "extendhisi2"
1687 [(set (match_dup 2)
1688 (ashift:DI (match_operand:HI 1 "some_operand" "")
1689 (const_int 48)))
1690 (set (match_operand:SI 0 "register_operand" "")
1691 (ashiftrt:DI (match_dup 2)
1692 (const_int 48)))]
1693 ""
1694 {
1695 if (TARGET_BWX)
1696 {
1697 emit_insn (gen_extendhisi2x (operands[0],
1698 force_reg (HImode, operands[1])));
1699 DONE;
1700 }
1702 /* If we have an unaligned MEM, extend to a DImode form of
1703 the result (which we do specially). */
1704 if (unaligned_memory_operand (operands[1], HImode))
1705 {
1706 rtx temp = gen_reg_rtx (DImode);
1708 emit_insn (gen_extendhidi2 (temp, operands[1]));
1709 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1710 DONE;
1711 }
1713 operands[0] = gen_lowpart (DImode, operands[0]);
1714 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1715 operands[2] = gen_reg_rtx (DImode);
1716 })
1718 (define_expand "extendhidi2"
1719 [(set (match_dup 2)
1720 (ashift:DI (match_operand:HI 1 "some_operand" "")
1721 (const_int 48)))
1722 (set (match_operand:DI 0 "register_operand" "")
1723 (ashiftrt:DI (match_dup 2)
1724 (const_int 48)))]
1725 ""
1726 {
1727 if (TARGET_BWX)
1728 {
1729 emit_insn (gen_extendhidi2x (operands[0],
1730 force_reg (HImode, operands[1])));
1731 DONE;
1732 }
1734 if (unaligned_memory_operand (operands[1], HImode))
1735 {
1736 rtx seq = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0));
1738 alpha_set_memflags (seq, operands[1]);
1739 emit_insn (seq);
1740 DONE;
1741 }
1743 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1744 operands[2] = gen_reg_rtx (DImode);
1745 })
1747 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1748 ;; as a pattern saves one instruction. The code is similar to that for
1749 ;; the unaligned loads (see below).
1750 ;;
1751 ;; Operand 1 is the address, operand 0 is the result.
1752 (define_expand "unaligned_extendqidi"
1753 [(use (match_operand:QI 0 "register_operand" ""))
1754 (use (match_operand:DI 1 "address_operand" ""))]
1755 ""
1756 {
1757 operands[0] = gen_lowpart (DImode, operands[0]);
1758 if (WORDS_BIG_ENDIAN)
1759 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1760 else
1761 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1762 DONE;
1763 })
1765 (define_expand "unaligned_extendqidi_le"
1766 [(set (match_dup 3)
1767 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1768 (set (match_dup 4)
1769 (ashift:DI (match_dup 3)
1770 (minus:DI (const_int 64)
1771 (ashift:DI
1772 (and:DI (match_dup 2) (const_int 7))
1773 (const_int 3)))))
1774 (set (match_operand:DI 0 "register_operand" "")
1775 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1776 "! WORDS_BIG_ENDIAN"
1777 {
1778 operands[2] = get_unaligned_offset (operands[1], 1);
1779 operands[3] = gen_reg_rtx (DImode);
1780 operands[4] = gen_reg_rtx (DImode);
1781 })
1783 (define_expand "unaligned_extendqidi_be"
1784 [(set (match_dup 3)
1785 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1786 (set (match_dup 4)
1787 (ashift:DI (match_dup 3)
1788 (ashift:DI
1789 (and:DI
1790 (plus:DI (match_dup 2) (const_int 1))
1791 (const_int 7))
1792 (const_int 3))))
1793 (set (match_operand:DI 0 "register_operand" "")
1794 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1795 "WORDS_BIG_ENDIAN"
1796 {
1797 operands[2] = get_unaligned_offset (operands[1], -1);
1798 operands[3] = gen_reg_rtx (DImode);
1799 operands[4] = gen_reg_rtx (DImode);
1800 })
1802 (define_expand "unaligned_extendhidi"
1803 [(use (match_operand:QI 0 "register_operand" ""))
1804 (use (match_operand:DI 1 "address_operand" ""))]
1805 ""
1806 {
1807 operands[0] = gen_lowpart (DImode, operands[0]);
1808 if (WORDS_BIG_ENDIAN)
1809 emit_insn (gen_unaligned_extendhidi_be (operands[0], operands[1]));
1810 else
1811 emit_insn (gen_unaligned_extendhidi_le (operands[0], operands[1]));
1812 DONE;
1813 })
1815 (define_expand "unaligned_extendhidi_le"
1816 [(set (match_dup 3)
1817 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1818 (set (match_dup 4)
1819 (ashift:DI (match_dup 3)
1820 (minus:DI (const_int 64)
1821 (ashift:DI
1822 (and:DI (match_dup 2) (const_int 7))
1823 (const_int 3)))))
1824 (set (match_operand:DI 0 "register_operand" "")
1825 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1826 "! WORDS_BIG_ENDIAN"
1827 {
1828 operands[2] = get_unaligned_offset (operands[1], 2);
1829 operands[3] = gen_reg_rtx (DImode);
1830 operands[4] = gen_reg_rtx (DImode);
1831 })
1833 (define_expand "unaligned_extendhidi_be"
1834 [(set (match_dup 3)
1835 (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
1836 (set (match_dup 4)
1837 (ashift:DI (match_dup 3)
1838 (ashift:DI
1839 (and:DI
1840 (plus:DI (match_dup 2) (const_int 1))
1841 (const_int 7))
1842 (const_int 3))))
1843 (set (match_operand:DI 0 "register_operand" "")
1844 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1845 "WORDS_BIG_ENDIAN"
1846 {
1847 operands[2] = get_unaligned_offset (operands[1], -1);
1848 operands[3] = gen_reg_rtx (DImode);
1849 operands[4] = gen_reg_rtx (DImode);
1850 })
1852 (define_insn "*extxl_const"
1853 [(set (match_operand:DI 0 "register_operand" "=r")
1854 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1855 (match_operand:DI 2 "mode_width_operand" "n")
1856 (match_operand:DI 3 "mul8_operand" "I")))]
1857 ""
1858 "ext%M2l %r1,%s3,%0"
1859 [(set_attr "type" "shift")])
1861 (define_insn "extxl_le"
1862 [(set (match_operand:DI 0 "register_operand" "=r")
1863 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1864 (match_operand:DI 2 "mode_width_operand" "n")
1865 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1866 (const_int 3))))]
1867 "! WORDS_BIG_ENDIAN"
1868 "ext%M2l %r1,%3,%0"
1869 [(set_attr "type" "shift")])
1871 (define_insn "extxl_be"
1872 [(set (match_operand:DI 0 "register_operand" "=r")
1873 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1874 (match_operand:DI 2 "mode_width_operand" "n")
1875 (minus:DI
1876 (const_int 56)
1877 (ashift:DI
1878 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1879 (const_int 3)))))]
1880 "WORDS_BIG_ENDIAN"
1881 "ext%M2l %r1,%3,%0"
1882 [(set_attr "type" "shift")])
1884 ;; Combine has some strange notion of preserving existing undefined behavior
1885 ;; in shifts larger than a word size. So capture these patterns that it
1886 ;; should have turned into zero_extracts.
1888 (define_insn "*extxl_1_le"
1889 [(set (match_operand:DI 0 "register_operand" "=r")
1890 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1891 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1892 (const_int 3)))
1893 (match_operand:DI 3 "mode_mask_operand" "n")))]
1894 "! WORDS_BIG_ENDIAN"
1895 "ext%U3l %1,%2,%0"
1896 [(set_attr "type" "shift")])
1898 (define_insn "*extxl_1_be"
1899 [(set (match_operand:DI 0 "register_operand" "=r")
1900 (and:DI (lshiftrt:DI
1901 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1902 (minus:DI (const_int 56)
1903 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1904 (const_int 3))))
1905 (match_operand:DI 3 "mode_mask_operand" "n")))]
1906 "WORDS_BIG_ENDIAN"
1907 "ext%U3l %1,%2,%0"
1908 [(set_attr "type" "shift")])
1910 (define_insn "*extql_2_le"
1911 [(set (match_operand:DI 0 "register_operand" "=r")
1912 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1913 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1914 (const_int 3))))]
1915 "! WORDS_BIG_ENDIAN"
1916 "extql %1,%2,%0"
1917 [(set_attr "type" "shift")])
1919 (define_insn "*extql_2_be"
1920 [(set (match_operand:DI 0 "register_operand" "=r")
1921 (lshiftrt:DI
1922 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1923 (minus:DI (const_int 56)
1924 (ashift:DI
1925 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1926 (const_int 3)))))]
1927 "WORDS_BIG_ENDIAN"
1928 "extql %1,%2,%0"
1929 [(set_attr "type" "shift")])
1931 (define_insn "extqh_le"
1932 [(set (match_operand:DI 0 "register_operand" "=r")
1933 (ashift:DI
1934 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1935 (minus:DI (const_int 64)
1936 (ashift:DI
1937 (and:DI
1938 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1939 (const_int 7))
1940 (const_int 3)))))]
1941 "! WORDS_BIG_ENDIAN"
1942 "extqh %r1,%2,%0"
1943 [(set_attr "type" "shift")])
1945 (define_insn "extqh_be"
1946 [(set (match_operand:DI 0 "register_operand" "=r")
1947 (ashift:DI
1948 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1949 (ashift:DI
1950 (and:DI
1951 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1952 (const_int 1))
1953 (const_int 7))
1954 (const_int 3))))]
1955 "WORDS_BIG_ENDIAN"
1956 "extqh %r1,%2,%0"
1957 [(set_attr "type" "shift")])
1959 (define_insn "extlh_le"
1960 [(set (match_operand:DI 0 "register_operand" "=r")
1961 (ashift:DI
1962 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1963 (const_int 2147483647))
1964 (minus:DI (const_int 64)
1965 (ashift:DI
1966 (and:DI
1967 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1968 (const_int 7))
1969 (const_int 3)))))]
1970 "! WORDS_BIG_ENDIAN"
1971 "extlh %r1,%2,%0"
1972 [(set_attr "type" "shift")])
1974 (define_insn "extlh_be"
1975 [(set (match_operand:DI 0 "register_operand" "=r")
1976 (and:DI
1977 (ashift:DI
1978 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1979 (ashift:DI
1980 (and:DI
1981 (plus:DI
1982 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1983 (const_int 1))
1984 (const_int 7))
1985 (const_int 3)))
1986 (const_int 2147483647)))]
1987 "WORDS_BIG_ENDIAN"
1988 "extlh %r1,%2,%0"
1989 [(set_attr "type" "shift")])
1991 (define_insn "extwh_le"
1992 [(set (match_operand:DI 0 "register_operand" "=r")
1993 (ashift:DI
1994 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1995 (const_int 65535))
1996 (minus:DI (const_int 64)
1997 (ashift:DI
1998 (and:DI
1999 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2000 (const_int 7))
2001 (const_int 3)))))]
2002 "! WORDS_BIG_ENDIAN"
2003 "extwh %r1,%2,%0"
2004 [(set_attr "type" "shift")])
2006 (define_insn "extwh_be"
2007 [(set (match_operand:DI 0 "register_operand" "=r")
2008 (and:DI
2009 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2010 (ashift:DI
2011 (and:DI
2012 (plus:DI
2013 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2014 (const_int 1))
2015 (const_int 7))
2016 (const_int 3)))
2017 (const_int 65535)))]
2018 "WORDS_BIG_ENDIAN"
2019 "extwh %r1,%2,%0"
2020 [(set_attr "type" "shift")])
2022 ;; This converts an extXl into an extXh with an appropriate adjustment
2023 ;; to the address calculation.
2025 ;;(define_split
2026 ;; [(set (match_operand:DI 0 "register_operand" "")
2027 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
2028 ;; (match_operand:DI 2 "mode_width_operand" "")
2029 ;; (ashift:DI (match_operand:DI 3 "" "")
2030 ;; (const_int 3)))
2031 ;; (match_operand:DI 4 "const_int_operand" "")))
2032 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
2033 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
2034 ;; [(set (match_dup 5) (match_dup 6))
2035 ;; (set (match_dup 0)
2036 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
2037 ;; (ashift:DI (plus:DI (match_dup 5)
2038 ;; (match_dup 7))
2039 ;; (const_int 3)))
2040 ;; (match_dup 4)))]
2041 ;; "
2042 ;;{
2043 ;; operands[6] = plus_constant (operands[3],
2044 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
2045 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
2046 ;;}")
2048 (define_insn "*insbl_const"
2049 [(set (match_operand:DI 0 "register_operand" "=r")
2050 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2051 (match_operand:DI 2 "mul8_operand" "I")))]
2052 ""
2053 "insbl %1,%s2,%0"
2054 [(set_attr "type" "shift")])
2056 (define_insn "inswl_const"
2057 [(set (match_operand:DI 0 "register_operand" "=r")
2058 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2059 (match_operand:DI 2 "mul8_operand" "I")))]
2060 ""
2061 "inswl %1,%s2,%0"
2062 [(set_attr "type" "shift")])
2064 (define_insn "*insll_const"
2065 [(set (match_operand:DI 0 "register_operand" "=r")
2066 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2067 (match_operand:DI 2 "mul8_operand" "I")))]
2068 ""
2069 "insll %1,%s2,%0"
2070 [(set_attr "type" "shift")])
2072 (define_insn "insbl_le"
2073 [(set (match_operand:DI 0 "register_operand" "=r")
2074 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2075 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2076 (const_int 3))))]
2077 "! WORDS_BIG_ENDIAN"
2078 "insbl %1,%2,%0"
2079 [(set_attr "type" "shift")])
2081 (define_insn "insbl_be"
2082 [(set (match_operand:DI 0 "register_operand" "=r")
2083 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2084 (minus:DI (const_int 56)
2085 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2086 (const_int 3)))))]
2087 "WORDS_BIG_ENDIAN"
2088 "insbl %1,%2,%0"
2089 [(set_attr "type" "shift")])
2091 (define_insn "inswl_le"
2092 [(set (match_operand:DI 0 "register_operand" "=r")
2093 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2094 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2095 (const_int 3))))]
2096 "! WORDS_BIG_ENDIAN"
2097 "inswl %1,%2,%0"
2098 [(set_attr "type" "shift")])
2100 (define_insn "inswl_be"
2101 [(set (match_operand:DI 0 "register_operand" "=r")
2102 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2103 (minus:DI (const_int 56)
2104 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2105 (const_int 3)))))]
2106 "WORDS_BIG_ENDIAN"
2107 "inswl %1,%2,%0"
2108 [(set_attr "type" "shift")])
2110 (define_insn "insll_le"
2111 [(set (match_operand:DI 0 "register_operand" "=r")
2112 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2113 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2114 (const_int 3))))]
2115 "! WORDS_BIG_ENDIAN"
2116 "insll %1,%2,%0"
2117 [(set_attr "type" "shift")])
2119 (define_insn "insll_be"
2120 [(set (match_operand:DI 0 "register_operand" "=r")
2121 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2122 (minus:DI (const_int 56)
2123 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2124 (const_int 3)))))]
2125 "WORDS_BIG_ENDIAN"
2126 "insll %1,%2,%0"
2127 [(set_attr "type" "shift")])
2129 (define_insn "insql_le"
2130 [(set (match_operand:DI 0 "register_operand" "=r")
2131 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2132 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2133 (const_int 3))))]
2134 "! WORDS_BIG_ENDIAN"
2135 "insql %1,%2,%0"
2136 [(set_attr "type" "shift")])
2138 (define_insn "insql_be"
2139 [(set (match_operand:DI 0 "register_operand" "=r")
2140 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2141 (minus:DI (const_int 56)
2142 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2143 (const_int 3)))))]
2144 "WORDS_BIG_ENDIAN"
2145 "insql %1,%2,%0"
2146 [(set_attr "type" "shift")])
2148 ;; Combine has this sometimes habit of moving the and outside of the
2149 ;; shift, making life more interesting.
2151 (define_insn "*insxl"
2152 [(set (match_operand:DI 0 "register_operand" "=r")
2153 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2154 (match_operand:DI 2 "mul8_operand" "I"))
2155 (match_operand:DI 3 "immediate_operand" "i")))]
2156 "HOST_BITS_PER_WIDE_INT == 64
2157 && GET_CODE (operands[3]) == CONST_INT
2158 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2159 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2160 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2161 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2162 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2163 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2164 {
2165 #if HOST_BITS_PER_WIDE_INT == 64
2166 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2167 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2168 return "insbl %1,%s2,%0";
2169 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2170 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2171 return "inswl %1,%s2,%0";
2172 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2173 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2174 return "insll %1,%s2,%0";
2175 #endif
2176 gcc_unreachable ();
2177 }
2178 [(set_attr "type" "shift")])
2180 ;; We do not include the insXh insns because they are complex to express
2181 ;; and it does not appear that we would ever want to generate them.
2182 ;;
2183 ;; Since we need them for block moves, though, cop out and use unspec.
2185 (define_insn "insxh"
2186 [(set (match_operand:DI 0 "register_operand" "=r")
2187 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2188 (match_operand:DI 2 "mode_width_operand" "n")
2189 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2190 UNSPEC_INSXH))]
2191 ""
2192 "ins%M2h %1,%3,%0"
2193 [(set_attr "type" "shift")])
2195 (define_insn "mskxl_le"
2196 [(set (match_operand:DI 0 "register_operand" "=r")
2197 (and:DI (not:DI (ashift:DI
2198 (match_operand:DI 2 "mode_mask_operand" "n")
2199 (ashift:DI
2200 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2201 (const_int 3))))
2202 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2203 "! WORDS_BIG_ENDIAN"
2204 "msk%U2l %r1,%3,%0"
2205 [(set_attr "type" "shift")])
2207 (define_insn "mskxl_be"
2208 [(set (match_operand:DI 0 "register_operand" "=r")
2209 (and:DI (not:DI (ashift:DI
2210 (match_operand:DI 2 "mode_mask_operand" "n")
2211 (minus:DI (const_int 56)
2212 (ashift:DI
2213 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2214 (const_int 3)))))
2215 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2216 "WORDS_BIG_ENDIAN"
2217 "msk%U2l %r1,%3,%0"
2218 [(set_attr "type" "shift")])
2220 ;; We do not include the mskXh insns because it does not appear we would
2221 ;; ever generate one.
2222 ;;
2223 ;; Again, we do for block moves and we use unspec again.
2225 (define_insn "mskxh"
2226 [(set (match_operand:DI 0 "register_operand" "=r")
2227 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2228 (match_operand:DI 2 "mode_width_operand" "n")
2229 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2230 UNSPEC_MSKXH))]
2231 ""
2232 "msk%M2h %1,%3,%0"
2233 [(set_attr "type" "shift")])
2235 ;; Prefer AND + NE over LSHIFTRT + AND.
2237 (define_insn_and_split "*ze_and_ne"
2238 [(set (match_operand:DI 0 "register_operand" "=r")
2239 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2240 (const_int 1)
2241 (match_operand 2 "const_int_operand" "I")))]
2242 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2243 "#"
2244 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2245 [(set (match_dup 0)
2246 (and:DI (match_dup 1) (match_dup 3)))
2247 (set (match_dup 0)
2248 (ne:DI (match_dup 0) (const_int 0)))]
2249 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2250 \f
2251 ;; Floating-point operations. All the double-precision insns can extend
2252 ;; from single, so indicate that. The exception are the ones that simply
2253 ;; play with the sign bits; it's not clear what to do there.
2255 (define_insn "abssf2"
2256 [(set (match_operand:SF 0 "register_operand" "=f")
2257 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2258 "TARGET_FP"
2259 "cpys $f31,%R1,%0"
2260 [(set_attr "type" "fcpys")])
2262 (define_insn "*nabssf2"
2263 [(set (match_operand:SF 0 "register_operand" "=f")
2264 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2265 "TARGET_FP"
2266 "cpysn $f31,%R1,%0"
2267 [(set_attr "type" "fadd")])
2269 (define_insn "absdf2"
2270 [(set (match_operand:DF 0 "register_operand" "=f")
2271 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2272 "TARGET_FP"
2273 "cpys $f31,%R1,%0"
2274 [(set_attr "type" "fcpys")])
2276 (define_insn "*nabsdf2"
2277 [(set (match_operand:DF 0 "register_operand" "=f")
2278 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2279 "TARGET_FP"
2280 "cpysn $f31,%R1,%0"
2281 [(set_attr "type" "fadd")])
2283 (define_expand "abstf2"
2284 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2285 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2286 (use (match_dup 2))])]
2287 "TARGET_HAS_XFLOATING_LIBS"
2288 {
2289 #if HOST_BITS_PER_WIDE_INT >= 64
2290 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2291 #else
2292 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2293 #endif
2294 })
2296 (define_insn_and_split "*abstf_internal"
2297 [(set (match_operand:TF 0 "register_operand" "=r")
2298 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2299 (use (match_operand:DI 2 "register_operand" "r"))]
2300 "TARGET_HAS_XFLOATING_LIBS"
2301 "#"
2302 "&& reload_completed"
2303 [(const_int 0)]
2304 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2306 (define_insn "negsf2"
2307 [(set (match_operand:SF 0 "register_operand" "=f")
2308 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2309 "TARGET_FP"
2310 "cpysn %R1,%R1,%0"
2311 [(set_attr "type" "fadd")])
2313 (define_insn "negdf2"
2314 [(set (match_operand:DF 0 "register_operand" "=f")
2315 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2316 "TARGET_FP"
2317 "cpysn %R1,%R1,%0"
2318 [(set_attr "type" "fadd")])
2320 (define_expand "negtf2"
2321 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2322 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2323 (use (match_dup 2))])]
2324 "TARGET_HAS_XFLOATING_LIBS"
2325 {
2326 #if HOST_BITS_PER_WIDE_INT >= 64
2327 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2328 #else
2329 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2330 #endif
2331 })
2333 (define_insn_and_split "*negtf_internal"
2334 [(set (match_operand:TF 0 "register_operand" "=r")
2335 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2336 (use (match_operand:DI 2 "register_operand" "r"))]
2337 "TARGET_HAS_XFLOATING_LIBS"
2338 "#"
2339 "&& reload_completed"
2340 [(const_int 0)]
2341 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2343 (define_insn "copysignsf3"
2344 [(set (match_operand:SF 0 "register_operand" "=f")
2345 (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2346 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2347 UNSPEC_COPYSIGN))]
2348 "TARGET_FP"
2349 "cpys %R2,%R1,%0"
2350 [(set_attr "type" "fadd")])
2352 (define_insn "*ncopysignsf3"
2353 [(set (match_operand:SF 0 "register_operand" "=f")
2354 (neg:SF (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2355 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2356 UNSPEC_COPYSIGN)))]
2357 "TARGET_FP"
2358 "cpysn %R2,%R1,%0"
2359 [(set_attr "type" "fadd")])
2361 (define_insn "copysigndf3"
2362 [(set (match_operand:DF 0 "register_operand" "=f")
2363 (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2364 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2365 UNSPEC_COPYSIGN))]
2366 "TARGET_FP"
2367 "cpys %R2,%R1,%0"
2368 [(set_attr "type" "fadd")])
2370 (define_insn "*ncopysigndf3"
2371 [(set (match_operand:DF 0 "register_operand" "=f")
2372 (neg:DF (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2373 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2374 UNSPEC_COPYSIGN)))]
2375 "TARGET_FP"
2376 "cpysn %R2,%R1,%0"
2377 [(set_attr "type" "fadd")])
2379 (define_insn "*addsf_ieee"
2380 [(set (match_operand:SF 0 "register_operand" "=&f")
2381 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2382 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2383 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2384 "add%,%/ %R1,%R2,%0"
2385 [(set_attr "type" "fadd")
2386 (set_attr "trap" "yes")
2387 (set_attr "round_suffix" "normal")
2388 (set_attr "trap_suffix" "u_su_sui")])
2390 (define_insn "addsf3"
2391 [(set (match_operand:SF 0 "register_operand" "=f")
2392 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2393 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2394 "TARGET_FP"
2395 "add%,%/ %R1,%R2,%0"
2396 [(set_attr "type" "fadd")
2397 (set_attr "trap" "yes")
2398 (set_attr "round_suffix" "normal")
2399 (set_attr "trap_suffix" "u_su_sui")])
2401 (define_insn "*adddf_ieee"
2402 [(set (match_operand:DF 0 "register_operand" "=&f")
2403 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2404 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2405 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2406 "add%-%/ %R1,%R2,%0"
2407 [(set_attr "type" "fadd")
2408 (set_attr "trap" "yes")
2409 (set_attr "round_suffix" "normal")
2410 (set_attr "trap_suffix" "u_su_sui")])
2412 (define_insn "adddf3"
2413 [(set (match_operand:DF 0 "register_operand" "=f")
2414 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2415 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2416 "TARGET_FP"
2417 "add%-%/ %R1,%R2,%0"
2418 [(set_attr "type" "fadd")
2419 (set_attr "trap" "yes")
2420 (set_attr "round_suffix" "normal")
2421 (set_attr "trap_suffix" "u_su_sui")])
2423 (define_insn "*adddf_ext1"
2424 [(set (match_operand:DF 0 "register_operand" "=f")
2425 (plus:DF (float_extend:DF
2426 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2427 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2428 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2429 "add%-%/ %R1,%R2,%0"
2430 [(set_attr "type" "fadd")
2431 (set_attr "trap" "yes")
2432 (set_attr "round_suffix" "normal")
2433 (set_attr "trap_suffix" "u_su_sui")])
2435 (define_insn "*adddf_ext2"
2436 [(set (match_operand:DF 0 "register_operand" "=f")
2437 (plus:DF (float_extend:DF
2438 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2439 (float_extend:DF
2440 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2441 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2442 "add%-%/ %R1,%R2,%0"
2443 [(set_attr "type" "fadd")
2444 (set_attr "trap" "yes")
2445 (set_attr "round_suffix" "normal")
2446 (set_attr "trap_suffix" "u_su_sui")])
2448 (define_expand "addtf3"
2449 [(use (match_operand 0 "register_operand" ""))
2450 (use (match_operand 1 "general_operand" ""))
2451 (use (match_operand 2 "general_operand" ""))]
2452 "TARGET_HAS_XFLOATING_LIBS"
2453 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2455 ;; Define conversion operators between DFmode and SImode, using the cvtql
2456 ;; instruction. To allow combine et al to do useful things, we keep the
2457 ;; operation as a unit until after reload, at which point we split the
2458 ;; instructions.
2459 ;;
2460 ;; Note that we (attempt to) only consider this optimization when the
2461 ;; ultimate destination is memory. If we will be doing further integer
2462 ;; processing, it is cheaper to do the truncation in the int regs.
2464 (define_insn "*cvtql"
2465 [(set (match_operand:SF 0 "register_operand" "=f")
2466 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2467 UNSPEC_CVTQL))]
2468 "TARGET_FP"
2469 "cvtql%/ %R1,%0"
2470 [(set_attr "type" "fadd")
2471 (set_attr "trap" "yes")
2472 (set_attr "trap_suffix" "v_sv")])
2474 (define_insn_and_split "*fix_truncdfsi_ieee"
2475 [(set (match_operand:SI 0 "memory_operand" "=m")
2476 (subreg:SI
2477 (match_operator:DI 4 "fix_operator"
2478 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2479 (clobber (match_scratch:DI 2 "=&f"))
2480 (clobber (match_scratch:SF 3 "=&f"))]
2481 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2482 "#"
2483 "&& reload_completed"
2484 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
2485 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2486 (set (match_dup 5) (match_dup 3))]
2487 {
2488 operands[5] = adjust_address (operands[0], SFmode, 0);
2489 }
2490 [(set_attr "type" "fadd")
2491 (set_attr "trap" "yes")])
2493 (define_insn_and_split "*fix_truncdfsi_internal"
2494 [(set (match_operand:SI 0 "memory_operand" "=m")
2495 (subreg:SI
2496 (match_operator:DI 3 "fix_operator"
2497 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2498 (clobber (match_scratch:DI 2 "=f"))]
2499 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2500 "#"
2501 "&& reload_completed"
2502 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
2503 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2504 (set (match_dup 5) (match_dup 4))]
2505 {
2506 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2507 operands[5] = adjust_address (operands[0], SFmode, 0);
2508 }
2509 [(set_attr "type" "fadd")
2510 (set_attr "trap" "yes")])
2512 (define_insn "*fix_truncdfdi_ieee"
2513 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2514 (match_operator:DI 2 "fix_operator"
2515 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2516 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2517 "cvt%-q%/ %R1,%0"
2518 [(set_attr "type" "fadd")
2519 (set_attr "trap" "yes")
2520 (set_attr "round_suffix" "c")
2521 (set_attr "trap_suffix" "v_sv_svi")])
2523 (define_insn "*fix_truncdfdi2"
2524 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2525 (match_operator:DI 2 "fix_operator"
2526 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2527 "TARGET_FP"
2528 "cvt%-q%/ %R1,%0"
2529 [(set_attr "type" "fadd")
2530 (set_attr "trap" "yes")
2531 (set_attr "round_suffix" "c")
2532 (set_attr "trap_suffix" "v_sv_svi")])
2534 (define_expand "fix_truncdfdi2"
2535 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2536 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2537 "TARGET_FP"
2538 "")
2540 (define_expand "fixuns_truncdfdi2"
2541 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2542 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2543 "TARGET_FP"
2544 "")
2546 ;; Likewise between SFmode and SImode.
2548 (define_insn_and_split "*fix_truncsfsi_ieee"
2549 [(set (match_operand:SI 0 "memory_operand" "=m")
2550 (subreg:SI
2551 (match_operator:DI 4 "fix_operator"
2552 [(float_extend:DF
2553 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2554 (clobber (match_scratch:DI 2 "=&f"))
2555 (clobber (match_scratch:SF 3 "=&f"))]
2556 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2557 "#"
2558 "&& reload_completed"
2559 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
2560 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2561 (set (match_dup 5) (match_dup 3))]
2562 {
2563 operands[5] = adjust_address (operands[0], SFmode, 0);
2564 }
2565 [(set_attr "type" "fadd")
2566 (set_attr "trap" "yes")])
2568 (define_insn_and_split "*fix_truncsfsi_internal"
2569 [(set (match_operand:SI 0 "memory_operand" "=m")
2570 (subreg:SI
2571 (match_operator:DI 3 "fix_operator"
2572 [(float_extend:DF
2573 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2574 (clobber (match_scratch:DI 2 "=f"))]
2575 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2576 "#"
2577 "&& reload_completed"
2578 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
2579 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2580 (set (match_dup 5) (match_dup 4))]
2581 {
2582 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2583 operands[5] = adjust_address (operands[0], SFmode, 0);
2584 }
2585 [(set_attr "type" "fadd")
2586 (set_attr "trap" "yes")])
2588 (define_insn "*fix_truncsfdi_ieee"
2589 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2590 (match_operator:DI 2 "fix_operator"
2591 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2592 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2593 "cvt%-q%/ %R1,%0"
2594 [(set_attr "type" "fadd")
2595 (set_attr "trap" "yes")
2596 (set_attr "round_suffix" "c")
2597 (set_attr "trap_suffix" "v_sv_svi")])
2599 (define_insn "*fix_truncsfdi2"
2600 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2601 (match_operator:DI 2 "fix_operator"
2602 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2603 "TARGET_FP"
2604 "cvt%-q%/ %R1,%0"
2605 [(set_attr "type" "fadd")
2606 (set_attr "trap" "yes")
2607 (set_attr "round_suffix" "c")
2608 (set_attr "trap_suffix" "v_sv_svi")])
2610 (define_expand "fix_truncsfdi2"
2611 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2612 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2613 "TARGET_FP"
2614 "")
2616 (define_expand "fixuns_truncsfdi2"
2617 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2618 (unsigned_fix:DI
2619 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2620 "TARGET_FP"
2621 "")
2623 (define_expand "fix_trunctfdi2"
2624 [(use (match_operand:DI 0 "register_operand" ""))
2625 (use (match_operand:TF 1 "general_operand" ""))]
2626 "TARGET_HAS_XFLOATING_LIBS"
2627 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2629 (define_expand "fixuns_trunctfdi2"
2630 [(use (match_operand:DI 0 "register_operand" ""))
2631 (use (match_operand:TF 1 "general_operand" ""))]
2632 "TARGET_HAS_XFLOATING_LIBS"
2633 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
2635 (define_insn "*floatdisf_ieee"
2636 [(set (match_operand:SF 0 "register_operand" "=&f")
2637 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2638 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2639 "cvtq%,%/ %1,%0"
2640 [(set_attr "type" "fadd")
2641 (set_attr "trap" "yes")
2642 (set_attr "round_suffix" "normal")
2643 (set_attr "trap_suffix" "sui")])
2645 (define_insn "floatdisf2"
2646 [(set (match_operand:SF 0 "register_operand" "=f")
2647 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2648 "TARGET_FP"
2649 "cvtq%,%/ %1,%0"
2650 [(set_attr "type" "fadd")
2651 (set_attr "trap" "yes")
2652 (set_attr "round_suffix" "normal")
2653 (set_attr "trap_suffix" "sui")])
2655 (define_insn_and_split "*floatsisf2_ieee"
2656 [(set (match_operand:SF 0 "register_operand" "=&f")
2657 (float:SF (match_operand:SI 1 "memory_operand" "m")))
2658 (clobber (match_scratch:DI 2 "=&f"))
2659 (clobber (match_scratch:SF 3 "=&f"))]
2660 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2661 "#"
2662 "&& reload_completed"
2663 [(set (match_dup 3) (match_dup 1))
2664 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2665 (set (match_dup 0) (float:SF (match_dup 2)))]
2666 {
2667 operands[1] = adjust_address (operands[1], SFmode, 0);
2668 })
2670 (define_insn_and_split "*floatsisf2"
2671 [(set (match_operand:SF 0 "register_operand" "=f")
2672 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
2673 "TARGET_FP"
2674 "#"
2675 "&& reload_completed"
2676 [(set (match_dup 0) (match_dup 1))
2677 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
2678 (set (match_dup 0) (float:SF (match_dup 2)))]
2679 {
2680 operands[1] = adjust_address (operands[1], SFmode, 0);
2681 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2682 })
2684 (define_insn "*floatdidf_ieee"
2685 [(set (match_operand:DF 0 "register_operand" "=&f")
2686 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2687 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2688 "cvtq%-%/ %1,%0"
2689 [(set_attr "type" "fadd")
2690 (set_attr "trap" "yes")
2691 (set_attr "round_suffix" "normal")
2692 (set_attr "trap_suffix" "sui")])
2694 (define_insn "floatdidf2"
2695 [(set (match_operand:DF 0 "register_operand" "=f")
2696 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2697 "TARGET_FP"
2698 "cvtq%-%/ %1,%0"
2699 [(set_attr "type" "fadd")
2700 (set_attr "trap" "yes")
2701 (set_attr "round_suffix" "normal")
2702 (set_attr "trap_suffix" "sui")])
2704 (define_insn_and_split "*floatsidf2_ieee"
2705 [(set (match_operand:DF 0 "register_operand" "=&f")
2706 (float:DF (match_operand:SI 1 "memory_operand" "m")))
2707 (clobber (match_scratch:DI 2 "=&f"))
2708 (clobber (match_scratch:SF 3 "=&f"))]
2709 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2710 "#"
2711 "&& reload_completed"
2712 [(set (match_dup 3) (match_dup 1))
2713 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2714 (set (match_dup 0) (float:DF (match_dup 2)))]
2715 {
2716 operands[1] = adjust_address (operands[1], SFmode, 0);
2717 })
2719 (define_insn_and_split "*floatsidf2"
2720 [(set (match_operand:DF 0 "register_operand" "=f")
2721 (float:DF (match_operand:SI 1 "memory_operand" "m")))]
2722 "TARGET_FP"
2723 "#"
2724 "&& reload_completed"
2725 [(set (match_dup 3) (match_dup 1))
2726 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2727 (set (match_dup 0) (float:DF (match_dup 2)))]
2728 {
2729 operands[1] = adjust_address (operands[1], SFmode, 0);
2730 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2731 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
2732 })
2734 (define_expand "floatditf2"
2735 [(use (match_operand:TF 0 "register_operand" ""))
2736 (use (match_operand:DI 1 "general_operand" ""))]
2737 "TARGET_HAS_XFLOATING_LIBS"
2738 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2740 (define_expand "floatunsdisf2"
2741 [(use (match_operand:SF 0 "register_operand" ""))
2742 (use (match_operand:DI 1 "register_operand" ""))]
2743 "TARGET_FP"
2744 "alpha_emit_floatuns (operands); DONE;")
2746 (define_expand "floatunsdidf2"
2747 [(use (match_operand:DF 0 "register_operand" ""))
2748 (use (match_operand:DI 1 "register_operand" ""))]
2749 "TARGET_FP"
2750 "alpha_emit_floatuns (operands); DONE;")
2752 (define_expand "floatunsditf2"
2753 [(use (match_operand:TF 0 "register_operand" ""))
2754 (use (match_operand:DI 1 "general_operand" ""))]
2755 "TARGET_HAS_XFLOATING_LIBS"
2756 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2758 (define_expand "extendsfdf2"
2759 [(set (match_operand:DF 0 "register_operand" "")
2760 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2761 "TARGET_FP"
2762 {
2763 if (alpha_fptm >= ALPHA_FPTM_SU)
2764 operands[1] = force_reg (SFmode, operands[1]);
2765 })
2767 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2768 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2770 (define_insn "*extendsfdf2_ieee"
2771 [(set (match_operand:DF 0 "register_operand" "=&f")
2772 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2773 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2774 "cvtsts %1,%0"
2775 [(set_attr "type" "fadd")
2776 (set_attr "trap" "yes")])
2778 (define_insn "*extendsfdf2_internal"
2779 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2780 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2781 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2782 "@
2783 cpys %1,%1,%0
2784 ld%, %0,%1
2785 st%- %1,%0"
2786 [(set_attr "type" "fcpys,fld,fst")])
2788 ;; Use register_operand for operand 1 to prevent compress_float_constant
2789 ;; from doing something silly. When optimizing we'll put things back
2790 ;; together anyway.
2791 (define_expand "extendsftf2"
2792 [(use (match_operand:TF 0 "register_operand" ""))
2793 (use (match_operand:SF 1 "register_operand" ""))]
2794 "TARGET_HAS_XFLOATING_LIBS"
2795 {
2796 rtx tmp = gen_reg_rtx (DFmode);
2797 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2798 emit_insn (gen_extenddftf2 (operands[0], tmp));
2799 DONE;
2800 })
2802 (define_expand "extenddftf2"
2803 [(use (match_operand:TF 0 "register_operand" ""))
2804 (use (match_operand:DF 1 "register_operand" ""))]
2805 "TARGET_HAS_XFLOATING_LIBS"
2806 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2808 (define_insn "*truncdfsf2_ieee"
2809 [(set (match_operand:SF 0 "register_operand" "=&f")
2810 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2811 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2812 "cvt%-%,%/ %R1,%0"
2813 [(set_attr "type" "fadd")
2814 (set_attr "trap" "yes")
2815 (set_attr "round_suffix" "normal")
2816 (set_attr "trap_suffix" "u_su_sui")])
2818 (define_insn "truncdfsf2"
2819 [(set (match_operand:SF 0 "register_operand" "=f")
2820 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2821 "TARGET_FP"
2822 "cvt%-%,%/ %R1,%0"
2823 [(set_attr "type" "fadd")
2824 (set_attr "trap" "yes")
2825 (set_attr "round_suffix" "normal")
2826 (set_attr "trap_suffix" "u_su_sui")])
2828 (define_expand "trunctfdf2"
2829 [(use (match_operand:DF 0 "register_operand" ""))
2830 (use (match_operand:TF 1 "general_operand" ""))]
2831 "TARGET_HAS_XFLOATING_LIBS"
2832 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2834 (define_expand "trunctfsf2"
2835 [(use (match_operand:SF 0 "register_operand" ""))
2836 (use (match_operand:TF 1 "general_operand" ""))]
2837 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2838 {
2839 rtx tmpf, sticky, arg, lo, hi;
2841 tmpf = gen_reg_rtx (DFmode);
2842 sticky = gen_reg_rtx (DImode);
2843 arg = copy_to_mode_reg (TFmode, operands[1]);
2844 lo = gen_lowpart (DImode, arg);
2845 hi = gen_highpart (DImode, arg);
2847 /* Convert the low word of the TFmode value into a sticky rounding bit,
2848 then or it into the low bit of the high word. This leaves the sticky
2849 bit at bit 48 of the fraction, which is representable in DFmode,
2850 which prevents rounding error in the final conversion to SFmode. */
2852 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2853 gen_rtx_NE (DImode, lo, const0_rtx)));
2854 emit_insn (gen_iordi3 (hi, hi, sticky));
2855 emit_insn (gen_trunctfdf2 (tmpf, arg));
2856 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2857 DONE;
2858 })
2860 (define_insn "*divsf3_ieee"
2861 [(set (match_operand:SF 0 "register_operand" "=&f")
2862 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2863 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2864 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2865 "div%,%/ %R1,%R2,%0"
2866 [(set_attr "type" "fdiv")
2867 (set_attr "opsize" "si")
2868 (set_attr "trap" "yes")
2869 (set_attr "round_suffix" "normal")
2870 (set_attr "trap_suffix" "u_su_sui")])
2872 (define_insn "divsf3"
2873 [(set (match_operand:SF 0 "register_operand" "=f")
2874 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2875 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2876 "TARGET_FP"
2877 "div%,%/ %R1,%R2,%0"
2878 [(set_attr "type" "fdiv")
2879 (set_attr "opsize" "si")
2880 (set_attr "trap" "yes")
2881 (set_attr "round_suffix" "normal")
2882 (set_attr "trap_suffix" "u_su_sui")])
2884 (define_insn "*divdf3_ieee"
2885 [(set (match_operand:DF 0 "register_operand" "=&f")
2886 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2887 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2888 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2889 "div%-%/ %R1,%R2,%0"
2890 [(set_attr "type" "fdiv")
2891 (set_attr "trap" "yes")
2892 (set_attr "round_suffix" "normal")
2893 (set_attr "trap_suffix" "u_su_sui")])
2895 (define_insn "divdf3"
2896 [(set (match_operand:DF 0 "register_operand" "=f")
2897 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2898 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2899 "TARGET_FP"
2900 "div%-%/ %R1,%R2,%0"
2901 [(set_attr "type" "fdiv")
2902 (set_attr "trap" "yes")
2903 (set_attr "round_suffix" "normal")
2904 (set_attr "trap_suffix" "u_su_sui")])
2906 (define_insn "*divdf_ext1"
2907 [(set (match_operand:DF 0 "register_operand" "=f")
2908 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2909 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2910 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2911 "div%-%/ %R1,%R2,%0"
2912 [(set_attr "type" "fdiv")
2913 (set_attr "trap" "yes")
2914 (set_attr "round_suffix" "normal")
2915 (set_attr "trap_suffix" "u_su_sui")])
2917 (define_insn "*divdf_ext2"
2918 [(set (match_operand:DF 0 "register_operand" "=f")
2919 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2920 (float_extend:DF
2921 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2922 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2923 "div%-%/ %R1,%R2,%0"
2924 [(set_attr "type" "fdiv")
2925 (set_attr "trap" "yes")
2926 (set_attr "round_suffix" "normal")
2927 (set_attr "trap_suffix" "u_su_sui")])
2929 (define_insn "*divdf_ext3"
2930 [(set (match_operand:DF 0 "register_operand" "=f")
2931 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2932 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2933 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2934 "div%-%/ %R1,%R2,%0"
2935 [(set_attr "type" "fdiv")
2936 (set_attr "trap" "yes")
2937 (set_attr "round_suffix" "normal")
2938 (set_attr "trap_suffix" "u_su_sui")])
2940 (define_expand "divtf3"
2941 [(use (match_operand 0 "register_operand" ""))
2942 (use (match_operand 1 "general_operand" ""))
2943 (use (match_operand 2 "general_operand" ""))]
2944 "TARGET_HAS_XFLOATING_LIBS"
2945 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2947 (define_insn "*mulsf3_ieee"
2948 [(set (match_operand:SF 0 "register_operand" "=&f")
2949 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2950 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2951 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2952 "mul%,%/ %R1,%R2,%0"
2953 [(set_attr "type" "fmul")
2954 (set_attr "trap" "yes")
2955 (set_attr "round_suffix" "normal")
2956 (set_attr "trap_suffix" "u_su_sui")])
2958 (define_insn "mulsf3"
2959 [(set (match_operand:SF 0 "register_operand" "=f")
2960 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2961 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2962 "TARGET_FP"
2963 "mul%,%/ %R1,%R2,%0"
2964 [(set_attr "type" "fmul")
2965 (set_attr "trap" "yes")
2966 (set_attr "round_suffix" "normal")
2967 (set_attr "trap_suffix" "u_su_sui")])
2969 (define_insn "*muldf3_ieee"
2970 [(set (match_operand:DF 0 "register_operand" "=&f")
2971 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2972 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2973 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2974 "mul%-%/ %R1,%R2,%0"
2975 [(set_attr "type" "fmul")
2976 (set_attr "trap" "yes")
2977 (set_attr "round_suffix" "normal")
2978 (set_attr "trap_suffix" "u_su_sui")])
2980 (define_insn "muldf3"
2981 [(set (match_operand:DF 0 "register_operand" "=f")
2982 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2983 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2984 "TARGET_FP"
2985 "mul%-%/ %R1,%R2,%0"
2986 [(set_attr "type" "fmul")
2987 (set_attr "trap" "yes")
2988 (set_attr "round_suffix" "normal")
2989 (set_attr "trap_suffix" "u_su_sui")])
2991 (define_insn "*muldf_ext1"
2992 [(set (match_operand:DF 0 "register_operand" "=f")
2993 (mult:DF (float_extend:DF
2994 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2995 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2996 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2997 "mul%-%/ %R1,%R2,%0"
2998 [(set_attr "type" "fmul")
2999 (set_attr "trap" "yes")
3000 (set_attr "round_suffix" "normal")
3001 (set_attr "trap_suffix" "u_su_sui")])
3003 (define_insn "*muldf_ext2"
3004 [(set (match_operand:DF 0 "register_operand" "=f")
3005 (mult:DF (float_extend:DF
3006 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
3007 (float_extend:DF
3008 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3009 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3010 "mul%-%/ %R1,%R2,%0"
3011 [(set_attr "type" "fmul")
3012 (set_attr "trap" "yes")
3013 (set_attr "round_suffix" "normal")
3014 (set_attr "trap_suffix" "u_su_sui")])
3016 (define_expand "multf3"
3017 [(use (match_operand 0 "register_operand" ""))
3018 (use (match_operand 1 "general_operand" ""))
3019 (use (match_operand 2 "general_operand" ""))]
3020 "TARGET_HAS_XFLOATING_LIBS"
3021 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
3023 (define_insn "*subsf3_ieee"
3024 [(set (match_operand:SF 0 "register_operand" "=&f")
3025 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
3026 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
3027 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3028 "sub%,%/ %R1,%R2,%0"
3029 [(set_attr "type" "fadd")
3030 (set_attr "trap" "yes")
3031 (set_attr "round_suffix" "normal")
3032 (set_attr "trap_suffix" "u_su_sui")])
3034 (define_insn "subsf3"
3035 [(set (match_operand:SF 0 "register_operand" "=f")
3036 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
3037 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
3038 "TARGET_FP"
3039 "sub%,%/ %R1,%R2,%0"
3040 [(set_attr "type" "fadd")
3041 (set_attr "trap" "yes")
3042 (set_attr "round_suffix" "normal")
3043 (set_attr "trap_suffix" "u_su_sui")])
3045 (define_insn "*subdf3_ieee"
3046 [(set (match_operand:DF 0 "register_operand" "=&f")
3047 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3048 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3049 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3050 "sub%-%/ %R1,%R2,%0"
3051 [(set_attr "type" "fadd")
3052 (set_attr "trap" "yes")
3053 (set_attr "round_suffix" "normal")
3054 (set_attr "trap_suffix" "u_su_sui")])
3056 (define_insn "subdf3"
3057 [(set (match_operand:DF 0 "register_operand" "=f")
3058 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3059 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3060 "TARGET_FP"
3061 "sub%-%/ %R1,%R2,%0"
3062 [(set_attr "type" "fadd")
3063 (set_attr "trap" "yes")
3064 (set_attr "round_suffix" "normal")
3065 (set_attr "trap_suffix" "u_su_sui")])
3067 (define_insn "*subdf_ext1"
3068 [(set (match_operand:DF 0 "register_operand" "=f")
3069 (minus:DF (float_extend:DF
3070 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3071 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3072 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3073 "sub%-%/ %R1,%R2,%0"
3074 [(set_attr "type" "fadd")
3075 (set_attr "trap" "yes")
3076 (set_attr "round_suffix" "normal")
3077 (set_attr "trap_suffix" "u_su_sui")])
3079 (define_insn "*subdf_ext2"
3080 [(set (match_operand:DF 0 "register_operand" "=f")
3081 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3082 (float_extend:DF
3083 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3084 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3085 "sub%-%/ %R1,%R2,%0"
3086 [(set_attr "type" "fadd")
3087 (set_attr "trap" "yes")
3088 (set_attr "round_suffix" "normal")
3089 (set_attr "trap_suffix" "u_su_sui")])
3091 (define_insn "*subdf_ext3"
3092 [(set (match_operand:DF 0 "register_operand" "=f")
3093 (minus:DF (float_extend:DF
3094 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3095 (float_extend:DF
3096 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3097 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3098 "sub%-%/ %R1,%R2,%0"
3099 [(set_attr "type" "fadd")
3100 (set_attr "trap" "yes")
3101 (set_attr "round_suffix" "normal")
3102 (set_attr "trap_suffix" "u_su_sui")])
3104 (define_expand "subtf3"
3105 [(use (match_operand 0 "register_operand" ""))
3106 (use (match_operand 1 "general_operand" ""))
3107 (use (match_operand 2 "general_operand" ""))]
3108 "TARGET_HAS_XFLOATING_LIBS"
3109 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
3111 (define_insn "*sqrtsf2_ieee"
3112 [(set (match_operand:SF 0 "register_operand" "=&f")
3113 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3114 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3115 "sqrt%,%/ %R1,%0"
3116 [(set_attr "type" "fsqrt")
3117 (set_attr "opsize" "si")
3118 (set_attr "trap" "yes")
3119 (set_attr "round_suffix" "normal")
3120 (set_attr "trap_suffix" "u_su_sui")])
3122 (define_insn "sqrtsf2"
3123 [(set (match_operand:SF 0 "register_operand" "=f")
3124 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3125 "TARGET_FP && TARGET_FIX"
3126 "sqrt%,%/ %R1,%0"
3127 [(set_attr "type" "fsqrt")
3128 (set_attr "opsize" "si")
3129 (set_attr "trap" "yes")
3130 (set_attr "round_suffix" "normal")
3131 (set_attr "trap_suffix" "u_su_sui")])
3133 (define_insn "*sqrtdf2_ieee"
3134 [(set (match_operand:DF 0 "register_operand" "=&f")
3135 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3136 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3137 "sqrt%-%/ %R1,%0"
3138 [(set_attr "type" "fsqrt")
3139 (set_attr "trap" "yes")
3140 (set_attr "round_suffix" "normal")
3141 (set_attr "trap_suffix" "u_su_sui")])
3143 (define_insn "sqrtdf2"
3144 [(set (match_operand:DF 0 "register_operand" "=f")
3145 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3146 "TARGET_FP && TARGET_FIX"
3147 "sqrt%-%/ %R1,%0"
3148 [(set_attr "type" "fsqrt")
3149 (set_attr "trap" "yes")
3150 (set_attr "round_suffix" "normal")
3151 (set_attr "trap_suffix" "u_su_sui")])
3152 \f
3153 ;; Next are all the integer comparisons, and conditional moves and branches
3154 ;; and some of the related define_expand's and define_split's.
3156 (define_insn "*setcc_internal"
3157 [(set (match_operand 0 "register_operand" "=r")
3158 (match_operator 1 "alpha_comparison_operator"
3159 [(match_operand:DI 2 "register_operand" "r")
3160 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3161 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3162 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3163 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3164 "cmp%C1 %2,%3,%0"
3165 [(set_attr "type" "icmp")])
3167 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3168 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3169 ;; from cse on.
3170 (define_insn "*setcc_swapped_internal"
3171 [(set (match_operand 0 "register_operand" "=r")
3172 (match_operator 1 "alpha_swapped_comparison_operator"
3173 [(match_operand:DI 2 "register_operand" "r")
3174 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3175 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3176 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3177 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3178 "cmp%c1 %r3,%2,%0"
3179 [(set_attr "type" "icmp")])
3181 ;; Use match_operator rather than ne directly so that we can match
3182 ;; multiple integer modes.
3183 (define_insn "*setne_internal"
3184 [(set (match_operand 0 "register_operand" "=r")
3185 (match_operator 1 "signed_comparison_operator"
3186 [(match_operand:DI 2 "register_operand" "r")
3187 (const_int 0)]))]
3188 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3189 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3190 && GET_CODE (operands[1]) == NE
3191 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3192 "cmpult $31,%2,%0"
3193 [(set_attr "type" "icmp")])
3195 ;; The mode folding trick can't be used with const_int operands, since
3196 ;; reload needs to know the proper mode.
3197 ;;
3198 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3199 ;; in order to create more pairs of constants. As long as we're allowing
3200 ;; two constants at the same time, and will have to reload one of them...
3202 (define_insn "*movqicc_internal"
3203 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3204 (if_then_else:QI
3205 (match_operator 2 "signed_comparison_operator"
3206 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3207 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3208 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3209 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3210 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3211 "@
3212 cmov%C2 %r3,%1,%0
3213 cmov%D2 %r3,%5,%0
3214 cmov%c2 %r4,%1,%0
3215 cmov%d2 %r4,%5,%0"
3216 [(set_attr "type" "icmov")])
3218 (define_insn "*movhicc_internal"
3219 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3220 (if_then_else:HI
3221 (match_operator 2 "signed_comparison_operator"
3222 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3223 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3224 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3225 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3226 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3227 "@
3228 cmov%C2 %r3,%1,%0
3229 cmov%D2 %r3,%5,%0
3230 cmov%c2 %r4,%1,%0
3231 cmov%d2 %r4,%5,%0"
3232 [(set_attr "type" "icmov")])
3234 (define_insn "*movsicc_internal"
3235 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3236 (if_then_else:SI
3237 (match_operator 2 "signed_comparison_operator"
3238 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3239 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3240 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3241 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3242 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3243 "@
3244 cmov%C2 %r3,%1,%0
3245 cmov%D2 %r3,%5,%0
3246 cmov%c2 %r4,%1,%0
3247 cmov%d2 %r4,%5,%0"
3248 [(set_attr "type" "icmov")])
3250 (define_insn "*movdicc_internal"
3251 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3252 (if_then_else:DI
3253 (match_operator 2 "signed_comparison_operator"
3254 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3255 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3256 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3257 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3258 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3259 "@
3260 cmov%C2 %r3,%1,%0
3261 cmov%D2 %r3,%5,%0
3262 cmov%c2 %r4,%1,%0
3263 cmov%d2 %r4,%5,%0"
3264 [(set_attr "type" "icmov")])
3266 (define_insn "*movqicc_lbc"
3267 [(set (match_operand:QI 0 "register_operand" "=r,r")
3268 (if_then_else:QI
3269 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3270 (const_int 1)
3271 (const_int 0))
3272 (const_int 0))
3273 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3274 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3275 ""
3276 "@
3277 cmovlbc %r2,%1,%0
3278 cmovlbs %r2,%3,%0"
3279 [(set_attr "type" "icmov")])
3281 (define_insn "*movhicc_lbc"
3282 [(set (match_operand:HI 0 "register_operand" "=r,r")
3283 (if_then_else:HI
3284 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3285 (const_int 1)
3286 (const_int 0))
3287 (const_int 0))
3288 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3289 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3290 ""
3291 "@
3292 cmovlbc %r2,%1,%0
3293 cmovlbs %r2,%3,%0"
3294 [(set_attr "type" "icmov")])
3296 (define_insn "*movsicc_lbc"
3297 [(set (match_operand:SI 0 "register_operand" "=r,r")
3298 (if_then_else:SI
3299 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3300 (const_int 1)
3301 (const_int 0))
3302 (const_int 0))
3303 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3304 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3305 ""
3306 "@
3307 cmovlbc %r2,%1,%0
3308 cmovlbs %r2,%3,%0"
3309 [(set_attr "type" "icmov")])
3311 (define_insn "*movdicc_lbc"
3312 [(set (match_operand:DI 0 "register_operand" "=r,r")
3313 (if_then_else:DI
3314 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3315 (const_int 1)
3316 (const_int 0))
3317 (const_int 0))
3318 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3319 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3320 ""
3321 "@
3322 cmovlbc %r2,%1,%0
3323 cmovlbs %r2,%3,%0"
3324 [(set_attr "type" "icmov")])
3326 (define_insn "*movqicc_lbs"
3327 [(set (match_operand:QI 0 "register_operand" "=r,r")
3328 (if_then_else:QI
3329 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3330 (const_int 1)
3331 (const_int 0))
3332 (const_int 0))
3333 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3334 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3335 ""
3336 "@
3337 cmovlbs %r2,%1,%0
3338 cmovlbc %r2,%3,%0"
3339 [(set_attr "type" "icmov")])
3341 (define_insn "*movhicc_lbs"
3342 [(set (match_operand:HI 0 "register_operand" "=r,r")
3343 (if_then_else:HI
3344 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3345 (const_int 1)
3346 (const_int 0))
3347 (const_int 0))
3348 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3349 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3350 ""
3351 "@
3352 cmovlbs %r2,%1,%0
3353 cmovlbc %r2,%3,%0"
3354 [(set_attr "type" "icmov")])
3356 (define_insn "*movsicc_lbs"
3357 [(set (match_operand:SI 0 "register_operand" "=r,r")
3358 (if_then_else:SI
3359 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3360 (const_int 1)
3361 (const_int 0))
3362 (const_int 0))
3363 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3364 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3365 ""
3366 "@
3367 cmovlbs %r2,%1,%0
3368 cmovlbc %r2,%3,%0"
3369 [(set_attr "type" "icmov")])
3371 (define_insn "*movdicc_lbs"
3372 [(set (match_operand:DI 0 "register_operand" "=r,r")
3373 (if_then_else:DI
3374 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3375 (const_int 1)
3376 (const_int 0))
3377 (const_int 0))
3378 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3379 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3380 ""
3381 "@
3382 cmovlbs %r2,%1,%0
3383 cmovlbc %r2,%3,%0"
3384 [(set_attr "type" "icmov")])
3386 ;; For ABS, we have two choices, depending on whether the input and output
3387 ;; registers are the same or not.
3388 (define_expand "absdi2"
3389 [(set (match_operand:DI 0 "register_operand" "")
3390 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3391 ""
3392 {
3393 if (rtx_equal_p (operands[0], operands[1]))
3394 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3395 else
3396 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3397 DONE;
3398 })
3400 (define_expand "absdi2_same"
3401 [(set (match_operand:DI 1 "register_operand" "")
3402 (neg:DI (match_operand:DI 0 "register_operand" "")))
3403 (set (match_dup 0)
3404 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3405 (match_dup 0)
3406 (match_dup 1)))]
3407 ""
3408 "")
3410 (define_expand "absdi2_diff"
3411 [(set (match_operand:DI 0 "register_operand" "")
3412 (neg:DI (match_operand:DI 1 "register_operand" "")))
3413 (set (match_dup 0)
3414 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3415 (match_dup 0)
3416 (match_dup 1)))]
3417 ""
3418 "")
3420 (define_split
3421 [(set (match_operand:DI 0 "register_operand" "")
3422 (abs:DI (match_dup 0)))
3423 (clobber (match_operand:DI 1 "register_operand" ""))]
3424 ""
3425 [(set (match_dup 1) (neg:DI (match_dup 0)))
3426 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3427 (match_dup 0) (match_dup 1)))]
3428 "")
3430 (define_split
3431 [(set (match_operand:DI 0 "register_operand" "")
3432 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3433 "! rtx_equal_p (operands[0], operands[1])"
3434 [(set (match_dup 0) (neg:DI (match_dup 1)))
3435 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3436 (match_dup 0) (match_dup 1)))]
3437 "")
3439 (define_split
3440 [(set (match_operand:DI 0 "register_operand" "")
3441 (neg:DI (abs:DI (match_dup 0))))
3442 (clobber (match_operand:DI 1 "register_operand" ""))]
3443 ""
3444 [(set (match_dup 1) (neg:DI (match_dup 0)))
3445 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3446 (match_dup 0) (match_dup 1)))]
3447 "")
3449 (define_split
3450 [(set (match_operand:DI 0 "register_operand" "")
3451 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3452 "! rtx_equal_p (operands[0], operands[1])"
3453 [(set (match_dup 0) (neg:DI (match_dup 1)))
3454 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3455 (match_dup 0) (match_dup 1)))]
3456 "")
3458 (define_insn "sminqi3"
3459 [(set (match_operand:QI 0 "register_operand" "=r")
3460 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3461 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3462 "TARGET_MAX"
3463 "minsb8 %r1,%2,%0"
3464 [(set_attr "type" "mvi")])
3466 (define_insn "uminqi3"
3467 [(set (match_operand:QI 0 "register_operand" "=r")
3468 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3469 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3470 "TARGET_MAX"
3471 "minub8 %r1,%2,%0"
3472 [(set_attr "type" "mvi")])
3474 (define_insn "smaxqi3"
3475 [(set (match_operand:QI 0 "register_operand" "=r")
3476 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3477 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3478 "TARGET_MAX"
3479 "maxsb8 %r1,%2,%0"
3480 [(set_attr "type" "mvi")])
3482 (define_insn "umaxqi3"
3483 [(set (match_operand:QI 0 "register_operand" "=r")
3484 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3485 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3486 "TARGET_MAX"
3487 "maxub8 %r1,%2,%0"
3488 [(set_attr "type" "mvi")])
3490 (define_insn "sminhi3"
3491 [(set (match_operand:HI 0 "register_operand" "=r")
3492 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3493 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3494 "TARGET_MAX"
3495 "minsw4 %r1,%2,%0"
3496 [(set_attr "type" "mvi")])
3498 (define_insn "uminhi3"
3499 [(set (match_operand:HI 0 "register_operand" "=r")
3500 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3501 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3502 "TARGET_MAX"
3503 "minuw4 %r1,%2,%0"
3504 [(set_attr "type" "mvi")])
3506 (define_insn "smaxhi3"
3507 [(set (match_operand:HI 0 "register_operand" "=r")
3508 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3509 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3510 "TARGET_MAX"
3511 "maxsw4 %r1,%2,%0"
3512 [(set_attr "type" "mvi")])
3514 (define_insn "umaxhi3"
3515 [(set (match_operand:HI 0 "register_operand" "=r")
3516 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3517 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3518 "TARGET_MAX"
3519 "maxuw4 %r1,%2,%0"
3520 [(set_attr "type" "mvi")])
3522 (define_expand "smaxdi3"
3523 [(set (match_dup 3)
3524 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3525 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3526 (set (match_operand:DI 0 "register_operand" "")
3527 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3528 (match_dup 1) (match_dup 2)))]
3529 ""
3530 { operands[3] = gen_reg_rtx (DImode); })
3532 (define_split
3533 [(set (match_operand:DI 0 "register_operand" "")
3534 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3535 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3536 (clobber (match_operand:DI 3 "register_operand" ""))]
3537 "operands[2] != const0_rtx"
3538 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3539 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3540 (match_dup 1) (match_dup 2)))]
3541 "")
3543 (define_insn "*smax_const0"
3544 [(set (match_operand:DI 0 "register_operand" "=r")
3545 (smax:DI (match_operand:DI 1 "register_operand" "0")
3546 (const_int 0)))]
3547 ""
3548 "cmovlt %0,0,%0"
3549 [(set_attr "type" "icmov")])
3551 (define_expand "smindi3"
3552 [(set (match_dup 3)
3553 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3554 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3555 (set (match_operand:DI 0 "register_operand" "")
3556 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3557 (match_dup 1) (match_dup 2)))]
3558 ""
3559 { operands[3] = gen_reg_rtx (DImode); })
3561 (define_split
3562 [(set (match_operand:DI 0 "register_operand" "")
3563 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3564 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3565 (clobber (match_operand:DI 3 "register_operand" ""))]
3566 "operands[2] != const0_rtx"
3567 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3568 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3569 (match_dup 1) (match_dup 2)))]
3570 "")
3572 (define_insn "*smin_const0"
3573 [(set (match_operand:DI 0 "register_operand" "=r")
3574 (smin:DI (match_operand:DI 1 "register_operand" "0")
3575 (const_int 0)))]
3576 ""
3577 "cmovgt %0,0,%0"
3578 [(set_attr "type" "icmov")])
3580 (define_expand "umaxdi3"
3581 [(set (match_dup 3)
3582 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3583 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3584 (set (match_operand:DI 0 "register_operand" "")
3585 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3586 (match_dup 1) (match_dup 2)))]
3587 ""
3588 "operands[3] = gen_reg_rtx (DImode);")
3590 (define_split
3591 [(set (match_operand:DI 0 "register_operand" "")
3592 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3593 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3594 (clobber (match_operand:DI 3 "register_operand" ""))]
3595 "operands[2] != const0_rtx"
3596 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3597 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3598 (match_dup 1) (match_dup 2)))]
3599 "")
3601 (define_expand "umindi3"
3602 [(set (match_dup 3)
3603 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3604 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3605 (set (match_operand:DI 0 "register_operand" "")
3606 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3607 (match_dup 1) (match_dup 2)))]
3608 ""
3609 "operands[3] = gen_reg_rtx (DImode);")
3611 (define_split
3612 [(set (match_operand:DI 0 "register_operand" "")
3613 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3614 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3615 (clobber (match_operand:DI 3 "register_operand" ""))]
3616 "operands[2] != const0_rtx"
3617 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3618 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3619 (match_dup 1) (match_dup 2)))]
3620 "")
3622 (define_insn "*bcc_normal"
3623 [(set (pc)
3624 (if_then_else
3625 (match_operator 1 "signed_comparison_operator"
3626 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3627 (const_int 0)])
3628 (label_ref (match_operand 0 "" ""))
3629 (pc)))]
3630 ""
3631 "b%C1 %r2,%0"
3632 [(set_attr "type" "ibr")])
3634 (define_insn "*bcc_reverse"
3635 [(set (pc)
3636 (if_then_else
3637 (match_operator 1 "signed_comparison_operator"
3638 [(match_operand:DI 2 "register_operand" "r")
3639 (const_int 0)])
3641 (pc)
3642 (label_ref (match_operand 0 "" ""))))]
3643 ""
3644 "b%c1 %2,%0"
3645 [(set_attr "type" "ibr")])
3647 (define_insn "*blbs_normal"
3648 [(set (pc)
3649 (if_then_else
3650 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3651 (const_int 1)
3652 (const_int 0))
3653 (const_int 0))
3654 (label_ref (match_operand 0 "" ""))
3655 (pc)))]
3656 ""
3657 "blbs %r1,%0"
3658 [(set_attr "type" "ibr")])
3660 (define_insn "*blbc_normal"
3661 [(set (pc)
3662 (if_then_else
3663 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3664 (const_int 1)
3665 (const_int 0))
3666 (const_int 0))
3667 (label_ref (match_operand 0 "" ""))
3668 (pc)))]
3669 ""
3670 "blbc %r1,%0"
3671 [(set_attr "type" "ibr")])
3673 (define_split
3674 [(parallel
3675 [(set (pc)
3676 (if_then_else
3677 (match_operator 1 "comparison_operator"
3678 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3679 (const_int 1)
3680 (match_operand:DI 3 "const_int_operand" ""))
3681 (const_int 0)])
3682 (label_ref (match_operand 0 "" ""))
3683 (pc)))
3684 (clobber (match_operand:DI 4 "register_operand" ""))])]
3685 "INTVAL (operands[3]) != 0"
3686 [(set (match_dup 4)
3687 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3688 (set (pc)
3689 (if_then_else (match_op_dup 1
3690 [(zero_extract:DI (match_dup 4)
3691 (const_int 1)
3692 (const_int 0))
3693 (const_int 0)])
3694 (label_ref (match_dup 0))
3695 (pc)))]
3696 "")
3697 \f
3698 ;; The following are the corresponding floating-point insns. Recall
3699 ;; we need to have variants that expand the arguments from SFmode
3700 ;; to DFmode.
3702 (define_insn "*cmpdf_ieee"
3703 [(set (match_operand:DF 0 "register_operand" "=&f")
3704 (match_operator:DF 1 "alpha_fp_comparison_operator"
3705 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3706 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3707 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3708 "cmp%-%C1%/ %R2,%R3,%0"
3709 [(set_attr "type" "fadd")
3710 (set_attr "trap" "yes")
3711 (set_attr "trap_suffix" "su")])
3713 (define_insn "*cmpdf_internal"
3714 [(set (match_operand:DF 0 "register_operand" "=f")
3715 (match_operator:DF 1 "alpha_fp_comparison_operator"
3716 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3717 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3718 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3719 "cmp%-%C1%/ %R2,%R3,%0"
3720 [(set_attr "type" "fadd")
3721 (set_attr "trap" "yes")
3722 (set_attr "trap_suffix" "su")])
3724 (define_insn "*cmpdf_ieee_ext1"
3725 [(set (match_operand:DF 0 "register_operand" "=&f")
3726 (match_operator:DF 1 "alpha_fp_comparison_operator"
3727 [(float_extend:DF
3728 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3729 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3730 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3731 "cmp%-%C1%/ %R2,%R3,%0"
3732 [(set_attr "type" "fadd")
3733 (set_attr "trap" "yes")
3734 (set_attr "trap_suffix" "su")])
3736 (define_insn "*cmpdf_ext1"
3737 [(set (match_operand:DF 0 "register_operand" "=f")
3738 (match_operator:DF 1 "alpha_fp_comparison_operator"
3739 [(float_extend:DF
3740 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3741 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3742 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3743 "cmp%-%C1%/ %R2,%R3,%0"
3744 [(set_attr "type" "fadd")
3745 (set_attr "trap" "yes")
3746 (set_attr "trap_suffix" "su")])
3748 (define_insn "*cmpdf_ieee_ext2"
3749 [(set (match_operand:DF 0 "register_operand" "=&f")
3750 (match_operator:DF 1 "alpha_fp_comparison_operator"
3751 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3752 (float_extend:DF
3753 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3754 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3755 "cmp%-%C1%/ %R2,%R3,%0"
3756 [(set_attr "type" "fadd")
3757 (set_attr "trap" "yes")
3758 (set_attr "trap_suffix" "su")])
3760 (define_insn "*cmpdf_ext2"
3761 [(set (match_operand:DF 0 "register_operand" "=f")
3762 (match_operator:DF 1 "alpha_fp_comparison_operator"
3763 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3764 (float_extend:DF
3765 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3766 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3767 "cmp%-%C1%/ %R2,%R3,%0"
3768 [(set_attr "type" "fadd")
3769 (set_attr "trap" "yes")
3770 (set_attr "trap_suffix" "su")])
3772 (define_insn "*cmpdf_ieee_ext3"
3773 [(set (match_operand:DF 0 "register_operand" "=&f")
3774 (match_operator:DF 1 "alpha_fp_comparison_operator"
3775 [(float_extend:DF
3776 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3777 (float_extend:DF
3778 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3779 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3780 "cmp%-%C1%/ %R2,%R3,%0"
3781 [(set_attr "type" "fadd")
3782 (set_attr "trap" "yes")
3783 (set_attr "trap_suffix" "su")])
3785 (define_insn "*cmpdf_ext3"
3786 [(set (match_operand:DF 0 "register_operand" "=f")
3787 (match_operator:DF 1 "alpha_fp_comparison_operator"
3788 [(float_extend:DF
3789 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3790 (float_extend:DF
3791 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3792 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3793 "cmp%-%C1%/ %R2,%R3,%0"
3794 [(set_attr "type" "fadd")
3795 (set_attr "trap" "yes")
3796 (set_attr "trap_suffix" "su")])
3798 (define_insn "*movdfcc_internal"
3799 [(set (match_operand:DF 0 "register_operand" "=f,f")
3800 (if_then_else:DF
3801 (match_operator 3 "signed_comparison_operator"
3802 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3803 (match_operand:DF 2 "const0_operand" "G,G")])
3804 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3805 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3806 "TARGET_FP"
3807 "@
3808 fcmov%C3 %R4,%R1,%0
3809 fcmov%D3 %R4,%R5,%0"
3810 [(set_attr "type" "fcmov")])
3812 (define_insn "*movsfcc_internal"
3813 [(set (match_operand:SF 0 "register_operand" "=f,f")
3814 (if_then_else:SF
3815 (match_operator 3 "signed_comparison_operator"
3816 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3817 (match_operand:DF 2 "const0_operand" "G,G")])
3818 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3819 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3820 "TARGET_FP"
3821 "@
3822 fcmov%C3 %R4,%R1,%0
3823 fcmov%D3 %R4,%R5,%0"
3824 [(set_attr "type" "fcmov")])
3826 (define_insn "*movdfcc_ext1"
3827 [(set (match_operand:DF 0 "register_operand" "=f,f")
3828 (if_then_else:DF
3829 (match_operator 3 "signed_comparison_operator"
3830 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3831 (match_operand:DF 2 "const0_operand" "G,G")])
3832 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3833 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3834 "TARGET_FP"
3835 "@
3836 fcmov%C3 %R4,%R1,%0
3837 fcmov%D3 %R4,%R5,%0"
3838 [(set_attr "type" "fcmov")])
3840 (define_insn "*movdfcc_ext2"
3841 [(set (match_operand:DF 0 "register_operand" "=f,f")
3842 (if_then_else:DF
3843 (match_operator 3 "signed_comparison_operator"
3844 [(float_extend:DF
3845 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3846 (match_operand:DF 2 "const0_operand" "G,G")])
3847 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3848 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3849 "TARGET_FP"
3850 "@
3851 fcmov%C3 %R4,%R1,%0
3852 fcmov%D3 %R4,%R5,%0"
3853 [(set_attr "type" "fcmov")])
3855 (define_insn "*movdfcc_ext3"
3856 [(set (match_operand:SF 0 "register_operand" "=f,f")
3857 (if_then_else:SF
3858 (match_operator 3 "signed_comparison_operator"
3859 [(float_extend:DF
3860 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3861 (match_operand:DF 2 "const0_operand" "G,G")])
3862 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3863 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3864 "TARGET_FP"
3865 "@
3866 fcmov%C3 %R4,%R1,%0
3867 fcmov%D3 %R4,%R5,%0"
3868 [(set_attr "type" "fcmov")])
3870 (define_insn "*movdfcc_ext4"
3871 [(set (match_operand:DF 0 "register_operand" "=f,f")
3872 (if_then_else:DF
3873 (match_operator 3 "signed_comparison_operator"
3874 [(float_extend:DF
3875 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3876 (match_operand:DF 2 "const0_operand" "G,G")])
3877 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3878 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3879 "TARGET_FP"
3880 "@
3881 fcmov%C3 %R4,%R1,%0
3882 fcmov%D3 %R4,%R5,%0"
3883 [(set_attr "type" "fcmov")])
3885 (define_expand "smaxdf3"
3886 [(set (match_dup 3)
3887 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3888 (match_operand:DF 2 "reg_or_0_operand" "")))
3889 (set (match_operand:DF 0 "register_operand" "")
3890 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3891 (match_dup 1) (match_dup 2)))]
3892 "TARGET_FP"
3893 {
3894 operands[3] = gen_reg_rtx (DFmode);
3895 operands[4] = CONST0_RTX (DFmode);
3896 })
3898 (define_expand "smindf3"
3899 [(set (match_dup 3)
3900 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3901 (match_operand:DF 2 "reg_or_0_operand" "")))
3902 (set (match_operand:DF 0 "register_operand" "")
3903 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3904 (match_dup 1) (match_dup 2)))]
3905 "TARGET_FP"
3906 {
3907 operands[3] = gen_reg_rtx (DFmode);
3908 operands[4] = CONST0_RTX (DFmode);
3909 })
3911 (define_expand "smaxsf3"
3912 [(set (match_dup 3)
3913 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3914 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3915 (set (match_operand:SF 0 "register_operand" "")
3916 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3917 (match_dup 1) (match_dup 2)))]
3918 "TARGET_FP"
3919 {
3920 operands[3] = gen_reg_rtx (DFmode);
3921 operands[4] = CONST0_RTX (DFmode);
3922 })
3924 (define_expand "sminsf3"
3925 [(set (match_dup 3)
3926 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3927 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3928 (set (match_operand:SF 0 "register_operand" "")
3929 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3930 (match_dup 1) (match_dup 2)))]
3931 "TARGET_FP"
3932 {
3933 operands[3] = gen_reg_rtx (DFmode);
3934 operands[4] = CONST0_RTX (DFmode);
3935 })
3937 (define_insn "*fbcc_normal"
3938 [(set (pc)
3939 (if_then_else
3940 (match_operator 1 "signed_comparison_operator"
3941 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3942 (match_operand:DF 3 "const0_operand" "G")])
3943 (label_ref (match_operand 0 "" ""))
3944 (pc)))]
3945 "TARGET_FP"
3946 "fb%C1 %R2,%0"
3947 [(set_attr "type" "fbr")])
3949 (define_insn "*fbcc_ext_normal"
3950 [(set (pc)
3951 (if_then_else
3952 (match_operator 1 "signed_comparison_operator"
3953 [(float_extend:DF
3954 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3955 (match_operand:DF 3 "const0_operand" "G")])
3956 (label_ref (match_operand 0 "" ""))
3957 (pc)))]
3958 "TARGET_FP"
3959 "fb%C1 %R2,%0"
3960 [(set_attr "type" "fbr")])
3961 \f
3962 ;; These are the main define_expand's used to make conditional branches
3963 ;; and compares.
3965 (define_expand "cmpdf"
3966 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3967 (match_operand:DF 1 "reg_or_0_operand" "")))]
3968 "TARGET_FP"
3969 {
3970 alpha_compare.op0 = operands[0];
3971 alpha_compare.op1 = operands[1];
3972 alpha_compare.fp_p = 1;
3973 DONE;
3974 })
3976 (define_expand "cmptf"
3977 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3978 (match_operand:TF 1 "general_operand" "")))]
3979 "TARGET_HAS_XFLOATING_LIBS"
3980 {
3981 alpha_compare.op0 = operands[0];
3982 alpha_compare.op1 = operands[1];
3983 alpha_compare.fp_p = 1;
3984 DONE;
3985 })
3987 (define_expand "cmpdi"
3988 [(set (cc0) (compare (match_operand:DI 0 "some_operand" "")
3989 (match_operand:DI 1 "some_operand" "")))]
3990 ""
3991 {
3992 alpha_compare.op0 = operands[0];
3993 alpha_compare.op1 = operands[1];
3994 alpha_compare.fp_p = 0;
3995 DONE;
3996 })
3998 (define_expand "beq"
3999 [(set (pc)
4000 (if_then_else (match_dup 1)
4001 (label_ref (match_operand 0 "" ""))
4002 (pc)))]
4003 ""
4004 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
4006 (define_expand "bne"
4007 [(set (pc)
4008 (if_then_else (match_dup 1)
4009 (label_ref (match_operand 0 "" ""))
4010 (pc)))]
4011 ""
4012 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
4014 (define_expand "blt"
4015 [(set (pc)
4016 (if_then_else (match_dup 1)
4017 (label_ref (match_operand 0 "" ""))
4018 (pc)))]
4019 ""
4020 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
4022 (define_expand "ble"
4023 [(set (pc)
4024 (if_then_else (match_dup 1)
4025 (label_ref (match_operand 0 "" ""))
4026 (pc)))]
4027 ""
4028 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
4030 (define_expand "bgt"
4031 [(set (pc)
4032 (if_then_else (match_dup 1)
4033 (label_ref (match_operand 0 "" ""))
4034 (pc)))]
4035 ""
4036 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
4038 (define_expand "bge"
4039 [(set (pc)
4040 (if_then_else (match_dup 1)
4041 (label_ref (match_operand 0 "" ""))
4042 (pc)))]
4043 ""
4044 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
4046 (define_expand "bltu"
4047 [(set (pc)
4048 (if_then_else (match_dup 1)
4049 (label_ref (match_operand 0 "" ""))
4050 (pc)))]
4051 ""
4052 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
4054 (define_expand "bleu"
4055 [(set (pc)
4056 (if_then_else (match_dup 1)
4057 (label_ref (match_operand 0 "" ""))
4058 (pc)))]
4059 ""
4060 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
4062 (define_expand "bgtu"
4063 [(set (pc)
4064 (if_then_else (match_dup 1)
4065 (label_ref (match_operand 0 "" ""))
4066 (pc)))]
4067 ""
4068 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
4070 (define_expand "bgeu"
4071 [(set (pc)
4072 (if_then_else (match_dup 1)
4073 (label_ref (match_operand 0 "" ""))
4074 (pc)))]
4075 ""
4076 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
4078 (define_expand "bunordered"
4079 [(set (pc)
4080 (if_then_else (match_dup 1)
4081 (label_ref (match_operand 0 "" ""))
4082 (pc)))]
4083 ""
4084 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
4086 (define_expand "bordered"
4087 [(set (pc)
4088 (if_then_else (match_dup 1)
4089 (label_ref (match_operand 0 "" ""))
4090 (pc)))]
4091 ""
4092 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
4094 (define_expand "seq"
4095 [(set (match_operand:DI 0 "register_operand" "")
4096 (match_dup 1))]
4097 ""
4098 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
4100 (define_expand "sne"
4101 [(set (match_operand:DI 0 "register_operand" "")
4102 (match_dup 1))]
4103 ""
4104 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
4106 (define_expand "slt"
4107 [(set (match_operand:DI 0 "register_operand" "")
4108 (match_dup 1))]
4109 ""
4110 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
4112 (define_expand "sle"
4113 [(set (match_operand:DI 0 "register_operand" "")
4114 (match_dup 1))]
4115 ""
4116 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
4118 (define_expand "sgt"
4119 [(set (match_operand:DI 0 "register_operand" "")
4120 (match_dup 1))]
4121 ""
4122 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
4124 (define_expand "sge"
4125 [(set (match_operand:DI 0 "register_operand" "")
4126 (match_dup 1))]
4127 ""
4128 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
4130 (define_expand "sltu"
4131 [(set (match_operand:DI 0 "register_operand" "")
4132 (match_dup 1))]
4133 ""
4134 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4136 (define_expand "sleu"
4137 [(set (match_operand:DI 0 "register_operand" "")
4138 (match_dup 1))]
4139 ""
4140 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4142 (define_expand "sgtu"
4143 [(set (match_operand:DI 0 "register_operand" "")
4144 (match_dup 1))]
4145 ""
4146 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4148 (define_expand "sgeu"
4149 [(set (match_operand:DI 0 "register_operand" "")
4150 (match_dup 1))]
4151 ""
4152 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4154 (define_expand "sunordered"
4155 [(set (match_operand:DI 0 "register_operand" "")
4156 (match_dup 1))]
4157 ""
4158 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4160 (define_expand "sordered"
4161 [(set (match_operand:DI 0 "register_operand" "")
4162 (match_dup 1))]
4163 ""
4164 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4165 \f
4166 ;; These are the main define_expand's used to make conditional moves.
4168 (define_expand "movsicc"
4169 [(set (match_operand:SI 0 "register_operand" "")
4170 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4171 (match_operand:SI 2 "reg_or_8bit_operand" "")
4172 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4173 ""
4174 {
4175 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4176 FAIL;
4177 })
4179 (define_expand "movdicc"
4180 [(set (match_operand:DI 0 "register_operand" "")
4181 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4182 (match_operand:DI 2 "reg_or_8bit_operand" "")
4183 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4184 ""
4185 {
4186 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4187 FAIL;
4188 })
4190 (define_expand "movsfcc"
4191 [(set (match_operand:SF 0 "register_operand" "")
4192 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4193 (match_operand:SF 2 "reg_or_8bit_operand" "")
4194 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4195 ""
4196 {
4197 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4198 FAIL;
4199 })
4201 (define_expand "movdfcc"
4202 [(set (match_operand:DF 0 "register_operand" "")
4203 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4204 (match_operand:DF 2 "reg_or_8bit_operand" "")
4205 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4206 ""
4207 {
4208 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4209 FAIL;
4210 })
4211 \f
4212 ;; These define_split definitions are used in cases when comparisons have
4213 ;; not be stated in the correct way and we need to reverse the second
4214 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4215 ;; comparison that tests the result being reversed. We have one define_split
4216 ;; for each use of a comparison. They do not match valid insns and need
4217 ;; not generate valid insns.
4218 ;;
4219 ;; We can also handle equality comparisons (and inequality comparisons in
4220 ;; cases where the resulting add cannot overflow) by doing an add followed by
4221 ;; a comparison with zero. This is faster since the addition takes one
4222 ;; less cycle than a compare when feeding into a conditional move.
4223 ;; For this case, we also have an SImode pattern since we can merge the add
4224 ;; and sign extend and the order doesn't matter.
4225 ;;
4226 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4227 ;; operation could have been generated.
4229 (define_split
4230 [(set (match_operand:DI 0 "register_operand" "")
4231 (if_then_else:DI
4232 (match_operator 1 "comparison_operator"
4233 [(match_operand:DI 2 "reg_or_0_operand" "")
4234 (match_operand:DI 3 "reg_or_cint_operand" "")])
4235 (match_operand:DI 4 "reg_or_cint_operand" "")
4236 (match_operand:DI 5 "reg_or_cint_operand" "")))
4237 (clobber (match_operand:DI 6 "register_operand" ""))]
4238 "operands[3] != const0_rtx"
4239 [(set (match_dup 6) (match_dup 7))
4240 (set (match_dup 0)
4241 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4242 {
4243 enum rtx_code code = GET_CODE (operands[1]);
4244 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4246 /* If we are comparing for equality with a constant and that constant
4247 appears in the arm when the register equals the constant, use the
4248 register since that is more likely to match (and to produce better code
4249 if both would). */
4251 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4252 && rtx_equal_p (operands[4], operands[3]))
4253 operands[4] = operands[2];
4255 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4256 && rtx_equal_p (operands[5], operands[3]))
4257 operands[5] = operands[2];
4259 if (code == NE || code == EQ
4260 || (extended_count (operands[2], DImode, unsignedp) >= 1
4261 && extended_count (operands[3], DImode, unsignedp) >= 1))
4262 {
4263 if (GET_CODE (operands[3]) == CONST_INT)
4264 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4265 GEN_INT (- INTVAL (operands[3])));
4266 else
4267 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4269 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4270 }
4272 else if (code == EQ || code == LE || code == LT
4273 || code == LEU || code == LTU)
4274 {
4275 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4276 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4277 }
4278 else
4279 {
4280 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4281 operands[2], operands[3]);
4282 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4283 }
4284 })
4286 (define_split
4287 [(set (match_operand:DI 0 "register_operand" "")
4288 (if_then_else:DI
4289 (match_operator 1 "comparison_operator"
4290 [(match_operand:SI 2 "reg_or_0_operand" "")
4291 (match_operand:SI 3 "reg_or_cint_operand" "")])
4292 (match_operand:DI 4 "reg_or_8bit_operand" "")
4293 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4294 (clobber (match_operand:DI 6 "register_operand" ""))]
4295 "operands[3] != const0_rtx
4296 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4297 [(set (match_dup 6) (match_dup 7))
4298 (set (match_dup 0)
4299 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4300 {
4301 enum rtx_code code = GET_CODE (operands[1]);
4302 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4303 rtx tem;
4305 if ((code != NE && code != EQ
4306 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4307 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4308 FAIL;
4310 if (GET_CODE (operands[3]) == CONST_INT)
4311 tem = gen_rtx_PLUS (SImode, operands[2],
4312 GEN_INT (- INTVAL (operands[3])));
4313 else
4314 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4316 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4317 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4318 operands[6], const0_rtx);
4319 })
4321 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4323 (define_split
4324 [(set (match_operand 0 "register_operand" "")
4325 (if_then_else (match_operator 1 "signed_comparison_operator"
4326 [(match_operand:DI 2 "reg_or_0_operand" "")
4327 (const_int 0)])
4328 (match_operand 3 "const_int_operand" "")
4329 (match_operand 4 "const_int_operand" "")))]
4330 ""
4331 [(const_int 0)]
4332 {
4333 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4334 operands[2], operands[3], operands[4]))
4335 DONE;
4336 else
4337 FAIL;
4338 })
4340 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4341 ;; Oh well, we match it in movcc, so it must be partially our fault.
4342 (define_split
4343 [(set (match_operand 0 "register_operand" "")
4344 (if_then_else (match_operator 1 "signed_comparison_operator"
4345 [(const_int 0)
4346 (match_operand:DI 2 "reg_or_0_operand" "")])
4347 (match_operand 3 "const_int_operand" "")
4348 (match_operand 4 "const_int_operand" "")))]
4349 ""
4350 [(const_int 0)]
4351 {
4352 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4353 operands[0], operands[2], operands[3],
4354 operands[4]))
4355 DONE;
4356 else
4357 FAIL;
4358 })
4360 (define_insn_and_split "*cmp_sadd_di"
4361 [(set (match_operand:DI 0 "register_operand" "=r")
4362 (plus:DI (if_then_else:DI
4363 (match_operator 1 "alpha_zero_comparison_operator"
4364 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4365 (const_int 0)])
4366 (match_operand:DI 3 "const48_operand" "I")
4367 (const_int 0))
4368 (match_operand:DI 4 "sext_add_operand" "rIO")))
4369 (clobber (match_scratch:DI 5 "=r"))]
4370 ""
4371 "#"
4372 ""
4373 [(set (match_dup 5)
4374 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4375 (set (match_dup 0)
4376 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4377 (match_dup 4)))]
4378 {
4379 if (can_create_pseudo_p ())
4380 operands[5] = gen_reg_rtx (DImode);
4381 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4382 operands[5] = operands[0];
4383 })
4385 (define_insn_and_split "*cmp_sadd_si"
4386 [(set (match_operand:SI 0 "register_operand" "=r")
4387 (plus:SI (if_then_else:SI
4388 (match_operator 1 "alpha_zero_comparison_operator"
4389 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4390 (const_int 0)])
4391 (match_operand:SI 3 "const48_operand" "I")
4392 (const_int 0))
4393 (match_operand:SI 4 "sext_add_operand" "rIO")))
4394 (clobber (match_scratch:SI 5 "=r"))]
4395 ""
4396 "#"
4397 ""
4398 [(set (match_dup 5)
4399 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4400 (set (match_dup 0)
4401 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4402 (match_dup 4)))]
4403 {
4404 if (can_create_pseudo_p ())
4405 operands[5] = gen_reg_rtx (DImode);
4406 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4407 operands[5] = operands[0];
4408 })
4410 (define_insn_and_split "*cmp_sadd_sidi"
4411 [(set (match_operand:DI 0 "register_operand" "=r")
4412 (sign_extend:DI
4413 (plus:SI (if_then_else:SI
4414 (match_operator 1 "alpha_zero_comparison_operator"
4415 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4416 (const_int 0)])
4417 (match_operand:SI 3 "const48_operand" "I")
4418 (const_int 0))
4419 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4420 (clobber (match_scratch:SI 5 "=r"))]
4421 ""
4422 "#"
4423 ""
4424 [(set (match_dup 5)
4425 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4426 (set (match_dup 0)
4427 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4428 (match_dup 4))))]
4429 {
4430 if (can_create_pseudo_p ())
4431 operands[5] = gen_reg_rtx (DImode);
4432 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4433 operands[5] = operands[0];
4434 })
4436 (define_insn_and_split "*cmp_ssub_di"
4437 [(set (match_operand:DI 0 "register_operand" "=r")
4438 (minus:DI (if_then_else:DI
4439 (match_operator 1 "alpha_zero_comparison_operator"
4440 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4441 (const_int 0)])
4442 (match_operand:DI 3 "const48_operand" "I")
4443 (const_int 0))
4444 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4445 (clobber (match_scratch:DI 5 "=r"))]
4446 ""
4447 "#"
4448 ""
4449 [(set (match_dup 5)
4450 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4451 (set (match_dup 0)
4452 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4453 (match_dup 4)))]
4454 {
4455 if (can_create_pseudo_p ())
4456 operands[5] = gen_reg_rtx (DImode);
4457 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4458 operands[5] = operands[0];
4459 })
4461 (define_insn_and_split "*cmp_ssub_si"
4462 [(set (match_operand:SI 0 "register_operand" "=r")
4463 (minus:SI (if_then_else:SI
4464 (match_operator 1 "alpha_zero_comparison_operator"
4465 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4466 (const_int 0)])
4467 (match_operand:SI 3 "const48_operand" "I")
4468 (const_int 0))
4469 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4470 (clobber (match_scratch:SI 5 "=r"))]
4471 ""
4472 "#"
4473 ""
4474 [(set (match_dup 5)
4475 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4476 (set (match_dup 0)
4477 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4478 (match_dup 4)))]
4479 {
4480 if (can_create_pseudo_p ())
4481 operands[5] = gen_reg_rtx (DImode);
4482 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4483 operands[5] = operands[0];
4484 })
4486 (define_insn_and_split "*cmp_ssub_sidi"
4487 [(set (match_operand:DI 0 "register_operand" "=r")
4488 (sign_extend:DI
4489 (minus:SI (if_then_else:SI
4490 (match_operator 1 "alpha_zero_comparison_operator"
4491 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4492 (const_int 0)])
4493 (match_operand:SI 3 "const48_operand" "I")
4494 (const_int 0))
4495 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4496 (clobber (match_scratch:SI 5 "=r"))]
4497 ""
4498 "#"
4499 ""
4500 [(set (match_dup 5)
4501 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4502 (set (match_dup 0)
4503 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4504 (match_dup 4))))]
4505 {
4506 if (can_create_pseudo_p ())
4507 operands[5] = gen_reg_rtx (DImode);
4508 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4509 operands[5] = operands[0];
4510 })
4511 \f
4512 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4513 ;; work differently, so we have different patterns for each.
4515 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4516 ;; call. The CIW contains information about arguments passed in registers
4517 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4518 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4519 ;; in the presence of inlining since the CIWs for calls performed by the
4520 ;; inlined function must be stored in the SSIB of the function it is inlined
4521 ;; into as well. We encode the CIW in an unspec and append it to the list
4522 ;; of the CIWs for the current function only when the instruction for loading
4523 ;; $25 is generated.
4525 (define_expand "call"
4526 [(use (match_operand:DI 0 "" ""))
4527 (use (match_operand 1 "" ""))
4528 (use (match_operand 2 "" ""))
4529 (use (match_operand 3 "" ""))]
4530 ""
4531 {
4532 if (TARGET_ABI_WINDOWS_NT)
4533 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4534 else if (TARGET_ABI_OPEN_VMS)
4535 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4536 else if (TARGET_ABI_UNICOSMK)
4537 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4538 else
4539 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4540 DONE;
4541 })
4543 (define_expand "sibcall"
4544 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4545 (match_operand 1 "" ""))
4546 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4547 "TARGET_ABI_OSF"
4548 {
4549 gcc_assert (GET_CODE (operands[0]) == MEM);
4550 operands[0] = XEXP (operands[0], 0);
4551 })
4553 (define_expand "call_osf"
4554 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4555 (match_operand 1 "" ""))
4556 (use (reg:DI 29))
4557 (clobber (reg:DI 26))])]
4558 ""
4559 {
4560 gcc_assert (GET_CODE (operands[0]) == MEM);
4562 operands[0] = XEXP (operands[0], 0);
4563 if (! call_operand (operands[0], Pmode))
4564 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4565 })
4567 (define_expand "call_nt"
4568 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4569 (match_operand 1 "" ""))
4570 (clobber (reg:DI 26))])]
4571 ""
4572 {
4573 gcc_assert (GET_CODE (operands[0]) == MEM);
4575 operands[0] = XEXP (operands[0], 0);
4576 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4577 operands[0] = force_reg (DImode, operands[0]);
4578 })
4580 ;; Calls on Unicos/Mk are always indirect.
4581 ;; op 0: symbol ref for called function
4582 ;; op 1: CIW for $25 represented by an unspec
4584 (define_expand "call_umk"
4585 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4586 (match_operand 1 "" ""))
4587 (use (reg:DI 25))
4588 (clobber (reg:DI 26))])]
4589 ""
4590 {
4591 gcc_assert (GET_CODE (operands[0]) == MEM);
4593 /* Always load the address of the called function into a register;
4594 load the CIW in $25. */
4596 operands[0] = XEXP (operands[0], 0);
4597 if (GET_CODE (operands[0]) != REG)
4598 operands[0] = force_reg (DImode, operands[0]);
4600 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4601 })
4603 ;;
4604 ;; call openvms/alpha
4605 ;; op 0: symbol ref for called function
4606 ;; op 1: next_arg_reg (argument information value for R25)
4607 ;;
4608 (define_expand "call_vms"
4609 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4610 (match_operand 1 "" ""))
4611 (use (match_dup 2))
4612 (use (reg:DI 25))
4613 (use (reg:DI 26))
4614 (clobber (reg:DI 27))])]
4615 ""
4616 {
4617 gcc_assert (GET_CODE (operands[0]) == MEM);
4619 operands[0] = XEXP (operands[0], 0);
4621 /* Always load AI with argument information, then handle symbolic and
4622 indirect call differently. Load RA and set operands[2] to PV in
4623 both cases. */
4625 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4626 if (GET_CODE (operands[0]) == SYMBOL_REF)
4627 {
4628 alpha_need_linkage (XSTR (operands[0], 0), 0);
4630 operands[2] = const0_rtx;
4631 }
4632 else
4633 {
4634 emit_move_insn (gen_rtx_REG (Pmode, 26),
4635 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4636 operands[2] = operands[0];
4637 }
4639 })
4641 (define_expand "call_value"
4642 [(use (match_operand 0 "" ""))
4643 (use (match_operand:DI 1 "" ""))
4644 (use (match_operand 2 "" ""))
4645 (use (match_operand 3 "" ""))
4646 (use (match_operand 4 "" ""))]
4647 ""
4648 {
4649 if (TARGET_ABI_WINDOWS_NT)
4650 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4651 else if (TARGET_ABI_OPEN_VMS)
4652 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4653 operands[3]));
4654 else if (TARGET_ABI_UNICOSMK)
4655 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4656 operands[3]));
4657 else
4658 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4659 operands[2]));
4660 DONE;
4661 })
4663 (define_expand "sibcall_value"
4664 [(parallel [(set (match_operand 0 "" "")
4665 (call (mem:DI (match_operand 1 "" ""))
4666 (match_operand 2 "" "")))
4667 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4668 "TARGET_ABI_OSF"
4669 {
4670 gcc_assert (GET_CODE (operands[1]) == MEM);
4671 operands[1] = XEXP (operands[1], 0);
4672 })
4674 (define_expand "call_value_osf"
4675 [(parallel [(set (match_operand 0 "" "")
4676 (call (mem:DI (match_operand 1 "" ""))
4677 (match_operand 2 "" "")))
4678 (use (reg:DI 29))
4679 (clobber (reg:DI 26))])]
4680 ""
4681 {
4682 gcc_assert (GET_CODE (operands[1]) == MEM);
4684 operands[1] = XEXP (operands[1], 0);
4685 if (! call_operand (operands[1], Pmode))
4686 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4687 })
4689 (define_expand "call_value_nt"
4690 [(parallel [(set (match_operand 0 "" "")
4691 (call (mem:DI (match_operand 1 "" ""))
4692 (match_operand 2 "" "")))
4693 (clobber (reg:DI 26))])]
4694 ""
4695 {
4696 gcc_assert (GET_CODE (operands[1]) == MEM);
4698 operands[1] = XEXP (operands[1], 0);
4699 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4700 operands[1] = force_reg (DImode, operands[1]);
4701 })
4703 (define_expand "call_value_vms"
4704 [(parallel [(set (match_operand 0 "" "")
4705 (call (mem:DI (match_operand:DI 1 "" ""))
4706 (match_operand 2 "" "")))
4707 (use (match_dup 3))
4708 (use (reg:DI 25))
4709 (use (reg:DI 26))
4710 (clobber (reg:DI 27))])]
4711 ""
4712 {
4713 gcc_assert (GET_CODE (operands[1]) == MEM);
4715 operands[1] = XEXP (operands[1], 0);
4717 /* Always load AI with argument information, then handle symbolic and
4718 indirect call differently. Load RA and set operands[3] to PV in
4719 both cases. */
4721 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4722 if (GET_CODE (operands[1]) == SYMBOL_REF)
4723 {
4724 alpha_need_linkage (XSTR (operands[1], 0), 0);
4726 operands[3] = const0_rtx;
4727 }
4728 else
4729 {
4730 emit_move_insn (gen_rtx_REG (Pmode, 26),
4731 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4732 operands[3] = operands[1];
4733 }
4734 })
4736 (define_expand "call_value_umk"
4737 [(parallel [(set (match_operand 0 "" "")
4738 (call (mem:DI (match_operand 1 "" ""))
4739 (match_operand 2 "" "")))
4740 (use (reg:DI 25))
4741 (clobber (reg:DI 26))])]
4742 ""
4743 {
4744 gcc_assert (GET_CODE (operands[1]) == MEM);
4746 operands[1] = XEXP (operands[1], 0);
4747 if (GET_CODE (operands[1]) != REG)
4748 operands[1] = force_reg (DImode, operands[1]);
4750 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4751 })
4753 (define_insn "*call_osf_1_er_noreturn"
4754 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4755 (match_operand 1 "" ""))
4756 (use (reg:DI 29))
4757 (clobber (reg:DI 26))]
4758 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4759 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4760 "@
4761 jsr $26,($27),0
4762 bsr $26,%0\t\t!samegp
4763 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#"
4764 [(set_attr "type" "jsr")
4765 (set_attr "length" "*,*,8")])
4767 (define_insn "*call_osf_1_er"
4768 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4769 (match_operand 1 "" ""))
4770 (use (reg:DI 29))
4771 (clobber (reg:DI 26))]
4772 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4773 "@
4774 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4775 bsr $26,%0\t\t!samegp
4776 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4777 [(set_attr "type" "jsr")
4778 (set_attr "length" "12,*,16")])
4780 ;; We must use peep2 instead of a split because we need accurate life
4781 ;; information for $gp. Consider the case of { bar(); while (1); }.
4782 (define_peephole2
4783 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4784 (match_operand 1 "" ""))
4785 (use (reg:DI 29))
4786 (clobber (reg:DI 26))])]
4787 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4788 && ! samegp_function_operand (operands[0], Pmode)
4789 && (peep2_regno_dead_p (1, 29)
4790 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4791 [(parallel [(call (mem:DI (match_dup 2))
4792 (match_dup 1))
4793 (use (reg:DI 29))
4794 (use (match_dup 0))
4795 (use (match_dup 3))
4796 (clobber (reg:DI 26))])]
4797 {
4798 if (CONSTANT_P (operands[0]))
4799 {
4800 operands[2] = gen_rtx_REG (Pmode, 27);
4801 operands[3] = GEN_INT (alpha_next_sequence_number++);
4802 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4803 operands[0], operands[3]));
4804 }
4805 else
4806 {
4807 operands[2] = operands[0];
4808 operands[0] = const0_rtx;
4809 operands[3] = const0_rtx;
4810 }
4811 })
4813 (define_peephole2
4814 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4815 (match_operand 1 "" ""))
4816 (use (reg:DI 29))
4817 (clobber (reg:DI 26))])]
4818 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4819 && ! samegp_function_operand (operands[0], Pmode)
4820 && ! (peep2_regno_dead_p (1, 29)
4821 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4822 [(parallel [(call (mem:DI (match_dup 2))
4823 (match_dup 1))
4824 (set (match_dup 5)
4825 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP1))
4826 (use (match_dup 0))
4827 (use (match_dup 4))
4828 (clobber (reg:DI 26))])
4829 (set (match_dup 5)
4830 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP2))]
4831 {
4832 if (CONSTANT_P (operands[0]))
4833 {
4834 operands[2] = gen_rtx_REG (Pmode, 27);
4835 operands[4] = GEN_INT (alpha_next_sequence_number++);
4836 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4837 operands[0], operands[4]));
4838 }
4839 else
4840 {
4841 operands[2] = operands[0];
4842 operands[0] = const0_rtx;
4843 operands[4] = const0_rtx;
4844 }
4845 operands[3] = GEN_INT (alpha_next_sequence_number++);
4846 operands[5] = pic_offset_table_rtx;
4847 })
4849 (define_insn "*call_osf_2_er_nogp"
4850 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4851 (match_operand 1 "" ""))
4852 (use (reg:DI 29))
4853 (use (match_operand 2 "" ""))
4854 (use (match_operand 3 "const_int_operand" ""))
4855 (clobber (reg:DI 26))]
4856 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4857 "jsr $26,(%0),%2%J3"
4858 [(set_attr "type" "jsr")])
4860 (define_insn "*call_osf_2_er"
4861 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4862 (match_operand 1 "" ""))
4863 (set (reg:DI 29)
4864 (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand" "")]
4865 UNSPEC_LDGP1))
4866 (use (match_operand 2 "" ""))
4867 (use (match_operand 3 "const_int_operand" ""))
4868 (clobber (reg:DI 26))]
4869 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4870 "jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4"
4871 [(set_attr "type" "jsr")
4872 (set_attr "cannot_copy" "true")
4873 (set_attr "length" "8")])
4875 (define_insn "*call_osf_1_noreturn"
4876 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4877 (match_operand 1 "" ""))
4878 (use (reg:DI 29))
4879 (clobber (reg:DI 26))]
4880 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4881 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4882 "@
4883 jsr $26,($27),0
4884 bsr $26,$%0..ng
4885 jsr $26,%0"
4886 [(set_attr "type" "jsr")
4887 (set_attr "length" "*,*,8")])
4889 (define_insn "*call_osf_1"
4890 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4891 (match_operand 1 "" ""))
4892 (use (reg:DI 29))
4893 (clobber (reg:DI 26))]
4894 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4895 "@
4896 jsr $26,($27),0\;ldgp $29,0($26)
4897 bsr $26,$%0..ng
4898 jsr $26,%0\;ldgp $29,0($26)"
4899 [(set_attr "type" "jsr")
4900 (set_attr "length" "12,*,16")])
4902 (define_insn "*sibcall_osf_1_er"
4903 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4904 (match_operand 1 "" ""))
4905 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4906 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4907 "@
4908 br $31,%0\t\t!samegp
4909 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4910 [(set_attr "type" "jsr")
4911 (set_attr "length" "*,8")])
4913 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4914 ;; doesn't do what we want.
4915 (define_insn "*sibcall_osf_1"
4916 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4917 (match_operand 1 "" ""))
4918 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4919 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4920 "@
4921 br $31,$%0..ng
4922 lda $27,%0\;jmp $31,($27),%0"
4923 [(set_attr "type" "jsr")
4924 (set_attr "length" "*,8")])
4926 (define_insn "*call_nt_1"
4927 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4928 (match_operand 1 "" ""))
4929 (clobber (reg:DI 26))]
4930 "TARGET_ABI_WINDOWS_NT"
4931 "@
4932 jsr $26,(%0)
4933 bsr $26,%0
4934 jsr $26,%0"
4935 [(set_attr "type" "jsr")
4936 (set_attr "length" "*,*,12")])
4938 ; GAS relies on the order and position of instructions output below in order
4939 ; to generate relocs for VMS link to potentially optimize the call.
4940 ; Please do not molest.
4941 (define_insn "*call_vms_1"
4942 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4943 (match_operand 1 "" ""))
4944 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4945 (use (reg:DI 25))
4946 (use (reg:DI 26))
4947 (clobber (reg:DI 27))]
4948 "TARGET_ABI_OPEN_VMS"
4949 {
4950 switch (which_alternative)
4951 {
4952 case 0:
4953 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4954 case 1:
4955 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4956 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4957 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4958 default:
4959 gcc_unreachable ();
4960 }
4961 }
4962 [(set_attr "type" "jsr")
4963 (set_attr "length" "12,16")])
4965 (define_insn "*call_umk_1"
4966 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4967 (match_operand 1 "" ""))
4968 (use (reg:DI 25))
4969 (clobber (reg:DI 26))]
4970 "TARGET_ABI_UNICOSMK"
4971 "jsr $26,(%0)"
4972 [(set_attr "type" "jsr")])
4974 ;; Call subroutine returning any type.
4976 (define_expand "untyped_call"
4977 [(parallel [(call (match_operand 0 "" "")
4978 (const_int 0))
4979 (match_operand 1 "" "")
4980 (match_operand 2 "" "")])]
4981 ""
4982 {
4983 int i;
4985 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4987 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4988 {
4989 rtx set = XVECEXP (operands[2], 0, i);
4990 emit_move_insn (SET_DEST (set), SET_SRC (set));
4991 }
4993 /* The optimizer does not know that the call sets the function value
4994 registers we stored in the result block. We avoid problems by
4995 claiming that all hard registers are used and clobbered at this
4996 point. */
4997 emit_insn (gen_blockage ());
4999 DONE;
5000 })
5002 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5003 ;; all of memory. This blocks insns from being moved across this point.
5005 (define_insn "blockage"
5006 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
5007 ""
5008 ""
5009 [(set_attr "length" "0")
5010 (set_attr "type" "none")])
5012 (define_insn "jump"
5013 [(set (pc)
5014 (label_ref (match_operand 0 "" "")))]
5015 ""
5016 "br $31,%l0"
5017 [(set_attr "type" "ibr")])
5019 (define_expand "return"
5020 [(return)]
5021 "direct_return ()"
5022 "")
5024 (define_insn "*return_internal"
5025 [(return)]
5026 "reload_completed"
5027 "ret $31,($26),1"
5028 [(set_attr "type" "ibr")])
5030 (define_insn "indirect_jump"
5031 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
5032 ""
5033 "jmp $31,(%0),0"
5034 [(set_attr "type" "ibr")])
5036 (define_expand "tablejump"
5037 [(parallel [(set (pc)
5038 (match_operand 0 "register_operand" ""))
5039 (use (label_ref:DI (match_operand 1 "" "")))])]
5040 ""
5041 {
5042 if (TARGET_ABI_WINDOWS_NT)
5043 {
5044 rtx dest = gen_reg_rtx (DImode);
5045 emit_insn (gen_extendsidi2 (dest, operands[0]));
5046 operands[0] = dest;
5047 }
5048 else if (TARGET_ABI_OSF)
5049 {
5050 rtx dest = gen_reg_rtx (DImode);
5051 emit_insn (gen_extendsidi2 (dest, operands[0]));
5052 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
5053 operands[0] = dest;
5054 }
5055 })
5057 (define_insn "*tablejump_osf_nt_internal"
5058 [(set (pc)
5059 (match_operand:DI 0 "register_operand" "r"))
5060 (use (label_ref:DI (match_operand 1 "" "")))]
5061 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
5062 && alpha_tablejump_addr_vec (insn)"
5063 {
5064 operands[2] = alpha_tablejump_best_label (insn);
5065 return "jmp $31,(%0),%2";
5066 }
5067 [(set_attr "type" "ibr")])
5069 (define_insn "*tablejump_internal"
5070 [(set (pc)
5071 (match_operand:DI 0 "register_operand" "r"))
5072 (use (label_ref (match_operand 1 "" "")))]
5073 ""
5074 "jmp $31,(%0),0"
5075 [(set_attr "type" "ibr")])
5077 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
5078 ;; want to have to include pal.h in our .s file.
5079 (define_insn "imb"
5080 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5081 ""
5082 "call_pal 0x86"
5083 [(set_attr "type" "callpal")])
5085 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
5086 ;; NT does not document anything at 0x81 -- presumably it would generate
5087 ;; the equivalent of SIGILL, but this isn't that important.
5088 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
5089 (define_insn "trap"
5090 [(trap_if (const_int 1) (const_int 0))]
5091 "!TARGET_ABI_WINDOWS_NT"
5092 "call_pal 0x81"
5093 [(set_attr "type" "callpal")])
5095 ;; For userland, we load the thread pointer from the TCB.
5096 ;; For the kernel, we load the per-cpu private value.
5098 (define_insn "load_tp"
5099 [(set (match_operand:DI 0 "register_operand" "=v")
5100 (unspec:DI [(const_int 0)] UNSPEC_TP))]
5101 "TARGET_ABI_OSF"
5102 {
5103 if (TARGET_TLS_KERNEL)
5104 return "call_pal 0x32";
5105 else
5106 return "call_pal 0x9e";
5107 }
5108 [(set_attr "type" "callpal")])
5110 ;; For completeness, and possibly a __builtin function, here's how to
5111 ;; set the thread pointer. Since we don't describe enough of this
5112 ;; quantity for CSE, we have to use a volatile unspec, and then there's
5113 ;; not much point in creating an R16_REG register class.
5115 (define_expand "set_tp"
5116 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
5117 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5118 "TARGET_ABI_OSF"
5119 "")
5121 (define_insn "*set_tp"
5122 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5123 "TARGET_ABI_OSF"
5124 {
5125 if (TARGET_TLS_KERNEL)
5126 return "call_pal 0x31";
5127 else
5128 return "call_pal 0x9f";
5129 }
5130 [(set_attr "type" "callpal")])
5131 \f
5132 ;; Finally, we have the basic data motion insns. The byte and word insns
5133 ;; are done via define_expand. Start with the floating-point insns, since
5134 ;; they are simpler.
5136 (define_insn "*movsf_nofix"
5137 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5138 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5139 "TARGET_FPREGS && ! TARGET_FIX
5140 && (register_operand (operands[0], SFmode)
5141 || reg_or_0_operand (operands[1], SFmode))"
5142 "@
5143 cpys %R1,%R1,%0
5144 ld%, %0,%1
5145 bis $31,%r1,%0
5146 ldl %0,%1
5147 st%, %R1,%0
5148 stl %r1,%0"
5149 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5151 (define_insn "*movsf_fix"
5152 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5153 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5154 "TARGET_FPREGS && TARGET_FIX
5155 && (register_operand (operands[0], SFmode)
5156 || reg_or_0_operand (operands[1], SFmode))"
5157 "@
5158 cpys %R1,%R1,%0
5159 ld%, %0,%1
5160 bis $31,%r1,%0
5161 ldl %0,%1
5162 st%, %R1,%0
5163 stl %r1,%0
5164 itofs %1,%0
5165 ftois %1,%0"
5166 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5168 (define_insn "*movsf_nofp"
5169 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5170 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5171 "! TARGET_FPREGS
5172 && (register_operand (operands[0], SFmode)
5173 || reg_or_0_operand (operands[1], SFmode))"
5174 "@
5175 bis $31,%r1,%0
5176 ldl %0,%1
5177 stl %r1,%0"
5178 [(set_attr "type" "ilog,ild,ist")])
5180 (define_insn "*movdf_nofix"
5181 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5182 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5183 "TARGET_FPREGS && ! TARGET_FIX
5184 && (register_operand (operands[0], DFmode)
5185 || reg_or_0_operand (operands[1], DFmode))"
5186 "@
5187 cpys %R1,%R1,%0
5188 ld%- %0,%1
5189 bis $31,%r1,%0
5190 ldq %0,%1
5191 st%- %R1,%0
5192 stq %r1,%0"
5193 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5195 (define_insn "*movdf_fix"
5196 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5197 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5198 "TARGET_FPREGS && TARGET_FIX
5199 && (register_operand (operands[0], DFmode)
5200 || reg_or_0_operand (operands[1], DFmode))"
5201 "@
5202 cpys %R1,%R1,%0
5203 ld%- %0,%1
5204 bis $31,%r1,%0
5205 ldq %0,%1
5206 st%- %R1,%0
5207 stq %r1,%0
5208 itoft %1,%0
5209 ftoit %1,%0"
5210 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5212 (define_insn "*movdf_nofp"
5213 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5214 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5215 "! TARGET_FPREGS
5216 && (register_operand (operands[0], DFmode)
5217 || reg_or_0_operand (operands[1], DFmode))"
5218 "@
5219 bis $31,%r1,%0
5220 ldq %0,%1
5221 stq %r1,%0"
5222 [(set_attr "type" "ilog,ild,ist")])
5224 ;; Subregs suck for register allocation. Pretend we can move TFmode
5225 ;; data between general registers until after reload.
5227 (define_insn_and_split "*movtf_internal"
5228 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5229 (match_operand:TF 1 "input_operand" "roG,rG"))]
5230 "register_operand (operands[0], TFmode)
5231 || reg_or_0_operand (operands[1], TFmode)"
5232 "#"
5233 "reload_completed"
5234 [(set (match_dup 0) (match_dup 2))
5235 (set (match_dup 1) (match_dup 3))]
5236 {
5237 alpha_split_tmode_pair (operands, TFmode, true);
5238 })
5240 (define_expand "movsf"
5241 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5242 (match_operand:SF 1 "general_operand" ""))]
5243 ""
5244 {
5245 if (GET_CODE (operands[0]) == MEM
5246 && ! reg_or_0_operand (operands[1], SFmode))
5247 operands[1] = force_reg (SFmode, operands[1]);
5248 })
5250 (define_expand "movdf"
5251 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5252 (match_operand:DF 1 "general_operand" ""))]
5253 ""
5254 {
5255 if (GET_CODE (operands[0]) == MEM
5256 && ! reg_or_0_operand (operands[1], DFmode))
5257 operands[1] = force_reg (DFmode, operands[1]);
5258 })
5260 (define_expand "movtf"
5261 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5262 (match_operand:TF 1 "general_operand" ""))]
5263 ""
5264 {
5265 if (GET_CODE (operands[0]) == MEM
5266 && ! reg_or_0_operand (operands[1], TFmode))
5267 operands[1] = force_reg (TFmode, operands[1]);
5268 })
5270 (define_insn "*movsi"
5271 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
5272 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ"))]
5273 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK)
5274 && (register_operand (operands[0], SImode)
5275 || reg_or_0_operand (operands[1], SImode))"
5276 "@
5277 bis $31,%r1,%0
5278 lda %0,%1($31)
5279 ldah %0,%h1($31)
5280 #
5281 ldl %0,%1
5282 stl %r1,%0"
5283 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist")])
5285 (define_insn "*movsi_nt_vms"
5286 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m")
5287 (match_operand:SI 1 "input_operand" "rJ,K,L,s,n,m,rJ"))]
5288 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5289 && (register_operand (operands[0], SImode)
5290 || reg_or_0_operand (operands[1], SImode))"
5291 "@
5292 bis $31,%1,%0
5293 lda %0,%1
5294 ldah %0,%h1
5295 lda %0,%1
5296 #
5297 ldl %0,%1
5298 stl %r1,%0"
5299 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist")])
5301 (define_insn "*movhi_nobwx"
5302 [(set (match_operand:HI 0 "register_operand" "=r,r")
5303 (match_operand:HI 1 "input_operand" "rJ,n"))]
5304 "! TARGET_BWX
5305 && (register_operand (operands[0], HImode)
5306 || register_operand (operands[1], HImode))"
5307 "@
5308 bis $31,%r1,%0
5309 lda %0,%L1($31)"
5310 [(set_attr "type" "ilog,iadd")])
5312 (define_insn "*movhi_bwx"
5313 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5314 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5315 "TARGET_BWX
5316 && (register_operand (operands[0], HImode)
5317 || reg_or_0_operand (operands[1], HImode))"
5318 "@
5319 bis $31,%r1,%0
5320 lda %0,%L1($31)
5321 ldwu %0,%1
5322 stw %r1,%0"
5323 [(set_attr "type" "ilog,iadd,ild,ist")])
5325 (define_insn "*movqi_nobwx"
5326 [(set (match_operand:QI 0 "register_operand" "=r,r")
5327 (match_operand:QI 1 "input_operand" "rJ,n"))]
5328 "! TARGET_BWX
5329 && (register_operand (operands[0], QImode)
5330 || register_operand (operands[1], QImode))"
5331 "@
5332 bis $31,%r1,%0
5333 lda %0,%L1($31)"
5334 [(set_attr "type" "ilog,iadd")])
5336 (define_insn "*movqi_bwx"
5337 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5338 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5339 "TARGET_BWX
5340 && (register_operand (operands[0], QImode)
5341 || reg_or_0_operand (operands[1], QImode))"
5342 "@
5343 bis $31,%r1,%0
5344 lda %0,%L1($31)
5345 ldbu %0,%1
5346 stb %r1,%0"
5347 [(set_attr "type" "ilog,iadd,ild,ist")])
5349 ;; We do two major things here: handle mem->mem and construct long
5350 ;; constants.
5352 (define_expand "movsi"
5353 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5354 (match_operand:SI 1 "general_operand" ""))]
5355 ""
5356 {
5357 if (alpha_expand_mov (SImode, operands))
5358 DONE;
5359 })
5361 ;; Split a load of a large constant into the appropriate two-insn
5362 ;; sequence.
5364 (define_split
5365 [(set (match_operand:SI 0 "register_operand" "")
5366 (match_operand:SI 1 "non_add_const_operand" ""))]
5367 ""
5368 [(const_int 0)]
5369 {
5370 if (alpha_split_const_mov (SImode, operands))
5371 DONE;
5372 else
5373 FAIL;
5374 })
5376 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5377 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5378 ;; optimizations. If the symbolic operand is a label_ref, generate
5379 ;; REG_LABEL_OPERAND notes and update LABEL_NUSES because this is not done
5380 ;; automatically. Labels may be incorrectly deleted if we don't do this.
5381 ;;
5382 ;; Describing what the individual instructions do correctly is too complicated
5383 ;; so use UNSPECs for each of the three parts of an address.
5385 (define_split
5386 [(set (match_operand:DI 0 "register_operand" "")
5387 (match_operand:DI 1 "symbolic_operand" ""))]
5388 "TARGET_ABI_UNICOSMK && reload_completed"
5389 [(const_int 0)]
5390 {
5391 rtx insn1, insn2, insn3;
5393 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5394 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5395 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5396 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5397 set_unique_reg_note (insn3, REG_EQUAL, operands[1]);
5399 if (GET_CODE (operands[1]) == LABEL_REF)
5400 {
5401 rtx label;
5403 label = XEXP (operands[1], 0);
5404 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL_OPERAND, label,
5405 REG_NOTES (insn1));
5406 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL_OPERAND, label,
5407 REG_NOTES (insn2));
5408 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL_OPERAND, label,
5409 REG_NOTES (insn3));
5410 LABEL_NUSES (label) += 3;
5411 }
5412 DONE;
5413 })
5415 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5417 (define_insn "umk_laum"
5418 [(set (match_operand:DI 0 "register_operand" "=r")
5419 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5420 UNSPEC_UMK_LAUM))]
5421 "TARGET_ABI_UNICOSMK"
5422 "laum %r0,%t1($31)"
5423 [(set_attr "type" "iadd")])
5425 (define_insn "umk_lalm"
5426 [(set (match_operand:DI 0 "register_operand" "=r")
5427 (plus:DI (match_operand:DI 1 "register_operand" "r")
5428 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5429 UNSPEC_UMK_LALM)))]
5430 "TARGET_ABI_UNICOSMK"
5431 "lalm %r0,%t2(%r1)"
5432 [(set_attr "type" "iadd")])
5434 (define_insn "umk_lal"
5435 [(set (match_operand:DI 0 "register_operand" "=r")
5436 (plus:DI (match_operand:DI 1 "register_operand" "r")
5437 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5438 UNSPEC_UMK_LAL)))]
5439 "TARGET_ABI_UNICOSMK"
5440 "lal %r0,%t2(%r1)"
5441 [(set_attr "type" "iadd")])
5443 ;; Add a new call information word to the current function's list of CIWs
5444 ;; and load its index into $25. Doing it here ensures that the CIW will be
5445 ;; associated with the correct function even in the presence of inlining.
5447 (define_insn "*umk_load_ciw"
5448 [(set (reg:DI 25)
5449 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5450 "TARGET_ABI_UNICOSMK"
5451 {
5452 operands[0] = unicosmk_add_call_info_word (operands[0]);
5453 return "lda $25,%0";
5454 }
5455 [(set_attr "type" "iadd")])
5457 (define_insn "*movdi_er_low_l"
5458 [(set (match_operand:DI 0 "register_operand" "=r")
5459 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5460 (match_operand:DI 2 "local_symbolic_operand" "")))]
5461 "TARGET_EXPLICIT_RELOCS"
5462 {
5463 if (true_regnum (operands[1]) == 29)
5464 return "lda %0,%2(%1)\t\t!gprel";
5465 else
5466 return "lda %0,%2(%1)\t\t!gprellow";
5467 }
5468 [(set_attr "usegp" "yes")])
5470 (define_split
5471 [(set (match_operand:DI 0 "register_operand" "")
5472 (match_operand:DI 1 "small_symbolic_operand" ""))]
5473 "TARGET_EXPLICIT_RELOCS && reload_completed"
5474 [(set (match_dup 0)
5475 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5476 "operands[2] = pic_offset_table_rtx;")
5478 (define_split
5479 [(set (match_operand:DI 0 "register_operand" "")
5480 (match_operand:DI 1 "local_symbolic_operand" ""))]
5481 "TARGET_EXPLICIT_RELOCS && reload_completed"
5482 [(set (match_dup 0)
5483 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5484 (set (match_dup 0)
5485 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5486 "operands[2] = pic_offset_table_rtx;")
5488 (define_split
5489 [(match_operand 0 "some_small_symbolic_operand" "")]
5490 ""
5491 [(match_dup 0)]
5492 "operands[0] = split_small_symbolic_operand (operands[0]);")
5494 ;; Accepts any symbolic, not just global, since function calls that
5495 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5496 (define_insn "movdi_er_high_g"
5497 [(set (match_operand:DI 0 "register_operand" "=r")
5498 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5499 (match_operand:DI 2 "symbolic_operand" "")
5500 (match_operand 3 "const_int_operand" "")]
5501 UNSPEC_LITERAL))]
5502 "TARGET_EXPLICIT_RELOCS"
5503 {
5504 if (INTVAL (operands[3]) == 0)
5505 return "ldq %0,%2(%1)\t\t!literal";
5506 else
5507 return "ldq %0,%2(%1)\t\t!literal!%3";
5508 }
5509 [(set_attr "type" "ldsym")])
5511 (define_split
5512 [(set (match_operand:DI 0 "register_operand" "")
5513 (match_operand:DI 1 "global_symbolic_operand" ""))]
5514 "TARGET_EXPLICIT_RELOCS && reload_completed"
5515 [(set (match_dup 0)
5516 (unspec:DI [(match_dup 2)
5517 (match_dup 1)
5518 (const_int 0)] UNSPEC_LITERAL))]
5519 "operands[2] = pic_offset_table_rtx;")
5521 (define_insn "movdi_er_tlsgd"
5522 [(set (match_operand:DI 0 "register_operand" "=r")
5523 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5524 (match_operand:DI 2 "symbolic_operand" "")
5525 (match_operand 3 "const_int_operand" "")]
5526 UNSPEC_TLSGD))]
5527 "HAVE_AS_TLS"
5528 {
5529 if (INTVAL (operands[3]) == 0)
5530 return "lda %0,%2(%1)\t\t!tlsgd";
5531 else
5532 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5533 })
5535 (define_insn "movdi_er_tlsldm"
5536 [(set (match_operand:DI 0 "register_operand" "=r")
5537 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5538 (match_operand 2 "const_int_operand" "")]
5539 UNSPEC_TLSLDM))]
5540 "HAVE_AS_TLS"
5541 {
5542 if (INTVAL (operands[2]) == 0)
5543 return "lda %0,%&(%1)\t\t!tlsldm";
5544 else
5545 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5546 })
5548 (define_insn "*movdi_er_gotdtp"
5549 [(set (match_operand:DI 0 "register_operand" "=r")
5550 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5551 (match_operand:DI 2 "symbolic_operand" "")]
5552 UNSPEC_DTPREL))]
5553 "HAVE_AS_TLS"
5554 "ldq %0,%2(%1)\t\t!gotdtprel"
5555 [(set_attr "type" "ild")
5556 (set_attr "usegp" "yes")])
5558 (define_split
5559 [(set (match_operand:DI 0 "register_operand" "")
5560 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5561 "HAVE_AS_TLS && reload_completed"
5562 [(set (match_dup 0)
5563 (unspec:DI [(match_dup 2)
5564 (match_dup 1)] UNSPEC_DTPREL))]
5565 {
5566 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5567 operands[2] = pic_offset_table_rtx;
5568 })
5570 (define_insn "*movdi_er_gottp"
5571 [(set (match_operand:DI 0 "register_operand" "=r")
5572 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5573 (match_operand:DI 2 "symbolic_operand" "")]
5574 UNSPEC_TPREL))]
5575 "HAVE_AS_TLS"
5576 "ldq %0,%2(%1)\t\t!gottprel"
5577 [(set_attr "type" "ild")
5578 (set_attr "usegp" "yes")])
5580 (define_split
5581 [(set (match_operand:DI 0 "register_operand" "")
5582 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5583 "HAVE_AS_TLS && reload_completed"
5584 [(set (match_dup 0)
5585 (unspec:DI [(match_dup 2)
5586 (match_dup 1)] UNSPEC_TPREL))]
5587 {
5588 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5589 operands[2] = pic_offset_table_rtx;
5590 })
5592 (define_insn "*movdi_er_nofix"
5593 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5594 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,n,m,rJ,*fJ,Q,*f"))]
5595 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5596 && (register_operand (operands[0], DImode)
5597 || reg_or_0_operand (operands[1], DImode))"
5598 "@
5599 mov %r1,%0
5600 lda %0,%1($31)
5601 ldah %0,%h1($31)
5602 #
5603 #
5604 #
5605 ldq%A1 %0,%1
5606 stq%A0 %r1,%0
5607 fmov %R1,%0
5608 ldt %0,%1
5609 stt %R1,%0"
5610 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst")
5611 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*")])
5613 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5614 ;; have been split up by the rules above but we shouldn't reject the
5615 ;; possibility of them getting through.
5617 (define_insn "*movdi_nofix"
5618 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5619 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,n,m,rJ,*fJ,Q,*f"))]
5620 "! TARGET_FIX
5621 && (register_operand (operands[0], DImode)
5622 || reg_or_0_operand (operands[1], DImode))"
5623 "@
5624 bis $31,%r1,%0
5625 lda %0,%1($31)
5626 ldah %0,%h1($31)
5627 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5628 lda %0,%1
5629 #
5630 ldq%A1 %0,%1
5631 stq%A0 %r1,%0
5632 cpys %R1,%R1,%0
5633 ldt %0,%1
5634 stt %R1,%0"
5635 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,multi,ild,ist,fcpys,fld,fst")
5636 (set_attr "length" "*,*,*,16,*,*,*,*,*,*,*")])
5638 (define_insn "*movdi_er_fix"
5639 [(set (match_operand:DI 0 "nonimmediate_operand"
5640 "=r,r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5641 (match_operand:DI 1 "input_operand"
5642 "rJ,K,L,T,s,n,m,rJ,*fJ, Q,*f,*f, r"))]
5643 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5644 && (register_operand (operands[0], DImode)
5645 || reg_or_0_operand (operands[1], DImode))"
5646 "@
5647 mov %r1,%0
5648 lda %0,%1($31)
5649 ldah %0,%h1($31)
5650 #
5651 #
5652 #
5653 ldq%A1 %0,%1
5654 stq%A0 %r1,%0
5655 fmov %R1,%0
5656 ldt %0,%1
5657 stt %R1,%0
5658 ftoit %1,%0
5659 itoft %1,%0"
5660 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
5661 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*")])
5663 (define_insn "*movdi_fix"
5664 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q,r,*f")
5665 (match_operand:DI 1 "input_operand" "rJ,K,L,s,n,m,rJ,*fJ,Q,*f,*f,r"))]
5666 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5667 && (register_operand (operands[0], DImode)
5668 || reg_or_0_operand (operands[1], DImode))"
5669 "@
5670 bis $31,%r1,%0
5671 lda %0,%1($31)
5672 ldah %0,%h1($31)
5673 lda %0,%1
5674 #
5675 ldq%A1 %0,%1
5676 stq%A0 %r1,%0
5677 cpys %R1,%R1,%0
5678 ldt %0,%1
5679 stt %R1,%0
5680 ftoit %1,%0
5681 itoft %1,%0"
5682 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
5684 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5685 ;; often appears dead to the life analysis code, at which point we
5686 ;; die for emitting dead prologue instructions. Force this live.
5688 (define_insn "force_movdi"
5689 [(set (match_operand:DI 0 "register_operand" "=r")
5690 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5691 UNSPECV_FORCE_MOV))]
5692 ""
5693 "mov %1,%0"
5694 [(set_attr "type" "ilog")])
5696 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5697 ;; memory, and construct long 32-bit constants.
5699 (define_expand "movdi"
5700 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5701 (match_operand:DI 1 "general_operand" ""))]
5702 ""
5703 {
5704 if (alpha_expand_mov (DImode, operands))
5705 DONE;
5706 })
5708 ;; Split a load of a large constant into the appropriate two-insn
5709 ;; sequence.
5711 (define_split
5712 [(set (match_operand:DI 0 "register_operand" "")
5713 (match_operand:DI 1 "non_add_const_operand" ""))]
5714 ""
5715 [(const_int 0)]
5716 {
5717 if (alpha_split_const_mov (DImode, operands))
5718 DONE;
5719 else
5720 FAIL;
5721 })
5723 ;; We need to prevent reload from splitting TImode moves, because it
5724 ;; might decide to overwrite a pointer with the value it points to.
5725 ;; In that case we have to do the loads in the appropriate order so
5726 ;; that the pointer is not destroyed too early.
5728 (define_insn_and_split "*movti_internal"
5729 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
5730 (match_operand:TI 1 "input_operand" "roJ,rJ"))]
5731 "(register_operand (operands[0], TImode)
5732 /* Prevent rematerialization of constants. */
5733 && ! CONSTANT_P (operands[1]))
5734 || reg_or_0_operand (operands[1], TImode)"
5735 "#"
5736 "reload_completed"
5737 [(set (match_dup 0) (match_dup 2))
5738 (set (match_dup 1) (match_dup 3))]
5739 {
5740 alpha_split_tmode_pair (operands, TImode, true);
5741 })
5743 (define_expand "movti"
5744 [(set (match_operand:TI 0 "nonimmediate_operand" "")
5745 (match_operand:TI 1 "general_operand" ""))]
5746 ""
5747 {
5748 if (GET_CODE (operands[0]) == MEM
5749 && ! reg_or_0_operand (operands[1], TImode))
5750 operands[1] = force_reg (TImode, operands[1]);
5752 if (operands[1] == const0_rtx)
5753 ;
5754 /* We must put 64-bit constants in memory. We could keep the
5755 32-bit constants in TImode and rely on the splitter, but
5756 this doesn't seem to be worth the pain. */
5757 else if (GET_CODE (operands[1]) == CONST_INT
5758 || GET_CODE (operands[1]) == CONST_DOUBLE)
5759 {
5760 rtx in[2], out[2], target;
5762 gcc_assert (can_create_pseudo_p ());
5764 split_double (operands[1], &in[0], &in[1]);
5766 if (in[0] == const0_rtx)
5767 out[0] = const0_rtx;
5768 else
5769 {
5770 out[0] = gen_reg_rtx (DImode);
5771 emit_insn (gen_movdi (out[0], in[0]));
5772 }
5774 if (in[1] == const0_rtx)
5775 out[1] = const0_rtx;
5776 else
5777 {
5778 out[1] = gen_reg_rtx (DImode);
5779 emit_insn (gen_movdi (out[1], in[1]));
5780 }
5782 if (GET_CODE (operands[0]) != REG)
5783 target = gen_reg_rtx (TImode);
5784 else
5785 target = operands[0];
5787 emit_insn (gen_movdi (operand_subword (target, 0, 0, TImode), out[0]));
5788 emit_insn (gen_movdi (operand_subword (target, 1, 0, TImode), out[1]));
5790 if (target != operands[0])
5791 emit_insn (gen_rtx_SET (VOIDmode, operands[0], target));
5793 DONE;
5794 }
5795 })
5797 ;; These are the partial-word cases.
5798 ;;
5799 ;; First we have the code to load an aligned word. Operand 0 is the register
5800 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5801 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5802 ;; number of bits within the word that the value is. Operand 3 is an SImode
5803 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5804 ;; same register. It is allowed to conflict with operand 1 as well.
5806 (define_expand "aligned_loadqi"
5807 [(set (match_operand:SI 3 "register_operand" "")
5808 (match_operand:SI 1 "memory_operand" ""))
5809 (set (match_operand:DI 0 "register_operand" "")
5810 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5811 (const_int 8)
5812 (match_operand:DI 2 "const_int_operand" "")))]
5814 ""
5815 "")
5817 (define_expand "aligned_loadhi"
5818 [(set (match_operand:SI 3 "register_operand" "")
5819 (match_operand:SI 1 "memory_operand" ""))
5820 (set (match_operand:DI 0 "register_operand" "")
5821 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5822 (const_int 16)
5823 (match_operand:DI 2 "const_int_operand" "")))]
5825 ""
5826 "")
5828 ;; Similar for unaligned loads, where we use the sequence from the
5829 ;; Alpha Architecture manual. We have to distinguish between little-endian
5830 ;; and big-endian systems as the sequences are different.
5831 ;;
5832 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5833 ;; operand 3 can overlap the input and output registers.
5835 (define_expand "unaligned_loadqi"
5836 [(use (match_operand:DI 0 "register_operand" ""))
5837 (use (match_operand:DI 1 "address_operand" ""))
5838 (use (match_operand:DI 2 "register_operand" ""))
5839 (use (match_operand:DI 3 "register_operand" ""))]
5840 ""
5841 {
5842 if (WORDS_BIG_ENDIAN)
5843 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5844 operands[2], operands[3]));
5845 else
5846 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5847 operands[2], operands[3]));
5848 DONE;
5849 })
5851 (define_expand "unaligned_loadqi_le"
5852 [(set (match_operand:DI 2 "register_operand" "")
5853 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5854 (const_int -8))))
5855 (set (match_operand:DI 3 "register_operand" "")
5856 (match_dup 1))
5857 (set (match_operand:DI 0 "register_operand" "")
5858 (zero_extract:DI (match_dup 2)
5859 (const_int 8)
5860 (ashift:DI (match_dup 3) (const_int 3))))]
5861 "! WORDS_BIG_ENDIAN"
5862 "")
5864 (define_expand "unaligned_loadqi_be"
5865 [(set (match_operand:DI 2 "register_operand" "")
5866 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5867 (const_int -8))))
5868 (set (match_operand:DI 3 "register_operand" "")
5869 (match_dup 1))
5870 (set (match_operand:DI 0 "register_operand" "")
5871 (zero_extract:DI (match_dup 2)
5872 (const_int 8)
5873 (minus:DI
5874 (const_int 56)
5875 (ashift:DI (match_dup 3) (const_int 3)))))]
5876 "WORDS_BIG_ENDIAN"
5877 "")
5879 (define_expand "unaligned_loadhi"
5880 [(use (match_operand:DI 0 "register_operand" ""))
5881 (use (match_operand:DI 1 "address_operand" ""))
5882 (use (match_operand:DI 2 "register_operand" ""))
5883 (use (match_operand:DI 3 "register_operand" ""))]
5884 ""
5885 {
5886 if (WORDS_BIG_ENDIAN)
5887 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5888 operands[2], operands[3]));
5889 else
5890 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5891 operands[2], operands[3]));
5892 DONE;
5893 })
5895 (define_expand "unaligned_loadhi_le"
5896 [(set (match_operand:DI 2 "register_operand" "")
5897 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5898 (const_int -8))))
5899 (set (match_operand:DI 3 "register_operand" "")
5900 (match_dup 1))
5901 (set (match_operand:DI 0 "register_operand" "")
5902 (zero_extract:DI (match_dup 2)
5903 (const_int 16)
5904 (ashift:DI (match_dup 3) (const_int 3))))]
5905 "! WORDS_BIG_ENDIAN"
5906 "")
5908 (define_expand "unaligned_loadhi_be"
5909 [(set (match_operand:DI 2 "register_operand" "")
5910 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5911 (const_int -8))))
5912 (set (match_operand:DI 3 "register_operand" "")
5913 (plus:DI (match_dup 1) (const_int 1)))
5914 (set (match_operand:DI 0 "register_operand" "")
5915 (zero_extract:DI (match_dup 2)
5916 (const_int 16)
5917 (minus:DI
5918 (const_int 56)
5919 (ashift:DI (match_dup 3) (const_int 3)))))]
5920 "WORDS_BIG_ENDIAN"
5921 "")
5923 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5924 ;; aligned SImode MEM. Operand 1 is the register containing the
5925 ;; byte or word to store. Operand 2 is the number of bits within the word that
5926 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5928 (define_expand "aligned_store"
5929 [(set (match_operand:SI 3 "register_operand" "")
5930 (match_operand:SI 0 "memory_operand" ""))
5931 (set (subreg:DI (match_dup 3) 0)
5932 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5933 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5934 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5935 (match_operand:DI 2 "const_int_operand" "")))
5936 (set (subreg:DI (match_dup 4) 0)
5937 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5938 (set (match_dup 0) (match_dup 4))]
5939 ""
5940 {
5941 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5942 << INTVAL (operands[2])));
5943 })
5945 ;; For the unaligned byte and halfword cases, we use code similar to that
5946 ;; in the ;; Architecture book, but reordered to lower the number of registers
5947 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5948 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5949 ;; be the same temporary, if desired. If the address is in a register,
5950 ;; operand 2 can be that register.
5952 (define_expand "unaligned_storeqi"
5953 [(use (match_operand:DI 0 "address_operand" ""))
5954 (use (match_operand:QI 1 "register_operand" ""))
5955 (use (match_operand:DI 2 "register_operand" ""))
5956 (use (match_operand:DI 3 "register_operand" ""))
5957 (use (match_operand:DI 4 "register_operand" ""))]
5958 ""
5959 {
5960 if (WORDS_BIG_ENDIAN)
5961 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5962 operands[2], operands[3],
5963 operands[4]));
5964 else
5965 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5966 operands[2], operands[3],
5967 operands[4]));
5968 DONE;
5969 })
5971 (define_expand "unaligned_storeqi_le"
5972 [(set (match_operand:DI 3 "register_operand" "")
5973 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5974 (const_int -8))))
5975 (set (match_operand:DI 2 "register_operand" "")
5976 (match_dup 0))
5977 (set (match_dup 3)
5978 (and:DI (not:DI (ashift:DI (const_int 255)
5979 (ashift:DI (match_dup 2) (const_int 3))))
5980 (match_dup 3)))
5981 (set (match_operand:DI 4 "register_operand" "")
5982 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5983 (ashift:DI (match_dup 2) (const_int 3))))
5984 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5985 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5986 (match_dup 4))]
5987 "! WORDS_BIG_ENDIAN"
5988 "")
5990 (define_expand "unaligned_storeqi_be"
5991 [(set (match_operand:DI 3 "register_operand" "")
5992 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5993 (const_int -8))))
5994 (set (match_operand:DI 2 "register_operand" "")
5995 (match_dup 0))
5996 (set (match_dup 3)
5997 (and:DI (not:DI (ashift:DI (const_int 255)
5998 (minus:DI (const_int 56)
5999 (ashift:DI (match_dup 2) (const_int 3)))))
6000 (match_dup 3)))
6001 (set (match_operand:DI 4 "register_operand" "")
6002 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
6003 (minus:DI (const_int 56)
6004 (ashift:DI (match_dup 2) (const_int 3)))))
6005 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
6006 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
6007 (match_dup 4))]
6008 "WORDS_BIG_ENDIAN"
6009 "")
6011 (define_expand "unaligned_storehi"
6012 [(use (match_operand:DI 0 "address_operand" ""))
6013 (use (match_operand:HI 1 "register_operand" ""))
6014 (use (match_operand:DI 2 "register_operand" ""))
6015 (use (match_operand:DI 3 "register_operand" ""))
6016 (use (match_operand:DI 4 "register_operand" ""))]
6017 ""
6018 {
6019 if (WORDS_BIG_ENDIAN)
6020 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
6021 operands[2], operands[3],
6022 operands[4]));
6023 else
6024 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
6025 operands[2], operands[3],
6026 operands[4]));
6027 DONE;
6028 })
6030 (define_expand "unaligned_storehi_le"
6031 [(set (match_operand:DI 3 "register_operand" "")
6032 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
6033 (const_int -8))))
6034 (set (match_operand:DI 2 "register_operand" "")
6035 (match_dup 0))
6036 (set (match_dup 3)
6037 (and:DI (not:DI (ashift:DI (const_int 65535)
6038 (ashift:DI (match_dup 2) (const_int 3))))
6039 (match_dup 3)))
6040 (set (match_operand:DI 4 "register_operand" "")
6041 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
6042 (ashift:DI (match_dup 2) (const_int 3))))
6043 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
6044 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
6045 (match_dup 4))]
6046 "! WORDS_BIG_ENDIAN"
6047 "")
6049 (define_expand "unaligned_storehi_be"
6050 [(set (match_operand:DI 3 "register_operand" "")
6051 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
6052 (const_int -8))))
6053 (set (match_operand:DI 2 "register_operand" "")
6054 (plus:DI (match_dup 0) (const_int 1)))
6055 (set (match_dup 3)
6056 (and:DI (not:DI (ashift:DI
6057 (const_int 65535)
6058 (minus:DI (const_int 56)
6059 (ashift:DI (match_dup 2) (const_int 3)))))
6060 (match_dup 3)))
6061 (set (match_operand:DI 4 "register_operand" "")
6062 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
6063 (minus:DI (const_int 56)
6064 (ashift:DI (match_dup 2) (const_int 3)))))
6065 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
6066 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
6067 (match_dup 4))]
6068 "WORDS_BIG_ENDIAN"
6069 "")
6070 \f
6071 ;; Here are the define_expand's for QI and HI moves that use the above
6072 ;; patterns. We have the normal sets, plus the ones that need scratch
6073 ;; registers for reload.
6075 (define_expand "movqi"
6076 [(set (match_operand:QI 0 "nonimmediate_operand" "")
6077 (match_operand:QI 1 "general_operand" ""))]
6078 ""
6079 {
6080 if (TARGET_BWX
6081 ? alpha_expand_mov (QImode, operands)
6082 : alpha_expand_mov_nobwx (QImode, operands))
6083 DONE;
6084 })
6086 (define_expand "movhi"
6087 [(set (match_operand:HI 0 "nonimmediate_operand" "")
6088 (match_operand:HI 1 "general_operand" ""))]
6089 ""
6090 {
6091 if (TARGET_BWX
6092 ? alpha_expand_mov (HImode, operands)
6093 : alpha_expand_mov_nobwx (HImode, operands))
6094 DONE;
6095 })
6097 ;; We need to hook into the extra support that we have for HImode
6098 ;; reloads when BWX insns are not available.
6099 (define_expand "movcqi"
6100 [(set (match_operand:CQI 0 "nonimmediate_operand" "")
6101 (match_operand:CQI 1 "general_operand" ""))]
6102 "!TARGET_BWX"
6103 {
6104 if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT)
6105 ;
6106 else if (!any_memory_operand (operands[0], CQImode))
6107 {
6108 if (!any_memory_operand (operands[1], CQImode))
6109 {
6110 emit_move_insn (gen_lowpart (HImode, operands[0]),
6111 gen_lowpart (HImode, operands[1]));
6112 DONE;
6113 }
6114 if (aligned_memory_operand (operands[1], CQImode))
6115 {
6116 bool done;
6117 do_aligned1:
6118 operands[1] = gen_lowpart (HImode, operands[1]);
6119 do_aligned2:
6120 operands[0] = gen_lowpart (HImode, operands[0]);
6121 done = alpha_expand_mov_nobwx (HImode, operands);
6122 gcc_assert (done);
6123 DONE;
6124 }
6125 }
6126 else if (aligned_memory_operand (operands[0], CQImode))
6127 {
6128 if (MEM_P (operands[1]))
6129 {
6130 rtx x = gen_reg_rtx (HImode);
6131 emit_move_insn (gen_lowpart (CQImode, x), operands[1]);
6132 operands[1] = x;
6133 goto do_aligned2;
6134 }
6135 goto do_aligned1;
6136 }
6138 gcc_assert (!reload_in_progress);
6139 emit_move_complex_parts (operands[0], operands[1]);
6140 DONE;
6141 })
6143 ;; Here are the versions for reload.
6144 ;;
6145 ;; The aligned input case is recognized early in alpha_secondary_reload
6146 ;; in order to avoid allocating an unnecessary scratch register.
6147 ;;
6148 ;; Note that in the unaligned cases we know that the operand must not be
6149 ;; a pseudo-register because stack slots are always aligned references.
6151 (define_expand "reload_in<mode>"
6152 [(parallel [(match_operand:RELOAD12 0 "register_operand" "=r")
6153 (match_operand:RELOAD12 1 "any_memory_operand" "m")
6154 (match_operand:TI 2 "register_operand" "=&r")])]
6155 "!TARGET_BWX"
6156 {
6157 rtx scratch, seq, addr;
6158 unsigned regno = REGNO (operands[2]);
6160 /* It is possible that one of the registers we got for operands[2]
6161 might coincide with that of operands[0] (which is why we made
6162 it TImode). Pick the other one to use as our scratch. */
6163 if (regno == REGNO (operands[0]))
6164 regno++;
6165 scratch = gen_rtx_REG (DImode, regno);
6167 addr = get_unaligned_address (operands[1]);
6168 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
6169 seq = gen_unaligned_load<reloadmode> (operands[0], addr,
6170 scratch, operands[0]);
6171 alpha_set_memflags (seq, operands[1]);
6173 emit_insn (seq);
6174 DONE;
6175 })
6177 (define_expand "reload_out<mode>"
6178 [(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m")
6179 (match_operand:RELOAD12 1 "register_operand" "r")
6180 (match_operand:TI 2 "register_operand" "=&r")])]
6181 "! TARGET_BWX"
6182 {
6183 unsigned regno = REGNO (operands[2]);
6185 if (<MODE>mode == CQImode)
6186 {
6187 operands[0] = gen_lowpart (HImode, operands[0]);
6188 operands[1] = gen_lowpart (HImode, operands[1]);
6189 }
6191 if (aligned_memory_operand (operands[0], <MODE>mode))
6192 {
6193 emit_insn (gen_reload_out<reloadmode>_aligned
6194 (operands[0], operands[1],
6195 gen_rtx_REG (SImode, regno),
6196 gen_rtx_REG (SImode, regno + 1)));
6197 }
6198 else
6199 {
6200 rtx addr = get_unaligned_address (operands[0]);
6201 rtx scratch1 = gen_rtx_REG (DImode, regno);
6202 rtx scratch2 = gen_rtx_REG (DImode, regno + 1);
6203 rtx scratch3 = scratch1;
6204 rtx seq;
6206 if (GET_CODE (addr) == REG)
6207 scratch1 = addr;
6209 seq = gen_unaligned_store<reloadmode> (addr, operands[1], scratch1,
6210 scratch2, scratch3);
6211 alpha_set_memflags (seq, operands[0]);
6212 emit_insn (seq);
6213 }
6214 DONE;
6215 })
6217 ;; Helpers for the above. The way reload is structured, we can't
6218 ;; always get a proper address for a stack slot during reload_foo
6219 ;; expansion, so we must delay our address manipulations until after.
6221 (define_insn_and_split "reload_in<mode>_aligned"
6222 [(set (match_operand:I12MODE 0 "register_operand" "=r")
6223 (match_operand:I12MODE 1 "memory_operand" "m"))]
6224 "!TARGET_BWX && (reload_in_progress || reload_completed)"
6225 "#"
6226 "!TARGET_BWX && reload_completed"
6227 [(const_int 0)]
6228 {
6229 rtx aligned_mem, bitnum;
6230 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6231 emit_insn (gen_aligned_load<reloadmode>
6232 (gen_lowpart (DImode, operands[0]), aligned_mem, bitnum,
6233 gen_rtx_REG (SImode, REGNO (operands[0]))));
6234 DONE;
6235 })
6237 (define_insn_and_split "reload_out<mode>_aligned"
6238 [(set (match_operand:I12MODE 0 "memory_operand" "=m")
6239 (match_operand:I12MODE 1 "register_operand" "r"))
6240 (clobber (match_operand:SI 2 "register_operand" "=r"))
6241 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6242 "!TARGET_BWX && (reload_in_progress || reload_completed)"
6243 "#"
6244 "!TARGET_BWX && reload_completed"
6245 [(const_int 0)]
6246 {
6247 rtx aligned_mem, bitnum;
6248 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6249 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6250 operands[2], operands[3]));
6251 DONE;
6252 })
6253 \f
6254 ;; Vector operations
6256 (define_mode_iterator VEC [V8QI V4HI V2SI])
6258 (define_expand "mov<mode>"
6259 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6260 (match_operand:VEC 1 "general_operand" ""))]
6261 ""
6262 {
6263 if (alpha_expand_mov (<MODE>mode, operands))
6264 DONE;
6265 })
6267 (define_split
6268 [(set (match_operand:VEC 0 "register_operand" "")
6269 (match_operand:VEC 1 "non_zero_const_operand" ""))]
6270 ""
6271 [(const_int 0)]
6272 {
6273 if (alpha_split_const_mov (<MODE>mode, operands))
6274 DONE;
6275 else
6276 FAIL;
6277 })
6280 (define_expand "movmisalign<mode>"
6281 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6282 (match_operand:VEC 1 "general_operand" ""))]
6283 ""
6284 {
6285 alpha_expand_movmisalign (<MODE>mode, operands);
6286 DONE;
6287 })
6289 (define_insn "*mov<mode>_fix"
6290 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
6291 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
6292 "TARGET_FIX
6293 && (register_operand (operands[0], <MODE>mode)
6294 || reg_or_0_operand (operands[1], <MODE>mode))"
6295 "@
6296 bis $31,%r1,%0
6297 #
6298 ldq %0,%1
6299 stq %r1,%0
6300 cpys %R1,%R1,%0
6301 ldt %0,%1
6302 stt %R1,%0
6303 ftoit %1,%0
6304 itoft %1,%0"
6305 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
6307 (define_insn "*mov<mode>_nofix"
6308 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m")
6309 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f"))]
6310 "! TARGET_FIX
6311 && (register_operand (operands[0], <MODE>mode)
6312 || reg_or_0_operand (operands[1], <MODE>mode))"
6313 "@
6314 bis $31,%r1,%0
6315 #
6316 ldq %0,%1
6317 stq %r1,%0
6318 cpys %R1,%R1,%0
6319 ldt %0,%1
6320 stt %R1,%0"
6321 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst")])
6323 (define_insn "uminv8qi3"
6324 [(set (match_operand:V8QI 0 "register_operand" "=r")
6325 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6326 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6327 "TARGET_MAX"
6328 "minub8 %r1,%r2,%0"
6329 [(set_attr "type" "mvi")])
6331 (define_insn "sminv8qi3"
6332 [(set (match_operand:V8QI 0 "register_operand" "=r")
6333 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6334 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6335 "TARGET_MAX"
6336 "minsb8 %r1,%r2,%0"
6337 [(set_attr "type" "mvi")])
6339 (define_insn "uminv4hi3"
6340 [(set (match_operand:V4HI 0 "register_operand" "=r")
6341 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6342 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6343 "TARGET_MAX"
6344 "minuw4 %r1,%r2,%0"
6345 [(set_attr "type" "mvi")])
6347 (define_insn "sminv4hi3"
6348 [(set (match_operand:V4HI 0 "register_operand" "=r")
6349 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6350 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6351 "TARGET_MAX"
6352 "minsw4 %r1,%r2,%0"
6353 [(set_attr "type" "mvi")])
6355 (define_insn "umaxv8qi3"
6356 [(set (match_operand:V8QI 0 "register_operand" "=r")
6357 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6358 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6359 "TARGET_MAX"
6360 "maxub8 %r1,%r2,%0"
6361 [(set_attr "type" "mvi")])
6363 (define_insn "smaxv8qi3"
6364 [(set (match_operand:V8QI 0 "register_operand" "=r")
6365 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6366 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6367 "TARGET_MAX"
6368 "maxsb8 %r1,%r2,%0"
6369 [(set_attr "type" "mvi")])
6371 (define_insn "umaxv4hi3"
6372 [(set (match_operand:V4HI 0 "register_operand" "=r")
6373 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6374 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6375 "TARGET_MAX"
6376 "maxuw4 %r1,%r2,%0"
6377 [(set_attr "type" "mvi")])
6379 (define_insn "smaxv4hi3"
6380 [(set (match_operand:V4HI 0 "register_operand" "=r")
6381 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6382 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6383 "TARGET_MAX"
6384 "maxsw4 %r1,%r2,%0"
6385 [(set_attr "type" "mvi")])
6387 (define_insn "one_cmpl<mode>2"
6388 [(set (match_operand:VEC 0 "register_operand" "=r")
6389 (not:VEC (match_operand:VEC 1 "register_operand" "r")))]
6390 ""
6391 "ornot $31,%1,%0"
6392 [(set_attr "type" "ilog")])
6394 (define_insn "and<mode>3"
6395 [(set (match_operand:VEC 0 "register_operand" "=r")
6396 (and:VEC (match_operand:VEC 1 "register_operand" "r")
6397 (match_operand:VEC 2 "register_operand" "r")))]
6398 ""
6399 "and %1,%2,%0"
6400 [(set_attr "type" "ilog")])
6402 (define_insn "*andnot<mode>3"
6403 [(set (match_operand:VEC 0 "register_operand" "=r")
6404 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r"))
6405 (match_operand:VEC 2 "register_operand" "r")))]
6406 ""
6407 "bic %2,%1,%0"
6408 [(set_attr "type" "ilog")])
6410 (define_insn "ior<mode>3"
6411 [(set (match_operand:VEC 0 "register_operand" "=r")
6412 (ior:VEC (match_operand:VEC 1 "register_operand" "r")
6413 (match_operand:VEC 2 "register_operand" "r")))]
6414 ""
6415 "bis %1,%2,%0"
6416 [(set_attr "type" "ilog")])
6418 (define_insn "*iornot<mode>3"
6419 [(set (match_operand:VEC 0 "register_operand" "=r")
6420 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r"))
6421 (match_operand:VEC 2 "register_operand" "r")))]
6422 ""
6423 "ornot %2,%1,%0"
6424 [(set_attr "type" "ilog")])
6426 (define_insn "xor<mode>3"
6427 [(set (match_operand:VEC 0 "register_operand" "=r")
6428 (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6429 (match_operand:VEC 2 "register_operand" "r")))]
6430 ""
6431 "xor %1,%2,%0"
6432 [(set_attr "type" "ilog")])
6434 (define_insn "*xornot<mode>3"
6435 [(set (match_operand:VEC 0 "register_operand" "=r")
6436 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6437 (match_operand:VEC 2 "register_operand" "r"))))]
6438 ""
6439 "eqv %1,%2,%0"
6440 [(set_attr "type" "ilog")])
6442 (define_expand "vec_shl_<mode>"
6443 [(set (match_operand:VEC 0 "register_operand" "")
6444 (ashift:DI (match_operand:VEC 1 "register_operand" "")
6445 (match_operand:DI 2 "reg_or_6bit_operand" "")))]
6446 ""
6447 {
6448 operands[0] = gen_lowpart (DImode, operands[0]);
6449 operands[1] = gen_lowpart (DImode, operands[1]);
6450 })
6452 (define_expand "vec_shr_<mode>"
6453 [(set (match_operand:VEC 0 "register_operand" "")
6454 (lshiftrt:DI (match_operand:VEC 1 "register_operand" "")
6455 (match_operand:DI 2 "reg_or_6bit_operand" "")))]
6456 ""
6457 {
6458 operands[0] = gen_lowpart (DImode, operands[0]);
6459 operands[1] = gen_lowpart (DImode, operands[1]);
6460 })
6461 \f
6462 ;; Bit field extract patterns which use ext[wlq][lh]
6464 (define_expand "extv"
6465 [(set (match_operand:DI 0 "register_operand" "")
6466 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6467 (match_operand:DI 2 "immediate_operand" "")
6468 (match_operand:DI 3 "immediate_operand" "")))]
6469 ""
6470 {
6471 int ofs;
6473 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6474 if (INTVAL (operands[3]) % 8 != 0
6475 || (INTVAL (operands[2]) != 16
6476 && INTVAL (operands[2]) != 32
6477 && INTVAL (operands[2]) != 64))
6478 FAIL;
6480 /* From mips.md: extract_bit_field doesn't verify that our source
6481 matches the predicate, so we force it to be a MEM here. */
6482 if (GET_CODE (operands[1]) != MEM)
6483 FAIL;
6485 /* The bit number is relative to the mode of operand 1 which is
6486 usually QImode (this might actually be a bug in expmed.c). Note
6487 that the bit number is negative in big-endian mode in this case.
6488 We have to convert that to the offset. */
6489 if (WORDS_BIG_ENDIAN)
6490 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6491 - INTVAL (operands[2]) - INTVAL (operands[3]);
6492 else
6493 ofs = INTVAL (operands[3]);
6495 ofs = ofs / 8;
6497 alpha_expand_unaligned_load (operands[0], operands[1],
6498 INTVAL (operands[2]) / 8,
6499 ofs, 1);
6500 DONE;
6501 })
6503 (define_expand "extzv"
6504 [(set (match_operand:DI 0 "register_operand" "")
6505 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6506 (match_operand:DI 2 "immediate_operand" "")
6507 (match_operand:DI 3 "immediate_operand" "")))]
6508 ""
6509 {
6510 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6511 if (INTVAL (operands[3]) % 8 != 0
6512 || (INTVAL (operands[2]) != 8
6513 && INTVAL (operands[2]) != 16
6514 && INTVAL (operands[2]) != 32
6515 && INTVAL (operands[2]) != 64))
6516 FAIL;
6518 if (GET_CODE (operands[1]) == MEM)
6519 {
6520 int ofs;
6522 /* Fail 8-bit fields, falling back on a simple byte load. */
6523 if (INTVAL (operands[2]) == 8)
6524 FAIL;
6526 /* The bit number is relative to the mode of operand 1 which is
6527 usually QImode (this might actually be a bug in expmed.c). Note
6528 that the bit number is negative in big-endian mode in this case.
6529 We have to convert that to the offset. */
6530 if (WORDS_BIG_ENDIAN)
6531 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6532 - INTVAL (operands[2]) - INTVAL (operands[3]);
6533 else
6534 ofs = INTVAL (operands[3]);
6536 ofs = ofs / 8;
6538 alpha_expand_unaligned_load (operands[0], operands[1],
6539 INTVAL (operands[2]) / 8,
6540 ofs, 0);
6541 DONE;
6542 }
6543 })
6545 (define_expand "insv"
6546 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6547 (match_operand:DI 1 "immediate_operand" "")
6548 (match_operand:DI 2 "immediate_operand" ""))
6549 (match_operand:DI 3 "register_operand" ""))]
6550 ""
6551 {
6552 int ofs;
6554 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6555 if (INTVAL (operands[2]) % 8 != 0
6556 || (INTVAL (operands[1]) != 16
6557 && INTVAL (operands[1]) != 32
6558 && INTVAL (operands[1]) != 64))
6559 FAIL;
6561 /* From mips.md: store_bit_field doesn't verify that our source
6562 matches the predicate, so we force it to be a MEM here. */
6563 if (GET_CODE (operands[0]) != MEM)
6564 FAIL;
6566 /* The bit number is relative to the mode of operand 1 which is
6567 usually QImode (this might actually be a bug in expmed.c). Note
6568 that the bit number is negative in big-endian mode in this case.
6569 We have to convert that to the offset. */
6570 if (WORDS_BIG_ENDIAN)
6571 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6572 - INTVAL (operands[1]) - INTVAL (operands[2]);
6573 else
6574 ofs = INTVAL (operands[2]);
6576 ofs = ofs / 8;
6578 alpha_expand_unaligned_store (operands[0], operands[3],
6579 INTVAL (operands[1]) / 8, ofs);
6580 DONE;
6581 })
6583 ;; Block move/clear, see alpha.c for more details.
6584 ;; Argument 0 is the destination
6585 ;; Argument 1 is the source
6586 ;; Argument 2 is the length
6587 ;; Argument 3 is the alignment
6589 (define_expand "movmemqi"
6590 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6591 (match_operand:BLK 1 "memory_operand" ""))
6592 (use (match_operand:DI 2 "immediate_operand" ""))
6593 (use (match_operand:DI 3 "immediate_operand" ""))])]
6594 ""
6595 {
6596 if (alpha_expand_block_move (operands))
6597 DONE;
6598 else
6599 FAIL;
6600 })
6602 (define_expand "movmemdi"
6603 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6604 (match_operand:BLK 1 "memory_operand" ""))
6605 (use (match_operand:DI 2 "immediate_operand" ""))
6606 (use (match_operand:DI 3 "immediate_operand" ""))
6607 (use (match_dup 4))
6608 (clobber (reg:DI 25))
6609 (clobber (reg:DI 16))
6610 (clobber (reg:DI 17))
6611 (clobber (reg:DI 18))
6612 (clobber (reg:DI 19))
6613 (clobber (reg:DI 20))
6614 (clobber (reg:DI 26))
6615 (clobber (reg:DI 27))])]
6616 "TARGET_ABI_OPEN_VMS"
6617 {
6618 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6619 alpha_need_linkage (XSTR (operands[4], 0), 0);
6620 })
6622 (define_insn "*movmemdi_1"
6623 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6624 (match_operand:BLK 1 "memory_operand" "m,m"))
6625 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6626 (use (match_operand:DI 3 "immediate_operand" ""))
6627 (use (match_operand:DI 4 "call_operand" "i,i"))
6628 (clobber (reg:DI 25))
6629 (clobber (reg:DI 16))
6630 (clobber (reg:DI 17))
6631 (clobber (reg:DI 18))
6632 (clobber (reg:DI 19))
6633 (clobber (reg:DI 20))
6634 (clobber (reg:DI 26))
6635 (clobber (reg:DI 27))]
6636 "TARGET_ABI_OPEN_VMS"
6637 {
6638 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6639 switch (which_alternative)
6640 {
6641 case 0:
6642 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6643 case 1:
6644 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6645 default:
6646 gcc_unreachable ();
6647 }
6648 }
6649 [(set_attr "type" "multi")
6650 (set_attr "length" "28")])
6652 (define_expand "setmemqi"
6653 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6654 (match_operand 2 "const_int_operand" ""))
6655 (use (match_operand:DI 1 "immediate_operand" ""))
6656 (use (match_operand:DI 3 "immediate_operand" ""))])]
6657 ""
6658 {
6659 /* If value to set is not zero, use the library routine. */
6660 if (operands[2] != const0_rtx)
6661 FAIL;
6663 if (alpha_expand_block_clear (operands))
6664 DONE;
6665 else
6666 FAIL;
6667 })
6669 (define_expand "setmemdi"
6670 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6671 (match_operand 2 "const_int_operand" ""))
6672 (use (match_operand:DI 1 "immediate_operand" ""))
6673 (use (match_operand:DI 3 "immediate_operand" ""))
6674 (use (match_dup 4))
6675 (clobber (reg:DI 25))
6676 (clobber (reg:DI 16))
6677 (clobber (reg:DI 17))
6678 (clobber (reg:DI 26))
6679 (clobber (reg:DI 27))])]
6680 "TARGET_ABI_OPEN_VMS"
6681 {
6682 /* If value to set is not zero, use the library routine. */
6683 if (operands[2] != const0_rtx)
6684 FAIL;
6686 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6687 alpha_need_linkage (XSTR (operands[4], 0), 0);
6688 })
6690 (define_insn "*clrmemdi_1"
6691 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6692 (const_int 0))
6693 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6694 (use (match_operand:DI 2 "immediate_operand" ""))
6695 (use (match_operand:DI 3 "call_operand" "i,i"))
6696 (clobber (reg:DI 25))
6697 (clobber (reg:DI 16))
6698 (clobber (reg:DI 17))
6699 (clobber (reg:DI 26))
6700 (clobber (reg:DI 27))]
6701 "TARGET_ABI_OPEN_VMS"
6702 {
6703 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6704 switch (which_alternative)
6705 {
6706 case 0:
6707 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6708 case 1:
6709 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6710 default:
6711 gcc_unreachable ();
6712 }
6713 }
6714 [(set_attr "type" "multi")
6715 (set_attr "length" "24")])
6717 \f
6718 ;; Subroutine of stack space allocation. Perform a stack probe.
6719 (define_expand "probe_stack"
6720 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6721 ""
6722 {
6723 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6724 INTVAL (operands[0])));
6725 MEM_VOLATILE_P (operands[1]) = 1;
6727 operands[0] = const0_rtx;
6728 })
6730 ;; This is how we allocate stack space. If we are allocating a
6731 ;; constant amount of space and we know it is less than 4096
6732 ;; bytes, we need do nothing.
6733 ;;
6734 ;; If it is more than 4096 bytes, we need to probe the stack
6735 ;; periodically.
6736 (define_expand "allocate_stack"
6737 [(set (reg:DI 30)
6738 (plus:DI (reg:DI 30)
6739 (match_operand:DI 1 "reg_or_cint_operand" "")))
6740 (set (match_operand:DI 0 "register_operand" "=r")
6741 (match_dup 2))]
6742 ""
6743 {
6744 if (GET_CODE (operands[1]) == CONST_INT
6745 && INTVAL (operands[1]) < 32768)
6746 {
6747 if (INTVAL (operands[1]) >= 4096)
6748 {
6749 /* We do this the same way as in the prologue and generate explicit
6750 probes. Then we update the stack by the constant. */
6752 int probed = 4096;
6754 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6755 while (probed + 8192 < INTVAL (operands[1]))
6756 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6758 if (probed + 4096 < INTVAL (operands[1]))
6759 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6760 }
6762 operands[1] = GEN_INT (- INTVAL (operands[1]));
6763 operands[2] = virtual_stack_dynamic_rtx;
6764 }
6765 else
6766 {
6767 rtx out_label = 0;
6768 rtx loop_label = gen_label_rtx ();
6769 rtx want = gen_reg_rtx (Pmode);
6770 rtx tmp = gen_reg_rtx (Pmode);
6771 rtx memref;
6773 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6774 force_reg (Pmode, operands[1])));
6775 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6777 if (GET_CODE (operands[1]) != CONST_INT)
6778 {
6779 out_label = gen_label_rtx ();
6780 emit_insn (gen_cmpdi (want, tmp));
6781 emit_jump_insn (gen_bgeu (out_label));
6782 }
6784 emit_label (loop_label);
6785 memref = gen_rtx_MEM (DImode, tmp);
6786 MEM_VOLATILE_P (memref) = 1;
6787 emit_move_insn (memref, const0_rtx);
6788 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6789 emit_insn (gen_cmpdi (tmp, want));
6790 emit_jump_insn (gen_bgtu (loop_label));
6792 memref = gen_rtx_MEM (DImode, want);
6793 MEM_VOLATILE_P (memref) = 1;
6794 emit_move_insn (memref, const0_rtx);
6796 if (out_label)
6797 emit_label (out_label);
6799 emit_move_insn (stack_pointer_rtx, want);
6800 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6801 DONE;
6802 }
6803 })
6805 ;; This is used by alpha_expand_prolog to do the same thing as above,
6806 ;; except we cannot at that time generate new basic blocks, so we hide
6807 ;; the loop in this one insn.
6809 (define_insn "prologue_stack_probe_loop"
6810 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6811 (match_operand:DI 1 "register_operand" "r")]
6812 UNSPECV_PSPL)]
6813 ""
6814 {
6815 operands[2] = gen_label_rtx ();
6816 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6817 CODE_LABEL_NUMBER (operands[2]));
6819 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6820 }
6821 [(set_attr "length" "16")
6822 (set_attr "type" "multi")])
6824 (define_expand "prologue"
6825 [(clobber (const_int 0))]
6826 ""
6827 {
6828 alpha_expand_prologue ();
6829 DONE;
6830 })
6832 ;; These take care of emitting the ldgp insn in the prologue. This will be
6833 ;; an lda/ldah pair and we want to align them properly. So we have two
6834 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6835 ;; and the second of which emits nothing. However, both are marked as type
6836 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6837 ;; with them.
6839 (define_expand "prologue_ldgp"
6840 [(set (match_dup 0)
6841 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6842 (set (match_dup 0)
6843 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6844 ""
6845 {
6846 operands[0] = pic_offset_table_rtx;
6847 operands[1] = gen_rtx_REG (Pmode, 27);
6848 operands[2] = (TARGET_EXPLICIT_RELOCS
6849 ? GEN_INT (alpha_next_sequence_number++)
6850 : const0_rtx);
6851 })
6853 (define_insn "*ldgp_er_1"
6854 [(set (match_operand:DI 0 "register_operand" "=r")
6855 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6856 (match_operand 2 "const_int_operand" "")]
6857 UNSPECV_LDGP1))]
6858 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6859 "ldah %0,0(%1)\t\t!gpdisp!%2"
6860 [(set_attr "cannot_copy" "true")])
6862 (define_insn "*ldgp_er_2"
6863 [(set (match_operand:DI 0 "register_operand" "=r")
6864 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6865 (match_operand 2 "const_int_operand" "")]
6866 UNSPEC_LDGP2))]
6867 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6868 "lda %0,0(%1)\t\t!gpdisp!%2"
6869 [(set_attr "cannot_copy" "true")])
6871 (define_insn "*prologue_ldgp_er_2"
6872 [(set (match_operand:DI 0 "register_operand" "=r")
6873 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6874 (match_operand 2 "const_int_operand" "")]
6875 UNSPECV_PLDGP2))]
6876 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6877 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
6878 [(set_attr "cannot_copy" "true")])
6880 (define_insn "*prologue_ldgp_1"
6881 [(set (match_operand:DI 0 "register_operand" "=r")
6882 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6883 (match_operand 2 "const_int_operand" "")]
6884 UNSPECV_LDGP1))]
6885 ""
6886 "ldgp %0,0(%1)\n$%~..ng:"
6887 [(set_attr "cannot_copy" "true")])
6889 (define_insn "*prologue_ldgp_2"
6890 [(set (match_operand:DI 0 "register_operand" "=r")
6891 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6892 (match_operand 2 "const_int_operand" "")]
6893 UNSPECV_PLDGP2))]
6894 ""
6895 "")
6897 ;; The _mcount profiling hook has special calling conventions, and
6898 ;; does not clobber all the registers that a normal call would. So
6899 ;; hide the fact this is a call at all.
6901 (define_insn "prologue_mcount"
6902 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6903 ""
6904 {
6905 if (TARGET_EXPLICIT_RELOCS)
6906 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6907 cannot be called via the PLT. */
6908 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6909 else
6910 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6911 }
6912 [(set_attr "type" "multi")
6913 (set_attr "length" "8")])
6915 (define_insn "init_fp"
6916 [(set (match_operand:DI 0 "register_operand" "=r")
6917 (match_operand:DI 1 "register_operand" "r"))
6918 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6919 ""
6920 "bis $31,%1,%0")
6922 (define_expand "epilogue"
6923 [(return)]
6924 ""
6925 {
6926 alpha_expand_epilogue ();
6927 })
6929 (define_expand "sibcall_epilogue"
6930 [(return)]
6931 "TARGET_ABI_OSF"
6932 {
6933 alpha_expand_epilogue ();
6934 DONE;
6935 })
6937 (define_expand "builtin_longjmp"
6938 [(use (match_operand:DI 0 "register_operand" "r"))]
6939 "TARGET_ABI_OSF"
6940 {
6941 /* The elements of the buffer are, in order: */
6942 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6943 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6944 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6945 rtx pv = gen_rtx_REG (Pmode, 27);
6947 /* This bit is the same as expand_builtin_longjmp. */
6948 emit_move_insn (hard_frame_pointer_rtx, fp);
6949 emit_move_insn (pv, lab);
6950 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6951 emit_use (hard_frame_pointer_rtx);
6952 emit_use (stack_pointer_rtx);
6954 /* Load the label we are jumping through into $27 so that we know
6955 where to look for it when we get back to setjmp's function for
6956 restoring the gp. */
6957 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6958 emit_barrier ();
6959 DONE;
6960 })
6962 ;; This is effectively a copy of indirect_jump, but constrained such
6963 ;; that register renaming cannot foil our cunning plan with $27.
6964 (define_insn "builtin_longjmp_internal"
6965 [(set (pc)
6966 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6967 UNSPECV_LONGJMP))]
6968 ""
6969 "jmp $31,(%0),0"
6970 [(set_attr "type" "ibr")])
6972 (define_expand "builtin_setjmp_receiver"
6973 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6974 "TARGET_ABI_OSF"
6975 "")
6977 (define_insn_and_split "*builtin_setjmp_receiver_1"
6978 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR)]
6979 "TARGET_ABI_OSF"
6980 {
6981 if (TARGET_EXPLICIT_RELOCS)
6982 return "#";
6983 else
6984 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)";
6985 }
6986 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6987 [(set (match_dup 1)
6988 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6989 (set (match_dup 1)
6990 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6991 {
6992 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0))
6993 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]),
6994 UNSPECV_SETJMPR_ER));
6995 operands[1] = pic_offset_table_rtx;
6996 operands[2] = gen_rtx_REG (Pmode, 27);
6997 operands[3] = GEN_INT (alpha_next_sequence_number++);
6998 }
6999 [(set_attr "length" "12")
7000 (set_attr "type" "multi")])
7002 (define_insn "*builtin_setjmp_receiver_er_sl_1"
7003 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
7004 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS && TARGET_AS_CAN_SUBTRACT_LABELS"
7005 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
7007 (define_insn "*builtin_setjmp_receiver_er_1"
7008 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
7009 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
7010 "br $27,$LSJ%=\n$LSJ%=:"
7011 [(set_attr "type" "ibr")])
7013 (define_expand "exception_receiver"
7014 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
7015 "TARGET_ABI_OSF"
7016 {
7017 if (TARGET_LD_BUGGY_LDGP)
7018 operands[0] = alpha_gp_save_rtx ();
7019 else
7020 operands[0] = const0_rtx;
7021 })
7023 (define_insn "*exception_receiver_2"
7024 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
7025 "TARGET_ABI_OSF && TARGET_LD_BUGGY_LDGP"
7026 "ldq $29,%0"
7027 [(set_attr "type" "ild")])
7029 (define_insn_and_split "*exception_receiver_1"
7030 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
7031 "TARGET_ABI_OSF"
7032 {
7033 if (TARGET_EXPLICIT_RELOCS)
7034 return "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*";
7035 else
7036 return "ldgp $29,0($26)";
7037 }
7038 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
7039 [(set (match_dup 0)
7040 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
7041 (set (match_dup 0)
7042 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
7043 {
7044 operands[0] = pic_offset_table_rtx;
7045 operands[1] = gen_rtx_REG (Pmode, 26);
7046 operands[2] = GEN_INT (alpha_next_sequence_number++);
7047 }
7048 [(set_attr "length" "8")
7049 (set_attr "type" "multi")])
7051 (define_expand "nonlocal_goto_receiver"
7052 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
7053 (set (reg:DI 27) (mem:DI (reg:DI 29)))
7054 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
7055 (use (reg:DI 27))]
7056 "TARGET_ABI_OPEN_VMS"
7057 "")
7059 (define_insn "arg_home"
7060 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7061 (use (reg:DI 1))
7062 (use (reg:DI 25))
7063 (use (reg:DI 16))
7064 (use (reg:DI 17))
7065 (use (reg:DI 18))
7066 (use (reg:DI 19))
7067 (use (reg:DI 20))
7068 (use (reg:DI 21))
7069 (use (reg:DI 48))
7070 (use (reg:DI 49))
7071 (use (reg:DI 50))
7072 (use (reg:DI 51))
7073 (use (reg:DI 52))
7074 (use (reg:DI 53))
7075 (clobber (mem:BLK (const_int 0)))
7076 (clobber (reg:DI 24))
7077 (clobber (reg:DI 25))
7078 (clobber (reg:DI 0))]
7079 "TARGET_ABI_OPEN_VMS"
7080 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
7081 [(set_attr "length" "16")
7082 (set_attr "type" "multi")])
7084 ;; Load the CIW into r2 for calling __T3E_MISMATCH
7086 (define_expand "umk_mismatch_args"
7087 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
7088 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
7089 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
7090 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
7091 (const_int 8))
7092 (match_dup 2)))
7093 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
7094 "TARGET_ABI_UNICOSMK"
7095 {
7096 operands[1] = gen_reg_rtx (DImode);
7097 operands[2] = gen_reg_rtx (DImode);
7098 operands[3] = gen_reg_rtx (DImode);
7099 })
7101 (define_insn "arg_home_umk"
7102 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7103 (use (reg:DI 1))
7104 (use (reg:DI 2))
7105 (use (reg:DI 16))
7106 (use (reg:DI 17))
7107 (use (reg:DI 18))
7108 (use (reg:DI 19))
7109 (use (reg:DI 20))
7110 (use (reg:DI 21))
7111 (use (reg:DI 48))
7112 (use (reg:DI 49))
7113 (use (reg:DI 50))
7114 (use (reg:DI 51))
7115 (use (reg:DI 52))
7116 (use (reg:DI 53))
7117 (clobber (mem:BLK (const_int 0)))
7118 (parallel [
7119 (clobber (reg:DI 22))
7120 (clobber (reg:DI 23))
7121 (clobber (reg:DI 24))
7122 (clobber (reg:DI 0))
7123 (clobber (reg:DI 1))
7124 (clobber (reg:DI 2))
7125 (clobber (reg:DI 3))
7126 (clobber (reg:DI 4))
7127 (clobber (reg:DI 5))
7128 (clobber (reg:DI 6))
7129 (clobber (reg:DI 7))
7130 (clobber (reg:DI 8))])]
7131 "TARGET_ABI_UNICOSMK"
7132 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
7133 [(set_attr "length" "16")
7134 (set_attr "type" "multi")])
7136 ;; Prefetch data.
7137 ;;
7138 ;; On EV4, these instructions are nops -- no load occurs.
7139 ;;
7140 ;; On EV5, these instructions act as a normal load, and thus can trap
7141 ;; if the address is invalid. The OS may (or may not) handle this in
7142 ;; the entMM fault handler and suppress the fault. If so, then this
7143 ;; has the effect of a read prefetch instruction.
7144 ;;
7145 ;; On EV6, these become official prefetch instructions.
7147 (define_insn "prefetch"
7148 [(prefetch (match_operand:DI 0 "address_operand" "p")
7149 (match_operand:DI 1 "const_int_operand" "n")
7150 (match_operand:DI 2 "const_int_operand" "n"))]
7151 "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6"
7152 {
7153 /* Interpret "no temporal locality" as this data should be evicted once
7154 it is used. The "evict next" alternatives load the data into the cache
7155 and leave the LRU eviction counter pointing to that block. */
7156 static const char * const alt[2][2] = {
7157 {
7158 "ldq $31,%a0", /* read, evict next */
7159 "ldl $31,%a0", /* read, evict last */
7160 },
7161 {
7162 "ldt $f31,%a0", /* write, evict next */
7163 "lds $f31,%a0", /* write, evict last */
7164 }
7165 };
7167 bool write = INTVAL (operands[1]) != 0;
7168 bool lru = INTVAL (operands[2]) != 0;
7170 return alt[write][lru];
7171 }
7172 [(set_attr "type" "ild")])
7174 ;; Close the trap shadow of preceding instructions. This is generated
7175 ;; by alpha_reorg.
7177 (define_insn "trapb"
7178 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7179 ""
7180 "trapb"
7181 [(set_attr "type" "misc")])
7183 ;; No-op instructions used by machine-dependent reorg to preserve
7184 ;; alignment for instruction issue.
7185 ;; The Unicos/Mk assembler does not support these opcodes.
7187 (define_insn "nop"
7188 [(const_int 0)]
7189 ""
7190 "bis $31,$31,$31"
7191 [(set_attr "type" "ilog")])
7193 (define_insn "fnop"
7194 [(const_int 1)]
7195 "TARGET_FP"
7196 "cpys $f31,$f31,$f31"
7197 [(set_attr "type" "fcpys")])
7199 (define_insn "unop"
7200 [(const_int 2)]
7201 ""
7202 "ldq_u $31,0($30)")
7204 ;; On Unicos/Mk we use a macro for aligning code.
7206 (define_insn "realign"
7207 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7208 UNSPECV_REALIGN)]
7209 ""
7210 {
7211 if (TARGET_ABI_UNICOSMK)
7212 return "gcc@code@align %0";
7213 else
7214 return ".align %0 #realign";
7215 })
7216 \f
7217 ;; Instructions to be emitted from __builtins.
7219 (define_insn "builtin_cmpbge"
7220 [(set (match_operand:DI 0 "register_operand" "=r")
7221 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7222 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7223 UNSPEC_CMPBGE))]
7224 ""
7225 "cmpbge %r1,%2,%0"
7226 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7227 ;; actually differentiate between ILOG and ICMP in the schedule.
7228 [(set_attr "type" "icmp")])
7230 (define_expand "builtin_extbl"
7231 [(match_operand:DI 0 "register_operand" "")
7232 (match_operand:DI 1 "reg_or_0_operand" "")
7233 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7234 ""
7235 {
7236 rtx (*gen) (rtx, rtx, rtx, rtx);
7237 if (WORDS_BIG_ENDIAN)
7238 gen = gen_extxl_be;
7239 else
7240 gen = gen_extxl_le;
7241 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7242 DONE;
7243 })
7245 (define_expand "builtin_extwl"
7246 [(match_operand:DI 0 "register_operand" "")
7247 (match_operand:DI 1 "reg_or_0_operand" "")
7248 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7249 ""
7250 {
7251 rtx (*gen) (rtx, rtx, rtx, rtx);
7252 if (WORDS_BIG_ENDIAN)
7253 gen = gen_extxl_be;
7254 else
7255 gen = gen_extxl_le;
7256 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7257 DONE;
7258 })
7260 (define_expand "builtin_extll"
7261 [(match_operand:DI 0 "register_operand" "")
7262 (match_operand:DI 1 "reg_or_0_operand" "")
7263 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7264 ""
7265 {
7266 rtx (*gen) (rtx, rtx, rtx, rtx);
7267 if (WORDS_BIG_ENDIAN)
7268 gen = gen_extxl_be;
7269 else
7270 gen = gen_extxl_le;
7271 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7272 DONE;
7273 })
7275 (define_expand "builtin_extql"
7276 [(match_operand:DI 0 "register_operand" "")
7277 (match_operand:DI 1 "reg_or_0_operand" "")
7278 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7279 ""
7280 {
7281 rtx (*gen) (rtx, rtx, rtx, rtx);
7282 if (WORDS_BIG_ENDIAN)
7283 gen = gen_extxl_be;
7284 else
7285 gen = gen_extxl_le;
7286 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7287 DONE;
7288 })
7290 (define_expand "builtin_extwh"
7291 [(match_operand:DI 0 "register_operand" "")
7292 (match_operand:DI 1 "reg_or_0_operand" "")
7293 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7294 ""
7295 {
7296 rtx (*gen) (rtx, rtx, rtx);
7297 if (WORDS_BIG_ENDIAN)
7298 gen = gen_extwh_be;
7299 else
7300 gen = gen_extwh_le;
7301 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7302 DONE;
7303 })
7305 (define_expand "builtin_extlh"
7306 [(match_operand:DI 0 "register_operand" "")
7307 (match_operand:DI 1 "reg_or_0_operand" "")
7308 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7309 ""
7310 {
7311 rtx (*gen) (rtx, rtx, rtx);
7312 if (WORDS_BIG_ENDIAN)
7313 gen = gen_extlh_be;
7314 else
7315 gen = gen_extlh_le;
7316 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7317 DONE;
7318 })
7320 (define_expand "builtin_extqh"
7321 [(match_operand:DI 0 "register_operand" "")
7322 (match_operand:DI 1 "reg_or_0_operand" "")
7323 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7324 ""
7325 {
7326 rtx (*gen) (rtx, rtx, rtx);
7327 if (WORDS_BIG_ENDIAN)
7328 gen = gen_extqh_be;
7329 else
7330 gen = gen_extqh_le;
7331 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7332 DONE;
7333 })
7335 (define_expand "builtin_insbl"
7336 [(match_operand:DI 0 "register_operand" "")
7337 (match_operand:DI 1 "register_operand" "")
7338 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7339 ""
7340 {
7341 rtx (*gen) (rtx, rtx, rtx);
7342 if (WORDS_BIG_ENDIAN)
7343 gen = gen_insbl_be;
7344 else
7345 gen = gen_insbl_le;
7346 operands[1] = gen_lowpart (QImode, operands[1]);
7347 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7348 DONE;
7349 })
7351 (define_expand "builtin_inswl"
7352 [(match_operand:DI 0 "register_operand" "")
7353 (match_operand:DI 1 "register_operand" "")
7354 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7355 ""
7356 {
7357 rtx (*gen) (rtx, rtx, rtx);
7358 if (WORDS_BIG_ENDIAN)
7359 gen = gen_inswl_be;
7360 else
7361 gen = gen_inswl_le;
7362 operands[1] = gen_lowpart (HImode, operands[1]);
7363 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7364 DONE;
7365 })
7367 (define_expand "builtin_insll"
7368 [(match_operand:DI 0 "register_operand" "")
7369 (match_operand:DI 1 "register_operand" "")
7370 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7371 ""
7372 {
7373 rtx (*gen) (rtx, rtx, rtx);
7374 if (WORDS_BIG_ENDIAN)
7375 gen = gen_insll_be;
7376 else
7377 gen = gen_insll_le;
7378 operands[1] = gen_lowpart (SImode, operands[1]);
7379 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7380 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7381 DONE;
7382 })
7384 (define_expand "builtin_insql"
7385 [(match_operand:DI 0 "register_operand" "")
7386 (match_operand:DI 1 "reg_or_0_operand" "")
7387 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7388 ""
7389 {
7390 rtx (*gen) (rtx, rtx, rtx);
7391 if (WORDS_BIG_ENDIAN)
7392 gen = gen_insql_be;
7393 else
7394 gen = gen_insql_le;
7395 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7396 DONE;
7397 })
7399 (define_expand "builtin_inswh"
7400 [(match_operand:DI 0 "register_operand" "")
7401 (match_operand:DI 1 "register_operand" "")
7402 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7403 ""
7404 {
7405 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7406 DONE;
7407 })
7409 (define_expand "builtin_inslh"
7410 [(match_operand:DI 0 "register_operand" "")
7411 (match_operand:DI 1 "register_operand" "")
7412 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7413 ""
7414 {
7415 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7416 DONE;
7417 })
7419 (define_expand "builtin_insqh"
7420 [(match_operand:DI 0 "register_operand" "")
7421 (match_operand:DI 1 "register_operand" "")
7422 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7423 ""
7424 {
7425 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7426 DONE;
7427 })
7429 (define_expand "builtin_mskbl"
7430 [(match_operand:DI 0 "register_operand" "")
7431 (match_operand:DI 1 "reg_or_0_operand" "")
7432 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7433 ""
7434 {
7435 rtx (*gen) (rtx, rtx, rtx, rtx);
7436 rtx mask;
7437 if (WORDS_BIG_ENDIAN)
7438 gen = gen_mskxl_be;
7439 else
7440 gen = gen_mskxl_le;
7441 mask = GEN_INT (0xff);
7442 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7443 DONE;
7444 })
7446 (define_expand "builtin_mskwl"
7447 [(match_operand:DI 0 "register_operand" "")
7448 (match_operand:DI 1 "reg_or_0_operand" "")
7449 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7450 ""
7451 {
7452 rtx (*gen) (rtx, rtx, rtx, rtx);
7453 rtx mask;
7454 if (WORDS_BIG_ENDIAN)
7455 gen = gen_mskxl_be;
7456 else
7457 gen = gen_mskxl_le;
7458 mask = GEN_INT (0xffff);
7459 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7460 DONE;
7461 })
7463 (define_expand "builtin_mskll"
7464 [(match_operand:DI 0 "register_operand" "")
7465 (match_operand:DI 1 "reg_or_0_operand" "")
7466 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7467 ""
7468 {
7469 rtx (*gen) (rtx, rtx, rtx, rtx);
7470 rtx mask;
7471 if (WORDS_BIG_ENDIAN)
7472 gen = gen_mskxl_be;
7473 else
7474 gen = gen_mskxl_le;
7475 mask = immed_double_const (0xffffffff, 0, DImode);
7476 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7477 DONE;
7478 })
7480 (define_expand "builtin_mskql"
7481 [(match_operand:DI 0 "register_operand" "")
7482 (match_operand:DI 1 "reg_or_0_operand" "")
7483 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7484 ""
7485 {
7486 rtx (*gen) (rtx, rtx, rtx, rtx);
7487 rtx mask;
7488 if (WORDS_BIG_ENDIAN)
7489 gen = gen_mskxl_be;
7490 else
7491 gen = gen_mskxl_le;
7492 mask = constm1_rtx;
7493 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7494 DONE;
7495 })
7497 (define_expand "builtin_mskwh"
7498 [(match_operand:DI 0 "register_operand" "")
7499 (match_operand:DI 1 "register_operand" "")
7500 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7501 ""
7502 {
7503 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7504 DONE;
7505 })
7507 (define_expand "builtin_msklh"
7508 [(match_operand:DI 0 "register_operand" "")
7509 (match_operand:DI 1 "register_operand" "")
7510 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7511 ""
7512 {
7513 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7514 DONE;
7515 })
7517 (define_expand "builtin_mskqh"
7518 [(match_operand:DI 0 "register_operand" "")
7519 (match_operand:DI 1 "register_operand" "")
7520 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7521 ""
7522 {
7523 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7524 DONE;
7525 })
7527 (define_expand "builtin_zap"
7528 [(set (match_operand:DI 0 "register_operand" "")
7529 (and:DI (unspec:DI
7530 [(match_operand:DI 2 "reg_or_cint_operand" "")]
7531 UNSPEC_ZAP)
7532 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7533 ""
7534 {
7535 if (GET_CODE (operands[2]) == CONST_INT)
7536 {
7537 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7539 if (mask == const0_rtx)
7540 {
7541 emit_move_insn (operands[0], const0_rtx);
7542 DONE;
7543 }
7544 if (mask == constm1_rtx)
7545 {
7546 emit_move_insn (operands[0], operands[1]);
7547 DONE;
7548 }
7550 operands[1] = force_reg (DImode, operands[1]);
7551 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7552 DONE;
7553 }
7555 operands[1] = force_reg (DImode, operands[1]);
7556 operands[2] = gen_lowpart (QImode, operands[2]);
7557 })
7559 (define_insn "*builtin_zap_1"
7560 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7561 (and:DI (unspec:DI
7562 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")]
7563 UNSPEC_ZAP)
7564 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))]
7565 ""
7566 "@
7567 #
7568 #
7569 bis $31,$31,%0
7570 zap %r1,%2,%0"
7571 [(set_attr "type" "shift,shift,ilog,shift")])
7573 (define_split
7574 [(set (match_operand:DI 0 "register_operand" "")
7575 (and:DI (unspec:DI
7576 [(match_operand:QI 2 "const_int_operand" "")]
7577 UNSPEC_ZAP)
7578 (match_operand:DI 1 "const_int_operand" "")))]
7579 ""
7580 [(const_int 0)]
7581 {
7582 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7583 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7584 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7585 else
7586 {
7587 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7588 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7589 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7590 c_hi & CONST_DOUBLE_HIGH (mask),
7591 DImode);
7592 }
7593 emit_move_insn (operands[0], operands[1]);
7594 DONE;
7595 })
7597 (define_split
7598 [(set (match_operand:DI 0 "register_operand" "")
7599 (and:DI (unspec:DI
7600 [(match_operand:QI 2 "const_int_operand" "")]
7601 UNSPEC_ZAP)
7602 (match_operand:DI 1 "register_operand" "")))]
7603 ""
7604 [(set (match_dup 0)
7605 (and:DI (match_dup 1) (match_dup 2)))]
7606 {
7607 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7608 if (operands[2] == const0_rtx)
7609 {
7610 emit_move_insn (operands[0], const0_rtx);
7611 DONE;
7612 }
7613 if (operands[2] == constm1_rtx)
7614 {
7615 emit_move_insn (operands[0], operands[1]);
7616 DONE;
7617 }
7618 })
7620 (define_expand "builtin_zapnot"
7621 [(set (match_operand:DI 0 "register_operand" "")
7622 (and:DI (unspec:DI
7623 [(not:QI (match_operand:DI 2 "reg_or_cint_operand" ""))]
7624 UNSPEC_ZAP)
7625 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7626 ""
7627 {
7628 if (GET_CODE (operands[2]) == CONST_INT)
7629 {
7630 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7632 if (mask == const0_rtx)
7633 {
7634 emit_move_insn (operands[0], const0_rtx);
7635 DONE;
7636 }
7637 if (mask == constm1_rtx)
7638 {
7639 emit_move_insn (operands[0], operands[1]);
7640 DONE;
7641 }
7643 operands[1] = force_reg (DImode, operands[1]);
7644 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7645 DONE;
7646 }
7648 operands[1] = force_reg (DImode, operands[1]);
7649 operands[2] = gen_lowpart (QImode, operands[2]);
7650 })
7652 (define_insn "*builtin_zapnot_1"
7653 [(set (match_operand:DI 0 "register_operand" "=r")
7654 (and:DI (unspec:DI
7655 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7656 UNSPEC_ZAP)
7657 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7658 ""
7659 "zapnot %r1,%2,%0"
7660 [(set_attr "type" "shift")])
7662 (define_insn "builtin_amask"
7663 [(set (match_operand:DI 0 "register_operand" "=r")
7664 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7665 UNSPEC_AMASK))]
7666 ""
7667 "amask %1,%0"
7668 [(set_attr "type" "ilog")])
7670 (define_insn "builtin_implver"
7671 [(set (match_operand:DI 0 "register_operand" "=r")
7672 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7673 ""
7674 "implver %0"
7675 [(set_attr "type" "ilog")])
7677 (define_insn "builtin_rpcc"
7678 [(set (match_operand:DI 0 "register_operand" "=r")
7679 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7680 ""
7681 "rpcc %0"
7682 [(set_attr "type" "ilog")])
7684 (define_expand "builtin_minub8"
7685 [(match_operand:DI 0 "register_operand" "")
7686 (match_operand:DI 1 "reg_or_0_operand" "")
7687 (match_operand:DI 2 "reg_or_0_operand" "")]
7688 "TARGET_MAX"
7689 {
7690 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7691 operands[1], operands[2]);
7692 DONE;
7693 })
7695 (define_expand "builtin_minsb8"
7696 [(match_operand:DI 0 "register_operand" "")
7697 (match_operand:DI 1 "reg_or_0_operand" "")
7698 (match_operand:DI 2 "reg_or_0_operand" "")]
7699 "TARGET_MAX"
7700 {
7701 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7702 operands[1], operands[2]);
7703 DONE;
7704 })
7706 (define_expand "builtin_minuw4"
7707 [(match_operand:DI 0 "register_operand" "")
7708 (match_operand:DI 1 "reg_or_0_operand" "")
7709 (match_operand:DI 2 "reg_or_0_operand" "")]
7710 "TARGET_MAX"
7711 {
7712 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7713 operands[1], operands[2]);
7714 DONE;
7715 })
7717 (define_expand "builtin_minsw4"
7718 [(match_operand:DI 0 "register_operand" "")
7719 (match_operand:DI 1 "reg_or_0_operand" "")
7720 (match_operand:DI 2 "reg_or_0_operand" "")]
7721 "TARGET_MAX"
7722 {
7723 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7724 operands[1], operands[2]);
7725 DONE;
7726 })
7728 (define_expand "builtin_maxub8"
7729 [(match_operand:DI 0 "register_operand" "")
7730 (match_operand:DI 1 "reg_or_0_operand" "")
7731 (match_operand:DI 2 "reg_or_0_operand" "")]
7732 "TARGET_MAX"
7733 {
7734 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7735 operands[1], operands[2]);
7736 DONE;
7737 })
7739 (define_expand "builtin_maxsb8"
7740 [(match_operand:DI 0 "register_operand" "")
7741 (match_operand:DI 1 "reg_or_0_operand" "")
7742 (match_operand:DI 2 "reg_or_0_operand" "")]
7743 "TARGET_MAX"
7744 {
7745 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7746 operands[1], operands[2]);
7747 DONE;
7748 })
7750 (define_expand "builtin_maxuw4"
7751 [(match_operand:DI 0 "register_operand" "")
7752 (match_operand:DI 1 "reg_or_0_operand" "")
7753 (match_operand:DI 2 "reg_or_0_operand" "")]
7754 "TARGET_MAX"
7755 {
7756 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7757 operands[1], operands[2]);
7758 DONE;
7759 })
7761 (define_expand "builtin_maxsw4"
7762 [(match_operand:DI 0 "register_operand" "")
7763 (match_operand:DI 1 "reg_or_0_operand" "")
7764 (match_operand:DI 2 "reg_or_0_operand" "")]
7765 "TARGET_MAX"
7766 {
7767 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7768 operands[1], operands[2]);
7769 DONE;
7770 })
7772 (define_insn "builtin_perr"
7773 [(set (match_operand:DI 0 "register_operand" "=r")
7774 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7775 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7776 UNSPEC_PERR))]
7777 "TARGET_MAX"
7778 "perr %r1,%r2,%0"
7779 [(set_attr "type" "mvi")])
7781 (define_expand "builtin_pklb"
7782 [(set (match_operand:DI 0 "register_operand" "")
7783 (vec_concat:V8QI
7784 (vec_concat:V4QI
7785 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7786 (match_dup 2))
7787 (match_dup 3)))]
7788 "TARGET_MAX"
7789 {
7790 operands[0] = gen_lowpart (V8QImode, operands[0]);
7791 operands[1] = gen_lowpart (V2SImode, operands[1]);
7792 operands[2] = CONST0_RTX (V2QImode);
7793 operands[3] = CONST0_RTX (V4QImode);
7794 })
7796 (define_insn "*pklb"
7797 [(set (match_operand:V8QI 0 "register_operand" "=r")
7798 (vec_concat:V8QI
7799 (vec_concat:V4QI
7800 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7801 (match_operand:V2QI 2 "const0_operand" ""))
7802 (match_operand:V4QI 3 "const0_operand" "")))]
7803 "TARGET_MAX"
7804 "pklb %r1,%0"
7805 [(set_attr "type" "mvi")])
7807 (define_expand "builtin_pkwb"
7808 [(set (match_operand:DI 0 "register_operand" "")
7809 (vec_concat:V8QI
7810 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7811 (match_dup 2)))]
7812 "TARGET_MAX"
7813 {
7814 operands[0] = gen_lowpart (V8QImode, operands[0]);
7815 operands[1] = gen_lowpart (V4HImode, operands[1]);
7816 operands[2] = CONST0_RTX (V4QImode);
7817 })
7819 (define_insn "*pkwb"
7820 [(set (match_operand:V8QI 0 "register_operand" "=r")
7821 (vec_concat:V8QI
7822 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7823 (match_operand:V4QI 2 "const0_operand" "")))]
7824 "TARGET_MAX"
7825 "pkwb %r1,%0"
7826 [(set_attr "type" "mvi")])
7828 (define_expand "builtin_unpkbl"
7829 [(set (match_operand:DI 0 "register_operand" "")
7830 (zero_extend:V2SI
7831 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7832 (parallel [(const_int 0) (const_int 1)]))))]
7833 "TARGET_MAX"
7834 {
7835 operands[0] = gen_lowpart (V2SImode, operands[0]);
7836 operands[1] = gen_lowpart (V8QImode, operands[1]);
7837 })
7839 (define_insn "*unpkbl"
7840 [(set (match_operand:V2SI 0 "register_operand" "=r")
7841 (zero_extend:V2SI
7842 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7843 (parallel [(const_int 0) (const_int 1)]))))]
7844 "TARGET_MAX"
7845 "unpkbl %r1,%0"
7846 [(set_attr "type" "mvi")])
7848 (define_expand "builtin_unpkbw"
7849 [(set (match_operand:DI 0 "register_operand" "")
7850 (zero_extend:V4HI
7851 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7852 (parallel [(const_int 0)
7853 (const_int 1)
7854 (const_int 2)
7855 (const_int 3)]))))]
7856 "TARGET_MAX"
7857 {
7858 operands[0] = gen_lowpart (V4HImode, operands[0]);
7859 operands[1] = gen_lowpart (V8QImode, operands[1]);
7860 })
7862 (define_insn "*unpkbw"
7863 [(set (match_operand:V4HI 0 "register_operand" "=r")
7864 (zero_extend:V4HI
7865 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7866 (parallel [(const_int 0)
7867 (const_int 1)
7868 (const_int 2)
7869 (const_int 3)]))))]
7870 "TARGET_MAX"
7871 "unpkbw %r1,%0"
7872 [(set_attr "type" "mvi")])
7873 \f
7874 (include "sync.md")
7875 \f
7876 ;; The call patterns are at the end of the file because their
7877 ;; wildcard operand0 interferes with nice recognition.
7879 (define_insn "*call_value_osf_1_er_noreturn"
7880 [(set (match_operand 0 "" "")
7881 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7882 (match_operand 2 "" "")))
7883 (use (reg:DI 29))
7884 (clobber (reg:DI 26))]
7885 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7886 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7887 "@
7888 jsr $26,($27),0
7889 bsr $26,%1\t\t!samegp
7890 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#"
7891 [(set_attr "type" "jsr")
7892 (set_attr "length" "*,*,8")])
7894 (define_insn "*call_value_osf_1_er"
7895 [(set (match_operand 0 "" "")
7896 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7897 (match_operand 2 "" "")))
7898 (use (reg:DI 29))
7899 (clobber (reg:DI 26))]
7900 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7901 "@
7902 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7903 bsr $26,%1\t\t!samegp
7904 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7905 [(set_attr "type" "jsr")
7906 (set_attr "length" "12,*,16")])
7908 ;; We must use peep2 instead of a split because we need accurate life
7909 ;; information for $gp. Consider the case of { bar(); while (1); }.
7910 (define_peephole2
7911 [(parallel [(set (match_operand 0 "" "")
7912 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7913 (match_operand 2 "" "")))
7914 (use (reg:DI 29))
7915 (clobber (reg:DI 26))])]
7916 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7917 && ! samegp_function_operand (operands[1], Pmode)
7918 && (peep2_regno_dead_p (1, 29)
7919 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7920 [(parallel [(set (match_dup 0)
7921 (call (mem:DI (match_dup 3))
7922 (match_dup 2)))
7923 (use (reg:DI 29))
7924 (use (match_dup 1))
7925 (use (match_dup 4))
7926 (clobber (reg:DI 26))])]
7927 {
7928 if (CONSTANT_P (operands[1]))
7929 {
7930 operands[3] = gen_rtx_REG (Pmode, 27);
7931 operands[4] = GEN_INT (alpha_next_sequence_number++);
7932 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7933 operands[1], operands[4]));
7934 }
7935 else
7936 {
7937 operands[3] = operands[1];
7938 operands[1] = const0_rtx;
7939 operands[4] = const0_rtx;
7940 }
7941 })
7943 (define_peephole2
7944 [(parallel [(set (match_operand 0 "" "")
7945 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7946 (match_operand 2 "" "")))
7947 (use (reg:DI 29))
7948 (clobber (reg:DI 26))])]
7949 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7950 && ! samegp_function_operand (operands[1], Pmode)
7951 && ! (peep2_regno_dead_p (1, 29)
7952 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7953 [(parallel [(set (match_dup 0)
7954 (call (mem:DI (match_dup 3))
7955 (match_dup 2)))
7956 (set (match_dup 6)
7957 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP1))
7958 (use (match_dup 1))
7959 (use (match_dup 5))
7960 (clobber (reg:DI 26))])
7961 (set (match_dup 6)
7962 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP2))]
7963 {
7964 if (CONSTANT_P (operands[1]))
7965 {
7966 operands[3] = gen_rtx_REG (Pmode, 27);
7967 operands[5] = GEN_INT (alpha_next_sequence_number++);
7968 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7969 operands[1], operands[5]));
7970 }
7971 else
7972 {
7973 operands[3] = operands[1];
7974 operands[1] = const0_rtx;
7975 operands[5] = const0_rtx;
7976 }
7977 operands[4] = GEN_INT (alpha_next_sequence_number++);
7978 operands[6] = pic_offset_table_rtx;
7979 })
7981 (define_insn "*call_value_osf_2_er_nogp"
7982 [(set (match_operand 0 "" "")
7983 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7984 (match_operand 2 "" "")))
7985 (use (reg:DI 29))
7986 (use (match_operand 3 "" ""))
7987 (use (match_operand 4 "" ""))
7988 (clobber (reg:DI 26))]
7989 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7990 "jsr $26,(%1),%3%J4"
7991 [(set_attr "type" "jsr")])
7993 (define_insn "*call_value_osf_2_er"
7994 [(set (match_operand 0 "" "")
7995 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7996 (match_operand 2 "" "")))
7997 (set (reg:DI 29)
7998 (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand" "")]
7999 UNSPEC_LDGP1))
8000 (use (match_operand 3 "" ""))
8001 (use (match_operand 4 "" ""))
8002 (clobber (reg:DI 26))]
8003 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8004 "jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5"
8005 [(set_attr "type" "jsr")
8006 (set_attr "cannot_copy" "true")
8007 (set_attr "length" "8")])
8009 (define_insn "*call_value_osf_1_noreturn"
8010 [(set (match_operand 0 "" "")
8011 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
8012 (match_operand 2 "" "")))
8013 (use (reg:DI 29))
8014 (clobber (reg:DI 26))]
8015 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
8016 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8017 "@
8018 jsr $26,($27),0
8019 bsr $26,$%1..ng
8020 jsr $26,%1"
8021 [(set_attr "type" "jsr")
8022 (set_attr "length" "*,*,8")])
8024 (define_insn_and_split "call_value_osf_tlsgd"
8025 [(set (match_operand 0 "" "")
8026 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
8027 (const_int 0)))
8028 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
8029 (use (reg:DI 29))
8030 (clobber (reg:DI 26))]
8031 "HAVE_AS_TLS"
8032 "#"
8033 "&& reload_completed"
8034 [(set (match_dup 3)
8035 (unspec:DI [(match_dup 5)
8036 (match_dup 1)
8037 (match_dup 2)] UNSPEC_LITERAL))
8038 (parallel [(set (match_dup 0)
8039 (call (mem:DI (match_dup 3))
8040 (const_int 0)))
8041 (set (match_dup 5)
8042 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
8043 (use (match_dup 1))
8044 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))
8045 (clobber (reg:DI 26))])
8046 (set (match_dup 5)
8047 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
8048 {
8049 operands[3] = gen_rtx_REG (Pmode, 27);
8050 operands[4] = GEN_INT (alpha_next_sequence_number++);
8051 operands[5] = pic_offset_table_rtx;
8052 }
8053 [(set_attr "type" "multi")])
8055 (define_insn_and_split "call_value_osf_tlsldm"
8056 [(set (match_operand 0 "" "")
8057 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
8058 (const_int 0)))
8059 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
8060 (use (reg:DI 29))
8061 (clobber (reg:DI 26))]
8062 "HAVE_AS_TLS"
8063 "#"
8064 "&& reload_completed"
8065 [(set (match_dup 3)
8066 (unspec:DI [(match_dup 5)
8067 (match_dup 1)
8068 (match_dup 2)] UNSPEC_LITERAL))
8069 (parallel [(set (match_dup 0)
8070 (call (mem:DI (match_dup 3))
8071 (const_int 0)))
8072 (set (match_dup 5)
8073 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
8074 (use (match_dup 1))
8075 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))
8076 (clobber (reg:DI 26))])
8077 (set (match_dup 5)
8078 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
8079 {
8080 operands[3] = gen_rtx_REG (Pmode, 27);
8081 operands[4] = GEN_INT (alpha_next_sequence_number++);
8082 operands[5] = pic_offset_table_rtx;
8083 }
8084 [(set_attr "type" "multi")])
8086 (define_insn "*call_value_osf_1"
8087 [(set (match_operand 0 "" "")
8088 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
8089 (match_operand 2 "" "")))
8090 (use (reg:DI 29))
8091 (clobber (reg:DI 26))]
8092 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8093 "@
8094 jsr $26,($27),0\;ldgp $29,0($26)
8095 bsr $26,$%1..ng
8096 jsr $26,%1\;ldgp $29,0($26)"
8097 [(set_attr "type" "jsr")
8098 (set_attr "length" "12,*,16")])
8100 (define_insn "*sibcall_value_osf_1_er"
8101 [(set (match_operand 0 "" "")
8102 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8103 (match_operand 2 "" "")))
8104 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8105 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8106 "@
8107 br $31,%1\t\t!samegp
8108 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
8109 [(set_attr "type" "jsr")
8110 (set_attr "length" "*,8")])
8112 (define_insn "*sibcall_value_osf_1"
8113 [(set (match_operand 0 "" "")
8114 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8115 (match_operand 2 "" "")))
8116 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8117 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8118 "@
8119 br $31,$%1..ng
8120 lda $27,%1\;jmp $31,($27),%1"
8121 [(set_attr "type" "jsr")
8122 (set_attr "length" "*,8")])
8124 (define_insn "*call_value_nt_1"
8125 [(set (match_operand 0 "" "")
8126 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
8127 (match_operand 2 "" "")))
8128 (clobber (reg:DI 26))]
8129 "TARGET_ABI_WINDOWS_NT"
8130 "@
8131 jsr $26,(%1)
8132 bsr $26,%1
8133 jsr $26,%1"
8134 [(set_attr "type" "jsr")
8135 (set_attr "length" "*,*,12")])
8137 ; GAS relies on the order and position of instructions output below in order
8138 ; to generate relocs for VMS link to potentially optimize the call.
8139 ; Please do not molest.
8140 (define_insn "*call_value_vms_1"
8141 [(set (match_operand 0 "" "")
8142 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
8143 (match_operand 2 "" "")))
8144 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
8145 (use (reg:DI 25))
8146 (use (reg:DI 26))
8147 (clobber (reg:DI 27))]
8148 "TARGET_ABI_OPEN_VMS"
8149 {
8150 switch (which_alternative)
8151 {
8152 case 0:
8153 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
8154 case 1:
8155 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
8156 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
8157 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8158 default:
8159 gcc_unreachable ();
8160 }
8161 }
8162 [(set_attr "type" "jsr")
8163 (set_attr "length" "12,16")])
8165 (define_insn "*call_value_umk"
8166 [(set (match_operand 0 "" "")
8167 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8168 (match_operand 2 "" "")))
8169 (use (reg:DI 25))
8170 (clobber (reg:DI 26))]
8171 "TARGET_ABI_UNICOSMK"
8172 "jsr $26,(%1)"
8173 [(set_attr "type" "jsr")])