| blob | 28669009014022afb3e1be8668fe8abc19dbe799 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
110 #ifndef CHECK_STACK_LIMIT
111 #define CHECK_STACK_LIMIT (-1)
112 #endif
114 /* Return index of given mode in mult and division cost tables. */
115 #define MODE_INDEX(mode) \
116 ((mode) == QImode ? 0 \
117 : (mode) == HImode ? 1 \
118 : (mode) == SImode ? 2 \
119 : (mode) == DImode ? 3 \
120 : 4)
122 /* Processor costs (relative to an add) */
123 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
124 #define COSTS_N_BYTES(N) ((N) * 2)
126 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
135 const
158 in QImode, HImode and SImode.
159 Relative to reg-reg move (2). */
163 in SFmode, DFmode and XFmode */
165 in SFmode, DFmode and XFmode */
168 in SImode and DImode */
170 in SImode and DImode */
173 in SImode, DImode and TImode */
175 in SImode, DImode and TImode */
188 ix86_size_memcpy,
189 ix86_size_memset,
201 };
203 /* Processor costs (relative to an add) */
206 DUMMY_STRINGOP_ALGS};
209 DUMMY_STRINGOP_ALGS};
211 static const
234 in QImode, HImode and SImode.
235 Relative to reg-reg move (2). */
239 in SFmode, DFmode and XFmode */
241 in SFmode, DFmode and XFmode */
244 in SImode and DImode */
246 in SImode and DImode */
249 in SImode, DImode and TImode */
251 in SImode, DImode and TImode */
264 i386_memcpy,
265 i386_memset,
277 };
281 DUMMY_STRINGOP_ALGS};
284 DUMMY_STRINGOP_ALGS};
286 static const
309 in QImode, HImode and SImode.
310 Relative to reg-reg move (2). */
314 in SFmode, DFmode and XFmode */
316 in SFmode, DFmode and XFmode */
319 in SImode and DImode */
321 in SImode and DImode */
324 in SImode, DImode and TImode */
326 in SImode, DImode and TImode */
329 shared for code and data, so 4kB is
330 not really precise. */
341 i486_memcpy,
342 i486_memset,
354 };
358 DUMMY_STRINGOP_ALGS};
361 DUMMY_STRINGOP_ALGS};
363 static const
386 in QImode, HImode and SImode.
387 Relative to reg-reg move (2). */
391 in SFmode, DFmode and XFmode */
393 in SFmode, DFmode and XFmode */
396 in SImode and DImode */
398 in SImode and DImode */
401 in SImode, DImode and TImode */
403 in SImode, DImode and TImode */
416 pentium_memcpy,
417 pentium_memset,
429 };
431 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
432 (we ensure the alignment). For small blocks inline loop is still a
433 noticeable win, for bigger blocks either rep movsl or rep movsb is
434 way to go. Rep movsb has apparently more expensive startup time in CPU,
435 but after 4K the difference is down in the noise. */
440 DUMMY_STRINGOP_ALGS};
445 DUMMY_STRINGOP_ALGS};
446 static const
469 in QImode, HImode and SImode.
470 Relative to reg-reg move (2). */
474 in SFmode, DFmode and XFmode */
476 in SFmode, DFmode and XFmode */
479 in SImode and DImode */
481 in SImode and DImode */
484 in SImode, DImode and TImode */
486 in SImode, DImode and TImode */
499 pentiumpro_memcpy,
500 pentiumpro_memset,
512 };
516 DUMMY_STRINGOP_ALGS};
519 DUMMY_STRINGOP_ALGS};
520 static const
543 in QImode, HImode and SImode.
544 Relative to reg-reg move (2). */
548 in SFmode, DFmode and XFmode */
550 in SFmode, DFmode and XFmode */
554 in SImode and DImode */
556 in SImode and DImode */
559 in SImode, DImode and TImode */
561 in SImode, DImode and TImode */
574 geode_memcpy,
575 geode_memset,
587 };
591 DUMMY_STRINGOP_ALGS};
594 DUMMY_STRINGOP_ALGS};
595 static const
618 in QImode, HImode and SImode.
619 Relative to reg-reg move (2). */
623 in SFmode, DFmode and XFmode */
625 in SFmode, DFmode and XFmode */
628 in SImode and DImode */
630 in SImode and DImode */
633 in SImode, DImode and TImode */
635 in SImode, DImode and TImode */
639 have integrated l2 cache, but
640 optimizing for k6 is not important
641 enough to worry about that. */
651 k6_memcpy,
652 k6_memset,
664 };
666 /* For some reason, Athlon deals better with REP prefix (relative to loops)
667 compared to K8. Alignment becomes important after 8 bytes for memcpy and
668 128 bytes for memset. */
671 DUMMY_STRINGOP_ALGS};
674 DUMMY_STRINGOP_ALGS};
675 static const
698 in QImode, HImode and SImode.
699 Relative to reg-reg move (2). */
703 in SFmode, DFmode and XFmode */
705 in SFmode, DFmode and XFmode */
708 in SImode and DImode */
710 in SImode and DImode */
713 in SImode, DImode and TImode */
715 in SImode, DImode and TImode */
728 athlon_memcpy,
729 athlon_memset,
741 };
743 /* K8 has optimized REP instruction for medium sized blocks, but for very
744 small blocks it is better to use loop. For large blocks, libcall can
745 do nontemporary accesses and beat inline considerably. */
756 static const
779 in QImode, HImode and SImode.
780 Relative to reg-reg move (2). */
784 in SFmode, DFmode and XFmode */
786 in SFmode, DFmode and XFmode */
789 in SImode and DImode */
791 in SImode and DImode */
794 in SImode, DImode and TImode */
796 in SImode, DImode and TImode */
801 /* New AMD processors never drop prefetches; if they cannot be performed
802 immediately, they are queued. We set number of simultaneous prefetches
803 to a large constant to reflect this (it probably is not a good idea not
804 to limit number of prefetches at all, as their execution also takes some
805 time). */
815 k8_memcpy,
816 k8_memset,
828 };
830 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
831 very small blocks it is better to use loop. For large blocks, libcall can
832 do nontemporary accesses and beat inline considerably. */
865 in QImode, HImode and SImode.
866 Relative to reg-reg move (2). */
870 in SFmode, DFmode and XFmode */
872 in SFmode, DFmode and XFmode */
875 in SImode and DImode */
877 in SImode and DImode */
880 in SImode, DImode and TImode */
882 in SImode, DImode and TImode */
884 /* On K8:
885 MOVD reg64, xmmreg Double FSTORE 4
886 MOVD reg32, xmmreg Double FSTORE 4
887 On AMDFAM10:
888 MOVD reg64, xmmreg Double FADD 3
889 1/1 1/1
890 MOVD reg32, xmmreg Double FADD 3
891 1/1 1/1 */
895 /* New AMD processors never drop prefetches; if they cannot be performed
896 immediately, they are queued. We set number of simultaneous prefetches
897 to a large constant to reflect this (it probably is not a good idea not
898 to limit number of prefetches at all, as their execution also takes some
899 time). */
909 amdfam10_memcpy,
910 amdfam10_memset,
922 };
924 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
925 very small blocks it is better to use loop. For large blocks, libcall
926 can do nontemporary accesses and beat inline considerably. */
960 in QImode, HImode and SImode.
961 Relative to reg-reg move (2). */
965 in SFmode, DFmode and XFmode */
967 in SFmode, DFmode and XFmode */
970 in SImode and DImode */
972 in SImode and DImode */
975 in SImode, DImode and TImode */
977 in SImode, DImode and TImode */
979 /* On K8:
980 MOVD reg64, xmmreg Double FSTORE 4
981 MOVD reg32, xmmreg Double FSTORE 4
982 On AMDFAM10:
983 MOVD reg64, xmmreg Double FADD 3
984 1/1 1/1
985 MOVD reg32, xmmreg Double FADD 3
986 1/1 1/1 */
990 /* New AMD processors never drop prefetches; if they cannot be performed
991 immediately, they are queued. We set number of simultaneous prefetches
992 to a large constant to reflect this (it probably is not a good idea not
993 to limit number of prefetches at all, as their execution also takes some
994 time). */
1004 bdver1_memcpy,
1005 bdver1_memset,
1017 };
1019 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1020 very small blocks it is better to use loop. For large blocks, libcall
1021 can do nontemporary accesses and beat inline considerably. */
1056 in QImode, HImode and SImode.
1057 Relative to reg-reg move (2). */
1061 in SFmode, DFmode and XFmode */
1063 in SFmode, DFmode and XFmode */
1066 in SImode and DImode */
1068 in SImode and DImode */
1071 in SImode, DImode and TImode */
1073 in SImode, DImode and TImode */
1075 /* On K8:
1076 MOVD reg64, xmmreg Double FSTORE 4
1077 MOVD reg32, xmmreg Double FSTORE 4
1078 On AMDFAM10:
1079 MOVD reg64, xmmreg Double FADD 3
1080 1/1 1/1
1081 MOVD reg32, xmmreg Double FADD 3
1082 1/1 1/1 */
1086 /* New AMD processors never drop prefetches; if they cannot be performed
1087 immediately, they are queued. We set number of simultaneous prefetches
1088 to a large constant to reflect this (it probably is not a good idea not
1089 to limit number of prefetches at all, as their execution also takes some
1090 time). */
1100 bdver2_memcpy,
1101 bdver2_memset,
1113 };
1116 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1117 very small blocks it is better to use loop. For large blocks, libcall
1118 can do nontemporary accesses and beat inline considerably. */
1151 in QImode, HImode and SImode.
1152 Relative to reg-reg move (2). */
1156 in SFmode, DFmode and XFmode */
1158 in SFmode, DFmode and XFmode */
1161 in SImode and DImode */
1163 in SImode and DImode */
1166 in SImode, DImode and TImode */
1168 in SImode, DImode and TImode */
1173 /* New AMD processors never drop prefetches; if they cannot be performed
1174 immediately, they are queued. We set number of simultaneous prefetches
1175 to a large constant to reflect this (it probably is not a good idea not
1176 to limit number of prefetches at all, as their execution also takes some
1177 time). */
1187 bdver3_memcpy,
1188 bdver3_memset,
1200 };
1202 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1203 very small blocks it is better to use loop. For large blocks, libcall
1204 can do nontemporary accesses and beat inline considerably. */
1237 in QImode, HImode and SImode.
1238 Relative to reg-reg move (2). */
1242 in SFmode, DFmode and XFmode */
1244 in SFmode, DFmode and XFmode */
1247 in SImode and DImode */
1249 in SImode and DImode */
1252 in SImode, DImode and TImode */
1254 in SImode, DImode and TImode */
1259 /* New AMD processors never drop prefetches; if they cannot be performed
1260 immediately, they are queued. We set number of simultaneous prefetches
1261 to a large constant to reflect this (it probably is not a good idea not
1262 to limit number of prefetches at all, as their execution also takes some
1263 time). */
1273 bdver4_memcpy,
1274 bdver4_memset,
1286 };
1288 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1289 very small blocks it is better to use loop. For large blocks, libcall can
1290 do nontemporary accesses and beat inline considerably. */
1323 in QImode, HImode and SImode.
1324 Relative to reg-reg move (2). */
1328 in SFmode, DFmode and XFmode */
1330 in SFmode, DFmode and XFmode */
1333 in SImode and DImode */
1335 in SImode and DImode */
1338 in SImode, DImode and TImode */
1340 in SImode, DImode and TImode */
1342 /* On K8:
1343 MOVD reg64, xmmreg Double FSTORE 4
1344 MOVD reg32, xmmreg Double FSTORE 4
1345 On AMDFAM10:
1346 MOVD reg64, xmmreg Double FADD 3
1347 1/1 1/1
1348 MOVD reg32, xmmreg Double FADD 3
1349 1/1 1/1 */
1362 btver1_memcpy,
1363 btver1_memset,
1375 };
1409 in QImode, HImode and SImode.
1410 Relative to reg-reg move (2). */
1414 in SFmode, DFmode and XFmode */
1416 in SFmode, DFmode and XFmode */
1419 in SImode and DImode */
1421 in SImode and DImode */
1424 in SImode, DImode and TImode */
1426 in SImode, DImode and TImode */
1428 /* On K8:
1429 MOVD reg64, xmmreg Double FSTORE 4
1430 MOVD reg32, xmmreg Double FSTORE 4
1431 On AMDFAM10:
1432 MOVD reg64, xmmreg Double FADD 3
1433 1/1 1/1
1434 MOVD reg32, xmmreg Double FADD 3
1435 1/1 1/1 */
1447 btver2_memcpy,
1448 btver2_memset,
1460 };
1464 DUMMY_STRINGOP_ALGS};
1468 DUMMY_STRINGOP_ALGS};
1470 static const
1493 in QImode, HImode and SImode.
1494 Relative to reg-reg move (2). */
1498 in SFmode, DFmode and XFmode */
1500 in SFmode, DFmode and XFmode */
1503 in SImode and DImode */
1505 in SImode and DImode */
1508 in SImode, DImode and TImode */
1510 in SImode, DImode and TImode */
1523 pentium4_memcpy,
1524 pentium4_memset,
1536 };
1549 static const
1572 in QImode, HImode and SImode.
1573 Relative to reg-reg move (2). */
1577 in SFmode, DFmode and XFmode */
1579 in SFmode, DFmode and XFmode */
1582 in SImode and DImode */
1584 in SImode and DImode */
1587 in SImode, DImode and TImode */
1589 in SImode, DImode and TImode */
1602 nocona_memcpy,
1603 nocona_memset,
1615 };
1626 static const
1649 in QImode, HImode and SImode.
1650 Relative to reg-reg move (2). */
1654 in SFmode, DFmode and XFmode */
1656 in SFmode, DFmode and XFmode */
1659 in SImode and DImode */
1661 in SImode and DImode */
1664 in SImode, DImode and TImode */
1666 in SImode, DImode and TImode */
1679 atom_memcpy,
1680 atom_memset,
1692 };
1703 static const
1726 in QImode, HImode and SImode.
1727 Relative to reg-reg move (2). */
1731 in SFmode, DFmode and XFmode */
1733 in SFmode, DFmode and XFmode */
1736 in SImode and DImode */
1738 in SImode and DImode */
1741 in SImode, DImode and TImode */
1743 in SImode, DImode and TImode */
1756 slm_memcpy,
1757 slm_memset,
1769 };
1780 static const
1803 in QImode, HImode and SImode.
1804 Relative to reg-reg move (2). */
1808 in SFmode, DFmode and XFmode */
1810 in SFmode, DFmode and XFmode */
1813 in SImode and DImode */
1815 in SImode and DImode */
1818 in SImode, DImode and TImode */
1820 in SImode, DImode and TImode */
1833 intel_memcpy,
1834 intel_memset,
1846 };
1848 /* Generic should produce code tuned for Core-i7 (and newer chips)
1849 and btver1 (and newer chips). */
1861 static const
1864 /* On all chips taken into consideration lea is 2 cycles and more. With
1865 this cost however our current implementation of synth_mult results in
1866 use of unnecessary temporary registers causing regression on several
1867 SPECfp benchmarks. */
1888 in QImode, HImode and SImode.
1889 Relative to reg-reg move (2). */
1893 in SFmode, DFmode and XFmode */
1895 in SFmode, DFmode and XFmode */
1898 in SImode and DImode */
1900 in SImode and DImode */
1903 in SImode, DImode and TImode */
1905 in SImode, DImode and TImode */
1911 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1912 value is increased to perhaps more appropriate value of 5. */
1920 generic_memcpy,
1921 generic_memset,
1933 };
1935 /* core_cost should produce code tuned for Core familly of CPUs. */
1948 static const
1951 /* On all chips taken into consideration lea is 2 cycles and more. With
1952 this cost however our current implementation of synth_mult results in
1953 use of unnecessary temporary registers causing regression on several
1954 SPECfp benchmarks. */
1975 in QImode, HImode and SImode.
1976 Relative to reg-reg move (2). */
1980 in SFmode, DFmode and XFmode */
1982 in SFmode, DFmode and XFmode */
1985 in SImode and DImode */
1987 in SImode and DImode */
1990 in SImode, DImode and TImode */
1992 in SImode, DImode and TImode */
1998 /* FIXME perhaps more appropriate value is 5. */
2006 core_memcpy,
2007 core_memset,
2019 };
2022 /* Set by -mtune. */
2025 /* Set by -mtune or -Os. */
2028 /* Processor feature/optimization bitmasks. */
2029 #define m_386 (1<<PROCESSOR_I386)
2030 #define m_486 (1<<PROCESSOR_I486)
2031 #define m_PENT (1<<PROCESSOR_PENTIUM)
2032 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2033 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2034 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2035 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2036 #define m_CORE2 (1<<PROCESSOR_CORE2)
2037 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2038 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2039 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2040 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2041 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2042 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2043 #define m_INTEL (1<<PROCESSOR_INTEL)
2045 #define m_GEODE (1<<PROCESSOR_GEODE)
2046 #define m_K6 (1<<PROCESSOR_K6)
2047 #define m_K6_GEODE (m_K6 | m_GEODE)
2048 #define m_K8 (1<<PROCESSOR_K8)
2049 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2050 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2051 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2052 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2053 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2054 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2055 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2056 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2057 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2058 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2059 #define m_BTVER (m_BTVER1 | m_BTVER2)
2060 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2062 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2065 #undef DEF_TUNE
2066 #define DEF_TUNE(tune, name, selector) name,
2068 #undef DEF_TUNE
2069 };
2071 /* Feature tests against the various tunings. */
2074 /* Feature tests against the various tunings used to create ix86_tune_features
2075 based on the processor mask. */
2077 #undef DEF_TUNE
2078 #define DEF_TUNE(tune, name, selector) selector,
2080 #undef DEF_TUNE
2081 };
2083 /* Feature tests against the various architecture variations. */
2086 /* Feature tests against the various architecture variations, used to create
2087 ix86_arch_features based on the processor mask. */
2089 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2092 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2095 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2098 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2101 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2103 };
2105 /* In case the average insn count for single function invocation is
2106 lower than this constant, emit fast (but longer) prologue and
2107 epilogue code. */
2108 #define FAST_PROLOGUE_INSN_COUNT 20
2110 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2115 /* Array of the smallest class containing reg number REGNO, indexed by
2116 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2119 {
2120 /* ax, dx, cx, bx */
2122 /* si, di, bp, sp */
2124 /* FP registers */
2127 /* arg pointer */
2128 NON_Q_REGS,
2129 /* flags, fpsr, fpcr, frame */
2131 /* SSE registers */
2134 /* MMX registers */
2137 /* REX registers */
2140 /* SSE REX registers */
2143 /* AVX-512 SSE registers */
2148 /* Mask registers. */
2151 /* MPX bound registers */
2153 };
2155 /* The "default" register map used in 32bit mode. */
2158 {
2170 };
2172 /* The "default" register map used in 64bit mode. */
2175 {
2187 };
2189 /* Define the register numbers to be used in Dwarf debugging information.
2190 The SVR4 reference port C compiler uses the following register numbers
2191 in its Dwarf output code:
2192 0 for %eax (gcc regno = 0)
2193 1 for %ecx (gcc regno = 2)
2194 2 for %edx (gcc regno = 1)
2195 3 for %ebx (gcc regno = 3)
2196 4 for %esp (gcc regno = 7)
2197 5 for %ebp (gcc regno = 6)
2198 6 for %esi (gcc regno = 4)
2199 7 for %edi (gcc regno = 5)
2200 The following three DWARF register numbers are never generated by
2201 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2202 believes these numbers have these meanings.
2203 8 for %eip (no gcc equivalent)
2204 9 for %eflags (gcc regno = 17)
2205 10 for %trapno (no gcc equivalent)
2206 It is not at all clear how we should number the FP stack registers
2207 for the x86 architecture. If the version of SDB on x86/svr4 were
2208 a bit less brain dead with respect to floating-point then we would
2209 have a precedent to follow with respect to DWARF register numbers
2210 for x86 FP registers, but the SDB on x86/svr4 is so completely
2211 broken with respect to FP registers that it is hardly worth thinking
2212 of it as something to strive for compatibility with.
2213 The version of x86/svr4 SDB I have at the moment does (partially)
2214 seem to believe that DWARF register number 11 is associated with
2215 the x86 register %st(0), but that's about all. Higher DWARF
2216 register numbers don't seem to be associated with anything in
2217 particular, and even for DWARF regno 11, SDB only seems to under-
2218 stand that it should say that a variable lives in %st(0) (when
2219 asked via an `=' command) if we said it was in DWARF regno 11,
2220 but SDB still prints garbage when asked for the value of the
2221 variable in question (via a `/' command).
2222 (Also note that the labels SDB prints for various FP stack regs
2223 when doing an `x' command are all wrong.)
2224 Note that these problems generally don't affect the native SVR4
2225 C compiler because it doesn't allow the use of -O with -g and
2226 because when it is *not* optimizing, it allocates a memory
2227 location for each floating-point variable, and the memory
2228 location is what gets described in the DWARF AT_location
2229 attribute for the variable in question.
2230 Regardless of the severe mental illness of the x86/svr4 SDB, we
2231 do something sensible here and we use the following DWARF
2232 register numbers. Note that these are all stack-top-relative
2233 numbers.
2234 11 for %st(0) (gcc regno = 8)
2235 12 for %st(1) (gcc regno = 9)
2236 13 for %st(2) (gcc regno = 10)
2237 14 for %st(3) (gcc regno = 11)
2238 15 for %st(4) (gcc regno = 12)
2239 16 for %st(5) (gcc regno = 13)
2240 17 for %st(6) (gcc regno = 14)
2241 18 for %st(7) (gcc regno = 15)
2242 */
2244 {
2256 };
2258 /* Define parameter passing and return registers. */
2261 {
2263 };
2266 {
2268 };
2271 {
2273 };
2275 /* Additional registers that are clobbered by SYSV calls. */
2278 {
2283 };
2285 /* Define the structure for the machine field in struct function. */
2290 rtx rtl;
2292 };
2294 /* Structure describing stack frame layout.
2295 Stack grows downward:
2297 [arguments]
2298 <- ARG_POINTER
2299 saved pc
2301 saved static chain if ix86_static_chain_on_stack
2303 saved frame pointer if frame_pointer_needed
2304 <- HARD_FRAME_POINTER
2305 [saved regs]
2306 <- regs_save_offset
2307 [padding0]
2309 [saved SSE regs]
2310 <- sse_regs_save_offset
2311 [padding1] |
2312 | <- FRAME_POINTER
2313 [va_arg registers] |
2314 |
2315 [frame] |
2316 |
2317 [padding2] | = to_allocate
2318 <- STACK_POINTER
2319 */
2320 struct ix86_frame
2321 {
2328 /* The offsets relative to ARG_POINTER. */
2329 HOST_WIDE_INT frame_pointer_offset;
2330 HOST_WIDE_INT hard_frame_pointer_offset;
2331 HOST_WIDE_INT stack_pointer_offset;
2332 HOST_WIDE_INT hfp_save_offset;
2333 HOST_WIDE_INT reg_save_offset;
2334 HOST_WIDE_INT sse_reg_save_offset;
2336 /* When save_regs_using_mov is set, emit prologue using
2337 move instead of push instructions. */
2339 };
2341 /* Which cpu are we scheduling for. */
2344 /* Which cpu are we optimizing for. */
2347 /* Which instruction set architecture to use. */
2350 /* True if processor has SSE prefetch instruction. */
2353 /* -mstackrealign option */
2370 /* Preferred alignment for stack boundary in bits. */
2373 /* Alignment for incoming stack boundary in bits specified at
2374 command line. */
2377 /* Default alignment for incoming stack boundary in bits. */
2380 /* Alignment for incoming stack boundary in bits. */
2383 /* Calling abi specific va_list type nodes. */
2387 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2391 /* Fence to use after loop using movnt. */
2392 tree x86_mfence;
2394 /* Register class used for passing given 64bit part of the argument.
2395 These represent classes as documented by the PS ABI, with the exception
2396 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2397 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2399 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2400 whenever possible (upper half does contain padding). */
2401 enum x86_64_reg_class
2402 {
2403 X86_64_NO_CLASS,
2404 X86_64_INTEGER_CLASS,
2405 X86_64_INTEGERSI_CLASS,
2406 X86_64_SSE_CLASS,
2407 X86_64_SSESF_CLASS,
2408 X86_64_SSEDF_CLASS,
2409 X86_64_SSEUP_CLASS,
2410 X86_64_X87_CLASS,
2411 X86_64_X87UP_CLASS,
2412 X86_64_COMPLEX_X87_CLASS,
2413 X86_64_MEMORY_CLASS
2414 };
2416 #define MAX_CLASSES 8
2418 /* Table of constants used by fldpi, fldln2, etc.... */
2422 \f
2427 const_tree);
2439 enum ix86_function_specific_strings
2440 {
2441 IX86_FUNCTION_SPECIFIC_ARCH,
2442 IX86_FUNCTION_SPECIFIC_TUNE,
2443 IX86_FUNCTION_SPECIFIC_MAX
2444 };
2465 \f
2466 #ifndef SUBTARGET32_DEFAULT_CPU
2468 #endif
2470 /* Whether -mtune= or -march= were specified */
2474 /* Vectorization library interface and handlers. */
2480 /* Processor target table, indexed by processor number */
2481 struct ptt
2482 {
2490 };
2492 /* This table must be in sync with enum processor_type in i386.h. */
2494 {
2520 };
2521 \f
2522 static unsigned int
2524 {
2527 /* vzeroupper instructions are inserted immediately after reload to
2528 account for possible spills from 256bit registers. The pass
2529 reuses mode switching infrastructure by re-running mode insertion
2530 pass, so disable entities that have already been processed. */
2536 /* Call optimize_mode_switching. */
2539 }
2544 {
2554 };
2557 {
2561 {}
2563 /* opt_pass methods: */
2565 {
2567 }
2570 {
2572 }
2578 rtl_opt_pass *
2580 {
2582 }
2584 /* Return true if a red-zone is in use. */
2588 {
2590 }
2591 \f
2592 /* Return a string that documents the current -m options. The caller is
2593 responsible for freeing the string. */
2599 {
2600 struct ix86_target_opts
2601 {
2604 };
2606 /* This table is ordered so that options like -msse4.2 that imply
2607 preceding options while match those first. */
2609 {
2658 };
2660 /* Flag options. */
2662 {
2691 };
2708 /* Add -march= option. */
2710 {
2713 }
2715 /* Add -mtune= option. */
2717 {
2720 }
2722 /* Add -m32/-m64/-mx32. */
2724 {
2727 else
2729 isa &= ~ (OPTION_MASK_ISA_64BIT
2730 | OPTION_MASK_ABI_64
2732 }
2733 else
2737 /* Pick out the options in isa options. */
2739 {
2741 {
2744 }
2745 }
2748 {
2751 isa);
2752 }
2754 /* Add flag options. */
2756 {
2758 {
2761 }
2762 }
2765 {
2768 }
2770 /* Add -fpmath= option. */
2772 {
2775 {
2790 }
2791 }
2793 /* Any options? */
2799 /* Size the string. */
2803 {
2808 }
2810 /* Build the string. */
2815 {
2822 {
2824 line_len++;
2827 {
2831 }
2832 }
2836 {
2840 }
2841 }
2847 }
2849 /* Return true, if profiling code should be emitted before
2850 prologue. Otherwise it returns false.
2851 Note: For x86 with "hotfix" it is sorried. */
2852 static bool
2854 {
2856 }
2858 /* Function that is callable from the debugger to print the current
2859 options. */
2860 void ATTRIBUTE_UNUSED
2862 {
2868 {
2871 }
2872 else
2876 }
2879 #define DEF_ENUM
2880 #define DEF_ALG(alg, name) #name,
2882 #undef DEF_ENUM
2883 #undef DEF_ALG
2884 };
2886 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2887 The string is of the following form (or comma separated list of it):
2889 strategy_alg:max_size:[align|noalign]
2891 where the full size range for the strategy is either [0, max_size] or
2892 [min_size, max_size], in which min_size is the max_size + 1 of the
2893 preceding range. The last size range must have max_size == -1.
2895 Examples:
2897 1.
2898 -mmemcpy-strategy=libcall:-1:noalign
2900 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2903 2.
2904 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2906 This is to tell the compiler to use the following strategy for memset
2907 1) when the expected size is between [1, 16], use rep_8byte strategy;
2908 2) when the size is between [17, 2048], use vector_loop;
2909 3) when the size is > 2048, use libcall. */
2911 struct stringop_size_range
2912 {
2914 stringop_alg alg;
2916 };
2918 static void
2920 {
2928 else
2933 do
2934 {
2944 {
2948 }
2951 {
2955 }
2962 {
2964 alg_name,
2967 }
2975 else
2976 {
2980 }
2981 n++;
2983 }
2987 {
2992 }
2995 {
2999 }
3001 /* Now override the default algs array. */
3003 {
3009 }
3010 }
3012 \f
3013 /* parse -mtune-ctrl= option. When DUMP is true,
3014 print the features that are explicitly set. */
3016 static void
3018 {
3026 do
3027 {
3034 {
3035 curr_feature_string++;
3037 }
3039 {
3041 {
3047 }
3048 }
3053 }
3056 }
3058 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3059 processor type. */
3061 static void
3063 {
3068 {
3071 else
3073 }
3076 {
3081 }
3084 }
3087 /* Override various settings based on options. If MAIN_ARGS_P, the
3088 options are from the command line, otherwise they are from
3089 attributes. */
3091 static void
3095 {
3103 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3104 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3105 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3106 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3107 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3108 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3109 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3110 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3111 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3112 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3113 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3114 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3115 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3116 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3117 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3118 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3119 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3120 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3121 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3122 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3123 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3124 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3125 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3126 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3127 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3128 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3129 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3130 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3131 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3132 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3133 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3134 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3135 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3136 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3137 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3138 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3139 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3140 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3141 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3142 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3143 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3144 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3145 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3146 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3147 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3148 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3149 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3150 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3151 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3152 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3153 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3154 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3155 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3157 #define PTA_CORE2 \
3158 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3159 | PTA_CX16 | PTA_FXSR)
3160 #define PTA_NEHALEM \
3161 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3162 #define PTA_WESTMERE \
3163 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3164 #define PTA_SANDYBRIDGE \
3165 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3166 #define PTA_IVYBRIDGE \
3167 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3168 #define PTA_HASWELL \
3169 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3170 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3171 #define PTA_BROADWELL \
3172 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3173 #define PTA_BONNELL \
3174 (PTA_CORE2 | PTA_MOVBE)
3175 #define PTA_SILVERMONT \
3176 (PTA_WESTMERE | PTA_MOVBE)
3178 /* if this reaches 64, need to widen struct pta flags below */
3180 static struct pta
3181 {
3186 }
3188 {
3222 PTA_SANDYBRIDGE},
3224 PTA_SANDYBRIDGE},
3226 PTA_IVYBRIDGE},
3228 PTA_IVYBRIDGE},
3319 PTA_64BIT
3321 };
3323 /* -mrecip options. */
3324 static struct
3325 {
3328 }
3330 {
3337 };
3341 /* Set up prefix/suffix so the error messages refer to either the command
3342 line argument, or the attribute(target). */
3344 {
3348 }
3349 else
3350 {
3354 }
3356 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3357 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3360 #ifdef TARGET_BI_ARCH
3361 else
3362 {
3363 #if TARGET_BI_ARCH == 1
3364 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3365 is on and OPTION_MASK_ABI_X32 is off. We turn off
3366 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3367 -mx32. */
3370 #else
3371 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3372 on and OPTION_MASK_ABI_64 is off. We turn off
3373 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3374 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3378 #endif
3379 }
3380 #endif
3383 {
3384 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3385 OPTION_MASK_ABI_64 for TARGET_X32. */
3388 }
3391 | OPTION_MASK_ABI_X32
3394 {
3395 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3396 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3399 }
3401 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3402 SUBTARGET_OVERRIDE_OPTIONS;
3403 #endif
3405 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3406 SUBSUBTARGET_OVERRIDE_OPTIONS;
3407 #endif
3409 /* -fPIC is the default for x86_64. */
3413 /* Need to check -mtune=generic first. */
3415 {
3416 /* As special support for cross compilers we read -mtune=native
3417 as -mtune=generic. With native compilers we won't see the
3418 -mtune=native, as it was changed by the driver. */
3420 {
3422 }
3427 }
3428 else
3429 {
3433 {
3434 opts->x_ix86_tune_string
3437 }
3439 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3440 or defaulted. We need to use a sensible tune option. */
3442 {
3444 }
3445 }
3449 {
3450 /* rep; movq isn't available in 32-bit code. */
3453 }
3456 opts->x_ix86_arch_string
3459 else
3463 {
3471 }
3472 else
3479 /* For targets using ms ABI enable ms-extensions, if not
3480 explicit turned off. For non-ms ABI we turn off this
3481 option. */
3486 {
3488 {
3532 {
3535 }
3543 }
3544 }
3545 else
3546 {
3547 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3548 use of rip-relative addressing. This eliminates fixups that
3549 would otherwise be needed if this object is to be placed in a
3550 DLL, and is essentially just as efficient as direct addressing. */
3556 else
3558 }
3560 {
3563 }
3571 {
3574 /* Default cpu tuning to the architecture. */
3740 }
3764 {
3768 {
3770 {
3772 {
3780 }
3781 else
3784 }
3785 }
3786 /* Intel CPUs have always interpreted SSE prefetch instructions as
3787 NOPs; so, we can enable SSE prefetch instructions even when
3788 -mtune (rather than -march) points us to a processor that has them.
3789 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3790 higher processors. */
3795 }
3803 #ifndef USE_IX86_FRAME_POINTER
3804 #define USE_IX86_FRAME_POINTER 0
3805 #endif
3807 #ifndef USE_X86_64_FRAME_POINTER
3808 #define USE_X86_64_FRAME_POINTER 0
3809 #endif
3811 /* Set the default values for switches whose default depends on TARGET_64BIT
3812 in case they weren't overwritten by command line options. */
3814 {
3822 opts->x_flag_unwind_tables
3826 }
3827 else
3828 {
3830 opts->x_flag_omit_frame_pointer
3836 }
3841 else
3844 /* Arrange to set up i386_stack_locals for all functions. */
3847 /* Validate -mregparm= value. */
3849 {
3853 {
3857 }
3858 }
3862 /* Default align_* from the processor table. */
3864 {
3867 }
3869 {
3872 }
3874 {
3876 }
3878 /* Provide default for -mbranch-cost= value. */
3883 {
3884 opts->x_target_flags
3887 /* Enable by default the SSE and MMX builtins. Do allow the user to
3888 explicitly disable any of these. In particular, disabling SSE and
3889 MMX for kernel code is extremely useful. */
3891 opts->x_ix86_isa_flags
3898 }
3899 else
3900 {
3901 opts->x_target_flags
3905 opts->x_ix86_isa_flags
3908 /* i386 ABI does not specify red zone. It still makes sense to use it
3909 when programmer takes care to stack from being destroyed. */
3912 }
3914 /* Keep nonleaf frame pointers. */
3920 /* If we're doing fast math, we don't care about comparison order
3921 wrt NaNs. This lets us use a shorter comparison sequence. */
3925 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3926 since the insns won't need emulation. */
3930 /* Likewise, if the target doesn't have a 387, or we've specified
3931 software floating point, don't use 387 inline intrinsics. */
3935 /* Turn on MMX builtins for -msse. */
3937 opts->x_ix86_isa_flags
3940 /* Enable SSE prefetch. */
3945 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3948 opts->x_ix86_isa_flags
3951 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3954 opts->x_ix86_isa_flags
3957 /* Enable lzcnt instruction for -mabm. */
3959 opts->x_ix86_isa_flags
3962 /* Validate -mpreferred-stack-boundary= value or default it to
3963 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3966 {
3973 {
3977 else
3980 }
3981 else
3982 ix86_preferred_stack_boundary
3984 }
3986 /* Set the default value for -mstackrealign. */
3992 /* Validate -mincoming-stack-boundary= value or default it to
3993 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3996 {
4003 else
4004 {
4005 ix86_user_incoming_stack_boundary
4007 ix86_incoming_stack_boundary
4009 }
4010 }
4012 #ifndef NO_PROFILE_COUNTERS
4015 #endif
4019 /* Accept -msseregparm only if at least SSE support is enabled. */
4025 {
4027 {
4029 {
4032 }
4035 {
4038 }
4039 }
4040 }
4041 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4042 fpmath=387. The second is however default at many targets since the
4043 extra 80bit precision of temporaries is considered to be part of ABI.
4044 Overwrite the default at least for -ffast-math.
4045 TODO: -mfpmath=both seems to produce same performing code with bit
4046 smaller binaries. It is however not clear if register allocation is
4047 ready for this setting.
4048 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4049 codegen. We may switch to 387 with -ffast-math for size optimized
4050 functions. */
4054 else
4057 /* If the i387 is disabled, then do not return values in it. */
4061 /* Use external vectorized library in vectorizing intrinsics. */
4064 {
4075 }
4082 /* If stack probes are required, the space used for large function
4083 arguments on the stack must also be probed, so enable
4084 -maccumulate-outgoing-args so this happens in the prologue. */
4087 {
4092 }
4094 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4095 {
4101 }
4103 /* When scheduling description is not available, disable scheduler pass
4104 so it won't slow down the compilation and make x87 code slower. */
4125 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4127 && HAVE_prefetch
4132 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4133 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4138 {
4141 {
4143 ix86_gen_tls_local_dynamic_base_64
4145 }
4146 else
4147 {
4149 ix86_gen_tls_local_dynamic_base_64
4151 }
4152 }
4153 else
4157 {
4167 }
4168 else
4169 {
4179 }
4181 #ifdef USE_IX86_CLD
4182 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4185 #endif
4188 {
4193 }
4195 {
4199 }
4201 {
4202 #if defined(PROFILE_BEFORE_PROLOGUE)
4204 #else
4206 #endif
4207 }
4209 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4210 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4211 AVX unaligned load/store. */
4213 {
4223 /* Enable 128-bit AVX instruction generation
4224 for the auto-vectorizer. */
4228 }
4231 {
4238 {
4241 {
4243 q++;
4244 }
4245 else
4250 else
4251 {
4254 {
4257 }
4260 {
4264 }
4265 }
4270 else
4272 }
4273 }
4280 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4281 for 64-bit Bionic. */
4286 ? MASK_LONG_DOUBLE_128
4289 /* Only one of them can be active. */
4293 /* Save the initial options in case the user does function specific
4294 options. */
4296 target_option_default_node = target_option_current_node
4299 /* Handle stack protector */
4301 opts->x_ix86_stack_protector_guard
4304 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4306 {
4310 }
4313 {
4317 }
4318 }
4320 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4322 static void
4324 {
4326 static struct register_pass_info insert_vzeroupper_info
4329 };
4334 /* This needs to be done at start up. It's convenient to do it here. */
4336 }
4338 /* Update register usage after having seen the compiler flags. */
4340 static void
4342 {
4346 /* The PIC register, if it exists, is fixed. */
4351 /* For 32-bit targets, squash the REX registers. */
4353 {
4360 }
4362 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4370 {
4371 /* Set/reset conditionally defined registers from
4372 CALL_USED_REGISTERS initializer. */
4376 /* Calculate registers of CLOBBERED_REGS register set
4377 as call used registers from GENERAL_REGS register set. */
4381 }
4383 /* If MMX is disabled, squash the registers. */
4389 /* If SSE is disabled, squash the registers. */
4395 /* If the FPU is disabled, squash the registers. */
4401 /* If AVX512F is disabled, squash the registers. */
4403 {
4409 }
4411 /* If MPX is disabled, squash the registers. */
4415 }
4417 \f
4418 /* Save the current options */
4420 static void
4423 {
4458 /* The fields are char but the variables are not; make sure the
4459 values fit in the fields. */
4464 }
4466 /* Restore the current options */
4468 static void
4471 {
4477 /* We don't change -fPIC. */
4514 /* Recreate the arch feature tests if the arch changed */
4516 {
4521 }
4523 /* Recreate the tune optimization tests */
4526 }
4528 /* Print the current options */
4530 static void
4533 {
4551 {
4554 }
4555 }
4557 \f
4558 /* Inner function to process the attribute((target(...))), take an argument and
4559 set the current options from the argument. If we have a list, recursively go
4560 over the list. */
4562 static bool
4567 {
4571 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4572 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4573 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4574 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4575 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4577 enum ix86_opt_type
4578 {
4579 ix86_opt_unknown,
4580 ix86_opt_yes,
4581 ix86_opt_no,
4582 ix86_opt_str,
4583 ix86_opt_enum,
4584 ix86_opt_isa
4585 };
4587 static const struct
4588 {
4595 /* isa options */
4644 /* enum options */
4647 /* string options */
4651 /* flag options */
4653 OPT_mcld,
4654 MASK_CLD),
4657 OPT_mfancy_math_387,
4658 MASK_NO_FANCY_MATH_387),
4661 OPT_mieee_fp,
4662 MASK_IEEE_FP),
4665 OPT_minline_all_stringops,
4666 MASK_INLINE_ALL_STRINGOPS),
4669 OPT_minline_stringops_dynamically,
4670 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4673 OPT_mno_align_stringops,
4674 MASK_NO_ALIGN_STRINGOPS),
4677 OPT_mrecip,
4678 MASK_RECIP),
4680 };
4682 /* If this is a list, recurse to get the options. */
4684 {
4691 enum_opts_set))
4695 }
4698 {
4701 }
4703 /* Handle multiple arguments separated by commas. */
4707 {
4721 {
4725 }
4726 else
4727 {
4730 }
4732 /* Recognize no-xxx. */
4734 {
4738 }
4739 else
4742 /* Find the option. */
4746 {
4754 {
4759 }
4760 }
4762 /* Process the option. */
4764 {
4767 }
4770 {
4776 }
4779 {
4785 else
4787 }
4790 {
4792 {
4795 }
4796 else
4798 }
4801 {
4809 global_dc);
4810 else
4811 {
4814 }
4815 }
4817 else
4819 }
4822 }
4824 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4826 tree
4830 {
4845 /* Process each of the options on the chain. */
4850 /* If the changed options are different from the default, rerun
4851 ix86_option_override_internal, and then save the options away.
4852 The string options are are attribute options, and will be undone
4853 when we copy the save structure. */
4859 {
4860 /* If we are using the default tune= or arch=, undo the string assigned,
4861 and use the default. */
4872 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4877 {
4880 }
4882 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4885 /* Add any builtin functions with the new isa if any. */
4888 /* Save the current options unless we are validating options for
4889 #pragma. */
4896 /* Free up memory allocated to hold the strings */
4899 }
4902 }
4904 /* Hook to validate attribute((target("string"))). */
4906 static bool
4909 tree args,
4911 {
4916 /* attribute((target("default"))) does nothing, beyond
4917 affecting multi-versioning. */
4926 /* Get the optimization options of the current function. */
4932 /* Init func_options. */
4940 /* Initialize func_options to the default before its target options can
4941 be set. */
4954 {
4959 }
4962 }
4964 \f
4965 /* Hook to determine if one function can safely inline another. */
4967 static bool
4969 {
4974 /* If callee has no option attributes, then it is ok to inline. */
4978 /* If caller has no option attributes, but callee does then it is not ok to
4979 inline. */
4983 else
4984 {
4988 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4989 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4990 function. */
4995 /* See if we have the same non-isa options. */
4999 /* See if arch, tune, etc. are the same. */
5012 else
5014 }
5017 }
5019 \f
5020 /* Remember the last target of ix86_set_current_function. */
5023 /* Invalidate ix86_previous_fndecl cache. */
5024 void
5026 {
5028 }
5030 /* Establish appropriate back-end context for processing the function
5031 FNDECL. The argument might be NULL to indicate processing at top
5032 level, outside of any function scope. */
5033 static void
5035 {
5036 /* Only change the context if the function changes. This hook is called
5037 several times in the course of compiling a function, and we don't want to
5038 slow things down too much or call target_reinit when it isn't safe. */
5040 {
5041 tree old_tree = (ix86_previous_fndecl
5045 tree new_tree = (fndecl
5051 ;
5054 {
5059 else
5062 }
5065 {
5073 else
5076 }
5077 }
5078 }
5080 \f
5081 /* Return true if this goes in large data/bss. */
5083 static bool
5085 {
5089 /* Functions are never large data. */
5093 /* Automatic variables are never large data. */
5098 {
5104 }
5105 else
5106 {
5109 /* If this is an incomplete type with size 0, then we can't put it
5110 in data because it might be too big when completed. Also,
5111 int_size_in_bytes returns -1 if size can vary or is larger than
5112 an integer in which case also it is safer to assume that it goes in
5113 large data. */
5116 }
5119 }
5121 /* Switch to the appropriate section for output of DECL.
5122 DECL is either a `VAR_DECL' node or a constant of some sort.
5123 RELOC indicates whether forming the initial value of DECL requires
5124 link-time relocations. */
5129 {
5131 {
5135 {
5169 /* We don't split these for medium model. Place them into
5170 default sections and hope for best. */
5172 }
5174 {
5175 /* We might get called with string constants, but get_named_section
5176 doesn't like them as they are not DECLs. Also, we need to set
5177 flags in that case. */
5181 }
5182 }
5184 }
5186 /* Select a set of attributes for section NAME based on the properties
5187 of DECL and whether or not RELOC indicates that DECL's initializer
5188 might contain runtime relocations. */
5190 static unsigned int ATTRIBUTE_UNUSED
5192 {
5206 }
5208 /* Build up a unique section name, expressed as a
5209 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5210 RELOC indicates whether the initial value of EXP requires
5211 link-time relocations. */
5213 static void ATTRIBUTE_UNUSED
5215 {
5217 {
5219 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5223 {
5247 /* We don't split these for medium model. Place them into
5248 default sections and hope for best. */
5250 }
5252 {
5259 /* If we're using one_only, then there needs to be a .gnu.linkonce
5260 prefix to the section name. */
5267 }
5268 }
5270 }
5272 #ifdef COMMON_ASM_OP
5273 /* This says how to output assembler code to declare an
5274 uninitialized external linkage data object.
5276 For medium model x86-64 we need to use .largecomm opcode for
5277 large objects. */
5278 void
5282 {
5286 else
5291 }
5292 #endif
5294 /* Utility function for targets to use in implementing
5295 ASM_OUTPUT_ALIGNED_BSS. */
5297 void
5300 {
5304 else
5307 #ifdef ASM_DECLARE_OBJECT_NAME
5310 #else
5311 /* Standard thing is just output label for the object. */
5315 }
5316 \f
5317 /* Decide whether we must probe the stack before any space allocation
5318 on this target. It's essentially TARGET_STACK_PROBE except when
5319 -fstack-check causes the stack to be already probed differently. */
5321 bool
5323 {
5324 /* Do not probe the stack twice if static stack checking is enabled. */
5329 }
5330 \f
5331 /* Decide whether we can make a sibling call to a function. DECL is the
5332 declaration of the function being targeted by the call and EXP is the
5333 CALL_EXPR representing the call. */
5335 static bool
5337 {
5341 /* If we are generating position-independent code, we cannot sibcall
5342 optimize any indirect call, or a direct call to a global function,
5343 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5345 && !TARGET_64BIT
5346 && flag_pic
5350 /* If we need to align the outgoing stack, then sibcalling would
5351 unalign the stack, which may break the called function. */
5357 {
5360 }
5361 else
5362 {
5363 /* We're looking at the CALL_EXPR, we need the type of the function. */
5368 }
5370 /* Check that the return value locations are the same. Like
5371 if we are returning floats on the 80387 register stack, we cannot
5372 make a sibcall from a function that doesn't return a float to a
5373 function that does or, conversely, from a function that does return
5374 a float to a function that doesn't; the necessary stack adjustment
5375 would not be executed. This is also the place we notice
5376 differences in the return value ABI. Note that it is ok for one
5377 of the functions to have void return type as long as the return
5378 value of the other is passed in a register. */
5383 {
5386 }
5388 ;
5393 {
5394 /* The SYSV ABI has more call-clobbered registers;
5395 disallow sibcalls from MS to SYSV. */
5399 }
5400 else
5401 {
5402 /* If this call is indirect, we'll need to be able to use a
5403 call-clobbered register for the address of the target function.
5404 Make sure that all such registers are not used for passing
5405 parameters. Note that DLLIMPORT functions are indirect. */
5408 {
5410 {
5411 /* ??? Need to count the actual number of registers to be used,
5412 not the possible number of registers. Fix later. */
5414 }
5415 }
5416 }
5418 /* Otherwise okay. That also includes certain types of indirect calls. */
5420 }
5422 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5423 and "sseregparm" calling convention attributes;
5424 arguments as in struct attribute_spec.handler. */
5426 static tree
5428 tree args,
5431 {
5436 {
5438 name);
5441 }
5443 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5445 {
5446 tree cst;
5449 {
5451 }
5454 {
5456 }
5460 {
5463 name);
5465 }
5467 {
5471 }
5474 }
5477 {
5478 /* Do not warn when emulating the MS ABI. */
5483 name);
5486 }
5488 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5490 {
5492 {
5494 }
5496 {
5498 }
5500 {
5502 }
5504 {
5506 }
5507 }
5509 /* Can combine stdcall with fastcall (redundant), regparm and
5510 sseregparm. */
5512 {
5514 {
5516 }
5518 {
5520 }
5522 {
5524 }
5525 }
5527 /* Can combine cdecl with regparm and sseregparm. */
5529 {
5531 {
5533 }
5535 {
5537 }
5539 {
5541 }
5542 }
5544 {
5547 name);
5549 {
5551 }
5553 {
5555 }
5557 {
5559 }
5560 }
5562 /* Can combine sseregparm with all attributes. */
5565 }
5567 /* The transactional memory builtins are implicitly regparm or fastcall
5568 depending on the ABI. Override the generic do-nothing attribute that
5569 these builtins were declared with, and replace it with one of the two
5570 attributes that we expect elsewhere. */
5572 static tree
5575 {
5576 tree alt;
5578 /* In no case do we want to add the placeholder attribute. */
5581 /* The 64-bit ABI is unchanged for transactional memory. */
5585 /* ??? Is there a better way to validate 32-bit windows? We have
5586 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5589 else
5590 {
5593 }
5597 }
5599 /* This function determines from TYPE the calling-convention. */
5601 unsigned int
5603 {
5606 tree attrs;
5613 {
5623 /* Regparam isn't allowed for thiscall and fastcall. */
5625 {
5630 }
5634 }
5641 || is_stdarg
5647 }
5649 /* Return 0 if the attributes for two types are incompatible, 1 if they
5650 are compatible, and 2 if they are nearly compatible (which causes a
5651 warning to be generated). */
5653 static int
5655 {
5671 }
5672 \f
5673 /* Return the regparm value for a function with the indicated TYPE and DECL.
5674 DECL may be NULL when calling function indirectly
5675 or considering a libcall. */
5677 static int
5679 {
5680 tree attr;
5691 {
5694 {
5697 }
5698 }
5704 /* Use register calling convention for local functions when possible. */
5707 /* Caller and callee must agree on the calling convention, so
5708 checking here just optimize means that with
5709 __attribute__((optimize (...))) caller could use regparm convention
5710 and callee not, or vice versa. Instead look at whether the callee
5711 is optimized or not. */
5714 {
5715 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5718 {
5721 /* Make sure no regparm register is taken by a
5722 fixed register variable. */
5727 /* We don't want to use regparm(3) for nested functions as
5728 these use a static chain pointer in the third argument. */
5732 /* In 32-bit mode save a register for the split stack. */
5736 /* Each fixed register usage increases register pressure,
5737 so less registers should be used for argument passing.
5738 This functionality can be overriden by an explicit
5739 regparm value. */
5742 globals++;
5744 local_regparm
5749 }
5750 }
5753 }
5755 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5756 DFmode (2) arguments in SSE registers for a function with the
5757 indicated TYPE and DECL. DECL may be NULL when calling function
5758 indirectly or considering a libcall. Otherwise return 0. */
5760 static int
5762 {
5765 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5766 by the sseregparm attribute. */
5769 {
5771 {
5773 {
5777 else
5780 }
5782 }
5785 }
5787 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5788 (and DFmode for SSE2) arguments in SSE registers. */
5791 {
5792 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5796 }
5799 }
5801 /* Return true if EAX is live at the start of the function. Used by
5802 ix86_expand_prologue to determine if we need special help before
5803 calling allocate_stack_worker. */
5805 static bool
5807 {
5808 /* Cheat. Don't bother working forward from ix86_function_regparm
5809 to the function type to whether an actual argument is located in
5810 eax. Instead just look at cfg info, which is still close enough
5811 to correct at this point. This gives false positives for broken
5812 functions that might use uninitialized data that happens to be
5813 allocated in eax, but who cares? */
5815 }
5817 static bool
5819 {
5820 tree attr;
5823 {
5829 /* For 32-bit MS-ABI the default is to keep aggregate
5830 return pointer. */
5833 }
5835 }
5837 /* Value is the number of bytes of arguments automatically
5838 popped when returning from a subroutine call.
5839 FUNDECL is the declaration node of the function (as a tree),
5840 FUNTYPE is the data type of the function (as a tree),
5841 or for a library call it is an identifier node for the subroutine name.
5842 SIZE is the number of bytes of arguments passed on the stack.
5844 On the 80386, the RTD insn may be used to pop them if the number
5845 of args is fixed, but if the number is variable then the caller
5846 must pop them all. RTD can't be used for library calls now
5847 because the library is compiled with the Unix compiler.
5848 Use of RTD is a selectable option, since it is incompatible with
5849 standard Unix calling sequences. If the option is not selected,
5850 the caller must always pop the args.
5852 The attribute stdcall is equivalent to RTD on a per module basis. */
5854 static int
5856 {
5859 /* None of the 64-bit ABIs pop arguments. */
5870 /* Lose any fake structure return argument if it is passed on the stack. */
5873 {
5877 }
5880 }
5882 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5884 static bool
5886 {
5887 /* Check operand constraints in case hard registers were propagated
5888 into insn pattern. This check prevents combine pass from
5889 generating insn patterns with invalid hard register operands.
5890 These invalid insns can eventually confuse reload to error out
5891 with a spill failure. See also PRs 46829 and 46843. */
5893 {
5902 {
5910 /* For pre-AVX disallow unaligned loads/stores where the
5911 instructions don't support it. */
5915 {
5919 }
5921 /* A unary operator may be accepted by the predicate, but it
5922 is irrelevant for matching constraints. */
5927 {
5935 }
5942 /* Operand has no constraints, anything is OK. */
5947 {
5952 && operands_match_p
5956 {
5959 }
5960 }
5964 }
5965 }
5968 }
5969 \f
5970 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5972 static unsigned HOST_WIDE_INT
5974 {
5978 }
5979 \f
5980 /* Argument support functions. */
5982 /* Return true when register may be used to pass function parameters. */
5983 bool
5985 {
5990 {
5994 else
6000 }
6006 /* TODO: The function should depend on current function ABI but
6007 builtins.c would need updating then. Therefore we use the
6008 default ABI. */
6010 /* RAX is used as hidden argument to va_arg functions. */
6016 else
6023 }
6025 /* Return if we do not know how to pass TYPE solely in registers. */
6027 static bool
6029 {
6033 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6034 The layout_type routine is crafty and tries to trick us into passing
6035 currently unsupported vector types on the stack by using TImode. */
6038 }
6040 /* It returns the size, in bytes, of the area reserved for arguments passed
6041 in registers for the function represented by fndecl dependent to the used
6042 abi format. */
6043 int
6045 {
6049 else
6054 }
6056 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6057 call abi used. */
6058 enum calling_abi
6060 {
6062 {
6065 {
6068 }
6072 }
6074 }
6076 /* We add this as a workaround in order to use libc_has_function
6077 hook in i386.md. */
6078 bool
6080 {
6082 }
6084 static bool
6086 {
6088 {
6092 else
6094 }
6096 }
6098 static enum calling_abi
6100 {
6104 }
6106 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6107 call abi used. */
6108 enum calling_abi
6110 {
6114 }
6116 /* Write the extra assembler code needed to declare a function properly. */
6118 void
6120 tree decl)
6121 {
6125 {
6131 }
6133 #ifdef SUBTARGET_ASM_UNWIND_INIT
6135 #endif
6139 /* Output magic byte marker, if hot-patch attribute is set. */
6141 {
6143 {
6144 /* leaq [%rsp + 0], %rsp */
6147 }
6148 else
6149 {
6150 /* movl.s %edi, %edi
6151 push %ebp
6152 movl.s %esp, %ebp */
6155 }
6156 }
6157 }
6159 /* regclass.c */
6162 /* Implementation of call abi switching target hook. Specific to FNDECL
6163 the specific call register sets are set. See also
6164 ix86_conditional_register_usage for more details. */
6165 void
6167 {
6170 else
6172 }
6174 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6175 expensive re-initialization of init_regs each time we switch function context
6176 since this is needed only during RTL expansion. */
6177 static void
6179 {
6183 }
6185 /* Return 1 if pseudo register should be created and used to hold
6186 GOT address for PIC code. */
6187 static bool
6189 {
6196 }
6198 /* Create and initialize PIC register if required. */
6199 static void
6201 {
6202 edge entry_edge;
6211 {
6213 {
6215 rtx tmp_reg;
6224 label));
6228 }
6229 else
6231 }
6232 else
6233 {
6234 /* If there is future mcount call in the function it is more profitable
6235 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6244 }
6252 }
6254 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6255 for a call to a function whose data type is FNTYPE.
6256 For a library call, FNTYPE is 0. */
6258 void
6262 tree fndecl,
6264 {
6270 {
6273 }
6274 else
6275 {
6278 }
6282 /* Set up the number of registers to use for passing arguments. */
6285 {
6287 ? X86_64_REGPARM_MAX
6289 }
6291 {
6294 {
6296 ? X86_64_SSE_REGPARM_MAX
6298 }
6299 }
6307 /* Because type might mismatch in between caller and callee, we need to
6308 use actual type of function for local calls.
6309 FIXME: cgraph_analyze can be told to actually record if function uses
6310 va_start so for local functions maybe_vaarg can be made aggressive
6311 helping K&R code.
6312 FIXME: once typesytem is fixed, we won't need this code anymore. */
6325 {
6326 /* If there are variable arguments, then we won't pass anything
6327 in registers in 32-bit mode. */
6329 {
6338 }
6340 /* Use ecx and edx registers if function has fastcall attribute,
6341 else look for regparm information. */
6343 {
6346 {
6349 }
6351 {
6354 }
6355 else
6357 }
6359 /* Set up the number of SSE registers used for passing SFmode
6360 and DFmode arguments. Warn for mismatching ABI. */
6362 }
6363 }
6365 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6366 But in the case of vector types, it is some vector mode.
6368 When we have only some of our vector isa extensions enabled, then there
6369 are some modes for which vector_mode_supported_p is false. For these
6370 modes, the generic vector support in gcc will choose some non-vector mode
6371 in order to implement the type. By computing the natural mode, we'll
6372 select the proper ABI location for the operand and not depend on whatever
6373 the middle-end decides to do with these vector types.
6375 The midde-end can't deal with the vector types > 16 bytes. In this
6376 case, we return the original mode and warn ABI change if CUM isn't
6377 NULL.
6379 If INT_RETURN is true, warn ABI change if the vector mode isn't
6380 available for function return value. */
6382 static machine_mode
6385 {
6389 {
6392 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6394 {
6399 else
6402 /* Get the mode which has this inner mode and number of units. */
6406 {
6408 {
6413 {
6417 }
6419 {
6423 }
6426 }
6428 {
6433 {
6437 }
6439 {
6443 }
6446 }
6449 {
6454 {
6458 }
6460 {
6464 }
6465 }
6467 {
6472 {
6476 }
6478 {
6482 }
6483 }
6485 }
6488 }
6489 }
6492 }
6494 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6495 this may not agree with the mode that the type system has chosen for the
6496 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6497 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6499 static rtx
6502 {
6503 rtx tmp;
6507 else
6508 {
6512 }
6515 }
6517 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6518 of this code is to classify each 8bytes of incoming argument by the register
6519 class and assign registers accordingly. */
6521 /* Return the union class of CLASS1 and CLASS2.
6522 See the x86-64 PS ABI for details. */
6524 static enum x86_64_reg_class
6526 {
6527 /* Rule #1: If both classes are equal, this is the resulting class. */
6531 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6532 the other class. */
6538 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6542 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6550 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6551 MEMORY is used. */
6560 /* Rule #6: Otherwise class SSE is used. */
6562 }
6564 /* Classify the argument of type TYPE and mode MODE.
6565 CLASSES will be filled by the register class used to pass each word
6566 of the operand. The number of words is returned. In case the parameter
6567 should be passed in memory, 0 is returned. As a special case for zero
6568 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6570 BIT_OFFSET is used internally for handling records and specifies offset
6571 of the offset in bits modulo 512 to avoid overflow cases.
6573 See the x86-64 PS ABI for details.
6574 */
6576 static int
6579 {
6580 HOST_WIDE_INT bytes =
6582 int words
6585 /* Variable sized entities are always passed/returned in memory. */
6594 {
6596 tree field;
6599 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6606 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6607 signalize memory class, so handle it as special case. */
6609 {
6612 }
6614 /* Classify each field of record and merge classes. */
6616 {
6618 /* And now merge the fields of structure. */
6620 {
6622 {
6628 /* Bitfields are always classified as integer. Handle them
6629 early, since later code would consider them to be
6630 misaligned integers. */
6632 {
6641 }
6642 else
6643 {
6648 /* Flexible array member is ignored. */
6655 {
6659 {
6662 "the ABI of passing struct with"
6663 " a flexible array member has"
6665 }
6667 }
6669 subclasses,
6679 }
6680 }
6681 }
6685 /* Arrays are handled as small records. */
6686 {
6693 /* The partial classes are now full classes. */
6704 }
6707 /* Unions are similar to RECORD_TYPE but offset is always 0.
6708 */
6710 {
6712 {
6720 bit_offset);
6725 }
6726 }
6731 }
6734 {
6735 /* When size > 16 bytes, if the first one isn't
6736 X86_64_SSE_CLASS or any other ones aren't
6737 X86_64_SSEUP_CLASS, everything should be passed in
6738 memory. */
6745 }
6747 /* Final merger cleanup. */
6749 {
6750 /* If one class is MEMORY, everything should be passed in
6751 memory. */
6755 /* The X86_64_SSEUP_CLASS should be always preceded by
6756 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6760 {
6761 /* The first one should never be X86_64_SSEUP_CLASS. */
6764 }
6766 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6767 everything should be passed in memory. */
6770 {
6773 /* The first one should never be X86_64_X87UP_CLASS. */
6776 {
6779 "the ABI of passing union with long double"
6781 }
6783 }
6784 }
6786 }
6788 /* Compute alignment needed. We align all types to natural boundaries with
6789 exception of XFmode that is aligned to 64bits. */
6791 {
6800 /* Misaligned fields are always returned in memory. */
6803 }
6805 /* for V1xx modes, just use the base mode */
6810 /* Classification of atomic types. */
6812 {
6828 {
6831 /* Analyze last 128 bits only. */
6835 {
6838 }
6840 {
6843 }
6845 {
6849 }
6851 {
6854 }
6855 else
6857 }
6864 /* OImode shouldn't be used directly. */
6871 else
6889 else
6890 {
6894 {
6897 "the ABI of passing structure with complex float"
6899 }
6902 }
6911 /* This modes is larger than 16 bytes. */
6969 else
6973 }
6974 }
6976 /* Examine the argument and return set number of register required in each
6977 class. Return true iff parameter should be passed in memory. */
6979 static bool
6982 {
6993 {
7014 }
7017 }
7019 /* Construct container for the argument used by GCC interface. See
7020 FUNCTION_ARG for the detailed description. */
7022 static rtx
7026 {
7027 /* The following variables hold the static issued_error state. */
7032 machine_mode tmpmode;
7041 rtx ret;
7052 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7053 some less clueful developer tries to use floating-point anyway. */
7055 {
7057 {
7059 {
7062 }
7063 }
7065 {
7068 }
7070 }
7072 /* Likewise, error if the ABI requires us to return values in the
7073 x87 registers and the user specified -mno-80387. */
7079 {
7081 {
7084 }
7086 }
7088 /* First construct simple cases. Avoid SCmode, since we want to use
7089 single register to pass this type. */
7092 {
7107 /* Zero sized array, struct or class. */
7111 }
7150 /* Otherwise figure out the entries of the PARALLEL. */
7152 {
7156 {
7161 /* Merge TImodes on aligned occasions here too. */
7163 tmpmode
7167 else
7169 /* We've requested 24 bytes we
7170 don't have mode for. Use DImode. */
7177 intreg++;
7185 sse_regno++;
7193 sse_regno++;
7198 {
7204 {
7206 i++;
7207 }
7208 else
7233 }
7239 sse_regno++;
7243 }
7244 }
7246 /* Empty aligned struct, union or class. */
7254 }
7256 /* Update the data in CUM to advance over an argument of mode MODE
7257 and data type TYPE. (TYPE is null for libcalls where that information
7258 may not be available.)
7260 Return a number of integer regsiters advanced over. */
7262 static int
7265 HOST_WIDE_INT words)
7266 {
7270 {
7277 /* FALLTHRU */
7289 {
7292 }
7296 /* OImode shouldn't be used directly. */
7305 /* FALLTHRU */
7327 {
7332 {
7335 }
7336 }
7346 {
7351 {
7354 }
7355 }
7357 }
7360 }
7362 static int
7365 {
7368 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7375 {
7381 }
7382 else
7383 {
7388 }
7389 }
7391 static int
7393 HOST_WIDE_INT words)
7394 {
7395 /* Otherwise, this should be passed indirect. */
7400 {
7404 }
7406 }
7408 /* Update the data in CUM to advance over an argument of mode MODE and
7409 data type TYPE. (TYPE is null for libcalls where that information
7410 may not be available.) */
7412 static void
7415 {
7422 else
7431 {
7432 /* If we pass bounds in BT then just update remained bounds count. */
7434 {
7437 }
7439 /* Update remained number of bounds to force. */
7446 }
7448 /* The first arg not going to Bounds Tables resets this counter. */
7450 /* For unnamed args we always pass bounds to avoid bounds mess when
7451 passed and received types do not match. If bounds do not follow
7452 unnamed arg, still pretend required number of bounds were passed. */
7454 {
7457 }
7463 else
7466 /* For stdarg we expect bounds to be passed for each value passed
7467 in register. */
7470 /* For pointers passed in memory we expect bounds passed in Bounds
7471 Table. */
7474 }
7476 /* Define where to put the arguments to a function.
7477 Value is zero to push the argument on the stack,
7478 or a hard register in which to store the argument.
7480 MODE is the argument's machine mode.
7481 TYPE is the data type of the argument (as a tree).
7482 This is null for libcalls where that information may
7483 not be available.
7484 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7485 the preceding args and about the function being called.
7486 NAMED is nonzero if this argument is a named parameter
7487 (otherwise it is an extra parameter matching an ellipsis). */
7489 static rtx
7493 {
7494 /* Avoid the AL settings for the Unix64 ABI. */
7499 {
7506 /* FALLTHRU */
7512 {
7515 /* Fastcall allocates the first two DWORD (SImode) or
7516 smaller arguments to ECX and EDX if it isn't an
7517 aggregate type . */
7519 {
7525 /* ECX not EAX is the first allocated register. */
7528 }
7530 }
7539 /* FALLTHRU */
7541 /* In 32bit, we pass TImode in xmm registers. */
7549 {
7553 }
7558 /* OImode and XImode shouldn't be used directly. */
7574 {
7578 }
7588 {
7592 }
7594 }
7597 }
7599 static rtx
7602 {
7603 /* Handle a hidden AL argument containing number of registers
7604 for varargs x86-64 functions. */
7608 ? X86_64_SSE_REGPARM_MAX
7613 {
7629 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7633 }
7639 }
7641 static rtx
7644 HOST_WIDE_INT bytes)
7645 {
7648 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7649 We use value of -2 to specify that current function call is MSABI. */
7653 /* If we've run out of registers, it goes on the stack. */
7659 /* Only floating point modes are passed in anything but integer regs. */
7661 {
7664 else
7665 {
7668 /* Unnamed floating parameters are passed in both the
7669 SSE and integer registers. */
7675 }
7676 }
7677 /* Handle aggregated types passed in register. */
7679 {
7684 }
7687 }
7689 /* Return where to put the arguments to a function.
7690 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7692 MODE is the argument's machine mode. TYPE is the data type of the
7693 argument. It is null for libcalls where that information may not be
7694 available. CUM gives information about the preceding args and about
7695 the function being called. NAMED is nonzero if this argument is a
7696 named parameter (otherwise it is an extra parameter matching an
7697 ellipsis). */
7699 static rtx
7702 {
7706 rtx arg;
7708 /* All pointer bounds argumntas are handled separately here. */
7711 {
7712 /* Return NULL if bounds are forced to go in Bounds Table. */
7715 /* Return the next available bound reg if any. */
7718 /* Return the next special slot number otherwise. */
7719 else
7723 }
7727 else
7731 /* To simplify the code below, represent vector types with a vector mode
7732 even if MMX/SSE are not active. */
7740 else
7744 }
7746 /* A C expression that indicates when an argument must be passed by
7747 reference. If nonzero for an argument, a copy of that argument is
7748 made in memory and a pointer to the argument is passed instead of
7749 the argument itself. The pointer is passed in whatever way is
7750 appropriate for passing a pointer to that type. */
7752 static bool
7755 {
7758 /* See Windows x64 Software Convention. */
7760 {
7763 {
7764 /* Arrays are passed by reference. */
7769 {
7770 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7771 are passed by reference. */
7773 }
7774 }
7776 /* __m128 is passed by reference. */
7782 }
7783 }
7788 }
7790 /* Return true when TYPE should be 128bit aligned for 32bit argument
7791 passing ABI. XXX: This function is obsolete and is only used for
7792 checking psABI compatibility with previous versions of GCC. */
7794 static bool
7796 {
7808 {
7809 /* Walk the aggregates recursively. */
7811 {
7815 {
7816 tree field;
7818 /* Walk all the structure fields. */
7820 {
7824 }
7826 }
7829 /* Just for use if some languages passes arrays by value. */
7836 }
7837 }
7839 }
7841 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7842 XXX: This function is obsolete and is only used for checking psABI
7843 compatibility with previous versions of GCC. */
7845 static unsigned int
7848 {
7849 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7850 natural boundaries. */
7852 {
7853 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7854 make an exception for SSE modes since these require 128bit
7855 alignment.
7857 The handling here differs from field_alignment. ICC aligns MMX
7858 arguments to 4 byte boundaries, while structure fields are aligned
7859 to 8 byte boundaries. */
7861 {
7864 }
7865 else
7866 {
7869 }
7870 }
7874 }
7876 /* Return true when TYPE should be 128bit aligned for 32bit argument
7877 passing ABI. */
7879 static bool
7881 {
7891 {
7892 /* Walk the aggregates recursively. */
7894 {
7898 {
7899 tree field;
7901 /* Walk all the structure fields. */
7903 field;
7905 {
7909 }
7911 }
7914 /* Just for use if some languages passes arrays by value. */
7921 }
7922 }
7923 else
7927 }
7929 /* Gives the alignment boundary, in bits, of an argument with the
7930 specified mode and type. */
7932 static unsigned int
7934 {
7937 {
7938 /* Since the main variant type is used for call, we convert it to
7939 the main variant type. */
7942 }
7943 else
7947 else
7948 {
7953 {
7954 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7956 {
7959 }
7965 }
7968 && !warned
7970 saved_align))
7971 {
7974 "The ABI for passing parameters with %d-byte"
7977 }
7978 }
7981 }
7983 /* Return true if N is a possible register number of function value. */
7985 static bool
7987 {
7989 {
8001 /* Complex values are returned in %st(0)/%st(1) pair. */
8004 /* TODO: The function should depend on current function ABI but
8005 builtins.c would need updating then. Therefore we use the
8006 default ABI. */
8011 /* Complex values are returned in %xmm0/%xmm1 pair. */
8020 }
8023 }
8025 /* Define how to find the value returned by a function.
8026 VALTYPE is the data type of the value (as a tree).
8027 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8028 otherwise, FUNC is 0. */
8030 static rtx
8033 {
8036 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8037 we normally prevent this case when mmx is not available. However
8038 some ABIs may require the result to be returned like DImode. */
8042 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8043 we prevent this case when sse is not available. However some ABIs
8044 may require the result to be returned like integer TImode. */
8049 /* 32-byte vector modes in %ymm0. */
8053 /* 64-byte vector modes in %zmm0. */
8057 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8060 else
8061 /* Most things go in %eax. */
8064 /* Override FP return register with %xmm0 for local functions when
8065 SSE math is enabled or for functions with sseregparm attribute. */
8067 {
8072 }
8074 /* OImode shouldn't be used directly. */
8078 }
8080 static rtx
8082 const_tree valtype)
8083 {
8084 rtx ret;
8086 /* Handle libcalls, which don't provide a type node. */
8088 {
8092 {
8111 }
8114 }
8116 {
8117 /* Pointers are always returned in word_mode. */
8119 }
8125 /* For zero sized structures, construct_container returns NULL, but we
8126 need to keep rest of compiler happy by returning meaningful value. */
8131 }
8133 static rtx
8135 const_tree valtype)
8136 {
8140 {
8142 {
8161 }
8162 }
8164 }
8166 static rtx
8169 {
8184 else
8186 }
8188 static rtx
8190 {
8196 }
8198 /* Return an RTX representing a place where a function returns
8199 or recieves pointer bounds or NULL if no bounds are returned.
8201 VALTYPE is a data type of a value returned by the function.
8203 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8204 or FUNCTION_TYPE of the function.
8206 If OUTGOING is false, return a place in which the caller will
8207 see the return value. Otherwise, return a place where a
8208 function returns a value. */
8210 static rtx
8212 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8214 {
8220 {
8221 bitmap slots;
8223 bitmap_iterator bi;
8231 {
8236 }
8242 }
8243 else
8247 }
8249 /* Pointer function arguments and return values are promoted to
8250 word_mode. */
8252 static machine_mode
8256 {
8258 {
8261 }
8263 for_return);
8264 }
8266 /* Return true if a structure, union or array with MODE containing FIELD
8267 should be accessed using BLKmode. */
8269 static bool
8271 {
8272 /* Union with XFmode must be in BLKmode. */
8276 }
8278 rtx
8280 {
8282 }
8284 /* Return true iff type is returned in memory. */
8286 static bool
8288 {
8289 #ifdef SUBTARGET_RETURN_IN_MEMORY
8291 #else
8293 HOST_WIDE_INT size;
8299 {
8301 {
8304 /* __m128 is returned in xmm0. */
8313 /* Otherwise, the size must be exactly in [1248]. */
8315 }
8316 else
8317 {
8322 }
8323 }
8324 else
8325 {
8335 {
8336 /* User-created vectors small enough to fit in EAX. */
8340 /* Unless ABI prescibes otherwise,
8341 MMX/3dNow values are returned in MM0 if available. */
8346 /* SSE values are returned in XMM0 if available. */
8350 /* AVX values are returned in YMM0 if available. */
8354 /* AVX512F values are returned in ZMM0 if available. */
8357 }
8365 /* OImode shouldn't be used directly. */
8369 }
8370 #endif
8371 }
8373 \f
8374 /* Create the va_list data type. */
8376 /* Returns the calling convention specific va_list date type.
8377 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8379 static tree
8381 {
8384 /* For i386 we use plain pointer to argument area. */
8394 unsigned_type_node);
8397 unsigned_type_node);
8400 ptr_type_node);
8403 ptr_type_node);
8422 /* The correct type is an array type of one element. */
8424 }
8426 /* Setup the builtin va_list data type and for 64-bit the additional
8427 calling convention specific va_list data types. */
8429 static tree
8431 {
8434 /* Initialize abi specific va_list builtin types. */
8436 {
8437 tree t;
8439 {
8444 }
8445 else
8446 {
8451 }
8453 {
8458 }
8459 else
8460 {
8465 }
8466 }
8469 }
8471 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8473 static void
8475 {
8477 alias_set_type set;
8480 /* GPR size of varargs save area. */
8483 else
8486 /* FPR size of varargs save area. We don't need it if we don't pass
8487 anything in SSE registers. */
8490 else
8504 {
8512 }
8515 {
8516 machine_mode smode;
8518 rtx test;
8520 /* Now emit code to save SSE registers. The AX parameter contains number
8521 of SSE parameter registers used to call this function, though all we
8522 actually check here is the zero/non-zero status. */
8527 label));
8529 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8530 we used movdqa (i.e. TImode) instead? Perhaps even better would
8531 be if we could determine the real mode of the data, via a hook
8532 into pass_stdarg. Ignore all that for now. */
8542 {
8551 }
8554 }
8555 }
8557 static void
8559 {
8563 /* Reset to zero, as there might be a sysv vaarg used
8564 before. */
8569 {
8580 }
8581 }
8583 static void
8586 {
8588 CUMULATIVE_ARGS next_cum;
8589 tree fntype;
8591 /* This argument doesn't appear to be used anymore. Which is good,
8592 because the old code here didn't suppress rtl generation. */
8600 /* For varargs, we do not want to skip the dummy va_dcl argument.
8601 For stdargs, we do want to skip the last named argument. */
8609 else
8611 }
8613 static void
8616 tree type,
8619 {
8621 CUMULATIVE_ARGS next_cum;
8622 tree fntype;
8623 rtx save_area;
8628 /* Do nothing if we use plain pointer to argument area. */
8634 /* For varargs, we do not want to skip the dummy va_dcl argument.
8635 For stdargs, we do want to skip the last named argument. */
8649 {
8654 rtx bounds;
8658 else
8659 {
8660 rtx ldx_addr =
8667 }
8673 bnd_reg++;
8674 }
8675 }
8678 /* Checks if TYPE is of kind va_list char *. */
8680 static bool
8682 {
8683 tree canonic;
8685 /* For 32-bit it is always true. */
8691 }
8693 /* Implement va_start. */
8695 static void
8697 {
8701 tree type;
8702 rtx ovf_rtx;
8706 {
8709 /* When we are splitting the stack, we can't refer to the stack
8710 arguments using internal_arg_pointer, because they may be on
8711 the old stack. The split stack prologue will arrange to
8712 leave a pointer to the old stack arguments in a scratch
8713 register, which we here copy to a pseudo-register. The split
8714 stack prologue can't set the pseudo-register directly because
8715 it (the prologue) runs before any registers have been saved. */
8719 {
8720 rtx reg;
8734 }
8735 }
8737 /* Only 64bit target needs something special. */
8739 {
8742 else
8743 {
8753 /* Store zero bounds for va_list. */
8757 next));
8759 }
8761 }
8770 /* The following should be folded into the MEM_REF offset. */
8780 /* Count number of gp and fp argument registers used. */
8786 {
8792 }
8795 {
8801 }
8803 /* Find the overflow area. */
8807 else
8813 /* Store zero bounds for overflow area pointer. */
8822 {
8823 /* Find the register save area.
8824 Prologue of the function save it right above stack frame. */
8830 /* Store zero bounds for save area pointer. */
8837 }
8838 }
8840 /* Implement va_arg. */
8842 static tree
8845 {
8852 rtx container;
8854 tree ptrtype;
8855 machine_mode nat_mode;
8858 /* Only 64bit target needs something special. */
8882 {
8895 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8897 {
8900 }
8908 }
8910 /* Pull the value out of the saved registers. */
8915 {
8929 /* In case we are passing structure, verify that it is consecutive block
8930 on the register save area. If not we need to do moves. */
8932 {
8933 /* Verify that all registers are strictly consecutive */
8935 {
8939 {
8944 }
8945 }
8946 else
8947 {
8951 {
8956 }
8957 }
8958 }
8960 {
8963 }
8964 else
8965 {
8968 }
8970 /* First ensure that we fit completely in registers. */
8972 {
8979 }
8981 {
8989 }
8991 /* Compute index to start of area used for integer regs. */
8993 {
8994 /* int_addr = gpr + sav; */
8997 }
8999 {
9000 /* sse_addr = fpr + sav; */
9003 }
9005 {
9009 /* addr = &temp; */
9014 {
9018 tree piece_type;
9019 tree addr_type;
9020 tree daddr_type;
9029 {
9034 }
9038 else
9045 {
9048 }
9049 else
9050 {
9053 }
9060 {
9065 }
9066 else
9067 {
9068 tree copy
9073 }
9075 }
9076 }
9079 {
9083 }
9086 {
9090 }
9095 }
9097 /* ... otherwise out of the overflow area. */
9099 /* When we align parameter on stack for caller, if the parameter
9100 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9101 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9102 here with caller. */
9107 /* Care for on-stack alignment if needed. */
9110 else
9111 {
9116 }
9133 }
9134 \f
9135 /* Return true if OPNUM's MEM should be matched
9136 in movabs* patterns. */
9138 bool
9140 {
9152 }
9153 \f
9154 /* Initialize the table of extra 80387 mathematical constants. */
9156 static void
9158 {
9160 {
9166 };
9170 {
9172 /* Ensure each constant is rounded to XFmode precision. */
9175 }
9178 }
9180 /* Return non-zero if the constant is something that
9181 can be loaded with a special instruction. */
9183 int
9185 {
9188 REAL_VALUE_TYPE r;
9200 /* For XFmode constants, try to find a special 80387 instruction when
9201 optimizing for size or on those CPUs that benefit from them. */
9204 {
9213 }
9215 /* Load of the constant -0.0 or -1.0 will be split as
9216 fldz;fchs or fld1;fchs sequence. */
9223 }
9225 /* Return the opcode of the special instruction to be used to load
9226 the constant X. */
9230 {
9232 {
9252 }
9253 }
9255 /* Return the CONST_DOUBLE representing the 80387 constant that is
9256 loaded by the specified special instruction. The argument IDX
9257 matches the return value from standard_80387_constant_p. */
9259 rtx
9261 {
9268 {
9279 }
9282 XFmode);
9283 }
9285 /* Return 1 if X is all 0s and 2 if x is all 1s
9286 in supported SSE/AVX vector mode. */
9288 int
9290 {
9297 {
9318 }
9321 }
9323 /* Return the opcode of the special instruction to be used to load
9324 the constant X. */
9328 {
9330 {
9333 {
9360 }
9370 else
9375 }
9377 }
9379 /* Returns true if OP contains a symbol reference */
9381 bool
9383 {
9392 {
9394 {
9400 }
9404 }
9407 }
9409 /* Return true if it is appropriate to emit `ret' instructions in the
9410 body of a function. Do this only if the epilogue is simple, needing a
9411 couple of insns. Prior to reloading, we can't tell how many registers
9412 must be saved, so return false then. Return false if there is no frame
9413 marker to de-allocate. */
9415 bool
9417 {
9423 /* Don't allow more than 32k pop, since that's all we can do
9424 with one instruction. */
9431 }
9432 \f
9433 /* Value should be nonzero if functions must have frame pointers.
9434 Zero means the frame pointer need not be set up (and parms may
9435 be accessed via the stack pointer) in functions that seem suitable. */
9437 static bool
9439 {
9440 /* If we accessed previous frames, then the generated code expects
9441 to be able to access the saved ebp value in our frame. */
9445 /* Several x86 os'es need a frame pointer for other reasons,
9446 usually pertaining to setjmp. */
9450 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9454 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9455 allocation is 4GB. */
9459 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9460 turns off the frame pointer by default. Turn it back on now if
9461 we've not got a leaf function. */
9471 }
9473 /* Record that the current function accesses previous call frames. */
9475 void
9477 {
9479 }
9480 \f
9481 #ifndef USE_HIDDEN_LINKONCE
9482 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9483 # define USE_HIDDEN_LINKONCE 1
9484 # else
9485 # define USE_HIDDEN_LINKONCE 0
9486 # endif
9487 #endif
9491 /* Fills in the label name that should be used for a pc thunk for
9492 the given register. */
9494 static void
9496 {
9501 else
9503 }
9506 /* This function generates code for -fpic that loads %ebx with
9507 the return address of the caller and then returns. */
9509 static void
9511 {
9516 {
9518 tree decl;
9534 #if TARGET_MACHO
9536 {
9545 }
9546 else
9547 #endif
9549 {
9560 }
9561 else
9562 {
9565 }
9571 /* Make sure unwind info is emitted for the thunk if needed. */
9574 /* Pad stack IP move with 4 instructions (two NOPs count
9575 as one instruction). */
9577 {
9582 }
9593 }
9597 }
9599 /* Emit code for the SET_GOT patterns. */
9603 {
9609 {
9610 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9615 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9616 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9617 an unadorned address. */
9622 }
9627 {
9629 /* We don't need a pic base, we're not producing pic. */
9636 }
9637 else
9638 {
9647 #if TARGET_MACHO
9648 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9649 This is what will be referenced by the Mach-O PIC subsystem. */
9653 /* When we are restoring the pic base at the site of a nonlocal label,
9654 and we decided to emit the pic base above, we will still output a
9655 local label used for calculating the correction offset (even though
9656 the offset will be 0 in that case). */
9660 #endif
9661 }
9667 }
9669 /* Generate an "push" pattern for input ARG. */
9671 static rtx
9673 {
9686 stack_pointer_rtx)),
9687 arg);
9688 }
9690 /* Generate an "pop" pattern for input ARG. */
9692 static rtx
9694 {
9699 arg,
9702 stack_pointer_rtx)));
9703 }
9705 /* Return >= 0 if there is an unused call-clobbered register available
9706 for the entire function. */
9708 static unsigned int
9710 {
9717 {
9719 /* Can't use the same register for both PIC and DRAP. */
9722 else
9727 }
9730 }
9732 /* Return TRUE if we need to save REGNO. */
9734 static bool
9736 {
9739 {
9741 {
9742 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
9743 _mcount in prologue. */
9746 }
9753 }
9756 {
9759 {
9765 }
9766 }
9777 }
9779 /* Return number of saved general prupose registers. */
9781 static int
9783 {
9789 nregs ++;
9791 }
9793 /* Return number of saved SSE registrers. */
9795 static int
9797 {
9805 nregs ++;
9807 }
9809 /* Given FROM and TO register numbers, say whether this elimination is
9810 allowed. If stack alignment is needed, we can only replace argument
9811 pointer with hard frame pointer, or replace frame pointer with stack
9812 pointer. Otherwise, frame pointer elimination is automatically
9813 handled and all other eliminations are valid. */
9815 static bool
9817 {
9823 else
9825 }
9827 /* Return the offset between two registers, one to be eliminated, and the other
9828 its replacement, at the start of a routine. */
9830 HOST_WIDE_INT
9832 {
9841 else
9842 {
9850 }
9851 }
9853 /* In a dynamically-aligned function, we can't know the offset from
9854 stack pointer to frame pointer, so we must ensure that setjmp
9855 eliminates fp against the hard fp (%ebp) rather than trying to
9856 index from %esp up to the top of the frame across a gap that is
9857 of unknown (at compile-time) size. */
9858 static rtx
9860 {
9862 }
9864 /* When using -fsplit-stack, the allocation routines set a field in
9865 the TCB to the bottom of the stack plus this much space, measured
9866 in bytes. */
9868 #define SPLIT_STACK_AVAILABLE 256
9870 /* Fill structure ix86_frame about frame of currently computed function. */
9872 static void
9874 {
9876 HOST_WIDE_INT offset;
9879 HOST_WIDE_INT to_allocate;
9884 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9885 function prologues and leaf. */
9889 {
9892 }
9893 /* preferred_stack_boundary is never updated for call
9894 expanded from tls descriptor. Update it here. We don't update it in
9895 expand stage because according to the comments before
9896 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
9897 away. */
9900 {
9904 }
9913 /* For SEH we have to limit the amount of code movement into the prologue.
9914 At present we do this via a BLOCKAGE, at which point there's very little
9915 scheduling that can be done, which means that there's very little point
9916 in doing anything except PUSHs. */
9920 /* During reload iteration the amount of registers saved can change.
9921 Recompute the value as needed. Do not recompute when amount of registers
9922 didn't change as reload does multiple calls to the function and does not
9923 expect the decision to change within single iteration. */
9926 {
9932 /* The fast prologue uses move instead of push to save registers. This
9933 is significantly longer, but also executes faster as modern hardware
9934 can execute the moves in parallel, but can't do that for push/pop.
9936 Be careful about choosing what prologue to emit: When function takes
9937 many instructions to execute we may use slow version as well as in
9938 case function is known to be outside hot spot (this is known with
9939 feedback only). Weight the size of function by number of registers
9940 to save as it is cheap to use one or two push instructions but very
9941 slow to use many of them. */
9945 || (flag_branch_probabilities
9948 else
9951 }
9953 frame->save_regs_using_mov
9955 /* If static stack checking is enabled and done with probes,
9956 the registers need to be saved before allocating the frame. */
9959 /* Skip return address. */
9962 /* Skip pushed static chain. */
9966 /* Skip saved base pointer. */
9971 /* The traditional frame pointer location is at the top of the frame. */
9974 /* Register save area */
9978 /* On SEH target, registers are pushed just before the frame pointer
9979 location. */
9983 /* Align and set SSE register save area. */
9985 {
9986 /* The only ABI that has saved SSE registers (Win64) also has a
9987 16-byte aligned default stack, and thus we don't need to be
9988 within the re-aligned local stack frame to save them. */
9992 }
9995 /* The re-aligned stack starts here. Values before this point are not
9996 directly comparable with values below this point. In order to make
9997 sure that no value happens to be the same before and after, force
9998 the alignment computation below to add a non-zero value. */
10002 /* Va-arg area */
10006 /* Align start of frame for local function. */
10015 /* Frame pointer points here. */
10020 /* Add outgoing arguments area. Can be skipped if we eliminated
10021 all the function calls as dead code.
10022 Skipping is however impossible when function calls alloca. Alloca
10023 expander assumes that last crtl->outgoing_args_size
10024 of stack frame are unused. */
10028 {
10031 }
10032 else
10035 /* Align stack boundary. Only needed if we're calling another function
10036 or using alloca. */
10041 /* We've reached end of stack frame. */
10044 /* Size prologue needs to allocate. */
10055 {
10061 }
10062 else
10066 /* The SEH frame pointer location is near the bottom of the frame.
10067 This is enforced by the fact that the difference between the
10068 stack pointer and the frame pointer is limited to 240 bytes in
10069 the unwind data structure. */
10071 {
10072 HOST_WIDE_INT diff;
10074 /* If we can leave the frame pointer where it is, do so. Also, returns
10075 the establisher frame for __builtin_frame_address (0). */
10080 {
10081 /* Ideally we'd determine what portion of the local stack frame
10082 (within the constraint of the lowest 240) is most heavily used.
10083 But without that complication, simply bias the frame pointer
10084 by 128 bytes so as to maximize the amount of the local stack
10085 frame that is addressable with 8-bit offsets. */
10087 }
10088 }
10089 }
10091 /* This is semi-inlined memory_address_length, but simplified
10092 since we know that we're always dealing with reg+offset, and
10093 to avoid having to create and discard all that rtl. */
10097 {
10101 {
10102 /* EBP and R13 cannot be encoded without an offset. */
10104 }
10108 /* ESP and R12 must be encoded with a SIB byte. */
10110 len++;
10113 }
10115 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10116 The valid base registers are taken from CFUN->MACHINE->FS. */
10118 static rtx
10120 {
10126 {
10127 /* Choose the base register most likely to allow the most scheduling
10128 opportunities. Generally FP is valid throughout the function,
10129 while DRAP must be reloaded within the epilogue. But choose either
10130 over the SP due to increased encoding size. */
10133 {
10136 }
10138 {
10141 }
10143 {
10146 }
10147 }
10148 else
10149 {
10150 HOST_WIDE_INT toffset;
10153 /* Choose the base register with the smallest address encoding.
10154 With a tie, choose FP > DRAP > SP. */
10156 {
10160 }
10162 {
10166 {
10170 }
10171 }
10173 {
10177 {
10181 }
10182 }
10183 }
10187 }
10189 /* Emit code to save registers in the prologue. */
10191 static void
10193 {
10195 rtx insn;
10199 {
10202 }
10203 }
10205 /* Emit a single register save at CFA - CFA_OFFSET. */
10207 static void
10209 HOST_WIDE_INT cfa_offset)
10210 {
10218 /* For SSE saves, we need to indicate the 128-bit alignment. */
10229 /* When saving registers into a re-aligned local stack frame, avoid
10230 any tricky guessing by dwarf2out. */
10232 {
10236 {
10237 /* A bit of a hack. We force the DRAP register to be saved in
10238 the re-aligned stack frame, which provides us with a copy
10239 of the CFA that will last past the prologue. Install it. */
10245 }
10246 else
10247 {
10248 /* The frame pointer is a stable reference within the
10249 aligned frame. Use it. */
10256 }
10257 }
10259 /* The memory may not be relative to the current CFA register,
10260 which means that we may need to generate a new pattern for
10261 use by the unwind info. */
10263 {
10268 }
10269 }
10271 /* Emit code to save registers using MOV insns.
10272 First register is stored at CFA - CFA_OFFSET. */
10273 static void
10275 {
10280 {
10283 }
10284 }
10286 /* Emit code to save SSE registers using MOV insns.
10287 First register is stored at CFA - CFA_OFFSET. */
10288 static void
10290 {
10295 {
10298 }
10299 }
10303 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10304 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10305 Don't add the note if the previously saved value will be left untouched
10306 within stack red-zone till return, as unwinders can find the same value
10307 in the register and on the stack. */
10309 static void
10311 {
10317 {
10320 }
10321 else
10322 queued_cfa_restores
10324 }
10326 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10328 static void
10330 {
10331 rtx last;
10335 ;
10340 }
10342 /* Expand prologue or epilogue stack adjustment.
10343 The pattern exist to put a dependency on all ebp-based memory accesses.
10344 STYLE should be negative if instructions should be marked as frame related,
10345 zero if %r11 register is live and cannot be freely used and positive
10346 otherwise. */
10348 static void
10351 {
10353 rtx insn;
10360 else
10361 {
10362 rtx tmp;
10363 /* r11 is used by indirect sibcall return as well, set before the
10364 epilogue and used after the epilogue. */
10367 else
10368 {
10372 }
10378 }
10385 {
10386 rtx r;
10396 }
10398 {
10401 {
10405 }
10406 }
10409 {
10414 {
10417 }
10419 {
10422 }
10423 else
10424 {
10425 /* Else there are two possibilities: SP itself, which we set
10426 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10427 taken care of this by hand along the eh_return path. */
10430 }
10434 }
10435 }
10437 /* Find an available register to be used as dynamic realign argument
10438 pointer regsiter. Such a register will be written in prologue and
10439 used in begin of body, so it must not be
10440 1. parameter passing register.
10441 2. GOT pointer.
10442 We reuse static-chain register if it is available. Otherwise, we
10443 use DI for i386 and R13 for x86-64. We chose R13 since it has
10444 shorter encoding.
10446 Return: the regno of chosen register. */
10448 static unsigned int
10450 {
10454 {
10455 /* Use R13 for nested function or function need static chain.
10456 Since function with tail call may use any caller-saved
10457 registers in epilogue, DRAP must not use caller-saved
10458 register in such case. */
10463 }
10464 else
10465 {
10466 /* Use DI for nested function or function need static chain.
10467 Since function with tail call may use any caller-saved
10468 registers in epilogue, DRAP must not use caller-saved
10469 register in such case. */
10473 /* Reuse static chain register if it isn't used for parameter
10474 passing. */
10476 {
10480 }
10482 }
10483 }
10485 /* Return minimum incoming stack alignment. */
10487 static unsigned int
10489 {
10492 /* Prefer the one specified at command line. */
10495 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10496 if -mstackrealign is used, it isn't used for sibcall check and
10497 estimated stack alignment is 128bit. */
10499 && !TARGET_64BIT
10500 && ix86_force_align_arg_pointer
10503 else
10506 /* Incoming stack alignment can be changed on individual functions
10507 via force_align_arg_pointer attribute. We use the smallest
10508 incoming stack boundary. */
10514 /* The incoming stack frame has to be aligned at least at
10515 parm_stack_boundary. */
10519 /* Stack at entrance of main is aligned by runtime. We use the
10520 smallest incoming stack boundary. */
10528 }
10530 /* Update incoming stack boundary and estimated stack alignment. */
10532 static void
10534 {
10535 ix86_incoming_stack_boundary
10538 /* x86_64 vararg needs 16byte stack alignment for register save
10539 area. */
10544 }
10546 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10547 needed or an rtx for DRAP otherwise. */
10549 static rtx
10551 {
10556 {
10557 /* Assign DRAP to vDRAP and returns vDRAP */
10559 rtx drap_vreg;
10560 rtx arg_ptr;
10573 {
10576 }
10578 }
10579 else
10581 }
10583 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10585 static rtx
10587 {
10589 }
10592 rtx reg;
10594 };
10596 /* Return a short-lived scratch register for use on function entry.
10597 In 32-bit mode, it is valid only after the registers are saved
10598 in the prologue. This register must be released by means of
10599 release_scratch_register_on_entry once it is dead. */
10601 static void
10603 {
10609 {
10610 /* We always use R11 in 64-bit mode. */
10612 }
10613 else
10614 {
10616 bool fastcall_p
10618 bool thiscall_p
10622 int drap_regno
10625 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10626 for the static chain register. */
10630 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10631 for the static chain register. */
10636 /* ecx is the static chain register. */
10638 && !static_chain_p
10643 /* esi is the static chain register. */
10649 else
10650 {
10653 }
10654 }
10658 {
10661 }
10662 }
10664 /* Release a scratch register obtained from the preceding function. */
10666 static void
10668 {
10670 {
10674 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10680 }
10681 }
10683 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10685 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10687 static void
10689 {
10690 /* We skip the probe for the first interval + a small dope of 4 words and
10691 probe that many bytes past the specified size to maintain a protection
10692 area at the botton of the stack. */
10696 /* See if we have a constant small number of probes to generate. If so,
10697 that's the easy case. The run-time loop is made up of 11 insns in the
10698 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10699 for n # of intervals. */
10701 {
10705 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10706 values of N from 1 until it exceeds SIZE. If only one probe is
10707 needed, this will not generate any code. Then adjust and probe
10708 to PROBE_INTERVAL + SIZE. */
10710 {
10712 {
10715 }
10716 else
10723 }
10727 else
10735 /* Adjust back to account for the additional first interval. */
10739 }
10741 /* Otherwise, do the same as above, but in a loop. Note that we must be
10742 extra careful with variables wrapping around because we might be at
10743 the very top (or the very bottom) of the address space and we have
10744 to be able to handle this case properly; in particular, we use an
10745 equality test for the loop condition. */
10746 else
10747 {
10748 HOST_WIDE_INT rounded_size;
10754 /* Step 1: round SIZE to the previous multiple of the interval. */
10759 /* Step 2: compute initial and final value of the loop counter. */
10761 /* SP = SP_0 + PROBE_INTERVAL. */
10766 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10770 stack_pointer_rtx)));
10773 /* Step 3: the loop
10775 while (SP != LAST_ADDR)
10776 {
10777 SP = SP + PROBE_INTERVAL
10778 probe at SP
10779 }
10781 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10782 values of N from 1 until it is equal to ROUNDED_SIZE. */
10787 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10788 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10791 {
10796 }
10798 /* Adjust back to account for the additional first interval. */
10804 }
10808 /* Even if the stack pointer isn't the CFA register, we need to correctly
10809 describe the adjustments made to it, in particular differentiate the
10810 frame-related ones from the frame-unrelated ones. */
10812 {
10825 }
10827 /* Make sure nothing is scheduled before we are done. */
10829 }
10831 /* Adjust the stack pointer up to REG while probing it. */
10835 {
10845 /* Jump to END_LAB if SP == LAST_ADDR. */
10853 /* SP = SP + PROBE_INTERVAL. */
10857 /* Probe at SP. */
10868 }
10870 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10871 inclusive. These are offsets from the current stack pointer. */
10873 static void
10875 {
10876 /* See if we have a constant small number of probes to generate. If so,
10877 that's the easy case. The run-time loop is made up of 7 insns in the
10878 generic case while the compile-time loop is made up of n insns for n #
10879 of intervals. */
10881 {
10882 HOST_WIDE_INT i;
10884 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10885 it exceeds SIZE. If only one probe is needed, this will not
10886 generate any code. Then probe at FIRST + SIZE. */
10893 }
10895 /* Otherwise, do the same as above, but in a loop. Note that we must be
10896 extra careful with variables wrapping around because we might be at
10897 the very top (or the very bottom) of the address space and we have
10898 to be able to handle this case properly; in particular, we use an
10899 equality test for the loop condition. */
10900 else
10901 {
10908 /* Step 1: round SIZE to the previous multiple of the interval. */
10913 /* Step 2: compute initial and final value of the loop counter. */
10915 /* TEST_OFFSET = FIRST. */
10918 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10922 /* Step 3: the loop
10924 while (TEST_ADDR != LAST_ADDR)
10925 {
10926 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10927 probe at TEST_ADDR
10928 }
10930 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10931 until it is equal to ROUNDED_SIZE. */
10936 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10937 that SIZE is equal to ROUNDED_SIZE. */
10942 stack_pointer_rtx,
10947 }
10949 /* Make sure nothing is scheduled before we are done. */
10951 }
10953 /* Probe a range of stack addresses from REG to END, inclusive. These are
10954 offsets from the current stack pointer. */
10958 {
10968 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10976 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10980 /* Probe at TEST_ADDR. */
10993 }
10995 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10996 to be generated in correct form. */
10997 static void
10999 {
11000 /* Check if stack realign is really needed after reload, and
11001 stores result in cfun */
11002 unsigned int incoming_stack_boundary
11011 {
11012 /* After stack_realign_needed is finalized, we can't no longer
11013 change it. */
11016 }
11018 /* If the only reason for frame_pointer_needed is that we conservatively
11019 assumed stack realignment might be needed, but in the end nothing that
11020 needed the stack alignment had been spilled, clear frame_pointer_needed
11021 and say we don't need stack realignment. */
11023 && frame_pointer_needed
11025 && flag_omit_frame_pointer
11027 && !ix86_current_function_calls_tls_descriptor
11036 {
11038 basic_block bb;
11045 HARD_FRAME_POINTER_REGNUM);
11047 {
11052 set_up_by_prologue))
11053 {
11057 }
11058 }
11060 /* If drap has been set, but it actually isn't live at the start
11061 of the function, there is no reason to set it up. */
11063 {
11066 {
11069 }
11070 }
11071 else
11086 }
11090 }
11092 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11094 static void
11096 {
11102 {
11105 {
11111 }
11112 }
11113 }
11115 /* Expand the prologue into a bunch of separate insns. */
11117 void
11119 {
11123 HOST_WIDE_INT allocate;
11129 /* DRAP should not coexist with stack_realign_fp */
11134 /* Initialize CFA state for before the prologue. */
11138 /* Track SP offset to the CFA. We continue tracking this after we've
11139 swapped the CFA register away from SP. In the case of re-alignment
11140 this is fudged; we're interested to offsets within the local frame. */
11147 {
11148 /* We should have already generated an error for any use of
11149 ms_hook on a nested function. */
11152 /* Check if profiling is active and we shall use profiling before
11153 prologue variant. If so sorry. */
11158 /* In ix86_asm_output_function_label we emitted:
11159 8b ff movl.s %edi,%edi
11160 55 push %ebp
11161 8b ec movl.s %esp,%ebp
11163 This matches the hookable function prologue in Win32 API
11164 functions in Microsoft Windows XP Service Pack 2 and newer.
11165 Wine uses this to enable Windows apps to hook the Win32 API
11166 functions provided by Wine.
11168 What that means is that we've already set up the frame pointer. */
11172 {
11175 /* We've decided to use the frame pointer already set up.
11176 Describe this to the unwinder by pretending that both
11177 push and mov insns happen right here.
11179 Putting the unwind info here at the end of the ms_hook
11180 is done so that we can make absolutely certain we get
11181 the required byte sequence at the start of the function,
11182 rather than relying on an assembler that can produce
11183 the exact encoding required.
11185 However it does mean (in the unpatched case) that we have
11186 a 1 insn window where the asynchronous unwind info is
11187 incorrect. However, if we placed the unwind info at
11188 its correct location we would have incorrect unwind info
11189 in the patched case. Which is probably all moot since
11190 I don't expect Wine generates dwarf2 unwind info for the
11191 system libraries that use this feature. */
11197 stack_pointer_rtx);
11205 /* Note that gen_push incremented m->fs.cfa_offset, even
11206 though we didn't emit the push insn here. */
11210 }
11211 else
11212 {
11213 /* The frame pointer is not needed so pop %ebp again.
11214 This leaves us with a pristine state. */
11216 }
11217 }
11219 /* The first insn of a function that accepts its static chain on the
11220 stack is to push the register that would be filled in by a direct
11221 call. This insn will be skipped by the trampoline. */
11223 {
11227 /* We don't want to interpret this push insn as a register save,
11228 only as a stack adjustment. The real copy of the register as
11229 a save will be done later, if needed. */
11234 }
11236 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11237 of DRAP is needed and stack realignment is really needed after reload */
11239 {
11242 /* Only need to push parameter pointer reg if it is caller saved. */
11244 {
11245 /* Push arg pointer reg */
11248 }
11250 /* Grab the argument pointer. */
11257 /* Align the stack. */
11259 stack_pointer_rtx,
11263 /* Replicate the return address on the stack so that return
11264 address can be reached via (argp - 1) slot. This is needed
11265 to implement macro RETURN_ADDR_RTX and intrinsic function
11266 expand_builtin_return_addr etc. */
11272 /* For the purposes of frame and register save area addressing,
11273 we've started over with a new frame. */
11276 }
11282 {
11283 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11284 slower on all targets. Also sdb doesn't like it. */
11288 /* Push registers now, before setting the frame pointer
11289 on SEH target. */
11291 && TARGET_SEH
11293 {
11297 }
11300 {
11308 }
11309 }
11312 {
11313 /* If saving registers via PUSH, do so now. */
11315 {
11319 }
11321 /* When using red zone we may start register saving before allocating
11322 the stack frame saving one cycle of the prologue. However, avoid
11323 doing this if we have to probe the stack; at least on x86_64 the
11324 stack probe can turn into a call that clobbers a red zone location. */
11326 && (! TARGET_STACK_PROBE
11328 {
11331 }
11332 }
11335 {
11339 /* The computation of the size of the re-aligned stack frame means
11340 that we must allocate the size of the register save area before
11341 performing the actual alignment. Otherwise we cannot guarantee
11342 that there's enough storage above the realignment point. */
11349 /* Align the stack. */
11351 stack_pointer_rtx,
11354 /* For the purposes of register save area addressing, the stack
11355 pointer is no longer valid. As for the value of sp_offset,
11356 see ix86_compute_frame_layout, which we need to match in order
11357 to pass verification of stack_pointer_offset at the end. */
11360 }
11365 {
11366 /* We start to count from ARG_POINTER. */
11369 /* If it was realigned, take into account the fake frame. */
11371 {
11378 /* This over-estimates by 1 minimal-stack-alignment-unit but
11379 mitigates that by counting in the new return address slot. */
11380 current_function_dynamic_stack_size
11382 }
11385 }
11387 /* On SEH target with very large frame size, allocate an area to save
11388 SSE registers (as the very large allocation won't be described). */
11392 {
11393 HOST_WIDE_INT sse_size =
11398 /* No need to do stack checking as the area will be immediately
11399 written. */
11406 }
11408 /* The stack has already been decremented by the instruction calling us
11409 so probe if the size is non-negative to preserve the protection area. */
11411 {
11412 /* We expect the registers to be saved when probes are used. */
11416 {
11419 {
11422 }
11423 }
11424 else
11425 {
11432 {
11434 {
11437 }
11438 else
11440 }
11441 else
11442 {
11444 {
11448 }
11449 else
11451 }
11452 }
11453 }
11456 ;
11459 {
11463 }
11464 else
11465 {
11477 {
11480 /* Note that SEH directives need to continue tracking the stack
11481 pointer even after the frame pointer has been set up. */
11483 {
11487 }
11488 }
11491 {
11496 {
11500 }
11501 }
11506 /* Use the fact that AX still contains ALLOCATE. */
11508 ? gen_pro_epilogue_adjust_stack_di_sub
11515 {
11523 }
11526 /* Use stack_pointer_rtx for relative addressing so that code
11527 works for realigned stack, too. */
11529 {
11536 }
11538 {
11543 }
11544 }
11547 /* If we havn't already set up the frame pointer, do so now. */
11549 {
11561 }
11568 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11569 in PROLOGUE. */
11571 {
11577 /* Deleting already emmitted SET_GOT if exist and allocated to
11578 REAL_PIC_OFFSET_TABLE_REGNUM. */
11580 }
11583 {
11584 /* vDRAP is setup but after reload it turns out stack realign
11585 isn't necessary, here we will emit prologue to setup DRAP
11586 without stack realign adjustment */
11589 }
11591 /* Prevent instructions from being scheduled into register save push
11592 sequence when access to the redzone area is done through frame pointer.
11593 The offset between the frame pointer and the stack pointer is calculated
11594 relative to the value of the stack pointer at the end of the function
11595 prologue, and moving instructions that access redzone area via frame
11596 pointer inside push sequence violates this assumption. */
11600 /* Emit cld instruction if stringops are used in the function. */
11604 /* SEH requires that the prologue end within 256 bytes of the start of
11605 the function. Prevent instruction schedules that would extend that.
11606 Further, prevent alloca modifications to the stack pointer from being
11607 combined with prologue modifications. */
11610 }
11612 /* Emit code to restore REG using a POP insn. */
11614 static void
11616 {
11625 {
11626 /* Previously we'd represented the CFA as an expression
11627 like *(%ebp - 8). We've just popped that value from
11628 the stack, which means we need to reset the CFA to
11629 the drap register. This will remain until we restore
11630 the stack pointer. */
11634 /* This means that the DRAP register is valid for addressing too. */
11637 }
11640 {
11647 }
11649 /* When the frame pointer is the CFA, and we pop it, we are
11650 swapping back to the stack pointer as the CFA. This happens
11651 for stack frames that don't allocate other data, so we assume
11652 the stack pointer is now pointing at the return address, i.e.
11653 the function entry state, which makes the offset be 1 word. */
11655 {
11658 {
11666 }
11667 }
11668 }
11670 /* Emit code to restore saved registers using POP insns. */
11672 static void
11674 {
11680 }
11682 /* Emit code and notes for the LEAVE instruction. */
11684 static void
11686 {
11698 {
11706 }
11709 }
11711 /* Emit code to restore saved registers using MOV insns.
11712 First register is restored from CFA - CFA_OFFSET. */
11713 static void
11716 {
11722 {
11731 {
11732 /* Previously we'd represented the CFA as an expression
11733 like *(%ebp - 8). We've just popped that value from
11734 the stack, which means we need to reset the CFA to
11735 the drap register. This will remain until we restore
11736 the stack pointer. */
11740 /* This means that the DRAP register is valid for addressing. */
11742 }
11743 else
11747 }
11748 }
11750 /* Emit code to restore saved registers using MOV insns.
11751 First register is restored from CFA - CFA_OFFSET. */
11752 static void
11755 {
11760 {
11762 rtx mem;
11772 }
11773 }
11775 /* Restore function stack, frame, and registers. */
11777 void
11779 {
11795 /* The FP must be valid if the frame pointer is present. */
11800 /* We must have *some* valid pointer to the stack frame. */
11803 /* The DRAP is never valid at this point. */
11806 /* See the comment about red zone and frame
11807 pointer usage in ix86_expand_prologue. */
11814 /* Determine the CFA offset of the end of the red-zone. */
11817 {
11818 /* The red-zone begins below the return address. */
11821 /* When the register save area is in the aligned portion of
11822 the stack, determine the maximum runtime displacement that
11823 matches up with the aligned frame. */
11827 }
11829 /* Special care must be taken for the normal return case of a function
11830 using eh_return: the eax and edx registers are marked as saved, but
11831 not restored along this path. Adjust the save location to match. */
11835 /* EH_RETURN requires the use of moves to function properly. */
11838 /* SEH requires the use of pops to identify the epilogue. */
11841 /* If we're only restoring one register and sp is not valid then
11842 using a move instruction to restore the register since it's
11843 less work than reloading sp and popping the register. */
11856 && TARGET_USE_LEAVE
11860 else
11864 {
11865 /* Ensure that the entire register save area is addressable via
11866 the stack pointer, if we will restore via sp. */
11871 {
11875 style,
11877 }
11878 }
11880 /* If there are any SSE registers to restore, then we have to do it
11881 via moves, since there's obviously no pop for SSE regs. */
11887 {
11888 rtx t;
11893 /* eh_return epilogues need %ecx added to the stack pointer. */
11895 {
11898 /* Stack align doesn't work with eh_return. */
11900 /* Neither does regparm nested functions. */
11904 {
11912 /* Note that we use SA as a temporary CFA, as the return
11913 address is at the proper place relative to it. We
11914 pretend this happens at the FP restore insn because
11915 prior to this insn the FP would be stored at the wrong
11916 offset relative to SA, and after this insn we have no
11917 other reasonable register to use for the CFA. We don't
11918 bother resetting the CFA to the SP for the duration of
11919 the return insn. */
11932 }
11933 else
11934 {
11942 {
11946 UNITS_PER_WORD));
11948 }
11949 }
11952 }
11953 }
11954 else
11955 {
11956 /* SEH requires that the function end with (1) a stack adjustment
11957 if necessary, (2) a sequence of pops, and (3) a return or
11958 jump instruction. Prevent insns from the function body from
11959 being scheduled into this sequence. */
11961 {
11962 /* Prevent a catch region from being adjacent to the standard
11963 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11964 several other flags that would be interesting to test are
11965 not yet set up. */
11968 else
11970 }
11972 /* First step is to deallocate the stack frame so that we can
11973 pop the registers. Also do it on SEH target for very large
11974 frame as the emitted instructions aren't allowed by the ABI in
11975 epilogues. */
11977 || (TARGET_SEH
11980 {
11985 }
11987 {
11991 style,
11993 }
11996 }
11998 /* If we used a stack pointer and haven't already got rid of it,
11999 then do so now. */
12001 {
12002 /* If the stack pointer is valid and pointing at the frame
12003 pointer store address, then we only need a pop. */
12006 /* Leave results in shorter dependency chains on CPUs that are
12007 able to grok it fast. */
12012 else
12013 {
12015 hard_frame_pointer_rtx,
12018 }
12019 }
12022 {
12024 rtx insn;
12050 }
12052 /* At this point the stack pointer must be valid, and we must have
12053 restored all of the registers. We may not have deallocated the
12054 entire stack frame. We've delayed this until now because it may
12055 be possible to merge the local stack deallocation with the
12056 deallocation forced by ix86_static_chain_on_stack. */
12061 {
12065 }
12066 else
12069 /* Sibcall epilogues don't want a return instruction. */
12071 {
12074 }
12077 {
12080 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12081 address, do explicit add, and jump indirectly to the caller. */
12084 {
12086 rtx insn;
12088 /* There is no "pascal" calling convention in any 64bit ABI. */
12105 }
12106 else
12108 }
12109 else
12112 /* Restore the state back to the state from the prologue,
12113 so that it's correct for the next epilogue. */
12115 }
12117 /* Reset from the function's potential modifications. */
12119 static void
12121 {
12125 #if TARGET_MACHO
12126 /* Mach-O doesn't support labels at the end of objects, so if
12127 it looks like we might want one, insert a NOP. */
12128 {
12134 {
12135 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12136 notes only, instead set their CODE_LABEL_NUMBER to -1,
12137 otherwise there would be code generation differences
12138 in between -g and -g0. */
12142 }
12152 }
12153 #endif
12155 }
12157 /* Return a scratch register to use in the split stack prologue. The
12158 split stack prologue is used for -fsplit-stack. It is the first
12159 instructions in the function, even before the regular prologue.
12160 The scratch register can be any caller-saved register which is not
12161 used for parameters or for the static chain. */
12163 static unsigned int
12165 {
12168 else
12169 {
12182 {
12184 {
12188 }
12190 }
12192 {
12196 }
12198 {
12201 else
12202 {
12204 {
12208 }
12210 }
12211 }
12212 else
12213 {
12214 /* FIXME: We could make this work by pushing a register
12215 around the addition and comparison. */
12218 }
12219 }
12220 }
12222 /* A SYMBOL_REF for the function which allocates new stackspace for
12223 -fsplit-stack. */
12227 /* A SYMBOL_REF for the more stack function when using the large
12228 model. */
12232 /* Handle -fsplit-stack. These are the first instructions in the
12233 function, even before the regular prologue. */
12235 void
12237 {
12239 HOST_WIDE_INT allocate;
12245 rtx fn;
12253 /* This is the label we will branch to if we have enough stack
12254 space. We expect the basic block reordering pass to reverse this
12255 branch if optimizing, so that we branch in the unlikely case. */
12258 /* We need to compare the stack pointer minus the frame size with
12259 the stack boundary in the TCB. The stack boundary always gives
12260 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12261 can compare directly. Otherwise we need to do an addition. */
12264 UNSPEC_STACK_CHECK);
12269 else
12270 {
12272 rtx offset;
12274 /* We need a scratch register to hold the stack pointer minus
12275 the required frame size. Since this is the very start of the
12276 function, the scratch register can be any caller-saved
12277 register which is not used for parameters. */
12284 {
12285 /* We don't use ix86_gen_add3 in this case because it will
12286 want to split to lea, but when not optimizing the insn
12287 will not be split after this point. */
12290 offset)));
12291 }
12292 else
12293 {
12296 stack_pointer_rtx));
12297 }
12299 }
12305 /* Mark the jump as very likely to be taken. */
12310 {
12313 }
12316 /* Get more stack space. We pass in the desired stack space and the
12317 size of the arguments to copy to the new stack. In 32-bit mode
12318 we push the parameters; __morestack will return on a new stack
12319 anyhow. In 64-bit mode we pass the parameters in r10 and
12320 r11. */
12325 {
12331 /* If this function uses a static chain, it will be in %r10.
12332 Preserve it across the call to __morestack. */
12334 {
12335 rtx rax;
12340 }
12344 {
12345 HOST_WIDE_INT argval;
12348 /* When using the large model we need to load the address
12349 into a register, and we've run out of registers. So we
12350 switch to a different calling convention, and we call a
12351 different function: __morestack_large. We pass the
12352 argument size in the upper 32 bits of r10 and pass the
12353 frame size in the lower 32 bits. */
12358 {
12359 split_stack_fn_large =
12362 }
12364 {
12366 rtx x;
12375 UNSPEC_GOT);
12381 }
12382 else
12389 }
12390 else
12391 {
12395 }
12398 }
12399 else
12400 {
12403 }
12409 /* In order to make call/return prediction work right, we now need
12410 to execute a return instruction. See
12411 libgcc/config/i386/morestack.S for the details on how this works.
12413 For flow purposes gcc must not see this as a return
12414 instruction--we need control flow to continue at the subsequent
12415 label. Therefore, we use an unspec. */
12419 /* If we are in 64-bit mode and this function uses a static chain,
12420 we saved %r10 in %rax before calling _morestack. */
12425 /* If this function calls va_start, we need to store a pointer to
12426 the arguments on the old stack, because they may not have been
12427 all copied to the new stack. At this point the old stack can be
12428 found at the frame pointer value used by __morestack, because
12429 __morestack has set that up before calling back to us. Here we
12430 store that pointer in a scratch register, and in
12431 ix86_expand_prologue we store the scratch register in a stack
12432 slot. */
12434 {
12436 rtx frame_reg;
12443 /* 64-bit:
12444 fp -> old fp value
12445 return address within this function
12446 return address of caller of this function
12447 stack arguments
12448 So we add three words to get to the stack arguments.
12450 32-bit:
12451 fp -> old fp value
12452 return address within this function
12453 first argument to __morestack
12454 second argument to __morestack
12455 return address of caller of this function
12456 stack arguments
12457 So we add five words to get to the stack arguments.
12458 */
12469 }
12474 /* If this function calls va_start, we now have to set the scratch
12475 register for the case where we do not call __morestack. In this
12476 case we need to set it based on the stack pointer. */
12478 {
12485 }
12486 }
12488 /* We may have to tell the dataflow pass that the split stack prologue
12489 is initializing a scratch register. */
12491 static void
12493 {
12495 {
12498 }
12499 }
12500 \f
12501 /* Extract the parts of an RTL expression that is a valid memory address
12502 for an instruction. Return 0 if the structure of the address is
12503 grossly off. Return -1 if the address contains ASHIFT, so it is not
12504 strictly valid, but still used for computing length of lea instruction. */
12506 int
12508 {
12513 rtx tmp;
12517 /* Allow zero-extended SImode addresses,
12518 they will be emitted with addr32 prefix. */
12520 {
12523 {
12527 }
12530 {
12537 }
12538 }
12540 /* Allow SImode subregs of DImode addresses,
12541 they will be emitted with addr32 prefix. */
12543 {
12546 {
12550 }
12551 }
12556 {
12559 else
12561 }
12563 {
12568 do
12569 {
12574 }
12581 {
12584 {
12609 /* FALLTHRU */
12613 && TARGET_TLS_DIRECT_SEG_REFS
12616 else
12623 /* FALLTHRU */
12630 else
12645 }
12646 }
12647 }
12649 {
12652 }
12654 {
12655 /* We're called for lea too, which implements ashift on occasion. */
12665 }
12666 else
12670 {
12672 ;
12675 ;
12676 else
12678 }
12680 /* Extract the integral value of scale. */
12682 {
12686 }
12691 /* Avoid useless 0 displacement. */
12695 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12700 {
12703 }
12705 /* Special case: %ebp cannot be encoded as a base without a displacement.
12706 Similarly %r13. */
12708 && base_reg
12717 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12718 Avoid this by transforming to [%esi+0].
12719 Reload calls address legitimization without cfun defined, so we need
12720 to test cfun for being non-NULL. */
12726 /* Special case: encode reg+reg instead of reg*2. */
12730 /* Special case: scaling cannot be encoded without base or displacement. */
12741 }
12742 \f
12743 /* Return cost of the memory address x.
12744 For i386, it is better to use a complex address than let gcc copy
12745 the address into a reg and make a new pseudo. But not if the address
12746 requires to two regs - that would mean more pseudos with longer
12747 lifetimes. */
12748 static int
12750 {
12762 /* Attempt to minimize number of registers in the address. */
12768 cost++;
12770 /* When address base or index is "pic_offset_table_rtx" we don't increase
12771 address cost. When a memopt with "pic_offset_table_rtx" is not invariant
12772 itself it most likely means that base or index is not invariant.
12773 Therefore only "pic_offset_table_rtx" could be hoisted out, which is not
12774 profitable for x86. */
12776 && (!pic_offset_table_rtx
12780 && (!pic_offset_table_rtx
12784 cost++;
12786 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12787 since it's predecode logic can't detect the length of instructions
12788 and it degenerates to vector decoded. Increase cost of such
12789 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12790 to split such addresses or even refuse such addresses at all.
12792 Following addressing modes are affected:
12793 [base+scale*index]
12794 [scale*index+disp]
12795 [base+index]
12797 The first and last case may be avoidable by explicitly coding the zero in
12798 memory address, but I don't have AMD-K6 machine handy to check this
12799 theory. */
12808 }
12809 \f
12810 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12811 this is used for to form addresses to local data when -fPIC is in
12812 use. */
12814 static bool
12816 {
12819 }
12821 /* Determine if a given RTX is a valid constant. We already know this
12822 satisfies CONSTANT_P. */
12824 static bool
12826 {
12827 /* Pointer bounds constants are not valid. */
12832 {
12837 {
12841 }
12846 /* Only some unspecs are valid as "constants". */
12849 {
12865 }
12867 /* We must have drilled down to a symbol. */
12872 /* FALLTHRU */
12875 /* TLS symbols are never valid. */
12879 /* DLLIMPORT symbols are never valid. */
12884 #if TARGET_MACHO
12885 /* mdynamic-no-pic */
12888 #endif
12904 }
12906 /* Otherwise we handle everything else in the move patterns. */
12908 }
12910 /* Determine if it's legal to put X into the constant pool. This
12911 is not possible for the address of thread-local symbols, which
12912 is checked above. */
12914 static bool
12916 {
12917 /* We can always put integral constants and vectors in memory. */
12919 {
12927 }
12929 }
12931 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12932 otherwise zero. */
12934 static bool
12936 {
12942 }
12945 /* Nonzero if the constant value X is a legitimate general operand
12946 when generating PIC code. It is given that flag_pic is on and
12947 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12949 bool
12951 {
12952 rtx inner;
12955 {
12962 /* Only some unspecs are valid as "constants". */
12965 {
12978 }
12979 /* FALLTHRU */
12987 }
12988 }
12990 /* Determine if a given CONST RTX is a valid memory displacement
12991 in PIC mode. */
12993 bool
12995 {
12998 /* In 64bit mode we can allow direct addresses of symbols and labels
12999 when they are not dynamic symbols. */
13001 {
13005 {
13029 /* FALLTHRU */
13032 /* TLS references should always be enclosed in UNSPEC.
13033 The dllimported symbol needs always to be resolved. */
13039 {
13047 /* Function-symbols need to be resolved only for
13048 large-model.
13049 For the small-model we don't need to resolve anything
13050 here. */
13055 /* Non-external symbols don't need to be resolved for
13056 large, and medium-model. */
13061 }
13070 }
13071 }
13077 {
13078 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13079 of GOT tables. We should not need these anyway. */
13091 }
13095 {
13100 }
13109 {
13113 /* We need to check for both symbols and labels because VxWorks loads
13114 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13115 details. */
13119 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13120 While ABI specify also 32bit relocation but we don't produce it in
13121 small PIC model at all. */
13143 }
13146 }
13148 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
13149 replace the input X, or the original X if no replacement is called for.
13150 The output parameter *WIN is 1 if the calling macro should goto WIN,
13151 0 if it should not. */
13153 bool
13156 {
13157 /* Reload can generate:
13159 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
13160 (reg:DI 97))
13161 (reg:DI 2 cx))
13163 This RTX is rejected from ix86_legitimate_address_p due to
13164 non-strictness of base register 97. Following this rejection,
13165 reload pushes all three components into separate registers,
13166 creating invalid memory address RTX.
13168 Following code reloads only the invalid part of the
13169 memory address RTX. */
13175 {
13181 {
13186 }
13190 {
13195 }
13199 }
13202 }
13204 /* Determine if op is suitable RTX for an address register.
13205 Return naked register if a register or a register subreg is
13206 found, otherwise return NULL_RTX. */
13208 static rtx
13210 {
13213 /* Only SImode or DImode registers can form the address. */
13220 {
13228 /* Don't allow SUBREGs that span more than a word. It can
13229 lead to spill failures when the register is one word out
13230 of a two word structure. */
13234 /* Allow only SUBREGs of non-eliminable hard registers. */
13237 }
13239 /* Op is not a register. */
13241 }
13243 /* Recognizes RTL expressions that are valid memory addresses for an
13244 instruction. The MODE argument is the machine mode for the MEM
13245 expression that wants to use this address.
13247 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13248 convert common non-canonical forms to canonical form so that they will
13249 be recognized. */
13251 static bool
13253 {
13256 HOST_WIDE_INT scale;
13260 /* Decomposition failed. */
13269 /* Validate base register. */
13271 {
13279 /* Base is not valid. */
13281 }
13283 /* Validate index register. */
13285 {
13293 /* Index is not valid. */
13295 }
13297 /* Index and base should have the same mode. */
13302 /* Address override works only on the (%reg) part of %fs:(%reg). */
13308 /* Validate scale factor. */
13310 {
13312 /* Scale without index. */
13316 /* Scale is not a valid multiplier. */
13318 }
13320 /* Validate displacement. */
13322 {
13327 {
13328 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13329 used. While ABI specify also 32bit relocations, we don't produce
13330 them at all and use IP relative instead. */
13337 /* 64bit address unspec. */
13357 /* Invalid address unspec. */
13359 }
13362 && (flag_pic
13363 || (TARGET_MACHO
13364 #if TARGET_MACHO
13365 && MACHOPIC_INDIRECT
13367 #endif
13368 )))
13369 {
13371 is_legitimate_pic:
13373 {
13374 /* foo@dtpoff(%rX) is ok. */
13381 /* Non-constant pic memory reference. */
13383 }
13386 /* Displacement is an invalid pic construct. */
13388 #if TARGET_MACHO
13391 /* displacment must be referenced via non_lazy_pointer */
13393 #endif
13395 /* This code used to verify that a symbolic pic displacement
13396 includes the pic_offset_table_rtx register.
13398 While this is good idea, unfortunately these constructs may
13399 be created by "adds using lea" optimization for incorrect
13400 code like:
13402 int a;
13403 int foo(int i)
13404 {
13405 return *(&a+i);
13406 }
13408 This code is nonsensical, but results in addressing
13409 GOT table with pic_offset_table_rtx base. We can't
13410 just refuse it easily, since it gets matched by
13411 "addsi3" pattern, that later gets split to lea in the
13412 case output register differs from input. While this
13413 can be handled by separate addsi pattern for this case
13414 that never results in lea, this seems to be easier and
13415 correct fix for crash to disable this test. */
13416 }
13423 /* Displacement is not constant. */
13427 /* Displacement is out of range. */
13429 /* In x32 mode, constant addresses are sign extended to 64bit, so
13430 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13435 }
13437 /* Everything looks valid. */
13439 }
13441 /* Determine if a given RTX is a valid constant address. */
13443 bool
13445 {
13447 }
13448 \f
13449 /* Return a unique alias set for the GOT. */
13451 static alias_set_type
13453 {
13458 }
13460 /* Set regs_ever_live for PIC base address register
13461 to true if required. */
13462 static void
13464 {
13467 }
13469 /* Return a legitimate reference for ORIG (an address) using the
13470 register REG. If REG is 0, a new pseudo is generated.
13472 There are two types of references that must be handled:
13474 1. Global data references must load the address from the GOT, via
13475 the PIC reg. An insn is emitted to do this load, and the reg is
13476 returned.
13478 2. Static data references, constant pool addresses, and code labels
13479 compute the address as an offset from the GOT, whose base is in
13480 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13481 differentiate them from global data objects. The returned
13482 address is the PIC reg + an unspec constant.
13484 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13485 reg also appears in the address. */
13487 static rtx
13489 {
13493 #if TARGET_MACHO
13495 {
13498 /* Use the generic Mach-O PIC machinery. */
13500 }
13501 #endif
13504 {
13508 }
13514 {
13515 rtx tmpreg;
13516 /* This symbol may be referenced via a displacement from the PIC
13517 base address (@GOTOFF). */
13523 {
13525 UNSPEC_GOTOFF);
13527 }
13528 else
13533 else
13538 {
13542 }
13543 else
13545 }
13547 {
13548 /* This symbol may be referenced via a displacement from the PIC
13549 base address (@GOTOFF). */
13555 {
13557 UNSPEC_GOTOFF);
13559 }
13560 else
13566 {
13569 }
13570 }
13572 /* We can't use @GOTOFF for text labels on VxWorks;
13573 see gotoff_operand. */
13575 {
13580 /* For x64 PE-COFF there is no GOT table. So we use address
13581 directly. */
13583 {
13591 }
13593 {
13601 /* Use directly gen_movsi, otherwise the address is loaded
13602 into register for CSE. We don't want to CSE this addresses,
13603 instead we CSE addresses from the GOT table, so skip this. */
13606 }
13607 else
13608 {
13609 /* This symbol must be referenced via a load from the
13610 Global Offset Table (@GOT). */
13625 }
13626 }
13627 else
13628 {
13631 {
13633 {
13636 }
13637 else
13639 }
13641 {
13644 /* We must match stuff we generate before. Assume the only
13645 unspecs that can get here are ours. Not that we could do
13646 anything with them anyway.... */
13652 }
13654 {
13657 /* Check first to see if this is a constant offset from a @GOTOFF
13658 symbol reference. */
13661 {
13663 {
13666 UNSPEC_GOTOFF);
13672 {
13675 }
13676 }
13677 else
13678 {
13681 {
13685 }
13686 }
13687 }
13688 else
13689 {
13692 new_rtx
13696 {
13699 {
13702 new_rtx
13704 }
13705 else
13707 }
13708 else
13709 {
13712 {
13715 }
13717 }
13718 }
13719 }
13720 }
13722 }
13723 \f
13724 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13726 static rtx
13728 {
13732 {
13737 }
13743 }
13745 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13749 static rtx
13751 {
13753 {
13759 }
13762 {
13764 UNSPEC_PLTOFF);
13767 }
13770 }
13772 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13776 rtx
13778 {
13780 {
13781 ix86_tls_module_base_symbol
13786 }
13789 }
13791 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13792 false if we expect this to be used for a memory address and true if
13793 we expect to load the address into a register. */
13795 static rtx
13797 {
13803 /* Fall back to global dynamic model if tool chain cannot support local
13804 dynamic. */
13811 {
13816 {
13819 else
13820 {
13823 }
13824 }
13827 {
13830 else
13840 }
13841 else
13842 {
13846 {
13851 emit_call_insn
13861 }
13862 else
13864 }
13871 {
13874 else
13875 {
13878 }
13879 }
13882 {
13887 else
13893 }
13894 else
13895 {
13899 {
13902 rtx eqv;
13905 emit_call_insn
13910 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13911 share the LD_BASE result with other LD model accesses. */
13913 UNSPEC_TLS_LD_BASE);
13917 }
13918 else
13920 }
13928 {
13935 }
13940 {
13942 {
13943 /* The Sun linker took the AMD64 TLS spec literally
13944 and can only handle %rax as destination of the
13945 initial executable code sequence. */
13950 }
13952 /* Generate DImode references to avoid %fs:(%reg32)
13953 problems and linker IE->LE relaxation bug. */
13957 }
13959 {
13963 }
13965 {
13969 }
13970 else
13971 {
13974 }
13984 {
13989 }
13990 else
13991 {
13995 }
14005 {
14009 }
14010 else
14011 {
14015 }
14020 }
14023 }
14025 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14026 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14027 unique refptr-DECL symbol corresponding to symbol DECL. */
14030 htab_t dllimport_map;
14032 static tree
14034 {
14041 tree to;
14042 rtx rtl;
14069 else
14082 {
14084 #ifdef SUB_TARGET_RECORD_STUB
14086 #endif
14087 }
14096 }
14098 /* Expand SYMBOL into its corresponding far-addresse symbol.
14099 WANT_REG is true if we require the result be a register. */
14101 static rtx
14103 {
14104 tree imp_decl;
14105 rtx x;
14114 }
14116 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14117 true if we require the result be a register. */
14119 static rtx
14121 {
14122 tree imp_decl;
14123 rtx x;
14132 }
14134 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14135 is true if we require the result be a register. */
14137 static rtx
14139 {
14144 {
14151 {
14154 }
14155 }
14171 {
14174 }
14176 }
14178 /* Try machine-dependent ways of modifying an illegitimate address
14179 to be legitimate. If we find one, return the new, valid address.
14180 This macro is used in only one place: `memory_address' in explow.c.
14182 OLDX is the address as it was before break_out_memory_refs was called.
14183 In some cases it is useful to look at this to decide what needs to be done.
14185 It is always safe for this macro to do nothing. It exists to recognize
14186 opportunities to optimize the output.
14188 For the 80386, we handle X+REG by loading X into a register R and
14189 using R+REG. R will go in a general reg and indexing will be used.
14190 However, if REG is a broken-out memory address or multiplication,
14191 nothing needs to be done because REG can certainly go in a general reg.
14193 When -fpic is used, special handling is needed for symbolic references.
14194 See comments by legitimize_pic_address in i386.c for details. */
14196 static rtx
14198 {
14209 {
14213 }
14216 {
14220 }
14225 #if TARGET_MACHO
14228 #endif
14230 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14234 {
14239 }
14242 {
14243 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14248 {
14254 }
14259 {
14265 }
14267 /* Put multiply first if it isn't already. */
14269 {
14274 }
14276 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14277 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14278 created by virtual register instantiation, register elimination, and
14279 similar optimizations. */
14281 {
14287 }
14289 /* Canonicalize
14290 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14291 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14296 {
14297 rtx constant;
14301 {
14304 }
14306 {
14309 }
14310 else
14314 {
14321 }
14322 }
14328 {
14331 }
14334 {
14337 }
14345 {
14348 }
14354 {
14358 {
14361 }
14365 }
14368 {
14372 {
14375 }
14379 }
14380 }
14383 }
14384 \f
14385 /* Print an integer constant expression in assembler syntax. Addition
14386 and subtraction are the only arithmetic that may appear in these
14387 expressions. FILE is the stdio stream to write to, X is the rtx, and
14388 CODE is the operand print code from the output string. */
14390 static void
14392 {
14396 {
14405 else
14406 {
14409 /* Mark the decl as referenced so that cgraph will
14410 output the function. */
14414 #if TARGET_MACHO
14418 #endif
14420 }
14428 /* FALLTHRU */
14439 /* This used to output parentheses around the expression,
14440 but that does not work on the 386 (either ATT or BSD assembler). */
14446 {
14447 /* We can use %d if the number is <32 bits and positive. */
14452 else
14454 }
14455 else
14456 /* We can't handle floating point constants;
14457 TARGET_PRINT_OPERAND must handle them. */
14462 /* Some assemblers need integer constants to appear first. */
14464 {
14468 }
14469 else
14470 {
14475 }
14490 {
14494 }
14499 {
14518 /* FIXME: This might be @TPOFF in Sun ld too. */
14527 else
14537 else
14543 #if TARGET_MACHO
14548 #endif
14552 }
14557 }
14558 }
14560 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14561 We need to emit DTP-relative relocations. */
14563 static void ATTRIBUTE_UNUSED
14565 {
14570 {
14578 }
14579 }
14581 /* Return true if X is a representation of the PIC register. This copes
14582 with calls from ix86_find_base_term, where the register might have
14583 been replaced by a cselib value. */
14585 static bool
14587 {
14594 {
14602 }
14603 else
14605 }
14607 /* Helper function for ix86_delegitimize_address.
14608 Attempt to delegitimize TLS local-exec accesses. */
14610 static rtx
14612 {
14637 {
14642 }
14648 }
14650 /* In the name of slightly smaller debug output, and to cater to
14651 general assembler lossage, recognize PIC+GOTOFF and turn it back
14652 into a direct symbol reference.
14654 On Darwin, this is necessary to avoid a crash, because Darwin
14655 has a different PIC label for each routine but the DWARF debugging
14656 information is not associated with any particular routine, so it's
14657 necessary to remove references to the PIC label from RTL stored by
14658 the DWARF output code. */
14660 static rtx
14662 {
14664 /* addend is NULL or some rtx if x is something+GOTOFF where
14665 something doesn't include the PIC register. */
14667 /* reg_addend is NULL or a multiple of some register. */
14669 /* const_addend is NULL or a const_int. */
14671 /* This is the result, or NULL. */
14680 {
14687 {
14693 }
14700 {
14703 {
14708 }
14710 }
14715 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14716 and -mcmodel=medium -fpic. */
14717 }
14724 /* %ebx + GOT/GOTOFF */
14725 ;
14727 {
14728 /* %ebx + %reg * scale + GOT/GOTOFF */
14734 else
14735 {
14738 }
14739 }
14740 else
14746 {
14749 }
14770 {
14771 /* If the rest of original X doesn't involve the PIC register, add
14772 addend and subtract pic_offset_table_rtx. This can happen e.g.
14773 for code like:
14774 leal (%ebx, %ecx, 4), %ecx
14775 ...
14776 movl foo@GOTOFF(%ecx), %edx
14777 in which case we return (%ecx - %ebx) + foo
14778 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
14779 and reload has completed. */
14783 pic_offset_table_rtx),
14784 result);
14786 {
14790 }
14791 else
14793 }
14795 {
14799 }
14801 }
14803 /* If X is a machine specific address (i.e. a symbol or label being
14804 referenced as a displacement from the GOT implemented using an
14805 UNSPEC), then return the base term. Otherwise return X. */
14807 rtx
14809 {
14810 rtx term;
14813 {
14827 }
14830 }
14831 \f
14832 static void
14835 {
14839 {
14842 }
14847 {
14850 {
14869 }
14873 {
14892 }
14899 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14900 Those same assemblers have the same but opposite lossage on cmov. */
14903 else
14908 {
14921 }
14928 else
14933 {
14946 }
14953 else
14963 else
14974 }
14976 }
14978 /* Print the name of register X to FILE based on its machine mode and number.
14979 If CODE is 'w', pretend the mode is HImode.
14980 If CODE is 'b', pretend the mode is QImode.
14981 If CODE is 'k', pretend the mode is SImode.
14982 If CODE is 'q', pretend the mode is DImode.
14983 If CODE is 'x', pretend the mode is V4SFmode.
14984 If CODE is 't', pretend the mode is V8SFmode.
14985 If CODE is 'g', pretend the mode is V16SFmode.
14986 If CODE is 'h', pretend the reg is the 'high' byte register.
14987 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14988 If CODE is 'd', duplicate the operand for AVX instruction.
14989 */
14991 void
14993 {
15002 {
15006 }
15033 else
15036 /* Irritatingly, AMD extended registers use different naming convention
15037 from the normal registers: "r%d[bwd]" */
15039 {
15044 {
15058 /* no suffix */
15063 }
15065 }
15069 {
15072 {
15075 }
15076 /* FALLTHRU */
15082 /* FALLTHRU */
15085 normal:
15100 {
15105 }
15108 {
15113 }
15117 }
15121 {
15124 else
15126 }
15127 }
15129 /* Meaning of CODE:
15130 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15131 C -- print opcode suffix for set/cmov insn.
15132 c -- like C, but print reversed condition
15133 F,f -- likewise, but for floating-point.
15134 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15135 otherwise nothing
15136 R -- print embeded rounding and sae.
15137 r -- print only sae.
15138 z -- print the opcode suffix for the size of the current operand.
15139 Z -- likewise, with special suffixes for x87 instructions.
15140 * -- print a star (in certain assembler syntax)
15141 A -- print an absolute memory reference.
15142 E -- print address with DImode register names if TARGET_64BIT.
15143 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15144 s -- print a shift double count, followed by the assemblers argument
15145 delimiter.
15146 b -- print the QImode name of the register for the indicated operand.
15147 %b0 would print %al if operands[0] is reg 0.
15148 w -- likewise, print the HImode name of the register.
15149 k -- likewise, print the SImode name of the register.
15150 q -- likewise, print the DImode name of the register.
15151 x -- likewise, print the V4SFmode name of the register.
15152 t -- likewise, print the V8SFmode name of the register.
15153 g -- likewise, print the V16SFmode name of the register.
15154 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15155 y -- print "st(0)" instead of "st" as a register.
15156 d -- print duplicated register operand for AVX instruction.
15157 D -- print condition for SSE cmp instruction.
15158 P -- if PIC, print an @PLT suffix.
15159 p -- print raw symbol name.
15160 X -- don't print any sort of PIC '@' suffix for a symbol.
15161 & -- print some in-use local-dynamic symbol name.
15162 H -- print a memory address offset by 8; used for sse high-parts
15163 Y -- print condition for XOP pcom* instruction.
15164 + -- print a branch hint as 'cs' or 'ds' prefix
15165 ; -- print a semicolon (after prefixes due to bug in older gas).
15166 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15167 @ -- print a segment register of thread base pointer load
15168 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15169 ! -- print MPX prefix for jxx/call/ret instructions if required.
15170 */
15172 void
15174 {
15176 {
15178 {
15181 {
15187 /* Intel syntax. For absolute addresses, registers should not
15188 be surrounded by braces. */
15190 {
15195 }
15200 }
15206 /* Wrap address in an UNSPEC to declare special handling. */
15244 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15249 {
15263 output_operand_lossage
15266 }
15269 #endif
15274 {
15275 /* Opcodes don't get size suffixes if using Intel opcodes. */
15280 {
15298 output_operand_lossage
15301 }
15302 }
15305 warning
15307 /* FALLTHRU */
15310 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15315 {
15317 {
15319 #ifdef HAVE_AS_IX86_FILDS
15321 #endif
15329 #ifdef HAVE_AS_IX86_FILDQ
15331 #else
15333 #endif
15338 }
15339 }
15341 {
15342 /* 387 opcodes don't get size suffixes
15343 if the operands are registers. */
15348 {
15364 }
15365 }
15366 else
15367 {
15368 output_operand_lossage
15371 }
15373 output_operand_lossage
15394 {
15397 }
15402 {
15453 }
15457 /* Little bit of braindamage here. The SSE compare instructions
15458 does use completely different names for the comparisons that the
15459 fp conditional moves. */
15461 {
15464 {
15467 }
15473 {
15476 }
15482 {
15485 }
15494 {
15497 }
15503 {
15506 }
15512 {
15515 }
15526 }
15531 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15534 #endif
15539 {
15543 }
15547 file);
15552 {
15556 }
15557 /* It doesn't actually matter what mode we use here, as we're
15558 only going to use this for printing. */
15560 /* Output 'qword ptr' for intel assembler dialect. */
15569 #ifdef HAVE_AS_IX86_HLE
15571 #else
15573 #endif
15575 #ifdef HAVE_AS_IX86_HLE
15577 #else
15579 #endif
15580 /* We do not want to print value of the operand. */
15609 {
15624 }
15637 {
15642 else
15645 }
15648 {
15649 rtx x;
15658 {
15663 {
15665 bool cputaken
15668 /* Emit hints only in the case default branch prediction
15669 heuristics would fail. */
15671 {
15672 /* We use 3e (DS) prefix for taken branches and
15673 2e (CS) prefix for not taken branches. */
15676 else
15678 }
15679 }
15680 }
15682 }
15685 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15687 #endif
15694 /* The kernel uses a different segment register for performance
15695 reasons; a system call would not have to trash the userspace
15696 segment register, which would be expensive. */
15699 else
15719 }
15720 }
15726 {
15727 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15730 {
15733 {
15742 else
15749 }
15751 /* Check for explicit size override (codes 'b', 'w', 'k',
15752 'q' and 'x') */
15766 }
15769 /* Avoid (%rip) for call operands. */
15775 else
15777 }
15780 {
15781 REAL_VALUE_TYPE r;
15789 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15793 else
15795 }
15798 {
15799 REAL_VALUE_TYPE r;
15808 }
15810 /* These float cases don't actually occur as immediate operands. */
15812 {
15817 }
15819 else
15820 {
15821 /* We have patterns that allow zero sets of memory, for instance.
15822 In 64-bit mode, we should probably support all 8-byte vectors,
15823 since we can in fact encode that into an immediate. */
15825 {
15828 }
15831 {
15833 {
15836 }
15839 {
15842 else
15844 }
15845 }
15850 else
15852 }
15853 }
15855 static bool
15857 {
15860 }
15861 \f
15862 /* Print a memory operand whose address is ADDR. */
15864 static void
15866 {
15875 {
15882 }
15884 {
15888 }
15890 {
15894 {
15897 }
15900 }
15902 {
15907 }
15908 else
15919 {
15930 }
15932 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15934 {
15946 }
15948 {
15949 /* Displacement only requires special attention. */
15952 {
15956 }
15959 else
15961 }
15962 else
15963 {
15964 /* Print SImode register names to force addr32 prefix. */
15966 {
15967 #ifdef ENABLE_CHECKING
15970 {
15981 }
15982 #endif
15985 }
15987 && TARGET_X32
15988 && disp
15991 {
15992 /* X32 runs in 64-bit mode, where displacement, DISP, in
15993 address DISP(%r64), is encoded as 32-bit immediate sign-
15994 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15995 address is %r64 + 0xffffffffbffffd00. When %r64 <
15996 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15997 which is invalid for x32. The correct address is %r64
15998 - 0x40000300 == 0xf7ffdd64. To properly encode
15999 -0x40000300(%r64) for x32, we zero-extend negative
16000 displacement by forcing addr32 prefix which truncates
16001 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16002 zero-extend all negative displacements, including -1(%rsp).
16003 However, for small negative displacements, sign-extension
16004 won't cause overflow. We only zero-extend negative
16005 displacements if they < -16*1024*1024, which is also used
16006 to check legitimate address displacements for PIC. */
16008 }
16011 {
16013 {
16018 else
16020 }
16026 {
16031 }
16033 }
16034 else
16035 {
16039 {
16040 /* Pull out the offset of a symbol; print any symbol itself. */
16044 {
16048 }
16056 else
16058 }
16062 {
16065 {
16069 }
16070 }
16073 else
16077 {
16082 }
16084 }
16085 }
16086 }
16088 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16090 static bool
16092 {
16093 rtx op;
16100 {
16103 /* FIXME: This might be @TPOFF in Sun ld. */
16114 else
16126 else
16133 #if TARGET_MACHO
16139 #endif
16142 {
16147 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16149 #else
16151 #endif
16154 }
16159 }
16162 }
16163 \f
16164 /* Split one or more double-mode RTL references into pairs of half-mode
16165 references. The RTL can be REG, offsettable MEM, integer constant, or
16166 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16167 split and "num" is its length. lo_half and hi_half are output arrays
16168 that parallel "operands". */
16170 void
16173 {
16174 machine_mode half_mode;
16178 {
16187 }
16192 {
16195 /* simplify_subreg refuse to split volatile memory addresses,
16196 but we still have to handle it. */
16198 {
16201 }
16202 else
16203 {
16210 }
16211 }
16212 }
16213 \f
16214 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16215 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16216 is the expression of the binary operation. The output may either be
16217 emitted here, or returned to the caller, like all output_* functions.
16219 There is no guarantee that the operands are the same mode, as they
16220 might be within FLOAT or FLOAT_EXTEND expressions. */
16222 #ifndef SYSV386_COMPAT
16223 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16224 wants to fix the assemblers because that causes incompatibility
16225 with gcc. No-one wants to fix gcc because that causes
16226 incompatibility with assemblers... You can use the option of
16227 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16228 #define SYSV386_COMPAT 1
16229 #endif
16233 {
16239 #ifdef ENABLE_CHECKING
16240 /* Even if we do not want to check the inputs, this documents input
16241 constraints. Which helps in understanding the following code. */
16251 else
16253 #endif
16256 {
16261 else
16270 else
16279 else
16288 else
16295 }
16298 {
16300 {
16304 else
16306 }
16307 else
16308 {
16312 else
16314 }
16316 }
16320 {
16324 {
16328 }
16330 /* know operands[0] == operands[1]. */
16333 {
16336 }
16339 {
16341 /* How is it that we are storing to a dead operand[2]?
16342 Well, presumably operands[1] is dead too. We can't
16343 store the result to st(0) as st(0) gets popped on this
16344 instruction. Instead store to operands[2] (which I
16345 think has to be st(1)). st(1) will be popped later.
16346 gcc <= 2.8.1 didn't have this check and generated
16347 assembly code that the Unixware assembler rejected. */
16349 else
16352 }
16356 else
16363 {
16366 }
16369 {
16372 }
16375 {
16376 #if SYSV386_COMPAT
16377 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16378 derived assemblers, confusingly reverse the direction of
16379 the operation for fsub{r} and fdiv{r} when the
16380 destination register is not st(0). The Intel assembler
16381 doesn't have this brain damage. Read !SYSV386_COMPAT to
16382 figure out what the hardware really does. */
16385 else
16387 #else
16389 /* As above for fmul/fadd, we can't store to st(0). */
16391 else
16393 #endif
16395 }
16398 {
16399 #if SYSV386_COMPAT
16402 else
16404 #else
16407 else
16409 #endif
16411 }
16414 {
16417 else
16420 }
16422 {
16423 #if SYSV386_COMPAT
16425 #else
16427 #endif
16428 }
16429 else
16430 {
16431 #if SYSV386_COMPAT
16433 #else
16435 #endif
16436 }
16441 }
16445 }
16447 /* Check if a 256bit AVX register is referenced inside of EXP. */
16449 static bool
16451 {
16457 }
16459 /* Return needed mode for entity in optimize_mode_switching pass. */
16461 static int
16463 {
16465 {
16466 rtx link;
16468 /* Needed mode is set to AVX_U128_CLEAN if there are
16469 no 256bit modes used in function arguments. */
16471 link;
16473 {
16475 {
16480 }
16481 }
16484 }
16486 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16487 changes state only when a 256bit register is written to, but we need
16488 to prevent the compiler from moving optimal insertion point above
16489 eventual read from 256bit register. */
16496 }
16498 /* Return mode that i387 must be switched into
16499 prior to the execution of insn. */
16501 static int
16503 {
16506 /* The mode UNINITIALIZED is used to store control word after a
16507 function call or ASM pattern. The mode ANY specify that function
16508 has no requirements on the control word and make no changes in the
16509 bits we are interested in. */
16523 {
16546 }
16549 }
16551 /* Return mode that entity must be switched into
16552 prior to the execution of insn. */
16554 static int
16556 {
16558 {
16568 }
16570 }
16572 /* Check if a 256bit AVX register is referenced in stores. */
16574 static void
16576 {
16578 {
16581 }
16582 }
16584 /* Calculate mode of upper 128bit AVX registers after the insn. */
16586 static int
16588 {
16595 /* We know that state is clean after CALL insn if there are no
16596 256bit registers used in the function return register. */
16598 {
16603 }
16605 /* Otherwise, return current mode. Remember that if insn
16606 references AVX 256bit registers, the mode was already changed
16607 to DIRTY from MODE_NEEDED. */
16609 }
16611 /* Return the mode that an insn results in. */
16613 int
16615 {
16617 {
16627 }
16628 }
16630 static int
16632 {
16633 tree arg;
16635 /* Entry mode is set to AVX_U128_DIRTY if there are
16636 256bit modes used in function arguments. */
16639 {
16644 }
16647 }
16649 /* Return a mode that ENTITY is assumed to be
16650 switched to at function entry. */
16652 static int
16654 {
16656 {
16666 }
16667 }
16669 static int
16671 {
16674 /* Exit mode is set to AVX_U128_DIRTY if there are
16675 256bit modes used in the function return register. */
16680 }
16682 /* Return a mode that ENTITY is assumed to be
16683 switched to at function exit. */
16685 static int
16687 {
16689 {
16699 }
16700 }
16702 static int
16704 {
16706 }
16708 /* Output code to initialize control word copies used by trunc?f?i and
16709 rounding patterns. CURRENT_MODE is set to current control word,
16710 while NEW_MODE is set to new control word. */
16712 static void
16714 {
16716 rtx new_mode;
16727 {
16729 {
16731 /* round toward zero (truncate) */
16737 /* round down toward -oo */
16744 /* round up toward +oo */
16751 /* mask precision exception for nearbyint() */
16758 }
16759 }
16760 else
16761 {
16763 {
16765 /* round toward zero (truncate) */
16771 /* round down toward -oo */
16777 /* round up toward +oo */
16783 /* mask precision exception for nearbyint() */
16790 }
16791 }
16797 }
16799 /* Emit vzeroupper. */
16801 void
16803 {
16806 /* Cancel automatic vzeroupper insertion if there are
16807 live call-saved SSE registers at the insertion point. */
16819 }
16821 /* Generate one or more insns to set ENTITY to MODE. */
16823 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16824 is the set of hard registers live at the point where the insn(s)
16825 are to be inserted. */
16827 static void
16829 HARD_REG_SET regs_live)
16830 {
16832 {
16847 }
16848 }
16850 /* Output code for INSN to convert a float to a signed int. OPERANDS
16851 are the insn operands. The output may be [HSD]Imode and the input
16852 operand may be [SDX]Fmode. */
16856 {
16861 /* Jump through a hoop or two for DImode, since the hardware has no
16862 non-popping instruction. We used to do this a different way, but
16863 that was somewhat fragile and broke with post-reload splitters. */
16873 else
16874 {
16879 else
16883 }
16886 }
16888 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16889 have the values zero or one, indicates the ffreep insn's operand
16890 from the OPERANDS array. */
16894 {
16896 #ifdef HAVE_AS_IX86_FFREEP
16898 #else
16899 {
16909 }
16910 #endif
16913 }
16916 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16917 should be used. UNORDERED_P is true when fucom should be used. */
16921 {
16927 {
16930 }
16931 else
16932 {
16935 }
16938 {
16942 else
16944 else
16947 else
16949 }
16956 {
16958 {
16961 }
16962 else
16964 }
16967 && stack_top_dies
16970 {
16971 /* If both the top of the 387 stack dies, and the other operand
16972 is also a stack register that dies, then this must be a
16973 `fcompp' float compare */
16976 {
16977 /* There is no double popping fcomi variant. Fortunately,
16978 eflags is immune from the fstp's cc clobbering. */
16981 else
16984 }
16985 else
16986 {
16989 else
16991 }
16992 }
16993 else
16994 {
16995 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16998 {
17006 NULL,
17007 NULL,
17014 NULL,
17015 NULL,
17016 NULL,
17017 NULL
17018 };
17033 }
17034 }
17036 void
17038 {
17041 #ifdef ASM_QUAD
17044 #else
17046 #endif
17049 }
17051 void
17053 {
17056 #ifdef ASM_QUAD
17059 #else
17061 #endif
17062 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17068 #if TARGET_MACHO
17070 {
17074 }
17075 #endif
17076 else
17079 }
17080 \f
17081 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17082 for the target. */
17084 void
17086 {
17087 rtx tmp;
17089 /* We play register width games, which are only valid after reload. */
17092 /* Avoid HImode and its attendant prefix byte. */
17098 {
17101 }
17104 }
17106 /* X is an unchanging MEM. If it is a constant pool reference, return
17107 the constant pool rtx, else NULL. */
17109 rtx
17111 {
17118 }
17120 void
17122 {
17130 {
17131 rtx tmp;
17135 {
17141 }
17144 }
17148 {
17151 rtx tmp;
17156 else
17160 {
17167 }
17168 }
17172 {
17174 {
17175 #if TARGET_MACHO
17176 /* dynamic-no-pic */
17178 {
17179 rtx temp = ((reload_in_progress
17187 }
17189 {
17193 }
17196 else
17197 {
17205 }
17206 /* dynamic-no-pic */
17207 #endif
17208 }
17209 else
17210 {
17214 {
17220 }
17221 }
17222 }
17223 else
17224 {
17235 /* Force large constants in 64bit compilation into register
17236 to get them CSEed. */
17248 {
17249 /* If we are loading a floating point constant to a register,
17250 force the value to memory now, since we'll get better code
17251 out the back end. */
17255 {
17260 }
17261 }
17262 }
17265 }
17267 void
17269 {
17276 /* Force constants other than zero into memory. We do not know how
17277 the instructions used to build constants modify the upper 64 bits
17278 of the register, once we have that information we may be able
17279 to handle some of them more efficiently. */
17288 /* We need to check memory alignment for SSE mode since attribute
17289 can make operands unaligned. */
17294 {
17297 /* ix86_expand_vector_move_misalign() does not like constants ... */
17303 /* ... nor both arguments in memory. */
17311 }
17313 /* Make operand1 a register if it isn't already. */
17317 {
17320 }
17323 }
17325 /* Split 32-byte AVX unaligned load and store if needed. */
17327 static void
17329 {
17330 rtx m;
17334 machine_mode mode;
17337 {
17358 }
17361 {
17363 {
17370 }
17371 /* Normal *mov<mode>_internal pattern will handle
17372 unaligned loads just fine if misaligned_operand
17373 is true, and without the UNSPEC it can be combined
17374 with arithmetic instructions. */
17377 else
17379 }
17381 {
17383 {
17388 }
17389 else
17391 }
17392 else
17394 }
17396 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17397 straight to ix86_expand_vector_move. */
17398 /* Code generation for scalar reg-reg moves of single and double precision data:
17399 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17400 movaps reg, reg
17401 else
17402 movss reg, reg
17403 if (x86_sse_partial_reg_dependency == true)
17404 movapd reg, reg
17405 else
17406 movsd reg, reg
17408 Code generation for scalar loads of double precision data:
17409 if (x86_sse_split_regs == true)
17410 movlpd mem, reg (gas syntax)
17411 else
17412 movsd mem, reg
17414 Code generation for unaligned packed loads of single precision data
17415 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17416 if (x86_sse_unaligned_move_optimal)
17417 movups mem, reg
17419 if (x86_sse_partial_reg_dependency == true)
17420 {
17421 xorps reg, reg
17422 movlps mem, reg
17423 movhps mem+8, reg
17424 }
17425 else
17426 {
17427 movlps mem, reg
17428 movhps mem+8, reg
17429 }
17431 Code generation for unaligned packed loads of double precision data
17432 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17433 if (x86_sse_unaligned_move_optimal)
17434 movupd mem, reg
17436 if (x86_sse_split_regs == true)
17437 {
17438 movlpd mem, reg
17439 movhpd mem+8, reg
17440 }
17441 else
17442 {
17443 movsd mem, reg
17444 movhpd mem+8, reg
17445 }
17446 */
17448 void
17450 {
17459 {
17461 {
17465 {
17467 {
17470 }
17471 else
17473 }
17475 /* FALLTHRU */
17479 {
17494 }
17500 else
17508 }
17511 }
17515 {
17517 {
17521 {
17523 {
17526 }
17527 else
17529 }
17531 /* FALLTHRU */
17541 }
17544 }
17547 {
17548 /* Normal *mov<mode>_internal pattern will handle
17549 unaligned loads just fine if misaligned_operand
17550 is true, and without the UNSPEC it can be combined
17551 with arithmetic instructions. */
17557 /* ??? If we have typed data, then it would appear that using
17558 movdqu is the only way to get unaligned data loaded with
17559 integer type. */
17561 {
17563 {
17566 }
17568 /* We will eventually emit movups based on insn attributes. */
17572 }
17574 {
17575 rtx zero;
17578 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17579 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17581 {
17582 /* We will eventually emit movups based on insn attributes. */
17585 }
17587 /* When SSE registers are split into halves, we can avoid
17588 writing to the top half twice. */
17590 {
17593 }
17594 else
17595 {
17596 /* ??? Not sure about the best option for the Intel chips.
17597 The following would seem to satisfy; the register is
17598 entirely cleared, breaking the dependency chain. We
17599 then store to the upper half, with a dependency depth
17600 of one. A rumor has it that Intel recommends two movsd
17601 followed by an unpacklpd, but this is unconfirmed. And
17602 given that the dependency depth of the unpacklpd would
17603 still be one, I'm not sure why this would be better. */
17605 }
17611 }
17612 else
17613 {
17614 rtx t;
17617 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17618 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17620 {
17622 {
17625 }
17632 }
17636 else
17641 else
17650 }
17651 }
17653 {
17655 {
17658 /* We will eventually emit movups based on insn attributes. */
17660 }
17662 {
17664 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17665 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17667 /* We will eventually emit movups based on insn attributes. */
17669 else
17670 {
17675 }
17676 }
17677 else
17678 {
17683 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17684 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17686 {
17689 }
17690 else
17691 {
17696 }
17697 }
17698 }
17699 else
17701 }
17703 /* Helper function of ix86_fixup_binary_operands to canonicalize
17704 operand order. Returns true if the operands should be swapped. */
17706 static bool
17708 rtx operands[])
17709 {
17714 /* If the operation is not commutative, we can't do anything. */
17718 /* Highest priority is that src1 should match dst. */
17724 /* Next highest priority is that immediate constants come second. */
17730 /* Lowest priority is that memory references should come second. */
17737 }
17740 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17741 destination to use for the operation. If different from the true
17742 destination in operands[0], a copy operation will be required. */
17744 rtx
17746 rtx operands[])
17747 {
17752 /* Canonicalize operand order. */
17754 {
17755 /* It is invalid to swap operands of different modes. */
17759 }
17761 /* Both source operands cannot be in memory. */
17763 {
17764 /* Optimization: Only read from memory once. */
17766 {
17769 }
17772 else
17774 }
17776 /* If the destination is memory, and we do not have matching source
17777 operands, do things in registers. */
17781 /* Source 1 cannot be a constant. */
17785 /* Source 1 cannot be a non-matching memory. */
17789 /* Improve address combine. */
17798 }
17800 /* Similarly, but assume that the destination has already been
17801 set up properly. */
17803 void
17806 {
17809 }
17811 /* Attempt to expand a binary operator. Make the expansion closer to the
17812 actual machine, then just general_operand, which will allow 3 separate
17813 memory references (one output, two input) in a single insn. */
17815 void
17817 rtx operands[])
17818 {
17825 /* Emit the instruction. */
17829 {
17830 /* Reload doesn't know about the flags register, and doesn't know that
17831 it doesn't want to clobber it. We can only do this with PLUS. */
17834 }
17838 {
17839 /* This is going to be an LEA; avoid splitting it later. */
17841 }
17842 else
17843 {
17846 }
17848 /* Fix up the destination if needed. */
17851 }
17853 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17854 the given OPERANDS. */
17856 void
17858 rtx operands[])
17859 {
17862 {
17865 }
17867 {
17870 }
17871 /* Optimize (__m128i) d | (__m128i) e and similar code
17872 when d and e are float vectors into float vector logical
17873 insn. In C/C++ without using intrinsics there is no other way
17874 to express vector logical operation on float vectors than
17875 to cast them temporarily to integer vectors. */
17877 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17886 {
17887 rtx dst;
17889 {
17898 {
17901 }
17902 else
17903 {
17908 }
17919 }
17920 }
17929 }
17931 /* Return TRUE or FALSE depending on whether the binary operator meets the
17932 appropriate constraints. */
17934 bool
17937 {
17942 /* Both source operands cannot be in memory. */
17946 /* Canonicalize operand order for commutative operators. */
17950 /* If the destination is memory, we must have a matching source operand. */
17954 /* Source 1 cannot be a constant. */
17958 /* Source 1 cannot be a non-matching memory. */
17960 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17968 }
17970 /* Attempt to expand a unary operator. Make the expansion closer to the
17971 actual machine, then just general_operand, which will allow 2 separate
17972 memory references (one output, one input) in a single insn. */
17974 void
17976 rtx operands[])
17977 {
17984 /* If the destination is memory, and we do not have matching source
17985 operands, do things in registers. */
17988 {
17991 else
17993 }
17995 /* When source operand is memory, destination must match. */
17999 /* Emit the instruction. */
18003 {
18004 /* Reload doesn't know about the flags register, and doesn't know that
18005 it doesn't want to clobber it. */
18008 }
18009 else
18010 {
18013 }
18015 /* Fix up the destination if needed. */
18018 }
18020 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18021 divisor are within the range [0-255]. */
18023 void
18026 {
18035 {
18048 }
18055 /* Use 8bit unsigned divimod if dividend and divisor are within
18056 the range [0-255]. */
18065 pc_rtx);
18070 /* Generate original signed/unsigned divimod. */
18075 /* Branch to the end. */
18079 /* Generate 8bit unsigned divide. */
18081 /* Don't use operands[0] for result of 8bit divide since not all
18082 registers support QImode ZERO_EXTRACT. */
18089 {
18092 }
18093 else
18094 {
18097 }
18099 /* Extract remainder from AH. */
18103 else
18104 {
18105 /* Need a new scratch register since the old one has result
18106 of 8bit divide. */
18110 }
18113 /* Zero extend quotient from AL. */
18119 }
18121 #define LEA_MAX_STALL (3)
18122 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18124 /* Increase given DISTANCE in half-cycles according to
18125 dependencies between PREV and NEXT instructions.
18126 Add 1 half-cycle if there is no dependency and
18127 go to next cycle if there is some dependecy. */
18129 static unsigned int
18131 {
18147 }
18149 /* Function checks if instruction INSN defines register number
18150 REGNO1 or REGNO2. */
18152 static bool
18154 rtx insn)
18155 {
18156 df_ref def;
18166 }
18168 /* Function checks if instruction INSN uses register number
18169 REGNO as a part of address expression. */
18171 static bool
18173 {
18174 df_ref use;
18181 }
18183 /* Search backward for non-agu definition of register number REGNO1
18184 or register number REGNO2 in basic block starting from instruction
18185 START up to head of basic block or instruction INSN.
18187 Function puts true value into *FOUND var if definition was found
18188 and false otherwise.
18190 Distance in half-cycles between START and found instruction or head
18191 of BB is added to DISTANCE and returned. */
18193 static int
18197 {
18207 {
18209 {
18212 {
18215 {
18218 }
18219 }
18222 }
18227 }
18230 }
18232 /* Search backward for non-agu definition of register number REGNO1
18233 or register number REGNO2 in INSN's basic block until
18234 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18235 2. Reach neighbour BBs boundary, or
18236 3. Reach agu definition.
18237 Returns the distance between the non-agu definition point and INSN.
18238 If no definition point, returns -1. */
18240 static int
18243 {
18254 {
18255 edge e;
18256 edge_iterator ei;
18261 {
18264 }
18270 else
18271 {
18276 {
18277 int bb_dist
18283 {
18290 }
18291 }
18294 }
18295 }
18297 /* get_attr_type may modify recog data. We want to make sure
18298 that recog data is valid for instruction INSN, on which
18299 distance_non_agu_define is called. INSN is unchanged here. */
18306 }
18308 /* Return the distance in half-cycles between INSN and the next
18309 insn that uses register number REGNO in memory address added
18310 to DISTANCE. Return -1 if REGNO0 is set.
18312 Put true value into *FOUND if register usage was found and
18313 false otherwise.
18314 Put true value into *REDEFINED if register redefinition was
18315 found and false otherwise. */
18317 static int
18321 {
18330 {
18333 /* If insn and start belong to the same bb, set prev to insn,
18334 so the call to increase_distance will increase the distance
18335 between insns by 1. */
18337 }
18342 {
18344 {
18347 {
18348 /* Return DISTANCE if OP0 is used in memory
18349 address in NEXT. */
18352 }
18355 {
18356 /* Return -1 if OP0 is set in NEXT. */
18359 }
18362 }
18368 }
18371 }
18373 /* Return the distance between INSN and the next insn that uses
18374 register number REGNO0 in memory address. Return -1 if no such
18375 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18377 static int
18379 {
18391 {
18392 edge e;
18393 edge_iterator ei;
18398 {
18401 }
18407 else
18408 {
18414 {
18415 int bb_dist
18420 {
18427 }
18428 }
18431 }
18432 }
18438 }
18440 /* Define this macro to tune LEA priority vs ADD, it take effect when
18441 there is a dilemma of choicing LEA or ADD
18442 Negative value: ADD is more preferred than LEA
18443 Zero: Netrual
18444 Positive value: LEA is more preferred than ADD*/
18445 #define IX86_LEA_PRIORITY 0
18447 /* Return true if usage of lea INSN has performance advantage
18448 over a sequence of instructions. Instructions sequence has
18449 SPLIT_COST cycles higher latency than lea latency. */
18451 static bool
18454 {
18457 /* For Silvermont if using a 2-source or 3-source LEA for
18458 non-destructive destination purposes, or due to wanting
18459 ability to use SCALE, the use of LEA is justified. */
18461 {
18469 }
18475 {
18476 /* If there is no non AGU operand definition, no AGU
18477 operand usage and split cost is 0 then both lea
18478 and non lea variants have same priority. Currently
18479 we prefer lea for 64 bit code and non lea on 32 bit
18480 code. */
18483 else
18485 }
18487 /* With longer definitions distance lea is more preferable.
18488 Here we change it to take into account splitting cost and
18489 lea priority. */
18492 /* If there is no use in memory addess then we just check
18493 that split cost exceeds AGU stall. */
18497 /* If this insn has both backward non-agu dependence and forward
18498 agu dependence, the one with short distance takes effect. */
18500 }
18502 /* Return true if it is legal to clobber flags by INSN and
18503 false otherwise. */
18505 static bool
18507 {
18509 df_ref use;
18510 bitmap live;
18513 {
18515 {
18522 }
18528 }
18532 }
18534 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18535 move and add to avoid AGU stalls. */
18537 bool
18539 {
18542 /* Check if we need to optimize. */
18546 /* Check it is correct to split here. */
18554 /* We need to split only adds with non destructive
18555 destination operand. */
18558 else
18560 }
18562 /* Return true if we should emit lea instruction instead of mov
18563 instruction. */
18565 bool
18567 {
18570 /* Check if we need to optimize. */
18574 /* Use lea for reg to reg moves only. */
18582 }
18584 /* Return true if we need to split lea into a sequence of
18585 instructions to avoid AGU stalls. */
18587 bool
18589 {
18595 /* Check we need to optimize. */
18599 /* The "at least two components" test below might not catch simple
18600 move or zero extension insns if parts.base is non-NULL and parts.disp
18601 is const0_rtx as the only components in the address, e.g. if the
18602 register is %rbp or %r13. As this test is much cheaper and moves or
18603 zero extensions are the common case, do this check first. */
18609 /* Check if it is OK to split here. */
18616 /* There should be at least two components in the address. */
18621 /* We should not split into add if non legitimate pic
18622 operand is used as displacement. */
18637 /* Compute how many cycles we will add to execution time
18638 if split lea into a sequence of instructions. */
18640 {
18641 /* Have to use mov instruction if non desctructive
18642 destination form is used. */
18646 /* Have to add index to base if both exist. */
18650 /* Have to use shift and adds if scale is 2 or greater. */
18652 {
18657 else
18659 }
18661 /* Have to use add instruction with immediate if
18662 disp is non zero. */
18666 /* Subtract the price of lea. */
18668 }
18672 }
18674 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18675 matches destination. RTX includes clobber of FLAGS_REG. */
18677 static void
18680 {
18687 }
18689 /* Return true if regno1 def is nearest to the insn. */
18691 static bool
18693 {
18700 {
18702 {
18705 }
18711 }
18713 /* None of the regs is defined in the bb. */
18715 }
18717 /* Split lea instructions into a sequence of instructions
18718 which are executed on ALU to avoid AGU stalls.
18719 It is assumed that it is allowed to clobber flags register
18720 at lea position. */
18722 void
18724 {
18740 {
18743 }
18746 {
18749 }
18755 {
18756 /* Case r1 = r1 + ... */
18758 {
18759 /* If we have a case r1 = r1 + C * r2 then we
18760 should use multiplication which is very
18761 expensive. Assume cost model is wrong if we
18762 have such case here. */
18767 }
18768 else
18769 {
18770 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18774 /* Use shift for scaling. */
18783 }
18784 }
18786 {
18789 }
18790 else
18791 {
18793 {
18796 }
18798 {
18801 }
18802 else
18803 {
18808 else
18809 {
18810 rtx tmp1;
18812 /* Find better operand for SET instruction, depending
18813 on which definition is farther from the insn. */
18816 else
18826 }
18829 }
18833 }
18834 }
18836 /* Return true if it is ok to optimize an ADD operation to LEA
18837 operation to avoid flag register consumation. For most processors,
18838 ADD is faster than LEA. For the processors like BONNELL, if the
18839 destination register of LEA holds an actual address which will be
18840 used soon, LEA is better and otherwise ADD is better. */
18842 bool
18844 {
18849 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18857 }
18859 /* Return true if destination reg of SET_BODY is shift count of
18860 USE_BODY. */
18862 static bool
18864 {
18865 rtx set_dest;
18866 rtx shift_rtx;
18869 /* Retrieve destination of SET_BODY. */
18871 {
18880 use_body))
18885 }
18887 /* Retrieve shift count of USE_BODY. */
18889 {
18901 }
18909 {
18912 /* Return true if shift count is dest of SET_BODY. */
18914 {
18915 /* Add check since it can be invoked before register
18916 allocation in pre-reload schedule. */
18922 }
18923 }
18926 }
18928 /* Return true if destination reg of SET_INSN is shift count of
18929 USE_INSN. */
18931 bool
18933 {
18936 }
18938 /* Return TRUE or FALSE depending on whether the unary operator meets the
18939 appropriate constraints. */
18941 bool
18943 machine_mode,
18945 {
18946 /* If one of operands is memory, source and destination must match. */
18952 }
18954 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
18955 are ok, keeping in mind the possible movddup alternative. */
18957 bool
18959 {
18965 }
18967 /* Post-reload splitter for converting an SF or DFmode value in an
18968 SSE register into an unsigned SImode. */
18970 void
18972 {
18973 machine_mode vecmode;
18983 /* Load up the value into the low element. We must ensure that the other
18984 elements are valid floats -- zero is the easiest such value. */
18986 {
18989 else
18991 }
18992 else
18993 {
18998 else
19000 }
19020 else
19025 }
19027 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19028 Expects the 64-bit DImode to be supplied in a pair of integral
19029 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19030 -mfpmath=sse, !optimize_size only. */
19032 void
19034 {
19038 rtx x;
19044 {
19047 }
19048 else
19049 {
19053 }
19061 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19064 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19065 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19066 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19067 (0x1.0p84 + double(fp_value_hi_xmm)).
19068 Note these exponents differ by 32. */
19072 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19073 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19082 /* Add the upper and lower DFmode values together. */
19085 else
19086 {
19090 }
19093 }
19095 /* Not used, but eases macroization of patterns. */
19096 void
19098 {
19100 }
19102 /* Convert an unsigned SImode value into a DFmode. Only currently used
19103 for SSE, but applicable anywhere. */
19105 void
19107 {
19108 REAL_VALUE_TYPE TWO31r;
19123 }
19125 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19126 32-bit mode; otherwise we have a direct convert instruction. */
19128 void
19130 {
19131 REAL_VALUE_TYPE TWO32r;
19149 }
19151 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19152 For x86_32, -mfpmath=sse, !optimize_size only. */
19153 void
19155 {
19156 REAL_VALUE_TYPE ONE16r;
19175 }
19177 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19178 a vector of unsigned ints VAL to vector of floats TARGET. */
19180 void
19182 {
19184 REAL_VALUE_TYPE TWO16r;
19191 else
19196 OPTAB_DIRECT);
19207 OPTAB_DIRECT);
19209 OPTAB_DIRECT);
19212 }
19214 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19215 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19216 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19217 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19219 rtx
19221 {
19222 REAL_VALUE_TYPE TWO31r;
19237 {
19243 }
19252 OPTAB_DIRECT);
19253 else
19254 {
19260 OPTAB_DIRECT);
19261 }
19264 }
19266 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19267 then replicate the value for all elements of the vector
19268 register. */
19270 rtx
19272 {
19274 rtvec v;
19275 machine_mode scalar_mode;
19278 {
19311 }
19312 }
19314 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19315 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19316 for an SSE register. If VECT is true, then replicate the mask for
19317 all elements of the vector register. If INVERT is true, then create
19318 a mask excluding the sign bit. */
19320 rtx
19322 {
19326 rtx v;
19327 rtx mask;
19329 /* Find the sign bit, sign extended to 2*HWI. */
19331 {
19355 else
19363 {
19366 }
19367 else
19368 {
19369 rtvec vec;
19375 {
19378 }
19379 else
19389 }
19394 }
19399 /* Force this value into the low part of a fp vector constant. */
19408 }
19410 /* Generate code for floating point ABS or NEG. */
19412 void
19414 rtx operands[])
19415 {
19426 {
19432 }
19434 /* NEG and ABS performed with SSE use bitwise mask operations.
19435 Create the appropriate mask now. */
19438 else
19448 {
19450 rtvec par;
19455 else
19456 {
19459 }
19461 }
19462 else
19464 }
19466 /* Expand a copysign operation. Special case operand 0 being a constant. */
19468 void
19470 {
19484 else
19488 {
19495 {
19498 else
19499 {
19503 }
19504 }
19514 else
19518 }
19519 else
19520 {
19530 else
19534 }
19535 }
19537 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19538 be a constant, and so has already been expanded into a vector constant. */
19540 void
19542 {
19558 {
19561 }
19562 }
19564 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19565 so we have to do two masks. */
19567 void
19569 {
19584 {
19585 /* Shouldn't happen often (it's useless, obviously), but when it does
19586 we'd generate incorrect code if we continue below. */
19589 }
19592 {
19603 }
19604 else
19605 {
19607 {
19609 }
19611 {
19615 }
19619 {
19622 }
19624 {
19629 }
19631 }
19635 }
19637 /* Return TRUE or FALSE depending on whether the first SET in INSN
19638 has source and destination with matching CC modes, and that the
19639 CC mode is at least as constrained as REQ_MODE. */
19641 bool
19643 {
19644 rtx set;
19645 machine_mode set_mode;
19655 {
19665 /* FALLTHRU */
19669 /* FALLTHRU */
19673 /* FALLTHRU */
19687 }
19690 }
19692 /* Generate insn patterns to do an integer compare of OPERANDS. */
19694 static rtx
19696 {
19697 machine_mode cmpmode;
19703 /* This is very simple, but making the interface the same as in the
19704 FP case makes the rest of the code easier. */
19708 /* Return the test that should be put into the flags user, i.e.
19709 the bcc, scc, or cmov instruction. */
19711 }
19713 /* Figure out whether to use ordered or unordered fp comparisons.
19714 Return the appropriate mode to use. */
19716 machine_mode
19718 {
19719 /* ??? In order to make all comparisons reversible, we do all comparisons
19720 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19721 all forms trapping and nontrapping comparisons, we can make inequality
19722 comparisons trapping again, since it results in better code when using
19723 FCOM based compares. */
19725 }
19727 machine_mode
19729 {
19733 {
19736 }
19739 {
19740 /* Only zero flag is needed. */
19744 /* Codes needing carry flag. */
19747 /* Detect overflow checks. They need just the carry flag. */
19751 else
19756 /* Codes possibly doable only with sign flag when
19757 comparing against zero. */
19762 else
19763 /* For other cases Carry flag is not required. */
19765 /* Codes doable only with sign flag when comparing
19766 against zero, but we miss jump instruction for it
19767 so we need to use relational tests against overflow
19768 that thus needs to be zero. */
19773 else
19775 /* strcmp pattern do (use flags) and combine may ask us for proper
19776 mode. */
19781 }
19782 }
19784 /* Return the fixed registers used for condition codes. */
19786 static bool
19788 {
19792 }
19794 /* If two condition code modes are compatible, return a condition code
19795 mode which is compatible with both. Otherwise, return
19796 VOIDmode. */
19798 static machine_mode
19800 {
19817 {
19831 {
19845 }
19849 /* These are only compatible with themselves, which we already
19850 checked above. */
19852 }
19853 }
19856 /* Return a comparison we can do and that it is equivalent to
19857 swap_condition (code) apart possibly from orderedness.
19858 But, never change orderedness if TARGET_IEEE_FP, returning
19859 UNKNOWN in that case if necessary. */
19861 static enum rtx_code
19863 {
19865 {
19876 }
19877 }
19879 /* Return cost of comparison CODE using the best strategy for performance.
19880 All following functions do use number of instructions as a cost metrics.
19881 In future this should be tweaked to compute bytes for optimize_size and
19882 take into account performance of various instructions on various CPUs. */
19884 static int
19886 {
19889 /* The cost of code using bit-twiddling on %ah. */
19891 {
19914 }
19917 {
19924 }
19925 }
19927 /* Return strategy to use for floating-point. We assume that fcomi is always
19928 preferrable where available, since that is also true when looking at size
19929 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19931 enum ix86_fpcmp_strategy
19933 {
19934 /* Do fcomi/sahf based test when profitable. */
19943 }
19945 /* Swap, force into registers, or otherwise massage the two operands
19946 to a fp comparison. The operands are updated in place; the new
19947 comparison code is returned. */
19949 static enum rtx_code
19951 {
19957 /* All of the unordered compare instructions only work on registers.
19958 The same is true of the fcomi compare instructions. The XFmode
19959 compare instructions require registers except when comparing
19960 against zero or when converting operand 1 from fixed point to
19961 floating point. */
19970 {
19973 }
19974 else
19975 {
19976 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19977 things around if they appear profitable, otherwise force op0
19978 into a register. */
19984 {
19987 {
19990 }
19991 }
19997 {
20002 {
20005 }
20006 else
20008 }
20009 }
20011 /* Try to rearrange the comparison to make it cheaper. */
20015 {
20020 }
20025 }
20027 /* Convert comparison codes we use to represent FP comparison to integer
20028 code that will result in proper branch. Return UNKNOWN if no such code
20029 is available. */
20031 enum rtx_code
20033 {
20035 {
20058 }
20059 }
20061 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20063 static rtx
20065 {
20072 /* Do fcomi/sahf based test when profitable. */
20074 {
20079 tmp);
20087 tmp);
20096 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20103 /* In the unordered case, we have to check C2 for NaN's, which
20104 doesn't happen to work out to anything nice combination-wise.
20105 So do some bit twiddling on the value we've got in AH to come
20106 up with an appropriate set of condition codes. */
20110 {
20114 {
20117 }
20118 else
20119 {
20125 }
20130 {
20135 }
20136 else
20137 {
20140 }
20145 {
20148 }
20149 else
20150 {
20154 }
20159 {
20165 }
20166 else
20167 {
20170 }
20175 {
20180 }
20181 else
20182 {
20185 }
20190 {
20195 }
20196 else
20197 {
20200 }
20214 }
20219 }
20221 /* Return the test that should be put into the flags user, i.e.
20222 the bcc, scc, or cmov instruction. */
20225 const0_rtx);
20226 }
20228 static rtx
20230 {
20231 rtx ret;
20237 {
20240 }
20241 else
20245 }
20247 void
20249 {
20251 rtx tmp;
20254 {
20261 simple:
20265 pc_rtx);
20273 /* Expand DImode branch into multiple compare+branch. */
20274 {
20278 machine_mode submode;
20281 {
20284 }
20291 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20292 avoid two branches. This costs one extra insn, so disable when
20293 optimizing for size. */
20298 {
20316 }
20318 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20319 op1 is a constant and the low word is zero, then we can just
20320 examine the high word. Similarly for low word -1 and
20321 less-or-equal-than or greater-than. */
20325 {
20328 {
20331 }
20335 {
20338 }
20342 }
20344 /* Otherwise, we need two or three jumps. */
20353 {
20367 }
20369 /*
20370 * a < b =>
20371 * if (hi(a) < hi(b)) goto true;
20372 * if (hi(a) > hi(b)) goto false;
20373 * if (lo(a) < lo(b)) goto true;
20374 * false:
20375 */
20387 }
20392 }
20393 }
20395 /* Split branch based on floating point condition. */
20396 void
20399 {
20400 rtx condition;
20401 rtx i;
20404 {
20409 }
20412 tmp);
20420 }
20422 void
20424 {
20425 rtx ret;
20432 }
20434 /* Expand comparison setting or clearing carry flag. Return true when
20435 successful and set pop for the operation. */
20436 static bool
20438 {
20439 machine_mode mode =
20442 /* Do not handle double-mode compares that go through special path. */
20447 {
20448 rtx compare_op;
20453 /* Shortcut: following common codes never translate
20454 into carry flag compares. */
20459 /* These comparisons require zero flag; swap operands so they won't. */
20462 {
20465 }
20467 /* Try to expand the comparison and verify that we end up with
20468 carry flag based comparison. This fails to be true only when
20469 we decide to expand comparison using arithmetic that is not
20470 too common scenario. */
20479 else
20488 }
20494 {
20499 /* Convert a==0 into (unsigned)a<1. */
20508 /* Convert a>b into b<a or a>=b-1. */
20512 {
20514 /* Bail out on overflow. We still can swap operands but that
20515 would force loading of the constant into register. */
20520 }
20521 else
20522 {
20525 }
20528 /* Convert a>=0 into (unsigned)a<0x80000000. */
20546 }
20547 /* Swapping operands may cause constant to appear as first operand. */
20549 {
20553 }
20557 }
20559 bool
20561 {
20564 rtx compare_op;
20586 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20587 HImode insns, we'd be swallowed in word prefix ops. */
20593 {
20597 HOST_WIDE_INT diff;
20600 /* Sign bit compares are better done using shifts than we do by using
20601 sbb. */
20604 {
20605 /* Detect overlap between destination and compare sources. */
20609 {
20610 rtx flags;
20619 {
20621 compare_code
20623 }
20625 /* To simplify rest of code, restrict to the GEU case. */
20627 {
20633 }
20634 else
20635 {
20638 reverse_condition_maybe_unordered
20640 else
20643 }
20652 else
20655 }
20656 else
20657 {
20660 else
20661 {
20666 }
20668 }
20671 {
20672 /*
20673 * cmpl op0,op1
20674 * sbbl dest,dest
20675 * [addl dest, ct]
20676 *
20677 * Size 5 - 8.
20678 */
20683 }
20685 {
20686 /*
20687 * cmpl op0,op1
20688 * sbbl dest,dest
20689 * orl $ct, dest
20690 *
20691 * Size 8.
20692 */
20696 }
20698 {
20699 /*
20700 * cmpl op0,op1
20701 * sbbl dest,dest
20702 * notl dest
20703 * [addl dest, cf]
20704 *
20705 * Size 8 - 11.
20706 */
20712 }
20713 else
20714 {
20715 /*
20716 * cmpl op0,op1
20717 * sbbl dest,dest
20718 * [notl dest]
20719 * andl cf - ct, dest
20720 * [addl dest, ct]
20721 *
20722 * Size 8 - 11.
20723 */
20726 {
20730 }
20740 }
20746 }
20749 {
20756 {
20759 /* We may be reversing unordered compare to normal compare, that
20760 is not valid in general (we may convert non-trapping condition
20761 to trapping one), however on i386 we currently emit all
20762 comparisons unordered. */
20765 }
20766 else
20767 {
20770 }
20771 }
20776 {
20781 {
20786 }
20787 }
20789 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20793 {
20794 /* If lea code below could be used, only optimize
20795 if it results in a 2 insn sequence. */
20801 {
20802 /*
20803 * notl op1 (if necessary)
20804 * sarl $31, op1
20805 * orl cf, op1
20806 */
20808 {
20812 }
20823 }
20824 }
20832 {
20833 /*
20834 * xorl dest,dest
20835 * cmpl op1,op2
20836 * setcc dest
20837 * lea cf(dest*(ct-cf)),dest
20838 *
20839 * Size 14.
20840 *
20841 * This also catches the degenerate setcc-only case.
20842 */
20844 rtx tmp;
20850 /* On x86_64 the lea instruction operates on Pmode, so we need
20851 to get arithmetics done in proper mode to match. */
20854 else
20855 {
20856 rtx out1;
20859 nops++;
20861 {
20863 nops++;
20864 }
20865 }
20867 {
20869 nops++;
20870 }
20872 {
20875 else
20877 }
20882 }
20884 /*
20885 * General case: Jumpful:
20886 * xorl dest,dest cmpl op1, op2
20887 * cmpl op1, op2 movl ct, dest
20888 * setcc dest jcc 1f
20889 * decl dest movl cf, dest
20890 * andl (cf-ct),dest 1:
20891 * addl ct,dest
20892 *
20893 * Size 20. Size 14.
20894 *
20895 * This is reasonably steep, but branch mispredict costs are
20896 * high on modern cpus, so consider failing only if optimizing
20897 * for space.
20898 */
20903 {
20905 {
20912 {
20915 /* We may be reversing unordered compare to normal compare,
20916 that is not valid in general (we may convert non-trapping
20917 condition to trapping one), however on i386 we currently
20918 emit all comparisons unordered. */
20920 }
20921 else
20922 {
20926 }
20927 }
20930 {
20931 /* notl op1 (if needed)
20932 sarl $31, op1
20933 andl (cf-ct), op1
20934 addl ct, op1
20936 For x < 0 (resp. x <= -1) there will be no notl,
20937 so if possible swap the constants to get rid of the
20938 complement.
20939 True/false will be -1/0 while code below (store flag
20940 followed by decrement) is 0/-1, so the constants need
20941 to be exchanged once more. */
20944 {
20947 }
20948 else
20952 }
20953 else
20954 {
20958 constm1_rtx,
20960 }
20972 }
20973 }
20976 {
20977 /* Try a few things more with specific constants and a variable. */
20979 optab op;
20985 /* If one of the two operands is an interesting constant, load a
20986 constant with the above and mask it in with a logical operation. */
20989 {
20995 else
20997 }
20999 {
21005 else
21007 }
21008 else
21015 /* Recurse to get the constant loaded. */
21019 /* Mask in the interesting variable. */
21021 OPTAB_WIDEN);
21026 }
21028 /*
21029 * For comparison with above,
21030 *
21031 * movl cf,dest
21032 * movl ct,tmp
21033 * cmpl op1,op2
21034 * cmovcc tmp,dest
21035 *
21036 * Size 15.
21037 */
21059 }
21061 /* Swap, force into registers, or otherwise massage the two operands
21062 to an sse comparison with a mask result. Thus we differ a bit from
21063 ix86_prepare_fp_compare_args which expects to produce a flags result.
21065 The DEST operand exists to help determine whether to commute commutative
21066 operators. The POP0/POP1 operands are updated in place. The new
21067 comparison code is returned, or UNKNOWN if not implementable. */
21069 static enum rtx_code
21072 {
21074 {
21077 /* AVX supports all the needed comparisons. */
21080 /* We have no LTGT as an operator. We could implement it with
21081 NE & ORDERED, but this requires an extra temporary. It's
21082 not clear that it's worth it. */
21089 /* These are supported directly. */
21096 /* AVX has 3 operand comparisons, no need to swap anything. */
21099 /* For commutative operators, try to canonicalize the destination
21100 operand to be first in the comparison - this helps reload to
21101 avoid extra moves. */
21104 /* FALLTHRU */
21110 /* These are not supported directly before AVX, and furthermore
21111 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21112 comparison operands to transform into something that is
21113 supported. */
21120 }
21123 }
21125 /* Detect conditional moves that exactly match min/max operational
21126 semantics. Note that this is IEEE safe, as long as we don't
21127 interchange the operands.
21129 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21130 and TRUE if the operation is successful and instructions are emitted. */
21132 static bool
21135 {
21136 machine_mode mode;
21138 rtx tmp;
21141 ;
21144 else
21151 else
21156 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21157 but MODE may be a vector mode and thus not appropriate. */
21159 {
21161 rtvec v;
21166 }
21167 else
21168 {
21171 }
21175 }
21177 /* Expand an sse vector comparison. Return the register with the result. */
21179 static rtx
21182 {
21186 /* In general case result of comparison can differ from operands' type. */
21187 machine_mode cmp_mode;
21189 /* In AVX512F the result of comparison is an integer mask. */
21191 rtx x;
21194 {
21199 }
21200 else
21213 /* Compare patterns for int modes are unspec in AVX512F only. */
21215 {
21219 {
21228 }
21231 {
21234 }
21235 }
21239 {
21242 }
21243 else
21247 }
21249 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21250 operations. This is used for both scalar and vector conditional moves. */
21252 static void
21254 {
21258 /* In AVX512F the result of comparison is an integer mask. */
21266 {
21268 }
21271 {
21275 }
21278 {
21283 }
21286 {
21290 }
21293 {
21301 op_true,
21302 op_false)));
21303 }
21304 else
21305 {
21315 {
21329 {
21336 }
21351 {
21358 }
21382 }
21385 {
21389 }
21390 else
21391 {
21397 else
21409 }
21410 }
21411 }
21413 /* Expand a floating-point conditional move. Return true if successful. */
21415 bool
21417 {
21425 {
21426 machine_mode cmode;
21428 /* Since we've no cmove for sse registers, don't force bad register
21429 allocation just to gain access to it. Deny movcc when the
21430 comparison mode doesn't match the move mode. */
21449 }
21456 /* The floating point conditional move instructions don't directly
21457 support conditions resulting from a signed integer comparison. */
21461 {
21466 }
21473 }
21475 /* Expand a floating-point vector conditional move; a vcond operation
21476 rather than a movcc operation. */
21478 bool
21480 {
21482 rtx cmp;
21487 {
21488 rtx temp;
21490 {
21507 }
21509 OPTAB_DIRECT);
21512 }
21522 }
21524 /* Expand a signed/unsigned integral vector conditional move. */
21526 bool
21528 {
21538 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21539 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21548 {
21552 {
21558 }
21561 {
21567 }
21568 }
21577 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21581 ;
21582 else
21583 {
21584 /* Canonicalize the comparison to EQ, GT, GTU. */
21586 {
21603 /* FALLTHRU */
21613 }
21615 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21617 {
21619 {
21621 /* SSE4.1 supports EQ. */
21628 /* SSE4.2 supports GT/GTU. */
21635 }
21636 }
21638 /* Unsigned parallel compare is not supported by the hardware.
21639 Play some tricks to turn this into a signed comparison
21640 against 0. */
21642 {
21646 {
21653 {
21658 {
21667 }
21668 /* Subtract (-(INT MAX) - 1) from both operands to make
21669 them signed. */
21680 }
21689 /* Perform a parallel unsigned saturating subtraction. */
21702 }
21703 }
21704 }
21706 /* Allow the comparison to be done in one mode, but the movcc to
21707 happen in another mode. */
21709 {
21712 }
21713 else
21714 {
21720 }
21725 }
21727 /* AVX512F does support 64-byte integer vector operations,
21728 thus the longest vector we are faced with is V64QImode. */
21729 #define MAX_VECT_LEN 64
21731 struct expand_vec_perm_d
21732 {
21735 machine_mode vmode;
21739 };
21741 static bool
21744 {
21745 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21746 expander, so args are either in d, or in op0, op1 etc. */
21752 {
21779 {
21782 }
21786 {
21789 }
21793 {
21796 }
21812 {
21815 }
21819 {
21822 }
21826 {
21829 }
21833 }
21838 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21839 expander, so args are either in d, or in op0, op1 etc. */
21841 {
21849 }
21853 }
21855 /* Expand a variable vector permutation. */
21857 void
21859 {
21870 /* Number of elements in the vector. */
21879 {
21881 {
21882 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21883 an constant shuffle operand. With a tiny bit of effort we can
21884 use VPERMD instead. A re-interpretation stall for V4DFmode is
21885 unfortunate but there's no avoiding it.
21886 Similarly for V16HImode we don't have instructions for variable
21887 shuffling, while for V32QImode we can use after preparing suitable
21888 masks vpshufb; vpshufb; vpermq; vpor. */
21891 {
21895 }
21896 else
21897 {
21901 }
21904 /* Replicate the low bits of the V4DImode mask into V8SImode:
21905 mask = { A B C D }
21906 t1 = { A A B B C C D D }. */
21914 else
21917 /* Multiply the shuffle indicies by two. */
21919 OPTAB_DIRECT);
21921 /* Add one to the odd shuffle indicies:
21922 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21924 {
21927 }
21931 OPTAB_DIRECT);
21933 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
21938 }
21941 {
21943 /* The VPERMD and VPERMPS instructions already properly ignore
21944 the high bits of the shuffle elements. No need for us to
21945 perform an AND ourselves. */
21947 {
21952 }
21953 else
21954 {
21960 }
21967 else
21968 {
21974 }
21978 /* By combining the two 128-bit input vectors into one 256-bit
21979 input vector, we can use VPERMD and VPERMPS for the full
21980 two-operand shuffle. */
22012 /* From mask create two adjusted masks, which contain the same
22013 bits as mask in the low 7 bits of each vector element.
22014 The first mask will have the most significant bit clear
22015 if it requests element from the same 128-bit lane
22016 and MSB set if it requests element from the other 128-bit lane.
22017 The second mask will have the opposite values of the MSB,
22018 and additionally will have its 128-bit lanes swapped.
22019 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22020 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22021 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22022 stands for other 12 bytes. */
22023 /* The bit whether element is from the same lane or the other
22024 lane is bit 4, so shift it up by 3 to the MSB position. */
22028 /* Clear MSB bits from the mask just in case it had them set. */
22030 /* After this t1 will have MSB set for elements from other lane. */
22032 /* Clear bits other than MSB. */
22034 /* Or in the lower bits from mask into t3. */
22036 /* And invert MSB bits in t1, so MSB is set for elements from the same
22037 lane. */
22039 /* Swap 128-bit lanes in t3. */
22044 /* And or in the lower bits from mask into t1. */
22047 {
22048 /* Each of these shuffles will put 0s in places where
22049 element from the other 128-bit lane is needed, otherwise
22050 will shuffle in the requested value. */
22054 /* For t3 the 128-bit lanes are swapped again. */
22059 /* And oring both together leads to the result. */
22066 }
22069 /* Similarly to the above one_operand_shuffle code,
22070 just for repeated twice for each operand. merge_two:
22071 code will merge the two results together. */
22095 }
22096 }
22099 {
22100 /* The XOP VPPERM insn supports three inputs. By ignoring the
22101 one_operand_shuffle special case, we avoid creating another
22102 set of constant vectors in memory. */
22105 /* mask = mask & {2*w-1, ...} */
22107 }
22108 else
22109 {
22110 /* mask = mask & {w-1, ...} */
22112 }
22120 /* For non-QImode operations, convert the word permutation control
22121 into a byte permutation control. */
22123 {
22128 /* Convert mask to vector of chars. */
22131 /* Replicate each of the input bytes into byte positions:
22132 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22133 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22134 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22141 else
22144 /* Convert it into the byte positions by doing
22145 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22151 }
22153 /* The actual shuffle operations all operate on V16QImode. */
22158 {
22165 }
22167 {
22174 }
22175 else
22176 {
22180 /* Shuffle the two input vectors independently. */
22186 merge_two:
22187 /* Then merge them together. The key is whether any given control
22188 element contained a bit set that indicates the second word. */
22192 {
22193 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22194 more shuffle to convert the V2DI input mask into a V4SI
22195 input mask. At which point the masking that expand_int_vcond
22196 will work as desired. */
22204 }
22226 }
22227 }
22229 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22230 true if we should do zero extension, else sign extension. HIGH_P is
22231 true if we want the N/2 high elements, else the low elements. */
22233 void
22235 {
22237 rtx tmp;
22240 {
22246 {
22250 else
22253 extract
22259 else
22262 extract
22268 else
22271 extract
22277 else
22280 extract
22286 else
22289 extract
22295 else
22298 extract
22304 else
22310 else
22316 else
22321 }
22324 {
22327 }
22329 {
22330 /* Shift higher 8 bytes to lower 8 bytes. */
22335 }
22336 else
22340 }
22341 else
22342 {
22346 {
22350 else
22356 else
22362 else
22367 }
22371 else
22378 }
22379 }
22381 /* Expand conditional increment or decrement using adb/sbb instructions.
22382 The default case using setcc followed by the conditional move can be
22383 done by generic code. */
22384 bool
22386 {
22388 rtx flags;
22390 rtx compare_op;
22393 machine_mode mode;
22408 {
22411 }
22414 {
22418 reverse_condition_maybe_unordered
22420 else
22422 }
22426 /* Construct either adc or sbb insn. */
22428 {
22430 {
22445 }
22446 }
22447 else
22448 {
22450 {
22465 }
22466 }
22470 }
22473 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22474 but works for floating pointer parameters and nonoffsetable memories.
22475 For pushes, it returns just stack offsets; the values will be saved
22476 in the right order. Maximally three parts are generated. */
22478 static int
22480 {
22485 else
22491 /* Optimize constant pool reference to immediates. This is used by fp
22492 moves, that force all constants to memory to allow combining. */
22494 {
22498 }
22501 {
22502 /* The only non-offsetable memories we handle are pushes. */
22511 }
22514 {
22516 /* Caution: if we looked through a constant pool memory above,
22517 the operand may actually have a different mode now. That's
22518 ok, since we want to pun this all the way back to an integer. */
22522 }
22525 {
22528 else
22529 {
22533 {
22537 }
22539 {
22544 }
22546 {
22547 REAL_VALUE_TYPE r;
22552 {
22559 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22560 long double may not be 80-bit. */
22569 }
22572 }
22573 else
22575 }
22576 }
22577 else
22578 {
22582 {
22585 {
22589 }
22591 {
22595 }
22597 {
22598 REAL_VALUE_TYPE r;
22604 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22607 = gen_int_mode
22610 DImode);
22611 else
22618 = gen_int_mode
22621 DImode);
22622 else
22624 }
22625 else
22627 }
22628 }
22631 }
22633 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22634 Return false when normal moves are needed; true when all required
22635 insns have been emitted. Operands 2-4 contain the input values
22636 int the correct order; operands 5-7 contain the output values. */
22638 void
22640 {
22648 /* The DFmode expanders may ask us to move double.
22649 For 64bit target this is single move. By hiding the fact
22650 here we simplify i386.md splitters. */
22652 {
22653 /* Optimize constant pool reference to immediates. This is used by
22654 fp moves, that force all constants to memory to allow combining. */
22661 {
22664 }
22665 else
22670 }
22672 /* The only non-offsettable memory we handle is push. */
22675 else
22682 /* When emitting push, take care for source operands on the stack. */
22685 {
22688 /* Compensate for the stack decrement by 4. */
22693 /* src_base refers to the stack pointer and is
22694 automatically decreased by emitted push. */
22698 }
22700 /* We need to do copy in the right order in case an address register
22701 of the source overlaps the destination. */
22703 {
22704 rtx tmp;
22707 {
22711 collisions++;
22712 }
22714 /* Collision in the middle part can be handled by reordering. */
22716 {
22719 }
22723 {
22725 {
22728 }
22729 else
22730 {
22733 }
22734 }
22736 /* If there are more collisions, we can't handle it by reordering.
22737 Do an lea to the last part and use only one colliding move. */
22739 {
22740 rtx base;
22746 /* Handle the case when the last part isn't valid for lea.
22747 Happens in 64-bit mode storing the 12-byte XFmode. */
22754 {
22757 }
22758 }
22759 }
22762 {
22764 {
22766 {
22771 }
22773 {
22776 }
22777 }
22778 else
22779 {
22780 /* In 64bit mode we don't have 32bit push available. In case this is
22781 register, it is OK - we will just use larger counterpart. We also
22782 retype memory - these comes from attempt to avoid REX prefix on
22783 moving of second half of TFmode value. */
22785 {
22787 {
22798 }
22802 }
22803 }
22807 }
22809 /* Choose correct order to not overwrite the source before it is copied. */
22819 {
22821 {
22824 }
22825 }
22826 else
22827 {
22829 {
22832 }
22833 }
22835 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22837 {
22846 }
22852 }
22854 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22855 left shift by a constant, either using a single shift or
22856 a sequence of add instructions. */
22858 static void
22860 {
22866 {
22870 }
22871 else
22872 {
22875 }
22876 }
22878 void
22880 {
22889 {
22894 {
22900 }
22901 else
22902 {
22910 }
22912 }
22919 {
22920 /* Assuming we've chosen a QImode capable registers, then 1 << N
22921 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22923 {
22939 }
22941 /* Otherwise, we can get the same results by manually performing
22942 a bit extract operation on bit 5/6, and then performing the two
22943 shifts. The two methods of getting 0/1 into low/high are exactly
22944 the same size. Avoiding the shift in the bit extract case helps
22945 pentium4 a bit; no one else seems to care much either way. */
22946 else
22947 {
22948 machine_mode half_mode;
22952 HOST_WIDE_INT bits;
22953 rtx x;
22956 {
22962 }
22963 else
22964 {
22970 }
22974 else
22982 }
22987 }
22990 {
22991 /* For -1 << N, we can avoid the shld instruction, because we
22992 know that we're shifting 0...31/63 ones into a -1. */
22996 else
22998 }
22999 else
23000 {
23008 }
23013 {
23019 }
23020 else
23021 {
23026 }
23027 }
23029 void
23031 {
23041 {
23046 {
23052 }
23054 {
23063 }
23064 else
23065 {
23073 }
23074 }
23075 else
23076 {
23088 {
23096 scratch));
23097 }
23098 else
23099 {
23104 }
23105 }
23106 }
23108 void
23110 {
23120 {
23125 {
23132 }
23133 else
23134 {
23142 }
23143 }
23144 else
23145 {
23157 {
23163 scratch));
23164 }
23165 else
23166 {
23171 }
23172 }
23173 }
23175 /* Predict just emitted jump instruction to be taken with probability PROB. */
23176 static void
23178 {
23182 }
23184 /* Helper function for the string operations below. Dest VARIABLE whether
23185 it is aligned to VALUE bytes. If true, jump to the label. */
23188 {
23193 else
23199 else
23202 }
23204 /* Adjust COUNTER by the VALUE. */
23205 static void
23207 {
23212 }
23214 /* Zero extend possibly SImode EXP to Pmode register. */
23215 rtx
23217 {
23219 }
23221 /* Divide COUNTREG by SCALE. */
23222 static rtx
23224 {
23225 rtx sc;
23237 }
23239 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23240 DImode for constant loop counts. */
23242 static machine_mode
23244 {
23252 }
23254 /* Copy the address to a Pmode register. This is used for x32 to
23255 truncate DImode TLS address to a SImode register. */
23257 static rtx
23259 {
23262 else
23263 {
23266 }
23267 }
23269 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23270 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23271 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23272 memory by VALUE (supposed to be in MODE).
23274 The size is rounded down to whole number of chunk size moved at once.
23275 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23278 static void
23283 {
23290 rtx size;
23299 /* Those two should combine. */
23301 {
23305 }
23312 /* This assert could be relaxed - in this case we'll need to compute
23313 smallest power of two, containing in PIECE_SIZE_N and pass it to
23314 offset_address. */
23320 {
23324 /* When unrolling for chips that reorder memory reads and writes,
23325 we can save registers by using single temporary.
23326 Also using 4 temporaries is overkill in 32bit mode. */
23328 {
23330 {
23332 {
23333 destmem =
23335 srcmem =
23337 }
23339 }
23340 }
23341 else
23342 {
23346 {
23349 {
23350 srcmem =
23352 }
23354 }
23356 {
23358 {
23359 destmem =
23361 }
23363 }
23364 }
23365 }
23366 else
23368 {
23370 destmem =
23373 }
23383 {
23389 else
23391 }
23392 else
23400 {
23405 }
23407 }
23409 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23410 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23411 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23412 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23413 ORIG_VALUE is the original value passed to memset to fill the memory with.
23414 Other arguments have same meaning as for previous function. */
23416 static void
23419 rtx count,
23421 {
23422 rtx destexp;
23423 rtx srcexp;
23424 rtx countreg;
23425 HOST_WIDE_INT rounded_count;
23427 /* If possible, it is shorter to use rep movs.
23428 TODO: Maybe it is better to move this logic to decide_alg. */
23439 {
23443 }
23444 else
23447 {
23452 }
23457 {
23460 }
23461 else
23462 {
23466 {
23470 }
23471 else
23474 {
23479 }
23480 else
23481 {
23484 }
23487 }
23488 }
23490 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23491 DESTMEM.
23492 SRC is passed by pointer to be updated on return.
23493 Return value is updated DST. */
23494 static rtx
23496 HOST_WIDE_INT size_to_move)
23497 {
23500 machine_mode move_mode;
23503 /* Find the widest mode in which we could perform moves.
23504 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23505 it until move of such size is supported. */
23510 {
23514 }
23516 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23517 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23519 {
23524 {
23528 }
23529 }
23535 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23539 {
23540 /* We move from memory to memory, so we'll need to do it via
23541 a temporary register. */
23552 piece_size);
23554 piece_size);
23555 }
23557 /* Update DST and SRC rtx. */
23560 }
23562 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23563 static void
23566 {
23569 {
23574 /* For now MAX_SIZE should be a power of 2. This assert could be
23575 relaxed, but it'll require a bit more complicated epilogue
23576 expanding. */
23579 {
23582 }
23584 }
23586 {
23592 }
23594 /* When there are stringops, we can cheaply increase dest and src pointers.
23595 Otherwise we save code size by maintaining offset (zero is readily
23596 available from preceding rep operation) and using x86 addressing modes.
23597 */
23599 {
23601 {
23608 }
23610 {
23617 }
23619 {
23626 }
23627 }
23628 else
23629 {
23631 rtx tmp;
23634 {
23645 }
23647 {
23660 }
23662 {
23671 }
23672 }
23673 }
23675 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23676 with value PROMOTED_VAL.
23677 SRC is passed by pointer to be updated on return.
23678 Return value is updated DST. */
23679 static rtx
23681 HOST_WIDE_INT size_to_move)
23682 {
23685 machine_mode move_mode;
23688 /* Find the widest mode in which we could perform moves.
23689 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23690 it until move of such size is supported. */
23695 {
23698 }
23705 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23709 {
23711 {
23714 piece_size);
23716 }
23724 piece_size);
23725 }
23727 /* Update DST rtx. */
23729 }
23730 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23731 static void
23734 {
23735 count =
23741 }
23743 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23744 static void
23747 {
23748 rtx dest;
23751 {
23756 /* For now MAX_SIZE should be a power of 2. This assert could be
23757 relaxed, but it'll require a bit more complicated epilogue
23758 expanding. */
23761 {
23763 {
23766 else
23768 }
23769 }
23771 }
23773 {
23776 }
23778 {
23781 {
23786 }
23787 else
23788 {
23797 }
23800 }
23802 {
23805 {
23808 }
23809 else
23810 {
23815 }
23818 }
23820 {
23826 }
23828 {
23834 }
23836 {
23842 }
23843 }
23845 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23846 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23847 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23848 ignored.
23849 Return value is updated DESTMEM. */
23850 static rtx
23855 {
23858 {
23860 {
23863 {
23866 else
23868 }
23869 else
23875 }
23876 }
23878 }
23880 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23881 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23882 and jump to DONE_LABEL. */
23883 static void
23889 {
23892 rtx modesize;
23895 /* If we do not have vector value to copy, we must reduce size. */
23897 {
23899 {
23904 }
23905 else
23907 }
23908 else
23909 {
23910 /* Choose appropriate vector mode. */
23916 }
23921 {
23924 else
23925 {
23928 }
23930 }
23936 {
23940 }
23942 {
23945 else
23946 {
23949 }
23951 }
23957 }
23959 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
23960 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
23961 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
23962 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
23963 DONE_LABEL is a label after the whole copying sequence. The label is created
23964 on demand if *DONE_LABEL is NULL.
23965 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
23966 bounds after the initial copies.
23968 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
23969 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
23970 we will dispatch to a library call for large blocks.
23972 In pseudocode we do:
23974 if (COUNT < SIZE)
23975 {
23976 Assume that SIZE is 4. Bigger sizes are handled analogously
23977 if (COUNT & 4)
23978 {
23979 copy 4 bytes from SRCPTR to DESTPTR
23980 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
23981 goto done_label
23982 }
23983 if (!COUNT)
23984 goto done_label;
23985 copy 1 byte from SRCPTR to DESTPTR
23986 if (COUNT & 2)
23987 {
23988 copy 2 bytes from SRCPTR to DESTPTR
23989 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
23990 }
23991 }
23992 else
23993 {
23994 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
23995 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
23997 OLD_DESPTR = DESTPTR;
23998 Align DESTPTR up to DESIRED_ALIGN
23999 SRCPTR += DESTPTR - OLD_DESTPTR
24000 COUNT -= DEST_PTR - OLD_DESTPTR
24001 if (DYNAMIC_CHECK)
24002 Round COUNT down to multiple of SIZE
24003 << optional caller supplied zero size guard is here >>
24004 << optional caller suppplied dynamic check is here >>
24005 << caller supplied main copy loop is here >>
24006 }
24007 done_label:
24008 */
24009 static void
24012 machine_mode mode,
24022 {
24025 rtx modesize;
24027 rtx mode_value;
24029 /* Chose proper value to copy. */
24032 else
24036 /* See if block is big or small, handle small blocks. */
24038 {
24049 /* Handle sizes > 3. */
24056 /* Nothing to copy? Jump to DONE_LABEL if so */
24060 /* Do a byte copy. */
24064 else
24065 {
24068 }
24070 /* Handle sizes 2 and 3. */
24077 else
24078 {
24083 }
24089 }
24090 else
24094 /* Start memcpy for COUNT >= SIZE. */
24096 {
24099 }
24101 /* Copy first desired_align bytes. */
24107 {
24110 else
24111 {
24114 }
24117 }
24120 /* Copy last SIZE bytes. */
24127 else
24128 {
24134 }
24136 {
24140 else
24141 {
24144 }
24145 }
24147 /* Align destination. */
24149 {
24153 /* Align destptr up, place it to new register. */
24160 /* See how many bytes we skipped. */
24164 /* Adjust srcptr and count. */
24170 /* We copied at most size + prolog_size. */
24173 else
24176 /* Our loops always round down the bock size, but for dispatch to library
24177 we need precise value. */
24181 }
24182 else
24183 {
24185 /* Decrease count, so we won't end up copying last word twice. */
24189 else
24193 }
24194 }
24197 /* This function is like the previous one, except here we know how many bytes
24198 need to be copied. That allows us to update alignment not only of DST, which
24199 is returned, but also of SRC, which is passed as a pointer for that
24200 reason. */
24201 static rtx
24206 {
24214 {
24218 }
24223 {
24225 {
24227 {
24230 else
24232 }
24233 else
24236 }
24237 }
24244 {
24250 {
24253 {
24257 }
24262 }
24266 }
24269 }
24271 /* Return true if ALG can be used in current context.
24272 Assume we expand memset if MEMSET is true. */
24273 static bool
24275 {
24280 /* Algorithms using the rep prefix want at least edi and ecx;
24281 additionally, memset wants eax and memcpy wants esi. Don't
24282 consider such algorithms if the user has appropriated those
24283 registers for their own purposes. */
24290 }
24292 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24293 static enum stringop_alg
24297 {
24308 /* Even if the string operation call is cold, we still might spend a lot
24309 of time processing large blocks. */
24315 else
24321 else
24324 /* See maximal size for user defined algorithm. */
24326 {
24333 }
24335 /* If expected size is not known but max size is small enough
24336 so inline version is a win, set expected size into
24337 the range. */
24342 /* If user specified the algorithm, honnor it if possible. */
24346 /* rep; movq or rep; movl is the smallest variant. */
24348 {
24353 else
24356 }
24357 /* Very tiny blocks are best handled via the loop, REP is expensive to
24358 setup. */
24362 {
24366 {
24367 /* We get here if the algorithms that were not libcall-based
24368 were rep-prefix based and we are unable to use rep prefixes
24369 based on global register usage. Break out of the loop and
24370 use the heuristic below. */
24374 {
24378 {
24381 }
24382 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24383 last non-libcall inline algorithm. */
24385 {
24386 /* When the current size is best to be copied by a libcall,
24387 but we are still forced to inline, run the heuristic below
24388 that will pick code for medium sized blocks. */
24390 {
24393 }
24395 }
24397 {
24400 }
24401 }
24402 }
24403 }
24404 /* When asked to inline the call anyway, try to pick meaningful choice.
24405 We look for maximal size of block that is faster to copy by hand and
24406 take blocks of at most of that size guessing that average size will
24407 be roughly half of the block.
24409 If this turns out to be bad, we might simply specify the preferred
24410 choice in ix86_costs. */
24414 {
24417 /* If there aren't any usable algorithms, then recursing on
24418 smaller sizes isn't going to find anything. Just return the
24419 simple byte-at-a-time copy loop. */
24421 {
24422 /* Pick something reasonable. */
24426 }
24436 }
24439 }
24441 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24442 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24443 static int
24447 machine_mode move_mode)
24448 {
24459 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24460 copying whole cacheline at once. */
24473 }
24476 /* Helper function for memcpy. For QImode value 0xXY produce
24477 0xXYXYXYXY of wide specified by MODE. This is essentially
24478 a * 0x10101010, but we can do slightly better than
24479 synth_mult by unwinding the sequence by hand on CPUs with
24480 slow multiply. */
24481 static rtx
24483 {
24485 rtx tmp;
24492 {
24500 }
24509 nops--;
24514 {
24518 OPTAB_DIRECT);
24519 }
24520 else
24521 {
24527 else
24529 else
24530 {
24533 reg =
24535 }
24545 }
24546 }
24548 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24549 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24550 alignment from ALIGN to DESIRED_ALIGN. */
24551 static rtx
24554 {
24555 rtx promoted_val;
24564 else
24568 }
24570 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24571 operations when profitable. The code depends upon architecture, block size
24572 and alignment, but always has one of the following overall structures:
24574 Aligned move sequence:
24576 1) Prologue guard: Conditional that jumps up to epilogues for small
24577 blocks that can be handled by epilogue alone. This is faster
24578 but also needed for correctness, since prologue assume the block
24579 is larger than the desired alignment.
24581 Optional dynamic check for size and libcall for large
24582 blocks is emitted here too, with -minline-stringops-dynamically.
24584 2) Prologue: copy first few bytes in order to get destination
24585 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24586 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24587 copied. We emit either a jump tree on power of two sized
24588 blocks, or a byte loop.
24590 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24591 with specified algorithm.
24593 4) Epilogue: code copying tail of the block that is too small to be
24594 handled by main body (or up to size guarded by prologue guard).
24596 Misaligned move sequence
24598 1) missaligned move prologue/epilogue containing:
24599 a) Prologue handling small memory blocks and jumping to done_label
24600 (skipped if blocks are known to be large enough)
24601 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24602 needed by single possibly misaligned move
24603 (skipped if alignment is not needed)
24604 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24606 2) Zero size guard dispatching to done_label, if needed
24608 3) dispatch to library call, if needed,
24610 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24611 with specified algorithm. */
24612 bool
24618 {
24619 rtx destreg;
24622 rtx tmp;
24638 /* TODO: Once value ranges are available, fill in proper data. */
24646 /* i386 can do misaligned access on reasonably increased cost. */
24650 /* ALIGN is the minimum of destination and source alignment, but we care here
24651 just about destination alignment. */
24657 {
24660 /* When COUNT is 0, there is nothing to do. */
24663 }
24664 else
24665 {
24674 }
24676 /* Make sure we don't need to care about overflow later on. */
24680 /* Step 0: Decide on preferred algorithm, desired alignment and
24681 size of chunks to be copied by main loop. */
24683 issetmem,
24690 /* For now vector-version of memset is generated only for memory zeroing, as
24691 creating of promoted vector value is very cheap in this case. */
24704 {
24723 /* Find the widest supported mode. */
24729 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24730 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24732 {
24737 }
24749 }
24757 /* Step 1: Prologue guard. */
24759 /* Alignment code needs count to be in register. */
24761 {
24764 {
24765 align_bytes
24769 else
24771 }
24774 }
24777 /* Misaligned move sequences handle both prologue and epilogue at once.
24778 Default code generation results in a smaller code for large alignments
24779 and also avoids redundant job when sizes are known precisely. */
24780 misaligned_prologue_used
24781 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24787 /* Do the cheap promotion to allow better CSE across the
24788 main loop and epilogue (ie one load of the big constant in the
24789 front of all code.
24790 For now the misaligned move sequences do not have fast path
24791 without broadcasting. */
24793 {
24795 {
24801 }
24802 else
24803 {
24806 }
24807 }
24808 /* Misaligned move sequences handles both prologues and epilogues at once.
24809 Default code generation results in smaller code for large alignments and
24810 also avoids redundant job when sizes are known precisely. */
24812 {
24813 /* Misaligned move prologue handled small blocks by itself. */
24814 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24819 desired_align < align
24828 {
24829 /* It is possible that we copied enough so the main loop will not
24830 execute. */
24840 else
24842 }
24843 }
24844 /* Ensure that alignment prologue won't copy past end of block. */
24846 {
24848 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24849 Make sure it is power of 2. */
24852 /* To improve performance of small blocks, we jump around the VAL
24853 promoting mode. This mean that if the promoted VAL is not constant,
24854 we might not use it in the epilogue and have to use byte
24855 loop variant. */
24860 {
24861 /* If main algorithm works on QImode, no epilogue is needed.
24862 For small sizes just don't align anything. */
24865 else
24867 }
24870 {
24877 else
24879 }
24880 }
24882 /* Emit code to decide on runtime whether library call or inline should be
24883 used. */
24885 {
24887 {
24889 {
24893 }
24894 }
24895 else
24896 {
24906 else
24910 }
24911 }
24913 /* Step 2: Alignment prologue. */
24914 /* Do the expensive promotion once we branched off the small blocks. */
24920 {
24922 {
24923 /* Except for the first move in prologue, we no longer know
24924 constant offset in aliasing info. It don't seems to worth
24925 the pain to maintain it for the first move, so throw away
24926 the info early. */
24933 issetmem);
24934 /* At most desired_align - align bytes are copied. */
24937 else
24939 }
24940 else
24941 {
24942 /* If we know how many bytes need to be stored before dst is
24943 sufficiently aligned, maintain aliasing info accurately. */
24945 srcreg,
24946 promoted_val,
24947 vec_promoted_val,
24948 desired_align,
24949 align_bytes,
24950 issetmem);
24957 }
24959 && !min_size
24964 {
24965 /* It is possible that we copied enough so the main loop will not
24966 execute. */
24976 else
24978 }
24979 }
24981 {
24988 }
24992 /* Step 3: Main loop. */
24995 {
25018 }
25019 /* Adjust properly the offset of src and dest memory for aliasing. */
25021 {
25027 }
25028 else
25029 {
25033 }
25035 /* Step 4: Epilogue to copy the remaining bytes. */
25036 epilogue:
25038 {
25039 /* When the main loop is done, COUNT_EXP might hold original count,
25040 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25041 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25042 bytes. Compensate if needed. */
25045 {
25046 tmp =
25049 OPTAB_DIRECT);
25052 }
25055 }
25058 {
25061 epilogue_size_needed);
25062 else
25063 {
25067 epilogue_size_needed);
25068 else
25070 epilogue_size_needed);
25071 }
25072 }
25076 }
25079 /* Expand the appropriate insns for doing strlen if not just doing
25080 repnz; scasb
25082 out = result, initialized with the start address
25083 align_rtx = alignment of the address.
25084 scratch = scratch register, initialized with the startaddress when
25085 not aligned, otherwise undefined
25087 This is just the body. It needs the initializations mentioned above and
25088 some address computing at the end. These things are done in i386.md. */
25090 static void
25092 {
25094 rtx tmp;
25099 rtx mem;
25102 rtx cmp;
25108 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25110 /* Is there a known alignment and is it less than 4? */
25112 {
25115 /* Is there a known alignment and is it not 2? */
25117 {
25121 /* Leave just the 3 lower bits. */
25131 }
25132 else
25133 {
25134 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25135 check if is aligned to 4 - byte. */
25142 }
25146 /* Now compare the bytes. */
25148 /* Compare the first n unaligned byte on a byte per byte basis. */
25152 /* Increment the address. */
25155 /* Not needed with an alignment of 2 */
25157 {
25161 end_0_label);
25166 }
25169 end_0_label);
25172 }
25174 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25175 align this loop. It gives only huge programs, but does not help to
25176 speed up. */
25183 /* This formula yields a nonzero result iff one of the bytes is zero.
25184 This saves three branches inside loop and many cycles. */
25192 align_4_label);
25195 {
25201 /* If zero is not in the first two bytes, move two bytes forward. */
25207 reg,
25208 tmpreg)));
25209 /* Emit lea manually to avoid clobbering of flags. */
25217 reg2,
25218 out)));
25219 }
25220 else
25221 {
25223 /* Is zero in the first two bytes? */
25230 pc_rtx);
25234 /* Not in the first two. Move two bytes forward. */
25240 }
25242 /* Avoid branch in fixing the byte. */
25250 }
25252 /* Expand strlen. */
25254 bool
25256 {
25259 /* The generic case of strlen expander is long. Avoid it's
25260 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25263 && !TARGET_INLINE_ALL_STRINGOPS
25273 {
25274 /* Well it seems that some optimizer does not combine a call like
25275 foo(strlen(bar), strlen(bar));
25276 when the move and the subtraction is done here. It does calculate
25277 the length just once when these instructions are done inside of
25278 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25279 often used and I use one fewer register for the lifetime of
25280 output_strlen_unroll() this is better. */
25286 /* strlensi_unroll_1 returns the address of the zero at the end of
25287 the string, like memchr(), so compute the length by subtracting
25288 the start address. */
25290 }
25291 else
25292 {
25293 rtx unspec;
25295 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25308 /* If .md starts supporting :P, this can be done in .md. */
25314 }
25316 }
25318 /* For given symbol (function) construct code to compute address of it's PLT
25319 entry in large x86-64 PIC model. */
25320 static rtx
25322 {
25335 }
25337 rtx
25339 rtx callarg2,
25341 {
25351 {
25352 #if TARGET_MACHO
25355 #endif
25356 }
25357 else
25358 {
25359 /* Static functions and indirect calls don't need the pic register. */
25361 && (!TARGET_64BIT
25366 {
25370 pic_offset_table_rtx);
25371 }
25372 }
25375 {
25379 }
25382 && !TARGET_PECOFF
25390 {
25393 }
25398 {
25399 /* We should add bounds as destination register in case
25400 pointer with bounds may be returned. */
25402 {
25407 }
25410 }
25414 {
25418 }
25422 {
25423 int const cregs_size
25428 {
25433 }
25434 }
25443 }
25445 /* Output the assembly for a call instruction. */
25449 {
25455 {
25458 /* SEH epilogue detection requires the indirect branch case
25459 to include REX.W. */
25462 else
25467 }
25469 /* SEH unwinding can require an extra nop to be emitted in several
25470 circumstances. Determine if we have one of those. */
25472 {
25476 {
25477 /* If we get to another real insn, we don't need the nop. */
25481 /* If we get to the epilogue note, prevent a catch region from
25482 being adjacent to the standard epilogue sequence. If non-
25483 call-exceptions, we'll have done this during epilogue emission. */
25485 && !flag_non_call_exceptions
25487 {
25490 }
25491 }
25493 /* If we didn't find a real insn following the call, prevent the
25494 unwinder from looking into the next function. */
25497 }
25501 else
25510 }
25511 \f
25512 /* Clear stack slot assignments remembered from previous functions.
25513 This is called from INIT_EXPANDERS once before RTL is emitted for each
25514 function. */
25518 {
25526 }
25528 /* Return a MEM corresponding to a stack slot with mode MODE.
25529 Allocate a new slot if necessary.
25531 The RTL for a function can have several slots available: N is
25532 which slot to use. */
25534 rtx
25536 {
25553 }
25555 static void
25557 {
25563 }
25564 \f
25565 /* Check whether x86 address PARTS is a pc-relative address. */
25567 static bool
25569 {
25577 {
25579 {
25596 }
25597 }
25599 }
25601 /* Calculate the length of the memory address in the instruction encoding.
25602 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25603 or other prefixes. We never generate addr32 prefix for LEA insn. */
25605 int
25607 {
25624 /* If this is not LEA instruction, add the length of addr32 prefix. */
25629 len++;
25643 /* Rule of thumb:
25644 - esp as the base always wants an index,
25645 - ebp as the base always wants a displacement,
25646 - r12 as the base always wants an index,
25647 - r13 as the base always wants a displacement. */
25649 /* Register Indirect. */
25651 {
25652 /* esp (for its index) and ebp (for its displacement) need
25653 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25654 code. */
25661 len++;
25662 }
25664 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25665 is not disp32, but disp32(%rip), so for disp32
25666 SIB byte is needed, unless print_operand_address
25667 optimizes it into disp32(%rip) or (%rip) is implied
25668 by UNSPEC. */
25670 {
25673 len++;
25674 }
25675 else
25676 {
25677 /* Find the length of the displacement constant. */
25679 {
25682 else
25684 }
25685 /* ebp always wants a displacement. Similarly r13. */
25687 len++;
25689 /* An index requires the two-byte modrm form.... */
25691 /* ...like esp (or r12), which always wants an index. */
25695 len++;
25696 }
25699 }
25701 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25702 is set, expect that insn have 8bit immediate alternative. */
25703 int
25705 {
25711 {
25716 {
25719 {
25731 }
25733 {
25736 }
25737 }
25739 {
25749 /* Immediates for DImode instructions are encoded
25750 as 32bit sign extended values. */
25756 }
25757 }
25759 }
25761 /* Compute default value for "length_address" attribute. */
25762 int
25764 {
25768 {
25779 }
25784 {
25787 {
25792 constraints++;
25795 ;
25796 /* Skip ignored operands. */
25799 }
25801 }
25803 }
25805 /* Compute default value for "length_vex" attribute. It includes
25806 2 or 3 byte VEX prefix and 1 opcode byte. */
25808 int
25811 {
25814 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25815 byte VEX prefix. */
25819 /* We can always use 2 byte VEX prefix in 32bit. */
25827 {
25828 /* REX.W bit uses 3 byte VEX prefix. */
25832 }
25833 else
25834 {
25835 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25839 }
25842 }
25843 \f
25844 /* Return the maximum number of instructions a cpu can issue. */
25846 static int
25848 {
25850 {
25881 }
25882 }
25884 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25885 by DEP_INSN and nothing set by DEP_INSN. */
25887 static bool
25889 {
25892 /* Simplify the test for uninteresting insns. */
25900 {
25903 }
25908 {
25911 }
25912 else
25918 /* This test is true if the dependent insn reads the flags but
25919 not any other potentially set register. */
25927 }
25929 /* Return true iff USE_INSN has a memory address with operands set by
25930 SET_INSN. */
25932 bool
25934 {
25939 {
25942 }
25944 }
25946 /* Helper function for exact_store_load_dependency.
25947 Return true if addr is found in insn. */
25948 static bool
25950 {
25957 {
25963 CASE_CONST_ANY:
25972 }
25976 {
25978 {
25988 }
25989 }
25991 }
25993 /* Return true if there exists exact dependency for store & load, i.e.
25994 the same memory address is used in them. */
25995 static bool
25997 {
26011 }
26013 static int
26015 {
26021 /* Anti and output dependencies have zero cost on all CPUs. */
26027 /* If we can't recognize the insns, we can't really do anything. */
26035 {
26037 /* Address Generation Interlock adds a cycle of latency. */
26039 {
26050 }
26054 /* ??? Compares pair with jump/setcc. */
26058 /* Floating point stores require value to be ready one cycle earlier. */
26066 /* INT->FP conversion is expensive. */
26070 /* There is one cycle extra latency between an FP op and a store. */
26080 /* Show ability of reorder buffer to hide latency of load by executing
26081 in parallel with previous instruction in case
26082 previous instruction is not needed to compute the address. */
26085 {
26086 /* Claim moves to take one cycle, as core can issue one load
26087 at time and the next load can start cycle later. */
26092 cost--;
26093 }
26097 /* The esp dependency is resolved before
26098 the instruction is really finished. */
26103 /* INT->FP conversion is expensive. */
26109 /* Show ability of reorder buffer to hide latency of load by executing
26110 in parallel with previous instruction in case
26111 previous instruction is not needed to compute the address. */
26114 {
26115 /* Claim moves to take one cycle, as core can issue one load
26116 at time and the next load can start cycle later. */
26122 else
26124 }
26135 /* Stack engine allows to execute push&pop instructions in parall. */
26139 /* FALLTHRU */
26145 /* Show ability of reorder buffer to hide latency of load by executing
26146 in parallel with previous instruction in case
26147 previous instruction is not needed to compute the address. */
26150 {
26154 /* Because of the difference between the length of integer and
26155 floating unit pipeline preparation stages, the memory operands
26156 for floating point are cheaper.
26158 ??? For Athlon it the difference is most probably 2. */
26161 else
26166 else
26168 }
26175 /* Stack engine allows to execute push&pop instructions in parall. */
26182 /* Show ability of reorder buffer to hide latency of load by executing
26183 in parallel with previous instruction in case
26184 previous instruction is not needed to compute the address. */
26187 {
26190 else
26192 }
26200 /* Increase cost of integer loads. */
26203 {
26206 {
26209 else
26210 {
26211 /* Increase cost of ld/st for short int types only
26212 because of store forwarding issue. */
26216 {
26217 /* Increase cost of store/load insn if exact
26218 dependence exists and it is load insn. */
26223 }
26224 }
26225 }
26226 }
26230 }
26233 }
26235 /* How many alternative schedules to try. This should be as wide as the
26236 scheduling freedom in the DFA, but no wider. Making this value too
26237 large results extra work for the scheduler. */
26239 static int
26241 {
26243 {
26255 /* We use lookahead value 4 for BD both before and after reload
26256 schedules. Plan is to have value 8 included for O3. */
26266 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26267 as many instructions can be executed on a cycle, i.e.,
26268 issue_rate. I wonder why tuning for many CPUs does not do this. */
26271 /* Don't use lookahead for pre-reload schedule to save compile time. */
26276 }
26277 }
26279 /* Return true if target platform supports macro-fusion. */
26281 static bool
26283 {
26285 }
26287 /* Check whether current microarchitecture support macro fusion
26288 for insn pair "CONDGEN + CONDJMP". Refer to
26289 "Intel Architectures Optimization Reference Manual". */
26291 static bool
26293 {
26314 {
26319 {
26323 else
26325 }
26326 }
26333 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26334 supported. */
26341 /* No fusion for RIP-relative address. */
26348 ix86_address parts;
26354 }
26359 /* Check whether conditional jump use Sign or Overflow Flags. */
26367 /* Return true for TYPE_TEST and TYPE_ICMP. */
26372 /* The following is the case that macro-fusion for alu + jmp. */
26376 /* No fusion for alu op with memory destination operand. */
26381 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26382 supported. */
26391 }
26393 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26394 execution. It is applied if
26395 (1) IMUL instruction is on the top of list;
26396 (2) There exists the only producer of independent IMUL instruction in
26397 ready list.
26398 Return index of IMUL producer if it was found and -1 otherwise. */
26399 static int
26401 {
26404 sd_iterator_def sd_it;
26405 dep_t dep;
26412 /* Check that IMUL instruction is on the top of ready list. */
26421 /* Search for producer of independent IMUL instruction. */
26423 {
26427 /* Skip IMUL instruction. */
26437 {
26438 rtx con;
26449 {
26450 sd_iterator_def sd_it1;
26451 dep_t dep1;
26452 /* Check if there is no other dependee for IMUL. */
26455 {
26456 rtx pro;
26462 }
26465 }
26466 }
26469 }
26471 }
26473 /* Try to find the best candidate on the top of ready list if two insns
26474 have the same priority - candidate is best if its dependees were
26475 scheduled earlier. Applied for Silvermont only.
26476 Return true if top 2 insns must be interchanged. */
26477 static bool
26479 {
26482 rtx set;
26483 sd_iterator_def sd_it;
26484 dep_t dep;
26487 #define INSN_TICK(INSN) (HID (INSN)->tick)
26508 {
26511 /* Determine winner more precise. */
26513 {
26514 rtx pro;
26520 }
26522 {
26523 rtx pro;
26529 }
26532 {
26533 /* Determine winner - load must win. */
26539 }
26541 }
26543 #undef INSN_TICK
26544 }
26546 /* Perform possible reodering of ready list for Atom/Silvermont only.
26547 Return issue rate. */
26548 static int
26551 {
26558 /* Set up issue rate. */
26561 /* Do reodering for BONNELL/SILVERMONT only. */
26565 /* Nothing to do if ready list contains only 1 instruction. */
26569 /* Do reodering for post-reload scheduler only. */
26574 {
26579 /* Put IMUL producer (ready[index]) at the top of ready list. */
26585 }
26587 {
26591 /* Swap 2 top elements of ready list. */
26595 }
26597 }
26599 static bool
26602 /* Returns true if lhs of insn is HW function argument register and set up
26603 is_spilled to true if it is likely spilled HW register. */
26604 static bool
26606 {
26607 rtx dst;
26611 /* Call instructions are not movable, ignore it. */
26622 {
26623 /* Is it likely spilled HW register? */
26628 }
26630 }
26632 /* Add output dependencies for chain of function adjacent arguments if only
26633 there is a move to likely spilled HW register. Return first argument
26634 if at least one dependence was added or NULL otherwise. */
26637 {
26645 /* Find nearest to call argument passing instruction. */
26647 {
26656 }
26660 {
26667 {
26670 }
26672 {
26673 /* Add output depdendence between two function arguments if chain
26674 of output arguments contains likely spilled HW registers. */
26678 }
26679 else
26681 }
26685 }
26687 /* Add output or anti dependency from insn to first_arg to restrict its code
26688 motion. */
26689 static void
26691 {
26692 rtx set;
26693 rtx tmp;
26700 {
26701 /* Add output dependency to the first function argument. */
26704 }
26705 /* Add anti dependency. */
26707 }
26709 /* Avoid cross block motion of function argument through adding dependency
26710 from the first non-jump instruction in bb. */
26711 static void
26713 {
26717 {
26719 {
26722 {
26725 }
26726 }
26730 }
26731 }
26733 /* Hook for pre-reload schedule - avoid motion of function arguments
26734 passed in likely spilled HW registers. */
26735 static void
26737 {
26746 {
26749 {
26750 /* Add dependee for first argument to predecessors if only
26751 region contains more than one block. */
26755 /* Skip trivial regions and region head blocks that can have
26756 predecessors outside of region. */
26758 {
26759 edge e;
26760 edge_iterator ei;
26762 /* Regions are SCCs with the exception of selective
26763 scheduling with pipelining of outer blocks enabled.
26764 So also check that immediate predecessors of a non-head
26765 block are in the same region. */
26767 {
26768 /* Avoid creating of loop-carried dependencies through
26769 using topological ordering in the region. */
26773 }
26774 }
26778 }
26779 }
26782 }
26784 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26785 HW registers to maximum, to schedule them at soon as possible. These are
26786 moves from function argument registers at the top of the function entry
26787 and moves from function return value registers after call. */
26788 static int
26790 {
26791 rtx set;
26801 {
26808 }
26811 }
26813 /* Model decoder of Core 2/i7.
26814 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26815 track the instruction fetch block boundaries and make sure that long
26816 (9+ bytes) instructions are assigned to D0. */
26818 /* Maximum length of an insn that can be handled by
26819 a secondary decoder unit. '8' for Core 2/i7. */
26822 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26823 '16' for Core 2/i7. */
26826 /* Maximum number of instructions decoder can handle per cycle.
26827 '6' for Core 2/i7. */
26831 ix86_first_cycle_multipass_data_t;
26833 const_ix86_first_cycle_multipass_data_t;
26835 /* A variable to store target state across calls to max_issue within
26836 one cycle. */
26840 /* Initialize DATA. */
26841 static void
26843 {
26844 ix86_first_cycle_multipass_data_t data
26851 }
26853 /* Advancing the cycle; reset ifetch block counts. */
26854 static void
26856 {
26863 }
26867 /* Filter out insns from ready_try that the core will not be able to issue
26868 on current cycle due to decoder. */
26869 static void
26870 core2i7_first_cycle_multipass_filter_ready_try
26873 {
26875 {
26886 (!first_cycle_insn_p
26888 /* ... or it would not fit into the ifetch block ... */
26890 /* ... or the decoder is full already ... */
26892 /* ... mask the insn out. */
26893 {
26898 }
26899 }
26900 }
26902 /* Prepare for a new round of multipass lookahead scheduling. */
26903 static void
26907 {
26908 ix86_first_cycle_multipass_data_t data
26910 const_ix86_first_cycle_multipass_data_t prev_data
26913 /* Restore the state from the end of the previous round. */
26917 /* Filter instructions that cannot be issued on current cycle due to
26918 decoder restrictions. */
26920 first_cycle_insn_p);
26921 }
26923 /* INSN is being issued in current solution. Account for its impact on
26924 the decoder model. */
26925 static void
26929 {
26930 ix86_first_cycle_multipass_data_t data
26932 const_ix86_first_cycle_multipass_data_t prev_data
26942 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
26944 {
26947 }
26949 {
26953 }
26956 /* Filter out insns from ready_try that the core will not be able to issue
26957 on current cycle due to decoder. */
26960 }
26962 /* Revert the effect on ready_try. */
26963 static void
26967 {
26968 const_ix86_first_cycle_multipass_data_t data
26971 sbitmap_iterator sbi;
26975 {
26977 }
26978 }
26980 /* Save the result of multipass lookahead scheduling for the next round. */
26981 static void
26983 {
26984 const_ix86_first_cycle_multipass_data_t data
26986 ix86_first_cycle_multipass_data_t next_data
26990 {
26993 }
26994 }
26996 /* Deallocate target data. */
26997 static void
26999 {
27000 ix86_first_cycle_multipass_data_t data
27004 {
27008 }
27009 }
27011 /* Prepare for scheduling pass. */
27012 static void
27014 {
27015 /* Install scheduling hooks for current CPU. Some of these hooks are used
27016 in time-critical parts of the scheduler, so we only set them up when
27017 they are actually used. */
27019 {
27024 /* Do not perform multipass scheduling for pre-reload schedule
27025 to save compile time. */
27027 {
27043 /* Set decoder parameters. */
27048 }
27049 /* ... Fall through ... */
27059 }
27060 }
27062 \f
27063 /* Compute the alignment given to a constant that is being placed in memory.
27064 EXP is the constant and ALIGN is the alignment that the object would
27065 ordinarily have.
27066 The value of this function is used instead of that alignment to align
27067 the object. */
27069 int
27071 {
27074 {
27079 }
27085 }
27087 /* Compute the alignment for a static variable.
27088 TYPE is the data type, and ALIGN is the alignment that
27089 the object would ordinarily have. The value of this function is used
27090 instead of that alignment to align the object. */
27092 int
27094 {
27095 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27096 for symbols from other compilation units or symbols that don't need
27097 to bind locally. In order to preserve some ABI compatibility with
27098 those compilers, ensure we don't decrease alignment from what we
27099 used to assume. */
27101 int max_align_compat
27104 /* A data structure, equal or greater than the size of a cache line
27105 (64 bytes in the Pentium 4 and other recent Intel processors, including
27106 processors based on Intel Core microarchitecture) should be aligned
27107 so that its base address is a multiple of a cache line size. */
27109 int max_align
27119 {
27126 }
27128 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27129 to 16byte boundary. */
27131 {
27138 }
27144 {
27149 }
27151 {
27158 }
27163 {
27168 }
27171 {
27176 }
27179 }
27181 /* Compute the alignment for a local variable or a stack slot. EXP is
27182 the data type or decl itself, MODE is the widest mode available and
27183 ALIGN is the alignment that the object would ordinarily have. The
27184 value of this macro is used instead of that alignment to align the
27185 object. */
27187 unsigned int
27190 {
27194 {
27197 }
27198 else
27199 {
27202 }
27204 /* Don't do dynamic stack realignment for long long objects with
27205 -mpreferred-stack-boundary=2. */
27214 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27215 register in MODE. We will return the largest alignment of XF
27216 and DF. */
27218 {
27222 }
27224 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27225 to 16byte boundary. Exact wording is:
27227 An array uses the same alignment as its elements, except that a local or
27228 global array variable of length at least 16 bytes or
27229 a C99 variable-length array variable always has alignment of at least 16 bytes.
27231 This was added to allow use of aligned SSE instructions at arrays. This
27232 rule is meant for static storage (where compiler can not do the analysis
27233 by itself). We follow it for automatic variables only when convenient.
27234 We fully control everything in the function compiled and functions from
27235 other unit can not rely on the alignment.
27237 Exclude va_list type. It is the common case of local array where
27238 we can not benefit from the alignment.
27240 TODO: Probably one should optimize for size only when var is not escaping. */
27243 {
27253 }
27255 {
27260 }
27262 {
27268 }
27273 {
27278 }
27281 {
27287 }
27289 }
27291 /* Compute the minimum required alignment for dynamic stack realignment
27292 purposes for a local variable, parameter or a stack slot. EXP is
27293 the data type or decl itself, MODE is its mode and ALIGN is the
27294 alignment that the object would ordinarily have. */
27296 unsigned int
27299 {
27303 {
27306 }
27307 else
27308 {
27311 }
27316 /* Don't do dynamic stack realignment for long long objects with
27317 -mpreferred-stack-boundary=2. */
27324 }
27325 \f
27326 /* Find a location for the static chain incoming to a nested function.
27327 This is a register, unless all free registers are used by arguments. */
27329 static rtx
27331 {
27338 {
27339 /* We always use R10 in 64-bit mode. */
27341 }
27342 else
27343 {
27344 tree fntype;
27347 /* By default in 32-bit mode we use ECX to pass the static chain. */
27353 {
27354 /* Fastcall functions use ecx/edx for arguments, which leaves
27355 us with EAX for the static chain.
27356 Thiscall functions use ecx for arguments, which also
27357 leaves us with EAX for the static chain. */
27359 }
27361 {
27362 /* Thiscall functions use ecx for arguments, which leaves
27363 us with EAX and EDX for the static chain.
27364 We are using for abi-compatibility EAX. */
27366 }
27368 {
27369 /* For regparm 3, we have no free call-clobbered registers in
27370 which to store the static chain. In order to implement this,
27371 we have the trampoline push the static chain to the stack.
27372 However, we can't push a value below the return address when
27373 we call the nested function directly, so we have to use an
27374 alternate entry point. For this we use ESI, and have the
27375 alternate entry point push ESI, so that things appear the
27376 same once we're executing the nested function. */
27378 {
27384 }
27386 }
27387 }
27390 }
27392 /* Emit RTL insns to initialize the variable parts of a trampoline.
27393 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27394 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27395 to be passed to the target function. */
27397 static void
27399 {
27407 {
27410 /* Load the function address to r11. Try to load address using
27411 the shorter movl instead of movabs. We may want to support
27412 movq for kernel mode, but kernel does not use trampolines at
27413 the moment. FNADDR is a 32bit address and may not be in
27414 DImode when ptr_mode == SImode. Always use movl in this
27415 case. */
27418 {
27427 }
27428 else
27429 {
27436 }
27438 /* Load static chain using movabs to r10. Use the shorter movl
27439 instead of movabs when ptr_mode == SImode. */
27441 {
27444 }
27445 else
27446 {
27449 }
27458 /* Jump to r11; the last (unused) byte is a nop, only there to
27459 pad the write out to a single 32-bit store. */
27463 }
27464 else
27465 {
27468 /* Depending on the static chain location, either load a register
27469 with a constant, or push the constant to the stack. All of the
27470 instructions are the same size. */
27473 {
27475 {
27482 }
27483 }
27484 else
27499 /* Compute offset from the end of the jmp to the target function.
27500 In the case in which the trampoline stores the static chain on
27501 the stack, we need to skip the first insn which pushes the
27502 (call-saved) register static chain; this push is 1 byte. */
27509 }
27513 #ifdef HAVE_ENABLE_EXECUTE_STACK
27514 #ifdef CHECK_EXECUTE_STACK_ENABLED
27516 #endif
27519 #endif
27520 }
27521 \f
27522 /* The following file contains several enumerations and data structures
27523 built from the definitions in i386-builtin-types.def. */
27527 /* Table for the ix86 builtin non-function types. */
27530 /* Retrieve an element from the above table, building some of
27531 the types lazily. */
27533 static tree
27535 {
27547 {
27548 machine_mode mode;
27555 }
27556 else
27557 {
27563 else
27571 }
27575 }
27577 /* Table for the ix86 builtin function types. */
27580 /* Retrieve an element from the above table, building some of
27581 the types lazily. */
27583 static tree
27585 {
27586 tree type;
27595 {
27603 {
27606 }
27609 }
27610 else
27611 {
27617 }
27621 }
27624 /* Codes for all the SSE/MMX builtins. */
27625 enum ix86_builtins
27626 {
27627 IX86_BUILTIN_ADDPS,
27628 IX86_BUILTIN_ADDSS,
27629 IX86_BUILTIN_DIVPS,
27630 IX86_BUILTIN_DIVSS,
27631 IX86_BUILTIN_MULPS,
27632 IX86_BUILTIN_MULSS,
27633 IX86_BUILTIN_SUBPS,
27634 IX86_BUILTIN_SUBSS,
27636 IX86_BUILTIN_CMPEQPS,
27637 IX86_BUILTIN_CMPLTPS,
27638 IX86_BUILTIN_CMPLEPS,
27639 IX86_BUILTIN_CMPGTPS,
27640 IX86_BUILTIN_CMPGEPS,
27641 IX86_BUILTIN_CMPNEQPS,
27642 IX86_BUILTIN_CMPNLTPS,
27643 IX86_BUILTIN_CMPNLEPS,
27644 IX86_BUILTIN_CMPNGTPS,
27645 IX86_BUILTIN_CMPNGEPS,
27646 IX86_BUILTIN_CMPORDPS,
27647 IX86_BUILTIN_CMPUNORDPS,
27648 IX86_BUILTIN_CMPEQSS,
27649 IX86_BUILTIN_CMPLTSS,
27650 IX86_BUILTIN_CMPLESS,
27651 IX86_BUILTIN_CMPNEQSS,
27652 IX86_BUILTIN_CMPNLTSS,
27653 IX86_BUILTIN_CMPNLESS,
27654 IX86_BUILTIN_CMPORDSS,
27655 IX86_BUILTIN_CMPUNORDSS,
27657 IX86_BUILTIN_COMIEQSS,
27658 IX86_BUILTIN_COMILTSS,
27659 IX86_BUILTIN_COMILESS,
27660 IX86_BUILTIN_COMIGTSS,
27661 IX86_BUILTIN_COMIGESS,
27662 IX86_BUILTIN_COMINEQSS,
27663 IX86_BUILTIN_UCOMIEQSS,
27664 IX86_BUILTIN_UCOMILTSS,
27665 IX86_BUILTIN_UCOMILESS,
27666 IX86_BUILTIN_UCOMIGTSS,
27667 IX86_BUILTIN_UCOMIGESS,
27668 IX86_BUILTIN_UCOMINEQSS,
27670 IX86_BUILTIN_CVTPI2PS,
27671 IX86_BUILTIN_CVTPS2PI,
27672 IX86_BUILTIN_CVTSI2SS,
27673 IX86_BUILTIN_CVTSI642SS,
27674 IX86_BUILTIN_CVTSS2SI,
27675 IX86_BUILTIN_CVTSS2SI64,
27676 IX86_BUILTIN_CVTTPS2PI,
27677 IX86_BUILTIN_CVTTSS2SI,
27678 IX86_BUILTIN_CVTTSS2SI64,
27680 IX86_BUILTIN_MAXPS,
27681 IX86_BUILTIN_MAXSS,
27682 IX86_BUILTIN_MINPS,
27683 IX86_BUILTIN_MINSS,
27685 IX86_BUILTIN_LOADUPS,
27686 IX86_BUILTIN_STOREUPS,
27687 IX86_BUILTIN_MOVSS,
27689 IX86_BUILTIN_MOVHLPS,
27690 IX86_BUILTIN_MOVLHPS,
27691 IX86_BUILTIN_LOADHPS,
27692 IX86_BUILTIN_LOADLPS,
27693 IX86_BUILTIN_STOREHPS,
27694 IX86_BUILTIN_STORELPS,
27696 IX86_BUILTIN_MASKMOVQ,
27697 IX86_BUILTIN_MOVMSKPS,
27698 IX86_BUILTIN_PMOVMSKB,
27700 IX86_BUILTIN_MOVNTPS,
27701 IX86_BUILTIN_MOVNTQ,
27703 IX86_BUILTIN_LOADDQU,
27704 IX86_BUILTIN_STOREDQU,
27706 IX86_BUILTIN_PACKSSWB,
27707 IX86_BUILTIN_PACKSSDW,
27708 IX86_BUILTIN_PACKUSWB,
27710 IX86_BUILTIN_PADDB,
27711 IX86_BUILTIN_PADDW,
27712 IX86_BUILTIN_PADDD,
27713 IX86_BUILTIN_PADDQ,
27714 IX86_BUILTIN_PADDSB,
27715 IX86_BUILTIN_PADDSW,
27716 IX86_BUILTIN_PADDUSB,
27717 IX86_BUILTIN_PADDUSW,
27718 IX86_BUILTIN_PSUBB,
27719 IX86_BUILTIN_PSUBW,
27720 IX86_BUILTIN_PSUBD,
27721 IX86_BUILTIN_PSUBQ,
27722 IX86_BUILTIN_PSUBSB,
27723 IX86_BUILTIN_PSUBSW,
27724 IX86_BUILTIN_PSUBUSB,
27725 IX86_BUILTIN_PSUBUSW,
27727 IX86_BUILTIN_PAND,
27728 IX86_BUILTIN_PANDN,
27729 IX86_BUILTIN_POR,
27730 IX86_BUILTIN_PXOR,
27732 IX86_BUILTIN_PAVGB,
27733 IX86_BUILTIN_PAVGW,
27735 IX86_BUILTIN_PCMPEQB,
27736 IX86_BUILTIN_PCMPEQW,
27737 IX86_BUILTIN_PCMPEQD,
27738 IX86_BUILTIN_PCMPGTB,
27739 IX86_BUILTIN_PCMPGTW,
27740 IX86_BUILTIN_PCMPGTD,
27742 IX86_BUILTIN_PMADDWD,
27744 IX86_BUILTIN_PMAXSW,
27745 IX86_BUILTIN_PMAXUB,
27746 IX86_BUILTIN_PMINSW,
27747 IX86_BUILTIN_PMINUB,
27749 IX86_BUILTIN_PMULHUW,
27750 IX86_BUILTIN_PMULHW,
27751 IX86_BUILTIN_PMULLW,
27753 IX86_BUILTIN_PSADBW,
27754 IX86_BUILTIN_PSHUFW,
27756 IX86_BUILTIN_PSLLW,
27757 IX86_BUILTIN_PSLLD,
27758 IX86_BUILTIN_PSLLQ,
27759 IX86_BUILTIN_PSRAW,
27760 IX86_BUILTIN_PSRAD,
27761 IX86_BUILTIN_PSRLW,
27762 IX86_BUILTIN_PSRLD,
27763 IX86_BUILTIN_PSRLQ,
27764 IX86_BUILTIN_PSLLWI,
27765 IX86_BUILTIN_PSLLDI,
27766 IX86_BUILTIN_PSLLQI,
27767 IX86_BUILTIN_PSRAWI,
27768 IX86_BUILTIN_PSRADI,
27769 IX86_BUILTIN_PSRLWI,
27770 IX86_BUILTIN_PSRLDI,
27771 IX86_BUILTIN_PSRLQI,
27773 IX86_BUILTIN_PUNPCKHBW,
27774 IX86_BUILTIN_PUNPCKHWD,
27775 IX86_BUILTIN_PUNPCKHDQ,
27776 IX86_BUILTIN_PUNPCKLBW,
27777 IX86_BUILTIN_PUNPCKLWD,
27778 IX86_BUILTIN_PUNPCKLDQ,
27780 IX86_BUILTIN_SHUFPS,
27782 IX86_BUILTIN_RCPPS,
27783 IX86_BUILTIN_RCPSS,
27784 IX86_BUILTIN_RSQRTPS,
27785 IX86_BUILTIN_RSQRTPS_NR,
27786 IX86_BUILTIN_RSQRTSS,
27787 IX86_BUILTIN_RSQRTF,
27788 IX86_BUILTIN_SQRTPS,
27789 IX86_BUILTIN_SQRTPS_NR,
27790 IX86_BUILTIN_SQRTSS,
27792 IX86_BUILTIN_UNPCKHPS,
27793 IX86_BUILTIN_UNPCKLPS,
27795 IX86_BUILTIN_ANDPS,
27796 IX86_BUILTIN_ANDNPS,
27797 IX86_BUILTIN_ORPS,
27798 IX86_BUILTIN_XORPS,
27800 IX86_BUILTIN_EMMS,
27801 IX86_BUILTIN_LDMXCSR,
27802 IX86_BUILTIN_STMXCSR,
27803 IX86_BUILTIN_SFENCE,
27805 IX86_BUILTIN_FXSAVE,
27806 IX86_BUILTIN_FXRSTOR,
27807 IX86_BUILTIN_FXSAVE64,
27808 IX86_BUILTIN_FXRSTOR64,
27810 IX86_BUILTIN_XSAVE,
27811 IX86_BUILTIN_XRSTOR,
27812 IX86_BUILTIN_XSAVE64,
27813 IX86_BUILTIN_XRSTOR64,
27815 IX86_BUILTIN_XSAVEOPT,
27816 IX86_BUILTIN_XSAVEOPT64,
27818 IX86_BUILTIN_XSAVEC,
27819 IX86_BUILTIN_XSAVEC64,
27821 IX86_BUILTIN_XSAVES,
27822 IX86_BUILTIN_XRSTORS,
27823 IX86_BUILTIN_XSAVES64,
27824 IX86_BUILTIN_XRSTORS64,
27826 /* 3DNow! Original */
27827 IX86_BUILTIN_FEMMS,
27828 IX86_BUILTIN_PAVGUSB,
27829 IX86_BUILTIN_PF2ID,
27830 IX86_BUILTIN_PFACC,
27831 IX86_BUILTIN_PFADD,
27832 IX86_BUILTIN_PFCMPEQ,
27833 IX86_BUILTIN_PFCMPGE,
27834 IX86_BUILTIN_PFCMPGT,
27835 IX86_BUILTIN_PFMAX,
27836 IX86_BUILTIN_PFMIN,
27837 IX86_BUILTIN_PFMUL,
27838 IX86_BUILTIN_PFRCP,
27839 IX86_BUILTIN_PFRCPIT1,
27840 IX86_BUILTIN_PFRCPIT2,
27841 IX86_BUILTIN_PFRSQIT1,
27842 IX86_BUILTIN_PFRSQRT,
27843 IX86_BUILTIN_PFSUB,
27844 IX86_BUILTIN_PFSUBR,
27845 IX86_BUILTIN_PI2FD,
27846 IX86_BUILTIN_PMULHRW,
27848 /* 3DNow! Athlon Extensions */
27849 IX86_BUILTIN_PF2IW,
27850 IX86_BUILTIN_PFNACC,
27851 IX86_BUILTIN_PFPNACC,
27852 IX86_BUILTIN_PI2FW,
27853 IX86_BUILTIN_PSWAPDSI,
27854 IX86_BUILTIN_PSWAPDSF,
27856 /* SSE2 */
27857 IX86_BUILTIN_ADDPD,
27858 IX86_BUILTIN_ADDSD,
27859 IX86_BUILTIN_DIVPD,
27860 IX86_BUILTIN_DIVSD,
27861 IX86_BUILTIN_MULPD,
27862 IX86_BUILTIN_MULSD,
27863 IX86_BUILTIN_SUBPD,
27864 IX86_BUILTIN_SUBSD,
27866 IX86_BUILTIN_CMPEQPD,
27867 IX86_BUILTIN_CMPLTPD,
27868 IX86_BUILTIN_CMPLEPD,
27869 IX86_BUILTIN_CMPGTPD,
27870 IX86_BUILTIN_CMPGEPD,
27871 IX86_BUILTIN_CMPNEQPD,
27872 IX86_BUILTIN_CMPNLTPD,
27873 IX86_BUILTIN_CMPNLEPD,
27874 IX86_BUILTIN_CMPNGTPD,
27875 IX86_BUILTIN_CMPNGEPD,
27876 IX86_BUILTIN_CMPORDPD,
27877 IX86_BUILTIN_CMPUNORDPD,
27878 IX86_BUILTIN_CMPEQSD,
27879 IX86_BUILTIN_CMPLTSD,
27880 IX86_BUILTIN_CMPLESD,
27881 IX86_BUILTIN_CMPNEQSD,
27882 IX86_BUILTIN_CMPNLTSD,
27883 IX86_BUILTIN_CMPNLESD,
27884 IX86_BUILTIN_CMPORDSD,
27885 IX86_BUILTIN_CMPUNORDSD,
27887 IX86_BUILTIN_COMIEQSD,
27888 IX86_BUILTIN_COMILTSD,
27889 IX86_BUILTIN_COMILESD,
27890 IX86_BUILTIN_COMIGTSD,
27891 IX86_BUILTIN_COMIGESD,
27892 IX86_BUILTIN_COMINEQSD,
27893 IX86_BUILTIN_UCOMIEQSD,
27894 IX86_BUILTIN_UCOMILTSD,
27895 IX86_BUILTIN_UCOMILESD,
27896 IX86_BUILTIN_UCOMIGTSD,
27897 IX86_BUILTIN_UCOMIGESD,
27898 IX86_BUILTIN_UCOMINEQSD,
27900 IX86_BUILTIN_MAXPD,
27901 IX86_BUILTIN_MAXSD,
27902 IX86_BUILTIN_MINPD,
27903 IX86_BUILTIN_MINSD,
27905 IX86_BUILTIN_ANDPD,
27906 IX86_BUILTIN_ANDNPD,
27907 IX86_BUILTIN_ORPD,
27908 IX86_BUILTIN_XORPD,
27910 IX86_BUILTIN_SQRTPD,
27911 IX86_BUILTIN_SQRTSD,
27913 IX86_BUILTIN_UNPCKHPD,
27914 IX86_BUILTIN_UNPCKLPD,
27916 IX86_BUILTIN_SHUFPD,
27918 IX86_BUILTIN_LOADUPD,
27919 IX86_BUILTIN_STOREUPD,
27920 IX86_BUILTIN_MOVSD,
27922 IX86_BUILTIN_LOADHPD,
27923 IX86_BUILTIN_LOADLPD,
27925 IX86_BUILTIN_CVTDQ2PD,
27926 IX86_BUILTIN_CVTDQ2PS,
27928 IX86_BUILTIN_CVTPD2DQ,
27929 IX86_BUILTIN_CVTPD2PI,
27930 IX86_BUILTIN_CVTPD2PS,
27931 IX86_BUILTIN_CVTTPD2DQ,
27932 IX86_BUILTIN_CVTTPD2PI,
27934 IX86_BUILTIN_CVTPI2PD,
27935 IX86_BUILTIN_CVTSI2SD,
27936 IX86_BUILTIN_CVTSI642SD,
27938 IX86_BUILTIN_CVTSD2SI,
27939 IX86_BUILTIN_CVTSD2SI64,
27940 IX86_BUILTIN_CVTSD2SS,
27941 IX86_BUILTIN_CVTSS2SD,
27942 IX86_BUILTIN_CVTTSD2SI,
27943 IX86_BUILTIN_CVTTSD2SI64,
27945 IX86_BUILTIN_CVTPS2DQ,
27946 IX86_BUILTIN_CVTPS2PD,
27947 IX86_BUILTIN_CVTTPS2DQ,
27949 IX86_BUILTIN_MOVNTI,
27950 IX86_BUILTIN_MOVNTI64,
27951 IX86_BUILTIN_MOVNTPD,
27952 IX86_BUILTIN_MOVNTDQ,
27954 IX86_BUILTIN_MOVQ128,
27956 /* SSE2 MMX */
27957 IX86_BUILTIN_MASKMOVDQU,
27958 IX86_BUILTIN_MOVMSKPD,
27959 IX86_BUILTIN_PMOVMSKB128,
27961 IX86_BUILTIN_PACKSSWB128,
27962 IX86_BUILTIN_PACKSSDW128,
27963 IX86_BUILTIN_PACKUSWB128,
27965 IX86_BUILTIN_PADDB128,
27966 IX86_BUILTIN_PADDW128,
27967 IX86_BUILTIN_PADDD128,
27968 IX86_BUILTIN_PADDQ128,
27969 IX86_BUILTIN_PADDSB128,
27970 IX86_BUILTIN_PADDSW128,
27971 IX86_BUILTIN_PADDUSB128,
27972 IX86_BUILTIN_PADDUSW128,
27973 IX86_BUILTIN_PSUBB128,
27974 IX86_BUILTIN_PSUBW128,
27975 IX86_BUILTIN_PSUBD128,
27976 IX86_BUILTIN_PSUBQ128,
27977 IX86_BUILTIN_PSUBSB128,
27978 IX86_BUILTIN_PSUBSW128,
27979 IX86_BUILTIN_PSUBUSB128,
27980 IX86_BUILTIN_PSUBUSW128,
27982 IX86_BUILTIN_PAND128,
27983 IX86_BUILTIN_PANDN128,
27984 IX86_BUILTIN_POR128,
27985 IX86_BUILTIN_PXOR128,
27987 IX86_BUILTIN_PAVGB128,
27988 IX86_BUILTIN_PAVGW128,
27990 IX86_BUILTIN_PCMPEQB128,
27991 IX86_BUILTIN_PCMPEQW128,
27992 IX86_BUILTIN_PCMPEQD128,
27993 IX86_BUILTIN_PCMPGTB128,
27994 IX86_BUILTIN_PCMPGTW128,
27995 IX86_BUILTIN_PCMPGTD128,
27997 IX86_BUILTIN_PMADDWD128,
27999 IX86_BUILTIN_PMAXSW128,
28000 IX86_BUILTIN_PMAXUB128,
28001 IX86_BUILTIN_PMINSW128,
28002 IX86_BUILTIN_PMINUB128,
28004 IX86_BUILTIN_PMULUDQ,
28005 IX86_BUILTIN_PMULUDQ128,
28006 IX86_BUILTIN_PMULHUW128,
28007 IX86_BUILTIN_PMULHW128,
28008 IX86_BUILTIN_PMULLW128,
28010 IX86_BUILTIN_PSADBW128,
28011 IX86_BUILTIN_PSHUFHW,
28012 IX86_BUILTIN_PSHUFLW,
28013 IX86_BUILTIN_PSHUFD,
28015 IX86_BUILTIN_PSLLDQI128,
28016 IX86_BUILTIN_PSLLWI128,
28017 IX86_BUILTIN_PSLLDI128,
28018 IX86_BUILTIN_PSLLQI128,
28019 IX86_BUILTIN_PSRAWI128,
28020 IX86_BUILTIN_PSRADI128,
28021 IX86_BUILTIN_PSRLDQI128,
28022 IX86_BUILTIN_PSRLWI128,
28023 IX86_BUILTIN_PSRLDI128,
28024 IX86_BUILTIN_PSRLQI128,
28026 IX86_BUILTIN_PSLLDQ128,
28027 IX86_BUILTIN_PSLLW128,
28028 IX86_BUILTIN_PSLLD128,
28029 IX86_BUILTIN_PSLLQ128,
28030 IX86_BUILTIN_PSRAW128,
28031 IX86_BUILTIN_PSRAD128,
28032 IX86_BUILTIN_PSRLW128,
28033 IX86_BUILTIN_PSRLD128,
28034 IX86_BUILTIN_PSRLQ128,
28036 IX86_BUILTIN_PUNPCKHBW128,
28037 IX86_BUILTIN_PUNPCKHWD128,
28038 IX86_BUILTIN_PUNPCKHDQ128,
28039 IX86_BUILTIN_PUNPCKHQDQ128,
28040 IX86_BUILTIN_PUNPCKLBW128,
28041 IX86_BUILTIN_PUNPCKLWD128,
28042 IX86_BUILTIN_PUNPCKLDQ128,
28043 IX86_BUILTIN_PUNPCKLQDQ128,
28045 IX86_BUILTIN_CLFLUSH,
28046 IX86_BUILTIN_MFENCE,
28047 IX86_BUILTIN_LFENCE,
28048 IX86_BUILTIN_PAUSE,
28050 IX86_BUILTIN_FNSTENV,
28051 IX86_BUILTIN_FLDENV,
28052 IX86_BUILTIN_FNSTSW,
28053 IX86_BUILTIN_FNCLEX,
28055 IX86_BUILTIN_BSRSI,
28056 IX86_BUILTIN_BSRDI,
28057 IX86_BUILTIN_RDPMC,
28058 IX86_BUILTIN_RDTSC,
28059 IX86_BUILTIN_RDTSCP,
28060 IX86_BUILTIN_ROLQI,
28061 IX86_BUILTIN_ROLHI,
28062 IX86_BUILTIN_RORQI,
28063 IX86_BUILTIN_RORHI,
28065 /* SSE3. */
28066 IX86_BUILTIN_ADDSUBPS,
28067 IX86_BUILTIN_HADDPS,
28068 IX86_BUILTIN_HSUBPS,
28069 IX86_BUILTIN_MOVSHDUP,
28070 IX86_BUILTIN_MOVSLDUP,
28071 IX86_BUILTIN_ADDSUBPD,
28072 IX86_BUILTIN_HADDPD,
28073 IX86_BUILTIN_HSUBPD,
28074 IX86_BUILTIN_LDDQU,
28076 IX86_BUILTIN_MONITOR,
28077 IX86_BUILTIN_MWAIT,
28079 /* SSSE3. */
28080 IX86_BUILTIN_PHADDW,
28081 IX86_BUILTIN_PHADDD,
28082 IX86_BUILTIN_PHADDSW,
28083 IX86_BUILTIN_PHSUBW,
28084 IX86_BUILTIN_PHSUBD,
28085 IX86_BUILTIN_PHSUBSW,
28086 IX86_BUILTIN_PMADDUBSW,
28087 IX86_BUILTIN_PMULHRSW,
28088 IX86_BUILTIN_PSHUFB,
28089 IX86_BUILTIN_PSIGNB,
28090 IX86_BUILTIN_PSIGNW,
28091 IX86_BUILTIN_PSIGND,
28092 IX86_BUILTIN_PALIGNR,
28093 IX86_BUILTIN_PABSB,
28094 IX86_BUILTIN_PABSW,
28095 IX86_BUILTIN_PABSD,
28097 IX86_BUILTIN_PHADDW128,
28098 IX86_BUILTIN_PHADDD128,
28099 IX86_BUILTIN_PHADDSW128,
28100 IX86_BUILTIN_PHSUBW128,
28101 IX86_BUILTIN_PHSUBD128,
28102 IX86_BUILTIN_PHSUBSW128,
28103 IX86_BUILTIN_PMADDUBSW128,
28104 IX86_BUILTIN_PMULHRSW128,
28105 IX86_BUILTIN_PSHUFB128,
28106 IX86_BUILTIN_PSIGNB128,
28107 IX86_BUILTIN_PSIGNW128,
28108 IX86_BUILTIN_PSIGND128,
28109 IX86_BUILTIN_PALIGNR128,
28110 IX86_BUILTIN_PABSB128,
28111 IX86_BUILTIN_PABSW128,
28112 IX86_BUILTIN_PABSD128,
28114 /* AMDFAM10 - SSE4A New Instructions. */
28115 IX86_BUILTIN_MOVNTSD,
28116 IX86_BUILTIN_MOVNTSS,
28117 IX86_BUILTIN_EXTRQI,
28118 IX86_BUILTIN_EXTRQ,
28119 IX86_BUILTIN_INSERTQI,
28120 IX86_BUILTIN_INSERTQ,
28122 /* SSE4.1. */
28123 IX86_BUILTIN_BLENDPD,
28124 IX86_BUILTIN_BLENDPS,
28125 IX86_BUILTIN_BLENDVPD,
28126 IX86_BUILTIN_BLENDVPS,
28127 IX86_BUILTIN_PBLENDVB128,
28128 IX86_BUILTIN_PBLENDW128,
28130 IX86_BUILTIN_DPPD,
28131 IX86_BUILTIN_DPPS,
28133 IX86_BUILTIN_INSERTPS128,
28135 IX86_BUILTIN_MOVNTDQA,
28136 IX86_BUILTIN_MPSADBW128,
28137 IX86_BUILTIN_PACKUSDW128,
28138 IX86_BUILTIN_PCMPEQQ,
28139 IX86_BUILTIN_PHMINPOSUW128,
28141 IX86_BUILTIN_PMAXSB128,
28142 IX86_BUILTIN_PMAXSD128,
28143 IX86_BUILTIN_PMAXUD128,
28144 IX86_BUILTIN_PMAXUW128,
28146 IX86_BUILTIN_PMINSB128,
28147 IX86_BUILTIN_PMINSD128,
28148 IX86_BUILTIN_PMINUD128,
28149 IX86_BUILTIN_PMINUW128,
28151 IX86_BUILTIN_PMOVSXBW128,
28152 IX86_BUILTIN_PMOVSXBD128,
28153 IX86_BUILTIN_PMOVSXBQ128,
28154 IX86_BUILTIN_PMOVSXWD128,
28155 IX86_BUILTIN_PMOVSXWQ128,
28156 IX86_BUILTIN_PMOVSXDQ128,
28158 IX86_BUILTIN_PMOVZXBW128,
28159 IX86_BUILTIN_PMOVZXBD128,
28160 IX86_BUILTIN_PMOVZXBQ128,
28161 IX86_BUILTIN_PMOVZXWD128,
28162 IX86_BUILTIN_PMOVZXWQ128,
28163 IX86_BUILTIN_PMOVZXDQ128,
28165 IX86_BUILTIN_PMULDQ128,
28166 IX86_BUILTIN_PMULLD128,
28168 IX86_BUILTIN_ROUNDSD,
28169 IX86_BUILTIN_ROUNDSS,
28171 IX86_BUILTIN_ROUNDPD,
28172 IX86_BUILTIN_ROUNDPS,
28174 IX86_BUILTIN_FLOORPD,
28175 IX86_BUILTIN_CEILPD,
28176 IX86_BUILTIN_TRUNCPD,
28177 IX86_BUILTIN_RINTPD,
28178 IX86_BUILTIN_ROUNDPD_AZ,
28180 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28181 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28182 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28184 IX86_BUILTIN_FLOORPS,
28185 IX86_BUILTIN_CEILPS,
28186 IX86_BUILTIN_TRUNCPS,
28187 IX86_BUILTIN_RINTPS,
28188 IX86_BUILTIN_ROUNDPS_AZ,
28190 IX86_BUILTIN_FLOORPS_SFIX,
28191 IX86_BUILTIN_CEILPS_SFIX,
28192 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28194 IX86_BUILTIN_PTESTZ,
28195 IX86_BUILTIN_PTESTC,
28196 IX86_BUILTIN_PTESTNZC,
28198 IX86_BUILTIN_VEC_INIT_V2SI,
28199 IX86_BUILTIN_VEC_INIT_V4HI,
28200 IX86_BUILTIN_VEC_INIT_V8QI,
28201 IX86_BUILTIN_VEC_EXT_V2DF,
28202 IX86_BUILTIN_VEC_EXT_V2DI,
28203 IX86_BUILTIN_VEC_EXT_V4SF,
28204 IX86_BUILTIN_VEC_EXT_V4SI,
28205 IX86_BUILTIN_VEC_EXT_V8HI,
28206 IX86_BUILTIN_VEC_EXT_V2SI,
28207 IX86_BUILTIN_VEC_EXT_V4HI,
28208 IX86_BUILTIN_VEC_EXT_V16QI,
28209 IX86_BUILTIN_VEC_SET_V2DI,
28210 IX86_BUILTIN_VEC_SET_V4SF,
28211 IX86_BUILTIN_VEC_SET_V4SI,
28212 IX86_BUILTIN_VEC_SET_V8HI,
28213 IX86_BUILTIN_VEC_SET_V4HI,
28214 IX86_BUILTIN_VEC_SET_V16QI,
28216 IX86_BUILTIN_VEC_PACK_SFIX,
28217 IX86_BUILTIN_VEC_PACK_SFIX256,
28219 /* SSE4.2. */
28220 IX86_BUILTIN_CRC32QI,
28221 IX86_BUILTIN_CRC32HI,
28222 IX86_BUILTIN_CRC32SI,
28223 IX86_BUILTIN_CRC32DI,
28225 IX86_BUILTIN_PCMPESTRI128,
28226 IX86_BUILTIN_PCMPESTRM128,
28227 IX86_BUILTIN_PCMPESTRA128,
28228 IX86_BUILTIN_PCMPESTRC128,
28229 IX86_BUILTIN_PCMPESTRO128,
28230 IX86_BUILTIN_PCMPESTRS128,
28231 IX86_BUILTIN_PCMPESTRZ128,
28232 IX86_BUILTIN_PCMPISTRI128,
28233 IX86_BUILTIN_PCMPISTRM128,
28234 IX86_BUILTIN_PCMPISTRA128,
28235 IX86_BUILTIN_PCMPISTRC128,
28236 IX86_BUILTIN_PCMPISTRO128,
28237 IX86_BUILTIN_PCMPISTRS128,
28238 IX86_BUILTIN_PCMPISTRZ128,
28240 IX86_BUILTIN_PCMPGTQ,
28242 /* AES instructions */
28243 IX86_BUILTIN_AESENC128,
28244 IX86_BUILTIN_AESENCLAST128,
28245 IX86_BUILTIN_AESDEC128,
28246 IX86_BUILTIN_AESDECLAST128,
28247 IX86_BUILTIN_AESIMC128,
28248 IX86_BUILTIN_AESKEYGENASSIST128,
28250 /* PCLMUL instruction */
28251 IX86_BUILTIN_PCLMULQDQ128,
28253 /* AVX */
28254 IX86_BUILTIN_ADDPD256,
28255 IX86_BUILTIN_ADDPS256,
28256 IX86_BUILTIN_ADDSUBPD256,
28257 IX86_BUILTIN_ADDSUBPS256,
28258 IX86_BUILTIN_ANDPD256,
28259 IX86_BUILTIN_ANDPS256,
28260 IX86_BUILTIN_ANDNPD256,
28261 IX86_BUILTIN_ANDNPS256,
28262 IX86_BUILTIN_BLENDPD256,
28263 IX86_BUILTIN_BLENDPS256,
28264 IX86_BUILTIN_BLENDVPD256,
28265 IX86_BUILTIN_BLENDVPS256,
28266 IX86_BUILTIN_DIVPD256,
28267 IX86_BUILTIN_DIVPS256,
28268 IX86_BUILTIN_DPPS256,
28269 IX86_BUILTIN_HADDPD256,
28270 IX86_BUILTIN_HADDPS256,
28271 IX86_BUILTIN_HSUBPD256,
28272 IX86_BUILTIN_HSUBPS256,
28273 IX86_BUILTIN_MAXPD256,
28274 IX86_BUILTIN_MAXPS256,
28275 IX86_BUILTIN_MINPD256,
28276 IX86_BUILTIN_MINPS256,
28277 IX86_BUILTIN_MULPD256,
28278 IX86_BUILTIN_MULPS256,
28279 IX86_BUILTIN_ORPD256,
28280 IX86_BUILTIN_ORPS256,
28281 IX86_BUILTIN_SHUFPD256,
28282 IX86_BUILTIN_SHUFPS256,
28283 IX86_BUILTIN_SUBPD256,
28284 IX86_BUILTIN_SUBPS256,
28285 IX86_BUILTIN_XORPD256,
28286 IX86_BUILTIN_XORPS256,
28287 IX86_BUILTIN_CMPSD,
28288 IX86_BUILTIN_CMPSS,
28289 IX86_BUILTIN_CMPPD,
28290 IX86_BUILTIN_CMPPS,
28291 IX86_BUILTIN_CMPPD256,
28292 IX86_BUILTIN_CMPPS256,
28293 IX86_BUILTIN_CVTDQ2PD256,
28294 IX86_BUILTIN_CVTDQ2PS256,
28295 IX86_BUILTIN_CVTPD2PS256,
28296 IX86_BUILTIN_CVTPS2DQ256,
28297 IX86_BUILTIN_CVTPS2PD256,
28298 IX86_BUILTIN_CVTTPD2DQ256,
28299 IX86_BUILTIN_CVTPD2DQ256,
28300 IX86_BUILTIN_CVTTPS2DQ256,
28301 IX86_BUILTIN_EXTRACTF128PD256,
28302 IX86_BUILTIN_EXTRACTF128PS256,
28303 IX86_BUILTIN_EXTRACTF128SI256,
28304 IX86_BUILTIN_VZEROALL,
28305 IX86_BUILTIN_VZEROUPPER,
28306 IX86_BUILTIN_VPERMILVARPD,
28307 IX86_BUILTIN_VPERMILVARPS,
28308 IX86_BUILTIN_VPERMILVARPD256,
28309 IX86_BUILTIN_VPERMILVARPS256,
28310 IX86_BUILTIN_VPERMILPD,
28311 IX86_BUILTIN_VPERMILPS,
28312 IX86_BUILTIN_VPERMILPD256,
28313 IX86_BUILTIN_VPERMILPS256,
28314 IX86_BUILTIN_VPERMIL2PD,
28315 IX86_BUILTIN_VPERMIL2PS,
28316 IX86_BUILTIN_VPERMIL2PD256,
28317 IX86_BUILTIN_VPERMIL2PS256,
28318 IX86_BUILTIN_VPERM2F128PD256,
28319 IX86_BUILTIN_VPERM2F128PS256,
28320 IX86_BUILTIN_VPERM2F128SI256,
28321 IX86_BUILTIN_VBROADCASTSS,
28322 IX86_BUILTIN_VBROADCASTSD256,
28323 IX86_BUILTIN_VBROADCASTSS256,
28324 IX86_BUILTIN_VBROADCASTPD256,
28325 IX86_BUILTIN_VBROADCASTPS256,
28326 IX86_BUILTIN_VINSERTF128PD256,
28327 IX86_BUILTIN_VINSERTF128PS256,
28328 IX86_BUILTIN_VINSERTF128SI256,
28329 IX86_BUILTIN_LOADUPD256,
28330 IX86_BUILTIN_LOADUPS256,
28331 IX86_BUILTIN_STOREUPD256,
28332 IX86_BUILTIN_STOREUPS256,
28333 IX86_BUILTIN_LDDQU256,
28334 IX86_BUILTIN_MOVNTDQ256,
28335 IX86_BUILTIN_MOVNTPD256,
28336 IX86_BUILTIN_MOVNTPS256,
28337 IX86_BUILTIN_LOADDQU256,
28338 IX86_BUILTIN_STOREDQU256,
28339 IX86_BUILTIN_MASKLOADPD,
28340 IX86_BUILTIN_MASKLOADPS,
28341 IX86_BUILTIN_MASKSTOREPD,
28342 IX86_BUILTIN_MASKSTOREPS,
28343 IX86_BUILTIN_MASKLOADPD256,
28344 IX86_BUILTIN_MASKLOADPS256,
28345 IX86_BUILTIN_MASKSTOREPD256,
28346 IX86_BUILTIN_MASKSTOREPS256,
28347 IX86_BUILTIN_MOVSHDUP256,
28348 IX86_BUILTIN_MOVSLDUP256,
28349 IX86_BUILTIN_MOVDDUP256,
28351 IX86_BUILTIN_SQRTPD256,
28352 IX86_BUILTIN_SQRTPS256,
28353 IX86_BUILTIN_SQRTPS_NR256,
28354 IX86_BUILTIN_RSQRTPS256,
28355 IX86_BUILTIN_RSQRTPS_NR256,
28357 IX86_BUILTIN_RCPPS256,
28359 IX86_BUILTIN_ROUNDPD256,
28360 IX86_BUILTIN_ROUNDPS256,
28362 IX86_BUILTIN_FLOORPD256,
28363 IX86_BUILTIN_CEILPD256,
28364 IX86_BUILTIN_TRUNCPD256,
28365 IX86_BUILTIN_RINTPD256,
28366 IX86_BUILTIN_ROUNDPD_AZ256,
28368 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28369 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28370 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28372 IX86_BUILTIN_FLOORPS256,
28373 IX86_BUILTIN_CEILPS256,
28374 IX86_BUILTIN_TRUNCPS256,
28375 IX86_BUILTIN_RINTPS256,
28376 IX86_BUILTIN_ROUNDPS_AZ256,
28378 IX86_BUILTIN_FLOORPS_SFIX256,
28379 IX86_BUILTIN_CEILPS_SFIX256,
28380 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28382 IX86_BUILTIN_UNPCKHPD256,
28383 IX86_BUILTIN_UNPCKLPD256,
28384 IX86_BUILTIN_UNPCKHPS256,
28385 IX86_BUILTIN_UNPCKLPS256,
28387 IX86_BUILTIN_SI256_SI,
28388 IX86_BUILTIN_PS256_PS,
28389 IX86_BUILTIN_PD256_PD,
28390 IX86_BUILTIN_SI_SI256,
28391 IX86_BUILTIN_PS_PS256,
28392 IX86_BUILTIN_PD_PD256,
28394 IX86_BUILTIN_VTESTZPD,
28395 IX86_BUILTIN_VTESTCPD,
28396 IX86_BUILTIN_VTESTNZCPD,
28397 IX86_BUILTIN_VTESTZPS,
28398 IX86_BUILTIN_VTESTCPS,
28399 IX86_BUILTIN_VTESTNZCPS,
28400 IX86_BUILTIN_VTESTZPD256,
28401 IX86_BUILTIN_VTESTCPD256,
28402 IX86_BUILTIN_VTESTNZCPD256,
28403 IX86_BUILTIN_VTESTZPS256,
28404 IX86_BUILTIN_VTESTCPS256,
28405 IX86_BUILTIN_VTESTNZCPS256,
28406 IX86_BUILTIN_PTESTZ256,
28407 IX86_BUILTIN_PTESTC256,
28408 IX86_BUILTIN_PTESTNZC256,
28410 IX86_BUILTIN_MOVMSKPD256,
28411 IX86_BUILTIN_MOVMSKPS256,
28413 /* AVX2 */
28414 IX86_BUILTIN_MPSADBW256,
28415 IX86_BUILTIN_PABSB256,
28416 IX86_BUILTIN_PABSW256,
28417 IX86_BUILTIN_PABSD256,
28418 IX86_BUILTIN_PACKSSDW256,
28419 IX86_BUILTIN_PACKSSWB256,
28420 IX86_BUILTIN_PACKUSDW256,
28421 IX86_BUILTIN_PACKUSWB256,
28422 IX86_BUILTIN_PADDB256,
28423 IX86_BUILTIN_PADDW256,
28424 IX86_BUILTIN_PADDD256,
28425 IX86_BUILTIN_PADDQ256,
28426 IX86_BUILTIN_PADDSB256,
28427 IX86_BUILTIN_PADDSW256,
28428 IX86_BUILTIN_PADDUSB256,
28429 IX86_BUILTIN_PADDUSW256,
28430 IX86_BUILTIN_PALIGNR256,
28431 IX86_BUILTIN_AND256I,
28432 IX86_BUILTIN_ANDNOT256I,
28433 IX86_BUILTIN_PAVGB256,
28434 IX86_BUILTIN_PAVGW256,
28435 IX86_BUILTIN_PBLENDVB256,
28436 IX86_BUILTIN_PBLENDVW256,
28437 IX86_BUILTIN_PCMPEQB256,
28438 IX86_BUILTIN_PCMPEQW256,
28439 IX86_BUILTIN_PCMPEQD256,
28440 IX86_BUILTIN_PCMPEQQ256,
28441 IX86_BUILTIN_PCMPGTB256,
28442 IX86_BUILTIN_PCMPGTW256,
28443 IX86_BUILTIN_PCMPGTD256,
28444 IX86_BUILTIN_PCMPGTQ256,
28445 IX86_BUILTIN_PHADDW256,
28446 IX86_BUILTIN_PHADDD256,
28447 IX86_BUILTIN_PHADDSW256,
28448 IX86_BUILTIN_PHSUBW256,
28449 IX86_BUILTIN_PHSUBD256,
28450 IX86_BUILTIN_PHSUBSW256,
28451 IX86_BUILTIN_PMADDUBSW256,
28452 IX86_BUILTIN_PMADDWD256,
28453 IX86_BUILTIN_PMAXSB256,
28454 IX86_BUILTIN_PMAXSW256,
28455 IX86_BUILTIN_PMAXSD256,
28456 IX86_BUILTIN_PMAXUB256,
28457 IX86_BUILTIN_PMAXUW256,
28458 IX86_BUILTIN_PMAXUD256,
28459 IX86_BUILTIN_PMINSB256,
28460 IX86_BUILTIN_PMINSW256,
28461 IX86_BUILTIN_PMINSD256,
28462 IX86_BUILTIN_PMINUB256,
28463 IX86_BUILTIN_PMINUW256,
28464 IX86_BUILTIN_PMINUD256,
28465 IX86_BUILTIN_PMOVMSKB256,
28466 IX86_BUILTIN_PMOVSXBW256,
28467 IX86_BUILTIN_PMOVSXBD256,
28468 IX86_BUILTIN_PMOVSXBQ256,
28469 IX86_BUILTIN_PMOVSXWD256,
28470 IX86_BUILTIN_PMOVSXWQ256,
28471 IX86_BUILTIN_PMOVSXDQ256,
28472 IX86_BUILTIN_PMOVZXBW256,
28473 IX86_BUILTIN_PMOVZXBD256,
28474 IX86_BUILTIN_PMOVZXBQ256,
28475 IX86_BUILTIN_PMOVZXWD256,
28476 IX86_BUILTIN_PMOVZXWQ256,
28477 IX86_BUILTIN_PMOVZXDQ256,
28478 IX86_BUILTIN_PMULDQ256,
28479 IX86_BUILTIN_PMULHRSW256,
28480 IX86_BUILTIN_PMULHUW256,
28481 IX86_BUILTIN_PMULHW256,
28482 IX86_BUILTIN_PMULLW256,
28483 IX86_BUILTIN_PMULLD256,
28484 IX86_BUILTIN_PMULUDQ256,
28485 IX86_BUILTIN_POR256,
28486 IX86_BUILTIN_PSADBW256,
28487 IX86_BUILTIN_PSHUFB256,
28488 IX86_BUILTIN_PSHUFD256,
28489 IX86_BUILTIN_PSHUFHW256,
28490 IX86_BUILTIN_PSHUFLW256,
28491 IX86_BUILTIN_PSIGNB256,
28492 IX86_BUILTIN_PSIGNW256,
28493 IX86_BUILTIN_PSIGND256,
28494 IX86_BUILTIN_PSLLDQI256,
28495 IX86_BUILTIN_PSLLWI256,
28496 IX86_BUILTIN_PSLLW256,
28497 IX86_BUILTIN_PSLLDI256,
28498 IX86_BUILTIN_PSLLD256,
28499 IX86_BUILTIN_PSLLQI256,
28500 IX86_BUILTIN_PSLLQ256,
28501 IX86_BUILTIN_PSRAWI256,
28502 IX86_BUILTIN_PSRAW256,
28503 IX86_BUILTIN_PSRADI256,
28504 IX86_BUILTIN_PSRAD256,
28505 IX86_BUILTIN_PSRLDQI256,
28506 IX86_BUILTIN_PSRLWI256,
28507 IX86_BUILTIN_PSRLW256,
28508 IX86_BUILTIN_PSRLDI256,
28509 IX86_BUILTIN_PSRLD256,
28510 IX86_BUILTIN_PSRLQI256,
28511 IX86_BUILTIN_PSRLQ256,
28512 IX86_BUILTIN_PSUBB256,
28513 IX86_BUILTIN_PSUBW256,
28514 IX86_BUILTIN_PSUBD256,
28515 IX86_BUILTIN_PSUBQ256,
28516 IX86_BUILTIN_PSUBSB256,
28517 IX86_BUILTIN_PSUBSW256,
28518 IX86_BUILTIN_PSUBUSB256,
28519 IX86_BUILTIN_PSUBUSW256,
28520 IX86_BUILTIN_PUNPCKHBW256,
28521 IX86_BUILTIN_PUNPCKHWD256,
28522 IX86_BUILTIN_PUNPCKHDQ256,
28523 IX86_BUILTIN_PUNPCKHQDQ256,
28524 IX86_BUILTIN_PUNPCKLBW256,
28525 IX86_BUILTIN_PUNPCKLWD256,
28526 IX86_BUILTIN_PUNPCKLDQ256,
28527 IX86_BUILTIN_PUNPCKLQDQ256,
28528 IX86_BUILTIN_PXOR256,
28529 IX86_BUILTIN_MOVNTDQA256,
28530 IX86_BUILTIN_VBROADCASTSS_PS,
28531 IX86_BUILTIN_VBROADCASTSS_PS256,
28532 IX86_BUILTIN_VBROADCASTSD_PD256,
28533 IX86_BUILTIN_VBROADCASTSI256,
28534 IX86_BUILTIN_PBLENDD256,
28535 IX86_BUILTIN_PBLENDD128,
28536 IX86_BUILTIN_PBROADCASTB256,
28537 IX86_BUILTIN_PBROADCASTW256,
28538 IX86_BUILTIN_PBROADCASTD256,
28539 IX86_BUILTIN_PBROADCASTQ256,
28540 IX86_BUILTIN_PBROADCASTB128,
28541 IX86_BUILTIN_PBROADCASTW128,
28542 IX86_BUILTIN_PBROADCASTD128,
28543 IX86_BUILTIN_PBROADCASTQ128,
28544 IX86_BUILTIN_VPERMVARSI256,
28545 IX86_BUILTIN_VPERMDF256,
28546 IX86_BUILTIN_VPERMVARSF256,
28547 IX86_BUILTIN_VPERMDI256,
28548 IX86_BUILTIN_VPERMTI256,
28549 IX86_BUILTIN_VEXTRACT128I256,
28550 IX86_BUILTIN_VINSERT128I256,
28551 IX86_BUILTIN_MASKLOADD,
28552 IX86_BUILTIN_MASKLOADQ,
28553 IX86_BUILTIN_MASKLOADD256,
28554 IX86_BUILTIN_MASKLOADQ256,
28555 IX86_BUILTIN_MASKSTORED,
28556 IX86_BUILTIN_MASKSTOREQ,
28557 IX86_BUILTIN_MASKSTORED256,
28558 IX86_BUILTIN_MASKSTOREQ256,
28559 IX86_BUILTIN_PSLLVV4DI,
28560 IX86_BUILTIN_PSLLVV2DI,
28561 IX86_BUILTIN_PSLLVV8SI,
28562 IX86_BUILTIN_PSLLVV4SI,
28563 IX86_BUILTIN_PSRAVV8SI,
28564 IX86_BUILTIN_PSRAVV4SI,
28565 IX86_BUILTIN_PSRLVV4DI,
28566 IX86_BUILTIN_PSRLVV2DI,
28567 IX86_BUILTIN_PSRLVV8SI,
28568 IX86_BUILTIN_PSRLVV4SI,
28570 IX86_BUILTIN_GATHERSIV2DF,
28571 IX86_BUILTIN_GATHERSIV4DF,
28572 IX86_BUILTIN_GATHERDIV2DF,
28573 IX86_BUILTIN_GATHERDIV4DF,
28574 IX86_BUILTIN_GATHERSIV4SF,
28575 IX86_BUILTIN_GATHERSIV8SF,
28576 IX86_BUILTIN_GATHERDIV4SF,
28577 IX86_BUILTIN_GATHERDIV8SF,
28578 IX86_BUILTIN_GATHERSIV2DI,
28579 IX86_BUILTIN_GATHERSIV4DI,
28580 IX86_BUILTIN_GATHERDIV2DI,
28581 IX86_BUILTIN_GATHERDIV4DI,
28582 IX86_BUILTIN_GATHERSIV4SI,
28583 IX86_BUILTIN_GATHERSIV8SI,
28584 IX86_BUILTIN_GATHERDIV4SI,
28585 IX86_BUILTIN_GATHERDIV8SI,
28587 /* AVX512F */
28588 IX86_BUILTIN_SI512_SI256,
28589 IX86_BUILTIN_PD512_PD256,
28590 IX86_BUILTIN_PS512_PS256,
28591 IX86_BUILTIN_SI512_SI,
28592 IX86_BUILTIN_PD512_PD,
28593 IX86_BUILTIN_PS512_PS,
28594 IX86_BUILTIN_ADDPD512,
28595 IX86_BUILTIN_ADDPS512,
28596 IX86_BUILTIN_ADDSD_ROUND,
28597 IX86_BUILTIN_ADDSS_ROUND,
28598 IX86_BUILTIN_ALIGND512,
28599 IX86_BUILTIN_ALIGNQ512,
28600 IX86_BUILTIN_BLENDMD512,
28601 IX86_BUILTIN_BLENDMPD512,
28602 IX86_BUILTIN_BLENDMPS512,
28603 IX86_BUILTIN_BLENDMQ512,
28604 IX86_BUILTIN_BROADCASTF32X4_512,
28605 IX86_BUILTIN_BROADCASTF64X4_512,
28606 IX86_BUILTIN_BROADCASTI32X4_512,
28607 IX86_BUILTIN_BROADCASTI64X4_512,
28608 IX86_BUILTIN_BROADCASTSD512,
28609 IX86_BUILTIN_BROADCASTSS512,
28610 IX86_BUILTIN_CMPD512,
28611 IX86_BUILTIN_CMPPD512,
28612 IX86_BUILTIN_CMPPS512,
28613 IX86_BUILTIN_CMPQ512,
28614 IX86_BUILTIN_CMPSD_MASK,
28615 IX86_BUILTIN_CMPSS_MASK,
28616 IX86_BUILTIN_COMIDF,
28617 IX86_BUILTIN_COMISF,
28618 IX86_BUILTIN_COMPRESSPD512,
28619 IX86_BUILTIN_COMPRESSPDSTORE512,
28620 IX86_BUILTIN_COMPRESSPS512,
28621 IX86_BUILTIN_COMPRESSPSSTORE512,
28622 IX86_BUILTIN_CVTDQ2PD512,
28623 IX86_BUILTIN_CVTDQ2PS512,
28624 IX86_BUILTIN_CVTPD2DQ512,
28625 IX86_BUILTIN_CVTPD2PS512,
28626 IX86_BUILTIN_CVTPD2UDQ512,
28627 IX86_BUILTIN_CVTPH2PS512,
28628 IX86_BUILTIN_CVTPS2DQ512,
28629 IX86_BUILTIN_CVTPS2PD512,
28630 IX86_BUILTIN_CVTPS2PH512,
28631 IX86_BUILTIN_CVTPS2UDQ512,
28632 IX86_BUILTIN_CVTSD2SS_ROUND,
28633 IX86_BUILTIN_CVTSI2SD64,
28634 IX86_BUILTIN_CVTSI2SS32,
28635 IX86_BUILTIN_CVTSI2SS64,
28636 IX86_BUILTIN_CVTSS2SD_ROUND,
28637 IX86_BUILTIN_CVTTPD2DQ512,
28638 IX86_BUILTIN_CVTTPD2UDQ512,
28639 IX86_BUILTIN_CVTTPS2DQ512,
28640 IX86_BUILTIN_CVTTPS2UDQ512,
28641 IX86_BUILTIN_CVTUDQ2PD512,
28642 IX86_BUILTIN_CVTUDQ2PS512,
28643 IX86_BUILTIN_CVTUSI2SD32,
28644 IX86_BUILTIN_CVTUSI2SD64,
28645 IX86_BUILTIN_CVTUSI2SS32,
28646 IX86_BUILTIN_CVTUSI2SS64,
28647 IX86_BUILTIN_DIVPD512,
28648 IX86_BUILTIN_DIVPS512,
28649 IX86_BUILTIN_DIVSD_ROUND,
28650 IX86_BUILTIN_DIVSS_ROUND,
28651 IX86_BUILTIN_EXPANDPD512,
28652 IX86_BUILTIN_EXPANDPD512Z,
28653 IX86_BUILTIN_EXPANDPDLOAD512,
28654 IX86_BUILTIN_EXPANDPDLOAD512Z,
28655 IX86_BUILTIN_EXPANDPS512,
28656 IX86_BUILTIN_EXPANDPS512Z,
28657 IX86_BUILTIN_EXPANDPSLOAD512,
28658 IX86_BUILTIN_EXPANDPSLOAD512Z,
28659 IX86_BUILTIN_EXTRACTF32X4,
28660 IX86_BUILTIN_EXTRACTF64X4,
28661 IX86_BUILTIN_EXTRACTI32X4,
28662 IX86_BUILTIN_EXTRACTI64X4,
28663 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28664 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28665 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28666 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28667 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28668 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28669 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28670 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28671 IX86_BUILTIN_GETEXPPD512,
28672 IX86_BUILTIN_GETEXPPS512,
28673 IX86_BUILTIN_GETEXPSD128,
28674 IX86_BUILTIN_GETEXPSS128,
28675 IX86_BUILTIN_GETMANTPD512,
28676 IX86_BUILTIN_GETMANTPS512,
28677 IX86_BUILTIN_GETMANTSD128,
28678 IX86_BUILTIN_GETMANTSS128,
28679 IX86_BUILTIN_INSERTF32X4,
28680 IX86_BUILTIN_INSERTF64X4,
28681 IX86_BUILTIN_INSERTI32X4,
28682 IX86_BUILTIN_INSERTI64X4,
28683 IX86_BUILTIN_LOADAPD512,
28684 IX86_BUILTIN_LOADAPS512,
28685 IX86_BUILTIN_LOADDQUDI512,
28686 IX86_BUILTIN_LOADDQUSI512,
28687 IX86_BUILTIN_LOADUPD512,
28688 IX86_BUILTIN_LOADUPS512,
28689 IX86_BUILTIN_MAXPD512,
28690 IX86_BUILTIN_MAXPS512,
28691 IX86_BUILTIN_MAXSD_ROUND,
28692 IX86_BUILTIN_MAXSS_ROUND,
28693 IX86_BUILTIN_MINPD512,
28694 IX86_BUILTIN_MINPS512,
28695 IX86_BUILTIN_MINSD_ROUND,
28696 IX86_BUILTIN_MINSS_ROUND,
28697 IX86_BUILTIN_MOVAPD512,
28698 IX86_BUILTIN_MOVAPS512,
28699 IX86_BUILTIN_MOVDDUP512,
28700 IX86_BUILTIN_MOVDQA32LOAD512,
28701 IX86_BUILTIN_MOVDQA32STORE512,
28702 IX86_BUILTIN_MOVDQA32_512,
28703 IX86_BUILTIN_MOVDQA64LOAD512,
28704 IX86_BUILTIN_MOVDQA64STORE512,
28705 IX86_BUILTIN_MOVDQA64_512,
28706 IX86_BUILTIN_MOVNTDQ512,
28707 IX86_BUILTIN_MOVNTDQA512,
28708 IX86_BUILTIN_MOVNTPD512,
28709 IX86_BUILTIN_MOVNTPS512,
28710 IX86_BUILTIN_MOVSHDUP512,
28711 IX86_BUILTIN_MOVSLDUP512,
28712 IX86_BUILTIN_MULPD512,
28713 IX86_BUILTIN_MULPS512,
28714 IX86_BUILTIN_MULSD_ROUND,
28715 IX86_BUILTIN_MULSS_ROUND,
28716 IX86_BUILTIN_PABSD512,
28717 IX86_BUILTIN_PABSQ512,
28718 IX86_BUILTIN_PADDD512,
28719 IX86_BUILTIN_PADDQ512,
28720 IX86_BUILTIN_PANDD512,
28721 IX86_BUILTIN_PANDND512,
28722 IX86_BUILTIN_PANDNQ512,
28723 IX86_BUILTIN_PANDQ512,
28724 IX86_BUILTIN_PBROADCASTD512,
28725 IX86_BUILTIN_PBROADCASTD512_GPR,
28726 IX86_BUILTIN_PBROADCASTMB512,
28727 IX86_BUILTIN_PBROADCASTMW512,
28728 IX86_BUILTIN_PBROADCASTQ512,
28729 IX86_BUILTIN_PBROADCASTQ512_GPR,
28730 IX86_BUILTIN_PBROADCASTQ512_MEM,
28731 IX86_BUILTIN_PCMPEQD512_MASK,
28732 IX86_BUILTIN_PCMPEQQ512_MASK,
28733 IX86_BUILTIN_PCMPGTD512_MASK,
28734 IX86_BUILTIN_PCMPGTQ512_MASK,
28735 IX86_BUILTIN_PCOMPRESSD512,
28736 IX86_BUILTIN_PCOMPRESSDSTORE512,
28737 IX86_BUILTIN_PCOMPRESSQ512,
28738 IX86_BUILTIN_PCOMPRESSQSTORE512,
28739 IX86_BUILTIN_PEXPANDD512,
28740 IX86_BUILTIN_PEXPANDD512Z,
28741 IX86_BUILTIN_PEXPANDDLOAD512,
28742 IX86_BUILTIN_PEXPANDDLOAD512Z,
28743 IX86_BUILTIN_PEXPANDQ512,
28744 IX86_BUILTIN_PEXPANDQ512Z,
28745 IX86_BUILTIN_PEXPANDQLOAD512,
28746 IX86_BUILTIN_PEXPANDQLOAD512Z,
28747 IX86_BUILTIN_PMAXSD512,
28748 IX86_BUILTIN_PMAXSQ512,
28749 IX86_BUILTIN_PMAXUD512,
28750 IX86_BUILTIN_PMAXUQ512,
28751 IX86_BUILTIN_PMINSD512,
28752 IX86_BUILTIN_PMINSQ512,
28753 IX86_BUILTIN_PMINUD512,
28754 IX86_BUILTIN_PMINUQ512,
28755 IX86_BUILTIN_PMOVDB512,
28756 IX86_BUILTIN_PMOVDB512_MEM,
28757 IX86_BUILTIN_PMOVDW512,
28758 IX86_BUILTIN_PMOVDW512_MEM,
28759 IX86_BUILTIN_PMOVQB512,
28760 IX86_BUILTIN_PMOVQB512_MEM,
28761 IX86_BUILTIN_PMOVQD512,
28762 IX86_BUILTIN_PMOVQD512_MEM,
28763 IX86_BUILTIN_PMOVQW512,
28764 IX86_BUILTIN_PMOVQW512_MEM,
28765 IX86_BUILTIN_PMOVSDB512,
28766 IX86_BUILTIN_PMOVSDB512_MEM,
28767 IX86_BUILTIN_PMOVSDW512,
28768 IX86_BUILTIN_PMOVSDW512_MEM,
28769 IX86_BUILTIN_PMOVSQB512,
28770 IX86_BUILTIN_PMOVSQB512_MEM,
28771 IX86_BUILTIN_PMOVSQD512,
28772 IX86_BUILTIN_PMOVSQD512_MEM,
28773 IX86_BUILTIN_PMOVSQW512,
28774 IX86_BUILTIN_PMOVSQW512_MEM,
28775 IX86_BUILTIN_PMOVSXBD512,
28776 IX86_BUILTIN_PMOVSXBQ512,
28777 IX86_BUILTIN_PMOVSXDQ512,
28778 IX86_BUILTIN_PMOVSXWD512,
28779 IX86_BUILTIN_PMOVSXWQ512,
28780 IX86_BUILTIN_PMOVUSDB512,
28781 IX86_BUILTIN_PMOVUSDB512_MEM,
28782 IX86_BUILTIN_PMOVUSDW512,
28783 IX86_BUILTIN_PMOVUSDW512_MEM,
28784 IX86_BUILTIN_PMOVUSQB512,
28785 IX86_BUILTIN_PMOVUSQB512_MEM,
28786 IX86_BUILTIN_PMOVUSQD512,
28787 IX86_BUILTIN_PMOVUSQD512_MEM,
28788 IX86_BUILTIN_PMOVUSQW512,
28789 IX86_BUILTIN_PMOVUSQW512_MEM,
28790 IX86_BUILTIN_PMOVZXBD512,
28791 IX86_BUILTIN_PMOVZXBQ512,
28792 IX86_BUILTIN_PMOVZXDQ512,
28793 IX86_BUILTIN_PMOVZXWD512,
28794 IX86_BUILTIN_PMOVZXWQ512,
28795 IX86_BUILTIN_PMULDQ512,
28796 IX86_BUILTIN_PMULLD512,
28797 IX86_BUILTIN_PMULUDQ512,
28798 IX86_BUILTIN_PORD512,
28799 IX86_BUILTIN_PORQ512,
28800 IX86_BUILTIN_PROLD512,
28801 IX86_BUILTIN_PROLQ512,
28802 IX86_BUILTIN_PROLVD512,
28803 IX86_BUILTIN_PROLVQ512,
28804 IX86_BUILTIN_PRORD512,
28805 IX86_BUILTIN_PRORQ512,
28806 IX86_BUILTIN_PRORVD512,
28807 IX86_BUILTIN_PRORVQ512,
28808 IX86_BUILTIN_PSHUFD512,
28809 IX86_BUILTIN_PSLLD512,
28810 IX86_BUILTIN_PSLLDI512,
28811 IX86_BUILTIN_PSLLQ512,
28812 IX86_BUILTIN_PSLLQI512,
28813 IX86_BUILTIN_PSLLVV16SI,
28814 IX86_BUILTIN_PSLLVV8DI,
28815 IX86_BUILTIN_PSRAD512,
28816 IX86_BUILTIN_PSRADI512,
28817 IX86_BUILTIN_PSRAQ512,
28818 IX86_BUILTIN_PSRAQI512,
28819 IX86_BUILTIN_PSRAVV16SI,
28820 IX86_BUILTIN_PSRAVV8DI,
28821 IX86_BUILTIN_PSRLD512,
28822 IX86_BUILTIN_PSRLDI512,
28823 IX86_BUILTIN_PSRLQ512,
28824 IX86_BUILTIN_PSRLQI512,
28825 IX86_BUILTIN_PSRLVV16SI,
28826 IX86_BUILTIN_PSRLVV8DI,
28827 IX86_BUILTIN_PSUBD512,
28828 IX86_BUILTIN_PSUBQ512,
28829 IX86_BUILTIN_PTESTMD512,
28830 IX86_BUILTIN_PTESTMQ512,
28831 IX86_BUILTIN_PTESTNMD512,
28832 IX86_BUILTIN_PTESTNMQ512,
28833 IX86_BUILTIN_PUNPCKHDQ512,
28834 IX86_BUILTIN_PUNPCKHQDQ512,
28835 IX86_BUILTIN_PUNPCKLDQ512,
28836 IX86_BUILTIN_PUNPCKLQDQ512,
28837 IX86_BUILTIN_PXORD512,
28838 IX86_BUILTIN_PXORQ512,
28839 IX86_BUILTIN_RCP14PD512,
28840 IX86_BUILTIN_RCP14PS512,
28841 IX86_BUILTIN_RCP14SD,
28842 IX86_BUILTIN_RCP14SS,
28843 IX86_BUILTIN_RNDSCALEPD,
28844 IX86_BUILTIN_RNDSCALEPS,
28845 IX86_BUILTIN_RNDSCALESD,
28846 IX86_BUILTIN_RNDSCALESS,
28847 IX86_BUILTIN_RSQRT14PD512,
28848 IX86_BUILTIN_RSQRT14PS512,
28849 IX86_BUILTIN_RSQRT14SD,
28850 IX86_BUILTIN_RSQRT14SS,
28851 IX86_BUILTIN_SCALEFPD512,
28852 IX86_BUILTIN_SCALEFPS512,
28853 IX86_BUILTIN_SCALEFSD,
28854 IX86_BUILTIN_SCALEFSS,
28855 IX86_BUILTIN_SHUFPD512,
28856 IX86_BUILTIN_SHUFPS512,
28857 IX86_BUILTIN_SHUF_F32x4,
28858 IX86_BUILTIN_SHUF_F64x2,
28859 IX86_BUILTIN_SHUF_I32x4,
28860 IX86_BUILTIN_SHUF_I64x2,
28861 IX86_BUILTIN_SQRTPD512,
28862 IX86_BUILTIN_SQRTPD512_MASK,
28863 IX86_BUILTIN_SQRTPS512_MASK,
28864 IX86_BUILTIN_SQRTPS_NR512,
28865 IX86_BUILTIN_SQRTSD_ROUND,
28866 IX86_BUILTIN_SQRTSS_ROUND,
28867 IX86_BUILTIN_STOREAPD512,
28868 IX86_BUILTIN_STOREAPS512,
28869 IX86_BUILTIN_STOREDQUDI512,
28870 IX86_BUILTIN_STOREDQUSI512,
28871 IX86_BUILTIN_STOREUPD512,
28872 IX86_BUILTIN_STOREUPS512,
28873 IX86_BUILTIN_SUBPD512,
28874 IX86_BUILTIN_SUBPS512,
28875 IX86_BUILTIN_SUBSD_ROUND,
28876 IX86_BUILTIN_SUBSS_ROUND,
28877 IX86_BUILTIN_UCMPD512,
28878 IX86_BUILTIN_UCMPQ512,
28879 IX86_BUILTIN_UNPCKHPD512,
28880 IX86_BUILTIN_UNPCKHPS512,
28881 IX86_BUILTIN_UNPCKLPD512,
28882 IX86_BUILTIN_UNPCKLPS512,
28883 IX86_BUILTIN_VCVTSD2SI32,
28884 IX86_BUILTIN_VCVTSD2SI64,
28885 IX86_BUILTIN_VCVTSD2USI32,
28886 IX86_BUILTIN_VCVTSD2USI64,
28887 IX86_BUILTIN_VCVTSS2SI32,
28888 IX86_BUILTIN_VCVTSS2SI64,
28889 IX86_BUILTIN_VCVTSS2USI32,
28890 IX86_BUILTIN_VCVTSS2USI64,
28891 IX86_BUILTIN_VCVTTSD2SI32,
28892 IX86_BUILTIN_VCVTTSD2SI64,
28893 IX86_BUILTIN_VCVTTSD2USI32,
28894 IX86_BUILTIN_VCVTTSD2USI64,
28895 IX86_BUILTIN_VCVTTSS2SI32,
28896 IX86_BUILTIN_VCVTTSS2SI64,
28897 IX86_BUILTIN_VCVTTSS2USI32,
28898 IX86_BUILTIN_VCVTTSS2USI64,
28899 IX86_BUILTIN_VFMADDPD512_MASK,
28900 IX86_BUILTIN_VFMADDPD512_MASK3,
28901 IX86_BUILTIN_VFMADDPD512_MASKZ,
28902 IX86_BUILTIN_VFMADDPS512_MASK,
28903 IX86_BUILTIN_VFMADDPS512_MASK3,
28904 IX86_BUILTIN_VFMADDPS512_MASKZ,
28905 IX86_BUILTIN_VFMADDSD3_ROUND,
28906 IX86_BUILTIN_VFMADDSS3_ROUND,
28907 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28908 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28909 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28910 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28911 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28912 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
28913 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
28914 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
28915 IX86_BUILTIN_VFMSUBPD512_MASK3,
28916 IX86_BUILTIN_VFMSUBPS512_MASK3,
28917 IX86_BUILTIN_VFMSUBSD3_MASK3,
28918 IX86_BUILTIN_VFMSUBSS3_MASK3,
28919 IX86_BUILTIN_VFNMADDPD512_MASK,
28920 IX86_BUILTIN_VFNMADDPS512_MASK,
28921 IX86_BUILTIN_VFNMSUBPD512_MASK,
28922 IX86_BUILTIN_VFNMSUBPD512_MASK3,
28923 IX86_BUILTIN_VFNMSUBPS512_MASK,
28924 IX86_BUILTIN_VFNMSUBPS512_MASK3,
28925 IX86_BUILTIN_VPCLZCNTD512,
28926 IX86_BUILTIN_VPCLZCNTQ512,
28927 IX86_BUILTIN_VPCONFLICTD512,
28928 IX86_BUILTIN_VPCONFLICTQ512,
28929 IX86_BUILTIN_VPERMDF512,
28930 IX86_BUILTIN_VPERMDI512,
28931 IX86_BUILTIN_VPERMI2VARD512,
28932 IX86_BUILTIN_VPERMI2VARPD512,
28933 IX86_BUILTIN_VPERMI2VARPS512,
28934 IX86_BUILTIN_VPERMI2VARQ512,
28935 IX86_BUILTIN_VPERMILPD512,
28936 IX86_BUILTIN_VPERMILPS512,
28937 IX86_BUILTIN_VPERMILVARPD512,
28938 IX86_BUILTIN_VPERMILVARPS512,
28939 IX86_BUILTIN_VPERMT2VARD512,
28940 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
28941 IX86_BUILTIN_VPERMT2VARPD512,
28942 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
28943 IX86_BUILTIN_VPERMT2VARPS512,
28944 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
28945 IX86_BUILTIN_VPERMT2VARQ512,
28946 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
28947 IX86_BUILTIN_VPERMVARDF512,
28948 IX86_BUILTIN_VPERMVARDI512,
28949 IX86_BUILTIN_VPERMVARSF512,
28950 IX86_BUILTIN_VPERMVARSI512,
28951 IX86_BUILTIN_VTERNLOGD512_MASK,
28952 IX86_BUILTIN_VTERNLOGD512_MASKZ,
28953 IX86_BUILTIN_VTERNLOGQ512_MASK,
28954 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
28956 /* Mask arithmetic operations */
28957 IX86_BUILTIN_KAND16,
28958 IX86_BUILTIN_KANDN16,
28959 IX86_BUILTIN_KNOT16,
28960 IX86_BUILTIN_KOR16,
28961 IX86_BUILTIN_KORTESTC16,
28962 IX86_BUILTIN_KORTESTZ16,
28963 IX86_BUILTIN_KUNPCKBW,
28964 IX86_BUILTIN_KXNOR16,
28965 IX86_BUILTIN_KXOR16,
28966 IX86_BUILTIN_KMOV16,
28968 /* AVX512VL. */
28969 IX86_BUILTIN_PMOVUSQD256_MEM,
28970 IX86_BUILTIN_PMOVUSQD128_MEM,
28971 IX86_BUILTIN_PMOVSQD256_MEM,
28972 IX86_BUILTIN_PMOVSQD128_MEM,
28973 IX86_BUILTIN_PMOVQD256_MEM,
28974 IX86_BUILTIN_PMOVQD128_MEM,
28975 IX86_BUILTIN_PMOVUSQW256_MEM,
28976 IX86_BUILTIN_PMOVUSQW128_MEM,
28977 IX86_BUILTIN_PMOVSQW256_MEM,
28978 IX86_BUILTIN_PMOVSQW128_MEM,
28979 IX86_BUILTIN_PMOVQW256_MEM,
28980 IX86_BUILTIN_PMOVQW128_MEM,
28981 IX86_BUILTIN_PMOVUSQB256_MEM,
28982 IX86_BUILTIN_PMOVUSQB128_MEM,
28983 IX86_BUILTIN_PMOVSQB256_MEM,
28984 IX86_BUILTIN_PMOVSQB128_MEM,
28985 IX86_BUILTIN_PMOVQB256_MEM,
28986 IX86_BUILTIN_PMOVQB128_MEM,
28987 IX86_BUILTIN_PMOVUSDW256_MEM,
28988 IX86_BUILTIN_PMOVUSDW128_MEM,
28989 IX86_BUILTIN_PMOVSDW256_MEM,
28990 IX86_BUILTIN_PMOVSDW128_MEM,
28991 IX86_BUILTIN_PMOVDW256_MEM,
28992 IX86_BUILTIN_PMOVDW128_MEM,
28993 IX86_BUILTIN_PMOVUSDB256_MEM,
28994 IX86_BUILTIN_PMOVUSDB128_MEM,
28995 IX86_BUILTIN_PMOVSDB256_MEM,
28996 IX86_BUILTIN_PMOVSDB128_MEM,
28997 IX86_BUILTIN_PMOVDB256_MEM,
28998 IX86_BUILTIN_PMOVDB128_MEM,
28999 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29000 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29001 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29002 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29003 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29004 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29005 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29006 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29007 IX86_BUILTIN_LOADAPD256_MASK,
29008 IX86_BUILTIN_LOADAPD128_MASK,
29009 IX86_BUILTIN_LOADAPS256_MASK,
29010 IX86_BUILTIN_LOADAPS128_MASK,
29011 IX86_BUILTIN_STOREAPD256_MASK,
29012 IX86_BUILTIN_STOREAPD128_MASK,
29013 IX86_BUILTIN_STOREAPS256_MASK,
29014 IX86_BUILTIN_STOREAPS128_MASK,
29015 IX86_BUILTIN_LOADUPD256_MASK,
29016 IX86_BUILTIN_LOADUPD128_MASK,
29017 IX86_BUILTIN_LOADUPS256_MASK,
29018 IX86_BUILTIN_LOADUPS128_MASK,
29019 IX86_BUILTIN_STOREUPD256_MASK,
29020 IX86_BUILTIN_STOREUPD128_MASK,
29021 IX86_BUILTIN_STOREUPS256_MASK,
29022 IX86_BUILTIN_STOREUPS128_MASK,
29023 IX86_BUILTIN_LOADDQUDI256_MASK,
29024 IX86_BUILTIN_LOADDQUDI128_MASK,
29025 IX86_BUILTIN_LOADDQUSI256_MASK,
29026 IX86_BUILTIN_LOADDQUSI128_MASK,
29027 IX86_BUILTIN_LOADDQUHI256_MASK,
29028 IX86_BUILTIN_LOADDQUHI128_MASK,
29029 IX86_BUILTIN_LOADDQUQI256_MASK,
29030 IX86_BUILTIN_LOADDQUQI128_MASK,
29031 IX86_BUILTIN_STOREDQUDI256_MASK,
29032 IX86_BUILTIN_STOREDQUDI128_MASK,
29033 IX86_BUILTIN_STOREDQUSI256_MASK,
29034 IX86_BUILTIN_STOREDQUSI128_MASK,
29035 IX86_BUILTIN_STOREDQUHI256_MASK,
29036 IX86_BUILTIN_STOREDQUHI128_MASK,
29037 IX86_BUILTIN_STOREDQUQI256_MASK,
29038 IX86_BUILTIN_STOREDQUQI128_MASK,
29039 IX86_BUILTIN_COMPRESSPDSTORE256,
29040 IX86_BUILTIN_COMPRESSPDSTORE128,
29041 IX86_BUILTIN_COMPRESSPSSTORE256,
29042 IX86_BUILTIN_COMPRESSPSSTORE128,
29043 IX86_BUILTIN_PCOMPRESSQSTORE256,
29044 IX86_BUILTIN_PCOMPRESSQSTORE128,
29045 IX86_BUILTIN_PCOMPRESSDSTORE256,
29046 IX86_BUILTIN_PCOMPRESSDSTORE128,
29047 IX86_BUILTIN_EXPANDPDLOAD256,
29048 IX86_BUILTIN_EXPANDPDLOAD128,
29049 IX86_BUILTIN_EXPANDPSLOAD256,
29050 IX86_BUILTIN_EXPANDPSLOAD128,
29051 IX86_BUILTIN_PEXPANDQLOAD256,
29052 IX86_BUILTIN_PEXPANDQLOAD128,
29053 IX86_BUILTIN_PEXPANDDLOAD256,
29054 IX86_BUILTIN_PEXPANDDLOAD128,
29055 IX86_BUILTIN_EXPANDPDLOAD256Z,
29056 IX86_BUILTIN_EXPANDPDLOAD128Z,
29057 IX86_BUILTIN_EXPANDPSLOAD256Z,
29058 IX86_BUILTIN_EXPANDPSLOAD128Z,
29059 IX86_BUILTIN_PEXPANDQLOAD256Z,
29060 IX86_BUILTIN_PEXPANDQLOAD128Z,
29061 IX86_BUILTIN_PEXPANDDLOAD256Z,
29062 IX86_BUILTIN_PEXPANDDLOAD128Z,
29063 IX86_BUILTIN_PALIGNR256_MASK,
29064 IX86_BUILTIN_PALIGNR128_MASK,
29065 IX86_BUILTIN_MOVDQA64_256_MASK,
29066 IX86_BUILTIN_MOVDQA64_128_MASK,
29067 IX86_BUILTIN_MOVDQA32_256_MASK,
29068 IX86_BUILTIN_MOVDQA32_128_MASK,
29069 IX86_BUILTIN_MOVAPD256_MASK,
29070 IX86_BUILTIN_MOVAPD128_MASK,
29071 IX86_BUILTIN_MOVAPS256_MASK,
29072 IX86_BUILTIN_MOVAPS128_MASK,
29073 IX86_BUILTIN_MOVDQUHI256_MASK,
29074 IX86_BUILTIN_MOVDQUHI128_MASK,
29075 IX86_BUILTIN_MOVDQUQI256_MASK,
29076 IX86_BUILTIN_MOVDQUQI128_MASK,
29077 IX86_BUILTIN_MINPS128_MASK,
29078 IX86_BUILTIN_MAXPS128_MASK,
29079 IX86_BUILTIN_MINPD128_MASK,
29080 IX86_BUILTIN_MAXPD128_MASK,
29081 IX86_BUILTIN_MAXPD256_MASK,
29082 IX86_BUILTIN_MAXPS256_MASK,
29083 IX86_BUILTIN_MINPD256_MASK,
29084 IX86_BUILTIN_MINPS256_MASK,
29085 IX86_BUILTIN_MULPS128_MASK,
29086 IX86_BUILTIN_DIVPS128_MASK,
29087 IX86_BUILTIN_MULPD128_MASK,
29088 IX86_BUILTIN_DIVPD128_MASK,
29089 IX86_BUILTIN_DIVPD256_MASK,
29090 IX86_BUILTIN_DIVPS256_MASK,
29091 IX86_BUILTIN_MULPD256_MASK,
29092 IX86_BUILTIN_MULPS256_MASK,
29093 IX86_BUILTIN_ADDPD128_MASK,
29094 IX86_BUILTIN_ADDPD256_MASK,
29095 IX86_BUILTIN_ADDPS128_MASK,
29096 IX86_BUILTIN_ADDPS256_MASK,
29097 IX86_BUILTIN_SUBPD128_MASK,
29098 IX86_BUILTIN_SUBPD256_MASK,
29099 IX86_BUILTIN_SUBPS128_MASK,
29100 IX86_BUILTIN_SUBPS256_MASK,
29101 IX86_BUILTIN_XORPD256_MASK,
29102 IX86_BUILTIN_XORPD128_MASK,
29103 IX86_BUILTIN_XORPS256_MASK,
29104 IX86_BUILTIN_XORPS128_MASK,
29105 IX86_BUILTIN_ORPD256_MASK,
29106 IX86_BUILTIN_ORPD128_MASK,
29107 IX86_BUILTIN_ORPS256_MASK,
29108 IX86_BUILTIN_ORPS128_MASK,
29109 IX86_BUILTIN_BROADCASTF32x2_256,
29110 IX86_BUILTIN_BROADCASTI32x2_256,
29111 IX86_BUILTIN_BROADCASTI32x2_128,
29112 IX86_BUILTIN_BROADCASTF64X2_256,
29113 IX86_BUILTIN_BROADCASTI64X2_256,
29114 IX86_BUILTIN_BROADCASTF32X4_256,
29115 IX86_BUILTIN_BROADCASTI32X4_256,
29116 IX86_BUILTIN_EXTRACTF32X4_256,
29117 IX86_BUILTIN_EXTRACTI32X4_256,
29118 IX86_BUILTIN_DBPSADBW256,
29119 IX86_BUILTIN_DBPSADBW128,
29120 IX86_BUILTIN_CVTTPD2QQ256,
29121 IX86_BUILTIN_CVTTPD2QQ128,
29122 IX86_BUILTIN_CVTTPD2UQQ256,
29123 IX86_BUILTIN_CVTTPD2UQQ128,
29124 IX86_BUILTIN_CVTPD2QQ256,
29125 IX86_BUILTIN_CVTPD2QQ128,
29126 IX86_BUILTIN_CVTPD2UQQ256,
29127 IX86_BUILTIN_CVTPD2UQQ128,
29128 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29129 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29130 IX86_BUILTIN_CVTTPS2QQ256,
29131 IX86_BUILTIN_CVTTPS2QQ128,
29132 IX86_BUILTIN_CVTTPS2UQQ256,
29133 IX86_BUILTIN_CVTTPS2UQQ128,
29134 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29135 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29136 IX86_BUILTIN_CVTTPS2UDQ256,
29137 IX86_BUILTIN_CVTTPS2UDQ128,
29138 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29139 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29140 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29141 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29142 IX86_BUILTIN_CVTPD2DQ256_MASK,
29143 IX86_BUILTIN_CVTPD2DQ128_MASK,
29144 IX86_BUILTIN_CVTDQ2PD256_MASK,
29145 IX86_BUILTIN_CVTDQ2PD128_MASK,
29146 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29147 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29148 IX86_BUILTIN_CVTDQ2PS256_MASK,
29149 IX86_BUILTIN_CVTDQ2PS128_MASK,
29150 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29151 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29152 IX86_BUILTIN_CVTPS2PD256_MASK,
29153 IX86_BUILTIN_CVTPS2PD128_MASK,
29154 IX86_BUILTIN_PBROADCASTB256_MASK,
29155 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29156 IX86_BUILTIN_PBROADCASTB128_MASK,
29157 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29158 IX86_BUILTIN_PBROADCASTW256_MASK,
29159 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29160 IX86_BUILTIN_PBROADCASTW128_MASK,
29161 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29162 IX86_BUILTIN_PBROADCASTD256_MASK,
29163 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29164 IX86_BUILTIN_PBROADCASTD128_MASK,
29165 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29166 IX86_BUILTIN_PBROADCASTQ256_MASK,
29167 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29168 IX86_BUILTIN_PBROADCASTQ256_MEM_MASK,
29169 IX86_BUILTIN_PBROADCASTQ128_MASK,
29170 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29171 IX86_BUILTIN_PBROADCASTQ128_MEM_MASK,
29172 IX86_BUILTIN_BROADCASTSS256,
29173 IX86_BUILTIN_BROADCASTSS128,
29174 IX86_BUILTIN_BROADCASTSD256,
29175 IX86_BUILTIN_EXTRACTF64X2_256,
29176 IX86_BUILTIN_EXTRACTI64X2_256,
29177 IX86_BUILTIN_INSERTF32X4_256,
29178 IX86_BUILTIN_INSERTI32X4_256,
29179 IX86_BUILTIN_PMOVSXBW256_MASK,
29180 IX86_BUILTIN_PMOVSXBW128_MASK,
29181 IX86_BUILTIN_PMOVSXBD256_MASK,
29182 IX86_BUILTIN_PMOVSXBD128_MASK,
29183 IX86_BUILTIN_PMOVSXBQ256_MASK,
29184 IX86_BUILTIN_PMOVSXBQ128_MASK,
29185 IX86_BUILTIN_PMOVSXWD256_MASK,
29186 IX86_BUILTIN_PMOVSXWD128_MASK,
29187 IX86_BUILTIN_PMOVSXWQ256_MASK,
29188 IX86_BUILTIN_PMOVSXWQ128_MASK,
29189 IX86_BUILTIN_PMOVSXDQ256_MASK,
29190 IX86_BUILTIN_PMOVSXDQ128_MASK,
29191 IX86_BUILTIN_PMOVZXBW256_MASK,
29192 IX86_BUILTIN_PMOVZXBW128_MASK,
29193 IX86_BUILTIN_PMOVZXBD256_MASK,
29194 IX86_BUILTIN_PMOVZXBD128_MASK,
29195 IX86_BUILTIN_PMOVZXBQ256_MASK,
29196 IX86_BUILTIN_PMOVZXBQ128_MASK,
29197 IX86_BUILTIN_PMOVZXWD256_MASK,
29198 IX86_BUILTIN_PMOVZXWD128_MASK,
29199 IX86_BUILTIN_PMOVZXWQ256_MASK,
29200 IX86_BUILTIN_PMOVZXWQ128_MASK,
29201 IX86_BUILTIN_PMOVZXDQ256_MASK,
29202 IX86_BUILTIN_PMOVZXDQ128_MASK,
29203 IX86_BUILTIN_REDUCEPD256_MASK,
29204 IX86_BUILTIN_REDUCEPD128_MASK,
29205 IX86_BUILTIN_REDUCEPS256_MASK,
29206 IX86_BUILTIN_REDUCEPS128_MASK,
29207 IX86_BUILTIN_REDUCESD_MASK,
29208 IX86_BUILTIN_REDUCESS_MASK,
29209 IX86_BUILTIN_VPERMVARHI256_MASK,
29210 IX86_BUILTIN_VPERMVARHI128_MASK,
29211 IX86_BUILTIN_VPERMT2VARHI256,
29212 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29213 IX86_BUILTIN_VPERMT2VARHI128,
29214 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29215 IX86_BUILTIN_VPERMI2VARHI256,
29216 IX86_BUILTIN_VPERMI2VARHI128,
29217 IX86_BUILTIN_RCP14PD256,
29218 IX86_BUILTIN_RCP14PD128,
29219 IX86_BUILTIN_RCP14PS256,
29220 IX86_BUILTIN_RCP14PS128,
29221 IX86_BUILTIN_RSQRT14PD256_MASK,
29222 IX86_BUILTIN_RSQRT14PD128_MASK,
29223 IX86_BUILTIN_RSQRT14PS256_MASK,
29224 IX86_BUILTIN_RSQRT14PS128_MASK,
29225 IX86_BUILTIN_SQRTPD256_MASK,
29226 IX86_BUILTIN_SQRTPD128_MASK,
29227 IX86_BUILTIN_SQRTPS256_MASK,
29228 IX86_BUILTIN_SQRTPS128_MASK,
29229 IX86_BUILTIN_PADDB128_MASK,
29230 IX86_BUILTIN_PADDW128_MASK,
29231 IX86_BUILTIN_PADDD128_MASK,
29232 IX86_BUILTIN_PADDQ128_MASK,
29233 IX86_BUILTIN_PSUBB128_MASK,
29234 IX86_BUILTIN_PSUBW128_MASK,
29235 IX86_BUILTIN_PSUBD128_MASK,
29236 IX86_BUILTIN_PSUBQ128_MASK,
29237 IX86_BUILTIN_PADDSB128_MASK,
29238 IX86_BUILTIN_PADDSW128_MASK,
29239 IX86_BUILTIN_PSUBSB128_MASK,
29240 IX86_BUILTIN_PSUBSW128_MASK,
29241 IX86_BUILTIN_PADDUSB128_MASK,
29242 IX86_BUILTIN_PADDUSW128_MASK,
29243 IX86_BUILTIN_PSUBUSB128_MASK,
29244 IX86_BUILTIN_PSUBUSW128_MASK,
29245 IX86_BUILTIN_PADDB256_MASK,
29246 IX86_BUILTIN_PADDW256_MASK,
29247 IX86_BUILTIN_PADDD256_MASK,
29248 IX86_BUILTIN_PADDQ256_MASK,
29249 IX86_BUILTIN_PADDSB256_MASK,
29250 IX86_BUILTIN_PADDSW256_MASK,
29251 IX86_BUILTIN_PADDUSB256_MASK,
29252 IX86_BUILTIN_PADDUSW256_MASK,
29253 IX86_BUILTIN_PSUBB256_MASK,
29254 IX86_BUILTIN_PSUBW256_MASK,
29255 IX86_BUILTIN_PSUBD256_MASK,
29256 IX86_BUILTIN_PSUBQ256_MASK,
29257 IX86_BUILTIN_PSUBSB256_MASK,
29258 IX86_BUILTIN_PSUBSW256_MASK,
29259 IX86_BUILTIN_PSUBUSB256_MASK,
29260 IX86_BUILTIN_PSUBUSW256_MASK,
29261 IX86_BUILTIN_SHUF_F64x2_256,
29262 IX86_BUILTIN_SHUF_I64x2_256,
29263 IX86_BUILTIN_SHUF_I32x4_256,
29264 IX86_BUILTIN_SHUF_F32x4_256,
29265 IX86_BUILTIN_PMOVWB128,
29266 IX86_BUILTIN_PMOVWB256,
29267 IX86_BUILTIN_PMOVSWB128,
29268 IX86_BUILTIN_PMOVSWB256,
29269 IX86_BUILTIN_PMOVUSWB128,
29270 IX86_BUILTIN_PMOVUSWB256,
29271 IX86_BUILTIN_PMOVDB128,
29272 IX86_BUILTIN_PMOVDB256,
29273 IX86_BUILTIN_PMOVSDB128,
29274 IX86_BUILTIN_PMOVSDB256,
29275 IX86_BUILTIN_PMOVUSDB128,
29276 IX86_BUILTIN_PMOVUSDB256,
29277 IX86_BUILTIN_PMOVDW128,
29278 IX86_BUILTIN_PMOVDW256,
29279 IX86_BUILTIN_PMOVSDW128,
29280 IX86_BUILTIN_PMOVSDW256,
29281 IX86_BUILTIN_PMOVUSDW128,
29282 IX86_BUILTIN_PMOVUSDW256,
29283 IX86_BUILTIN_PMOVQB128,
29284 IX86_BUILTIN_PMOVQB256,
29285 IX86_BUILTIN_PMOVSQB128,
29286 IX86_BUILTIN_PMOVSQB256,
29287 IX86_BUILTIN_PMOVUSQB128,
29288 IX86_BUILTIN_PMOVUSQB256,
29289 IX86_BUILTIN_PMOVQW128,
29290 IX86_BUILTIN_PMOVQW256,
29291 IX86_BUILTIN_PMOVSQW128,
29292 IX86_BUILTIN_PMOVSQW256,
29293 IX86_BUILTIN_PMOVUSQW128,
29294 IX86_BUILTIN_PMOVUSQW256,
29295 IX86_BUILTIN_PMOVQD128,
29296 IX86_BUILTIN_PMOVQD256,
29297 IX86_BUILTIN_PMOVSQD128,
29298 IX86_BUILTIN_PMOVSQD256,
29299 IX86_BUILTIN_PMOVUSQD128,
29300 IX86_BUILTIN_PMOVUSQD256,
29301 IX86_BUILTIN_RANGEPD256,
29302 IX86_BUILTIN_RANGEPD128,
29303 IX86_BUILTIN_RANGEPS256,
29304 IX86_BUILTIN_RANGEPS128,
29305 IX86_BUILTIN_GETEXPPS256,
29306 IX86_BUILTIN_GETEXPPD256,
29307 IX86_BUILTIN_GETEXPPS128,
29308 IX86_BUILTIN_GETEXPPD128,
29309 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29310 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29311 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29312 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29313 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29314 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29315 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29316 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29317 IX86_BUILTIN_PABSQ256,
29318 IX86_BUILTIN_PABSQ128,
29319 IX86_BUILTIN_PABSD256_MASK,
29320 IX86_BUILTIN_PABSD128_MASK,
29321 IX86_BUILTIN_PMULHRSW256_MASK,
29322 IX86_BUILTIN_PMULHRSW128_MASK,
29323 IX86_BUILTIN_PMULHUW128_MASK,
29324 IX86_BUILTIN_PMULHUW256_MASK,
29325 IX86_BUILTIN_PMULHW256_MASK,
29326 IX86_BUILTIN_PMULHW128_MASK,
29327 IX86_BUILTIN_PMULLW256_MASK,
29328 IX86_BUILTIN_PMULLW128_MASK,
29329 IX86_BUILTIN_PMULLQ256,
29330 IX86_BUILTIN_PMULLQ128,
29331 IX86_BUILTIN_ANDPD256_MASK,
29332 IX86_BUILTIN_ANDPD128_MASK,
29333 IX86_BUILTIN_ANDPS256_MASK,
29334 IX86_BUILTIN_ANDPS128_MASK,
29335 IX86_BUILTIN_ANDNPD256_MASK,
29336 IX86_BUILTIN_ANDNPD128_MASK,
29337 IX86_BUILTIN_ANDNPS256_MASK,
29338 IX86_BUILTIN_ANDNPS128_MASK,
29339 IX86_BUILTIN_PSLLWI128_MASK,
29340 IX86_BUILTIN_PSLLDI128_MASK,
29341 IX86_BUILTIN_PSLLQI128_MASK,
29342 IX86_BUILTIN_PSLLW128_MASK,
29343 IX86_BUILTIN_PSLLD128_MASK,
29344 IX86_BUILTIN_PSLLQ128_MASK,
29345 IX86_BUILTIN_PSLLWI256_MASK ,
29346 IX86_BUILTIN_PSLLW256_MASK,
29347 IX86_BUILTIN_PSLLDI256_MASK,
29348 IX86_BUILTIN_PSLLD256_MASK,
29349 IX86_BUILTIN_PSLLQI256_MASK,
29350 IX86_BUILTIN_PSLLQ256_MASK,
29351 IX86_BUILTIN_PSRADI128_MASK,
29352 IX86_BUILTIN_PSRAD128_MASK,
29353 IX86_BUILTIN_PSRADI256_MASK,
29354 IX86_BUILTIN_PSRAD256_MASK,
29355 IX86_BUILTIN_PSRAQI128_MASK,
29356 IX86_BUILTIN_PSRAQ128_MASK,
29357 IX86_BUILTIN_PSRAQI256_MASK,
29358 IX86_BUILTIN_PSRAQ256_MASK,
29359 IX86_BUILTIN_PANDD256,
29360 IX86_BUILTIN_PANDD128,
29361 IX86_BUILTIN_PSRLDI128_MASK,
29362 IX86_BUILTIN_PSRLD128_MASK,
29363 IX86_BUILTIN_PSRLDI256_MASK,
29364 IX86_BUILTIN_PSRLD256_MASK,
29365 IX86_BUILTIN_PSRLQI128_MASK,
29366 IX86_BUILTIN_PSRLQ128_MASK,
29367 IX86_BUILTIN_PSRLQI256_MASK,
29368 IX86_BUILTIN_PSRLQ256_MASK,
29369 IX86_BUILTIN_PANDQ256,
29370 IX86_BUILTIN_PANDQ128,
29371 IX86_BUILTIN_PANDND256,
29372 IX86_BUILTIN_PANDND128,
29373 IX86_BUILTIN_PANDNQ256,
29374 IX86_BUILTIN_PANDNQ128,
29375 IX86_BUILTIN_PORD256,
29376 IX86_BUILTIN_PORD128,
29377 IX86_BUILTIN_PORQ256,
29378 IX86_BUILTIN_PORQ128,
29379 IX86_BUILTIN_PXORD256,
29380 IX86_BUILTIN_PXORD128,
29381 IX86_BUILTIN_PXORQ256,
29382 IX86_BUILTIN_PXORQ128,
29383 IX86_BUILTIN_PACKSSWB256_MASK,
29384 IX86_BUILTIN_PACKSSWB128_MASK,
29385 IX86_BUILTIN_PACKUSWB256_MASK,
29386 IX86_BUILTIN_PACKUSWB128_MASK,
29387 IX86_BUILTIN_RNDSCALEPS256,
29388 IX86_BUILTIN_RNDSCALEPD256,
29389 IX86_BUILTIN_RNDSCALEPS128,
29390 IX86_BUILTIN_RNDSCALEPD128,
29391 IX86_BUILTIN_VTERNLOGQ256_MASK,
29392 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29393 IX86_BUILTIN_VTERNLOGD256_MASK,
29394 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29395 IX86_BUILTIN_VTERNLOGQ128_MASK,
29396 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29397 IX86_BUILTIN_VTERNLOGD128_MASK,
29398 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29399 IX86_BUILTIN_SCALEFPD256,
29400 IX86_BUILTIN_SCALEFPS256,
29401 IX86_BUILTIN_SCALEFPD128,
29402 IX86_BUILTIN_SCALEFPS128,
29403 IX86_BUILTIN_VFMADDPD256_MASK,
29404 IX86_BUILTIN_VFMADDPD256_MASK3,
29405 IX86_BUILTIN_VFMADDPD256_MASKZ,
29406 IX86_BUILTIN_VFMADDPD128_MASK,
29407 IX86_BUILTIN_VFMADDPD128_MASK3,
29408 IX86_BUILTIN_VFMADDPD128_MASKZ,
29409 IX86_BUILTIN_VFMADDPS256_MASK,
29410 IX86_BUILTIN_VFMADDPS256_MASK3,
29411 IX86_BUILTIN_VFMADDPS256_MASKZ,
29412 IX86_BUILTIN_VFMADDPS128_MASK,
29413 IX86_BUILTIN_VFMADDPS128_MASK3,
29414 IX86_BUILTIN_VFMADDPS128_MASKZ,
29415 IX86_BUILTIN_VFMSUBPD256_MASK3,
29416 IX86_BUILTIN_VFMSUBPD128_MASK3,
29417 IX86_BUILTIN_VFMSUBPS256_MASK3,
29418 IX86_BUILTIN_VFMSUBPS128_MASK3,
29419 IX86_BUILTIN_VFNMADDPD256_MASK,
29420 IX86_BUILTIN_VFNMADDPD128_MASK,
29421 IX86_BUILTIN_VFNMADDPS256_MASK,
29422 IX86_BUILTIN_VFNMADDPS128_MASK,
29423 IX86_BUILTIN_VFNMSUBPD256_MASK,
29424 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29425 IX86_BUILTIN_VFNMSUBPD128_MASK,
29426 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29427 IX86_BUILTIN_VFNMSUBPS256_MASK,
29428 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29429 IX86_BUILTIN_VFNMSUBPS128_MASK,
29430 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29431 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29432 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29433 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29434 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29435 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29436 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29437 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29438 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29439 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29440 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29441 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29442 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29443 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29444 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29445 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29446 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29447 IX86_BUILTIN_INSERTF64X2_256,
29448 IX86_BUILTIN_INSERTI64X2_256,
29449 IX86_BUILTIN_PSRAVV16HI,
29450 IX86_BUILTIN_PSRAVV8HI,
29451 IX86_BUILTIN_PMADDUBSW256_MASK,
29452 IX86_BUILTIN_PMADDUBSW128_MASK,
29453 IX86_BUILTIN_PMADDWD256_MASK,
29454 IX86_BUILTIN_PMADDWD128_MASK,
29455 IX86_BUILTIN_PSRLVV16HI,
29456 IX86_BUILTIN_PSRLVV8HI,
29457 IX86_BUILTIN_CVTPS2DQ256_MASK,
29458 IX86_BUILTIN_CVTPS2DQ128_MASK,
29459 IX86_BUILTIN_CVTPS2UDQ256,
29460 IX86_BUILTIN_CVTPS2UDQ128,
29461 IX86_BUILTIN_CVTPS2QQ256,
29462 IX86_BUILTIN_CVTPS2QQ128,
29463 IX86_BUILTIN_CVTPS2UQQ256,
29464 IX86_BUILTIN_CVTPS2UQQ128,
29465 IX86_BUILTIN_GETMANTPS256,
29466 IX86_BUILTIN_GETMANTPS128,
29467 IX86_BUILTIN_GETMANTPD256,
29468 IX86_BUILTIN_GETMANTPD128,
29469 IX86_BUILTIN_MOVDDUP256_MASK,
29470 IX86_BUILTIN_MOVDDUP128_MASK,
29471 IX86_BUILTIN_MOVSHDUP256_MASK,
29472 IX86_BUILTIN_MOVSHDUP128_MASK,
29473 IX86_BUILTIN_MOVSLDUP256_MASK,
29474 IX86_BUILTIN_MOVSLDUP128_MASK,
29475 IX86_BUILTIN_CVTQQ2PS256,
29476 IX86_BUILTIN_CVTQQ2PS128,
29477 IX86_BUILTIN_CVTUQQ2PS256,
29478 IX86_BUILTIN_CVTUQQ2PS128,
29479 IX86_BUILTIN_CVTQQ2PD256,
29480 IX86_BUILTIN_CVTQQ2PD128,
29481 IX86_BUILTIN_CVTUQQ2PD256,
29482 IX86_BUILTIN_CVTUQQ2PD128,
29483 IX86_BUILTIN_VPERMT2VARQ256,
29484 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29485 IX86_BUILTIN_VPERMT2VARD256,
29486 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29487 IX86_BUILTIN_VPERMI2VARQ256,
29488 IX86_BUILTIN_VPERMI2VARD256,
29489 IX86_BUILTIN_VPERMT2VARPD256,
29490 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29491 IX86_BUILTIN_VPERMT2VARPS256,
29492 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29493 IX86_BUILTIN_VPERMI2VARPD256,
29494 IX86_BUILTIN_VPERMI2VARPS256,
29495 IX86_BUILTIN_VPERMT2VARQ128,
29496 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29497 IX86_BUILTIN_VPERMT2VARD128,
29498 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29499 IX86_BUILTIN_VPERMI2VARQ128,
29500 IX86_BUILTIN_VPERMI2VARD128,
29501 IX86_BUILTIN_VPERMT2VARPD128,
29502 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29503 IX86_BUILTIN_VPERMT2VARPS128,
29504 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29505 IX86_BUILTIN_VPERMI2VARPD128,
29506 IX86_BUILTIN_VPERMI2VARPS128,
29507 IX86_BUILTIN_PSHUFB256_MASK,
29508 IX86_BUILTIN_PSHUFB128_MASK,
29509 IX86_BUILTIN_PSHUFHW256_MASK,
29510 IX86_BUILTIN_PSHUFHW128_MASK,
29511 IX86_BUILTIN_PSHUFLW256_MASK,
29512 IX86_BUILTIN_PSHUFLW128_MASK,
29513 IX86_BUILTIN_PSHUFD256_MASK,
29514 IX86_BUILTIN_PSHUFD128_MASK,
29515 IX86_BUILTIN_SHUFPD256_MASK,
29516 IX86_BUILTIN_SHUFPD128_MASK,
29517 IX86_BUILTIN_SHUFPS256_MASK,
29518 IX86_BUILTIN_SHUFPS128_MASK,
29519 IX86_BUILTIN_PROLVQ256,
29520 IX86_BUILTIN_PROLVQ128,
29521 IX86_BUILTIN_PROLQ256,
29522 IX86_BUILTIN_PROLQ128,
29523 IX86_BUILTIN_PRORVQ256,
29524 IX86_BUILTIN_PRORVQ128,
29525 IX86_BUILTIN_PRORQ256,
29526 IX86_BUILTIN_PRORQ128,
29527 IX86_BUILTIN_PSRAVQ128,
29528 IX86_BUILTIN_PSRAVQ256,
29529 IX86_BUILTIN_PSLLVV4DI_MASK,
29530 IX86_BUILTIN_PSLLVV2DI_MASK,
29531 IX86_BUILTIN_PSLLVV8SI_MASK,
29532 IX86_BUILTIN_PSLLVV4SI_MASK,
29533 IX86_BUILTIN_PSRAVV8SI_MASK,
29534 IX86_BUILTIN_PSRAVV4SI_MASK,
29535 IX86_BUILTIN_PSRLVV4DI_MASK,
29536 IX86_BUILTIN_PSRLVV2DI_MASK,
29537 IX86_BUILTIN_PSRLVV8SI_MASK,
29538 IX86_BUILTIN_PSRLVV4SI_MASK,
29539 IX86_BUILTIN_PSRAWI256_MASK,
29540 IX86_BUILTIN_PSRAW256_MASK,
29541 IX86_BUILTIN_PSRAWI128_MASK,
29542 IX86_BUILTIN_PSRAW128_MASK,
29543 IX86_BUILTIN_PSRLWI256_MASK,
29544 IX86_BUILTIN_PSRLW256_MASK,
29545 IX86_BUILTIN_PSRLWI128_MASK,
29546 IX86_BUILTIN_PSRLW128_MASK,
29547 IX86_BUILTIN_PRORVD256,
29548 IX86_BUILTIN_PROLVD256,
29549 IX86_BUILTIN_PRORD256,
29550 IX86_BUILTIN_PROLD256,
29551 IX86_BUILTIN_PRORVD128,
29552 IX86_BUILTIN_PROLVD128,
29553 IX86_BUILTIN_PRORD128,
29554 IX86_BUILTIN_PROLD128,
29555 IX86_BUILTIN_FPCLASSPD256,
29556 IX86_BUILTIN_FPCLASSPD128,
29557 IX86_BUILTIN_FPCLASSSD,
29558 IX86_BUILTIN_FPCLASSPS256,
29559 IX86_BUILTIN_FPCLASSPS128,
29560 IX86_BUILTIN_FPCLASSSS,
29561 IX86_BUILTIN_CVTB2MASK128,
29562 IX86_BUILTIN_CVTB2MASK256,
29563 IX86_BUILTIN_CVTW2MASK128,
29564 IX86_BUILTIN_CVTW2MASK256,
29565 IX86_BUILTIN_CVTD2MASK128,
29566 IX86_BUILTIN_CVTD2MASK256,
29567 IX86_BUILTIN_CVTQ2MASK128,
29568 IX86_BUILTIN_CVTQ2MASK256,
29569 IX86_BUILTIN_CVTMASK2B128,
29570 IX86_BUILTIN_CVTMASK2B256,
29571 IX86_BUILTIN_CVTMASK2W128,
29572 IX86_BUILTIN_CVTMASK2W256,
29573 IX86_BUILTIN_CVTMASK2D128,
29574 IX86_BUILTIN_CVTMASK2D256,
29575 IX86_BUILTIN_CVTMASK2Q128,
29576 IX86_BUILTIN_CVTMASK2Q256,
29577 IX86_BUILTIN_PCMPEQB128_MASK,
29578 IX86_BUILTIN_PCMPEQB256_MASK,
29579 IX86_BUILTIN_PCMPEQW128_MASK,
29580 IX86_BUILTIN_PCMPEQW256_MASK,
29581 IX86_BUILTIN_PCMPEQD128_MASK,
29582 IX86_BUILTIN_PCMPEQD256_MASK,
29583 IX86_BUILTIN_PCMPEQQ128_MASK,
29584 IX86_BUILTIN_PCMPEQQ256_MASK,
29585 IX86_BUILTIN_PCMPGTB128_MASK,
29586 IX86_BUILTIN_PCMPGTB256_MASK,
29587 IX86_BUILTIN_PCMPGTW128_MASK,
29588 IX86_BUILTIN_PCMPGTW256_MASK,
29589 IX86_BUILTIN_PCMPGTD128_MASK,
29590 IX86_BUILTIN_PCMPGTD256_MASK,
29591 IX86_BUILTIN_PCMPGTQ128_MASK,
29592 IX86_BUILTIN_PCMPGTQ256_MASK,
29593 IX86_BUILTIN_PTESTMB128,
29594 IX86_BUILTIN_PTESTMB256,
29595 IX86_BUILTIN_PTESTMW128,
29596 IX86_BUILTIN_PTESTMW256,
29597 IX86_BUILTIN_PTESTMD128,
29598 IX86_BUILTIN_PTESTMD256,
29599 IX86_BUILTIN_PTESTMQ128,
29600 IX86_BUILTIN_PTESTMQ256,
29601 IX86_BUILTIN_PTESTNMB128,
29602 IX86_BUILTIN_PTESTNMB256,
29603 IX86_BUILTIN_PTESTNMW128,
29604 IX86_BUILTIN_PTESTNMW256,
29605 IX86_BUILTIN_PTESTNMD128,
29606 IX86_BUILTIN_PTESTNMD256,
29607 IX86_BUILTIN_PTESTNMQ128,
29608 IX86_BUILTIN_PTESTNMQ256,
29609 IX86_BUILTIN_PBROADCASTMB128,
29610 IX86_BUILTIN_PBROADCASTMB256,
29611 IX86_BUILTIN_PBROADCASTMW128,
29612 IX86_BUILTIN_PBROADCASTMW256,
29613 IX86_BUILTIN_COMPRESSPD256,
29614 IX86_BUILTIN_COMPRESSPD128,
29615 IX86_BUILTIN_COMPRESSPS256,
29616 IX86_BUILTIN_COMPRESSPS128,
29617 IX86_BUILTIN_PCOMPRESSQ256,
29618 IX86_BUILTIN_PCOMPRESSQ128,
29619 IX86_BUILTIN_PCOMPRESSD256,
29620 IX86_BUILTIN_PCOMPRESSD128,
29621 IX86_BUILTIN_EXPANDPD256,
29622 IX86_BUILTIN_EXPANDPD128,
29623 IX86_BUILTIN_EXPANDPS256,
29624 IX86_BUILTIN_EXPANDPS128,
29625 IX86_BUILTIN_PEXPANDQ256,
29626 IX86_BUILTIN_PEXPANDQ128,
29627 IX86_BUILTIN_PEXPANDD256,
29628 IX86_BUILTIN_PEXPANDD128,
29629 IX86_BUILTIN_EXPANDPD256Z,
29630 IX86_BUILTIN_EXPANDPD128Z,
29631 IX86_BUILTIN_EXPANDPS256Z,
29632 IX86_BUILTIN_EXPANDPS128Z,
29633 IX86_BUILTIN_PEXPANDQ256Z,
29634 IX86_BUILTIN_PEXPANDQ128Z,
29635 IX86_BUILTIN_PEXPANDD256Z,
29636 IX86_BUILTIN_PEXPANDD128Z,
29637 IX86_BUILTIN_PMAXSD256_MASK,
29638 IX86_BUILTIN_PMINSD256_MASK,
29639 IX86_BUILTIN_PMAXUD256_MASK,
29640 IX86_BUILTIN_PMINUD256_MASK,
29641 IX86_BUILTIN_PMAXSD128_MASK,
29642 IX86_BUILTIN_PMINSD128_MASK,
29643 IX86_BUILTIN_PMAXUD128_MASK,
29644 IX86_BUILTIN_PMINUD128_MASK,
29645 IX86_BUILTIN_PMAXSQ256_MASK,
29646 IX86_BUILTIN_PMINSQ256_MASK,
29647 IX86_BUILTIN_PMAXUQ256_MASK,
29648 IX86_BUILTIN_PMINUQ256_MASK,
29649 IX86_BUILTIN_PMAXSQ128_MASK,
29650 IX86_BUILTIN_PMINSQ128_MASK,
29651 IX86_BUILTIN_PMAXUQ128_MASK,
29652 IX86_BUILTIN_PMINUQ128_MASK,
29653 IX86_BUILTIN_PMINSB256_MASK,
29654 IX86_BUILTIN_PMINUB256_MASK,
29655 IX86_BUILTIN_PMAXSB256_MASK,
29656 IX86_BUILTIN_PMAXUB256_MASK,
29657 IX86_BUILTIN_PMINSB128_MASK,
29658 IX86_BUILTIN_PMINUB128_MASK,
29659 IX86_BUILTIN_PMAXSB128_MASK,
29660 IX86_BUILTIN_PMAXUB128_MASK,
29661 IX86_BUILTIN_PMINSW256_MASK,
29662 IX86_BUILTIN_PMINUW256_MASK,
29663 IX86_BUILTIN_PMAXSW256_MASK,
29664 IX86_BUILTIN_PMAXUW256_MASK,
29665 IX86_BUILTIN_PMINSW128_MASK,
29666 IX86_BUILTIN_PMINUW128_MASK,
29667 IX86_BUILTIN_PMAXSW128_MASK,
29668 IX86_BUILTIN_PMAXUW128_MASK,
29669 IX86_BUILTIN_VPCONFLICTQ256,
29670 IX86_BUILTIN_VPCONFLICTD256,
29671 IX86_BUILTIN_VPCLZCNTQ256,
29672 IX86_BUILTIN_VPCLZCNTD256,
29673 IX86_BUILTIN_UNPCKHPD256_MASK,
29674 IX86_BUILTIN_UNPCKHPD128_MASK,
29675 IX86_BUILTIN_UNPCKHPS256_MASK,
29676 IX86_BUILTIN_UNPCKHPS128_MASK,
29677 IX86_BUILTIN_UNPCKLPD256_MASK,
29678 IX86_BUILTIN_UNPCKLPD128_MASK,
29679 IX86_BUILTIN_UNPCKLPS256_MASK,
29680 IX86_BUILTIN_VPCONFLICTQ128,
29681 IX86_BUILTIN_VPCONFLICTD128,
29682 IX86_BUILTIN_VPCLZCNTQ128,
29683 IX86_BUILTIN_VPCLZCNTD128,
29684 IX86_BUILTIN_UNPCKLPS128_MASK,
29685 IX86_BUILTIN_ALIGND256,
29686 IX86_BUILTIN_ALIGNQ256,
29687 IX86_BUILTIN_ALIGND128,
29688 IX86_BUILTIN_ALIGNQ128,
29689 IX86_BUILTIN_CVTPS2PH256_MASK,
29690 IX86_BUILTIN_CVTPS2PH_MASK,
29691 IX86_BUILTIN_CVTPH2PS_MASK,
29692 IX86_BUILTIN_CVTPH2PS256_MASK,
29693 IX86_BUILTIN_PUNPCKHDQ128_MASK,
29694 IX86_BUILTIN_PUNPCKHDQ256_MASK,
29695 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
29696 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
29697 IX86_BUILTIN_PUNPCKLDQ128_MASK,
29698 IX86_BUILTIN_PUNPCKLDQ256_MASK,
29699 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
29700 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
29701 IX86_BUILTIN_PUNPCKHBW128_MASK,
29702 IX86_BUILTIN_PUNPCKHBW256_MASK,
29703 IX86_BUILTIN_PUNPCKHWD128_MASK,
29704 IX86_BUILTIN_PUNPCKHWD256_MASK,
29705 IX86_BUILTIN_PUNPCKLBW128_MASK,
29706 IX86_BUILTIN_PUNPCKLBW256_MASK,
29707 IX86_BUILTIN_PUNPCKLWD128_MASK,
29708 IX86_BUILTIN_PUNPCKLWD256_MASK,
29709 IX86_BUILTIN_PSLLVV16HI,
29710 IX86_BUILTIN_PSLLVV8HI,
29711 IX86_BUILTIN_PACKSSDW256_MASK,
29712 IX86_BUILTIN_PACKSSDW128_MASK,
29713 IX86_BUILTIN_PACKUSDW256_MASK,
29714 IX86_BUILTIN_PACKUSDW128_MASK,
29715 IX86_BUILTIN_PAVGB256_MASK,
29716 IX86_BUILTIN_PAVGW256_MASK,
29717 IX86_BUILTIN_PAVGB128_MASK,
29718 IX86_BUILTIN_PAVGW128_MASK,
29719 IX86_BUILTIN_VPERMVARSF256_MASK,
29720 IX86_BUILTIN_VPERMVARDF256_MASK,
29721 IX86_BUILTIN_VPERMDF256_MASK,
29722 IX86_BUILTIN_PABSB256_MASK,
29723 IX86_BUILTIN_PABSB128_MASK,
29724 IX86_BUILTIN_PABSW256_MASK,
29725 IX86_BUILTIN_PABSW128_MASK,
29726 IX86_BUILTIN_VPERMILVARPD_MASK,
29727 IX86_BUILTIN_VPERMILVARPS_MASK,
29728 IX86_BUILTIN_VPERMILVARPD256_MASK,
29729 IX86_BUILTIN_VPERMILVARPS256_MASK,
29730 IX86_BUILTIN_VPERMILPD_MASK,
29731 IX86_BUILTIN_VPERMILPS_MASK,
29732 IX86_BUILTIN_VPERMILPD256_MASK,
29733 IX86_BUILTIN_VPERMILPS256_MASK,
29734 IX86_BUILTIN_BLENDMQ256,
29735 IX86_BUILTIN_BLENDMD256,
29736 IX86_BUILTIN_BLENDMPD256,
29737 IX86_BUILTIN_BLENDMPS256,
29738 IX86_BUILTIN_BLENDMQ128,
29739 IX86_BUILTIN_BLENDMD128,
29740 IX86_BUILTIN_BLENDMPD128,
29741 IX86_BUILTIN_BLENDMPS128,
29742 IX86_BUILTIN_BLENDMW256,
29743 IX86_BUILTIN_BLENDMB256,
29744 IX86_BUILTIN_BLENDMW128,
29745 IX86_BUILTIN_BLENDMB128,
29746 IX86_BUILTIN_PMULLD256_MASK,
29747 IX86_BUILTIN_PMULLD128_MASK,
29748 IX86_BUILTIN_PMULUDQ256_MASK,
29749 IX86_BUILTIN_PMULDQ256_MASK,
29750 IX86_BUILTIN_PMULDQ128_MASK,
29751 IX86_BUILTIN_PMULUDQ128_MASK,
29752 IX86_BUILTIN_CVTPD2PS256_MASK,
29753 IX86_BUILTIN_CVTPD2PS_MASK,
29754 IX86_BUILTIN_VPERMVARSI256_MASK,
29755 IX86_BUILTIN_VPERMVARDI256_MASK,
29756 IX86_BUILTIN_VPERMDI256_MASK,
29757 IX86_BUILTIN_CMPQ256,
29758 IX86_BUILTIN_CMPD256,
29759 IX86_BUILTIN_UCMPQ256,
29760 IX86_BUILTIN_UCMPD256,
29761 IX86_BUILTIN_CMPB256,
29762 IX86_BUILTIN_CMPW256,
29763 IX86_BUILTIN_UCMPB256,
29764 IX86_BUILTIN_UCMPW256,
29765 IX86_BUILTIN_CMPPD256_MASK,
29766 IX86_BUILTIN_CMPPS256_MASK,
29767 IX86_BUILTIN_CMPQ128,
29768 IX86_BUILTIN_CMPD128,
29769 IX86_BUILTIN_UCMPQ128,
29770 IX86_BUILTIN_UCMPD128,
29771 IX86_BUILTIN_CMPB128,
29772 IX86_BUILTIN_CMPW128,
29773 IX86_BUILTIN_UCMPB128,
29774 IX86_BUILTIN_UCMPW128,
29775 IX86_BUILTIN_CMPPD128_MASK,
29776 IX86_BUILTIN_CMPPS128_MASK,
29778 IX86_BUILTIN_GATHER3SIV8SF,
29779 IX86_BUILTIN_GATHER3SIV4SF,
29780 IX86_BUILTIN_GATHER3SIV4DF,
29781 IX86_BUILTIN_GATHER3SIV2DF,
29782 IX86_BUILTIN_GATHER3DIV8SF,
29783 IX86_BUILTIN_GATHER3DIV4SF,
29784 IX86_BUILTIN_GATHER3DIV4DF,
29785 IX86_BUILTIN_GATHER3DIV2DF,
29786 IX86_BUILTIN_GATHER3SIV8SI,
29787 IX86_BUILTIN_GATHER3SIV4SI,
29788 IX86_BUILTIN_GATHER3SIV4DI,
29789 IX86_BUILTIN_GATHER3SIV2DI,
29790 IX86_BUILTIN_GATHER3DIV8SI,
29791 IX86_BUILTIN_GATHER3DIV4SI,
29792 IX86_BUILTIN_GATHER3DIV4DI,
29793 IX86_BUILTIN_GATHER3DIV2DI,
29794 IX86_BUILTIN_SCATTERSIV8SF,
29795 IX86_BUILTIN_SCATTERSIV4SF,
29796 IX86_BUILTIN_SCATTERSIV4DF,
29797 IX86_BUILTIN_SCATTERSIV2DF,
29798 IX86_BUILTIN_SCATTERDIV8SF,
29799 IX86_BUILTIN_SCATTERDIV4SF,
29800 IX86_BUILTIN_SCATTERDIV4DF,
29801 IX86_BUILTIN_SCATTERDIV2DF,
29802 IX86_BUILTIN_SCATTERSIV8SI,
29803 IX86_BUILTIN_SCATTERSIV4SI,
29804 IX86_BUILTIN_SCATTERSIV4DI,
29805 IX86_BUILTIN_SCATTERSIV2DI,
29806 IX86_BUILTIN_SCATTERDIV8SI,
29807 IX86_BUILTIN_SCATTERDIV4SI,
29808 IX86_BUILTIN_SCATTERDIV4DI,
29809 IX86_BUILTIN_SCATTERDIV2DI,
29811 /* AVX512DQ. */
29812 IX86_BUILTIN_RANGESD128,
29813 IX86_BUILTIN_RANGESS128,
29814 IX86_BUILTIN_KUNPCKWD,
29815 IX86_BUILTIN_KUNPCKDQ,
29816 IX86_BUILTIN_BROADCASTF32x2_512,
29817 IX86_BUILTIN_BROADCASTI32x2_512,
29818 IX86_BUILTIN_BROADCASTF64X2_512,
29819 IX86_BUILTIN_BROADCASTI64X2_512,
29820 IX86_BUILTIN_BROADCASTF32X8_512,
29821 IX86_BUILTIN_BROADCASTI32X8_512,
29822 IX86_BUILTIN_EXTRACTF64X2_512,
29823 IX86_BUILTIN_EXTRACTF32X8,
29824 IX86_BUILTIN_EXTRACTI64X2_512,
29825 IX86_BUILTIN_EXTRACTI32X8,
29826 IX86_BUILTIN_REDUCEPD512_MASK,
29827 IX86_BUILTIN_REDUCEPS512_MASK,
29828 IX86_BUILTIN_PMULLQ512,
29829 IX86_BUILTIN_XORPD512,
29830 IX86_BUILTIN_XORPS512,
29831 IX86_BUILTIN_ORPD512,
29832 IX86_BUILTIN_ORPS512,
29833 IX86_BUILTIN_ANDPD512,
29834 IX86_BUILTIN_ANDPS512,
29835 IX86_BUILTIN_ANDNPD512,
29836 IX86_BUILTIN_ANDNPS512,
29837 IX86_BUILTIN_INSERTF32X8,
29838 IX86_BUILTIN_INSERTI32X8,
29839 IX86_BUILTIN_INSERTF64X2_512,
29840 IX86_BUILTIN_INSERTI64X2_512,
29841 IX86_BUILTIN_FPCLASSPD512,
29842 IX86_BUILTIN_FPCLASSPS512,
29843 IX86_BUILTIN_CVTD2MASK512,
29844 IX86_BUILTIN_CVTQ2MASK512,
29845 IX86_BUILTIN_CVTMASK2D512,
29846 IX86_BUILTIN_CVTMASK2Q512,
29847 IX86_BUILTIN_CVTPD2QQ512,
29848 IX86_BUILTIN_CVTPS2QQ512,
29849 IX86_BUILTIN_CVTPD2UQQ512,
29850 IX86_BUILTIN_CVTPS2UQQ512,
29851 IX86_BUILTIN_CVTQQ2PS512,
29852 IX86_BUILTIN_CVTUQQ2PS512,
29853 IX86_BUILTIN_CVTQQ2PD512,
29854 IX86_BUILTIN_CVTUQQ2PD512,
29855 IX86_BUILTIN_CVTTPS2QQ512,
29856 IX86_BUILTIN_CVTTPS2UQQ512,
29857 IX86_BUILTIN_CVTTPD2QQ512,
29858 IX86_BUILTIN_CVTTPD2UQQ512,
29859 IX86_BUILTIN_RANGEPS512,
29860 IX86_BUILTIN_RANGEPD512,
29862 /* AVX512BW. */
29863 IX86_BUILTIN_PACKUSDW512,
29864 IX86_BUILTIN_PACKSSDW512,
29865 IX86_BUILTIN_LOADDQUHI512_MASK,
29866 IX86_BUILTIN_LOADDQUQI512_MASK,
29867 IX86_BUILTIN_PSLLDQ512,
29868 IX86_BUILTIN_PSRLDQ512,
29869 IX86_BUILTIN_STOREDQUHI512_MASK,
29870 IX86_BUILTIN_STOREDQUQI512_MASK,
29871 IX86_BUILTIN_PALIGNR512,
29872 IX86_BUILTIN_PALIGNR512_MASK,
29873 IX86_BUILTIN_MOVDQUHI512_MASK,
29874 IX86_BUILTIN_MOVDQUQI512_MASK,
29875 IX86_BUILTIN_PSADBW512,
29876 IX86_BUILTIN_DBPSADBW512,
29877 IX86_BUILTIN_PBROADCASTB512,
29878 IX86_BUILTIN_PBROADCASTB512_GPR,
29879 IX86_BUILTIN_PBROADCASTW512,
29880 IX86_BUILTIN_PBROADCASTW512_GPR,
29881 IX86_BUILTIN_PMOVSXBW512_MASK,
29882 IX86_BUILTIN_PMOVZXBW512_MASK,
29883 IX86_BUILTIN_VPERMVARHI512_MASK,
29884 IX86_BUILTIN_VPERMT2VARHI512,
29885 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
29886 IX86_BUILTIN_VPERMI2VARHI512,
29887 IX86_BUILTIN_PAVGB512,
29888 IX86_BUILTIN_PAVGW512,
29889 IX86_BUILTIN_PADDB512,
29890 IX86_BUILTIN_PSUBB512,
29891 IX86_BUILTIN_PSUBSB512,
29892 IX86_BUILTIN_PADDSB512,
29893 IX86_BUILTIN_PSUBUSB512,
29894 IX86_BUILTIN_PADDUSB512,
29895 IX86_BUILTIN_PSUBW512,
29896 IX86_BUILTIN_PADDW512,
29897 IX86_BUILTIN_PSUBSW512,
29898 IX86_BUILTIN_PADDSW512,
29899 IX86_BUILTIN_PSUBUSW512,
29900 IX86_BUILTIN_PADDUSW512,
29901 IX86_BUILTIN_PMAXUW512,
29902 IX86_BUILTIN_PMAXSW512,
29903 IX86_BUILTIN_PMINUW512,
29904 IX86_BUILTIN_PMINSW512,
29905 IX86_BUILTIN_PMAXUB512,
29906 IX86_BUILTIN_PMAXSB512,
29907 IX86_BUILTIN_PMINUB512,
29908 IX86_BUILTIN_PMINSB512,
29909 IX86_BUILTIN_PMOVWB512,
29910 IX86_BUILTIN_PMOVSWB512,
29911 IX86_BUILTIN_PMOVUSWB512,
29912 IX86_BUILTIN_PMULHRSW512_MASK,
29913 IX86_BUILTIN_PMULHUW512_MASK,
29914 IX86_BUILTIN_PMULHW512_MASK,
29915 IX86_BUILTIN_PMULLW512_MASK,
29916 IX86_BUILTIN_PSLLWI512_MASK,
29917 IX86_BUILTIN_PSLLW512_MASK,
29918 IX86_BUILTIN_PACKSSWB512,
29919 IX86_BUILTIN_PACKUSWB512,
29920 IX86_BUILTIN_PSRAVV32HI,
29921 IX86_BUILTIN_PMADDUBSW512_MASK,
29922 IX86_BUILTIN_PMADDWD512_MASK,
29923 IX86_BUILTIN_PSRLVV32HI,
29924 IX86_BUILTIN_PUNPCKHBW512,
29925 IX86_BUILTIN_PUNPCKHWD512,
29926 IX86_BUILTIN_PUNPCKLBW512,
29927 IX86_BUILTIN_PUNPCKLWD512,
29928 IX86_BUILTIN_PSHUFB512,
29929 IX86_BUILTIN_PSHUFHW512,
29930 IX86_BUILTIN_PSHUFLW512,
29931 IX86_BUILTIN_PSRAWI512,
29932 IX86_BUILTIN_PSRAW512,
29933 IX86_BUILTIN_PSRLWI512,
29934 IX86_BUILTIN_PSRLW512,
29935 IX86_BUILTIN_CVTB2MASK512,
29936 IX86_BUILTIN_CVTW2MASK512,
29937 IX86_BUILTIN_CVTMASK2B512,
29938 IX86_BUILTIN_CVTMASK2W512,
29939 IX86_BUILTIN_PCMPEQB512_MASK,
29940 IX86_BUILTIN_PCMPEQW512_MASK,
29941 IX86_BUILTIN_PCMPGTB512_MASK,
29942 IX86_BUILTIN_PCMPGTW512_MASK,
29943 IX86_BUILTIN_PTESTMB512,
29944 IX86_BUILTIN_PTESTMW512,
29945 IX86_BUILTIN_PTESTNMB512,
29946 IX86_BUILTIN_PTESTNMW512,
29947 IX86_BUILTIN_PSLLVV32HI,
29948 IX86_BUILTIN_PABSB512,
29949 IX86_BUILTIN_PABSW512,
29950 IX86_BUILTIN_BLENDMW512,
29951 IX86_BUILTIN_BLENDMB512,
29952 IX86_BUILTIN_CMPB512,
29953 IX86_BUILTIN_CMPW512,
29954 IX86_BUILTIN_UCMPB512,
29955 IX86_BUILTIN_UCMPW512,
29957 /* Alternate 4 and 8 element gather/scatter for the vectorizer
29958 where all operands are 32-byte or 64-byte wide respectively. */
29959 IX86_BUILTIN_GATHERALTSIV4DF,
29960 IX86_BUILTIN_GATHERALTDIV8SF,
29961 IX86_BUILTIN_GATHERALTSIV4DI,
29962 IX86_BUILTIN_GATHERALTDIV8SI,
29963 IX86_BUILTIN_GATHER3ALTDIV16SF,
29964 IX86_BUILTIN_GATHER3ALTDIV16SI,
29965 IX86_BUILTIN_GATHER3ALTSIV4DF,
29966 IX86_BUILTIN_GATHER3ALTDIV8SF,
29967 IX86_BUILTIN_GATHER3ALTSIV4DI,
29968 IX86_BUILTIN_GATHER3ALTDIV8SI,
29969 IX86_BUILTIN_GATHER3ALTSIV8DF,
29970 IX86_BUILTIN_GATHER3ALTSIV8DI,
29971 IX86_BUILTIN_GATHER3DIV16SF,
29972 IX86_BUILTIN_GATHER3DIV16SI,
29973 IX86_BUILTIN_GATHER3DIV8DF,
29974 IX86_BUILTIN_GATHER3DIV8DI,
29975 IX86_BUILTIN_GATHER3SIV16SF,
29976 IX86_BUILTIN_GATHER3SIV16SI,
29977 IX86_BUILTIN_GATHER3SIV8DF,
29978 IX86_BUILTIN_GATHER3SIV8DI,
29979 IX86_BUILTIN_SCATTERDIV16SF,
29980 IX86_BUILTIN_SCATTERDIV16SI,
29981 IX86_BUILTIN_SCATTERDIV8DF,
29982 IX86_BUILTIN_SCATTERDIV8DI,
29983 IX86_BUILTIN_SCATTERSIV16SF,
29984 IX86_BUILTIN_SCATTERSIV16SI,
29985 IX86_BUILTIN_SCATTERSIV8DF,
29986 IX86_BUILTIN_SCATTERSIV8DI,
29988 /* AVX512PF */
29989 IX86_BUILTIN_GATHERPFQPD,
29990 IX86_BUILTIN_GATHERPFDPS,
29991 IX86_BUILTIN_GATHERPFDPD,
29992 IX86_BUILTIN_GATHERPFQPS,
29993 IX86_BUILTIN_SCATTERPFDPD,
29994 IX86_BUILTIN_SCATTERPFDPS,
29995 IX86_BUILTIN_SCATTERPFQPD,
29996 IX86_BUILTIN_SCATTERPFQPS,
29998 /* AVX-512ER */
29999 IX86_BUILTIN_EXP2PD_MASK,
30000 IX86_BUILTIN_EXP2PS_MASK,
30001 IX86_BUILTIN_EXP2PS,
30002 IX86_BUILTIN_RCP28PD,
30003 IX86_BUILTIN_RCP28PS,
30004 IX86_BUILTIN_RCP28SD,
30005 IX86_BUILTIN_RCP28SS,
30006 IX86_BUILTIN_RSQRT28PD,
30007 IX86_BUILTIN_RSQRT28PS,
30008 IX86_BUILTIN_RSQRT28SD,
30009 IX86_BUILTIN_RSQRT28SS,
30011 /* SHA builtins. */
30012 IX86_BUILTIN_SHA1MSG1,
30013 IX86_BUILTIN_SHA1MSG2,
30014 IX86_BUILTIN_SHA1NEXTE,
30015 IX86_BUILTIN_SHA1RNDS4,
30016 IX86_BUILTIN_SHA256MSG1,
30017 IX86_BUILTIN_SHA256MSG2,
30018 IX86_BUILTIN_SHA256RNDS2,
30020 /* CLFLUSHOPT instructions. */
30021 IX86_BUILTIN_CLFLUSHOPT,
30023 /* TFmode support builtins. */
30024 IX86_BUILTIN_INFQ,
30025 IX86_BUILTIN_HUGE_VALQ,
30026 IX86_BUILTIN_FABSQ,
30027 IX86_BUILTIN_COPYSIGNQ,
30029 /* Vectorizer support builtins. */
30030 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30031 IX86_BUILTIN_CPYSGNPS,
30032 IX86_BUILTIN_CPYSGNPD,
30033 IX86_BUILTIN_CPYSGNPS256,
30034 IX86_BUILTIN_CPYSGNPS512,
30035 IX86_BUILTIN_CPYSGNPD256,
30036 IX86_BUILTIN_CPYSGNPD512,
30037 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30038 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30041 /* FMA4 instructions. */
30042 IX86_BUILTIN_VFMADDSS,
30043 IX86_BUILTIN_VFMADDSD,
30044 IX86_BUILTIN_VFMADDPS,
30045 IX86_BUILTIN_VFMADDPD,
30046 IX86_BUILTIN_VFMADDPS256,
30047 IX86_BUILTIN_VFMADDPD256,
30048 IX86_BUILTIN_VFMADDSUBPS,
30049 IX86_BUILTIN_VFMADDSUBPD,
30050 IX86_BUILTIN_VFMADDSUBPS256,
30051 IX86_BUILTIN_VFMADDSUBPD256,
30053 /* FMA3 instructions. */
30054 IX86_BUILTIN_VFMADDSS3,
30055 IX86_BUILTIN_VFMADDSD3,
30057 /* XOP instructions. */
30058 IX86_BUILTIN_VPCMOV,
30059 IX86_BUILTIN_VPCMOV_V2DI,
30060 IX86_BUILTIN_VPCMOV_V4SI,
30061 IX86_BUILTIN_VPCMOV_V8HI,
30062 IX86_BUILTIN_VPCMOV_V16QI,
30063 IX86_BUILTIN_VPCMOV_V4SF,
30064 IX86_BUILTIN_VPCMOV_V2DF,
30065 IX86_BUILTIN_VPCMOV256,
30066 IX86_BUILTIN_VPCMOV_V4DI256,
30067 IX86_BUILTIN_VPCMOV_V8SI256,
30068 IX86_BUILTIN_VPCMOV_V16HI256,
30069 IX86_BUILTIN_VPCMOV_V32QI256,
30070 IX86_BUILTIN_VPCMOV_V8SF256,
30071 IX86_BUILTIN_VPCMOV_V4DF256,
30073 IX86_BUILTIN_VPPERM,
30075 IX86_BUILTIN_VPMACSSWW,
30076 IX86_BUILTIN_VPMACSWW,
30077 IX86_BUILTIN_VPMACSSWD,
30078 IX86_BUILTIN_VPMACSWD,
30079 IX86_BUILTIN_VPMACSSDD,
30080 IX86_BUILTIN_VPMACSDD,
30081 IX86_BUILTIN_VPMACSSDQL,
30082 IX86_BUILTIN_VPMACSSDQH,
30083 IX86_BUILTIN_VPMACSDQL,
30084 IX86_BUILTIN_VPMACSDQH,
30085 IX86_BUILTIN_VPMADCSSWD,
30086 IX86_BUILTIN_VPMADCSWD,
30088 IX86_BUILTIN_VPHADDBW,
30089 IX86_BUILTIN_VPHADDBD,
30090 IX86_BUILTIN_VPHADDBQ,
30091 IX86_BUILTIN_VPHADDWD,
30092 IX86_BUILTIN_VPHADDWQ,
30093 IX86_BUILTIN_VPHADDDQ,
30094 IX86_BUILTIN_VPHADDUBW,
30095 IX86_BUILTIN_VPHADDUBD,
30096 IX86_BUILTIN_VPHADDUBQ,
30097 IX86_BUILTIN_VPHADDUWD,
30098 IX86_BUILTIN_VPHADDUWQ,
30099 IX86_BUILTIN_VPHADDUDQ,
30100 IX86_BUILTIN_VPHSUBBW,
30101 IX86_BUILTIN_VPHSUBWD,
30102 IX86_BUILTIN_VPHSUBDQ,
30104 IX86_BUILTIN_VPROTB,
30105 IX86_BUILTIN_VPROTW,
30106 IX86_BUILTIN_VPROTD,
30107 IX86_BUILTIN_VPROTQ,
30108 IX86_BUILTIN_VPROTB_IMM,
30109 IX86_BUILTIN_VPROTW_IMM,
30110 IX86_BUILTIN_VPROTD_IMM,
30111 IX86_BUILTIN_VPROTQ_IMM,
30113 IX86_BUILTIN_VPSHLB,
30114 IX86_BUILTIN_VPSHLW,
30115 IX86_BUILTIN_VPSHLD,
30116 IX86_BUILTIN_VPSHLQ,
30117 IX86_BUILTIN_VPSHAB,
30118 IX86_BUILTIN_VPSHAW,
30119 IX86_BUILTIN_VPSHAD,
30120 IX86_BUILTIN_VPSHAQ,
30122 IX86_BUILTIN_VFRCZSS,
30123 IX86_BUILTIN_VFRCZSD,
30124 IX86_BUILTIN_VFRCZPS,
30125 IX86_BUILTIN_VFRCZPD,
30126 IX86_BUILTIN_VFRCZPS256,
30127 IX86_BUILTIN_VFRCZPD256,
30129 IX86_BUILTIN_VPCOMEQUB,
30130 IX86_BUILTIN_VPCOMNEUB,
30131 IX86_BUILTIN_VPCOMLTUB,
30132 IX86_BUILTIN_VPCOMLEUB,
30133 IX86_BUILTIN_VPCOMGTUB,
30134 IX86_BUILTIN_VPCOMGEUB,
30135 IX86_BUILTIN_VPCOMFALSEUB,
30136 IX86_BUILTIN_VPCOMTRUEUB,
30138 IX86_BUILTIN_VPCOMEQUW,
30139 IX86_BUILTIN_VPCOMNEUW,
30140 IX86_BUILTIN_VPCOMLTUW,
30141 IX86_BUILTIN_VPCOMLEUW,
30142 IX86_BUILTIN_VPCOMGTUW,
30143 IX86_BUILTIN_VPCOMGEUW,
30144 IX86_BUILTIN_VPCOMFALSEUW,
30145 IX86_BUILTIN_VPCOMTRUEUW,
30147 IX86_BUILTIN_VPCOMEQUD,
30148 IX86_BUILTIN_VPCOMNEUD,
30149 IX86_BUILTIN_VPCOMLTUD,
30150 IX86_BUILTIN_VPCOMLEUD,
30151 IX86_BUILTIN_VPCOMGTUD,
30152 IX86_BUILTIN_VPCOMGEUD,
30153 IX86_BUILTIN_VPCOMFALSEUD,
30154 IX86_BUILTIN_VPCOMTRUEUD,
30156 IX86_BUILTIN_VPCOMEQUQ,
30157 IX86_BUILTIN_VPCOMNEUQ,
30158 IX86_BUILTIN_VPCOMLTUQ,
30159 IX86_BUILTIN_VPCOMLEUQ,
30160 IX86_BUILTIN_VPCOMGTUQ,
30161 IX86_BUILTIN_VPCOMGEUQ,
30162 IX86_BUILTIN_VPCOMFALSEUQ,
30163 IX86_BUILTIN_VPCOMTRUEUQ,
30165 IX86_BUILTIN_VPCOMEQB,
30166 IX86_BUILTIN_VPCOMNEB,
30167 IX86_BUILTIN_VPCOMLTB,
30168 IX86_BUILTIN_VPCOMLEB,
30169 IX86_BUILTIN_VPCOMGTB,
30170 IX86_BUILTIN_VPCOMGEB,
30171 IX86_BUILTIN_VPCOMFALSEB,
30172 IX86_BUILTIN_VPCOMTRUEB,
30174 IX86_BUILTIN_VPCOMEQW,
30175 IX86_BUILTIN_VPCOMNEW,
30176 IX86_BUILTIN_VPCOMLTW,
30177 IX86_BUILTIN_VPCOMLEW,
30178 IX86_BUILTIN_VPCOMGTW,
30179 IX86_BUILTIN_VPCOMGEW,
30180 IX86_BUILTIN_VPCOMFALSEW,
30181 IX86_BUILTIN_VPCOMTRUEW,
30183 IX86_BUILTIN_VPCOMEQD,
30184 IX86_BUILTIN_VPCOMNED,
30185 IX86_BUILTIN_VPCOMLTD,
30186 IX86_BUILTIN_VPCOMLED,
30187 IX86_BUILTIN_VPCOMGTD,
30188 IX86_BUILTIN_VPCOMGED,
30189 IX86_BUILTIN_VPCOMFALSED,
30190 IX86_BUILTIN_VPCOMTRUED,
30192 IX86_BUILTIN_VPCOMEQQ,
30193 IX86_BUILTIN_VPCOMNEQ,
30194 IX86_BUILTIN_VPCOMLTQ,
30195 IX86_BUILTIN_VPCOMLEQ,
30196 IX86_BUILTIN_VPCOMGTQ,
30197 IX86_BUILTIN_VPCOMGEQ,
30198 IX86_BUILTIN_VPCOMFALSEQ,
30199 IX86_BUILTIN_VPCOMTRUEQ,
30201 /* LWP instructions. */
30202 IX86_BUILTIN_LLWPCB,
30203 IX86_BUILTIN_SLWPCB,
30204 IX86_BUILTIN_LWPVAL32,
30205 IX86_BUILTIN_LWPVAL64,
30206 IX86_BUILTIN_LWPINS32,
30207 IX86_BUILTIN_LWPINS64,
30209 IX86_BUILTIN_CLZS,
30211 /* RTM */
30212 IX86_BUILTIN_XBEGIN,
30213 IX86_BUILTIN_XEND,
30214 IX86_BUILTIN_XABORT,
30215 IX86_BUILTIN_XTEST,
30217 /* MPX */
30218 IX86_BUILTIN_BNDMK,
30219 IX86_BUILTIN_BNDSTX,
30220 IX86_BUILTIN_BNDLDX,
30221 IX86_BUILTIN_BNDCL,
30222 IX86_BUILTIN_BNDCU,
30223 IX86_BUILTIN_BNDRET,
30224 IX86_BUILTIN_BNDNARROW,
30225 IX86_BUILTIN_BNDINT,
30226 IX86_BUILTIN_SIZEOF,
30227 IX86_BUILTIN_BNDLOWER,
30228 IX86_BUILTIN_BNDUPPER,
30230 /* BMI instructions. */
30231 IX86_BUILTIN_BEXTR32,
30232 IX86_BUILTIN_BEXTR64,
30233 IX86_BUILTIN_CTZS,
30235 /* TBM instructions. */
30236 IX86_BUILTIN_BEXTRI32,
30237 IX86_BUILTIN_BEXTRI64,
30239 /* BMI2 instructions. */
30240 IX86_BUILTIN_BZHI32,
30241 IX86_BUILTIN_BZHI64,
30242 IX86_BUILTIN_PDEP32,
30243 IX86_BUILTIN_PDEP64,
30244 IX86_BUILTIN_PEXT32,
30245 IX86_BUILTIN_PEXT64,
30247 /* ADX instructions. */
30248 IX86_BUILTIN_ADDCARRYX32,
30249 IX86_BUILTIN_ADDCARRYX64,
30251 /* SBB instructions. */
30252 IX86_BUILTIN_SBB32,
30253 IX86_BUILTIN_SBB64,
30255 /* FSGSBASE instructions. */
30256 IX86_BUILTIN_RDFSBASE32,
30257 IX86_BUILTIN_RDFSBASE64,
30258 IX86_BUILTIN_RDGSBASE32,
30259 IX86_BUILTIN_RDGSBASE64,
30260 IX86_BUILTIN_WRFSBASE32,
30261 IX86_BUILTIN_WRFSBASE64,
30262 IX86_BUILTIN_WRGSBASE32,
30263 IX86_BUILTIN_WRGSBASE64,
30265 /* RDRND instructions. */
30266 IX86_BUILTIN_RDRAND16_STEP,
30267 IX86_BUILTIN_RDRAND32_STEP,
30268 IX86_BUILTIN_RDRAND64_STEP,
30270 /* RDSEED instructions. */
30271 IX86_BUILTIN_RDSEED16_STEP,
30272 IX86_BUILTIN_RDSEED32_STEP,
30273 IX86_BUILTIN_RDSEED64_STEP,
30275 /* F16C instructions. */
30276 IX86_BUILTIN_CVTPH2PS,
30277 IX86_BUILTIN_CVTPH2PS256,
30278 IX86_BUILTIN_CVTPS2PH,
30279 IX86_BUILTIN_CVTPS2PH256,
30281 /* CFString built-in for darwin */
30282 IX86_BUILTIN_CFSTRING,
30284 /* Builtins to get CPU type and supported features. */
30285 IX86_BUILTIN_CPU_INIT,
30286 IX86_BUILTIN_CPU_IS,
30287 IX86_BUILTIN_CPU_SUPPORTS,
30289 /* Read/write FLAGS register built-ins. */
30290 IX86_BUILTIN_READ_FLAGS,
30291 IX86_BUILTIN_WRITE_FLAGS,
30293 IX86_BUILTIN_MAX
30294 };
30296 /* Table for the ix86 builtin decls. */
30299 /* Table of all of the builtin functions that are possible with different ISA's
30300 but are waiting to be built until a function is declared to use that
30301 ISA. */
30310 };
30315 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30316 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30317 function decl in the ix86_builtins array. Returns the function decl or
30318 NULL_TREE, if the builtin was not added.
30320 If the front end has a special hook for builtin functions, delay adding
30321 builtin functions that aren't in the current ISA until the ISA is changed
30322 with function specific optimization. Doing so, can save about 300K for the
30323 default compiler. When the builtin is expanded, check at that time whether
30324 it is valid.
30326 If the front end doesn't have a special hook, record all builtins, even if
30327 it isn't an instruction set in the current ISA in case the user uses
30328 function specific options for a different ISA, so that we don't get scope
30329 errors if a builtin is added in the middle of a function scope. */
30335 {
30339 {
30348 {
30354 }
30355 else
30356 {
30364 }
30365 }
30368 }
30370 /* Like def_builtin, but also marks the function decl "const". */
30375 {
30379 else
30383 }
30385 /* Add any new builtin functions for a given ISA that may not have been
30386 declared. This saves a bit of space compared to adding all of the
30387 declarations to the tree, even if we didn't use them. */
30389 static void
30391 {
30395 {
30398 {
30401 /* Don't define the builtin again. */
30407 NULL_TREE);
30414 NULL_TREE);
30417 }
30418 }
30419 }
30421 /* Bits for builtin_description.flag. */
30423 /* Set when we don't support the comparison natively, and should
30424 swap_comparison in order to support it. */
30425 #define BUILTIN_DESC_SWAP_OPERANDS 1
30427 struct builtin_description
30428 {
30435 };
30438 {
30439 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30440 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30441 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30442 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30443 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30444 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30445 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30446 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30447 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30448 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30449 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30450 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30451 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30452 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30453 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30454 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30455 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30456 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30457 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30458 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30459 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30460 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30461 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30462 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30463 };
30466 {
30467 /* SSE4.2 */
30468 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30469 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30470 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30471 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30472 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30473 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30474 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30475 };
30478 {
30479 /* SSE4.2 */
30480 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30481 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30482 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30483 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30484 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30485 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30486 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30487 };
30489 /* Special builtins with variable number of arguments. */
30491 {
30492 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30493 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30494 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30496 /* 80387 (for use internally for atomic compound assignment). */
30497 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30498 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30499 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30500 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30502 /* MMX */
30503 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30505 /* 3DNow! */
30506 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30508 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30509 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30510 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30511 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30512 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30513 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30514 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30515 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30516 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30518 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30519 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30520 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30521 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30522 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30523 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30524 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30525 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30527 /* SSE */
30528 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30529 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30530 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30532 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30533 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30534 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30535 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30537 /* SSE or 3DNow!A */
30538 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30539 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30541 /* SSE2 */
30542 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30543 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30544 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30545 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30546 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30547 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30548 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30549 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30550 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30551 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30553 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30554 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30556 /* SSE3 */
30557 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30559 /* SSE4.1 */
30560 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30562 /* SSE4A */
30563 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30564 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30566 /* AVX */
30567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30570 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30571 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30572 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30577 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30588 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
30589 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
30590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
30591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
30592 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
30593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
30594 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
30595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
30597 /* AVX2 */
30598 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
30599 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
30600 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
30601 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
30602 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
30603 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
30604 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
30605 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
30606 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
30608 /* AVX512F */
30609 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30610 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30611 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30612 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30613 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30614 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30615 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30616 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30617 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30618 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30619 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30620 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30621 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30622 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30623 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30624 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30625 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30626 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30627 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30628 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30629 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
30630 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
30631 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
30632 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
30633 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30634 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30635 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30636 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30637 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30638 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30639 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30640 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30641 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30642 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30643 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30644 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30645 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30646 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30647 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30648 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30649 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30650 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30651 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30652 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30653 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30654 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30655 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30657 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
30658 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
30659 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
30660 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
30661 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
30662 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
30664 /* FSGSBASE */
30665 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30666 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30667 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30668 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30669 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30670 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30671 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30672 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30674 /* RTM */
30675 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30676 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
30677 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
30679 /* AVX512BW */
30680 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
30681 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
30682 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
30683 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
30685 /* AVX512VL */
30686 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
30687 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
30688 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
30689 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
30690 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30691 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30692 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30693 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30694 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30695 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30696 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30697 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30698 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30699 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30700 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30701 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30702 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30703 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30704 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30705 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30706 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30707 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30708 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30709 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30710 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30711 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30712 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30713 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30714 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30715 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30716 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30717 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30718 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30719 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30720 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30721 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30722 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
30723 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
30724 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
30725 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
30726 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30727 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30728 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30729 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30730 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30731 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30732 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30733 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30734 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30735 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30736 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30737 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30738 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30739 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30740 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30741 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30742 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30743 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30744 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30745 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30746 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30747 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30748 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30749 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30750 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30751 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30752 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30753 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30754 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30755 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30756 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30757 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30758 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30759 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30760 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30761 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30762 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30763 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30764 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30765 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30766 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30767 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30768 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30769 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30770 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30771 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30772 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30773 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30774 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30775 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30776 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30777 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30778 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30779 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30780 };
30782 /* Builtins with variable number of arguments. */
30784 {
30785 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
30786 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
30787 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
30788 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30789 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30790 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30791 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30793 /* MMX */
30794 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30795 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30796 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30797 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30798 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30799 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30801 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30802 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30803 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30804 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30805 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30806 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30807 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30808 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30810 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30811 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30813 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30814 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30815 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30816 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30818 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30819 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30820 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30821 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30822 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30823 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30825 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30826 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30827 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30828 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30829 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
30830 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
30832 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
30833 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
30834 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
30836 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
30838 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
30839 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
30840 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
30841 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
30842 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
30843 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
30845 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
30846 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
30847 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
30848 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
30849 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
30850 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
30852 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
30853 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
30854 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
30855 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
30857 /* 3DNow! */
30858 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
30859 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
30860 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
30861 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
30863 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30864 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30865 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30866 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
30867 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
30868 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
30869 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30870 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30871 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30872 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30873 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30874 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30875 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30876 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30877 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30879 /* 3DNow!A */
30880 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
30881 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
30882 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
30883 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
30884 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30885 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30887 /* SSE */
30888 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
30889 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30890 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30891 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30892 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30893 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30894 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
30895 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
30896 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
30897 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
30898 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
30899 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
30901 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30903 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30904 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30905 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30906 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30907 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30908 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30909 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30910 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30912 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
30913 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
30914 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
30915 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
30916 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
30917 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
30918 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
30919 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
30920 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
30921 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
30922 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
30923 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
30924 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
30925 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
30926 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
30927 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
30928 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
30929 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
30930 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
30931 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
30933 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30934 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30935 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30936 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30938 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30939 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30940 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30941 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30943 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30945 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30946 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30947 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30948 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30949 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30951 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
30952 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
30953 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
30955 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
30957 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
30958 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
30959 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
30961 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
30962 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
30964 /* SSE MMX or 3Dnow!A */
30965 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30966 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30967 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30969 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30970 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30971 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30972 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30974 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
30975 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
30977 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
30979 /* SSE2 */
30980 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30982 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
30983 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
30984 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
30985 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
30986 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
30988 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
30989 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
30990 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
30991 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
30992 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
30994 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
30996 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
30997 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
30998 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
30999 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31001 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31002 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31003 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31005 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31006 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31007 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31008 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31009 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31010 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31011 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31012 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31014 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31015 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31016 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31017 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31018 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31019 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31020 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31021 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31022 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31023 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31024 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31025 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31026 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31027 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31028 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31029 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31030 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31031 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31032 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31033 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31035 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31036 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31037 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31040 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31041 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31042 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31043 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31045 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31047 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31048 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31049 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31051 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31053 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31054 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31055 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31056 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31057 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31058 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31059 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31060 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31062 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31063 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31064 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31065 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31066 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31067 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31068 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31069 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31071 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31072 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31074 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31075 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31076 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31077 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31079 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31080 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31082 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31083 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31084 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31085 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31086 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31087 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31089 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31090 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31091 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31092 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31094 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31095 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31096 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31097 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31098 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31099 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31100 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31101 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31103 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31104 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31105 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31107 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31108 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31110 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31111 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31113 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31115 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31116 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31117 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31118 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31120 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31121 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31122 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31123 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31124 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31125 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31126 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31128 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31129 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31130 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31131 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31132 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31133 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31134 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31136 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31137 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31138 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31139 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31141 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31142 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31143 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31145 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31147 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31149 /* SSE2 MMX */
31150 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31151 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31153 /* SSE3 */
31154 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31155 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31157 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31158 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31159 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31160 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31161 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31162 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31164 /* SSSE3 */
31165 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31166 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31167 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31168 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31169 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31170 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31172 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31173 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31174 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31175 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31176 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31177 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31178 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31179 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31180 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31181 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31182 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31183 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31184 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31185 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31186 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31187 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31188 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31189 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31190 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31191 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31192 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31193 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31194 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31195 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31197 /* SSSE3. */
31198 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31199 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31201 /* SSE4.1 */
31202 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31203 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31204 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31205 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31206 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31207 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31208 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31209 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31210 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31211 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31213 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31214 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31215 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31216 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31217 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31218 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31219 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31220 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31221 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31222 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31223 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31224 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31225 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31227 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31228 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31229 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31230 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31231 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31232 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31233 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31234 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31235 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31236 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31237 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31238 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31240 /* SSE4.1 */
31241 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31242 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31243 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31244 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31246 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31247 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31248 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31249 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31251 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31252 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31254 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31255 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31257 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31258 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31259 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31260 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31262 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31263 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31265 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31266 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31268 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31269 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31270 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31272 /* SSE4.2 */
31273 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31274 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31275 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31276 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31277 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31279 /* SSE4A */
31280 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31281 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31282 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31283 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31285 /* AES */
31286 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31287 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31289 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31290 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31291 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31292 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31294 /* PCLMUL */
31295 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31297 /* AVX */
31298 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31299 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31300 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31301 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31302 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31303 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31304 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31305 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31306 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31307 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31308 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31309 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31310 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31311 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31312 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31313 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31314 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31315 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31316 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31317 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31318 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31319 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31320 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31321 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31322 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31323 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31325 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31326 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31327 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31328 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31330 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31331 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31332 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31333 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31334 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31335 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31336 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31337 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31338 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31339 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31340 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31341 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31342 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31343 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31344 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31345 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31346 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31347 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31348 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31349 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31350 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31351 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31352 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31353 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31354 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31355 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31356 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31357 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31358 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31359 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31360 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31361 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31362 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31363 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31365 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31366 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31367 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31369 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31370 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31371 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31372 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31373 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31375 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31377 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31378 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31380 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31381 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31382 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31383 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31385 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31386 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31388 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31389 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31391 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31392 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31393 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31394 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31396 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31397 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31399 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31400 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31402 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31403 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31404 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31405 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31407 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31408 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31409 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31410 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31411 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31412 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31414 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31415 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31416 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31417 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31418 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31419 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31420 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31421 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31422 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31423 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31424 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31425 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31426 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31427 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31428 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31430 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31431 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31433 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31434 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31436 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31438 /* AVX2 */
31439 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31440 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31441 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31442 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31443 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31444 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31445 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31446 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31447 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31448 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31449 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31450 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31451 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31452 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31453 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31454 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31455 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31456 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31457 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31458 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31459 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31460 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31461 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31462 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31463 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31464 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31465 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31466 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31467 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31468 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31469 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31470 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31471 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31472 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31473 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31474 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31475 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31476 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31477 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31478 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31479 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31480 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31481 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31482 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31483 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31484 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31485 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31486 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31487 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31488 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31489 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31490 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31491 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31492 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31493 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31494 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31495 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31496 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31497 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31498 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31499 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31500 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31501 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31502 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31503 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31504 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31505 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31506 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31507 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31508 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31509 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31510 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31511 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31512 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31513 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31514 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31515 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31516 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31517 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31518 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31519 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31520 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31521 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31522 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31523 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31524 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31525 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31526 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31527 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31528 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31529 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31530 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31531 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31532 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31533 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31534 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31535 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31536 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31537 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31538 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31539 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31540 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31541 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31542 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31543 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31544 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31545 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31546 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31547 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31548 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31549 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31550 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31551 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31552 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31553 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31554 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31555 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31556 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31557 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31558 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31559 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31560 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31561 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31562 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31563 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31564 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31565 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31566 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31567 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31568 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31569 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31570 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31571 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31572 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31573 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31574 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31575 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31576 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31577 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31578 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31579 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31580 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31581 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31582 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31583 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31584 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31586 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31588 /* BMI */
31589 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31590 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31591 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31593 /* TBM */
31594 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31595 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31597 /* F16C */
31598 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
31599 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
31600 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
31601 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
31603 /* BMI2 */
31604 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31605 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31606 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31607 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31608 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31609 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31611 /* AVX512F */
31612 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
31613 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
31614 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
31615 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
31616 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
31617 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
31618 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31619 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31620 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31621 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31622 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31623 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31624 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31625 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
31626 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31627 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
31628 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
31629 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31630 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31631 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31632 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31633 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31634 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31635 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
31636 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31637 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
31638 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31639 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31640 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31641 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31642 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
31643 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
31644 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
31645 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
31646 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
31647 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
31648 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
31649 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
31650 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31651 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31652 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31653 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31654 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31655 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31656 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31657 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31658 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31659 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31660 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31661 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31662 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31663 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31664 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31665 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31666 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
31667 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
31668 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
31669 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
31670 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31671 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31672 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31673 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31674 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31675 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31676 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31677 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31678 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31679 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31680 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31681 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31682 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31683 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31684 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31685 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31686 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31687 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31688 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31689 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31690 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31691 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31692 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31693 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31694 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31695 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31696 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31697 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31698 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31699 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31700 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31701 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31702 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31703 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31704 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31705 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31706 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31707 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31708 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31709 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31710 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31711 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31712 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31713 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31714 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31715 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31716 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31717 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31718 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31719 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31720 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31721 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31722 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31723 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31724 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31725 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31726 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31727 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31728 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31729 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31730 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31731 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31732 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31733 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31734 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31735 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31736 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31737 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31738 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31739 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31740 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31741 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31742 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31743 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31744 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31745 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31746 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31747 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31748 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31749 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31750 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31751 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31752 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31753 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31754 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31755 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31756 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31757 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31758 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31759 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31760 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31761 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31762 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31763 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31764 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31765 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31766 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31767 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31768 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31769 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31770 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31771 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31772 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31773 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31774 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31775 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31776 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31777 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31778 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31779 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31780 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31781 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31782 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31783 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31784 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31785 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31786 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31787 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31788 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31789 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31790 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
31791 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31792 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31793 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31794 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31795 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31796 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31797 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
31798 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
31799 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31800 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31801 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31802 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31803 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31804 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31805 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
31806 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
31807 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
31808 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
31810 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
31811 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
31812 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
31813 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
31814 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
31815 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
31816 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
31817 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
31819 /* Mask arithmetic operations */
31820 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31821 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31822 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
31823 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31824 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31825 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31826 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
31827 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31828 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31829 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
31831 /* SHA */
31832 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31833 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31834 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31835 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31836 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31837 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31838 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
31840 /* AVX512VL. */
31841 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
31842 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
31843 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
31844 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
31845 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
31846 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
31847 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
31848 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
31849 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
31850 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
31851 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
31852 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
31853 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
31854 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
31855 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31856 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31857 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31858 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31859 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31860 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31861 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31862 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31863 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31864 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31865 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31866 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31867 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31868 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31869 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31870 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31871 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31872 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31873 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31874 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31875 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31876 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31877 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31878 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31879 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31880 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31881 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31882 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31883 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31884 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31885 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31886 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31887 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
31888 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
31889 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
31890 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
31891 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
31892 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
31893 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
31894 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
31895 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
31896 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
31897 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
31898 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
31899 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
31900 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
31901 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
31902 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
31903 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
31904 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
31905 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
31906 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
31907 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
31908 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
31909 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
31910 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
31911 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
31912 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
31913 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
31914 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
31915 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
31916 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
31917 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
31918 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
31919 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
31920 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
31921 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
31922 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
31923 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
31924 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
31925 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
31926 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
31927 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
31928 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
31929 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
31930 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
31931 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
31932 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
31933 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
31934 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
31935 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
31936 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
31937 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
31938 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
31939 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
31940 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
31941 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
31942 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
31943 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
31944 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
31945 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
31946 { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv4di_mask, "__builtin_ia32_pbroadcastq256_mem_mask", IX86_BUILTIN_PBROADCASTQ256_MEM_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
31947 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
31948 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
31949 { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv2di_mask, "__builtin_ia32_pbroadcastq128_mem_mask", IX86_BUILTIN_PBROADCASTQ128_MEM_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
31950 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
31951 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
31952 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
31953 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
31954 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
31955 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
31956 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
31957 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
31958 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
31959 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
31960 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
31961 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
31962 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
31963 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
31964 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
31965 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
31966 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
31967 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
31968 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
31969 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
31970 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
31971 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
31972 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
31973 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
31974 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
31975 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
31976 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
31977 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
31978 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
31979 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
31980 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
31981 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
31982 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
31983 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
31984 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
31985 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31986 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31987 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31988 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31989 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31990 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31991 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31992 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31993 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31994 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31995 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
31996 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
31997 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
31998 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
31999 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32000 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32001 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32002 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32003 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32004 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32005 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32006 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32007 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32008 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32009 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32010 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32011 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32012 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32013 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32014 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32015 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32016 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32017 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32018 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32019 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32020 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32021 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32022 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32023 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32024 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32025 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32026 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32027 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32028 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32029 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32030 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32031 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32032 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32033 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32034 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32035 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32036 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32037 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32038 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32039 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32040 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32041 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32042 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32043 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32044 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32045 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32046 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32047 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32048 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32049 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32050 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32051 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32052 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32053 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32054 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32055 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32056 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32057 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32058 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32059 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32060 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32061 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32062 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32063 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32064 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32065 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32066 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32067 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32068 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32069 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32070 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32071 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32072 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32073 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32074 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32075 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32076 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32077 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32078 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32079 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32080 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32081 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32082 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32083 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32084 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32085 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32086 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32087 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32088 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32089 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32090 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32091 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32092 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32093 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32094 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32095 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32096 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32097 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32098 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32099 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32100 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32101 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32102 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32103 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32104 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32105 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32106 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32107 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32108 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32109 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32110 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32111 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32112 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32113 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32114 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32115 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32116 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32117 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32118 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32119 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32120 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32121 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32122 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32123 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32124 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32125 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32126 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32127 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32128 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32129 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32130 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32131 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32132 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32133 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32134 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32135 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32136 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32137 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32138 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32139 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32140 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32141 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32142 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32143 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32144 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32145 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32146 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32147 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32148 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32149 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32150 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32151 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32152 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32153 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32154 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32155 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32156 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32157 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32158 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32159 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32160 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32161 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32162 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32163 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32164 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32165 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32166 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32167 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32168 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32169 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32170 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32171 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32172 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32173 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32174 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32175 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32177 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32178 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32179 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32180 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32181 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32182 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32183 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32184 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32185 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32186 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32189 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32190 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32191 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32192 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32193 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32194 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32195 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32196 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32197 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32198 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32199 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32200 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32201 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32202 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32203 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32204 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32205 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32206 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32207 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32208 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32209 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32210 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32211 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32212 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32213 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32214 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32215 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32216 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32217 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32218 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32219 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32220 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32221 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32222 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32223 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32224 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32225 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32226 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32227 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32228 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32229 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32230 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32231 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32232 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32233 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32234 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32235 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32236 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32237 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32238 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32239 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32240 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32241 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32242 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32243 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32244 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32245 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32246 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32247 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32248 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32249 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32250 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32251 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32252 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32253 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32254 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32255 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32256 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32257 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32258 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32259 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32260 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32261 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32262 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32263 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32264 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32265 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32266 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32267 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32268 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32269 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32270 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32271 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32272 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32273 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32274 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32275 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32276 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32277 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32278 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32279 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32280 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32281 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32282 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32283 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32284 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32285 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32286 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32287 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32288 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32289 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32290 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32291 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32292 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32293 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32294 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32295 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32296 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32297 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32298 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32299 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32300 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32301 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32302 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32303 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32304 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32305 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32306 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32307 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32308 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32309 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32310 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32311 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32312 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32313 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32314 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32315 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32316 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32317 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32318 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32319 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32320 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32321 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32322 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32323 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32324 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32325 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32326 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32327 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32330 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32331 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32333 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32334 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32335 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32336 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32337 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32338 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32339 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32340 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32341 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32342 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32343 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32344 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32345 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32346 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32347 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32348 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32349 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32350 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32351 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32352 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32353 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32354 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32355 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32356 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32357 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32358 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32359 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32360 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32361 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32362 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32363 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32364 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32365 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32366 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32367 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32368 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32369 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32370 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32371 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32372 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32373 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32374 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32377 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32378 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32379 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32380 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32381 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32382 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32383 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32384 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32385 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32386 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32387 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32388 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32389 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32390 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32394 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32395 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32396 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32398 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32399 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32400 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32401 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32402 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32403 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32404 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32405 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32406 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32407 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32408 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32412 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32419 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32420 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32421 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32422 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32423 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32424 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32425 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32426 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32427 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32428 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32429 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32430 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32431 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32432 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32433 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32434 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32435 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32436 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32437 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32438 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32439 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32440 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32441 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32442 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32443 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32444 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32445 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32446 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32447 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32448 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32449 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32450 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32451 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32452 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32453 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32454 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32455 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32456 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32457 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32458 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32459 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32460 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32461 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32464 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32465 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32466 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32469 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32470 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32471 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32472 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32473 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32474 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32475 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32476 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32479 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32480 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32481 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32482 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32483 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32484 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32485 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32486 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32487 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32488 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32489 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32490 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32491 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32492 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32493 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32494 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32495 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32496 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32497 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32498 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32499 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32500 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32501 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32502 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32503 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32504 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32505 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32506 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32507 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32508 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32509 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32510 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32511 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32512 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32514 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32515 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32516 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32517 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32518 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32519 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32520 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32521 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32522 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32523 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32524 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32525 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32526 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32527 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32528 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32529 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32533 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32534 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32535 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32536 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32537 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32539 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32540 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32541 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32542 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32543 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32544 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32545 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32546 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32547 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32548 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32549 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32550 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32551 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32552 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32553 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32554 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32556 /* AVX512DQ. */
32557 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32558 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32559 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32560 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32561 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32562 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32563 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32564 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32565 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32566 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32567 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32568 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32569 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32570 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32571 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32572 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32573 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32574 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32575 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32576 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32577 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32578 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32579 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32580 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32581 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32582 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32583 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32584 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32585 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32586 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
32587 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
32589 /* AVX512BW. */
32590 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
32591 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
32592 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32593 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32594 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32595 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32596 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
32597 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
32598 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32599 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32600 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
32601 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
32602 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
32603 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
32604 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
32605 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
32606 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32607 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32608 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32609 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32610 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32611 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32612 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32613 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32614 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32615 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32616 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32617 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32618 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32619 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32620 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32621 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32622 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32623 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32624 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32625 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32626 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32627 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32628 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32629 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32630 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32631 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32632 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32633 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32634 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32635 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32636 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32637 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32638 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32639 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32640 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32641 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32642 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32643 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32644 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32645 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32646 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
32647 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
32648 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32649 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32650 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32651 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32652 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32653 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32654 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32655 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32656 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32657 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32658 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32659 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32660 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
32661 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
32662 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
32663 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
32664 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32665 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32666 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32667 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32668 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32669 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32670 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32671 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32672 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32673 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32674 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32675 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32676 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32677 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32678 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32679 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32680 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32681 };
32683 /* Builtins with rounding support. */
32685 {
32686 /* AVX512F */
32687 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32688 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32689 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32690 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32691 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
32692 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
32693 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
32694 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
32695 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
32696 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
32697 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32698 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32699 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
32700 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32701 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
32702 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32703 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
32704 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32705 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
32706 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
32707 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
32708 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
32709 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
32710 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32711 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32712 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32713 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32714 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32715 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
32716 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
32717 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
32718 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32719 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32720 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32721 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32722 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32723 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32724 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32725 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32726 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32727 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32728 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32729 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32730 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32731 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32732 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32733 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32734 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32735 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32736 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32737 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32738 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32739 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32740 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32741 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32742 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32743 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32744 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32745 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32746 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32747 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32748 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32749 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32750 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32751 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32752 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32753 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32754 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32755 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32756 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32757 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32758 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32759 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32760 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32761 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32762 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32763 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32764 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32765 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32766 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32767 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
32768 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
32769 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
32770 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
32771 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
32772 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
32773 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
32774 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32775 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
32776 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
32777 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
32778 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
32779 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
32780 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
32781 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
32782 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32783 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32784 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32785 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32786 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32787 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32788 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
32789 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
32790 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32791 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32792 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32793 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32794 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32795 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32796 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32797 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32798 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32799 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32800 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32801 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32802 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32803 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32804 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32805 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32807 /* AVX512ER */
32808 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32809 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32810 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32811 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32812 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32813 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32814 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32815 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32816 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32817 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32819 /* AVX512DQ. */
32820 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32821 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32822 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32823 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32824 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32825 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32826 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
32827 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
32828 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
32829 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
32830 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32831 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32832 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32833 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32834 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
32835 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
32836 };
32838 /* Bultins for MPX. */
32840 {
32841 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
32842 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
32843 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
32844 };
32846 /* Const builtins for MPX. */
32848 {
32849 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
32850 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
32851 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
32852 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
32853 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
32854 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
32855 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
32856 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
32857 };
32859 /* FMA4 and XOP. */
32860 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
32861 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
32862 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
32863 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
32864 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
32865 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
32866 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
32867 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
32868 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
32869 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
32870 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
32871 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
32872 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
32873 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
32874 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
32875 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
32876 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
32877 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
32878 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
32879 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
32880 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
32881 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
32882 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
32883 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
32884 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
32885 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
32886 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
32887 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
32888 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
32889 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
32890 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
32891 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
32892 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
32893 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
32894 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
32895 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
32896 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
32897 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
32898 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
32899 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
32900 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
32901 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
32902 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
32903 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
32904 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
32905 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
32906 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
32907 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
32908 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
32909 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
32910 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
32911 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
32914 {
32955 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
32956 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
32957 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
32958 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
32959 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
32960 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
32961 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
32963 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
32964 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
32965 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
32966 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
32967 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
32968 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
32969 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
32971 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
32973 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
32974 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
32975 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
32976 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
32977 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
32978 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
32979 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
32980 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
32981 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
32982 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
32983 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
32984 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
32986 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
32987 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
32988 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
32989 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
32990 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
32991 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
32992 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
32993 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
32994 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
32995 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
32996 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
32997 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
32998 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
32999 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33000 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33001 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33003 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33004 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33005 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33006 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33007 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33008 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33010 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33011 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33012 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33013 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33014 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33015 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33016 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33017 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33018 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33019 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33020 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33021 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33022 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33023 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33024 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33026 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33027 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33028 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33029 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33030 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33031 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33032 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33034 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33035 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33036 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33037 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33038 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33039 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33040 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33042 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33043 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33044 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33045 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33046 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33047 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33048 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33050 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33051 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33052 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33053 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33054 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33055 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33056 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33058 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33059 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33060 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33061 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33062 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33063 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33064 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33066 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33067 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33068 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33069 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33070 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33071 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33072 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33074 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33075 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33076 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33077 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33078 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33079 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33080 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33082 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33083 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33084 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33085 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33086 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33087 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33088 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33090 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33091 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33092 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33093 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33094 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33095 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33096 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33097 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33099 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33100 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33101 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33102 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33103 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33104 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33105 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33106 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33108 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33109 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33110 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33111 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33113 };
33114 \f
33115 /* TM vector builtins. */
33117 /* Reuse the existing x86-specific `struct builtin_description' cause
33118 we're lazy. Add casts to make them fit. */
33120 {
33121 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33122 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33123 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33124 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33125 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33126 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33127 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33129 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33130 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33131 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33132 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33133 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33134 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33135 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33137 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33138 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33139 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33140 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33141 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33142 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33143 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33145 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33146 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33147 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33148 };
33150 /* TM callbacks. */
33152 /* Return the builtin decl needed to load a vector of TYPE. */
33154 static tree
33156 {
33158 {
33160 {
33167 }
33168 }
33170 }
33172 /* Return the builtin decl needed to store a vector of TYPE. */
33174 static tree
33176 {
33178 {
33180 {
33187 }
33188 }
33190 }
33191 \f
33192 /* Initialize the transactional memory vector load/store builtins. */
33194 static void
33196 {
33200 tree decl;
33207 /* If there are no builtins defined, we must be compiling in a
33208 language without trans-mem support. */
33212 /* Use whatever attributes a normal TM load has. */
33216 /* Use whatever attributes a normal TM store has. */
33220 /* Use whatever attributes a normal TM log has. */
33228 {
33232 {
33240 {
33243 }
33245 {
33248 }
33249 else
33250 {
33253 }
33255 /* The builtin without the prefix for
33256 calling it directly. */
33258 attrs);
33259 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33260 set the TYPE_ATTRIBUTES. */
33264 }
33265 }
33266 }
33268 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33269 in the current target ISA to allow the user to compile particular modules
33270 with different target specific options that differ from the command line
33271 options. */
33272 static void
33274 {
33279 /* Add all special builtins with variable number of operands. */
33283 {
33289 }
33291 /* Add all builtins with variable number of operands. */
33295 {
33301 }
33303 /* Add all builtins with rounding. */
33307 {
33313 }
33315 /* pcmpestr[im] insns. */
33319 {
33322 else
33325 }
33327 /* pcmpistr[im] insns. */
33331 {
33334 else
33337 }
33339 /* comi/ucomi insns. */
33341 {
33344 else
33347 }
33349 /* SSE */
33355 /* SSE or 3DNow!A */
33358 IX86_BUILTIN_MASKMOVQ);
33360 /* SSE2 */
33369 /* SSE3. */
33375 /* AES */
33389 /* PCLMUL */
33393 /* RDRND */
33400 IX86_BUILTIN_RDRAND64_STEP);
33402 /* AVX2 */
33404 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33405 IX86_BUILTIN_GATHERSIV2DF);
33408 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33409 IX86_BUILTIN_GATHERSIV4DF);
33412 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33413 IX86_BUILTIN_GATHERDIV2DF);
33416 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33417 IX86_BUILTIN_GATHERDIV4DF);
33420 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33421 IX86_BUILTIN_GATHERSIV4SF);
33424 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33425 IX86_BUILTIN_GATHERSIV8SF);
33428 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33429 IX86_BUILTIN_GATHERDIV4SF);
33432 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33433 IX86_BUILTIN_GATHERDIV8SF);
33436 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33437 IX86_BUILTIN_GATHERSIV2DI);
33440 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33441 IX86_BUILTIN_GATHERSIV4DI);
33444 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33445 IX86_BUILTIN_GATHERDIV2DI);
33448 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33449 IX86_BUILTIN_GATHERDIV4DI);
33452 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33453 IX86_BUILTIN_GATHERSIV4SI);
33456 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33457 IX86_BUILTIN_GATHERSIV8SI);
33460 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33461 IX86_BUILTIN_GATHERDIV4SI);
33464 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33465 IX86_BUILTIN_GATHERDIV8SI);
33468 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33469 IX86_BUILTIN_GATHERALTSIV4DF);
33472 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33473 IX86_BUILTIN_GATHERALTDIV8SF);
33476 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33477 IX86_BUILTIN_GATHERALTSIV4DI);
33480 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33481 IX86_BUILTIN_GATHERALTDIV8SI);
33483 /* AVX512F */
33485 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33486 IX86_BUILTIN_GATHER3SIV16SF);
33489 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33490 IX86_BUILTIN_GATHER3SIV8DF);
33493 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33494 IX86_BUILTIN_GATHER3DIV16SF);
33497 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33498 IX86_BUILTIN_GATHER3DIV8DF);
33501 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33502 IX86_BUILTIN_GATHER3SIV16SI);
33505 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33506 IX86_BUILTIN_GATHER3SIV8DI);
33509 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33510 IX86_BUILTIN_GATHER3DIV16SI);
33513 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33514 IX86_BUILTIN_GATHER3DIV8DI);
33517 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33518 IX86_BUILTIN_GATHER3ALTSIV8DF);
33521 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33522 IX86_BUILTIN_GATHER3ALTDIV16SF);
33525 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33526 IX86_BUILTIN_GATHER3ALTSIV8DI);
33529 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33530 IX86_BUILTIN_GATHER3ALTDIV16SI);
33533 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33534 IX86_BUILTIN_SCATTERSIV16SF);
33537 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33538 IX86_BUILTIN_SCATTERSIV8DF);
33541 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33542 IX86_BUILTIN_SCATTERDIV16SF);
33545 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33546 IX86_BUILTIN_SCATTERDIV8DF);
33549 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33550 IX86_BUILTIN_SCATTERSIV16SI);
33553 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33554 IX86_BUILTIN_SCATTERSIV8DI);
33557 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
33558 IX86_BUILTIN_SCATTERDIV16SI);
33561 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
33562 IX86_BUILTIN_SCATTERDIV8DI);
33564 /* AVX512VL */
33566 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
33567 IX86_BUILTIN_GATHER3SIV2DF);
33570 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
33571 IX86_BUILTIN_GATHER3SIV4DF);
33574 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
33575 IX86_BUILTIN_GATHER3DIV2DF);
33578 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
33579 IX86_BUILTIN_GATHER3DIV4DF);
33582 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
33583 IX86_BUILTIN_GATHER3SIV4SF);
33586 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
33587 IX86_BUILTIN_GATHER3SIV8SF);
33590 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
33591 IX86_BUILTIN_GATHER3DIV4SF);
33594 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
33595 IX86_BUILTIN_GATHER3DIV8SF);
33598 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
33599 IX86_BUILTIN_GATHER3SIV2DI);
33602 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
33603 IX86_BUILTIN_GATHER3SIV4DI);
33606 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
33607 IX86_BUILTIN_GATHER3DIV2DI);
33610 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
33611 IX86_BUILTIN_GATHER3DIV4DI);
33614 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
33615 IX86_BUILTIN_GATHER3SIV4SI);
33618 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
33619 IX86_BUILTIN_GATHER3SIV8SI);
33622 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
33623 IX86_BUILTIN_GATHER3DIV4SI);
33626 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
33627 IX86_BUILTIN_GATHER3DIV8SI);
33630 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
33631 IX86_BUILTIN_GATHER3ALTSIV4DF);
33634 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
33635 IX86_BUILTIN_GATHER3ALTDIV8SF);
33638 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
33639 IX86_BUILTIN_GATHER3ALTSIV4DI);
33642 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
33643 IX86_BUILTIN_GATHER3ALTDIV8SI);
33646 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
33647 IX86_BUILTIN_SCATTERSIV8SF);
33650 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
33651 IX86_BUILTIN_SCATTERSIV4SF);
33654 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
33655 IX86_BUILTIN_SCATTERSIV4DF);
33658 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
33659 IX86_BUILTIN_SCATTERSIV2DF);
33662 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
33663 IX86_BUILTIN_SCATTERDIV8SF);
33666 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
33667 IX86_BUILTIN_SCATTERDIV4SF);
33670 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
33671 IX86_BUILTIN_SCATTERDIV4DF);
33674 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
33675 IX86_BUILTIN_SCATTERDIV2DF);
33678 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
33679 IX86_BUILTIN_SCATTERSIV8SI);
33682 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
33683 IX86_BUILTIN_SCATTERSIV4SI);
33686 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
33687 IX86_BUILTIN_SCATTERSIV4DI);
33690 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
33691 IX86_BUILTIN_SCATTERSIV2DI);
33694 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
33695 IX86_BUILTIN_SCATTERDIV8SI);
33698 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
33699 IX86_BUILTIN_SCATTERDIV4SI);
33702 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
33703 IX86_BUILTIN_SCATTERDIV4DI);
33706 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
33707 IX86_BUILTIN_SCATTERDIV2DI);
33709 /* AVX512PF */
33711 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33712 IX86_BUILTIN_GATHERPFDPD);
33714 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33715 IX86_BUILTIN_GATHERPFDPS);
33717 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33718 IX86_BUILTIN_GATHERPFQPD);
33720 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33721 IX86_BUILTIN_GATHERPFQPS);
33723 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33724 IX86_BUILTIN_SCATTERPFDPD);
33726 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33727 IX86_BUILTIN_SCATTERPFDPS);
33729 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33730 IX86_BUILTIN_SCATTERPFQPD);
33732 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33733 IX86_BUILTIN_SCATTERPFQPS);
33735 /* SHA */
33751 /* RTM. */
33755 /* MMX access to the vec_init patterns. */
33760 V4HI_FTYPE_HI_HI_HI_HI,
33761 IX86_BUILTIN_VEC_INIT_V4HI);
33764 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
33765 IX86_BUILTIN_VEC_INIT_V8QI);
33767 /* Access to the vec_extract patterns. */
33789 /* Access to the vec_set patterns. */
33810 /* RDSEED */
33819 /* ADCX */
33824 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
33825 IX86_BUILTIN_ADDCARRYX64);
33827 /* SBB */
33832 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
33833 IX86_BUILTIN_SBB64);
33835 /* Read/write FLAGS. */
33845 /* CLFLUSHOPT. */
33849 /* Add FMA4 multi-arg argument instructions */
33851 {
33857 }
33858 }
33860 static void
33862 {
33865 tree decl;
33871 {
33878 /* With no leaf and nothrow flags for MPX builtins
33879 abnormal edges may follow its call when setjmp
33880 presents in the function. Since we may have a lot
33881 of MPX builtins calls it causes lots of useless
33882 edges and enormous PHI nodes. To avoid this we mark
33883 MPX builtins as leaf and nothrow. */
33885 {
33887 NULL_TREE);
33889 }
33890 else
33891 {
33894 }
33895 }
33900 {
33908 {
33910 NULL_TREE);
33912 }
33913 else
33914 {
33917 }
33918 }
33919 }
33921 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
33922 to return a pointer to VERSION_DECL if the outcome of the expression
33923 formed by PREDICATE_CHAIN is true. This function will be called during
33924 version dispatch to decide which function version to execute. It returns
33925 the basic block at the end, to which more conditions can be added. */
33927 static basic_block
33930 {
33931 gimple return_stmt;
33933 gimple convert_stmt;
33934 gimple call_cond_stmt;
33935 gimple if_else_stmt;
33941 gimple_seq gseq;
33958 {
33966 }
33969 {
33984 else
33985 {
33986 gimple assign_stmt;
33987 /* Use MIN_EXPR to check if any integer is zero?.
33988 and_expr_var = min_expr <cond_var, and_expr_var> */
33996 }
33997 }
34000 integer_zero_node,
34030 }
34032 /* This parses the attribute arguments to target in DECL and determines
34033 the right builtin to use to match the platform specification.
34034 It returns the priority value for this version decl. If PREDICATE_LIST
34035 is not NULL, it stores the list of cpu features that need to be checked
34036 before dispatching this function. */
34038 static unsigned int
34040 {
34041 tree attrs;
34043 tree target_node;
34050 /* Priority of i386 features, greater value is higher priority. This is
34051 used to decide the order in which function dispatch must happen. For
34052 instance, a version specialized for SSE4.2 should be checked for dispatch
34053 before a version for SSE3, as SSE4.2 implies SSE3. */
34054 enum feature_priority
34055 {
34057 P_MMX,
34058 P_SSE,
34059 P_SSE2,
34060 P_SSE3,
34061 P_SSSE3,
34062 P_PROC_SSSE3,
34063 P_SSE4_A,
34064 P_PROC_SSE4_A,
34065 P_SSE4_1,
34066 P_SSE4_2,
34067 P_PROC_SSE4_2,
34068 P_POPCNT,
34069 P_AVX,
34070 P_PROC_AVX,
34071 P_FMA4,
34072 P_XOP,
34073 P_PROC_XOP,
34074 P_FMA,
34075 P_PROC_FMA,
34076 P_AVX2,
34077 P_PROC_AVX2
34078 };
34082 /* These are the target attribute strings for which a dispatcher is
34083 available, from fold_builtin_cpu. */
34085 static struct _feature_list
34086 {
34089 }
34091 {
34106 };
34109 static unsigned int NUM_FEATURES
34125 /* Return priority zero for default function. */
34129 /* Handle arch= if specified. For priority, set it to be 1 more than
34130 the best instruction set the processor can handle. For instance, if
34131 there is a version for atom and a version for ssse3 (the highest ISA
34132 priority for atom), the atom version must be checked for dispatch
34133 before the ssse3 version. */
34135 {
34145 {
34147 {
34155 else
34156 /* We translate "arch=corei7" and "arch=nehalem" to
34157 "corei7" so that it will be mapped to M_INTEL_COREI7
34158 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34165 else
34172 else
34212 }
34213 }
34218 {
34222 }
34225 {
34227 /* For a C string literal the length includes the trailing NULL. */
34230 predicate_chain);
34231 }
34232 }
34234 /* Process feature name. */
34241 {
34242 /* Do not process "arch=" */
34244 {
34247 }
34249 {
34251 {
34253 {
34258 predicate_chain);
34259 }
34260 /* Find the maximum priority feature. */
34265 }
34266 }
34268 {
34272 }
34274 }
34278 {
34281 attrs_str);
34283 }
34285 {
34288 }
34291 }
34293 /* This compares the priority of target features in function DECL1
34294 and DECL2. It returns positive value if DECL1 is higher priority,
34295 negative value if DECL2 is higher priority and 0 if they are the
34296 same. */
34298 static int
34300 {
34305 }
34307 /* V1 and V2 point to function versions with different priorities
34308 based on the target ISA. This function compares their priorities. */
34310 static int
34312 {
34314 {
34315 tree version_decl;
34316 tree predicate_chain;
34323 }
34325 /* This function generates the dispatch function for
34326 multi-versioned functions. DISPATCH_DECL is the function which will
34327 contain the dispatch logic. FNDECLS are the function choices for
34328 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34329 in DISPATCH_DECL in which the dispatch code is generated. */
34331 static int
34335 {
34336 tree default_decl;
34337 gimple ifunc_cpu_init_stmt;
34338 gimple_seq gseq;
34340 tree ele;
34346 struct _function_version_info
34347 {
34348 tree version_decl;
34349 tree predicate_chain;
34357 /*fndecls_p is actually a vector. */
34360 /* At least one more version other than the default. */
34367 /* The first version in the vector is the default decl. */
34373 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34374 constructors, so explicity call __builtin_cpu_init here. */
34385 {
34389 /* Get attribute string, parse it and find the right predicate decl.
34390 The predicate function could be a lengthy combination of many
34391 features, like arch-type and various isa-variants. */
34402 actual_versions++;
34403 }
34405 /* Sort the versions according to descending order of dispatch priority. The
34406 priority is based on the ISA. This is not a perfect solution. There
34407 could still be ambiguity. If more than one function version is suitable
34408 to execute, which one should be dispatched? In future, allow the user
34409 to specify a dispatch priority next to the version. */
34419 /* dispatch default version at the end. */
34425 }
34427 /* Comparator function to be used in qsort routine to sort attribute
34428 specification strings to "target". */
34430 static int
34432 {
34436 }
34438 /* ARGLIST is the argument to target attribute. This function tokenizes
34439 the comma separated arguments, sorts them and returns a string which
34440 is a unique identifier for the comma separated arguments. It also
34441 replaces non-identifier characters "=,-" with "_". */
34445 {
34446 tree arg;
34455 {
34460 argnum++;
34463 argnum++;
34464 }
34469 {
34475 }
34477 /* Replace "=,-" with "_". */
34490 {
34492 i++;
34494 }
34501 {
34506 }
34511 }
34513 /* This function changes the assembler name for functions that are
34514 versions. If DECL is a function version and has a "target"
34515 attribute, it appends the attribute string to its assembler name. */
34517 static tree
34519 {
34520 tree version_attr;
34528 "Function versions cannot be marked as gnu_inline,"
34537 /* target attribute string cannot be NULL. */
34541 version_string
34552 /* Allow assembler name to be modified if already set. */
34560 }
34562 /* This function returns true if FN1 and FN2 are versions of the same function,
34563 that is, the target strings of the function decls are different. This assumes
34564 that FN1 and FN2 have the same signature. */
34566 static bool
34568 {
34580 /* At least one function decl should have the target attribute specified. */
34584 /* Diagnose missing target attribute if one of the decls is already
34585 multi-versioned. */
34587 {
34589 {
34591 {
34596 }
34599 fn2);
34602 /* Prevent diagnosing of the same error multiple times. */
34607 }
34609 }
34614 /* The sorted target strings must be different for fn1 and fn2
34615 to be versions. */
34618 else
34625 }
34627 static tree
34629 {
34630 /* For function version, add the target suffix to the assembler name. */
34634 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
34636 #endif
34639 }
34641 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
34642 is true, append the full path name of the source file. */
34646 {
34654 /* Get a unique name that can be used globally without any chances
34655 of collision at link time. */
34665 /* Use '.' to concatenate names as it is demangler friendly. */
34668 suffix);
34669 else
34673 }
34675 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34677 /* Make a dispatcher declaration for the multi-versioned function DECL.
34678 Calls to DECL function will be replaced with calls to the dispatcher
34679 by the front-end. Return the decl created. */
34681 static tree
34683 {
34684 tree func_decl;
34704 /* Mark this func as external, the resolver will flip it again if
34705 it gets generated. */
34707 /* This will be of type IFUNCs have to be externally visible. */
34711 }
34713 #endif
34715 /* Returns true if decl is multi-versioned and DECL is the default function,
34716 that is it is not tagged with target specific optimization. */
34718 static bool
34720 {
34729 }
34731 /* Make a dispatcher declaration for the multi-versioned function DECL.
34732 Calls to DECL function will be replaced with calls to the dispatcher
34733 by the front-end. Returns the decl of the dispatcher function. */
34735 static tree
34737 {
34759 /* Find the default version and make it the first node. */
34761 /* Go to the beginning of the chain. */
34766 {
34771 }
34773 /* If there is no default node, just return NULL. */
34777 /* Make default info the first node. */
34779 {
34786 }
34790 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34792 {
34797 /* Right now, the dispatching is done via ifunc. */
34803 dispatcher_version_info
34808 /* Set the dispatcher for all the versions. */
34811 {
34814 }
34815 }
34816 else
34817 #endif
34818 {
34820 "multiversioning needs ifunc which is not supported "
34822 }
34825 }
34827 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
34828 it to CHAIN. */
34830 static tree
34832 {
34833 tree attr_name;
34834 tree attr_arg_name;
34835 tree attr_args;
34836 tree attr;
34843 }
34845 /* Make the resolver function decl to dispatch the versions of
34846 a multi-versioned function, DEFAULT_DECL. Create an
34847 empty basic block in the resolver and store the pointer in
34848 EMPTY_BB. Return the decl of the resolver function. */
34850 static tree
34854 {
34859 /* IFUNC's have to be globally visible. So, if the default_decl is
34860 not, then the name of the IFUNC should be made unique. */
34864 /* Append the filename to the resolver function if the versions are
34865 not externally visible. This is because the resolver function has
34866 to be externally visible for the loader to find it. So, appending
34867 the filename will prevent conflicts with a resolver function from
34868 another module which is based on the same version name. */
34871 /* The resolver function should return a (void *). */
34882 /* IFUNC resolvers have to be externally visible. */
34886 /* Resolver is not external, body is generated. */
34896 {
34897 /* In this case, each translation unit with a call to this
34898 versioned function will put out a resolver. Ensure it
34899 is comdat to keep just one copy. */
34902 }
34903 /* Build result decl and add to function_decl. */
34919 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
34923 /* Create the alias for dispatch to resolver here. */
34924 /*cgraph_create_function_alias (dispatch_decl, decl);*/
34928 }
34930 /* Generate the dispatching code body to dispatch multi-versioned function
34931 DECL. The target hook is called to process the "target" attributes and
34932 provide the code to dispatch the right function at run-time. NODE points
34933 to the dispatcher decl whose body will be created. */
34935 static tree
34937 {
34938 tree resolver_decl;
34939 basic_block empty_bb;
34940 tree default_ver_decl;
34956 /* The first version in the chain corresponds to the default version. */
34959 /* node is going to be an alias, so remove the finalized bit. */
34973 {
34975 /* Check for virtual functions here again, as by this time it should
34976 have been determined if this function needs a vtable index or
34977 not. This happens for methods in derived classes that override
34978 virtual methods in base classes but are not explicitly marked as
34979 virtual. */
34984 }
34990 }
34991 /* This builds the processor_model struct type defined in
34992 libgcc/config/i386/cpuinfo.c */
34994 static tree
34996 {
35003 /* The first 3 fields are unsigned int. */
35005 {
35011 }
35013 /* The last field is an array of unsigned integers of size one. */
35024 }
35026 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35028 static tree
35030 {
35031 tree new_decl;
35034 VAR_DECL,
35036 type);
35049 }
35051 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35052 into an integer defined in libgcc/config/i386/cpuinfo.c */
35054 static tree
35056 {
35062 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35063 enum processor_features
35064 {
35066 F_MMX,
35067 F_POPCNT,
35068 F_SSE,
35069 F_SSE2,
35070 F_SSE3,
35071 F_SSSE3,
35072 F_SSE4_1,
35073 F_SSE4_2,
35074 F_AVX,
35075 F_AVX2,
35076 F_SSE4_A,
35077 F_FMA4,
35078 F_XOP,
35079 F_FMA,
35080 F_MAX
35081 };
35083 /* These are the values for vendor types and cpu types and subtypes
35084 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35085 the corresponding start value. */
35086 enum processor_model
35087 {
35089 M_AMD,
35090 M_CPU_TYPE_START,
35091 M_INTEL_BONNELL,
35092 M_INTEL_CORE2,
35093 M_INTEL_COREI7,
35094 M_AMDFAM10H,
35095 M_AMDFAM15H,
35096 M_INTEL_SILVERMONT,
35097 M_AMD_BTVER1,
35098 M_AMD_BTVER2,
35099 M_CPU_SUBTYPE_START,
35100 M_INTEL_COREI7_NEHALEM,
35101 M_INTEL_COREI7_WESTMERE,
35102 M_INTEL_COREI7_SANDYBRIDGE,
35103 M_AMDFAM10H_BARCELONA,
35104 M_AMDFAM10H_SHANGHAI,
35105 M_AMDFAM10H_ISTANBUL,
35106 M_AMDFAM15H_BDVER1,
35107 M_AMDFAM15H_BDVER2,
35108 M_AMDFAM15H_BDVER3,
35109 M_AMDFAM15H_BDVER4,
35110 M_INTEL_COREI7_IVYBRIDGE,
35111 M_INTEL_COREI7_HASWELL
35112 };
35114 static struct _arch_names_table
35115 {
35118 }
35120 {
35145 };
35147 static struct _isa_names_table
35148 {
35151 }
35153 {
35169 };
35183 {
35184 /* *args must be a expr that can contain other EXPRS leading to a
35185 STRING_CST. */
35187 {
35190 }
35192 }
35197 {
35198 tree ref;
35199 tree field;
35200 tree final;
35203 unsigned int NUM_ARCH_NAMES
35212 {
35216 }
35221 /* CPU types are stored in the next field. */
35224 {
35227 }
35229 /* CPU subtypes are stored in the next field. */
35231 {
35234 }
35236 /* Get the appropriate field in __cpu_model. */
35240 /* Check the value. */
35244 }
35246 {
35247 tree ref;
35248 tree array_elt;
35249 tree field;
35250 tree final;
35253 unsigned int NUM_ISA_NAMES
35262 {
35266 }
35269 /* Get the last field, which is __cpu_features. */
35273 /* Get the appropriate field: __cpu_model.__cpu_features */
35277 /* Access the 0th element of __cpu_features array. */
35282 /* Return __cpu_model.__cpu_features[0] & field_val */
35286 }
35288 }
35290 static tree
35293 {
35295 {
35300 {
35303 }
35304 }
35306 #ifdef SUBTARGET_FOLD_BUILTIN
35308 #endif
35311 }
35313 /* Make builtins to detect cpu type and features supported. NAME is
35314 the builtin name, CODE is the builtin code, and FTYPE is the function
35315 type of the builtin. */
35317 static void
35320 {
35321 tree decl;
35322 tree type;
35330 }
35332 /* Make builtins to get CPU type and features supported. The created
35333 builtins are :
35335 __builtin_cpu_init (), to detect cpu type and features,
35336 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35337 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35338 */
35340 static void
35342 {
35349 }
35351 /* Internal method for ix86_init_builtins. */
35353 static void
35355 {
35367 sysv_va_ref =
35370 fnvoid_va_end_ms =
35372 fnvoid_va_start_ms =
35374 fnvoid_va_end_sysv =
35376 fnvoid_va_start_sysv =
35378 NULL_TREE);
35379 fnvoid_va_copy_ms =
35381 NULL_TREE);
35382 fnvoid_va_copy_sysv =
35398 }
35400 static void
35402 {
35405 /* The __float80 type. */
35408 {
35409 /* The __float80 type. */
35414 }
35417 /* The __float128 type. */
35423 /* This macro is built by i386-builtin-types.awk. */
35424 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35425 }
35427 static void
35429 {
35430 tree t;
35434 /* Builtins to get CPU type and features. */
35437 /* TFmode support builtins. */
35443 /* We will expand them to normal call if SSE isn't available since
35444 they are used by libgcc. */
35464 #ifdef SUBTARGET_INIT_BUILTINS
35465 SUBTARGET_INIT_BUILTINS;
35466 #endif
35467 }
35469 /* Return the ix86 builtin for CODE. */
35471 static tree
35473 {
35478 }
35480 /* Errors in the source file can cause expand_expr to return const0_rtx
35481 where we expect a vector. To avoid crashing, use one of the vector
35482 clear instructions. */
35483 static rtx
35485 {
35489 }
35491 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35493 static rtx
35495 {
35496 rtx pat;
35516 {
35520 }
35534 }
35536 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
35538 static rtx
35542 {
35543 rtx pat;
35551 rtx op;
35552 machine_mode mode;
35558 {
35638 }
35648 {
35655 {
35657 {
35660 {
35678 xop_rotl:
35680 {
35683 gcc_checking_assert
35685 }
35686 else
35687 {
35688 gcc_checking_assert
35699 }
35703 }
35704 }
35705 }
35706 else
35707 {
35708 non_constant:
35712 /* If we aren't optimizing, only allow one memory operand to be
35713 generated. */
35715 num_memory++;
35723 }
35727 }
35730 {
35741 else
35742 {
35748 }
35761 }
35768 }
35770 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
35771 insns with vec_merge. */
35773 static rtx
35775 rtx target)
35776 {
35777 rtx pat;
35804 }
35806 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
35808 static rtx
35811 {
35812 rtx pat;
35817 rtx op2;
35828 /* Swap operands if we have a comparison that isn't available in
35829 hardware. */
35831 {
35836 }
35856 }
35858 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
35860 static rtx
35862 rtx target)
35863 {
35864 rtx pat;
35878 /* Swap operands if we have a comparison that isn't available in
35879 hardware. */
35902 const0_rtx)));
35905 }
35907 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
35909 static rtx
35911 rtx target)
35912 {
35913 rtx pat;
35938 }
35940 static rtx
35943 {
35944 rtx pat;
35949 rtx op2;
35976 }
35978 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
35980 static rtx
35982 rtx target)
35983 {
35984 rtx pat;
36017 const0_rtx)));
36020 }
36022 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36024 static rtx
36027 {
36028 rtx pat;
36066 {
36069 }
36072 {
36081 }
36083 {
36092 }
36093 else
36094 {
36101 }
36109 {
36114 emit_insn
36118 FLAGS_REG),
36119 const0_rtx)));
36121 }
36122 else
36124 }
36127 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36129 static rtx
36132 {
36133 rtx pat;
36161 {
36164 }
36167 {
36176 }
36178 {
36187 }
36188 else
36189 {
36196 }
36204 {
36209 emit_insn
36213 FLAGS_REG),
36214 const0_rtx)));
36216 }
36217 else
36219 }
36221 /* Subroutine of ix86_expand_builtin to take care of insns with
36222 variable number of operands. */
36224 static rtx
36227 {
36233 struct
36234 {
36235 rtx op;
36236 machine_mode mode;
36247 {
36957 }
36962 {
36965 }
36968 {
36975 }
36976 else
36977 {
36980 }
36983 {
36990 {
36991 /* SIMD shift insns take either an 8-bit immediate or
36992 register as count. But builtin functions take int as
36993 count. If count doesn't match, we put it in register. */
36995 {
36999 }
37000 }
37003 {
37006 {
37115 {
37119 {
37122 }
37128 }
37130 }
37131 }
37132 else
37133 {
37137 /* If we aren't optimizing, only allow one memory operand to
37138 be generated. */
37140 num_memory++;
37143 {
37146 }
37147 else
37148 {
37151 }
37152 }
37156 }
37159 {
37184 }
37191 }
37193 /* Transform pattern of following layout:
37194 (parallel [
37195 set (A B)
37196 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37197 ])
37198 into:
37199 (set (A B))
37201 Or:
37202 (parallel [ A B
37203 ...
37204 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37205 ...
37206 ])
37207 into:
37208 (parallel [ A B ... ]) */
37210 static rtx
37212 {
37219 {
37228 }
37229 else
37230 {
37236 {
37241 }
37243 /* No more than 1 occurence was removed. */
37247 }
37248 }
37250 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37251 with rounding. */
37252 static rtx
37255 {
37272 /* See avxintrin.h for values. */
37274 {
37278 };
37280 {
37285 };
37288 {
37291 }
37293 {
37296 }
37299 {
37302 }
37325 ? CODE_FOR_sse_ucomi_round
37332 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37334 {
37340 }
37341 else
37342 {
37345 }
37351 set_dst,
37352 const0_rtx)));
37355 }
37357 static rtx
37360 {
37361 rtx pat;
37363 struct
37364 {
37365 rtx op;
37366 machine_mode mode;
37375 {
37458 }
37468 {
37475 {
37477 {
37479 {
37495 }
37496 }
37497 }
37499 {
37501 {
37504 }
37506 /* If there is no rounding use normal version of the pattern. */
37509 }
37510 else
37511 {
37516 {
37519 }
37520 else
37521 {
37524 }
37525 }
37529 }
37532 {
37557 }
37567 }
37569 /* Subroutine of ix86_expand_builtin to take care of special insns
37570 with variable number of operands. */
37572 static rtx
37575 {
37576 tree arg;
37580 struct
37581 {
37582 rtx op;
37583 machine_mode mode;
37592 {
37632 {
37640 }
37659 /* Reserve memory operand for target. */
37662 {
37663 /* These builtins and instructions require the memory
37664 to be properly aligned. */
37683 }
37712 {
37713 /* These builtins and instructions require the memory
37714 to be properly aligned. */
37731 }
37732 /* FALLTHRU */
37770 /* Reserve memory operand for target. */
37797 {
37798 /* These builtins and instructions require the memory
37799 to be properly aligned. */
37822 }
37835 }
37840 {
37845 {
37848 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
37849 on it. Try to improve it using get_pointer_alignment,
37850 and if the special builtin is one that requires strict
37851 mode alignment, also from it's GET_MODE_ALIGNMENT.
37852 Failure to do so could lead to ix86_legitimate_combined_insn
37853 rejecting all changes to such insns. */
37859 }
37860 else
37863 }
37864 else
37865 {
37872 }
37875 {
37884 {
37886 {
37892 else
37895 }
37896 }
37897 else
37898 {
37900 {
37901 /* This must be the memory operand. */
37904 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
37905 on it. Try to improve it using get_pointer_alignment,
37906 and if the special builtin is one that requires strict
37907 mode alignment, also from it's GET_MODE_ALIGNMENT.
37908 Failure to do so could lead to ix86_legitimate_combined_insn
37909 rejecting all changes to such insns. */
37915 }
37916 else
37917 {
37918 /* This must be register. */
37924 else
37925 {
37928 }
37929 }
37930 }
37934 }
37937 {
37952 }
37958 }
37960 /* Return the integer constant in ARG. Constrain it to be in the range
37961 of the subparts of VEC_TYPE; issue an error if not. */
37963 static int
37965 {
37970 {
37973 }
37976 }
37978 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
37979 ix86_expand_vector_init. We DO have language-level syntax for this, in
37980 the form of (type){ init-list }. Except that since we can't place emms
37981 instructions from inside the compiler, we can't allow the use of MMX
37982 registers unless the user explicitly asks for it. So we do *not* define
37983 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
37984 we have builtins invoked by mmintrin.h that gives us license to emit
37985 these sorts of instructions. */
37987 static rtx
37989 {
37999 {
38002 }
38009 }
38011 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38012 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38013 had a language-level syntax for referencing vector elements. */
38015 static rtx
38017 {
38021 rtx op0;
38041 }
38043 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38044 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38045 a language-level syntax for referencing vector elements. */
38047 static rtx
38049 {
38073 /* OP0 is the source of these builtin functions and shouldn't be
38074 modified. Create a copy, use it and return it as target. */
38080 }
38082 /* Emit conditional move of SRC to DST with condition
38083 OP1 CODE OP2. */
38084 static void
38086 {
38087 rtx t;
38090 {
38095 }
38096 else
38097 {
38103 }
38104 }
38106 /* Choose max of DST and SRC and put it to DST. */
38107 static void
38109 {
38111 }
38113 /* Expand an expression EXP that calls a built-in function,
38114 with result going to TARGET if that's convenient
38115 (and in mode MODE if that's convenient).
38116 SUBTARGET may be used as the target for computing one of EXP's operands.
38117 IGNORE is nonzero if the value is to be ignored. */
38119 static rtx
38122 {
38132 /* For CPU builtins that can be folded, fold first and expand the fold. */
38134 {
38136 {
38137 /* Make it call __cpu_indicator_init in libgcc. */
38143 }
38146 {
38151 }
38152 }
38154 /* Determine whether the builtin function is available under the current ISA.
38155 Originally the builtin was not created if it wasn't applicable to the
38156 current ISA based on the command line switches. With function specific
38157 options, we need to check in the context of the function making the call
38158 whether it is supported. */
38161 {
38167 else
38168 {
38172 }
38174 }
38177 {
38195 /* Builtin arg1 is size of block but instruction op1 should
38196 be (size - 1). */
38287 /* If no bounds were specified for returned value,
38288 then use INIT bounds. It usually happens when
38289 some built-in function is expanded. */
38291 {
38300 }
38306 {
38309 /* Return value and lb. */
38311 /* Bounds. */
38313 /* Size. */
38320 /* Size was passed but we need to use (size - 1) as for bndmk. */
38324 /* Add LB to size and inverse to get UB. */
38334 /* We need to move bounds to memory before any computations. */
38337 else
38338 {
38341 }
38343 /* Generate mem expression to be used for access to LB and UB. */
38349 /* Compute LB. */
38354 /* Compute UB. UB is stored in 1's complement form. Therefore
38355 we also use max here. */
38364 }
38367 {
38385 /* Put first bounds to temporaries. */
38389 {
38393 }
38394 else
38395 {
38399 }
38401 /* Put second bounds to temporaries. */
38405 {
38409 }
38410 else
38411 {
38415 }
38417 /* Compute LB. */
38421 /* Compute UB. UB is stored in 1's complement form. Therefore
38422 we also use max here. */
38429 }
38432 {
38433 tree name;
38434 rtx symbol;
38452 }
38455 {
38466 /* We need to move bounds to memory first. */
38469 else
38470 {
38473 }
38475 /* Generate mem expression to access LB and load it. */
38480 }
38483 {
38494 /* We need to move bounds to memory first. */
38497 else
38498 {
38501 }
38503 /* Generate mem expression to access UB. */
38506 /* We need to inverse all bits of UB. */
38513 }
38518 ? CODE_FOR_mmx_maskmovq
38520 /* Note the arg order is different from the operand order. */
38631 {
38632 REAL_VALUE_TYPE inf;
38633 rtx tmp;
38645 }
38655 {
38661 insn = (TARGET_64BIT
38665 }
38667 {
38668 insn = (TARGET_64BIT
38672 }
38673 else
38674 {
38677 insn = (TARGET_64BIT
38685 {
38688 }
38690 }
38693 {
38694 /* mode is VOIDmode if __builtin_rd* has been called
38695 without lhs. */
38699 }
38702 {
38707 }
38720 {
38741 }
38747 {
38750 }
38776 {
38779 }
38785 {
38789 {
38828 }
38833 }
38834 else
38835 {
38837 {
38858 }
38860 }
38890 ? CODE_FOR_tbm_bextri_si
38893 {
38896 }
38897 else
38898 {
38907 }
38923 rdrand_step:
38930 {
38933 }
38939 /* Emit SImode conditional move. */
38941 {
38944 }
38947 else
38955 const0_rtx);
38974 rdseed_step:
38981 {
38984 }
38990 const0_rtx);
39019 addcarryx:
39027 /* Generate CF from input operand. */
39032 /* Gen ADCX instruction to compute X+Y+CF. */
39047 /* Store the result. */
39050 {
39053 }
39056 /* Return current CF value. */
39098 kortest:
39112 /* Emit kortest. */
39114 /* And use setcc to return result from flags. */
39372 gather_gen:
39373 rtx half;
39386 /* Note the arg order is different from the operand order. */
39397 else
39401 {
39425 else
39432 {
39437 }
39446 else
39453 {
39458 }
39462 }
39464 /* Force memory operand only with base register here. But we
39465 don't want to do it on memory operand for other builtin
39466 functions. */
39476 {
39479 }
39480 else
39481 {
39484 }
39486 {
39489 }
39491 /* Optimize. If mask is known to have all high bits set,
39492 replace op0 with pc_rtx to signal that the instruction
39493 overwrites the whole destination and doesn't use its
39494 previous contents. */
39496 {
39498 {
39501 }
39503 {
39506 {
39510 negative++;
39513 negative++;
39514 }
39517 }
39520 {
39521 /* Recognize also when mask is like:
39522 __v2df src = _mm_setzero_pd ();
39523 __v2df mask = _mm_cmpeq_pd (src, src);
39524 or
39525 __v8sf src = _mm256_setzero_ps ();
39526 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
39527 as that is a cheaper way to load all ones into
39528 a register than having to load a constant from
39529 memory. */
39532 {
39537 {
39544 /* FALLTHRU */
39554 }
39555 }
39556 }
39557 }
39565 {
39591 }
39594 scatter_gen:
39610 /* Force memory operand only with base register here. But we
39611 don't want to do it on memory operand for other builtin
39612 functions. */
39619 {
39622 }
39623 else
39624 {
39627 }
39636 {
39639 }
39648 vec_prefetch_gen:
39666 {
39669 }
39671 {
39674 }
39679 /* Force memory operand only with base register here. But we
39680 don't want to do it on memory operand for other builtin
39681 functions. */
39688 {
39691 }
39694 {
39697 }
39713 {
39716 }
39722 }
39735 {
39739 /* Emit a normal call if SSE isn't available. */
39743 }
39772 }
39774 /* This returns the target-specific builtin with code CODE if
39775 current_function_decl has visibility on this builtin, which is checked
39776 using isa flags. Returns NULL_TREE otherwise. */
39779 {
39783 /* Determine the isa flags of current_function_decl. */
39795 else
39797 }
39799 /* Return function decl for target specific builtin
39800 for given MPX builtin passed i FCODE. */
39801 static tree
39803 {
39805 {
39841 }
39844 }
39846 /* Helper function for ix86_load_bounds and ix86_store_bounds.
39848 Return an address to be used to load/store bounds for pointer
39849 passed in SLOT.
39851 SLOT_NO is an integer constant holding number of a target
39852 dependent special slot to be used in case SLOT is not a memory.
39854 SPECIAL_BASE is a pointer to be used as a base of fake address
39855 to access special slots in Bounds Table. SPECIAL_BASE[-1],
39856 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
39858 static rtx
39860 {
39863 /* NULL slot means we pass bounds for pointer not passed to the
39864 function at all. Register slot means we pass pointer in a
39865 register. In both these cases bounds are passed via Bounds
39866 Table. Since we do not have actual pointer stored in memory,
39867 we have to use fake addresses to access Bounds Table. We
39868 start with (special_base - sizeof (void*)) and decrease this
39869 address by pointer size to get addresses for other slots. */
39871 {
39875 }
39876 /* If pointer is passed in a memory then its address is used to
39877 access Bounds Table. */
39879 {
39883 }
39884 else
39888 }
39890 /* Expand pass uses this hook to load bounds for function parameter
39891 PTR passed in SLOT in case its bounds are not passed in a register.
39893 If SLOT is a memory, then bounds are loaded as for regular pointer
39894 loaded from memory. PTR may be NULL in case SLOT is a memory.
39895 In such case value of PTR (if required) may be loaded from SLOT.
39897 If SLOT is NULL or a register then SLOT_NO is an integer constant
39898 holding number of the target dependent special slot which should be
39899 used to obtain bounds.
39901 Return loaded bounds. */
39903 static rtx
39905 {
39907 rtx addr;
39909 /* Get address to be used to access Bounds Table. Special slots start
39910 at the location of return address of the current function. */
39913 /* Load pointer value from a memory if we don't have it. */
39915 {
39918 }
39925 }
39927 /* Expand pass uses this hook to store BOUNDS for call argument PTR
39928 passed in SLOT in case BOUNDS are not passed in a register.
39930 If SLOT is a memory, then BOUNDS are stored as for regular pointer
39931 stored in memory. PTR may be NULL in case SLOT is a memory.
39932 In such case value of PTR (if required) may be loaded from SLOT.
39934 If SLOT is NULL or a register then SLOT_NO is an integer constant
39935 holding number of the target dependent special slot which should be
39936 used to store BOUNDS. */
39938 static void
39940 {
39941 rtx addr;
39943 /* Get address to be used to access Bounds Table. Special slots start
39944 at the location of return address of a called function. */
39947 /* Load pointer value from a memory if we don't have it. */
39949 {
39952 }
39961 }
39963 /* Load and return bounds returned by function in SLOT. */
39965 static rtx
39967 {
39968 rtx res;
39975 }
39977 /* Store BOUNDS returned by function into SLOT. */
39979 static void
39981 {
39984 }
39986 /* Returns a function decl for a vectorized version of the builtin function
39987 with builtin function code FN and the result vector type TYPE, or NULL_TREE
39988 if it is not available. */
39990 static tree
39992 tree type_in)
39993 {
40009 {
40012 {
40019 }
40024 {
40027 }
40032 {
40039 }
40045 /* The round insn does not trap on denormals. */
40050 {
40057 }
40063 /* The round insn does not trap on denormals. */
40068 {
40073 }
40079 /* The round insn does not trap on denormals. */
40084 {
40091 }
40097 /* The round insn does not trap on denormals. */
40102 {
40107 }
40114 {
40119 }
40126 {
40131 }
40137 /* The round insn does not trap on denormals. */
40142 {
40149 }
40155 /* The round insn does not trap on denormals. */
40160 {
40165 }
40170 {
40177 }
40182 {
40189 }
40193 /* The round insn does not trap on denormals. */
40198 {
40203 }
40207 /* The round insn does not trap on denormals. */
40212 {
40217 }
40221 /* The round insn does not trap on denormals. */
40226 {
40231 }
40235 /* The round insn does not trap on denormals. */
40240 {
40245 }
40249 /* The round insn does not trap on denormals. */
40254 {
40259 }
40263 /* The round insn does not trap on denormals. */
40268 {
40273 }
40277 /* The round insn does not trap on denormals. */
40282 {
40287 }
40291 /* The round insn does not trap on denormals. */
40296 {
40301 }
40305 /* The round insn does not trap on denormals. */
40310 {
40315 }
40319 /* The round insn does not trap on denormals. */
40324 {
40329 }
40334 {
40339 }
40344 {
40349 }
40354 }
40356 /* Dispatch to a handler for a vectorization library. */
40359 type_in);
40362 }
40364 /* Handler for an SVML-style interface to
40365 a library with vectorized intrinsics. */
40367 static tree
40369 {
40377 /* The SVML is suitable for unsafe math only. */
40390 {
40437 }
40446 {
40449 }
40450 else
40453 /* Convert to uppercase. */
40458 args;
40460 arity++;
40464 else
40467 /* Build a function declaration for the vectorized function. */
40476 }
40478 /* Handler for an ACML-style interface to
40479 a library with vectorized intrinsics. */
40481 static tree
40483 {
40491 /* The ACML is 64bits only and suitable for unsafe math only as
40492 it does not correctly support parts of IEEE with the required
40493 precision such as denormals. */
40507 {
40537 }
40544 args;
40546 arity++;
40550 else
40553 /* Build a function declaration for the vectorized function. */
40562 }
40564 /* Returns a decl of a function that implements gather load with
40565 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
40566 Return NULL_TREE if it is not available. */
40568 static tree
40571 {
40587 /* v*gather* insn sign extends index to pointer mode. */
40599 {
40603 else
40609 else
40615 else
40621 else
40627 else
40633 else
40639 else
40645 else
40651 else
40657 else
40663 else
40669 else
40674 }
40677 }
40679 /* Returns a code for a target-specific builtin that implements
40680 reciprocal of the function, or NULL_TREE if not available. */
40682 static tree
40684 {
40691 /* Machine dependent builtins. */
40693 {
40694 /* Vectorized version of sqrt to rsqrt conversion. */
40703 }
40704 else
40705 /* Normal builtins. */
40707 {
40708 /* Sqrt to rsqrt conversion. */
40714 }
40715 }
40716 \f
40717 /* Helper for avx_vpermilps256_operand et al. This is also used by
40718 the expansion functions to turn the parallel back into a mask.
40719 The return value is 0 for no match and the imm8+1 for a match. */
40721 int
40723 {
40731 /* Validate that all of the elements are constants, and not totally
40732 out of range. Copy the data into an integral array to make the
40733 subsequent checks easier. */
40735 {
40745 }
40748 {
40750 /* In the 512-bit DFmode case, we can only move elements within
40751 a 128-bit lane. First fill the second part of the mask,
40752 then fallthru. */
40754 {
40758 }
40760 {
40764 }
40765 /* FALLTHRU */
40768 /* In the 256-bit DFmode case, we can only move elements within
40769 a 128-bit lane. */
40771 {
40775 }
40777 {
40781 }
40785 /* In 512 bit SFmode case, permutation in the upper 256 bits
40786 must mirror the permutation in the lower 256-bits. */
40790 /* FALLTHRU */
40793 /* In 256 bit SFmode case, we have full freedom of
40794 movement within the low 128-bit lane, but the high 128-bit
40795 lane must mirror the exact same pattern. */
40800 /* FALLTHRU */
40804 /* In the 128-bit case, we've full freedom in the placement of
40805 the elements from the source operand. */
40812 }
40814 /* Make sure success has a non-zero value by adding one. */
40816 }
40818 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
40819 the expansion functions to turn the parallel back into a mask.
40820 The return value is 0 for no match and the imm8+1 for a match. */
40822 int
40824 {
40832 /* Validate that all of the elements are constants, and not totally
40833 out of range. Copy the data into an integral array to make the
40834 subsequent checks easier. */
40836 {
40846 }
40848 /* Validate that the halves of the permute are halves. */
40856 /* Reconstruct the mask. */
40858 {
40864 }
40866 /* Make sure success has a non-zero value by adding one. */
40868 }
40869 \f
40870 /* Return a register priority for hard reg REGNO. */
40871 static int
40873 {
40874 /* ebp and r13 as the base always wants a displacement, r12 as the
40875 base always wants an index. So discourage their usage in an
40876 address. */
40881 /* New x86-64 int registers result in bigger code size. Discourage
40882 them. */
40885 /* New x86-64 SSE registers result in bigger code size. Discourage
40886 them. */
40889 /* Usage of AX register results in smaller code. Prefer it. */
40893 }
40895 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
40897 Put float CONST_DOUBLE in the constant pool instead of fp regs.
40898 QImode must go into class Q_REGS.
40899 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
40900 movdf to do mem-to-mem moves through integer regs. */
40902 static reg_class_t
40904 {
40907 /* We're only allowed to return a subclass of CLASS. Many of the
40908 following checks fail for NO_REGS, so eliminate that early. */
40912 /* All classes can load zeros. */
40916 /* Force constants into memory if we are loading a (nonzero) constant into
40917 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
40918 instructions to load from a constant. */
40925 /* Prefer SSE regs only, if we can use them for math. */
40929 /* Floating-point constants need more complex checks. */
40931 {
40932 /* General regs can load everything. */
40936 /* Floats can load 0 and 1 plus some others. Note that we eliminated
40937 zero above. We only want to wind up preferring 80387 registers if
40938 we plan on doing computation with them. */
40941 {
40942 /* Limit class to non-sse. */
40951 }
40954 }
40956 /* Generally when we see PLUS here, it's the function invariant
40957 (plus soft-fp const_int). Which can only be computed into general
40958 regs. */
40962 /* QImode constants are easy to load, but non-constant QImode data
40963 must go into Q_REGS. */
40965 {
40971 }
40974 }
40976 /* Discourage putting floating-point values in SSE registers unless
40977 SSE math is being used, and likewise for the 387 registers. */
40978 static reg_class_t
40980 {
40983 /* Restrict the output reload class to the register bank that we are doing
40984 math on. If we would like not to return a subset of CLASS, reject this
40985 alternative: if reload cannot do this, it will still use its choice. */
40991 {
40996 else
40998 }
41001 }
41003 static reg_class_t
41006 {
41007 /* Double-word spills from general registers to non-offsettable memory
41008 references (zero-extended addresses) require special handling. */
41014 {
41016 ? CODE_FOR_reload_noff_load
41018 /* Add the cost of moving address to a temporary. */
41022 }
41024 /* QImode spills from non-QI registers require
41025 intermediate register on 32bit targets. */
41031 {
41036 else
41042 /* Return Q_REGS if the operand is in memory. */
41045 }
41047 /* This condition handles corner case where an expression involving
41048 pointers gets vectorized. We're trying to use the address of a
41049 stack slot as a vector initializer.
41051 (set (reg:V2DI 74 [ vect_cst_.2 ])
41052 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41054 Eventually frame gets turned into sp+offset like this:
41056 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41057 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41058 (const_int 392 [0x188]))))
41060 That later gets turned into:
41062 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41063 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41064 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41066 We'll have the following reload recorded:
41068 Reload 0: reload_in (DI) =
41069 (plus:DI (reg/f:DI 7 sp)
41070 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41071 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41072 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41073 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41074 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41075 reload_reg_rtx: (reg:V2DI 22 xmm1)
41077 Which isn't going to work since SSE instructions can't handle scalar
41078 additions. Returning GENERAL_REGS forces the addition into integer
41079 register and reload can handle subsequent reloads without problems. */
41087 }
41089 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41091 static bool
41093 {
41095 {
41111 }
41114 }
41116 /* If we are copying between general and FP registers, we need a memory
41117 location. The same is true for SSE and MMX registers.
41119 To optimize register_move_cost performance, allow inline variant.
41121 The macro can't work reliably when one of the CLASSES is class containing
41122 registers from multiple units (SSE, MMX, integer). We avoid this by never
41123 combining those units in single alternative in the machine description.
41124 Ensure that this constraint holds to avoid unexpected surprises.
41126 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41127 enforce these sanity checks. */
41132 {
41141 {
41144 }
41149 /* Between mask and general, we have moves no larger than word size. */
41154 /* ??? This is a lie. We do have moves between mmx/general, and for
41155 mmx/sse2. But by saying we need secondary memory we discourage the
41156 register allocator from using the mmx registers unless needed. */
41161 {
41162 /* SSE1 doesn't have any direct moves from other classes. */
41166 /* If the target says that inter-unit moves are more expensive
41167 than moving through memory, then don't generate them. */
41172 /* Between SSE and general, we have moves no larger than word size. */
41175 }
41178 }
41180 bool
41183 {
41185 }
41187 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41189 On the 80386, this is the size of MODE in words,
41190 except in the FP regs, where a single reg is always enough. */
41192 static unsigned char
41194 {
41196 {
41201 else
41203 }
41204 else
41205 {
41208 else
41210 }
41211 }
41213 /* Return true if the registers in CLASS cannot represent the change from
41214 modes FROM to TO. */
41216 bool
41219 {
41223 /* x87 registers can't do subreg at all, as all values are reformatted
41224 to extended precision. */
41229 {
41230 /* Vector registers do not support QI or HImode loads. If we don't
41231 disallow a change to these modes, reload will assume it's ok to
41232 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41233 the vec_dupv4hi pattern. */
41236 }
41239 }
41241 /* Return the cost of moving data of mode M between a
41242 register and memory. A value of 2 is the default; this cost is
41243 relative to those in `REGISTER_MOVE_COST'.
41245 This function is used extensively by register_move_cost that is used to
41246 build tables at startup. Make it inline in this case.
41247 When IN is 2, return maximum of in and out move cost.
41249 If moving between registers and memory is more expensive than
41250 between two registers, you should define this macro to express the
41251 relative cost.
41253 Model also increased moving costs of QImode registers in non
41254 Q_REGS classes.
41255 */
41259 {
41262 {
41265 {
41277 }
41281 }
41283 {
41286 {
41298 }
41302 }
41304 {
41307 {
41316 }
41320 }
41322 {
41325 {
41331 else
41336 }
41337 else
41338 {
41343 else
41345 }
41352 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41359 else
41363 }
41364 }
41366 static int
41369 {
41371 }
41374 /* Return the cost of moving data from a register in class CLASS1 to
41375 one in class CLASS2.
41377 It is not required that the cost always equal 2 when FROM is the same as TO;
41378 on some machines it is expensive to move between registers if they are not
41379 general registers. */
41381 static int
41383 reg_class_t class2_i)
41384 {
41388 /* In case we require secondary memory, compute cost of the store followed
41389 by load. In order to avoid bad register allocation choices, we need
41390 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41393 {
41399 /* In case of copying from general_purpose_register we may emit multiple
41400 stores followed by single load causing memory size mismatch stall.
41401 Count this as arbitrarily high cost of 20. */
41406 /* In the case of FP/MMX moves, the registers actually overlap, and we
41407 have to switch modes in order to treat them differently. */
41413 }
41415 /* Moves between SSE/MMX and integer unit are expensive. */
41419 /* ??? By keeping returned value relatively high, we limit the number
41420 of moves between integer and MMX/SSE registers for all targets.
41421 Additionally, high value prevents problem with x86_modes_tieable_p(),
41422 where integer modes in MMX/SSE registers are not tieable
41423 because of missing QImode and HImode moves to, from or between
41424 MMX/SSE registers. */
41434 }
41436 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41437 MODE. */
41439 bool
41441 {
41442 /* Flags and only flags can only hold CCmode values. */
41457 {
41458 /* We implement the move patterns for all vector modes into and
41459 out of SSE registers, even when no operation instructions
41460 are available. */
41462 /* For AVX-512 we allow, regardless of regno:
41463 - XI mode
41464 - any of 512-bit wide vector mode
41465 - any scalar mode. */
41472 /* TODO check for QI/HI scalars. */
41473 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
41481 /* xmm16-xmm31 are only available for AVX-512. */
41485 /* OImode and AVX modes are available only when AVX is enabled. */
41492 }
41494 {
41495 /* We implement the move patterns for 3DNOW modes even in MMX mode,
41496 so if the register is available at all, then we can move data of
41497 the given mode into or out of it. */
41500 }
41503 {
41504 /* Take care for QImode values - they can be in non-QI regs,
41505 but then they do cause partial register stalls. */
41510 /* LRA checks if the hard register is OK for the given mode.
41511 QImode values can live in non-QI regs, so we allow all
41512 registers here. */
41516 }
41517 /* We handle both integer and floats in the general purpose registers. */
41524 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
41525 on to use that value in smaller contexts, this can easily force a
41526 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
41527 supporting DImode, allow it. */
41532 }
41534 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
41535 tieable integer mode. */
41537 static bool
41539 {
41541 {
41554 }
41555 }
41557 /* Return true if MODE1 is accessible in a register that can hold MODE2
41558 without copying. That is, all register classes that can hold MODE2
41559 can also hold MODE1. */
41561 bool
41563 {
41571 /* MODE2 being XFmode implies fp stack or general regs, which means we
41572 can tie any smaller floating point modes to it. Note that we do not
41573 tie this with TFmode. */
41577 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
41578 that we can tie it with SFmode. */
41582 /* If MODE2 is only appropriate for an SSE register, then tie with
41583 any other mode acceptable to SSE registers. */
41593 /* If MODE2 is appropriate for an MMX register, then tie
41594 with any other mode acceptable to MMX registers. */
41601 }
41603 /* Return the cost of moving between two registers of mode MODE. */
41605 static int
41607 {
41611 {
41643 }
41645 /* Return the cost of moving between two registers of mode MODE,
41646 assuming that the move will be in pieces of at most UNITS bytes. */
41648 }
41650 /* Compute a (partial) cost for rtx X. Return true if the complete
41651 cost has been computed, and false if subexpressions should be
41652 scanned. In either case, *TOTAL contains the cost result. */
41654 static bool
41657 {
41658 rtx mask;
41665 {
41669 {
41672 }
41684 && !(TARGET_64BIT
41689 else
41695 {
41698 }
41700 {
41710 }
41712 {
41715 {
41724 }
41725 }
41726 /* Fall back to (MEM (SYMBOL_REF)), since that's where
41727 it'll probably end up. Add a penalty for size. */
41734 /* The zero extensions is often completely free on x86_64, so make
41735 it as cheap as possible. */
41741 else
41753 {
41756 {
41759 }
41762 {
41765 }
41766 }
41767 /* FALLTHRU */
41774 {
41775 /* ??? Should be SSE vector operation cost. */
41776 /* At least for published AMD latencies, this really is the same
41777 as the latency for a simple fpu operation like fabs. */
41778 /* V*QImode is emulated with 1-11 insns. */
41780 {
41783 {
41784 /* For XOP we use vpshab, which requires a broadcast of the
41785 value to the variable shift insn. For constants this
41786 means a V16Q const in mem; even when we can perform the
41787 shift with one insn set the cost to prefer paddb. */
41789 {
41794 }
41796 }
41800 }
41801 else
41803 }
41805 {
41807 {
41810 else
41812 }
41813 else
41814 {
41817 else
41819 }
41820 }
41821 else
41822 {
41827 {
41828 /* Return the cost after shift-and truncation. */
41831 }
41832 else
41834 }
41838 {
41839 rtx sub;
41844 /* ??? SSE scalar/vector cost should be used here. */
41845 /* ??? Bald assumption that fma has the same cost as fmul. */
41849 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
41860 }
41864 {
41865 /* ??? SSE scalar cost should be used here. */
41868 }
41870 {
41873 }
41875 {
41876 /* ??? SSE vector cost should be used here. */
41879 }
41881 {
41882 /* V*QImode is emulated with 7-13 insns. */
41884 {
41891 }
41892 /* V*DImode is emulated with 5-8 insns. */
41894 {
41897 else
41899 }
41900 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
41901 insns, including two PMULUDQ. */
41904 else
41907 }
41908 else
41909 {
41914 {
41917 nbits++;
41918 }
41919 else
41920 /* This is arbitrary. */
41923 /* Compute costs correctly for widening multiplication. */
41927 {
41934 {
41938 else
41940 }
41944 }
41952 }
41959 /* ??? SSE cost should be used here. */
41964 /* ??? SSE vector cost should be used here. */
41966 else
41973 {
41978 {
41981 {
41989 }
41990 }
41993 {
41996 {
42002 }
42003 }
42005 {
42013 }
42014 }
42015 /* FALLTHRU */
42019 {
42020 /* ??? SSE cost should be used here. */
42023 }
42025 {
42028 }
42030 {
42031 /* ??? SSE vector cost should be used here. */
42034 }
42035 /* FALLTHRU */
42042 {
42049 }
42050 /* FALLTHRU */
42054 {
42055 /* ??? SSE cost should be used here. */
42058 }
42060 {
42063 }
42065 {
42066 /* ??? SSE vector cost should be used here. */
42069 }
42070 /* FALLTHRU */
42074 {
42075 /* ??? Should be SSE vector operation cost. */
42076 /* At least for published AMD latencies, this really is the same
42077 as the latency for a simple fpu operation like fabs. */
42079 }
42082 else
42091 {
42092 /* This kind of construct is implemented using test[bwl].
42093 Treat it as if we had an AND. */
42098 }
42108 /* ??? SSE cost should be used here. */
42113 /* ??? SSE vector cost should be used here. */
42119 /* ??? SSE cost should be used here. */
42124 /* ??? SSE vector cost should be used here. */
42136 /* ??? Assume all of these vector manipulation patterns are
42137 recognizable. In which case they all pretty much have the
42138 same cost. */
42143 /* This is masked instruction, assume the same cost,
42144 as nonmasked variant. */
42147 else
42153 }
42154 }
42156 #if TARGET_MACHO
42160 /* Given a symbol name and its associated stub, write out the
42161 definition of the stub. */
42163 void
42165 {
42170 /* For 64-bit we shouldn't get here. */
42173 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42190 else
42197 {
42199 }
42201 {
42202 /* PIC stub. */
42203 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42209 }
42210 else
42213 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42214 it needs no stub-binding-helper. */
42221 {
42224 }
42225 else
42230 /* N.B. Keep the correspondence of these
42231 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42232 old-pic/new-pic/non-pic stubs; altering this will break
42233 compatibility with existing dylibs. */
42235 {
42236 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42238 }
42239 else
42240 /* 16-byte -mdynamic-no-pic stub. */
42246 }
42249 /* Order the registers for register allocator. */
42251 void
42253 {
42257 /* First allocate the local general purpose registers. */
42262 /* Global general purpose registers. */
42267 /* x87 registers come first in case we are doing FP math
42268 using them. */
42273 /* SSE registers. */
42279 /* Extended REX SSE registers. */
42283 /* Mask register. */
42287 /* MPX bound registers. */
42291 /* x87 registers. */
42299 /* Initialize the rest of array as we do not allocate some registers
42300 at all. */
42303 }
42305 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42306 in struct attribute_spec handler. */
42307 static tree
42309 tree args,
42312 {
42317 {
42319 name);
42322 }
42324 {
42326 name);
42329 }
42331 {
42332 tree cst;
42336 {
42339 name);
42341 }
42344 {
42347 name);
42349 }
42352 }
42355 }
42357 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42358 struct attribute_spec.handler. */
42359 static tree
42362 {
42367 {
42369 name);
42372 }
42374 /* Can combine regparm with all attributes but fastcall. */
42376 {
42378 {
42380 }
42383 }
42385 {
42387 {
42389 }
42392 }
42395 }
42397 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42398 struct attribute_spec.handler. */
42399 static tree
42402 {
42405 {
42408 }
42409 else
42413 {
42415 name);
42417 }
42423 {
42425 name);
42427 }
42430 }
42432 static tree
42435 {
42437 {
42439 name);
42441 }
42443 }
42445 static bool
42447 {
42451 }
42453 /* Returns an expression indicating where the this parameter is
42454 located on entry to the FUNCTION. */
42456 static rtx
42458 {
42464 {
42469 else
42472 }
42477 {
42484 {
42489 }
42490 else
42491 {
42494 {
42500 }
42501 }
42503 }
42507 }
42509 /* Determine whether x86_output_mi_thunk can succeed. */
42511 static bool
42513 const_tree function)
42514 {
42515 /* 64-bit can handle anything. */
42519 /* For 32-bit, everything's fine if we have one free register. */
42523 /* Need a free register for vcall_offset. */
42527 /* Need a free register for GOT references. */
42531 /* Otherwise ok. */
42533 }
42535 /* Output the assembler code for a thunk function. THUNK_DECL is the
42536 declaration for the thunk function itself, FUNCTION is the decl for
42537 the target function. DELTA is an immediate constant offset to be
42538 added to THIS. If VCALL_OFFSET is nonzero, the word at
42539 *(*this + vcall_offset) should be added to THIS. */
42541 static void
42544 {
42552 else
42553 {
42559 else
42561 }
42565 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
42566 pull it in now and let DELTA benefit. */
42570 {
42571 /* Put the this parameter into %eax. */
42574 }
42575 else
42578 /* Adjust the this parameter by a fixed constant. */
42580 {
42585 {
42587 {
42591 }
42592 }
42595 }
42597 /* Adjust the this parameter by a value stored in the vtable. */
42599 {
42609 /* Adjust the this parameter. */
42613 {
42617 }
42624 vcall_mem));
42625 else
42627 }
42629 /* If necessary, drop THIS back to its stack slot. */
42635 {
42638 ;
42639 else
42640 {
42644 }
42645 }
42646 else
42647 {
42649 ;
42650 #if TARGET_MACHO
42652 {
42655 }
42657 else
42658 {
42666 }
42667 }
42669 /* Our sibling call patterns do not allow memories, because we have no
42670 predicate that can distinguish between frame and non-frame memory.
42671 For our purposes here, we can get away with (ab)using a jump pattern,
42672 because we're going to do no optimization. */
42674 {
42676 {
42682 }
42683 else
42685 }
42686 else
42687 {
42693 {
42699 }
42705 }
42708 /* Emit just enough of rest_of_compilation to get the insns emitted.
42709 Note that use_thunk calls assemble_start_function et al. */
42715 }
42717 static void
42719 {
42723 #if TARGET_MACHO
42725 #endif
42732 }
42734 int
42736 {
42737 machine_mode mode;
42748 }
42750 /* Print call to TARGET to FILE. */
42752 static void
42754 {
42757 else
42759 }
42761 /* Output assembler code to FILE to increment profiler label # LABELNO
42762 for profiling a function entry. */
42763 void
42765 {
42769 {
42770 #ifndef NO_PROFILE_COUNTERS
42772 #endif
42776 else
42778 }
42780 {
42781 #ifndef NO_PROFILE_COUNTERS
42784 #endif
42786 }
42787 else
42788 {
42789 #ifndef NO_PROFILE_COUNTERS
42792 #endif
42794 }
42797 {
42801 }
42802 }
42804 /* We don't have exact information about the insn sizes, but we may assume
42805 quite safely that we are informed about all 1 byte insns and memory
42806 address sizes. This is enough to eliminate unnecessary padding in
42807 99% of cases. */
42809 static int
42811 {
42817 /* Discard alignments we've emit and jump instructions. */
42822 /* Important case - calls are always 5 bytes.
42823 It is common to have many calls in the row. */
42832 /* For normal instructions we rely on get_attr_length being exact,
42833 with a few exceptions. */
42835 {
42839 {
42849 /* Otherwise trust get_attr_length. */
42851 }
42856 }
42859 else
42861 }
42863 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
42865 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
42866 window. */
42868 static void
42870 {
42875 /* Look for all minimal intervals of instructions containing 4 jumps.
42876 The intervals are bounded by START and INSN. NBYTES is the total
42877 size of instructions in the interval including INSN and not including
42878 START. When the NBYTES is smaller than 16 bytes, it is possible
42879 that the end of START and INSN ends up in the same 16byte page.
42881 The smallest offset in the page INSN can start is the case where START
42882 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
42883 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
42885 Don't consider asm goto as jump, while it can contain a jump, it doesn't
42886 have to, control transfer to label(s) can be performed through other
42887 means, and also we estimate minimum length of all asm stmts as 0. */
42889 {
42893 {
42899 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
42900 already in the current 16 byte page, because otherwise
42901 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
42902 bytes to reach 16 byte boundary. */
42910 {
42912 {
42917 else
42920 }
42921 }
42923 }
42932 njumps++;
42933 else
42937 {
42942 else
42945 }
42952 {
42959 }
42960 }
42961 }
42962 #endif
42964 /* AMD Athlon works faster
42965 when RET is not destination of conditional jump or directly preceded
42966 by other jump instruction. We avoid the penalty by inserting NOP just
42967 before the RET instructions in such cases. */
42968 static void
42970 {
42971 edge e;
42972 edge_iterator ei;
42975 {
42988 {
42989 edge e;
42990 edge_iterator ei;
42995 {
42998 }
42999 }
43001 {
43007 /* Empty functions get branch mispredict even when
43008 the jump destination is not visible to us. */
43011 }
43013 {
43016 }
43017 }
43018 }
43020 /* Count the minimum number of instructions in BB. Return 4 if the
43021 number of instructions >= 4. */
43023 static int
43025 {
43029 /* Count number of instructions in this block. Return 4 if the number
43030 of instructions >= 4. */
43032 {
43033 /* Only happen in exit blocks. */
43041 {
43042 insn_count++;
43045 }
43046 }
43049 }
43052 /* Count the minimum number of instructions in code path in BB.
43053 Return 4 if the number of instructions >= 4. */
43055 static int
43057 {
43058 edge e;
43059 edge_iterator ei;
43062 /* Only bother counting instructions along paths with no
43063 more than 2 basic blocks between entry and exit. Given
43064 that BB has an edge to exit, determine if a predecessor
43065 of BB has an edge from entry. If so, compute the number
43066 of instructions in the predecessor block. If there
43067 happen to be multiple such blocks, compute the minimum. */
43070 {
43071 edge prev_e;
43072 edge_iterator prev_ei;
43075 {
43078 }
43080 {
43082 {
43087 }
43088 }
43089 }
43095 }
43097 /* Pad short function to 4 instructions. */
43099 static void
43101 {
43102 edge e;
43103 edge_iterator ei;
43106 {
43109 {
43112 /* Pad short function. */
43114 {
43117 /* Find epilogue. */
43126 /* Two NOPs count as one instruction. */
43129 }
43130 }
43131 }
43132 }
43134 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43135 the epilogue, the Windows system unwinder will apply epilogue logic and
43136 produce incorrect offsets. This can be avoided by adding a nop between
43137 the last insn that can throw and the first insn of the epilogue. */
43139 static void
43141 {
43142 edge e;
43143 edge_iterator ei;
43146 {
43149 /* Find the beginning of the epilogue. */
43156 /* We only care about preceding insns that can throw. */
43161 /* Do not separate calls from their debug information. */
43167 else
43171 }
43172 }
43174 /* Implement machine specific optimizations. We implement padding of returns
43175 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43176 static void
43178 {
43179 /* We are freeing block_for_insn in the toplev to keep compatibility
43180 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43187 {
43192 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43195 #endif
43196 }
43197 }
43199 /* Return nonzero when QImode register that must be represented via REX prefix
43200 is used. */
43201 bool
43203 {
43211 }
43213 /* Return true when INSN mentions register that must be encoded using REX
43214 prefix. */
43215 bool
43217 {
43220 {
43225 }
43227 }
43229 /* If profitable, negate (without causing overflow) integer constant
43230 of mode MODE at location LOC. Return true in this case. */
43231 bool
43233 {
43234 HOST_WIDE_INT val;
43240 {
43242 /* DImode x86_64 constants must fit in 32 bits. */
43255 }
43257 /* Avoid overflows. */
43263 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43264 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43267 {
43270 }
43273 }
43275 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43276 optabs would emit if we didn't have TFmode patterns. */
43278 void
43280 {
43315 }
43316 \f
43322 /* Get a vector mode of the same size as the original but with elements
43323 twice as wide. This is only guaranteed to apply to integral vectors. */
43327 {
43328 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43333 }
43335 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43336 fill target with val via vec_duplicate. */
43338 static bool
43340 {
43343 rtx dup;
43345 /* First attempt to recognize VAL as-is. */
43349 {
43351 /* If that fails, force VAL into a register. */
43362 }
43364 }
43366 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43367 with all elements equal to VAR. Return true if successful. */
43369 static bool
43372 {
43376 {
43381 /* FALLTHRU */
43401 {
43402 rtx x;
43409 }
43422 {
43426 permute:
43434 /* Extend to SImode using a paradoxical SUBREG. */
43438 /* Insert the SImode value as low element of a V4SImode vector. */
43447 }
43458 widen:
43459 /* Replicate the value once into the next wider mode and recurse. */
43460 {
43462 rtx x;
43479 }
43485 else
43486 {
43495 }
43502 else
43503 {
43512 }
43517 }
43518 }
43520 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43521 whose ONE_VAR element is VAR, and other elements are zero. Return true
43522 if successful. */
43524 static bool
43527 {
43528 machine_mode vsimode;
43529 rtx new_target;
43534 {
43536 /* For SSE4.1, we normally use vector set. But if the second
43537 element is zero and inter-unit moves are OK, we use movq
43538 instead. */
43540 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
43562 /* Use ix86_expand_vector_set in 64bit mode only. */
43567 }
43570 {
43575 }
43578 {
43583 /* FALLTHRU */
43598 else
43605 {
43606 /* We need to shuffle the value to the correct position, so
43607 create a new pseudo to store the intermediate result. */
43609 /* With SSE2, we can use the integer shuffle insns. */
43611 {
43613 const1_rtx,
43620 }
43622 /* Otherwise convert the intermediate result to V4SFmode and
43623 use the SSE1 shuffle instructions. */
43625 {
43628 }
43629 else
43633 const1_rtx,
43642 }
43657 widen:
43661 /* Zero extend the variable element to SImode and recurse. */
43674 }
43675 }
43677 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43678 consisting of the values in VALS. It is known that all elements
43679 except ONE_VAR are constants. Return true if successful. */
43681 static bool
43684 {
43686 machine_mode wmode;
43694 {
43699 /* For the two element vectors, it's just as easy to use
43700 the general case. */
43704 /* Use ix86_expand_vector_set in 64bit mode only. */
43726 widen:
43727 /* There's no way to set one QImode entry easily. Combine
43728 the variable value with its adjacent constant value, and
43729 promote to an HImode set. */
43732 {
43737 }
43738 else
43739 {
43742 }
43756 }
43761 }
43763 /* A subroutine of ix86_expand_vector_init_general. Use vector
43764 concatenate to handle the most general case: all values variable,
43765 and none identical. */
43767 static void
43770 {
43773 rtvec v;
43777 {
43780 {
43825 }
43838 {
43853 }
43858 {
43877 }
43882 {
43895 }
43898 half:
43899 /* FIXME: We process inputs backward to help RA. PR 36222. */
43903 {
43908 }
43912 {
43916 {
43920 }
43923 {
43927 }
43930 }
43932 {
43935 {
43939 }
43942 }
43943 else
43949 }
43950 }
43952 /* A subroutine of ix86_expand_vector_init_general. Use vector
43953 interleave to handle the most general case: all values variable,
43954 and none identical. */
43956 static void
43959 {
43968 {
43989 }
43992 {
43993 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
43997 /* Insert the SImode value as low element of V4SImode vector. */
44001 op0),
44003 const1_rtx);
44006 /* Cast the V4SImode vector back to a vector in orignal mode. */
44010 /* Load even elements into the second position. */
44014 const1_rtx));
44016 /* Cast vector to FIRST_IMODE vector. */
44019 }
44021 /* Interleave low FIRST_IMODE vectors. */
44023 {
44027 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44030 }
44032 /* Interleave low SECOND_IMODE vectors. */
44034 {
44037 {
44042 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44043 vector. */
44046 }
44049 /* FALLTHRU */
44056 /* Cast the SECOND_IMODE vector back to a vector on original
44057 mode. */
44064 }
44065 }
44067 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44068 all values variable, and none identical. */
44070 static void
44073 {
44080 {
44085 /* FALLTHRU */
44113 half:
44137 quarter:
44166 /* FALLTHRU */
44172 /* Don't use ix86_expand_vector_init_interleave if we can't
44173 move from GPR to SSE register directly. */
44189 }
44191 {
44193 machine_mode inner_mode;
44203 {
44207 {
44213 else
44214 {
44219 }
44220 }
44223 }
44228 {
44234 }
44236 {
44242 }
44243 else
44245 }
44246 }
44248 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44249 instructions unless MMX_OK is true. */
44251 void
44253 {
44260 rtx x;
44263 {
44273 }
44275 /* Constants are best loaded from the constant pool. */
44277 {
44280 }
44282 /* If all values are identical, broadcast the value. */
44288 /* Values where only one field is non-constant are best loaded from
44289 the pool and overwritten via move later. */
44291 {
44295 one_var))
44300 }
44303 }
44305 void
44307 {
44310 machine_mode half_mode;
44312 rtx tmp;
44314 = {
44321 };
44323 = {
44330 };
44334 {
44338 {
44343 else
44347 }
44359 else
44365 {
44368 /* For the two element vectors, we implement a VEC_CONCAT with
44369 the extraction of the other element. */
44376 else
44381 }
44390 {
44396 /* tmp = target = A B C D */
44398 /* target = A A B B */
44400 /* target = X A B B */
44402 /* target = A X C D */
44409 /* tmp = target = A B C D */
44411 /* tmp = X B C D */
44413 /* target = A B X D */
44420 /* tmp = target = A B C D */
44422 /* tmp = X B C D */
44424 /* target = A B X D */
44432 }
44440 /* Element 0 handled by vec_merge below. */
44442 {
44445 }
44448 {
44449 /* With SSE2, use integer shuffles to swap element 0 and ELT,
44450 store into element 0, then shuffle them back. */
44467 }
44468 else
44469 {
44470 /* For SSE1, we have to reuse the V4SF code. */
44474 }
44527 half:
44528 /* Compute offset. */
44534 /* Extract the half. */
44538 /* Put val in tmp at elt. */
44541 /* Put it back. */
44547 {
44554 }
44555 else
44559 {
44566 }
44567 else
44571 {
44578 }
44579 else
44583 {
44590 }
44591 else
44595 {
44602 }
44603 else
44607 {
44614 }
44615 else
44620 }
44623 {
44627 }
44628 else
44629 {
44638 }
44639 }
44641 void
44643 {
44647 rtx tmp;
44650 {
44655 /* FALLTHRU */
44668 {
44688 }
44700 {
44702 {
44722 }
44726 }
44727 else
44728 {
44729 /* For SSE1, we have to reuse the V4SF code. */
44733 }
44749 {
44753 else
44757 }
44762 {
44766 else
44770 }
44775 {
44779 else
44783 }
44788 {
44792 else
44796 }
44801 {
44805 else
44809 }
44814 {
44818 else
44822 }
44827 {
44831 else
44835 }
44840 {
44844 else
44848 }
44855 else
44864 else
44873 else
44882 else
44888 /* ??? Could extract the appropriate HImode element and shift. */
44891 }
44894 {
44898 /* Let the rtl optimizers know about the zero extension performed. */
44900 {
44903 }
44906 }
44907 else
44908 {
44915 }
44916 }
44918 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
44919 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
44920 The upper bits of DEST are undefined, though they shouldn't cause
44921 exceptions (some bits from src or all zeros are ok). */
44923 static void
44925 {
44928 {
44932 else
44950 else
44957 else
44965 {
44970 const1_rtx);
44971 }
44972 else
44973 {
44977 }
44999 else
45021 }
45025 }
45027 /* Expand a vector reduction. FN is the binary pattern to reduce;
45028 DEST is the destination; IN is the input vector. */
45030 void
45032 {
45037 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45041 {
45044 }
45049 {
45054 else
45058 }
45059 }
45060 \f
45061 /* Target hook for scalar_mode_supported_p. */
45062 static bool
45064 {
45069 else
45071 }
45073 /* Implements target hook vector_mode_supported_p. */
45074 static bool
45076 {
45090 }
45092 /* Implement target hook libgcc_floating_mode_supported_p. */
45093 static bool
45095 {
45097 {
45104 #ifdef IX86_NO_LIBGCC_TFMODE
45106 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45108 #else
45110 #endif
45114 }
45115 }
45117 /* Target hook for c_mode_for_suffix. */
45118 static machine_mode
45120 {
45127 }
45129 /* Worker function for TARGET_MD_ASM_CLOBBERS.
45131 We do this in the new i386 backend to maintain source compatibility
45132 with the old cc0-based compiler. */
45134 static tree
45136 {
45138 clobbers);
45140 clobbers);
45142 }
45144 /* Implements target vector targetm.asm.encode_section_info. */
45146 static void ATTRIBUTE_UNUSED
45148 {
45153 }
45155 /* Worker function for REVERSE_CONDITION. */
45157 enum rtx_code
45159 {
45163 }
45165 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45166 to OPERANDS[0]. */
45170 {
45172 {
45175 {
45179 }
45183 }
45185 {
45189 else
45190 {
45191 /* There is no non-popping store to memory for XFmode.
45192 So if we need one, follow the store with a load. */
45195 else
45197 }
45198 }
45199 else
45201 }
45203 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45204 FP status register is set. */
45206 void
45208 {
45210 rtx temp;
45215 {
45220 }
45221 else
45222 {
45227 }
45231 pc_rtx);
45236 }
45238 /* Output code to perform a log1p XFmode calculation. */
45241 {
45247 rtx test;
45253 XFmode));
45267 }
45269 /* Emit code for round calculation. */
45271 {
45278 rtx insn;
45283 {
45295 }
45298 {
45319 }
45327 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
45329 /* scratch = fxam(op1) */
45332 UNSPEC_FXAM)));
45333 /* e1 = fabs(op1) */
45336 /* e2 = e1 + 0.5 */
45341 /* res = floor(e2) */
45343 {
45348 }
45349 else
45353 {
45356 {
45363 UNSPEC_TRUNC_NOOP)));
45364 }
45380 }
45382 /* flags = signbit(a) */
45385 /* if (flags) then res = -res */
45389 pc_rtx);
45400 }
45402 /* Output code to perform a Newton-Rhapson approximation of a single precision
45403 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
45406 {
45414 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
45418 /* x0 = rcp(b) estimate */
45422 UNSPEC_RCP14)));
45423 else
45426 UNSPEC_RCP)));
45428 /* e0 = x0 * b */
45432 /* e0 = x0 * e0 */
45436 /* e1 = x0 + x0 */
45440 /* x1 = e1 - e0 */
45444 /* res = a * x1 */
45447 }
45449 /* Output code to perform a Newton-Rhapson approximation of a
45450 single precision floating point [reciprocal] square root. */
45454 {
45456 REAL_VALUE_TYPE r;
45473 {
45476 /* There is no 512-bit rsqrt. There is however rsqrt14. */
45479 }
45481 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
45482 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
45486 /* x0 = rsqrt(a) estimate */
45489 unspec)));
45491 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
45493 {
45501 /* Handle masked compare. */
45503 {
45505 /* Imm value 0x4 corresponds to not-equal comparison. */
45508 }
45509 else
45510 {
45516 }
45517 }
45519 /* e0 = x0 * a */
45522 /* e1 = e0 * x0 */
45526 /* e2 = e1 - 3. */
45533 /* e3 = -.5 * x0 */
45536 else
45537 /* e3 = -.5 * e0 */
45540 /* ret = e2 * e3 */
45543 }
45545 #ifdef TARGET_SOLARIS
45546 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
45548 static void
45550 tree decl)
45551 {
45552 /* With Binutils 2.15, the "@unwind" marker must be specified on
45553 every occurrence of the ".eh_frame" section, not just the first
45554 one. */
45557 {
45561 }
45563 #ifndef USE_GAS
45565 {
45568 }
45569 #endif
45572 }
45575 /* Return the mangling of TYPE if it is an extended fundamental type. */
45579 {
45587 {
45589 /* __float128 is "g". */
45592 /* "long double" or __float80 is "e". */
45596 }
45597 }
45599 /* For 32-bit code we can save PIC register setup by using
45600 __stack_chk_fail_local hidden function instead of calling
45601 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
45602 register, so it is better to call __stack_chk_fail directly. */
45604 static tree ATTRIBUTE_UNUSED
45606 {
45607 return TARGET_64BIT
45610 }
45612 /* Select a format to encode pointers in exception handling data. CODE
45613 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
45614 true if the symbol may be affected by dynamic relocations.
45616 ??? All x86 object file formats are capable of representing this.
45617 After all, the relocation needed is the same as for the call insn.
45618 Whether or not a particular assembler allows us to enter such, I
45619 guess we'll have to see. */
45620 int
45622 {
45624 {
45631 }
45636 }
45637 \f
45638 /* Expand copysign from SIGN to the positive value ABS_VALUE
45639 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
45640 the sign-bit. */
45641 static void
45643 {
45647 {
45648 machine_mode vmode;
45654 else
45659 {
45660 /* We need to generate a scalar mode mask in this case. */
45665 }
45666 }
45667 else
45673 }
45675 /* Expand fabs (OP0) and return a new rtx that holds the result. The
45676 mask for masking out the sign-bit is stored in *SMASK, if that is
45677 non-null. */
45678 static rtx
45680 {
45689 else
45693 {
45694 /* We need to generate a scalar mode mask in this case. */
45699 }
45707 }
45709 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
45710 swapping the operands if SWAP_OPERANDS is true. The expanded
45711 code is a forward jump to a newly created label in case the
45712 comparison is true. The generated label rtx is returned. */
45716 {
45719 rtx tmp;
45735 }
45737 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
45738 using comparison code CODE. Operands are swapped for the comparison if
45739 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
45740 static rtx
45743 {
45756 }
45758 /* Generate and return a rtx of mode MODE for 2**n where n is the number
45759 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
45760 static rtx
45762 {
45763 REAL_VALUE_TYPE TWO52r;
45764 rtx TWO52;
45771 }
45773 /* Expand SSE sequence for computing lround from OP1 storing
45774 into OP0. */
45775 void
45777 {
45778 /* C code for the stuff we're doing below:
45779 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
45780 return (long)tmp;
45781 */
45785 rtx adj;
45787 /* load nextafter (0.5, 0.0) */
45792 /* adj = copysign (0.5, op1) */
45796 /* adj = op1 + adj */
45799 /* op0 = (imode)adj */
45801 }
45803 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
45804 into OPERAND0. */
45805 void
45807 {
45808 /* C code for the stuff we're doing below (for do_floor):
45809 xi = (long)op1;
45810 xi -= (double)xi > op1 ? 1 : 0;
45811 return xi;
45812 */
45818 /* reg = (long)op1 */
45822 /* freg = (double)reg */
45826 /* ireg = (freg > op1) ? ireg - 1 : ireg */
45837 }
45839 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
45840 result in OPERAND0. */
45841 void
45843 {
45844 /* C code for the stuff we're doing below:
45845 xa = fabs (operand1);
45846 if (!isless (xa, 2**52))
45847 return operand1;
45848 xa = xa + 2**52 - 2**52;
45849 return copysign (xa, operand1);
45850 */
45858 /* xa = abs (operand1) */
45861 /* if (!isless (xa, TWO52)) goto label; */
45874 }
45876 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
45877 into OPERAND0. */
45878 void
45880 {
45881 /* C code for the stuff we expand below.
45882 double xa = fabs (x), x2;
45883 if (!isless (xa, TWO52))
45884 return x;
45885 xa = xa + TWO52 - TWO52;
45886 x2 = copysign (xa, x);
45887 Compensate. Floor:
45888 if (x2 > x)
45889 x2 -= 1;
45890 Compensate. Ceil:
45891 if (x2 < x)
45892 x2 -= -1;
45893 return x2;
45894 */
45901 /* Temporary for holding the result, initialized to the input
45902 operand to ease control flow. */
45906 /* xa = abs (operand1) */
45909 /* if (!isless (xa, TWO52)) goto label; */
45912 /* xa = xa + TWO52 - TWO52; */
45916 /* xa = copysign (xa, operand1) */
45919 /* generate 1.0 or -1.0 */
45924 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
45928 /* We always need to subtract here to preserve signed zero. */
45937 }
45939 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
45940 into OPERAND0. */
45941 void
45943 {
45944 /* C code for the stuff we expand below.
45945 double xa = fabs (x), x2;
45946 if (!isless (xa, TWO52))
45947 return x;
45948 x2 = (double)(long)x;
45949 Compensate. Floor:
45950 if (x2 > x)
45951 x2 -= 1;
45952 Compensate. Ceil:
45953 if (x2 < x)
45954 x2 += 1;
45955 if (HONOR_SIGNED_ZEROS (mode))
45956 return copysign (x2, x);
45957 return x2;
45958 */
45965 /* Temporary for holding the result, initialized to the input
45966 operand to ease control flow. */
45970 /* xa = abs (operand1) */
45973 /* if (!isless (xa, TWO52)) goto label; */
45976 /* xa = (double)(long)x */
45981 /* generate 1.0 */
45984 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
45999 }
46001 /* Expand SSE sequence for computing round from OPERAND1 storing
46002 into OPERAND0. Sequence that works without relying on DImode truncation
46003 via cvttsd2siq that is only available on 64bit targets. */
46004 void
46006 {
46007 /* C code for the stuff we expand below.
46008 double xa = fabs (x), xa2, x2;
46009 if (!isless (xa, TWO52))
46010 return x;
46011 Using the absolute value and copying back sign makes
46012 -0.0 -> -0.0 correct.
46013 xa2 = xa + TWO52 - TWO52;
46014 Compensate.
46015 dxa = xa2 - xa;
46016 if (dxa <= -0.5)
46017 xa2 += 1;
46018 else if (dxa > 0.5)
46019 xa2 -= 1;
46020 x2 = copysign (xa2, x);
46021 return x2;
46022 */
46029 /* Temporary for holding the result, initialized to the input
46030 operand to ease control flow. */
46034 /* xa = abs (operand1) */
46037 /* if (!isless (xa, TWO52)) goto label; */
46040 /* xa2 = xa + TWO52 - TWO52; */
46044 /* dxa = xa2 - xa; */
46047 /* generate 0.5, 1.0 and -0.5 */
46053 /* Compensate. */
46055 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46060 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46066 /* res = copysign (xa2, operand1) */
46073 }
46075 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46076 into OPERAND0. */
46077 void
46079 {
46080 /* C code for SSE variant we expand below.
46081 double xa = fabs (x), x2;
46082 if (!isless (xa, TWO52))
46083 return x;
46084 x2 = (double)(long)x;
46085 if (HONOR_SIGNED_ZEROS (mode))
46086 return copysign (x2, x);
46087 return x2;
46088 */
46095 /* Temporary for holding the result, initialized to the input
46096 operand to ease control flow. */
46100 /* xa = abs (operand1) */
46103 /* if (!isless (xa, TWO52)) goto label; */
46106 /* x = (double)(long)x */
46118 }
46120 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46121 into OPERAND0. */
46122 void
46124 {
46129 /* C code for SSE variant we expand below.
46130 double xa = fabs (x), x2;
46131 if (!isless (xa, TWO52))
46132 return x;
46133 xa2 = xa + TWO52 - TWO52;
46134 Compensate:
46135 if (xa2 > xa)
46136 xa2 -= 1.0;
46137 x2 = copysign (xa2, x);
46138 return x2;
46139 */
46143 /* Temporary for holding the result, initialized to the input
46144 operand to ease control flow. */
46148 /* xa = abs (operand1) */
46151 /* if (!isless (xa, TWO52)) goto label; */
46154 /* res = xa + TWO52 - TWO52; */
46159 /* generate 1.0 */
46162 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46170 /* res = copysign (res, operand1) */
46177 }
46179 /* Expand SSE sequence for computing round from OPERAND1 storing
46180 into OPERAND0. */
46181 void
46183 {
46184 /* C code for the stuff we're doing below:
46185 double xa = fabs (x);
46186 if (!isless (xa, TWO52))
46187 return x;
46188 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46189 return copysign (xa, x);
46190 */
46197 /* Temporary for holding the result, initialized to the input
46198 operand to ease control flow. */
46206 /* load nextafter (0.5, 0.0) */
46211 /* xa = xa + 0.5 */
46215 /* xa = (double)(int64_t)xa */
46220 /* res = copysign (xa, operand1) */
46227 }
46229 /* Expand SSE sequence for computing round
46230 from OP1 storing into OP0 using sse4 round insn. */
46231 void
46233 {
46242 {
46253 }
46255 /* round (a) = trunc (a + copysign (0.5, a)) */
46257 /* load nextafter (0.5, 0.0) */
46263 /* e1 = copysign (0.5, op1) */
46267 /* e2 = op1 + e1 */
46270 /* res = trunc (e2) */
46275 }
46276 \f
46278 /* Table of valid machine attributes. */
46280 {
46281 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46282 affects_type_identity } */
46283 /* Stdcall attribute says callee is responsible for popping arguments
46284 if they are not variable. */
46287 /* Fastcall attribute says callee is responsible for popping arguments
46288 if they are not variable. */
46291 /* Thiscall attribute says callee is responsible for popping arguments
46292 if they are not variable. */
46295 /* Cdecl attribute says the callee is a normal C declaration */
46298 /* Regparm attribute specifies how many integer arguments are to be
46299 passed in registers. */
46302 /* Sseregparm attribute says we are using x86_64 calling conventions
46303 for FP arguments. */
46306 /* The transactional memory builtins are implicitly regparm or fastcall
46307 depending on the ABI. Override the generic do-nothing attribute that
46308 these builtins were declared with. */
46311 /* force_align_arg_pointer says this function realigns the stack at entry. */
46314 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46319 #endif
46324 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46325 SUBTARGET_ATTRIBUTE_TABLE,
46326 #endif
46327 /* ms_abi and sysv_abi calling convention function attributes. */
46334 /* End element. */
46336 };
46338 /* Implement targetm.vectorize.builtin_vectorization_cost. */
46339 static int
46342 {
46346 {
46391 }
46392 }
46394 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
46395 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
46396 insn every time. */
46400 /* Initialize vselect_insn. */
46402 static void
46404 {
46406 rtx x;
46417 }
46419 /* Construct (set target (vec_select op0 (parallel perm))) and
46420 return true if that's a valid instruction in the active ISA. */
46422 static bool
46425 {
46451 }
46453 /* Similar, but generate a vec_concat from op0 and op1 as well. */
46455 static bool
46459 {
46460 machine_mode v2mode;
46461 rtx x;
46476 }
46478 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46479 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
46481 static bool
46483 {
46493 ;
46495 ;
46497 ;
46499 ;
46500 else
46503 /* This is a blend, not a permute. Elements must stay in their
46504 respective lanes. */
46506 {
46510 }
46515 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
46516 decision should be extracted elsewhere, so that we only try that
46517 sequence once all budget==3 options have been tried. */
46524 {
46554 /* See if bytes move in pairs so we can use pblendw with
46555 an immediate argument, rather than pblendvb with a vector
46556 argument. */
46559 {
46560 use_pblendvb:
46564 finish_pblendvb:
46570 else
46575 }
46580 /* FALLTHRU */
46582 do_subreg:
46589 /* See if bytes move in pairs. If not, vpblendvb must be used. */
46593 /* See if bytes move in quadruplets. If yes, vpblendd
46594 with immediate can be used. */
46599 {
46600 /* See if bytes move the same in both lanes. If yes,
46601 vpblendw with immediate can be used. */
46606 /* Use vpblendw. */
46611 }
46613 /* Use vpblendd. */
46620 /* See if words move in pairs. If yes, vpblendd can be used. */
46625 {
46626 /* See if words move the same in both lanes. If not,
46627 vpblendvb must be used. */
46630 {
46631 /* Use vpblendvb. */
46641 }
46643 /* Use vpblendw. */
46647 }
46649 /* Use vpblendd. */
46656 /* Use vpblendd. */
46664 }
46666 /* This matches five different patterns with the different modes. */
46674 }
46676 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46677 in terms of the variable form of vpermilps.
46679 Note that we will have already failed the immediate input vpermilps,
46680 which requires that the high and low part shuffle be identical; the
46681 variable form doesn't require that. */
46683 static bool
46685 {
46692 /* We can only permute within the 128-bit lane. */
46694 {
46698 }
46704 {
46707 /* Within each 128-bit lane, the elements of op0 are numbered
46708 from 0 and the elements of op1 are numbered from 4. */
46715 }
46722 }
46724 /* Return true if permutation D can be performed as VMODE permutation
46725 instead. */
46727 static bool
46729 {
46744 else
46750 }
46752 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46753 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
46755 static bool
46757 {
46766 {
46768 {
46771 {
46775 /* Use vperm2i128 insn. The pattern uses
46776 V4DImode instead of V2TImode. */
46789 }
46791 }
46792 }
46793 else
46794 {
46796 {
46799 }
46801 {
46805 /* V4DImode should be already handled through
46806 expand_vselect by vpermq instruction. */
46813 {
46814 /* First see if vpermq can be used for
46815 V8SImode/V16HImode/V32QImode. */
46817 {
46825 {
46829 }
46831 }
46833 /* Next see if vpermd can be used. */
46836 }
46837 /* Or if vpermps can be used. */
46842 {
46843 /* vpshufb only works intra lanes, it is not
46844 possible to shuffle bytes in between the lanes. */
46848 }
46849 }
46851 {
46855 /* If vpermq didn't work, vpshufb won't work either. */
46863 {
46864 /* First see if vpermq can be used for
46865 V16SImode/V32HImode/V64QImode. */
46867 {
46875 {
46879 }
46881 }
46883 /* Next see if vpermd can be used. */
46886 }
46887 /* Or if vpermps can be used. */
46891 {
46892 /* vpshufb only works intra lanes, it is not
46893 possible to shuffle bytes in between the lanes. */
46897 }
46898 }
46899 else
46901 }
46912 else
46913 {
46921 else
46925 {
46929 }
46930 }
46941 {
46956 else
46958 }
46959 else
46960 {
46963 }
46968 }
46970 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
46971 in a single instruction. */
46973 static bool
46975 {
46979 /* Check plain VEC_SELECT first, because AVX has instructions that could
46980 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
46981 input where SEL+CONCAT may not. */
46983 {
46989 {
46995 }
46998 {
47002 }
47004 {
47005 /* Use vpbroadcast{b,w,d}. */
47008 {
47051 /* For other modes prefer other shuffles this function creates. */
47053 }
47055 {
47059 }
47060 }
47065 /* There are plenty of patterns in sse.md that are written for
47066 SEL+CONCAT and are not replicated for a single op. Perhaps
47067 that should be changed, to avoid the nastiness here. */
47069 /* Recognize interleave style patterns, which means incrementing
47070 every other permutation operand. */
47072 {
47075 }
47080 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47082 {
47084 {
47089 }
47094 }
47095 }
47097 /* Finally, try the fully general two operand permute. */
47102 /* Recognize interleave style patterns with reversed operands. */
47104 {
47106 {
47110 else
47113 }
47118 }
47120 /* Try the SSE4.1 blend variable merge instructions. */
47124 /* Try one of the AVX vpermil variable permutations. */
47128 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47129 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47133 /* Try the AVX2 vpalignr instruction. */
47137 /* Try the AVX512F vpermi2 instructions. */
47142 }
47144 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47145 in terms of a pair of pshuflw + pshufhw instructions. */
47147 static bool
47149 {
47157 /* The two permutations only operate in 64-bit lanes. */
47168 /* Emit the pshuflw. */
47175 /* Emit the pshufhw. */
47183 }
47185 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47186 the permutation using the SSSE3 palignr instruction. This succeeds
47187 when all of the elements in PERM fit within one vector and we merely
47188 need to shift them down so that a single vector permutation has a
47189 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47190 the vpalignr instruction itself can perform the requested permutation. */
47192 static bool
47194 {
47201 /* Even with AVX, palignr only operates on 128-bit vectors,
47202 in AVX2 palignr operates on both 128-bit lanes. */
47212 {
47216 {
47219 }
47228 }
47231 {
47240 }
47242 /* Given that we have SSSE3, we know we'll be able to implement the
47243 single operand permutation after the palignr with pshufb for
47244 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47245 first. */
47251 {
47256 }
47260 {
47266 else
47271 }
47277 /* For AVX2, test whether we can permute the result in one instruction. */
47279 {
47284 }
47288 {
47292 }
47293 else
47294 {
47299 shift));
47300 }
47304 /* Test for the degenerate case where the alignment by itself
47305 produces the desired permutation. */
47307 {
47310 }
47316 }
47318 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
47319 the permutation using the SSE4_1 pblendv instruction. Potentially
47320 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
47322 static bool
47324 {
47330 /* Use the same checks as in expand_vec_perm_blend. */
47334 ;
47336 ;
47338 ;
47339 else
47342 /* Figure out where permutation elements stay not in their
47343 respective lanes. */
47345 {
47349 }
47350 /* We can pblend the part where elements stay not in their
47351 respective lanes only when these elements are all in one
47352 half of a permutation.
47353 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
47354 lanes, but both 8 and 9 >= 8
47355 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
47356 respective lanes and 8 >= 8, but 2 not. */
47362 /* First we apply one operand permutation to the part where
47363 elements stay not in their respective lanes. */
47367 else
47377 else
47382 /* Next we put permuted elements into their positions. */
47386 else
47396 }
47400 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47401 a two vector permutation into a single vector permutation by using
47402 an interleave operation to merge the vectors. */
47404 static bool
47406 {
47415 {
47418 }
47420 {
47423 /* For 32-byte modes allow even d->one_operand_p.
47424 The lack of cross-lane shuffling in some instructions
47425 might prevent a single insn shuffle. */
47428 /* If expand_vec_perm_interleave3 can expand this into
47429 a 3 insn sequence, give up and let it be expanded as
47430 3 insn sequence. While that is one insn longer,
47431 it doesn't need a memory operand and in the common
47432 case that both interleave low and high permutations
47433 with the same operands are adjacent needs 4 insns
47434 for both after CSE. */
47437 }
47438 else
47441 /* Examine from whence the elements come. */
47450 {
47453 /* Split the two input vectors into 4 halves. */
47459 /* If the elements from the low halves use interleave low, and similarly
47460 for interleave high. If the elements are from mis-matched halves, we
47461 can use shufps for V4SF/V4SI or do a DImode shuffle. */
47463 {
47464 /* punpckl* */
47466 {
47471 }
47474 }
47476 {
47477 /* punpckh* */
47479 {
47484 }
47487 }
47489 {
47490 /* shufps */
47492 {
47497 }
47499 {
47500 /* shufpd */
47505 }
47506 }
47508 {
47509 /* shufps */
47511 {
47516 }
47518 {
47519 /* shufpd */
47524 }
47525 }
47526 else
47528 }
47529 else
47530 {
47535 /* Split the two input vectors into 8 quarters. */
47541 {
47544 }
47547 {
47551 }
47553 {
47556 }
47559 {
47561 {
47562 /* Attempt to increase the likelihood that dfinal
47563 shuffle will be intra-lane. */
47567 }
47569 /* vperm2f128 or vperm2i128. */
47571 {
47576 }
47581 {
47585 {
47588 }
47589 }
47590 }
47595 {
47596 /* vpunpckl* */
47598 {
47607 }
47608 }
47611 {
47612 /* vpunpckh* */
47614 {
47623 }
47624 }
47625 else
47627 }
47629 /* Use the remapping array set up above to move the elements from their
47630 swizzled locations into their final destinations. */
47633 {
47636 /* If same_halves is true, both halves of the remapped vector are the
47637 same. Avoid cross-lane accesses if possible. */
47639 {
47642 }
47643 else
47645 }
47647 {
47650 }
47654 /* Test if the final remap can be done with a single insn. For V4SFmode or
47655 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
47668 {
47671 }
47678 }
47680 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47681 a single vector cross-lane permutation into vpermq followed
47682 by any of the single insn permutations. */
47684 static bool
47686 {
47700 {
47703 }
47706 {
47711 }
47724 {
47731 }
47738 {
47743 ;
47746 else
47748 }
47757 }
47759 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
47760 a vector permutation using two instructions, vperm2f128 resp.
47761 vperm2i128 followed by any single in-lane permutation. */
47763 static bool
47765 {
47779 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
47780 immediate. For perm < 16 the second permutation uses
47781 d->op0 as first operand, for perm >= 16 it uses d->op1
47782 as first operand. The second operand is the result of
47783 vperm2[fi]128. */
47785 {
47786 /* Ignore permutations which do not move anything cross-lane. */
47788 {
47789 /* The second shuffle for e.g. V4DFmode has
47790 0123 and ABCD operands.
47791 Ignore AB23, as 23 is already in the second lane
47792 of the first operand. */
47794 /* And 01CD, as 01 is in the first lane of the first
47795 operand. */
47797 /* And 4567, as then the vperm2[fi]128 doesn't change
47798 anything on the original 4567 second operand. */
47800 }
47801 else
47802 {
47803 /* The second shuffle for e.g. V4DFmode has
47804 4567 and ABCD operands.
47805 Ignore AB67, as 67 is already in the second lane
47806 of the first operand. */
47808 /* And 45CD, as 45 is in the first lane of the first
47809 operand. */
47811 /* And 0123, as then the vperm2[fi]128 doesn't change
47812 anything on the original 0123 first operand. */
47814 }
47817 {
47823 else
47825 }
47828 {
47832 }
47833 else
47837 {
47841 /* Found a usable second shuffle. dfirst will be
47842 vperm2f128 on d->op0 and d->op1. */
47854 /* And dsecond is some single insn shuffle, taking
47855 d->op0 and result of vperm2f128 (if perm < 16) or
47856 d->op1 and result of vperm2f128 (otherwise). */
47865 }
47867 /* For one operand, the only useful vperm2f128 permutation is 0x01
47868 aka lanes swap. */
47871 }
47874 }
47876 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47877 a two vector permutation using 2 intra-lane interleave insns
47878 and cross-lane shuffle for 32-byte vectors. */
47880 static bool
47882 {
47889 ;
47891 ;
47892 else
47907 {
47911 else
47917 else
47923 else
47929 else
47935 else
47941 else
47946 }
47950 }
47952 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
47953 a single vector permutation using a single intra-lane vector
47954 permutation, vperm2f128 swapping the lanes and vblend* insn blending
47955 the non-swapped and swapped vectors together. */
47957 static bool
47959 {
47967 || TARGET_AVX2
47976 {
47983 }
48018 }
48020 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48021 permutation using two vperm2f128, followed by a vshufpd insn blending
48022 the two vectors together. */
48024 static bool
48026 {
48069 }
48071 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48072 permutation with two pshufb insns and an ior. We should have already
48073 failed all two instruction sequences. */
48075 static bool
48077 {
48091 /* Generate two permutation masks. If the required element is within
48092 the given vector it is shuffled into the proper lane. If the required
48093 element is in the other vector, force a zero into the lane by setting
48094 bit 7 in the permutation mask. */
48097 {
48104 {
48107 }
48108 }
48132 }
48134 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48135 with two vpshufb insns, vpermq and vpor. We should have already failed
48136 all two or three instruction sequences. */
48138 static bool
48140 {
48155 /* Generate two permutation masks. If the required element is within
48156 the same lane, it is shuffled in. If the required element from the
48157 other lane, force a zero by setting bit 7 in the permutation mask.
48158 In the other mask the mask has non-negative elements if element
48159 is requested from the other lane, but also moved to the other lane,
48160 so that the result of vpshufb can have the two V2TImode halves
48161 swapped. */
48164 {
48169 {
48172 }
48173 }
48182 /* Swap the 128-byte lanes of h into hp. */
48186 const1_rtx));
48203 }
48205 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48206 and extract-odd permutations of two V32QImode and V16QImode operand
48207 with two vpshufb insns, vpor and vpermq. We should have already
48208 failed all two or three instruction sequences. */
48210 static bool
48212 {
48231 /* Generate two permutation masks. In the first permutation mask
48232 the first quarter will contain indexes for the first half
48233 of the op0, the second quarter will contain bit 7 set, third quarter
48234 will contain indexes for the second half of the op0 and the
48235 last quarter bit 7 set. In the second permutation mask
48236 the first quarter will contain bit 7 set, the second quarter
48237 indexes for the first half of the op1, the third quarter bit 7 set
48238 and last quarter indexes for the second half of the op1.
48239 I.e. the first mask e.g. for V32QImode extract even will be:
48240 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48241 (all values masked with 0xf except for -128) and second mask
48242 for extract even will be
48243 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48246 {
48252 {
48255 }
48256 }
48275 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48283 }
48285 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
48286 and extract-odd permutations. */
48288 static bool
48290 {
48294 {
48301 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48305 /* Now an unpck[lh]pd will produce the result required. */
48308 else
48314 {
48323 /* Shuffle within the 128-bit lanes to produce:
48324 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
48328 /* Shuffle the lanes around to produce:
48329 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
48333 /* Shuffle within the 128-bit lanes to produce:
48334 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
48337 /* Shuffle within the 128-bit lanes to produce:
48338 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
48341 /* Shuffle the lanes around to produce:
48342 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
48345 }
48352 /* These are always directly implementable by expand_vec_perm_1. */
48358 else
48359 {
48362 /* We need 2*log2(N)-1 operations to achieve odd/even
48363 with interleave. */
48372 else
48375 }
48381 else
48382 {
48396 else
48399 }
48408 {
48413 else
48418 {
48423 }
48425 }
48433 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48437 /* Now an vpunpck[lh]qdq will produce the result required. */
48440 else
48447 {
48452 else
48457 {
48462 }
48464 }
48475 /* Shuffle the lanes around into
48476 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
48484 /* Swap the 2nd and 3rd position in each lane into
48485 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
48491 /* Now an vpunpck[lh]qdq will produce
48492 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
48496 else
48505 }
48508 }
48510 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48511 extract-even and extract-odd permutations. */
48513 static bool
48515 {
48527 }
48529 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
48530 permutations. We assume that expand_vec_perm_1 has already failed. */
48532 static bool
48534 {
48542 {
48545 /* These are special-cased in sse.md so that we can optionally
48546 use the vbroadcast instruction. They expand to two insns
48547 if the input happens to be in a register. */
48554 /* These are always implementable using standard shuffle patterns. */
48559 /* These can be implemented via interleave. We save one insn by
48560 stopping once we have promoted to V4SImode and then use pshufd. */
48563 do
48564 {
48565 rtx dest;
48571 {
48575 }
48582 }
48597 /* For AVX2 broadcasts of the first element vpbroadcast* or
48598 vpermq should be used by expand_vec_perm_1. */
48604 }
48605 }
48607 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48608 broadcast permutations. */
48610 static bool
48612 {
48624 }
48626 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
48627 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
48628 all the shorter instruction sequences. */
48630 static bool
48632 {
48648 /* Generate 4 permutation masks. If the required element is within
48649 the same lane, it is shuffled in. If the required element from the
48650 other lane, force a zero by setting bit 7 in the permutation mask.
48651 In the other mask the mask has non-negative elements if element
48652 is requested from the other lane, but also moved to the other lane,
48653 so that the result of vpshufb can have the two V2TImode halves
48654 swapped. */
48657 {
48662 }
48668 {
48676 }
48679 {
48681 {
48684 }
48691 }
48693 /* Swap the 128-byte lanes of h[X]. */
48695 {
48701 const1_rtx));
48703 }
48706 {
48708 {
48711 }
48717 }
48720 {
48722 {
48726 }
48729 }
48739 }
48741 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
48742 With all of the interface bits taken care of, perform the expansion
48743 in D and return true on success. */
48745 static bool
48747 {
48748 /* Try a single instruction expansion. */
48752 /* Try sequences of two instructions. */
48775 /* Try sequences of three instructions. */
48789 /* Try sequences of four instructions. */
48797 /* ??? Look for narrow permutations whose element orderings would
48798 allow the promotion to a wider mode. */
48800 /* ??? Look for sequences of interleave or a wider permute that place
48801 the data into the correct lanes for a half-vector shuffle like
48802 pshuf[lh]w or vpermilps. */
48804 /* ??? Look for sequences of interleave that produce the desired results.
48805 The combinatorics of punpck[lh] get pretty ugly... */
48810 /* Even longer sequences. */
48815 }
48817 /* If a permutation only uses one operand, make it clear. Returns true
48818 if the permutation references both operands. */
48820 static bool
48822 {
48830 {
48836 {
48839 }
48840 /* The elements of PERM do not suggest that only the first operand
48841 is used, but both operands are identical. Allow easier matching
48842 of the permutation by folding the permutation into the single
48843 input vector. */
48844 /* FALLTHRU */
48855 }
48858 }
48860 bool
48862 {
48867 rtx sel;
48884 {
48889 }
48896 /* If the selector says both arguments are needed, but the operands are the
48897 same, the above tried to expand with one_operand_p and flattened selector.
48898 If that didn't work, retry without one_operand_p; we succeeded with that
48899 during testing. */
48901 {
48905 }
48908 }
48910 /* Implement targetm.vectorize.vec_perm_const_ok. */
48912 static bool
48915 {
48924 /* Given sufficient ISA support we can just return true here
48925 for selected vector modes. */
48927 {
48933 /* All implementable with a single vpermi2 insn. */
48938 /* All implementable with a single vpermi2 insn. */
48946 /* All implementable with a single vpermi2 insn. */
48951 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
48956 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
48963 /* All implementable with a single vpperm insn. */
48966 /* All implementable with 2 pshufb + 1 ior. */
48972 /* All implementable with shufpd or unpck[lh]pd. */
48976 }
48978 /* Extract the values from the vector CST into the permutation
48979 array in D. */
48982 {
48986 }
48988 /* For all elements from second vector, fold the elements to first. */
48993 /* Check whether the mask can be applied to the vector type. */
48996 /* Implementable with shufps or pshufd. */
49000 /* Otherwise we have to go through the motions and see if we can
49001 figure out how to generate the requested permutation. */
49012 }
49014 void
49016 {
49031 /* We'll either be able to implement the permutation directly... */
49035 /* ... or we use the special-case patterns. */
49037 }
49039 static void
49041 {
49056 {
49059 }
49061 /* Note that for AVX this isn't one instruction. */
49064 }
49067 /* Expand a vector operation CODE for a V*QImode in terms of the
49068 same operation on V*HImode. */
49070 void
49072 {
49074 machine_mode himode;
49084 {
49102 }
49106 {
49108 /* Unpack data such that we've got a source byte in each low byte of
49109 each word. We don't care what goes into the high byte of each word.
49110 Rather than trying to get zero in there, most convenient is to let
49111 it be a copy of the low byte. */
49116 /* FALLTHRU */
49128 /* FALLTHRU */
49138 }
49140 /* Perform the operation. */
49147 /* Merge the data back into the right place. */
49157 {
49158 /* For SSE2, we used an full interleave, so the desired
49159 results are in the even elements. */
49162 }
49163 else
49164 {
49165 /* For AVX, the interleave used above was not cross-lane. So the
49166 extraction is evens but with the second and third quarter swapped.
49167 Happily, that is even one insn shorter than even extraction. */
49170 }
49177 }
49179 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
49180 if op is CONST_VECTOR with all odd elements equal to their
49181 preceding element. */
49183 static bool
49185 {
49195 }
49197 void
49200 {
49203 rtx x;
49211 /* We only play even/odd games with vectors of SImode. */
49214 /* If we're looking for the odd results, shift those members down to
49215 the even slots. For some cpus this is faster than a PSHUFD. */
49217 {
49218 /* For XOP use vpmacsdqh, but only for smult, as it is only
49219 signed. */
49221 {
49225 }
49236 }
49239 {
49242 else
49244 }
49246 {
49249 else
49251 }
49256 else
49257 {
49260 /* The easiest way to implement this without PMULDQ is to go through
49261 the motions as if we are performing a full 64-bit multiply. With
49262 the exception that we need to do less shuffling of the elements. */
49264 /* Compute the sign-extension, aka highparts, of the two operands. */
49270 /* Multiply LO(A) * HI(B), and vice-versa. */
49276 /* Multiply LO(A) * LO(B). */
49280 /* Combine and shift the highparts into place. */
49285 /* Combine high and low parts. */
49288 }
49290 }
49292 void
49295 {
49301 {
49306 {
49307 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
49308 shuffle the elements once so that all elements are in the right
49309 place for immediate use: { A C B D }. */
49314 }
49315 else
49316 {
49317 /* Put the elements into place for the multiply. */
49321 }
49326 /* Shuffle the elements between the lanes. After this we
49327 have { A B E F | C D G H } for each operand. */
49337 /* Shuffle the elements within the lanes. After this we
49338 have { A A B B | C C D D } or { E E F F | G G H H }. */
49379 }
49380 }
49382 void
49384 {
49394 /* Move the results in element 2 down to element 1; we don't care
49395 what goes in elements 2 and 3. Then we can merge the parts
49396 back together with an interleave.
49398 Note that two other sequences were tried:
49399 (1) Use interleaves at the start instead of psrldq, which allows
49400 us to use a single shufps to merge things back at the end.
49401 (2) Use shufps here to combine the two vectors, then pshufd to
49402 put the elements in the correct order.
49403 In both cases the cost of the reformatting stall was too high
49404 and the overall sequence slower. */
49415 }
49417 void
49419 {
49430 {
49431 /* op1: A,B,C,D, op2: E,F,G,H */
49440 /* t1: B,A,D,C */
49447 /* t2: (B*E),(A*F),(D*G),(C*H) */
49450 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
49453 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
49456 /* Multiply lower parts and add all */
49463 }
49464 else
49465 {
49466 machine_mode nmode;
49470 {
49473 }
49475 {
49478 }
49480 {
49483 }
49484 else
49488 /* Multiply low parts. */
49492 /* Shift input vectors right 32 bits so we can multiply high parts. */
49497 /* Multiply high parts by low parts. */
49503 /* Combine and shift the highparts back. */
49507 /* Combine high and low parts. */
49509 }
49513 }
49515 /* Return 1 if control tansfer instruction INSN
49516 should be encoded with bnd prefix.
49517 If insn is NULL then return 1 when control
49518 transfer instructions should be prefixed with
49519 bnd by default for current function. */
49521 bool
49523 {
49524 /* For call insns check special flag. */
49526 {
49530 }
49532 /* All other insns are prefixed only if function is instrumented. */
49534 }
49536 /* Calculate integer abs() using only SSE2 instructions. */
49538 void
49540 {
49545 {
49546 /* For 32-bit signed integer X, the best way to calculate the absolute
49547 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
49559 /* For 16-bit signed integer X, the best way to calculate the absolute
49560 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
49568 /* For 8-bit signed integer X, the best way to calculate the absolute
49569 value of X is min ((unsigned char) X, (unsigned char) (-X)),
49570 as SSE2 provides the PMINUB insn. */
49580 }
49584 }
49586 /* Expand an insert into a vector register through pinsr insn.
49587 Return true if successful. */
49589 bool
49591 {
49599 {
49602 }
49608 {
49613 {
49620 {
49652 }
49666 }
49670 }
49671 }
49672 \f
49673 /* This function returns the calling abi specific va_list type node.
49674 It returns the FNDECL specific va_list type. */
49676 static tree
49678 {
49685 else
49687 }
49689 /* Returns the canonical va_list type specified by TYPE. If there
49690 is no valid TYPE provided, it return NULL_TREE. */
49692 static tree
49694 {
49697 /* Resolve references and pointers to va_list type. */
49706 {
49711 {
49712 /* If va_list is an array type, the argument may have decayed
49713 to a pointer type, e.g. by being passed to another function.
49714 In that case, unwrap both types so that we can compare the
49715 underlying records. */
49718 {
49721 }
49722 }
49729 {
49730 /* If va_list is an array type, the argument may have decayed
49731 to a pointer type, e.g. by being passed to another function.
49732 In that case, unwrap both types so that we can compare the
49733 underlying records. */
49736 {
49739 }
49740 }
49747 {
49748 /* If va_list is an array type, the argument may have decayed
49749 to a pointer type, e.g. by being passed to another function.
49750 In that case, unwrap both types so that we can compare the
49751 underlying records. */
49754 {
49757 }
49758 }
49762 }
49764 }
49766 /* Iterate through the target-specific builtin types for va_list.
49767 IDX denotes the iterator, *PTREE is set to the result type of
49768 the va_list builtin, and *PNAME to its internal type.
49769 Returns zero if there is no element for this index, otherwise
49770 IDX should be increased upon the next call.
49771 Note, do not iterate a base builtin's name like __builtin_va_list.
49772 Used from c_common_nodes_and_builtins. */
49774 static int
49776 {
49778 {
49780 {
49793 }
49794 }
49797 }
49799 #undef TARGET_SCHED_DISPATCH
49800 #define TARGET_SCHED_DISPATCH has_dispatch
49801 #undef TARGET_SCHED_DISPATCH_DO
49802 #define TARGET_SCHED_DISPATCH_DO do_dispatch
49803 #undef TARGET_SCHED_REASSOCIATION_WIDTH
49804 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
49805 #undef TARGET_SCHED_REORDER
49806 #define TARGET_SCHED_REORDER ix86_sched_reorder
49807 #undef TARGET_SCHED_ADJUST_PRIORITY
49808 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
49809 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
49810 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
49811 ix86_dependencies_evaluation_hook
49813 /* The size of the dispatch window is the total number of bytes of
49814 object code allowed in a window. */
49815 #define DISPATCH_WINDOW_SIZE 16
49817 /* Number of dispatch windows considered for scheduling. */
49818 #define MAX_DISPATCH_WINDOWS 3
49820 /* Maximum number of instructions in a window. */
49821 #define MAX_INSN 4
49823 /* Maximum number of immediate operands in a window. */
49824 #define MAX_IMM 4
49826 /* Maximum number of immediate bits allowed in a window. */
49827 #define MAX_IMM_SIZE 128
49829 /* Maximum number of 32 bit immediates allowed in a window. */
49830 #define MAX_IMM_32 4
49832 /* Maximum number of 64 bit immediates allowed in a window. */
49833 #define MAX_IMM_64 2
49835 /* Maximum total of loads or prefetches allowed in a window. */
49836 #define MAX_LOAD 2
49838 /* Maximum total of stores allowed in a window. */
49839 #define MAX_STORE 1
49841 #undef BIG
49842 #define BIG 100
49845 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
49848 disp_load,
49849 disp_store,
49850 disp_load_store,
49851 disp_prefetch,
49852 disp_imm,
49853 disp_imm_32,
49854 disp_imm_64,
49855 disp_branch,
49856 disp_cmp,
49857 disp_jcc,
49858 disp_last
49859 };
49861 /* Number of allowable groups in a dispatch window. It is an array
49862 indexed by dispatch_group enum. 100 is used as a big number,
49863 because the number of these kind of operations does not have any
49864 effect in dispatch window, but we need them for other reasons in
49865 the table. */
49868 };
49874 };
49876 /* Instruction path. */
49882 last_path
49883 };
49885 /* sched_insn_info defines a window to the instructions scheduled in
49886 the basic block. It contains a pointer to the insn_info table and
49887 the instruction scheduled.
49889 Windows are allocated for each basic block and are linked
49890 together. */
49892 rtx insn;
49899 /* Linked list of dispatch windows. This is a two way list of
49900 dispatch windows of a basic block. It contains information about
49901 the number of uops in the window and the total number of
49902 instructions and of bytes in the object code for this dispatch
49903 window. */
49921 /* Immediate valuse used in an insn. */
49923 {
49932 /* Get dispatch group of insn. */
49934 static enum dispatch_group
49936 {
49952 }
49954 /* Return true if insn is a compare instruction. */
49956 static bool
49958 {
49966 }
49968 /* Return true if a dispatch violation encountered. */
49970 static bool
49972 {
49976 }
49978 /* Return true if insn is a branch instruction. */
49980 static bool
49982 {
49984 }
49986 /* Return true if insn is a prefetch instruction. */
49988 static bool
49990 {
49992 }
49994 /* This function initializes a dispatch window and the list container holding a
49995 pointer to the window. */
49997 static void
49999 {
50005 else
50023 {
50029 }
50031 }
50033 /* This function allocates and initializes a dispatch window and the
50034 list container holding a pointer to the window. */
50038 {
50043 }
50045 /* This routine initializes the dispatch scheduling information. It
50046 initiates building dispatch scheduler tables and constructs the
50047 first dispatch window. */
50049 static void
50051 {
50052 /* Allocate a dispatch list and a window. */
50057 }
50059 /* This function returns true if a branch is detected. End of a basic block
50060 does not have to be a branch, but here we assume only branches end a
50061 window. */
50063 static bool
50065 {
50067 }
50069 /* This function is called when the end of a window processing is reached. */
50071 static void
50073 {
50076 {
50081 }
50083 }
50085 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50086 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50087 for 48 bytes of instructions. Note that these windows are not dispatch
50088 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50092 {
50094 {
50099 }
50105 }
50107 /* Compute number of immediate operands of an instruction. */
50109 static void
50111 {
50118 {
50125 else
50136 {
50139 }
50144 }
50145 }
50147 /* Return total size of immediate operands of an instruction along with number
50148 of corresponding immediate-operands. It initializes its parameters to zero
50149 befor calling FIND_CONSTANT.
50150 INSN is the input instruction. IMM is the total of immediates.
50151 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
50152 bit immediates. */
50154 static int
50156 {
50164 }
50166 /* This function indicates if an operand of an instruction is an
50167 immediate. */
50169 static bool
50171 {
50180 }
50182 /* Return single or double path for instructions. */
50184 static enum insn_path
50186 {
50196 }
50198 /* Return insn dispatch group. */
50200 static enum dispatch_group
50202 {
50220 }
50222 /* Count number of GROUP restricted instructions in a dispatch
50223 window WINDOW_LIST. */
50225 static int
50227 {
50238 {
50257 }
50270 }
50272 /* This function returns true if insn satisfies dispatch rules on the
50273 last window scheduled. */
50275 static bool
50277 {
50285 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
50286 instructions should be given the lowest priority in the
50287 scheduling process in Haifa scheduler to make sure they will be
50288 scheduled in the same dispatch window as the reference to them. */
50292 /* Check nonrestricted. */
50296 /* Get last dispatch window. */
50301 {
50306 /* Window 1 is full. Go for next window. */
50308 }
50315 /* See if it fits in the first window. */
50317 {
50318 /* The first widow should have only single and double path
50319 uops. */
50325 }
50327 }
50329 /* Add an instruction INSN with NUM_UOPS micro-operations to the
50330 dispatch window WINDOW_LIST. */
50332 static void
50334 {
50352 /* Initialize window with new instruction. */
50373 {
50376 }
50377 }
50379 /* Adds a scheduled instruction, INSN, to the current dispatch window.
50380 If the total bytes of instructions or the number of instructions in
50381 the window exceed allowable, it allocates a new window. */
50383 static void
50385 {
50408 /* Get the last dispatch window. */
50416 else
50419 /* If current window is full, get a new window.
50420 Window number zero is full, if MAX_INSN uops are scheduled in it.
50421 Window number one is full, if window zero's bytes plus window
50422 one's bytes is 32, or if the bytes of the new instruction added
50423 to the total makes it greater than 48, or it has already MAX_INSN
50424 instructions in it. */
50433 {
50436 }
50439 {
50443 {
50446 }
50447 }
50449 {
50454 {
50457 }
50460 }
50461 else
50465 {
50466 /* End of basic block is reached do end-basic-block process. */
50469 }
50470 }
50472 /* Print the dispatch window, WINDOW_NUM, to FILE. */
50474 DEBUG_FUNCTION static void
50476 {
50482 else
50496 {
50499 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
50505 }
50506 }
50508 /* Print to stdout a dispatch window. */
50510 DEBUG_FUNCTION void
50512 {
50514 }
50516 /* Print INSN dispatch information to FILE. */
50518 DEBUG_FUNCTION static void
50520 {
50543 }
50545 /* Print to STDERR the status of the ready list with respect to
50546 dispatch windows. */
50548 DEBUG_FUNCTION void
50550 {
50558 }
50560 /* This routine is the driver of the dispatch scheduler. */
50562 static void
50564 {
50569 }
50571 /* Return TRUE if Dispatch Scheduling is supported. */
50573 static bool
50575 {
50579 {
50595 }
50598 }
50600 /* Implementation of reassociation_width target hook used by
50601 reassoc phase to identify parallelism level in reassociated
50602 tree. Statements tree_code is passed in OPC. Arguments type
50603 is passed in MODE.
50605 Currently parallel reassociation is enabled for Atom
50606 processors only and we set reassociation width to be 2
50607 because Atom may issue up to 2 instructions per cycle.
50609 Return value should be fixed if parallel reassociation is
50610 enabled for other processors. */
50612 static int
50614 {
50617 /* Vector part. */
50619 {
50622 else
50624 }
50626 /* Scalar part. */
50633 }
50635 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
50636 place emms and femms instructions. */
50638 static machine_mode
50640 {
50645 {
50664 else
50676 /* FALLTHRU */
50680 }
50681 }
50683 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
50684 vectors. If AVX512F is enabled then try vectorizing with 512bit,
50685 256bit and 128bit vectors. */
50687 static unsigned int
50689 {
50692 }
50694 \f
50696 /* Return class of registers which could be used for pseudo of MODE
50697 and of class RCLASS for spilling instead of memory. Return NO_REGS
50698 if it is not possible or non-profitable. */
50699 static reg_class_t
50701 {
50707 }
50709 /* Implement targetm.vectorize.init_cost. */
50713 {
50717 }
50719 /* Implement targetm.vectorize.add_stmt_cost. */
50721 static unsigned
50725 {
50732 /* Statements in an inner loop relative to the loop being
50733 vectorized are weighted more heavily. The value here is
50734 arbitrary and could potentially be improved with analysis. */
50740 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
50741 for Silvermont as it has out of order integer pipeline and can execute
50742 2 scalar instruction per tick, but has in order SIMD pipeline. */
50745 {
50749 }
50754 }
50756 /* Implement targetm.vectorize.finish_cost. */
50758 static void
50761 {
50766 }
50768 /* Implement targetm.vectorize.destroy_cost_data. */
50770 static void
50772 {
50774 }
50776 /* Validate target specific memory model bits in VAL. */
50778 static unsigned HOST_WIDE_INT
50780 {
50787 {
50791 }
50794 {
50798 }
50800 {
50804 }
50806 }
50808 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
50809 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
50810 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
50811 or number of vecsize_mangle variants that should be emitted. */
50813 static int
50817 {
50824 {
50828 }
50833 {
50840 /* case SCmode: */
50841 /* case DCmode: */
50847 }
50849 tree t;
50853 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
50855 {
50862 /* case SCmode: */
50863 /* case DCmode: */
50869 }
50872 {
50873 /* Parse here processor clause. If not present, default to 'b'. */
50875 }
50877 {
50878 /* If the function isn't exported, we can pick up just one ISA
50879 for the clones. */
50884 else
50887 }
50888 else
50889 {
50892 }
50894 {
50907 }
50909 {
50912 else
50917 }
50919 }
50921 /* Add target attribute to SIMD clone NODE if needed. */
50923 static void
50925 {
50929 {
50944 }
50954 }
50956 /* If SIMD clone NODE can't be used in a vectorized loop
50957 in current function, return -1, otherwise return a badness of using it
50958 (0 if it is most desirable from vecsize_mangle point of view, 1
50959 slightly less desirable, etc.). */
50961 static int
50963 {
50965 {
50983 }
50984 }
50986 /* This function adjusts the unroll factor based on
50987 the hardware capabilities. For ex, bdver3 has
50988 a loop buffer which makes unrolling of smaller
50989 loops less important. This function decides the
50990 unroll factor using number of memory references
50991 (value 32 is used) as a heuristic. */
50993 static unsigned
50995 {
51004 /* Count the number of memory references within the loop body.
51005 This value determines the unrolling factor for bdver3 and bdver4
51006 architectures. */
51015 {
51020 else
51022 }
51029 }
51032 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51034 static bool
51036 {
51037 /* For x87 floating point with standard excess precision handling,
51038 there is no adddf3 pattern (since x87 floating point only has
51039 XFmode operations) so the default hook implementation gets this
51040 wrong. */
51042 }
51044 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51046 static void
51048 {
51053 {
51068 hold_fnclex);
51081 }
51083 {
51092 mxcsr_orig_var,
51102 ldmxcsr_hold_call);
51105 else
51110 ldmxcsr_clear_call);
51111 else
51115 stxmcsr_update_call);
51117 {
51123 exceptions_assign);
51124 }
51125 else
51130 ldmxcsr_update_call);
51131 }
51132 tree atomic_feraiseexcept
51137 atomic_feraiseexcept_call);
51138 }
51140 /* Return mode to be used for bounds or VOIDmode
51141 if bounds are not supported. */
51143 static enum machine_mode
51145 {
51146 /* Do not support pointer checker if MPX
51147 is not enabled. */
51149 {
51154 }
51157 }
51159 /* Return constant used to statically initialize constant bounds.
51161 This function is used to create special bound values. For now
51162 only INIT bounds and NONE bounds are expected. More special
51163 values may be added later. */
51165 static tree
51167 {
51173 /* This function is supposed to be used to create INIT and
51174 NONE bounds only. */
51179 }
51181 /* Generate a list of statements STMTS to initialize pointer bounds
51182 variable VAR with bounds LB and UB. Return the number of generated
51183 statements. */
51185 static int
51187 {
51205 }
51207 /* Initialize the GCC target structure. */
51208 #undef TARGET_RETURN_IN_MEMORY
51209 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
51211 #undef TARGET_LEGITIMIZE_ADDRESS
51212 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
51214 #undef TARGET_ATTRIBUTE_TABLE
51215 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
51216 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
51217 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
51218 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51219 # undef TARGET_MERGE_DECL_ATTRIBUTES
51220 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
51221 #endif
51223 #undef TARGET_COMP_TYPE_ATTRIBUTES
51224 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
51226 #undef TARGET_INIT_BUILTINS
51227 #define TARGET_INIT_BUILTINS ix86_init_builtins
51228 #undef TARGET_BUILTIN_DECL
51229 #define TARGET_BUILTIN_DECL ix86_builtin_decl
51230 #undef TARGET_EXPAND_BUILTIN
51231 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
51233 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
51234 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
51235 ix86_builtin_vectorized_function
51237 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
51238 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
51240 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
51241 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
51243 #undef TARGET_VECTORIZE_BUILTIN_GATHER
51244 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
51246 #undef TARGET_BUILTIN_RECIPROCAL
51247 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
51249 #undef TARGET_ASM_FUNCTION_EPILOGUE
51250 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
51252 #undef TARGET_ENCODE_SECTION_INFO
51253 #ifndef SUBTARGET_ENCODE_SECTION_INFO
51254 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
51255 #else
51256 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
51257 #endif
51259 #undef TARGET_ASM_OPEN_PAREN
51261 #undef TARGET_ASM_CLOSE_PAREN
51264 #undef TARGET_ASM_BYTE_OP
51265 #define TARGET_ASM_BYTE_OP ASM_BYTE
51267 #undef TARGET_ASM_ALIGNED_HI_OP
51268 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
51269 #undef TARGET_ASM_ALIGNED_SI_OP
51270 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
51271 #ifdef ASM_QUAD
51272 #undef TARGET_ASM_ALIGNED_DI_OP
51273 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
51274 #endif
51276 #undef TARGET_PROFILE_BEFORE_PROLOGUE
51277 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
51279 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
51280 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
51282 #undef TARGET_ASM_UNALIGNED_HI_OP
51283 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
51284 #undef TARGET_ASM_UNALIGNED_SI_OP
51285 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
51286 #undef TARGET_ASM_UNALIGNED_DI_OP
51287 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
51289 #undef TARGET_PRINT_OPERAND
51290 #define TARGET_PRINT_OPERAND ix86_print_operand
51291 #undef TARGET_PRINT_OPERAND_ADDRESS
51292 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
51293 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
51294 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
51295 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
51296 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
51298 #undef TARGET_SCHED_INIT_GLOBAL
51299 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
51300 #undef TARGET_SCHED_ADJUST_COST
51301 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
51302 #undef TARGET_SCHED_ISSUE_RATE
51303 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
51304 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
51305 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
51306 ia32_multipass_dfa_lookahead
51307 #undef TARGET_SCHED_MACRO_FUSION_P
51308 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
51309 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
51310 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
51312 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
51313 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
51315 #undef TARGET_MEMMODEL_CHECK
51316 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
51318 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
51319 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
51321 #ifdef HAVE_AS_TLS
51322 #undef TARGET_HAVE_TLS
51323 #define TARGET_HAVE_TLS true
51324 #endif
51325 #undef TARGET_CANNOT_FORCE_CONST_MEM
51326 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
51327 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
51328 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
51330 #undef TARGET_DELEGITIMIZE_ADDRESS
51331 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
51333 #undef TARGET_MS_BITFIELD_LAYOUT_P
51334 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
51336 #if TARGET_MACHO
51337 #undef TARGET_BINDS_LOCAL_P
51338 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
51339 #endif
51340 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51341 #undef TARGET_BINDS_LOCAL_P
51342 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
51343 #endif
51345 #undef TARGET_ASM_OUTPUT_MI_THUNK
51346 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
51347 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
51348 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
51350 #undef TARGET_ASM_FILE_START
51351 #define TARGET_ASM_FILE_START x86_file_start
51353 #undef TARGET_OPTION_OVERRIDE
51354 #define TARGET_OPTION_OVERRIDE ix86_option_override
51356 #undef TARGET_REGISTER_MOVE_COST
51357 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
51358 #undef TARGET_MEMORY_MOVE_COST
51359 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
51360 #undef TARGET_RTX_COSTS
51361 #define TARGET_RTX_COSTS ix86_rtx_costs
51362 #undef TARGET_ADDRESS_COST
51363 #define TARGET_ADDRESS_COST ix86_address_cost
51365 #undef TARGET_FIXED_CONDITION_CODE_REGS
51366 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
51367 #undef TARGET_CC_MODES_COMPATIBLE
51368 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
51370 #undef TARGET_MACHINE_DEPENDENT_REORG
51371 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
51373 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
51374 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
51376 #undef TARGET_BUILD_BUILTIN_VA_LIST
51377 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
51379 #undef TARGET_FOLD_BUILTIN
51380 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
51382 #undef TARGET_COMPARE_VERSION_PRIORITY
51383 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
51385 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
51386 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
51387 ix86_generate_version_dispatcher_body
51389 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
51390 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
51391 ix86_get_function_versions_dispatcher
51393 #undef TARGET_ENUM_VA_LIST_P
51394 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
51396 #undef TARGET_FN_ABI_VA_LIST
51397 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
51399 #undef TARGET_CANONICAL_VA_LIST_TYPE
51400 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
51402 #undef TARGET_EXPAND_BUILTIN_VA_START
51403 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
51405 #undef TARGET_MD_ASM_CLOBBERS
51406 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
51408 #undef TARGET_PROMOTE_PROTOTYPES
51409 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
51410 #undef TARGET_SETUP_INCOMING_VARARGS
51411 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
51412 #undef TARGET_MUST_PASS_IN_STACK
51413 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
51414 #undef TARGET_FUNCTION_ARG_ADVANCE
51415 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
51416 #undef TARGET_FUNCTION_ARG
51417 #define TARGET_FUNCTION_ARG ix86_function_arg
51418 #undef TARGET_INIT_PIC_REG
51419 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
51420 #undef TARGET_USE_PSEUDO_PIC_REG
51421 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
51422 #undef TARGET_FUNCTION_ARG_BOUNDARY
51423 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
51424 #undef TARGET_PASS_BY_REFERENCE
51425 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
51426 #undef TARGET_INTERNAL_ARG_POINTER
51427 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
51428 #undef TARGET_UPDATE_STACK_BOUNDARY
51429 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
51430 #undef TARGET_GET_DRAP_RTX
51431 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
51432 #undef TARGET_STRICT_ARGUMENT_NAMING
51433 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
51434 #undef TARGET_STATIC_CHAIN
51435 #define TARGET_STATIC_CHAIN ix86_static_chain
51436 #undef TARGET_TRAMPOLINE_INIT
51437 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
51438 #undef TARGET_RETURN_POPS_ARGS
51439 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
51441 #undef TARGET_LEGITIMATE_COMBINED_INSN
51442 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
51444 #undef TARGET_ASAN_SHADOW_OFFSET
51445 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
51447 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
51448 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
51450 #undef TARGET_SCALAR_MODE_SUPPORTED_P
51451 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
51453 #undef TARGET_VECTOR_MODE_SUPPORTED_P
51454 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
51456 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
51457 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
51458 ix86_libgcc_floating_mode_supported_p
51460 #undef TARGET_C_MODE_FOR_SUFFIX
51461 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
51463 #ifdef HAVE_AS_TLS
51464 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
51465 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
51466 #endif
51468 #ifdef SUBTARGET_INSERT_ATTRIBUTES
51469 #undef TARGET_INSERT_ATTRIBUTES
51470 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
51471 #endif
51473 #undef TARGET_MANGLE_TYPE
51474 #define TARGET_MANGLE_TYPE ix86_mangle_type
51476 #if !TARGET_MACHO
51477 #undef TARGET_STACK_PROTECT_FAIL
51478 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
51479 #endif
51481 #undef TARGET_FUNCTION_VALUE
51482 #define TARGET_FUNCTION_VALUE ix86_function_value
51484 #undef TARGET_FUNCTION_VALUE_REGNO_P
51485 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
51487 #undef TARGET_PROMOTE_FUNCTION_MODE
51488 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
51490 #undef TARGET_MEMBER_TYPE_FORCES_BLK
51491 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
51493 #undef TARGET_INSTANTIATE_DECLS
51494 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
51496 #undef TARGET_SECONDARY_RELOAD
51497 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
51499 #undef TARGET_CLASS_MAX_NREGS
51500 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
51502 #undef TARGET_PREFERRED_RELOAD_CLASS
51503 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
51504 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
51505 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
51506 #undef TARGET_CLASS_LIKELY_SPILLED_P
51507 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
51509 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
51510 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
51511 ix86_builtin_vectorization_cost
51512 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
51513 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
51514 ix86_vectorize_vec_perm_const_ok
51515 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
51516 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
51517 ix86_preferred_simd_mode
51518 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
51519 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
51520 ix86_autovectorize_vector_sizes
51521 #undef TARGET_VECTORIZE_INIT_COST
51522 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
51523 #undef TARGET_VECTORIZE_ADD_STMT_COST
51524 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
51525 #undef TARGET_VECTORIZE_FINISH_COST
51526 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
51527 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
51528 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
51530 #undef TARGET_SET_CURRENT_FUNCTION
51531 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
51533 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
51534 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
51536 #undef TARGET_OPTION_SAVE
51537 #define TARGET_OPTION_SAVE ix86_function_specific_save
51539 #undef TARGET_OPTION_RESTORE
51540 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
51542 #undef TARGET_OPTION_PRINT
51543 #define TARGET_OPTION_PRINT ix86_function_specific_print
51545 #undef TARGET_OPTION_FUNCTION_VERSIONS
51546 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
51548 #undef TARGET_CAN_INLINE_P
51549 #define TARGET_CAN_INLINE_P ix86_can_inline_p
51551 #undef TARGET_EXPAND_TO_RTL_HOOK
51552 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
51554 #undef TARGET_LEGITIMATE_ADDRESS_P
51555 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
51557 #undef TARGET_LRA_P
51558 #define TARGET_LRA_P hook_bool_void_true
51560 #undef TARGET_REGISTER_PRIORITY
51561 #define TARGET_REGISTER_PRIORITY ix86_register_priority
51563 #undef TARGET_REGISTER_USAGE_LEVELING_P
51564 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
51566 #undef TARGET_LEGITIMATE_CONSTANT_P
51567 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
51569 #undef TARGET_FRAME_POINTER_REQUIRED
51570 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
51572 #undef TARGET_CAN_ELIMINATE
51573 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
51575 #undef TARGET_EXTRA_LIVE_ON_ENTRY
51576 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
51578 #undef TARGET_ASM_CODE_END
51579 #define TARGET_ASM_CODE_END ix86_code_end
51581 #undef TARGET_CONDITIONAL_REGISTER_USAGE
51582 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
51584 #if TARGET_MACHO
51585 #undef TARGET_INIT_LIBFUNCS
51586 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
51587 #endif
51589 #undef TARGET_LOOP_UNROLL_ADJUST
51590 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
51592 #undef TARGET_SPILL_CLASS
51593 #define TARGET_SPILL_CLASS ix86_spill_class
51595 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
51596 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
51597 ix86_simd_clone_compute_vecsize_and_simdlen
51599 #undef TARGET_SIMD_CLONE_ADJUST
51600 #define TARGET_SIMD_CLONE_ADJUST \
51601 ix86_simd_clone_adjust
51603 #undef TARGET_SIMD_CLONE_USABLE
51604 #define TARGET_SIMD_CLONE_USABLE \
51605 ix86_simd_clone_usable
51607 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
51608 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
51609 ix86_float_exceptions_rounding_supported_p
51611 #undef TARGET_MODE_EMIT
51612 #define TARGET_MODE_EMIT ix86_emit_mode_set
51614 #undef TARGET_MODE_NEEDED
51615 #define TARGET_MODE_NEEDED ix86_mode_needed
51617 #undef TARGET_MODE_AFTER
51618 #define TARGET_MODE_AFTER ix86_mode_after
51620 #undef TARGET_MODE_ENTRY
51621 #define TARGET_MODE_ENTRY ix86_mode_entry
51623 #undef TARGET_MODE_EXIT
51624 #define TARGET_MODE_EXIT ix86_mode_exit
51626 #undef TARGET_MODE_PRIORITY
51627 #define TARGET_MODE_PRIORITY ix86_mode_priority
51629 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
51630 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
51632 #undef TARGET_LOAD_BOUNDS_FOR_ARG
51633 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
51635 #undef TARGET_STORE_BOUNDS_FOR_ARG
51636 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
51638 #undef TARGET_LOAD_RETURNED_BOUNDS
51639 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
51641 #undef TARGET_STORE_RETURNED_BOUNDS
51642 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
51644 #undef TARGET_CHKP_BOUND_MODE
51645 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
51647 #undef TARGET_BUILTIN_CHKP_FUNCTION
51648 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
51650 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
51651 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
51653 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
51654 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
51656 #undef TARGET_CHKP_INITIALIZE_BOUNDS
51657 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
51659 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
51660 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
51663 \f