| blob | 143f9d03722609d9679b7b8cdbb5dde7073b0d77 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2018 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
24 #define INCLUDE_STRING
75 /* This file should be included last. */
78 /* Defined for convenience. */
79 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
81 /* Classifies an address.
83 ADDRESS_REG_IMM
84 A simple base register plus immediate offset.
86 ADDRESS_REG_WB
87 A base register indexed by immediate offset with writeback.
89 ADDRESS_REG_REG
90 A base register indexed by (optionally scaled) register.
92 ADDRESS_REG_UXTW
93 A base register indexed by (optionally scaled) zero-extended register.
95 ADDRESS_REG_SXTW
96 A base register indexed by (optionally scaled) sign-extended register.
98 ADDRESS_LO_SUM
99 A LO_SUM rtx with a base register and "LO12" symbol relocation.
101 ADDRESS_SYMBOLIC:
102 A constant symbolic address, in pc-relative literal pool. */
105 ADDRESS_REG_IMM,
106 ADDRESS_REG_WB,
107 ADDRESS_REG_REG,
108 ADDRESS_REG_UXTW,
109 ADDRESS_REG_SXTW,
110 ADDRESS_LO_SUM,
111 ADDRESS_SYMBOLIC
112 };
116 rtx base;
117 rtx offset;
118 poly_int64 const_offset;
121 };
123 /* Information about a legitimate vector immediate operand. */
124 struct simd_immediate_info
125 {
136 /* The mode of the elements. */
137 scalar_mode elt_mode;
139 /* The value of each element if all elements are the same, or the
140 first value if the constant is a series. */
141 rtx value;
143 /* The value of the step if the constant is a series, null otherwise. */
144 rtx step;
146 /* The instruction to use to move the immediate into a vector. */
147 insn_type insn;
149 /* The kind of shift modifier to use, and the number of bits to shift.
150 This is (LSL, 0) if no shift is needed. */
151 modifier_type modifier;
153 };
155 /* Construct a floating-point immediate in which each element has mode
156 ELT_MODE_IN and value VALUE_IN. */
157 inline simd_immediate_info
161 {}
163 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
164 and value VALUE_IN. The other parameters are as for the structure
165 fields. */
166 inline simd_immediate_info
173 {}
175 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
176 and where element I is equal to VALUE_IN + I * STEP_IN. */
177 inline simd_immediate_info
181 {}
183 /* The current code model. */
186 /* The number of 64-bit elements in an SVE vector. */
187 poly_uint16 aarch64_sve_vg;
189 #ifdef HAVE_AS_TLS
190 #undef TARGET_HAVE_TLS
191 #define TARGET_HAVE_TLS 1
192 #endif
196 const_tree,
205 const_tree type,
211 /* Major revision number of the ARM Architecture implemented by the target. */
214 /* The processor for which instructions should be scheduled. */
217 /* Mask to specify which instruction scheduling options should be used. */
220 /* Global flag for PC relative loads. */
223 /* Global flag for whether frame pointer is enabled. */
226 /* Support for command line parsing of boolean flags in the tuning
227 structures. */
228 struct aarch64_flag_desc
229 {
232 };
234 #define AARCH64_FUSION_PAIR(name, internal_name) \
235 { name, AARCH64_FUSE_##internal_name },
237 {
242 };
244 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
245 { name, AARCH64_EXTRA_TUNE_##internal_name },
247 {
252 };
254 /* Tuning parameters. */
257 {
258 {
263 },
270 };
273 {
274 {
279 },
286 };
289 {
290 {
295 },
302 };
305 {
306 {
311 },
318 };
321 {
322 {
327 },
334 };
337 {
339 /* Avoid the use of slow int<->fp moves for spilling by setting
340 their cost higher than memmov_cost. */
344 };
347 {
349 /* Avoid the use of slow int<->fp moves for spilling by setting
350 their cost higher than memmov_cost. */
354 };
357 {
359 /* Avoid the use of slow int<->fp moves for spilling by setting
360 their cost higher than memmov_cost. */
364 };
367 {
369 /* Avoid the use of slow int<->fp moves for spilling by setting
370 their cost higher than memmov_cost (actual, 4 and 9). */
374 };
377 {
382 };
385 {
387 /* Avoid the use of slow int<->fp moves for spilling by setting
388 their cost higher than memmov_cost. */
392 };
395 {
397 /* Avoid the use of int<->fp moves for spilling. */
401 };
404 {
406 /* Avoid the use of int<->fp moves for spilling. */
410 };
412 /* Generic costs for vector insn classes. */
414 {
430 };
432 /* ThunderX costs for vector insn classes. */
434 {
450 };
452 /* Generic costs for vector insn classes. */
454 {
470 };
473 {
489 };
491 /* Generic costs for vector insn classes. */
493 {
509 };
511 /* Costs for vector insn classes for Vulcan. */
513 {
529 };
531 /* Generic costs for branch instructions. */
533 {
536 };
538 /* Generic approximation modes. */
540 {
543 AARCH64_APPROX_NONE /* recip_sqrt */
544 };
546 /* Approximation modes for Exynos M1. */
548 {
551 AARCH64_APPROX_ALL /* recip_sqrt */
552 };
554 /* Approximation modes for X-Gene 1. */
556 {
559 AARCH64_APPROX_ALL /* recip_sqrt */
560 };
562 /* Generic prefetch settings (which disable prefetch). */
564 {
572 };
575 {
583 };
586 {
594 };
597 {
605 };
608 {
616 };
619 {
627 };
630 {
651 &generic_prefetch_tune
652 };
655 {
677 &generic_prefetch_tune
678 };
681 {
703 &generic_prefetch_tune
704 };
707 {
729 &generic_prefetch_tune
730 };
733 {
755 &generic_prefetch_tune
756 };
759 {
781 &generic_prefetch_tune
782 };
787 {
808 &exynosm1_prefetch_tune
809 };
812 {
833 &thunderxt88_prefetch_tune
834 };
837 {
857 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
859 &thunderx_prefetch_tune
860 };
863 {
884 &generic_prefetch_tune
885 };
888 {
910 &qdf24xx_prefetch_tune
911 };
913 /* Tuning structure for the Qualcomm Saphira core. Default to falkor values
914 for now. */
916 {
938 &generic_prefetch_tune
939 };
942 {
964 &thunderx2t99_prefetch_tune
965 };
967 /* Support for fine-grained override of the tuning structures. */
968 struct aarch64_tuning_override_function
969 {
972 };
977 static const struct aarch64_tuning_override_function
978 aarch64_tuning_override_functions[] =
979 {
983 };
985 /* A processor implementing AArch64. */
986 struct processor
987 {
995 };
997 /* Architectures implementing AArch64. */
999 {
1000 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
1001 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
1004 };
1006 /* Processor cores implementing AArch64. */
1008 {
1009 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
1010 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
1011 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
1012 FLAGS, &COSTS##_tunings},
1017 };
1020 /* Target specification. These are populated by the -march, -mtune, -mcpu
1021 handling code or by target attributes. */
1026 /* The current tuning set. */
1029 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
1031 /* An ISA extension in the co-processor and main instruction set space. */
1032 struct aarch64_option_extension
1033 {
1037 };
1040 {
1044 }
1045 aarch64_cc;
1047 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
1049 /* The condition codes of the processor, and the inverse function. */
1051 {
1054 };
1056 /* Generate code to enable conditional branches in functions over 1 MiB. */
1060 {
1077 }
1079 void
1081 {
1086 else
1089 else
1093 else
1096 }
1098 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
1099 The register allocator chooses POINTER_AND_FP_REGS if FP_REGS and
1100 GENERAL_REGS have the same cost - even if POINTER_AND_FP_REGS has a much
1101 higher cost. POINTER_AND_FP_REGS is also used if the cost of both FP_REGS
1102 and GENERAL_REGS is lower than the memory cost (in this case the best class
1103 is the lowest cost one). Using POINTER_AND_FP_REGS irrespectively of its
1104 cost results in bad allocations with many redundant int<->FP moves which
1105 are expensive on various cores.
1106 To avoid this we don't allow POINTER_AND_FP_REGS as the allocno class, but
1107 force a decision between FP_REGS and GENERAL_REGS. We use the allocno class
1108 if it isn't POINTER_AND_FP_REGS. Similarly, use the best class if it isn't
1109 POINTER_AND_FP_REGS. Otherwise set the allocno class depending on the mode.
1110 The result of this is that it is no longer inefficient to have a higher
1111 memory move cost than the register move cost.
1112 */
1114 static reg_class_t
1116 reg_class_t best_class)
1117 {
1118 machine_mode mode;
1130 }
1132 static unsigned int
1134 {
1138 }
1140 /* Return the reassociation width of treeop OPC with mode MODE. */
1141 static int
1143 {
1148 /* Avoid reassociating floating point addition so we emit more FMAs. */
1152 }
1154 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1155 unsigned
1157 {
1169 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1170 equivalent DWARF register. */
1172 }
1174 /* Return true if MODE is any of the Advanced SIMD structure modes. */
1175 static bool
1177 {
1180 }
1182 /* Return true if MODE is an SVE predicate mode. */
1183 static bool
1185 {
1191 }
1193 /* Three mutually-exclusive flags describing a vector or predicate type. */
1197 /* Can be used in combination with VEC_ADVSIMD or VEC_SVE_DATA to indicate
1198 a structure of 2, 3 or 4 vectors. */
1200 /* Useful combinations of the above. */
1204 /* Return a set of flags describing the vector properties of mode MODE.
1205 Ignore modes that are not supported by the current target. */
1206 static unsigned int
1208 {
1224 {
1226 {
1233 }
1235 /* This includes V1DF but not V1DI (which doesn't exist). */
1240 }
1243 }
1245 /* Return true if MODE is any of the data vector modes, including
1246 structure modes. */
1247 static bool
1249 {
1251 }
1253 /* Return true if MODE is an SVE data vector mode; either a single vector
1254 or a structure of vectors. */
1255 static bool
1257 {
1259 }
1261 /* Implement target hook TARGET_ARRAY_MODE. */
1262 static opt_machine_mode
1264 {
1271 }
1273 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1274 static bool
1277 {
1285 }
1287 /* Return the SVE predicate mode to use for elements that have
1288 ELEM_NBYTES bytes, if such a mode exists. */
1290 opt_machine_mode
1292 {
1294 {
1303 }
1305 }
1307 /* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
1309 static opt_machine_mode
1311 {
1313 {
1315 machine_mode pred_mode;
1318 }
1321 }
1323 /* Implement TARGET_HARD_REGNO_NREGS. */
1325 static unsigned int
1327 {
1328 /* ??? Logically we should only need to provide a value when
1329 HARD_REGNO_MODE_OK says that the combination is valid,
1330 but at the moment we need to handle all modes. Just ignore
1331 any runtime parts for registers that can't store them. */
1334 {
1347 }
1349 }
1351 /* Implement TARGET_HARD_REGNO_MODE_OK. */
1353 static bool
1355 {
1360 /* This must have the same size as _Unwind_Word. */
1371 /* The purpose of comparing with ptr_mode is to support the
1372 global register variable associated with the stack pointer
1373 register via the syntax of asm ("wsp") in ILP32. */
1383 {
1386 else
1388 }
1391 }
1393 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
1394 the lower 64 bits of a 128-bit register. Tell the compiler the callee
1395 clobbers the top 64 bits when restoring the bottom 64 bits. */
1397 static bool
1399 {
1401 }
1403 /* Implement REGMODE_NATURAL_SIZE. */
1404 poly_uint64
1406 {
1407 /* The natural size for SVE data modes is one SVE data vector,
1408 and similarly for predicates. We can't independently modify
1409 anything smaller than that. */
1410 /* ??? For now, only do this for variable-width SVE registers.
1411 Doing it for constant-sized registers breaks lower-subreg.c. */
1412 /* ??? And once that's fixed, we should probably have similar
1413 code for Advanced SIMD. */
1415 {
1421 }
1423 }
1425 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1426 machine_mode
1428 machine_mode mode)
1429 {
1430 /* The predicate mode determines which bits are significant and
1431 which are "don't care". Decreasing the number of lanes would
1432 lose data while increasing the number of lanes would make bits
1433 unnecessarily significant. */
1438 else
1440 }
1442 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
1443 that strcpy from constants will be faster. */
1445 static HOST_WIDE_INT
1447 {
1451 }
1453 /* Return true if calls to DECL should be treated as
1454 long-calls (ie called via a register). */
1455 static bool
1457 {
1459 }
1461 /* Return true if calls to symbol-ref SYM should be treated as
1462 long-calls (ie called via a register). */
1463 bool
1465 {
1467 }
1469 /* Return true if calls to symbol-ref SYM should not go through
1470 plt stubs. */
1472 bool
1474 {
1478 && decl
1479 && (!flag_plt
1485 }
1487 /* Return true if the offsets to a zero/sign-extract operation
1488 represent an expression that matches an extend operation. The
1489 operands represent the paramters from
1491 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1492 bool
1494 rtx extract_imm)
1495 {
1512 }
1514 /* Emit an insn that's a simple single-set. Both the operands must be
1515 known to be valid. */
1518 {
1520 }
1522 /* X and Y are two things to compare using CODE. Emit the compare insn and
1523 return the rtx for register 0 in the proper mode. */
1524 rtx
1526 {
1532 }
1534 /* Build the SYMBOL_REF for __tls_get_addr. */
1538 rtx
1540 {
1544 }
1546 /* Return the TLS model to use for ADDR. */
1548 static enum tls_model
1550 {
1553 {
1554 poly_int64 addend;
1558 }
1563 }
1565 /* We'll allow lo_sum's in addresses in our legitimate addresses
1566 so that combine would take care of combining addresses where
1567 necessary, but for generation purposes, we'll generate the address
1568 as :
1569 RTL Absolute
1570 tmp = hi (symbol_ref); adrp x1, foo
1571 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1572 nop
1574 PIC TLS
1575 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1576 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1577 bl __tls_get_addr
1578 nop
1580 Load TLS symbol, depending on TLS mechanism and TLS access model.
1582 Global Dynamic - Traditional TLS:
1583 adrp tmp, :tlsgd:imm
1584 add dest, tmp, #:tlsgd_lo12:imm
1585 bl __tls_get_addr
1587 Global Dynamic - TLS Descriptors:
1588 adrp dest, :tlsdesc:imm
1589 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1590 add dest, dest, #:tlsdesc_lo12:imm
1591 blr tmp
1592 mrs tp, tpidr_el0
1593 add dest, dest, tp
1595 Initial Exec:
1596 mrs tp, tpidr_el0
1597 adrp tmp, :gottprel:imm
1598 ldr dest, [tmp, #:gottprel_lo12:imm]
1599 add dest, dest, tp
1601 Local Exec:
1602 mrs tp, tpidr_el0
1603 add t0, tp, #:tprel_hi12:imm, lsl #12
1604 add t0, t0, #:tprel_lo12_nc:imm
1605 */
1607 static void
1610 {
1612 {
1614 {
1615 /* In ILP32, the mode of dest can be either SImode or DImode. */
1627 }
1634 {
1637 rtx insn;
1638 rtx mem;
1640 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1641 here before rtl expand. Tree IVOPT will generate rtl pattern to
1642 decide rtx costs, in which case pic_offset_table_rtx is not
1643 initialized. For that case no need to generate the first adrp
1644 instruction as the final cost for global variable access is
1645 one instruction. */
1647 {
1648 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1649 using the page base as GOT base, the first page may be wasted,
1650 in the worst scenario, there is only 28K space for GOT).
1652 The generate instruction sequence for accessing global variable
1653 is:
1655 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1657 Only one instruction needed. But we must initialize
1658 pic_offset_table_rtx properly. We generate initialize insn for
1659 every global access, and allow CSE to remove all redundant.
1661 The final instruction sequences will look like the following
1662 for multiply global variables access.
1664 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1666 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1667 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1668 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1669 ... */
1678 }
1681 {
1684 else
1688 }
1689 else
1690 {
1695 }
1697 /* The operand is expected to be MEM. Whenever the related insn
1698 pattern changed, above code which calculate mem should be
1699 updated. */
1705 }
1708 {
1709 /* In ILP32, the mode of dest can be either SImode or DImode,
1710 while the got entry is always of SImode size. The mode of
1711 dest depends on how dest is used: if dest is assigned to a
1712 pointer (e.g. in the memory), it has SImode; it may have
1713 DImode if dest is dereferenced to access the memeory.
1714 This is why we have to handle three different ldr_got_small
1715 patterns here (two patterns for ILP32). */
1717 rtx insn;
1718 rtx mem;
1727 {
1730 else
1734 }
1735 else
1736 {
1741 }
1748 }
1751 {
1759 else
1767 }
1770 {
1773 rtx tp;
1777 /* In ILP32, the got entry is always of SImode size. Unlike
1778 small GOT, the dest is fixed at reg 0. */
1781 else
1792 }
1795 {
1796 /* In ILP32, the mode of dest can be either SImode or DImode,
1797 while the got entry is always of SImode size. The mode of
1798 dest depends on how dest is used: if dest is assigned to a
1799 pointer (e.g. in the memory), it has SImode; it may have
1800 DImode if dest is dereferenced to access the memeory.
1801 This is why we have to handle three different tlsie_small
1802 patterns here (two patterns for ILP32). */
1808 {
1811 else
1812 {
1815 }
1816 }
1817 else
1818 {
1821 }
1827 }
1833 {
1841 {
1864 }
1869 }
1876 {
1881 {
1884 else
1885 {
1888 }
1889 }
1890 else
1891 {
1894 }
1899 }
1903 }
1904 }
1906 /* Emit a move from SRC to DEST. Assume that the move expanders can
1907 handle all moves if !can_create_pseudo_p (). The distinction is
1908 important because, unlike emit_move_insn, the move expanders know
1909 how to force Pmode objects into the constant pool even when the
1910 constant pool address is not itself legitimate. */
1911 static rtx
1913 {
1917 }
1919 /* Apply UNOPTAB to OP and store the result in DEST. */
1921 static void
1923 {
1927 }
1929 /* Apply BINOPTAB to OP0 and OP1 and store the result in DEST. */
1931 static void
1933 {
1935 OPTAB_DIRECT);
1938 }
1940 /* Split a 128-bit move operation into two 64-bit move operations,
1941 taking care to handle partial overlap of register to register
1942 copies. Special cases are needed when moving between GP regs and
1943 FP regs. SRC can be a register, constant or memory; DST a register
1944 or memory. If either operand is memory it must not have any side
1945 effects. */
1946 void
1948 {
1959 {
1963 /* Handle FP <-> GP regs. */
1965 {
1970 {
1973 }
1974 else
1975 {
1978 }
1980 }
1982 {
1987 {
1990 }
1991 else
1992 {
1995 }
1997 }
1998 }
2005 /* At most one pairing may overlap. */
2007 {
2010 }
2011 else
2012 {
2015 }
2016 }
2018 bool
2020 {
2023 }
2025 /* Split a complex SIMD combine. */
2027 void
2029 {
2041 {
2065 }
2069 }
2071 /* Split a complex SIMD move. */
2073 void
2075 {
2082 {
2088 {
2112 }
2116 }
2117 }
2119 bool
2122 {
2126 }
2129 static rtx
2131 {
2134 else
2135 {
2139 }
2140 }
2142 /* Return true if we can move VALUE into a register using a single
2143 CNT[BHWD] instruction. */
2145 static bool
2147 {
2149 /* The coefficient must be [1, 16] * {2, 4, 8, 16}. */
2154 }
2156 /* Likewise for rtx X. */
2158 bool
2160 {
2161 poly_int64 value;
2163 }
2165 /* Return the asm string for an instruction with a CNT-like vector size
2166 operand (a vector pattern followed by a multiplier in the range [1, 16]).
2167 PREFIX is the mnemonic without the size suffix and OPERANDS is the
2168 first part of the operands template (the part that comes before the
2169 vector size itself). FACTOR is the number of quadwords.
2170 NELTS_PER_VQ, if nonzero, is the number of elements in each quadword.
2171 If it is zero, we can use any element size. */
2177 {
2181 /* There is some overlap in the ranges of the four CNT instructions.
2182 Here we always use the smallest possible element size, so that the
2183 multiplier is 1 whereever possible. */
2194 else
2199 }
2201 /* Return the asm string for an instruction with a CNT-like vector size
2202 operand (a vector pattern followed by a multiplier in the range [1, 16]).
2203 PREFIX is the mnemonic without the size suffix and OPERANDS is the
2204 first part of the operands template (the part that comes before the
2205 vector size itself). X is the value of the vector size operand,
2206 as a polynomial integer rtx. */
2210 rtx x)
2211 {
2216 }
2218 /* Return true if we can add VALUE to a register using a single ADDVL
2219 or ADDPL instruction. */
2221 static bool
2223 {
2227 /* FACTOR counts VG / 2, so a value of 2 is one predicate width
2228 and a value of 16 is one vector width. */
2231 }
2233 /* Likewise for rtx X. */
2235 bool
2237 {
2238 poly_int64 value;
2241 }
2243 /* Return the asm string for adding ADDVL or ADDPL immediate X to operand 1
2244 and storing the result in operand 0. */
2248 {
2253 /* Use INC or DEC if possible. */
2255 {
2262 }
2267 else
2270 }
2272 /* Return true if X is a valid immediate for an SVE vector INC or DEC
2273 instruction. If it is, store the number of elements in each vector
2274 quadword in *NELTS_PER_VQ_OUT (if nonnull) and store the multiplication
2275 factor in *FACTOR_OUT (if nonnull). */
2277 bool
2280 {
2281 rtx elt;
2282 poly_int64 value;
2290 /* There's no vector INCB. */
2297 /* The coefficient must be [1, 16] * NELTS_PER_VQ. */
2307 }
2309 /* Return true if X is a valid immediate for an SVE vector INC or DEC
2310 instruction. */
2312 bool
2314 {
2316 }
2318 /* Return the asm template for an SVE vector INC or DEC instruction.
2319 OPERANDS gives the operands before the vector count and X is the
2320 value of the vector count operand itself. */
2324 {
2331 nelts_per_vq);
2332 else
2334 nelts_per_vq);
2335 }
2337 static int
2339 scalar_int_mode mode)
2340 {
2349 {
2353 }
2355 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
2356 (with XXXX non-zero). In that case check to see if the move can be done in
2357 a smaller mode. */
2362 {
2366 /* Check if we have to emit a second instruction by checking to see
2367 if any of the upper 32 bits of the original DI mode value is set. */
2378 }
2381 {
2383 {
2388 else
2391 }
2393 }
2395 /* Remaining cases are all for DImode. */
2404 {
2405 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
2406 For a 64-bit bitmask try whether changing 16 bits to all ones or
2407 zeroes creates a valid bitmask. To check any repeated bitmask,
2408 try using 16 bits from the other 32-bit half of val. */
2411 {
2422 }
2424 {
2426 {
2430 }
2432 }
2433 }
2435 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
2436 are emitted by the initial mov. If one_match > zero_match, skip set bits,
2437 otherwise skip zero bits. */
2449 {
2455 num_insns ++;
2456 }
2459 }
2461 /* Return whether imm is a 128-bit immediate which is simple enough to
2462 expand inline. */
2463 bool
2465 {
2476 }
2479 /* Return the number of temporary registers that aarch64_add_offset_1
2480 would need to add OFFSET to a register. */
2482 static unsigned int
2484 {
2486 }
2488 /* A subroutine of aarch64_add_offset. Set DEST to SRC + OFFSET for
2489 a non-polynomial OFFSET. MODE is the mode of the addition.
2490 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
2491 be set and CFA adjustments added to the generated instructions.
2493 TEMP1, if nonnull, is a register of mode MODE that can be used as a
2494 temporary if register allocation is already complete. This temporary
2495 register may overlap DEST but must not overlap SRC. If TEMP1 is known
2496 to hold abs (OFFSET), EMIT_MOVE_IMM can be set to false to avoid emitting
2497 the immediate again.
2499 Since this function may be used to adjust the stack pointer, we must
2500 ensure that it cannot cause transient stack deallocation (for example
2501 by first incrementing SP and then decrementing when adjusting by a
2502 large immediate). */
2504 static void
2508 {
2516 {
2518 {
2521 }
2523 }
2525 /* Single instruction adjustment. */
2527 {
2531 }
2533 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits
2534 and either:
2536 a) the offset cannot be loaded by a 16-bit move or
2537 b) there is no spare register into which we can move it. */
2541 {
2550 }
2552 /* Emit a move immediate if required and an addition/subtraction. */
2554 {
2557 }
2562 {
2566 }
2567 }
2569 /* Return the number of temporary registers that aarch64_add_offset
2570 would need to move OFFSET into a register or add OFFSET to a register;
2571 ADD_P is true if we want the latter rather than the former. */
2573 static unsigned int
2575 {
2576 /* This follows the same structure as aarch64_add_offset. */
2585 /* Need one register for the ADDVL/ADDPL result. */
2588 {
2591 /* Need one register for the CNT result and one for the multiplication
2592 factor. If necessary, the second temporary can be reused for the
2593 constant part of the offset. */
2595 /* Need one register for the CNT result (which might then
2596 be shifted). */
2598 }
2600 }
2602 /* If X can be represented as a poly_int64, return the number
2603 of temporaries that are required to add it to a register.
2604 Return -1 otherwise. */
2606 int
2608 {
2609 poly_int64 offset;
2613 }
2615 /* Set DEST to SRC + OFFSET. MODE is the mode of the addition.
2616 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
2617 be set and CFA adjustments added to the generated instructions.
2619 TEMP1, if nonnull, is a register of mode MODE that can be used as a
2620 temporary if register allocation is already complete. This temporary
2621 register may overlap DEST if !FRAME_RELATED_P but must not overlap SRC.
2622 If TEMP1 is known to hold abs (OFFSET), EMIT_MOVE_IMM can be set to
2623 false to avoid emitting the immediate again.
2625 TEMP2, if nonnull, is a second temporary register that doesn't
2626 overlap either DEST or REG.
2628 Since this function may be used to adjust the stack pointer, we must
2629 ensure that it cannot cause transient stack deallocation (for example
2630 by first incrementing SP and then decrementing when adjusting by a
2631 large immediate). */
2633 static void
2637 {
2641 || !frame_related_p
2645 /* Try using ADDVL or ADDPL to add the whole value. */
2647 {
2652 }
2654 /* Coefficient 1 is multiplied by the number of 128-bit blocks in an
2655 SVE vector register, over and above the minimum size of 128 bits.
2656 This is equivalent to half the value returned by CNTD with a
2657 vector shape of ALL. */
2661 /* Try using ADDVL or ADDPL to add the VG-based part. */
2665 {
2668 {
2672 }
2673 else
2674 {
2679 }
2680 }
2681 /* Otherwise use a CNT-based sequence. */
2683 {
2684 /* Use a subtraction if we have a negative factor. */
2687 {
2690 }
2692 /* Calculate CNTD * FACTOR / 2. First try to fold the division
2693 into the multiplication. */
2694 rtx val;
2697 /* Use a right shift by 1. */
2699 else
2703 {
2705 {
2706 /* "CNTB Xn, ALL, MUL #FACTOR" is out of range, so calculate
2707 the value with the minimum multiplier and shift it into
2708 position. */
2712 }
2714 }
2715 else
2716 {
2717 /* Use CNTD, then multiply it by FACTOR. */
2721 /* Go back to using a negative multiplication factor if we have
2722 no register from which to subtract. */
2724 {
2727 }
2731 }
2734 {
2735 /* Multiply by 1 << SHIFT. */
2738 }
2740 {
2741 /* Divide by 2. */
2744 }
2746 /* Calculate SRC +/- CNTD * FACTOR / 2. */
2748 {
2751 }
2753 {
2756 }
2759 {
2762 {
2766 poly_offset)));
2767 }
2771 }
2772 else
2773 {
2777 }
2780 }
2784 }
2786 /* Like aarch64_add_offset, but the offset is given as an rtx rather
2787 than a poly_int64. */
2789 void
2792 {
2795 }
2797 /* Add DELTA to the stack pointer, marking the instructions frame-related.
2798 TEMP1 is available as a temporary if nonnull. EMIT_MOVE_IMM is false
2799 if TEMP1 already contains abs (DELTA). */
2803 {
2806 }
2808 /* Subtract DELTA from the stack pointer, marking the instructions
2809 frame-related if FRAME_RELATED_P. TEMP1 is available as a temporary
2810 if nonnull. */
2814 {
2817 }
2819 /* Set DEST to (vec_series BASE STEP). */
2821 static void
2823 {
2827 /* Each operand can be a register or an immediate in the range [-16, 15]. */
2834 }
2836 /* Try to duplicate SRC into SVE register DEST, given that SRC is an
2837 integer of mode INT_MODE. Return true on success. */
2839 static bool
2841 rtx src)
2842 {
2843 /* If the constant is smaller than 128 bits, we can do the move
2844 using a vector of SRC_MODEs. */
2846 {
2853 }
2855 /* Use LD1RQ[BHWD] to load the 128 bits from memory. */
2860 /* Make sure that the address is legitimate. */
2862 {
2865 }
2874 }
2876 /* Expand a move of general CONST_VECTOR SRC into DEST, given that it
2877 isn't a simple duplicate or series. */
2879 static void
2881 {
2888 {
2889 /* The constant is a repeating seqeuence of at least two elements,
2890 where the repeating elements occupy no more than 128 bits.
2891 Get an integer representation of the replicated value. */
2892 scalar_int_mode int_mode;
2894 /* For now, always use LD1RQ to load the value on big-endian
2895 targets, since the handling of smaller integers includes a
2896 subreg that is semantically an element reverse. */
2898 else
2899 {
2903 }
2908 }
2910 /* Expand each pattern individually. */
2911 rtx_vector_builder builder;
2914 {
2919 }
2921 /* Use permutes to interleave the separate vectors. */
2923 {
2926 {
2931 }
2932 }
2934 }
2936 /* Set DEST to immediate IMM. For SVE vector modes, GEN_VEC_DUPLICATE
2937 is a pattern that can be used to set DEST to a replicated scalar
2938 element. */
2940 void
2943 {
2946 /* Check on what type of symbol it is. */
2947 scalar_int_mode int_mode;
2953 {
2954 rtx mem;
2955 poly_int64 offset;
2956 HOST_WIDE_INT const_offset;
2959 /* If we have (const (plus symbol offset)), separate out the offset
2960 before we start classifying the symbol. */
2963 /* We must always add an offset involving VL separately, rather than
2964 folding it into the relocation. */
2966 {
2969 else
2970 {
2971 /* Do arithmetic on 32-bit values if the result is smaller
2972 than that. */
2974 {
2975 /* It is invalid to do symbol calculations in modes
2976 narrower than SImode. */
2980 }
2982 {
2986 }
2987 else
2990 }
2992 }
2996 {
3000 {
3006 }
3011 /* If we aren't generating PC relative literals, then
3012 we need to expand the literal pool access carefully.
3013 This is something that needs to be done in a number
3014 of places, so could well live as a separate function. */
3016 {
3023 }
3040 {
3046 }
3047 /* FALLTHRU */
3060 }
3061 }
3064 {
3072 {
3073 /* If the constant is out of range of an SVE vector move,
3074 load it from memory if we can, otherwise move it into
3075 a register and use a DUP. */
3081 {
3084 }
3086 }
3090 else
3091 {
3095 }
3098 }
3102 }
3104 /* Emit an SVE predicated move from SRC to DEST. PRED is a predicate
3105 that is known to contain PTRUE. */
3107 void
3109 {
3112 UNSPEC_MERGE_PTRUE)));
3113 }
3115 /* Expand a pre-RA SVE data move from SRC to DEST in which at least one
3116 operand is in memory. In this case we need to use the predicated LD1
3117 and ST1 instead of LDR and STR, both for correctness on big-endian
3118 targets and because LD1 and ST1 support a wider range of addressing modes.
3119 PRED_MODE is the mode of the predicate.
3121 See the comment at the head of aarch64-sve.md for details about the
3122 big-endian handling. */
3124 void
3126 {
3131 {
3135 else
3138 }
3140 }
3142 /* Called only on big-endian targets. See whether an SVE vector move
3143 from SRC to DEST is effectively a REV[BHW] instruction, because at
3144 least one operand is a subreg of an SVE vector that has wider or
3145 narrower elements. Return true and emit the instruction if so.
3147 For example:
3149 (set (reg:VNx8HI R1) (subreg:VNx8HI (reg:VNx16QI R2) 0))
3151 represents a VIEW_CONVERT between the following vectors, viewed
3152 in memory order:
3154 R2: { [0].high, [0].low, [1].high, [1].low, ... }
3155 R1: { [0], [1], [2], [3], ... }
3157 The high part of lane X in R2 should therefore correspond to lane X*2
3158 of R1, but the register representations are:
3160 msb lsb
3161 R2: ...... [1].high [1].low [0].high [0].low
3162 R1: ...... [3] [2] [1] [0]
3164 where the low part of lane X in R2 corresponds to lane X*2 in R1.
3165 We therefore need a reverse operation to swap the high and low values
3166 around.
3168 This is purely an optimization. Without it we would spill the
3169 subreg operand to the stack in one mode and reload it in the
3170 other mode, which has the same effect as the REV. */
3172 bool
3174 {
3181 /* The optimization handles two single SVE REGs with different element
3182 sizes. */
3191 /* Generate *aarch64_sve_mov<mode>_subreg_be. */
3194 UNSPEC_REV_SUBREG);
3197 }
3199 /* Return a copy of X with mode MODE, without changing its other
3200 attributes. Unlike gen_lowpart, this doesn't care whether the
3201 mode change is valid. */
3203 static rtx
3205 {
3212 }
3214 /* Split a *aarch64_sve_mov<mode>_subreg_be pattern with the given
3215 operands. */
3217 void
3219 {
3220 /* Decide which REV operation we need. The mode with narrower elements
3221 determines the mode of the operands and the mode with the wider
3222 elements determines the reverse width. */
3237 else
3241 /* Emit:
3243 (set DEST (unspec [PTRUE (unspec [SRC] UNSPEC_REV<nn>)]
3244 UNSPEC_MERGE_PTRUE))
3246 with the appropriate modes. */
3252 UNSPEC_MERGE_PTRUE);
3254 }
3256 static bool
3258 tree exp ATTRIBUTE_UNUSED)
3259 {
3260 /* Currently, always true. */
3262 }
3264 /* Implement TARGET_PASS_BY_REFERENCE. */
3266 static bool
3268 machine_mode mode,
3269 const_tree type,
3271 {
3272 HOST_WIDE_INT size;
3273 machine_mode dummymode;
3276 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
3279 else
3280 /* No frontends can create types with variable-sized modes, so we
3281 shouldn't be asked to pass or return them. */
3284 /* Aggregates are passed by reference based on their size. */
3286 {
3288 }
3290 /* Variable sized arguments are always returned by reference. */
3294 /* Can this be a candidate to be passed in fp/simd register(s)? */
3297 NULL))
3300 /* Arguments which are variable sized or larger than 2 registers are
3301 passed by reference unless they are a homogenous floating point
3302 aggregate. */
3304 }
3306 /* Return TRUE if VALTYPE is padded to its least significant bits. */
3307 static bool
3309 {
3310 machine_mode dummy_mode;
3313 /* Never happens in little-endian mode. */
3317 /* Only composite types smaller than or equal to 16 bytes can
3318 be potentially returned in registers. */
3324 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
3325 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
3326 is always passed/returned in the least significant bits of fp/simd
3327 register(s). */
3333 }
3335 /* Implement TARGET_FUNCTION_VALUE.
3336 Define how to find the value returned by a function. */
3338 static rtx
3341 {
3342 machine_mode mode;
3345 machine_mode ag_mode;
3352 {
3356 {
3359 }
3360 }
3364 {
3366 {
3369 }
3370 else
3371 {
3373 rtx par;
3377 {
3382 }
3384 }
3385 }
3386 else
3388 }
3390 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
3391 Return true if REGNO is the number of a hard register in which the values
3392 of called function may come back. */
3394 static bool
3396 {
3397 /* Maximum of 16 bytes can be returned in the general registers. Examples
3398 of 16-byte return values are: 128-bit integers and 16-byte small
3399 structures (excluding homogeneous floating-point aggregates). */
3403 /* Up to four fp/simd registers can return a function value, e.g. a
3404 homogeneous floating-point aggregate having four members. */
3409 }
3411 /* Implement TARGET_RETURN_IN_MEMORY.
3413 If the type T of the result of a function is such that
3414 void func (T arg)
3415 would require that arg be passed as a value in a register (or set of
3416 registers) according to the parameter passing rules, then the result
3417 is returned in the same registers as would be used for such an
3418 argument. */
3420 static bool
3422 {
3423 HOST_WIDE_INT size;
3424 machine_mode ag_mode;
3430 /* Simple scalar types always returned in registers. */
3434 type,
3437 NULL))
3440 /* Types larger than 2 registers returned in memory. */
3443 }
3445 static bool
3448 {
3451 type,
3453 nregs,
3454 NULL);
3455 }
3457 /* Given MODE and TYPE of a function argument, return the alignment in
3458 bits. The idea is to suppress any stronger alignment requested by
3459 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
3460 This is a helper function for local use only. */
3462 static unsigned int
3464 {
3485 }
3487 /* Layout a function argument according to the AAPCS64 rules. The rule
3488 numbers refer to the rule numbers in the AAPCS64. */
3490 static void
3492 const_tree type,
3494 {
3498 HOST_WIDE_INT size;
3500 /* We need to do this once per argument. */
3506 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
3509 else
3510 /* No frontends can create types with variable-sized modes, so we
3511 shouldn't be asked to pass or return them. */
3517 mode,
3518 type,
3521 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
3522 The following code thus handles passing by SIMD/FP registers first. */
3526 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
3527 and homogenous short-vector aggregates (HVA). */
3529 {
3534 {
3537 {
3540 }
3541 else
3542 {
3543 rtx par;
3547 {
3550 rtx offset = gen_int_mode
3554 }
3556 }
3558 }
3559 else
3560 {
3561 /* C.3 NSRN is set to 8. */
3564 }
3565 }
3570 /* C6 - C9. though the sign and zero extension semantics are
3571 handled elsewhere. This is the case where the argument fits
3572 entirely general registers. */
3574 {
3578 /* C.8 if the argument has an alignment of 16 then the NGRN is
3579 rounded up to the next even number. */
3582 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
3583 comparison is there because for > 16 * BITS_PER_UNIT
3584 alignment nregs should be > 2 and therefore it should be
3585 passed by reference rather than value. */
3587 {
3590 }
3592 /* NREGS can be 0 when e.g. an empty structure is to be passed.
3593 A reg is still generated for it, but the caller should be smart
3594 enough not to use it. */
3597 else
3598 {
3599 rtx par;
3604 {
3609 }
3611 }
3615 }
3617 /* C.11 */
3620 /* The argument is passed on stack; record the needed number of words for
3621 this argument and align the total size if necessary. */
3622 on_stack:
3629 }
3631 /* Implement TARGET_FUNCTION_ARG. */
3633 static rtx
3636 {
3645 }
3647 void
3649 const_tree fntype ATTRIBUTE_UNUSED,
3650 rtx libname ATTRIBUTE_UNUSED,
3651 const_tree fndecl ATTRIBUTE_UNUSED,
3653 {
3667 {
3674 }
3676 }
3678 static void
3680 machine_mode mode,
3681 const_tree type,
3683 {
3686 {
3696 }
3697 }
3699 bool
3701 {
3704 }
3706 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3707 PARM_BOUNDARY bits of alignment, but will be given anything up
3708 to STACK_BOUNDARY bits if the type requires it. This makes sure
3709 that both before and after the layout of each argument, the Next
3710 Stacked Argument Address (NSAA) will have a minimum alignment of
3711 8 bytes. */
3713 static unsigned int
3715 {
3718 }
3720 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
3722 static fixed_size_mode
3724 {
3726 /* Don't use the SVE part of the register for __builtin_apply and
3727 __builtin_return. The SVE registers aren't used by the normal PCS,
3728 so using them there would be a waste of time. The PCS extensions
3729 for SVE types are fundamentally incompatible with the
3730 __builtin_return/__builtin_apply interface. */
3733 }
3735 /* Implement TARGET_FUNCTION_ARG_PADDING.
3737 Small aggregate types are placed in the lowest memory address.
3739 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
3741 static pad_direction
3743 {
3744 /* On little-endian targets, the least significant byte of every stack
3745 argument is passed at the lowest byte address of the stack slot. */
3749 /* Otherwise, integral, floating-point and pointer types are padded downward:
3750 the least significant byte of a stack argument is passed at the highest
3751 byte address of the stack slot. */
3758 /* Everything else padded upward, i.e. data in first byte of stack slot. */
3760 }
3762 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
3764 It specifies padding for the last (may also be the only)
3765 element of a block move between registers and memory. If
3766 assuming the block is in the memory, padding upward means that
3767 the last element is padded after its highest significant byte,
3768 while in downward padding, the last element is padded at the
3769 its least significant byte side.
3771 Small aggregates and small complex types are always padded
3772 upwards.
3774 We don't need to worry about homogeneous floating-point or
3775 short-vector aggregates; their move is not affected by the
3776 padding direction determined here. Regardless of endianness,
3777 each element of such an aggregate is put in the least
3778 significant bits of a fp/simd register.
3780 Return !BYTES_BIG_ENDIAN if the least significant byte of the
3781 register has useful data, and return the opposite if the most
3782 significant byte does. */
3784 bool
3787 {
3789 /* Small composite types are always padded upward. */
3791 {
3792 HOST_WIDE_INT size;
3795 else
3796 /* No frontends can create types with variable-sized modes, so we
3797 shouldn't be asked to pass or return them. */
3801 }
3803 /* Otherwise, use the default padding. */
3805 }
3807 static scalar_int_mode
3809 {
3811 }
3813 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
3815 /* We use the 12-bit shifted immediate arithmetic instructions so values
3816 must be multiple of (1 << 12), i.e. 4096. */
3817 #define ARITH_FACTOR 4096
3819 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
3820 #error Cannot use simple address calculation for stack probing
3821 #endif
3823 /* The pair of scratch registers used for stack probing. */
3824 #define PROBE_STACK_FIRST_REG 9
3825 #define PROBE_STACK_SECOND_REG 10
3827 /* Emit code to probe a range of stack addresses from FIRST to FIRST+POLY_SIZE,
3828 inclusive. These are offsets from the current stack pointer. */
3830 static void
3832 {
3833 HOST_WIDE_INT size;
3835 {
3838 }
3842 /* See the same assertion on PROBE_INTERVAL above. */
3845 /* See if we have a constant small number of probes to generate. If so,
3846 that's the easy case. */
3848 {
3855 }
3857 /* The run-time loop is made up of 8 insns in the generic case while the
3858 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
3860 {
3865 stack_pointer_rtx,
3869 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
3870 it exceeds SIZE. If only two probes are needed, this will not
3871 generate any code. Then probe at FIRST + SIZE. */
3873 {
3877 }
3881 {
3886 }
3887 else
3889 }
3891 /* Otherwise, do the same as above, but in a loop. Note that we must be
3892 extra careful with variables wrapping around because we might be at
3893 the very top (or the very bottom) of the address space and we have
3894 to be able to handle this case properly; in particular, we use an
3895 equality test for the loop condition. */
3896 else
3897 {
3900 /* Step 1: round SIZE to the previous multiple of the interval. */
3905 /* Step 2: compute initial and final value of the loop counter. */
3907 /* TEST_ADDR = SP + FIRST. */
3911 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
3914 {
3918 }
3919 else
3923 /* Step 3: the loop
3925 do
3926 {
3927 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
3928 probe at TEST_ADDR
3929 }
3930 while (TEST_ADDR != LAST_ADDR)
3932 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
3933 until it is equal to ROUNDED_SIZE. */
3938 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
3939 that SIZE is equal to ROUNDED_SIZE. */
3942 {
3946 {
3951 }
3952 else
3954 }
3955 }
3957 /* Make sure nothing is scheduled before we are done. */
3959 }
3961 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
3962 absolute addresses. */
3966 {
3973 /* Loop. */
3976 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
3981 /* Probe at TEST_ADDR. */
3984 /* Test if TEST_ADDR == LAST_ADDR. */
3988 /* Branch. */
3994 }
3996 /* Determine whether a frame chain needs to be generated. */
3997 static bool
3999 {
4000 /* Force a frame chain for EH returns so the return address is at FP+8. */
4004 /* A leaf function cannot have calls or write LR. */
4007 /* Don't use a frame chain in leaf functions if leaf frame pointers
4008 are disabled. */
4013 }
4015 /* Mark the registers that need to be saved by the callee and calculate
4016 the size of the callee-saved registers area and frame record (both FP
4017 and LR may be omitted). */
4018 static void
4020 {
4029 #define SLOT_NOT_REQUIRED (-2)
4030 #define SLOT_REQUIRED (-1)
4035 /* First mark all the registers that really need to be saved... */
4042 /* ... that includes the eh data registers (if needed)... */
4048 /* ... and any callee saved register that dataflow says is live. */
4058 {
4061 }
4064 {
4065 /* FP and LR are placed in the linkage record. */
4071 }
4073 /* Now assign stack slots for them. */
4076 {
4083 }
4091 {
4092 /* If there is an alignment gap between integer and fp callee-saves,
4093 allocate the last fp register to it if possible. */
4095 {
4098 }
4107 }
4113 HOST_WIDE_INT varargs_and_saved_regs_size
4121 /* Both these values are already aligned. */
4145 {
4146 /* Simple, small frame with no outgoing arguments:
4147 stp reg1, reg2, [sp, -frame_size]!
4148 stp reg3, reg4, [sp, 16] */
4150 }
4155 max_push_offset)))
4156 {
4157 /* Frame with small outgoing arguments:
4158 sub sp, sp, frame_size
4159 stp reg1, reg2, [sp, outgoing_args_size]
4160 stp reg3, reg4, [sp, outgoing_args_size + 16] */
4164 }
4167 {
4168 /* Frame with large outgoing arguments but a small local area:
4169 stp reg1, reg2, [sp, -hard_fp_offset]!
4170 stp reg3, reg4, [sp, 16]
4171 sub sp, sp, outgoing_args_size */
4175 }
4176 else
4177 {
4178 /* Frame with large local area and outgoing arguments using frame pointer:
4179 sub sp, sp, hard_fp_offset
4180 stp x29, x30, [sp, 0]
4181 add x29, sp, 0
4182 stp reg3, reg4, [sp, 16]
4183 sub sp, sp, outgoing_args_size */
4187 }
4190 }
4192 /* Return true if the register REGNO is saved on entry to
4193 the current function. */
4195 static bool
4197 {
4199 }
4201 /* Return the next register up from REGNO up to LIMIT for the callee
4202 to save. */
4204 static unsigned
4206 {
4208 regno ++;
4210 }
4212 /* Push the register number REGNO of mode MODE to the stack with write-back
4213 adjusting the stack by ADJUSTMENT. */
4215 static void
4217 HOST_WIDE_INT adjustment)
4218 {
4229 }
4231 /* Generate and return an instruction to store the pair of registers
4232 REG and REG2 of mode MODE to location BASE with write-back adjusting
4233 the stack location BASE by ADJUSTMENT. */
4235 static rtx
4237 HOST_WIDE_INT adjustment)
4238 {
4240 {
4251 }
4252 }
4254 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
4255 stack pointer by ADJUSTMENT. */
4257 static void
4259 {
4274 }
4276 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
4277 adjusting it by ADJUSTMENT afterwards. */
4279 static rtx
4281 HOST_WIDE_INT adjustment)
4282 {
4284 {
4293 }
4294 }
4296 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
4297 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
4298 into CFI_OPS. */
4300 static void
4303 {
4310 {
4314 }
4315 else
4316 {
4321 }
4322 }
4324 /* Generate and return a store pair instruction of mode MODE to store
4325 register REG1 to MEM1 and register REG2 to MEM2. */
4327 static rtx
4329 rtx reg2)
4330 {
4332 {
4341 }
4342 }
4344 /* Generate and regurn a load pair isntruction of mode MODE to load register
4345 REG1 from MEM1 and register REG2 from MEM2. */
4347 static rtx
4349 rtx mem2)
4350 {
4352 {
4361 }
4362 }
4364 /* Return TRUE if return address signing should be enabled for the current
4365 function, otherwise return FALSE. */
4367 bool
4369 {
4370 /* This function should only be called after frame laid out. */
4373 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
4374 if it's LR is pushed onto stack. */
4378 }
4380 /* Emit code to save the callee-saved registers from register number START
4381 to LIMIT to the stack at the location starting at offset START_OFFSET,
4382 skipping any write-back candidates if SKIP_WB is true. */
4384 static void
4387 {
4395 {
4397 poly_int64 offset;
4410 offset));
4419 {
4421 rtx mem2;
4425 offset));
4427 reg2));
4429 /* The first part of a frame-related parallel insn is
4430 always assumed to be relevant to the frame
4431 calculations; subsequent parts, are only
4432 frame-related if explicitly marked. */
4435 }
4436 else
4440 }
4441 }
4443 /* Emit code to restore the callee registers of mode MODE from register
4444 number START up to and including LIMIT. Restore from the stack offset
4445 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
4446 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
4448 static void
4452 {
4456 poly_int64 offset;
4461 {
4482 {
4484 rtx mem2;
4492 }
4493 else
4496 }
4497 }
4499 /* Return true if OFFSET is a signed 4-bit value multiplied by the size
4500 of MODE. */
4504 {
4505 HOST_WIDE_INT multiple;
4508 }
4510 /* Return true if OFFSET is a unsigned 6-bit value multiplied by the size
4511 of MODE. */
4515 {
4516 HOST_WIDE_INT multiple;
4519 }
4521 /* Return true if OFFSET is a signed 7-bit value multiplied by the size
4522 of MODE. */
4524 bool
4526 {
4527 HOST_WIDE_INT multiple;
4530 }
4532 /* Return true if OFFSET is a signed 9-bit value. */
4536 poly_int64 offset)
4537 {
4538 HOST_WIDE_INT const_offset;
4541 }
4543 /* Return true if OFFSET is a signed 9-bit value multiplied by the size
4544 of MODE. */
4548 {
4549 HOST_WIDE_INT multiple;
4552 }
4554 /* Return true if OFFSET is an unsigned 12-bit value multiplied by the size
4555 of MODE. */
4559 {
4560 HOST_WIDE_INT multiple;
4563 }
4565 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
4567 static sbitmap
4569 {
4575 /* The registers we need saved to the frame. */
4578 {
4583 /* Check that we can access the stack slot of the register with one
4584 direct load with no adjustments needed. */
4587 }
4589 /* Don't mess with the hard frame pointer. */
4595 /* If aarch64_layout_frame has chosen registers to store/restore with
4596 writeback don't interfere with them to avoid having to output explicit
4597 stack adjustment instructions. */
4607 }
4609 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
4611 static sbitmap
4613 {
4621 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
4627 {
4631 /* If there is a callee-save at an adjacent offset, add it too
4632 to increase the use of LDP/STP. */
4637 {
4641 }
4642 }
4645 }
4647 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
4648 Nothing to do for aarch64. */
4650 static void
4652 {
4653 }
4655 /* Return the next set bit in BMP from START onwards. Return the total number
4656 of bits in BMP if no set bit is found at or after START. */
4658 static unsigned int
4660 {
4671 }
4673 /* Do the work for aarch64_emit_prologue_components and
4674 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
4675 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
4676 for these components or the epilogue sequence. That is, it determines
4677 whether we should emit stores or loads and what kind of CFA notes to attach
4678 to the insns. Otherwise the logic for the two sequences is very
4679 similar. */
4681 static void
4683 {
4685 ? HARD_FRAME_POINTER_REGNUM
4693 {
4694 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
4695 so DFmode for the vector registers is enough. */
4707 /* No more registers to handle after REGNO.
4708 Emit a single save/restore and exit. */
4710 {
4715 else
4718 }
4721 /* The next register is not of the same class or its offset is not
4722 mergeable with the current one into a pair. */
4727 {
4732 else
4737 }
4739 /* REGNO2 can be saved/restored in a pair with REGNO. */
4751 else
4756 {
4759 }
4760 else
4761 {
4764 }
4767 }
4768 }
4770 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
4772 static void
4774 {
4776 }
4778 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
4780 static void
4782 {
4784 }
4786 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
4788 static void
4790 {
4794 }
4796 /* Add a REG_CFA_EXPRESSION note to INSN to say that register REG
4797 is saved at BASE + OFFSET. */
4799 static void
4802 {
4806 }
4808 /* AArch64 stack frames generated by this compiler look like:
4810 +-------------------------------+
4811 | |
4812 | incoming stack arguments |
4813 | |
4814 +-------------------------------+
4815 | | <-- incoming stack pointer (aligned)
4816 | callee-allocated save area |
4817 | for register varargs |
4818 | |
4819 +-------------------------------+
4820 | local variables | <-- frame_pointer_rtx
4821 | |
4822 +-------------------------------+
4823 | padding0 | \
4824 +-------------------------------+ |
4825 | callee-saved registers | | frame.saved_regs_size
4826 +-------------------------------+ |
4827 | LR' | |
4828 +-------------------------------+ |
4829 | FP' | / <- hard_frame_pointer_rtx (aligned)
4830 +-------------------------------+
4831 | dynamic allocation |
4832 +-------------------------------+
4833 | padding |
4834 +-------------------------------+
4835 | outgoing stack arguments | <-- arg_pointer
4836 | |
4837 +-------------------------------+
4838 | | <-- stack_pointer_rtx (aligned)
4840 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
4841 but leave frame_pointer_rtx and hard_frame_pointer_rtx
4842 unchanged. */
4844 /* Generate the prologue instructions for entry into a function.
4845 Establish the stack frame by decreasing the stack pointer with a
4846 properly calculated size and, if necessary, create a frame record
4847 filled with the values of LR and previous frame pointer. The
4848 current FP is also set up if it is in use. */
4850 void
4852 {
4865 /* Sign return address for functions. */
4867 {
4871 }
4877 {
4879 {
4883 (frame_size
4885 }
4888 }
4899 {
4902 {
4907 }
4912 {
4913 /* Variable-sized frames need to describe the save slot
4914 address using DW_CFA_expression rather than DW_CFA_offset.
4915 This means that, without taking further action, the
4916 locations of the registers that we've already saved would
4917 remain based on the stack pointer even after we redefine
4918 the CFA based on the frame pointer. We therefore need new
4919 DW_CFA_expressions to re-express the save slots with addresses
4920 based on the frame pointer. */
4924 /* Add an explicit CFA definition if this was previously
4925 implicit. */
4927 {
4929 callee_offset);
4932 }
4934 /* Change the save slot expressions for the registers that
4935 we've already saved. */
4940 reg_offset);
4941 }
4943 }
4950 }
4952 /* Return TRUE if we can use a simple_return insn.
4954 This function checks whether the callee saved stack is empty, which
4955 means no restore actions are need. The pro_and_epilogue will use
4956 this to check whether shrink-wrapping opt is feasible. */
4958 bool
4960 {
4970 }
4972 /* Generate the epilogue instructions for returning from a function.
4973 This is almost exactly the reverse of the prolog sequence, except
4974 that we need to insert barriers to avoid scheduling loads that read
4975 from a deallocated stack, and we optimize the unwind records by
4976 emitting them all together if possible. */
4977 void
4979 {
4990 /* A stack clash protection prologue may not have left IP0_REGNUM or
4991 IP1_REGNUM in a usable state. The same is true for allocations
4992 with an SVE component, since we then need both temporary registers
4993 for each allocation. */
4998 /* We need to add memory barrier to prevent read from deallocated stack. */
4999 bool need_barrier_p
5003 /* Emit a barrier to prevent loads from a deallocated stack. */
5007 {
5010 }
5012 /* Restore the stack pointer from the frame pointer if it may not
5013 be the same as the stack pointer. */
5018 /* If writeback is used when restoring callee-saves, the CFA
5019 is restored on the instruction doing the writeback. */
5023 else
5039 {
5040 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
5046 }
5052 {
5053 /* Emit delayed restores and reset the CFA to be SP. */
5058 }
5060 /* We prefer to emit the combined return/authenticate instruction RETAA,
5061 however there are three cases in which we must instead emit an explicit
5062 authentication instruction.
5064 1) Sibcalls don't return in a normal way, so if we're about to call one
5065 we must authenticate.
5067 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
5068 generating code for !TARGET_ARMV8_3 we can't use it and must
5069 explicitly authenticate.
5071 3) On an eh_return path we make extra stack adjustments to update the
5072 canonical frame address to be the exception handler's CFA. We want
5073 to authenticate using the CFA of the function which calls eh_return.
5074 */
5077 {
5081 }
5083 /* Stack adjustment for exception handler. */
5085 {
5086 /* We need to unwind the stack by the offset computed by
5087 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
5088 to be SP; letting the CFA move during this adjustment
5089 is just as correct as retaining the CFA from the body
5090 of the function. Therefore, do nothing special. */
5092 }
5097 }
5099 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
5100 normally or return to a previous frame after unwinding.
5102 An EH return uses a single shared return sequence. The epilogue is
5103 exactly like a normal epilogue except that it has an extra input
5104 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
5105 that must be applied after the frame has been destroyed. An extra label
5106 is inserted before the epilogue which initializes this register to zero,
5107 and this is the entry point for a normal return.
5109 An actual EH return updates the return address, initializes the stack
5110 adjustment and jumps directly into the epilogue (bypassing the zeroing
5111 of the adjustment). Since the return address is typically saved on the
5112 stack when a function makes a call, the saved LR must be updated outside
5113 the epilogue.
5115 This poses problems as the store is generated well before the epilogue,
5116 so the offset of LR is not known yet. Also optimizations will remove the
5117 store as it appears dead, even after the epilogue is generated (as the
5118 base or offset for loading LR is different in many cases).
5120 To avoid these problems this implementation forces the frame pointer
5121 in eh_return functions so that the location of LR is fixed and known early.
5122 It also marks the store volatile, so no optimization is permitted to
5123 remove the store. */
5124 rtx
5126 {
5130 /* Mark the store volatile, so no optimization is permitted to remove it. */
5133 }
5135 /* Output code to add DELTA to the first argument, and then jump
5136 to FUNCTION. Used for C++ multiple inheritance. */
5137 static void
5139 HOST_WIDE_INT delta,
5140 HOST_WIDE_INT vcall_offset,
5141 tree function)
5142 {
5143 /* The this pointer is always in x0. Note that this differs from
5144 Arm where the this pointer maybe bumped to r1 if r0 is required
5145 to return a pointer to an aggregate. On AArch64 a result value
5146 pointer will be in x8. */
5160 else
5161 {
5166 {
5170 else
5173 }
5177 else
5184 else
5185 {
5187 Pmode);
5189 }
5193 else
5199 }
5201 /* Generate a tail call to the target function. */
5203 {
5206 }
5218 /* Stop pretending to be a post-reload pass. */
5220 }
5222 static bool
5224 {
5229 {
5233 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
5234 TLS offsets, not real symbol references. */
5237 }
5239 }
5242 /* Return true if val can be encoded as a 12-bit unsigned immediate with
5243 a left shift of 0 or 12 bits. */
5244 bool
5246 {
5249 );
5250 }
5253 /* Return true if val is an immediate that can be loaded into a
5254 register by a MOVZ instruction. */
5255 static bool
5257 {
5259 {
5263 }
5264 else
5265 {
5266 /* Ignore sign extension. */
5268 }
5271 }
5273 /* VAL is a value with the inner mode of MODE. Replicate it to fill a
5274 64-bit (DImode) integer. */
5276 static unsigned HOST_WIDE_INT
5278 {
5281 {
5285 }
5287 }
5289 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
5292 {
5298 };
5301 /* Return true if val is a valid bitmask immediate. */
5303 bool
5305 {
5309 /* Check for a single sequence of one bits and return quickly if so.
5310 The special cases of all ones and all zeroes returns false. */
5317 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
5321 /* Invert if the immediate doesn't start with a zero bit - this means we
5322 only need to search for sequences of one bits. */
5326 /* Find the first set bit and set tmp to val with the first sequence of one
5327 bits removed. Return success if there is a single sequence of ones. */
5334 /* Find the next set bit and compute the difference in bit position. */
5339 /* Check the bit position difference is a power of 2, and that the first
5340 sequence of one bits fits within 'bits' bits. */
5344 /* Check the sequence of one bits is repeated 64/bits times. */
5346 }
5348 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
5349 Assumed precondition: VAL_IN Is not zero. */
5351 unsigned HOST_WIDE_INT
5353 {
5360 }
5362 /* Create constant where bits outside of lowest bit set to highest bit set
5363 are set to 1. */
5365 unsigned HOST_WIDE_INT
5367 {
5369 }
5371 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
5373 bool
5375 {
5376 scalar_int_mode int_mode;
5389 }
5391 /* Return true if val is an immediate that can be loaded into a
5392 register in a single instruction. */
5393 bool
5395 {
5396 scalar_int_mode int_mode;
5403 }
5405 static bool
5407 {
5413 /* There's no way to calculate VL-based values using relocations. */
5421 {
5425 else
5426 /* Avoid generating a 64-bit relocation in ILP32; leave
5427 to aarch64_expand_mov_immediate to handle it properly. */
5429 }
5432 }
5434 /* Implement TARGET_CASE_VALUES_THRESHOLD.
5435 The expansion for a table switch is quite expensive due to the number
5436 of instructions, the table lookup and hard to predict indirect jump.
5437 When optimizing for speed, and -O3 enabled, use the per-core tuning if
5438 set, otherwise use tables for > 16 cases as a tradeoff between size and
5439 performance. When optimizing for size, use the default setting. */
5441 static unsigned int
5443 {
5444 /* Use the specified limit for the number of cases before using jump
5445 tables at higher optimization levels. */
5449 else
5451 }
5453 /* Return true if register REGNO is a valid index register.
5454 STRICT_P is true if REG_OK_STRICT is in effect. */
5456 bool
5458 {
5460 {
5468 }
5470 }
5472 /* Return true if register REGNO is a valid base register for mode MODE.
5473 STRICT_P is true if REG_OK_STRICT is in effect. */
5475 bool
5477 {
5479 {
5487 }
5489 /* The fake registers will be eliminated to either the stack or
5490 hard frame pointer, both of which are usually valid base registers.
5491 Reload deals with the cases where the eliminated form isn't valid. */
5496 }
5498 /* Return true if X is a valid base register for mode MODE.
5499 STRICT_P is true if REG_OK_STRICT is in effect. */
5501 static bool
5503 {
5510 }
5512 /* Return true if address offset is a valid index. If it is, fill in INFO
5513 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
5515 static bool
5518 {
5520 rtx index;
5523 /* (reg:P) */
5526 {
5530 }
5531 /* (sign_extend:DI (reg:SI)) */
5536 {
5541 }
5542 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
5549 {
5554 }
5555 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
5562 {
5567 }
5568 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
5575 {
5583 }
5584 /* (and:DI (mult:DI (reg:DI) (const_int scale))
5585 (const_int 0xffffffff<<shift)) */
5592 {
5598 }
5599 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
5606 {
5614 }
5615 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
5616 (const_int 0xffffffff<<shift)) */
5623 {
5629 }
5630 /* (mult:P (reg:P) (const_int scale)) */
5635 {
5639 }
5640 /* (ashift:P (reg:P) (const_int shift)) */
5645 {
5649 }
5650 else
5659 {
5663 }
5664 else
5665 {
5670 }
5674 {
5679 }
5682 }
5684 /* Return true if MODE is one of the modes for which we
5685 support LDP/STP operations. */
5687 static bool
5689 {
5697 }
5699 /* Return true if REGNO is a virtual pointer register, or an eliminable
5700 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
5701 include stack_pointer or hard_frame_pointer. */
5702 static bool
5704 {
5709 }
5711 /* Return true if X is a valid address of type TYPE for machine mode MODE.
5712 If it is, fill in INFO appropriately. STRICT_P is true if
5713 REG_OK_STRICT is in effect. */
5715 static bool
5719 {
5722 poly_int64 offset;
5724 HOST_WIDE_INT const_size;
5726 /* On BE, we use load/store pair for all large int mode load/stores.
5727 TI/TFmode may also use a load/store pair. */
5740 /* For SVE, only accept [Rn], [Rn, Rm, LSL #shift] and
5741 [Rn, #offset, MUL VL]. */
5746 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
5747 REG addressing. */
5749 && !BYTES_BIG_ENDIAN
5757 {
5774 {
5781 }
5786 {
5792 /* TImode and TFmode values are allowed in both pairs of X
5793 registers and individual Q registers. The available
5794 address modes are:
5795 X,X: 7-bit signed scaled offset
5796 Q: 9-bit signed offset
5797 We conservatively require an offset representable in either mode.
5798 When performing the check for pairs of X registers i.e. LDP/STP
5799 pass down DImode since that is the natural size of the LDP/STP
5800 instruction memory accesses. */
5806 /* A 7bit offset check because OImode will emit a ldp/stp
5807 instruction (only big endian will get here).
5808 For ldp/stp instructions, the offset is scaled for the size of a
5809 single element of the pair. */
5813 /* Three 9/12 bit offsets checks because CImode will emit three
5814 ldr/str instructions (only big endian will get here). */
5821 /* Two 7bit offsets checks because XImode will emit two ldp/stp
5822 instructions (only big endian will get here). */
5828 /* Make "m" use the LD1 offset range for SVE data modes, so
5829 that pre-RTL optimizers like ivopts will work to that
5830 instead of the wider LDR/STR range. */
5837 {
5838 poly_int64 end_offset = (offset
5845 end_offset)));
5846 }
5856 else
5859 }
5862 {
5863 /* Look for base + (scaled/extended) index register. */
5866 {
5869 }
5872 {
5875 }
5876 }
5897 {
5901 /* TImode and TFmode values are allowed in both pairs of X
5902 registers and individual Q registers. The available
5903 address modes are:
5904 X,X: 7-bit signed scaled offset
5905 Q: 9-bit signed offset
5906 We conservatively require an offset representable in either mode.
5907 */
5917 else
5919 }
5925 /* load literal: pc-relative constant pool entry. Only supported
5926 for SI mode or larger. */
5932 {
5940 }
5949 {
5955 {
5956 /* The symbol and offset must be aligned to the access size. */
5962 {
5966 }
5972 else
5981 }
5982 }
5987 }
5988 }
5990 /* Return true if the address X is valid for a PRFM instruction.
5991 STRICT_P is true if we should do strict checking with
5992 aarch64_classify_address. */
5994 bool
5996 {
5999 /* PRFM accepts the same addresses as DImode... */
6004 /* ... except writeback forms. */
6006 }
6008 bool
6010 {
6011 rtx offset;
6015 }
6017 /* Classify the base of symbolic expression X. */
6019 enum aarch64_symbol_type
6021 {
6022 rtx offset;
6026 }
6029 /* Return TRUE if X is a legitimate address for accessing memory in
6030 mode MODE. */
6031 static bool
6033 {
6037 }
6039 /* Return TRUE if X is a legitimate address of type TYPE for accessing
6040 memory in mode MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
6041 bool
6043 aarch64_addr_query_type type)
6044 {
6048 }
6050 /* Implement TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT. */
6052 static bool
6054 poly_int64 orig_offset,
6055 machine_mode mode)
6056 {
6057 HOST_WIDE_INT size;
6059 {
6062 /* A general SVE offset is A * VQ + B. Remove the A component from
6063 coefficient 0 in order to get the constant B. */
6066 /* Split an out-of-range address displacement into a base and
6067 offset. Use 4KB range for 1- and 2-byte accesses and a 16KB
6068 range otherwise to increase opportunities for sharing the base
6069 address of different sizes. Unaligned accesses use the signed
6070 9-bit range, TImode/TFmode use the intersection of signed
6071 scaled 7-bit and signed 9-bit offset. */
6076 else
6082 /* Split the offset into second_offset and the rest. */
6086 }
6087 else
6088 {
6089 /* Get the mode we should use as the basis of the range. For structure
6090 modes this is the mode of one vector. */
6092 machine_mode step_mode
6095 /* Get the "mul vl" multiplier we'd like to use. */
6099 /* LDR supports a 9-bit range, but the move patterns for
6100 structure modes require all vectors to be in range of the
6101 same base. The simplest way of accomodating that while still
6102 promoting reuse of anchor points between different modes is
6103 to use an 8-bit range unconditionally. */
6105 else
6106 /* Predicates are only handled singly, so we might as well use
6107 the full range. */
6112 /* Convert the "mul vl" multiplier into a byte offset. */
6117 /* Split the offset into second_offset and the rest. */
6121 }
6122 }
6124 /* Return the binary representation of floating point constant VALUE in INTVAL.
6125 If the value cannot be converted, return false without setting INTVAL.
6126 The conversion is done in the given MODE. */
6127 bool
6129 {
6131 /* We make a general exception for 0. */
6133 {
6136 }
6138 scalar_float_mode mode;
6142 /* Only support up to DF mode. */
6154 {
6158 }
6159 else
6164 }
6166 /* Return TRUE if rtx X is an immediate constant that can be moved using a
6167 single MOV(+MOVK) followed by an FMOV. */
6168 bool
6170 {
6175 /* Determine whether it's cheaper to write float constants as
6176 mov/movk pairs over ldr/adrp pairs. */
6182 {
6184 ? SImode
6189 }
6192 }
6194 /* Return TRUE if rtx X is immediate constant 0.0 */
6195 bool
6197 {
6204 }
6206 /* Return TRUE if rtx X is immediate constant that fits in a single
6207 MOVI immediate operation. */
6208 bool
6210 {
6214 machine_mode vmode;
6215 scalar_int_mode imode;
6220 {
6224 /* We make a general exception for 0. */
6229 }
6233 else
6236 /* use a 64 bit mode for everything except for DI/DF mode, where we use
6237 a 128 bit vector mode. */
6244 }
6247 /* Return the fixed registers used for condition codes. */
6249 static bool
6251 {
6255 }
6257 /* This function is used by the call expanders of the machine description.
6258 RESULT is the register in which the result is returned. It's NULL for
6259 "call" and "sibcall".
6260 MEM is the location of the function call.
6261 SIBCALL indicates whether this function call is normal call or sibling call.
6262 It will generate different pattern accordingly. */
6264 void
6266 {
6268 rtvec vec;
6269 machine_mode mode;
6276 /* Decide if we should generate indirect calls by loading the
6277 address of the callee into a register before performing
6278 the branch-and-link. */
6292 else
6299 }
6301 /* Emit call insn with PAT and do aarch64-specific handling. */
6303 void
6305 {
6311 }
6313 machine_mode
6315 {
6316 /* All floating point compares return CCFP if it is an equality
6317 comparison, and CCFPE otherwise. */
6319 {
6321 {
6342 }
6343 }
6345 /* Equality comparisons of short modes against zero can be performed
6346 using the TST instruction with the appropriate bitmask. */
6352 /* Similarly, comparisons of zero_extends from shorter modes can
6353 be performed using an ANDS with an immediate mask. */
6369 /* A compare with a shifted operand. Because of canonicalization,
6370 the comparison will have to be swapped when we emit the assembly
6371 code. */
6379 /* Similarly for a negated operand, but we can only do this for
6380 equalities. */
6387 /* A test for unsigned overflow. */
6394 /* For everything else, return CCmode. */
6396 }
6398 static int
6401 int
6403 {
6410 }
6412 static int
6414 {
6416 {
6420 {
6434 }
6439 {
6451 }
6456 {
6468 }
6473 {
6479 }
6484 {
6488 }
6493 {
6497 }
6502 }
6505 }
6507 bool
6509 HOST_WIDE_INT minval,
6510 HOST_WIDE_INT maxval)
6511 {
6512 rtx elt;
6516 }
6518 bool
6520 {
6522 }
6524 /* Return true if VEC is a constant in which every element is in the range
6525 [MINVAL, MAXVAL]. The elements do not need to have the same value. */
6527 static bool
6529 HOST_WIDE_INT minval,
6530 HOST_WIDE_INT maxval)
6531 {
6543 {
6548 }
6550 }
6552 /* N Z C V. */
6553 #define AARCH64_CC_V 1
6554 #define AARCH64_CC_C (1 << 1)
6555 #define AARCH64_CC_Z (1 << 2)
6556 #define AARCH64_CC_N (1 << 3)
6558 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
6560 {
6577 };
6579 /* Print floating-point vector immediate operand X to F, negating it
6580 first if NEGATE is true. Return true on success, false if it isn't
6581 a constant we can handle. */
6583 static bool
6585 {
6586 rtx elt;
6595 /* We only handle the SVE single-bit immediates here. */
6602 else
6606 }
6608 /* Return the equivalent letter for size. */
6609 static char
6611 {
6613 {
6619 }
6620 }
6622 /* Print operand X to file F in a target specific manner according to CODE.
6623 The acceptable formatting commands given by CODE are:
6624 'c': An integer or symbol address without a preceding #
6625 sign.
6626 'C': Take the duplicated element in a vector constant
6627 and print it in hex.
6628 'D': Take the duplicated element in a vector constant
6629 and print it as an unsigned integer, in decimal.
6630 'e': Print the sign/zero-extend size as a character 8->b,
6631 16->h, 32->w.
6632 'p': Prints N such that 2^N == X (X must be power of 2 and
6633 const int).
6634 'P': Print the number of non-zero bits in X (a const_int).
6635 'H': Print the higher numbered register of a pair (TImode)
6636 of regs.
6637 'm': Print a condition (eq, ne, etc).
6638 'M': Same as 'm', but invert condition.
6639 'N': Take the duplicated element in a vector constant
6640 and print the negative of it in decimal.
6641 'b/h/s/d/q': Print a scalar FP/SIMD register name.
6642 'S/T/U/V': Print a FP/SIMD register name for a register list.
6643 The register printed is the FP/SIMD register name
6644 of X + 0/1/2/3 for S/T/U/V.
6645 'R': Print a scalar FP/SIMD register name + 1.
6646 'X': Print bottom 16 bits of integer constant in hex.
6647 'w/x': Print a general register name or the zero register
6648 (32-bit or 64-bit).
6649 '0': Print a normal operand, if it's a general register,
6650 then we assume DImode.
6651 'k': Print NZCV for conditional compare instructions.
6652 'A': Output address constant representing the first
6653 argument of X, specifying a relocation offset
6654 if appropriate.
6655 'L': Output constant address specified by X
6656 with a relocation offset if appropriate.
6657 'G': Prints address of X, specifying a PC relative
6658 relocation mode if appropriate.
6659 'y': Output address of LDP or STP - this is used for
6660 some LDP/STPs which don't use a PARALLEL in their
6661 pattern (so the mode needs to be adjusted).
6662 'z': Output address of a typical LDP or STP. */
6664 static void
6666 {
6667 rtx elt;
6669 {
6672 {
6684 {
6687 }
6688 /* Fall through. */
6692 }
6696 {
6701 {
6704 }
6707 {
6720 }
6721 }
6725 {
6729 {
6732 }
6735 }
6740 {
6743 }
6750 {
6753 }
6760 {
6762 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
6764 {
6768 }
6771 {
6774 }
6781 }
6786 {
6789 }
6795 ;
6796 else
6797 {
6800 }
6809 {
6810 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6812 }
6821 {
6822 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6824 }
6832 {
6833 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6835 }
6841 {
6844 }
6849 {
6850 /* Print a replicated constant in hex. */
6852 {
6855 }
6858 }
6862 {
6863 /* Print a replicated constant in decimal, treating it as
6864 unsigned. */
6866 {
6869 }
6872 }
6879 {
6882 }
6885 {
6888 }
6891 {
6894 }
6896 /* Fall through */
6900 {
6903 }
6906 {
6909 {
6912 else
6913 {
6914 char suffix
6919 }
6920 }
6921 else
6940 {
6943 }
6944 /* fall through */
6948 {
6951 }
6957 ;
6958 else
6959 {
6962 }
6966 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
6967 be getting CONST_DOUBLEs holding integers. */
6970 {
6973 }
6975 {
6976 #define buf_size 20
6984 #undef buf_size
6985 }
6991 }
6999 {
7026 }
7032 {
7067 }
7073 {
7079 }
7084 {
7085 HOST_WIDE_INT cond_code;
7088 {
7091 }
7096 }
7101 {
7106 {
7109 }
7112 /* LDP/STP which uses a single double-width memory operand.
7113 Adjust the mode to appear like a typical LDP/STP.
7114 Currently this is supported for 16-byte accesses only. */
7119 }
7125 }
7126 }
7128 /* Print address 'x' of a memory access with mode 'mode'.
7129 'op' is the context required by aarch64_classify_address. It can either be
7130 MEM for a normal memory access or PARALLEL for LDP/STP. */
7131 static bool
7133 aarch64_addr_query_type type)
7134 {
7138 /* Check all addresses are Pmode - including ILP32. */
7144 {
7149 {
7150 HOST_WIDE_INT vnum
7155 }
7157 {
7158 HOST_WIDE_INT vnum
7163 }
7164 else
7173 else
7182 else
7191 else
7197 /* Writeback is only supported for fixed-width modes. */
7200 {
7223 }
7235 }
7238 }
7240 /* Print address 'x' of a LDP/STP with mode 'mode'. */
7241 static bool
7243 {
7245 }
7247 /* Print address 'x' of a memory access with mode 'mode'. */
7248 static void
7250 {
7253 }
7255 bool
7257 {
7264 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
7265 referencing instruction, but they are constant offsets, not
7266 symbols. */
7272 {
7274 {
7280 }
7283 }
7286 }
7288 /* Implement REGNO_REG_CLASS. */
7290 enum reg_class
7292 {
7310 }
7312 /* OFFSET is an address offset for mode MODE, which has SIZE bytes.
7313 If OFFSET is out of range, return an offset of an anchor point
7314 that is in range. Return 0 otherwise. */
7316 static HOST_WIDE_INT
7318 machine_mode mode)
7319 {
7320 /* Does it look like we'll need a 16-byte load/store-pair operation? */
7324 /* For offsets that aren't a multiple of the access size, the limit is
7325 -256...255. */
7327 {
7328 /* BLKmode typically uses LDP of X-registers. */
7332 }
7334 /* Small negative offsets are supported. */
7341 /* Use 12-bit offset by access size. */
7343 }
7345 static rtx
7347 {
7348 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
7349 where mask is selected by alignment and size of the offset.
7350 We try to pick as large a range for the offset as possible to
7351 maximize the chance of a CSE. However, for aligned addresses
7352 we limit the range to 4k so that structures with different sized
7353 elements are likely to use the same base. We need to be careful
7354 not to split a CONST for some forms of address expression, otherwise
7355 it will generate sub-optimal code. */
7358 {
7364 {
7368 /* Force any scaling into a temp for CSE. */
7372 /* Let the pointer register be in op0. */
7376 /* If the pointer is virtual or frame related, then we know that
7377 virtual register instantiation or register elimination is going
7378 to apply a second constant. We want the two constants folded
7379 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
7381 {
7385 }
7387 /* Otherwise, in order to encourage CSE (and thence loop strength
7388 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
7392 }
7394 HOST_WIDE_INT size;
7396 {
7398 mode);
7400 {
7404 }
7405 }
7406 }
7409 }
7411 /* Return the reload icode required for a constant pool in mode. */
7412 static enum insn_code
7414 {
7416 {
7452 }
7455 }
7456 static reg_class_t
7458 reg_class_t rclass,
7459 machine_mode mode,
7461 {
7462 /* Use aarch64_sve_reload_be for SVE reloads that cannot be handled
7463 directly by the *aarch64_sve_mov<mode>_be move pattern. See the
7464 comment at the head of aarch64-sve.md for more details about the
7465 big-endian handling. */
7471 {
7474 }
7476 /* If we have to disable direct literal pool loads and stores because the
7477 function is too big, then we need a scratch register. */
7482 {
7485 }
7487 /* Without the TARGET_SIMD instructions we cannot move a Q register
7488 to a Q register directly. We need a scratch. */
7492 {
7498 }
7500 /* A TFmode or TImode memory access should be handled via an FP_REGS
7501 because AArch64 has richer addressing modes for LDR/STR instructions
7502 than LDP/STP instructions. */
7511 }
7513 static bool
7515 {
7518 /* If we need a frame pointer, ARG_POINTER_REGNUM and FRAME_POINTER_REGNUM
7519 can only eliminate to HARD_FRAME_POINTER_REGNUM. */
7523 }
7525 poly_int64
7527 {
7531 {
7538 }
7541 {
7545 }
7548 }
7550 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
7551 previous frame. */
7553 rtx
7555 {
7559 }
7562 static void
7564 {
7566 {
7569 }
7570 else
7571 {
7574 }
7579 }
7581 static void
7583 {
7587 /* Don't need to copy the trailing D-words, we fill those in below. */
7599 /* XXX We should really define a "clear_cache" pattern and use
7600 gen_clear_cache(). */
7605 ptr_mode);
7606 }
7608 static unsigned char
7610 {
7611 /* ??? Logically we should only need to provide a value when
7612 HARD_REGNO_MODE_OK says that at least one register in REGCLASS
7613 can hold MODE, but at the moment we need to handle all modes.
7614 Just ignore any runtime parts for registers that can't store them. */
7618 {
7644 }
7646 }
7648 static reg_class_t
7650 {
7655 {
7661 }
7663 /* Register eliminiation can result in a request for
7664 SP+constant->FP_REGS. We cannot support such operations which
7665 use SP as source and an FP_REG as destination, so reject out
7666 right now. */
7668 {
7671 /* Look through a possible SUBREG introduced by ILP32. */
7677 POINTER_REGS));
7679 }
7682 }
7684 void
7686 {
7688 }
7690 static void
7692 {
7695 else
7696 {
7698 /* While priority is known to be in range [0, 65535], so 18 bytes
7699 would be enough, the compiler might not know that. To avoid
7700 -Wformat-truncation false positive, use a larger size. */
7707 }
7708 }
7710 static void
7712 {
7715 else
7716 {
7718 /* While priority is known to be in range [0, 65535], so 18 bytes
7719 would be enough, the compiler might not know that. To avoid
7720 -Wformat-truncation false positive, use a larger size. */
7727 }
7728 }
7732 {
7738 {
7739 {
7742 },
7743 {
7746 },
7747 {
7750 },
7751 /* We assume that DImode is only generated when not optimizing and
7752 that we don't really need 64-bit address offsets. That would
7753 imply an object file with 8GB of code in a single function! */
7754 {
7757 }
7758 };
7767 /* Need to implement table size reduction, by chaning the code below. */
7777 }
7780 /* Return size in bits of an arithmetic operand which is shifted/scaled and
7781 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
7782 operator. */
7784 int
7786 {
7788 {
7791 {
7795 }
7796 }
7798 }
7800 /* Constant pools are per function only when PC relative
7801 literal loads are true or we are in the large memory
7802 model. */
7806 {
7809 }
7811 static bool
7813 {
7814 /* We can't use blocks for constants when we're using a per-function
7815 constant pool. */
7817 }
7819 /* Select appropriate section for constants depending
7820 on where we place literal pools. */
7824 rtx x,
7826 {
7831 }
7833 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
7834 void
7836 HOST_WIDE_INT offset)
7837 {
7838 /* When using per-function literal pools, we must ensure that any code
7839 section is aligned to the minimal instruction length, lest we get
7840 errors from the assembler re "unaligned instructions". */
7843 }
7845 /* Costs. */
7847 /* Helper function for rtx cost calculation. Strip a shift expression
7848 from X. Returns the inner operand if successful, or the original
7849 expression on failure. */
7850 static rtx
7852 {
7855 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
7856 we can convert both to ROR during final output. */
7871 }
7873 /* Helper function for rtx cost calculation. Strip an extend
7874 expression from X. Returns the inner operand if successful, or the
7875 original expression on failure. We deal with a number of possible
7876 canonicalization variations here. If STRIP_SHIFT is true, then
7877 we can strip off a shift also. */
7878 static rtx
7880 {
7881 scalar_int_mode mode;
7887 /* Zero and sign extraction of a widened value. */
7895 /* It can also be represented (for zero-extend) as an AND with an
7896 immediate. */
7905 /* Now handle extended register, as this may also have an optional
7906 left shift by 1..4. */
7921 }
7923 /* Return true iff CODE is a shift supported in combination
7924 with arithmetic instructions. */
7926 static bool
7928 {
7930 }
7933 /* Return true iff X is a cheap shift without a sign extend. */
7935 static bool
7937 {
7963 }
7965 /* Helper function for rtx cost calculation. Calculate the cost of
7966 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
7967 Return the calculated cost of the expression, recursing manually in to
7968 operands where needed. */
7970 static int
7972 {
7988 /* Integer multiply/fma. */
7990 {
7991 /* The multiply will be canonicalized as a shift, cost it as such. */
7995 {
7999 {
8001 {
8002 /* If the shift is considered cheap,
8003 then don't add any cost. */
8005 ;
8007 /* ARITH + shift-by-register. */
8010 /* ARITH + extended register. We don't have a cost field
8011 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
8013 else
8014 /* ARITH + shift-by-immediate. */
8016 }
8017 else
8018 /* LSL (immediate). */
8021 }
8022 /* Strip extends as we will have costed them in the case above. */
8029 }
8031 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
8032 compound and let the below cases handle it. After all, MNEG is a
8033 special-case alias of MSUB. */
8035 {
8038 }
8040 /* Integer multiplies or FMAs have zero/sign extending variants. */
8045 {
8050 {
8052 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
8054 else
8055 /* MUL/SMULL/UMULL. */
8057 }
8060 }
8062 /* This is either an integer multiply or a MADD. In both cases
8063 we want to recurse and cost the operands. */
8068 {
8070 /* MADD/MSUB. */
8072 else
8073 /* MUL. */
8075 }
8078 }
8079 else
8080 {
8082 {
8083 /* Floating-point FMA/FMUL can also support negations of the
8084 operands, unless the rounding mode is upward or downward in
8085 which case FNMUL is different than FMUL with operand negation. */
8089 {
8094 }
8097 /* FMADD/FNMADD/FNMSUB/FMSUB. */
8099 else
8100 /* FMUL/FNMUL. */
8102 }
8107 }
8108 }
8110 static int
8112 machine_mode mode,
8113 addr_space_t as ATTRIBUTE_UNUSED,
8115 {
8123 {
8125 {
8126 /* This is a CONST or SYMBOL ref which will be split
8127 in a different way depending on the code model in use.
8128 Cost it through the generic infrastructure. */
8130 /* Divide through by the cost of one instruction to
8131 bring it to the same units as the address costs. */
8133 /* The cost is then the cost of preparing the address,
8134 followed by an immediate (possibly 0) offset. */
8136 }
8137 else
8138 {
8139 /* This is most likely a jump table from a case
8140 statement. */
8142 }
8143 }
8146 {
8158 else
8177 }
8181 {
8182 /* For the sake of calculating the cost of the shifted register
8183 component, we can treat same sized modes in the same way. */
8190 else
8191 /* We can't tell, or this is a 128-bit vector. */
8193 }
8196 }
8198 /* Return the cost of a branch. If SPEED_P is true then the compiler is
8199 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
8200 to be taken. */
8202 int
8204 {
8205 /* When optimizing for speed, use the cost of unpredictable branches. */
8211 else
8213 }
8215 /* Return true if the RTX X in mode MODE is a zero or sign extract
8216 usable in an ADD or SUB (extended register) instruction. */
8217 static bool
8219 {
8220 /* Catch add with a sign extract.
8221 This is add_<optab><mode>_multp2. */
8224 {
8235 op1))
8236 {
8238 }
8239 }
8240 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
8241 No shift. */
8247 }
8249 static bool
8251 {
8253 {
8265 }
8266 }
8268 /* Return true iff X is an rtx that will match an extr instruction
8269 i.e. as described in the *extr<mode>5_insn family of patterns.
8270 OP0 and OP1 will be set to the operands of the shifts involved
8271 on success and will be NULL_RTX otherwise. */
8273 static bool
8275 {
8277 scalar_int_mode mode;
8292 {
8293 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
8305 {
8309 }
8310 }
8313 }
8315 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
8316 storing it in *COST. Result is true if the total cost of the operation
8317 has now been calculated. */
8318 static bool
8320 {
8321 rtx inner;
8322 rtx comparator;
8326 {
8330 }
8331 else
8332 {
8336 }
8339 {
8340 /* Conditional branch. */
8343 else
8344 {
8346 {
8348 {
8349 /* TBZ/TBNZ/CBZ/CBNZ. */
8351 /* TBZ/TBNZ. */
8354 else
8355 /* CBZ/CBNZ. */
8359 }
8360 }
8362 {
8363 /* TBZ/TBNZ. */
8366 }
8367 }
8368 }
8370 {
8371 /* CCMP. */
8373 {
8374 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
8378 {
8385 else
8387 }
8389 }
8391 /* It's a conditional operation based on the status flags,
8392 so it must be some flavor of CSEL. */
8394 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
8400 {
8401 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
8404 }
8409 }
8411 /* We don't know what this is, cost all operands. */
8413 }
8415 /* Check whether X is a bitfield operation of the form shift + extend that
8416 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
8417 operand to which the bitfield operation is applied. Otherwise return
8418 NULL_RTX. */
8420 static rtx
8422 {
8436 {
8454 }
8457 }
8459 /* Return true if the mask and a shift amount from an RTX of the form
8460 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
8461 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
8463 bool
8465 rtx shft_amnt)
8466 {
8471 }
8473 /* Calculate the cost of calculating X, storing it in *COST. Result
8474 is true if the total cost of the operation has now been calculated. */
8475 static bool
8478 {
8483 scalar_int_mode int_mode;
8485 /* By default, assume that everything has equivalent cost to the
8486 cheapest instruction. Any additional costs are applied as a delta
8487 above this default. */
8491 {
8493 /* The cost depends entirely on the operands to SET. */
8499 {
8502 {
8516 }
8525 /* Fall through. */
8527 /* The cost is one per vector-register copied. */
8529 {
8532 }
8533 /* const0_rtx is in general free, but we will use an
8534 instruction to set a register to 0. */
8536 {
8537 /* The cost is 1 per register copied. */
8540 }
8541 else
8542 /* Cost is just the cost of the RHS of the set. */
8548 /* Bit-field insertion. Strip any redundant widening of
8549 the RHS to meet the width of the target. */
8560 {
8561 /* MOV immediate is assumed to always be cheap. */
8563 }
8564 else
8565 {
8566 /* BFM. */
8570 }
8575 /* We can't make sense of this, assume default cost. */
8578 }
8582 /* If an instruction can incorporate a constant within the
8583 instruction, the instruction's expression avoids calling
8584 rtx_cost() on the constant. If rtx_cost() is called on a
8585 constant, then it is usually because the constant must be
8586 moved into a register by one or more instructions.
8588 The exception is constant 0, which can be expressed
8589 as XZR/WZR and is therefore free. The exception to this is
8590 if we have (set (reg) (const0_rtx)) in which case we must cost
8591 the move. However, we can catch that when we cost the SET, so
8592 we don't need to consider that here. */
8595 else
8596 {
8597 /* To an approximation, building any other constant is
8598 proportionally expensive to the number of instructions
8599 required to build that constant. This is true whether we
8600 are compiling for SPEED or otherwise. */
8605 }
8610 /* First determine number of instructions to do the move
8611 as an integer constant. */
8615 {
8621 ? SImode
8627 }
8630 {
8631 /* mov[df,sf]_aarch64. */
8633 /* FMOV (scalar immediate). */
8636 {
8637 /* This will be a load from memory. */
8640 else
8642 }
8643 else
8644 /* Otherwise this is +0.0. We get this using MOVI d0, #0
8645 or MOV v0.s[0], wzr - neither of which are modeled by the
8646 cost tables. Just use the default cost. */
8647 {
8648 }
8649 }
8655 {
8656 /* For loads we want the base cost of a load, plus an
8657 approximation for the additional cost of the addressing
8658 mode. */
8672 }
8680 {
8682 {
8683 /* FNEG. */
8685 }
8687 }
8690 {
8693 {
8694 /* CSETM. */
8697 }
8699 /* Cost this as SUB wzr, X. */
8703 }
8706 {
8707 /* Support (neg(fma...)) as a single instruction only if
8708 sign of zeros is unimportant. This matches the decision
8709 making in aarch64.md. */
8711 {
8712 /* FNMADD. */
8715 }
8717 {
8718 /* FNMUL. */
8721 }
8723 /* FNEG. */
8726 }
8733 {
8736 else
8738 }
8748 {
8752 }
8755 {
8756 /* TODO: A write to the CC flags possibly costs extra, this
8757 needs encoding in the cost tables. */
8760 /* ANDS. */
8762 {
8765 }
8768 {
8769 /* ADDS (and CMN alias). */
8772 }
8775 {
8776 /* SUBS. */
8779 }
8784 {
8785 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
8786 Handle it here directly rather than going to cost_logic
8787 since we know the immediate generated for the TST is valid
8788 so we can avoid creating an intermediate rtx for it only
8789 for costing purposes. */
8796 }
8799 {
8800 /* CMN. */
8807 }
8809 /* CMP.
8811 Compare can freely swap the order of operands, and
8812 canonicalization puts the more complex operation first.
8813 But the integer MINUS logic expects the shift/extend
8814 operation in op1. */
8817 {
8820 }
8822 }
8825 {
8826 /* FCMP. */
8831 {
8833 /* FCMP supports constant 0.0 for no extra cost. */
8835 }
8837 }
8840 {
8841 /* Vector compare. */
8846 {
8847 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
8848 cost. */
8850 }
8852 }
8856 {
8860 cost_minus:
8863 /* Detect valid immediates. */
8869 {
8871 /* SUB(S) (immediate). */
8874 }
8876 /* Look for SUB (extended register). */
8879 {
8887 }
8891 /* Cost this as an FMA-alike operation. */
8895 {
8898 speed);
8900 }
8905 {
8907 {
8908 /* Vector SUB. */
8910 }
8912 {
8913 /* SUB(S). */
8915 }
8917 {
8918 /* FSUB. */
8920 }
8921 }
8923 }
8926 {
8927 rtx new_op0;
8932 cost_plus:
8935 {
8936 /* CSINC. */
8940 }
8945 {
8949 /* ADD (immediate). */
8952 }
8956 /* Look for ADD (extended register). */
8959 {
8967 }
8969 /* Strip any extend, leave shifts behind as we will
8970 cost them through mult_cost. */
8975 {
8977 speed);
8979 }
8984 {
8986 {
8987 /* Vector ADD. */
8989 }
8991 {
8992 /* ADD. */
8994 }
8996 {
8997 /* FADD. */
8999 }
9000 }
9002 }
9008 {
9011 else
9013 }
9018 {
9022 {
9025 else
9027 }
9029 }
9032 {
9039 }
9040 /* Fall through. */
9043 cost_logic:
9048 {
9052 }
9060 {
9061 /* This is a UBFM/SBFM. */
9066 }
9069 {
9071 {
9072 /* We have a mask + shift version of a UBFIZ
9073 i.e. the *andim_ashift<mode>_bfiz pattern. */
9077 {
9084 }
9086 {
9087 /* We possibly get the immediate for free, this is not
9088 modelled. */
9095 }
9096 }
9097 else
9098 {
9101 /* Handle ORN, EON, or BIC. */
9107 /* If we had a shift on op0 then this is a logical-shift-
9108 by-register/immediate operation. Otherwise, this is just
9109 a logical operation. */
9111 {
9113 {
9114 /* Shift by immediate. */
9117 else
9119 }
9120 else
9122 }
9124 /* In both cases we want to cost both operands. */
9131 }
9132 }
9140 {
9141 /* Vector NOT. */
9144 }
9146 /* MVN-shifted-reg. */
9148 {
9155 }
9156 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
9157 Handle the second form here taking care that 'a' in the above can
9158 be a shift. */
9160 {
9169 {
9172 else
9174 }
9177 }
9178 /* MVN. */
9187 /* If a value is written in SI mode, then zero extended to DI
9188 mode, the operation will in general be free as a write to
9189 a 'w' register implicitly zeroes the upper bits of an 'x'
9190 register. However, if this is
9192 (set (reg) (zero_extend (reg)))
9194 we must cost the explicit register move. */
9198 {
9201 /* If OP_COST is non-zero, then the cost of the zero extend
9202 is effectively the cost of the inner operation. Otherwise
9203 we have a MOV instruction and we take the cost from the MOV
9204 itself. This is true independently of whether we are
9205 optimizing for space or time. */
9210 }
9212 {
9213 /* All loads can zero extend to any size for free. */
9216 }
9220 {
9225 }
9228 {
9230 {
9231 /* UMOV. */
9233 }
9234 else
9235 {
9236 /* We generate an AND instead of UXTB/UXTH. */
9238 }
9239 }
9244 {
9245 /* LDRSH. */
9247 {
9254 }
9256 }
9260 {
9265 }
9268 {
9271 else
9273 }
9281 {
9283 {
9285 {
9286 /* Vector shift (immediate). */
9288 }
9289 else
9290 {
9291 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
9292 aliases. */
9294 }
9295 }
9297 /* We can incorporate zero/sign extend for free. */
9304 }
9305 else
9306 {
9308 {
9310 /* Vector shift (register). */
9312 }
9313 else
9314 {
9316 /* LSLV. */
9323 {
9325 /* We already demanded XEXP (op1, 0) to be REG_P, so
9326 don't recurse into it. */
9328 }
9329 }
9331 }
9341 {
9342 /* ASR (immediate) and friends. */
9344 {
9347 else
9349 }
9353 }
9354 else
9355 {
9357 {
9359 /* Vector shift (register). */
9361 }
9362 else
9363 {
9365 /* ASR (register) and friends. */
9372 {
9374 /* We already demanded XEXP (op1, 0) to be REG_P, so
9375 don't recurse into it. */
9377 }
9378 }
9380 }
9386 {
9387 /* LDR. */
9390 }
9393 {
9394 /* ADRP, followed by ADD. */
9398 }
9401 {
9402 /* ADR. */
9405 }
9408 {
9409 /* One extra load instruction, after accessing the GOT. */
9413 }
9418 /* ADRP/ADD (immediate). */
9425 /* UBFX/SBFX. */
9427 {
9430 else
9432 }
9434 /* We can trust that the immediates used will be correct (there
9435 are no by-register forms), so we need only cost op0. */
9441 /* aarch64_rtx_mult_cost always handles recursion to its
9442 operands. */
9446 /* We can expand signed mod by power of 2 using a NEGS, two parallel
9447 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
9448 an unconditional negate. This case should only ever be reached through
9449 the set_smod_pow2_cheap check in expmed.c. */
9453 {
9454 /* We expand to 4 instructions. Reset the baseline. */
9462 }
9464 /* Fall-through. */
9467 {
9468 /* Slighly prefer UMOD over SMOD. */
9475 }
9482 {
9486 /* There is no integer SQRT, so only DIV and UDIV can get
9487 here. */
9489 /* Slighly prefer UDIV over SDIV. */
9491 else
9493 }
9519 {
9522 else
9524 }
9526 /* FMSUB, FNMADD, and FNMSUB are free. */
9533 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
9534 and the by-element operand as operand 0. */
9538 /* Catch vector-by-element operations. The by-element operand can
9539 either be (vec_duplicate (vec_select (x))) or just
9540 (vec_select (x)), depending on whether we are multiplying by
9541 a vector or a scalar.
9543 Canonicalization is not very good in these cases, FMA4 will put the
9544 by-element operand as operand 0, FNMA4 will have it as operand 1. */
9555 /* If the remaining parameters are not registers,
9556 get the cost to put them into registers. */
9570 {
9572 {
9573 /*Vector truncate. */
9575 }
9576 else
9578 }
9583 {
9585 {
9586 /*Vector conversion. */
9588 }
9589 else
9591 }
9597 /* Strip the rounding part. They will all be implemented
9598 by the fcvt* family of instructions anyway. */
9600 {
9609 }
9612 {
9615 else
9617 }
9619 /* We can combine fmul by a power of 2 followed by a fcvt into a single
9620 fixed-point fcvt. */
9625 {
9629 }
9636 {
9637 /* ABS (vector). */
9640 }
9642 {
9645 /* FABD, which is analogous to FADD. */
9647 {
9654 }
9655 /* Simple FABS is analogous to FNEG. */
9658 }
9659 else
9660 {
9661 /* Integer ABS will either be split to
9662 two arithmetic instructions, or will be an ABS
9663 (scalar), which we don't model. */
9667 }
9673 {
9676 else
9677 {
9678 /* FMAXNM/FMINNM/FMAX/FMIN.
9679 TODO: This may not be accurate for all implementations, but
9680 we do not model this in the cost tables. */
9682 }
9683 }
9687 /* The floating point round to integer frint* instructions. */
9689 {
9694 }
9697 {
9702 }
9707 /* Decompose <su>muldi3_highpart. */
9709 mode == DImode
9710 /* (lshiftrt:TI */
9713 /* (mult:TI */
9715 /* (ANY_EXTEND:TI (reg:DI))
9716 (ANY_EXTEND:TI (reg:DI))) */
9723 /* (const_int 64) */
9726 {
9727 /* UMULH/SMULH. */
9735 }
9737 /* Fall through. */
9740 }
9748 }
9750 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
9751 calculated for X. This cost is stored in *COST. Returns true
9752 if the total cost of X was calculated. */
9753 static bool
9756 {
9761 {
9766 }
9769 }
9771 static int
9774 {
9780 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
9787 /* Moving between GPR and stack cost is the same as GP2GP. */
9792 /* To/From the stack register, we move via the gprs. */
9798 {
9799 /* 128-bit operations on general registers require 2 instructions. */
9807 /* When AdvSIMD instructions are disabled it is not possible to move
9808 a 128-bit value directly between Q registers. This is handled in
9809 secondary reload. A general register is used as a scratch to move
9810 the upper DI value and the lower DI value is moved directly,
9811 hence the cost is the sum of three moves. */
9816 }
9826 }
9828 static int
9830 reg_class_t rclass ATTRIBUTE_UNUSED,
9832 {
9834 }
9836 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
9837 to optimize 1.0/sqrt. */
9839 static bool
9841 {
9843 && flag_unsafe_math_optimizations
9847 }
9849 /* Function to decide when to use the approximate reciprocal square root
9850 builtin. */
9852 static tree
9854 {
9860 }
9864 /* Select reciprocal square root initial estimate insn depending on machine
9865 mode. */
9867 static rsqrte_type
9869 {
9871 {
9878 }
9879 }
9883 /* Select reciprocal square root series step insn depending on machine mode. */
9885 static rsqrts_type
9887 {
9889 {
9896 }
9897 }
9899 /* Emit instruction sequence to compute either the approximate square root
9900 or its approximate reciprocal, depending on the flag RECP, and return
9901 whether the sequence was emitted or not. */
9903 bool
9905 {
9909 {
9912 }
9915 {
9922 || flag_trapping_math
9923 || !flag_unsafe_math_optimizations
9926 }
9927 else
9928 /* Caller assumes we cannot fail. */
9934 /* When calculating the approximate square root, compare the
9935 argument with 0.0 and create a mask. */
9941 /* Estimate the approximate reciprocal square root. */
9945 /* Iterate over the series twice for SF and thrice for DF. */
9948 /* Optionally iterate over the series once less for faster performance
9949 while sacrificing the accuracy. */
9952 iterations--;
9954 /* Iterate over the series to calculate the approximate reciprocal square
9955 root. */
9958 {
9966 }
9969 {
9970 /* Qualify the approximate reciprocal square root when the argument is
9971 0.0 by squashing the intermediary result to 0.0. */
9977 /* Calculate the approximate square root. */
9979 }
9981 /* Finalize the approximation. */
9985 }
9989 /* Select reciprocal initial estimate insn depending on machine mode. */
9991 static recpe_type
9993 {
9995 {
10002 }
10003 }
10007 /* Select reciprocal series step insn depending on machine mode. */
10009 static recps_type
10011 {
10013 {
10020 }
10021 }
10023 /* Emit the instruction sequence to compute the approximation for the division
10024 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
10026 bool
10028 {
10039 || flag_trapping_math
10040 || !flag_unsafe_math_optimizations
10048 /* Estimate the approximate reciprocal. */
10052 /* Iterate over the series twice for SF and thrice for DF. */
10055 /* Optionally iterate over the series once less for faster performance,
10056 while sacrificing the accuracy. */
10058 iterations--;
10060 /* Iterate over the series to calculate the approximate reciprocal. */
10063 {
10068 }
10071 {
10072 /* As the approximate reciprocal of DEN is already calculated, only
10073 calculate the approximate division when NUM is not 1.0. */
10076 }
10078 /* Finalize the approximation. */
10081 }
10083 /* Return the number of instructions that can be issued per cycle. */
10084 static int
10086 {
10088 }
10090 static int
10092 {
10096 }
10099 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
10100 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
10101 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
10103 static int
10106 {
10108 }
10111 /* Vectorizer cost model target hooks. */
10113 /* Implement targetm.vectorize.builtin_vectorization_cost. */
10114 static int
10116 tree vectype,
10118 {
10127 {
10178 }
10179 }
10181 /* Implement targetm.vectorize.add_stmt_cost. */
10182 static unsigned
10186 {
10191 {
10196 /* Statements in an inner loop relative to the loop being
10197 vectorized are weighted more heavily. The value here is
10198 arbitrary and could potentially be improved with analysis. */
10204 }
10207 }
10211 /* Parse the TO_PARSE string and put the architecture struct that it
10212 selects into RES and the architectural features into ISA_FLAGS.
10213 Return an aarch64_parse_opt_result describing the parse result.
10214 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
10216 static enum aarch64_parse_opt_result
10219 {
10231 else
10238 /* Loop through the list of supported ARCHes to find a match. */
10240 {
10242 {
10246 {
10247 /* TO_PARSE string contains at least one extension. */
10248 enum aarch64_parse_opt_result ext_res
10253 }
10254 /* Extension parsing was successful. Confirm the result
10255 arch and ISA flags. */
10259 }
10260 }
10262 /* ARCH name not found in list. */
10264 }
10266 /* Parse the TO_PARSE string and put the result tuning in RES and the
10267 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
10268 describing the parse result. If there is an error parsing, RES and
10269 ISA_FLAGS are left unchanged. */
10271 static enum aarch64_parse_opt_result
10274 {
10286 else
10293 /* Loop through the list of supported CPUs to find a match. */
10295 {
10297 {
10302 {
10303 /* TO_PARSE string contains at least one extension. */
10304 enum aarch64_parse_opt_result ext_res
10309 }
10310 /* Extension parsing was successfull. Confirm the result
10311 cpu and ISA flags. */
10315 }
10316 }
10318 /* CPU name not found in list. */
10320 }
10322 /* Parse the TO_PARSE string and put the cpu it selects into RES.
10323 Return an aarch64_parse_opt_result describing the parse result.
10324 If the parsing fails the RES does not change. */
10326 static enum aarch64_parse_opt_result
10328 {
10334 /* Loop through the list of supported CPUs to find a match. */
10336 {
10338 {
10341 }
10342 }
10344 /* CPU name not found in list. */
10346 }
10348 /* Parse TOKEN, which has length LENGTH to see if it is an option
10349 described in FLAG. If it is, return the index bit for that fusion type.
10350 If not, error (printing OPTION_NAME) and return zero. */
10352 static unsigned int
10357 {
10359 {
10363 }
10367 }
10369 /* Parse OPTION which is a comma-separated list of flags to enable.
10370 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
10371 default state we inherit from the CPU tuning structures. OPTION_NAME
10372 gives the top-level option we are parsing in the -moverride string,
10373 for use in error messages. */
10375 static unsigned int
10380 {
10387 {
10390 token_length,
10391 flags,
10392 option_name);
10393 /* If we find "none" (or, for simplicity's sake, an error) anywhere
10394 in the token stream, reset the supported operations. So:
10396 adrp+add.cmp+branch.none.adrp+add
10398 would have the result of turning on only adrp+add fusion. */
10404 }
10406 /* We ended with a comma, print something. */
10408 {
10411 }
10413 /* We still have one more token to parse. */
10416 token_length,
10417 flags,
10418 option_name);
10424 }
10426 /* Support for overriding instruction fusion. */
10428 static void
10431 {
10433 aarch64_fusible_pairs,
10436 }
10438 /* Support for overriding other tuning flags. */
10440 static void
10443 {
10444 tune->extra_tuning_flags
10446 aarch64_tuning_flags,
10449 }
10451 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
10452 we understand. If it is, extract the option string and handoff to
10453 the appropriate function. */
10455 void
10459 {
10465 {
10468 }
10470 /* Get the length of the option name. */
10472 /* Skip the '=' to get to the option string. */
10473 option_part++;
10476 {
10478 {
10481 }
10482 }
10486 }
10488 /* A checking mechanism for the implementation of the tls size. */
10490 static void
10492 {
10497 {
10499 /* Both the default and maximum TLS size allowed under tiny is 1M which
10500 needs two instructions to address, so we clamp the size to 24. */
10505 /* The maximum TLS size allowed under small is 4G. */
10510 /* The maximum TLS size allowed under large is 16E.
10511 FIXME: 16E should be 64bit, we only support 48bit offset now. */
10517 }
10520 }
10522 /* Parse STRING looking for options in the format:
10523 string :: option:string
10524 option :: name=substring
10525 name :: {a-z}
10526 substring :: defined by option. */
10528 static void
10531 {
10542 {
10544 /* Make this substring look like a string. */
10548 }
10550 /* One last option to parse. */
10553 }
10556 static void
10558 {
10559 /* PR 70044: We have to be careful about being called multiple times for the
10560 same function. This means all changes should be repeatable. */
10562 /* Set aarch64_use_frame_pointer based on -fno-omit-frame-pointer.
10563 Disable the frame pointer flag so the mid-end will not use a frame
10564 pointer in leaf functions in order to support -fomit-leaf-frame-pointer.
10565 Set x_flag_omit_frame_pointer to the special value 2 to differentiate
10566 between -fomit-frame-pointer (1) and -fno-omit-frame-pointer (2). */
10571 /* If not optimizing for size, set the default
10572 alignment to what the target wants. */
10574 {
10581 }
10583 /* We default to no pc-relative literal loads. */
10587 /* If -mpc-relative-literal-loads is set on the command line, this
10588 implies that the user asked for PC relative literal loads. */
10592 /* In the tiny memory model it makes no sense to disallow PC relative
10593 literal pool loads. */
10598 /* When enabling the lower precision Newton series for the square root, also
10599 enable it for the reciprocal square root, since the latter is an
10600 intermediary step for the former. */
10603 }
10605 /* 'Unpack' up the internal tuning structs and update the options
10606 in OPTS. The caller must have set up selected_tune and selected_arch
10607 as all the other target-specific codegen decisions are
10608 derived from them. */
10610 void
10612 {
10615 /* Make a copy of the tuning parameters attached to the core, which
10616 we may later overwrite. */
10624 /* This target defaults to strict volatile bitfields. */
10633 {
10645 }
10647 /* We don't mind passing in global_options_set here as we don't use
10648 the *options_set structs anyway. */
10650 queue_depth,
10654 /* Set up parameters to be used in prefetching algorithm. Do not
10655 override the defaults unless we are tuning for a core we have
10656 researched values for. */
10688 /* Use the alternative scheduling-pressure algorithm by default. */
10693 /* Enable sw prefetching at specified optimization level for
10694 CPUS that have prefetch. Lower optimization level threshold by 1
10695 when profiling is enabled. */
10703 }
10705 /* Print a hint with a suggestion for a core or architecture name that
10706 most closely resembles what the user passed in STR. ARCH is true if
10707 the user is asking for an architecture name. ARCH is false if the user
10708 is asking for a core name. */
10710 static void
10712 {
10718 #ifdef HAVE_LOCAL_CPU_DETECT
10719 /* Add also "native" as possible value. */
10722 #endif
10729 else
10733 }
10735 /* Print a hint with a suggestion for a core name that most closely resembles
10736 what the user passed in STR. */
10740 {
10742 }
10744 /* Print a hint with a suggestion for an architecture name that most closely
10745 resembles what the user passed in STR. */
10749 {
10751 }
10753 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
10754 specified in STR and throw errors if appropriate. Put the results if
10755 they are valid in RES and ISA_FLAGS. Return whether the option is
10756 valid. */
10758 static bool
10761 {
10762 enum aarch64_parse_opt_result parse_res
10769 {
10782 }
10785 }
10787 /* Validate a command-line -march option. Parse the arch and extensions
10788 (if any) specified in STR and throw errors if appropriate. Put the
10789 results, if they are valid, in RES and ISA_FLAGS. Return whether the
10790 option is valid. */
10792 static bool
10795 {
10796 enum aarch64_parse_opt_result parse_res
10803 {
10816 }
10819 }
10821 /* Validate a command-line -mtune option. Parse the cpu
10822 specified in STR and throw errors if appropriate. Put the
10823 result, if it is valid, in RES. Return whether the option is
10824 valid. */
10826 static bool
10828 {
10829 enum aarch64_parse_opt_result parse_res
10836 {
10846 }
10848 }
10850 /* Return the CPU corresponding to the enum CPU.
10851 If it doesn't specify a cpu, return the default. */
10855 {
10859 /* The & 0x3f is to extract the bottom 6 bits that encode the
10860 default cpu as selected by the --with-cpu GCC configure option
10861 in config.gcc.
10862 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
10863 flags mechanism should be reworked to make it more sane. */
10865 }
10867 /* Return the architecture corresponding to the enum ARCH.
10868 If it doesn't specify a valid architecture, return the default. */
10872 {
10879 }
10881 /* Return the VG value associated with -msve-vector-bits= value VALUE. */
10883 static poly_uint16
10885 {
10886 /* For now generate vector-length agnostic code for -msve-vector-bits=128.
10887 This ensures we can clearly distinguish SVE and Advanced SIMD modes when
10888 deciding which .md file patterns to use and when deciding whether
10889 something is a legitimate address or constant. */
10892 else
10894 }
10896 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
10897 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
10898 tuning structs. In particular it must set selected_tune and
10899 aarch64_isa_flags that define the available ISA features and tuning
10900 decisions. It must also set selected_arch as this will be used to
10901 output the .arch asm tags for each function. */
10903 static void
10905 {
10918 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
10919 If either of -march or -mtune is given, they override their
10920 respective component of -mcpu. */
10932 /* If the user did not specify a processor, choose the default
10933 one for them. This will be the CPU set during configuration using
10934 --with-cpu, otherwise it is "generic". */
10936 {
10938 {
10942 }
10943 else
10944 {
10945 /* Get default configure-time CPU. */
10948 }
10952 }
10953 /* If both -mcpu and -march are specified check that they are architecturally
10954 compatible, warn if they're not and prefer the -march ISA flags. */
10956 {
10958 {
10962 }
10967 }
10968 else
10969 {
10970 /* -mcpu but no -march. */
10977 }
10979 /* Set the arch as well as we will need it when outputing
10980 the .arch directive in assembly. */
10982 {
10985 }
10990 #ifndef HAVE_AS_MABI_OPTION
10991 /* The compiler may have been configured with 2.23.* binutils, which does
10992 not have support for ILP32. */
10995 #endif
10997 /* Convert -msve-vector-bits to a VG count. */
11003 /* Make sure we properly set up the explicit options. */
11014 /* Save these options as the default ones in case we push and pop them later
11015 while processing functions with potential target attributes. */
11016 target_option_default_node = target_option_current_node
11018 }
11020 /* Implement targetm.override_options_after_change. */
11022 static void
11024 {
11026 }
11030 {
11034 }
11036 void
11038 {
11040 }
11042 /* A checking mechanism for the implementation of the various code models. */
11043 static void
11045 {
11047 {
11049 {
11054 #ifdef HAVE_AS_SMALL_PIC_RELOCS
11056 ? AARCH64_CMODEL_SMALL_PIC
11058 #else
11060 #endif
11068 }
11069 }
11070 else
11072 }
11074 /* Implement TARGET_OPTION_SAVE. */
11076 static void
11078 {
11080 }
11082 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
11083 using the information saved in PTR. */
11085 static void
11087 {
11095 }
11097 /* Implement TARGET_OPTION_PRINT. */
11099 static void
11101 {
11112 }
11116 void
11118 {
11120 }
11122 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
11123 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
11124 make sure optab availability predicates are recomputed when necessary. */
11126 void
11128 {
11133 else
11135 }
11137 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
11138 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
11139 of the function, if such exists. This function may be called multiple
11140 times on a single function so use aarch64_previous_fndecl to avoid
11141 setting up identical state. */
11143 static void
11145 {
11149 tree old_tree = (aarch64_previous_fndecl
11155 /* If current function has no attributes but the previous one did,
11156 use the default node. */
11160 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
11161 the default have been handled by aarch64_save_restore_target_globals from
11162 aarch64_pragma_target_parse. */
11168 /* First set the target options. */
11172 }
11174 /* Enum describing the various ways we can handle attributes.
11175 In many cases we can reuse the generic option handling machinery. */
11177 enum aarch64_attr_opt_type
11178 {
11182 aarch64_attr_custom /* Attribute requires a custom handling function. */
11183 };
11185 /* All the information needed to handle a target attribute.
11186 NAME is the name of the attribute.
11187 ATTR_TYPE specifies the type of behavior of the attribute as described
11188 in the definition of enum aarch64_attr_opt_type.
11189 ALLOW_NEG is true if the attribute supports a "no-" form.
11190 HANDLER is the function that takes the attribute string as an argument
11191 It is needed only when the ATTR_TYPE is aarch64_attr_custom.
11192 OPT_NUM is the enum specifying the option that the attribute modifies.
11193 This is needed for attributes that mirror the behavior of a command-line
11194 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
11195 aarch64_attr_enum. */
11197 struct aarch64_attribute_info
11198 {
11204 };
11206 /* Handle the ARCH_STR argument to the arch= target attribute. */
11208 static bool
11210 {
11212 enum aarch64_parse_opt_result parse_res
11216 {
11221 }
11224 {
11237 }
11240 }
11242 /* Handle the argument CPU_STR to the cpu= target attribute. */
11244 static bool
11246 {
11248 enum aarch64_parse_opt_result parse_res
11252 {
11260 }
11263 {
11276 }
11279 }
11281 /* Handle the argument STR to the tune= target attribute. */
11283 static bool
11285 {
11287 enum aarch64_parse_opt_result parse_res
11291 {
11296 }
11299 {
11306 }
11309 }
11311 /* Parse an architecture extensions target attribute string specified in STR.
11312 For example "+fp+nosimd". Show any errors if needed. Return TRUE
11313 if successful. Update aarch64_isa_flags to reflect the ISA features
11314 modified. */
11316 static bool
11318 {
11322 /* We allow "+nothing" in the beginning to clear out all architectural
11323 features if the user wants to handpick specific features. */
11325 {
11328 }
11333 {
11336 }
11339 {
11350 }
11353 }
11355 /* The target attributes that we support. On top of these we also support just
11356 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
11357 handled explicitly in aarch64_process_one_target_attr. */
11360 {
11362 OPT_mgeneral_regs_only },
11364 OPT_mfix_cortex_a53_835769 },
11366 OPT_mfix_cortex_a53_843419 },
11370 OPT_momit_leaf_frame_pointer },
11373 OPT_march_ },
11376 OPT_mtune_ },
11378 OPT_msign_return_address_ },
11380 };
11382 /* Parse ARG_STR which contains the definition of one target attribute.
11383 Show appropriate errors if any or return true if the attribute is valid. */
11385 static bool
11387 {
11393 {
11396 }
11401 /* Skip leading whitespace. */
11403 str_to_check++;
11405 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
11406 It is easier to detect and handle it explicitly here rather than going
11407 through the machinery for the rest of the target attributes in this
11408 function. */
11413 {
11416 }
11419 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
11420 and point ARG to "foo". */
11422 {
11424 arg++;
11425 }
11429 {
11430 /* If the names don't match up, or the user has given an argument
11431 to an attribute that doesn't accept one, or didn't give an argument
11432 to an attribute that expects one, fail to match. */
11441 {
11444 }
11446 /* If the name matches but the attribute does not allow "no-" versions
11447 then we can't match. */
11449 {
11452 }
11455 {
11456 /* Has a custom handler registered.
11457 For example, cpu=, arch=, tune=. */
11464 /* Either set or unset a boolean option. */
11466 {
11474 }
11475 /* Set or unset a bit in the target_flags. aarch64_handle_option
11476 should know what mask to apply given the option number. */
11478 {
11480 /* We only need to specify the option number.
11481 aarch64_handle_option will know which mask to apply. */
11487 }
11488 /* Use the option setting machinery to set an option to an enum. */
11490 {
11497 {
11500 global_dc);
11501 }
11502 else
11503 {
11505 }
11507 }
11510 }
11511 }
11513 /* If we reached here we either have found an attribute and validated
11514 it or didn't match any. If we matched an attribute but its arguments
11515 were malformed we will have returned false already. */
11517 }
11519 /* Count how many times the character C appears in
11520 NULL-terminated string STR. */
11522 static unsigned int
11524 {
11527 {
11529 res++;
11531 str++;
11532 }
11535 }
11537 /* Parse the tree in ARGS that contains the target attribute information
11538 and update the global target options space. */
11540 bool
11542 {
11544 {
11545 do
11546 {
11549 {
11552 }
11557 }
11560 {
11563 }
11570 {
11573 }
11575 /* Used to catch empty spaces between commas i.e.
11576 attribute ((target ("attr1,,attr2"))). */
11579 /* Handle multiple target attributes separated by ','. */
11584 {
11585 num_attrs++;
11587 {
11590 }
11593 }
11596 {
11599 }
11602 }
11604 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
11605 process attribute ((target ("..."))). */
11607 static bool
11609 {
11612 tree old_optimize;
11616 /* If what we're processing is the current pragma string then the
11617 target option node is already stored in target_option_current_node
11618 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
11619 having to re-parse the string. This is especially useful to keep
11620 arm_neon.h compile times down since that header contains a lot
11621 of intrinsics enclosed in pragmas. */
11623 {
11626 }
11632 /* If the function changed the optimization levels as well as setting
11633 target options, start with the optimizations specified. */
11638 /* Save the current target options to restore at the end. */
11641 /* If fndecl already has some target attributes applied to it, unpack
11642 them so that we add this attribute on top of them, rather than
11643 overwriting them. */
11645 {
11651 }
11652 else
11658 /* Set up any additional state. */
11660 {
11662 /* Initialize SIMD builtins if we haven't already.
11663 Set current_target_pragma to NULL for the duration so that
11664 the builtin initialization code doesn't try to tag the functions
11665 being built with the attributes specified by any current pragma, thus
11666 going into an infinite recursion. */
11668 {
11673 }
11675 }
11676 else
11682 {
11687 }
11695 }
11697 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
11698 tri-bool options (yes, no, don't care) and the default value is
11699 DEF, determine whether to reject inlining. */
11701 static bool
11704 {
11705 /* If the callee doesn't care, always allow inlining. */
11709 /* If the caller doesn't care, always allow inlining. */
11713 /* Otherwise, allow inlining if either the callee and caller values
11714 agree, or if the callee is using the default value. */
11716 }
11718 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
11719 to inline CALLEE into CALLER based on target-specific info.
11720 Make sure that the caller and callee have compatible architectural
11721 features. Then go through the other possible target attributes
11722 and see if they can block inlining. Try not to reject always_inline
11723 callees unless they are incompatible architecturally. */
11725 static bool
11727 {
11739 /* Callee's ISA flags should be a subset of the caller's. */
11744 /* Allow non-strict aligned functions inlining into strict
11745 aligned ones. */
11755 /* If the architectural features match up and the callee is always_inline
11756 then the other attributes don't matter. */
11768 /* Honour explicit requests to workaround errata. */
11781 /* If the user explicitly specified -momit-leaf-frame-pointer for the
11782 caller and calle and they don't match up, reject inlining. */
11789 /* If the callee has specific tuning overrides, respect them. */
11794 /* If the user specified tuning override strings for the
11795 caller and callee and they don't match up, reject inlining.
11796 We just do a string compare here, we don't analyze the meaning
11797 of the string, as it would be too costly for little gain. */
11805 }
11807 /* Return true if SYMBOL_REF X binds locally. */
11809 static bool
11811 {
11815 }
11817 /* Return true if SYMBOL_REF X is thread local */
11818 static bool
11820 {
11828 }
11830 /* Classify a TLS symbol into one of the TLS kinds. */
11831 enum aarch64_symbol_type
11833 {
11837 {
11844 {
11850 }
11861 else
11870 }
11871 }
11873 /* Return the correct method for accessing X + OFFSET, where X is either
11874 a SYMBOL_REF or LABEL_REF. */
11876 enum aarch64_symbol_type
11878 {
11880 {
11882 {
11897 }
11898 }
11901 {
11906 {
11908 /* When we retrieve symbol + offset address, we have to make sure
11909 the offset does not cause overflow of the final address. But
11910 we have no way of knowing the address of symbol at compile time
11911 so we can't accurately say if the distance between the PC and
11912 symbol + offset is outside the addressible range of +/-1M in the
11913 TINY code model. So we rely on images not being greater than
11914 1M and cap the offset at 1M and anything beyond 1M will have to
11915 be loaded using an alternative mechanism. Furthermore if the
11916 symbol is a weak reference to something that isn't known to
11917 resolve to a symbol in this module, then force to memory. */
11925 /* Same reasoning as the tiny code model, but the offset cap here is
11926 4G. */
11947 /* This is alright even in PIC code as the constant
11948 pool reference is always PC relative and within
11949 the same translation unit. */
11952 else
11957 }
11958 }
11960 /* By default push everything into the constant pool. */
11962 }
11964 bool
11966 {
11968 }
11970 bool
11972 {
11980 }
11982 /* Implement TARGET_LEGITIMATE_CONSTANT_P hook. Return true for constants
11983 that should be rematerialized rather than spilled. */
11985 static bool
11987 {
11988 /* Support CSE and rematerialization of common constants. */
11994 /* Do not allow vector struct mode constants for Advanced SIMD.
11995 We could support 0 and -1 easily, but they need support in
11996 aarch64-simd.md. */
12001 /* Only accept variable-length vector constants if they can be
12002 handled directly.
12004 ??? It would be possible to handle rematerialization of other
12005 constants via secondary reloads. */
12012 /* Accept polynomial constants that can be calculated by using the
12013 destination of a move as the sole temporary. Constants that
12014 require a second temporary cannot be rematerialized (they can't be
12015 forced to memory and also aren't legitimate constants). */
12016 poly_int64 offset;
12020 /* If an offset is being added to something else, we need to allow the
12021 base to be moved into the destination register, meaning that there
12022 are no free temporaries for the offset. */
12027 /* Do not allow const (plus (anchor_symbol, const_int)). */
12031 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
12032 so spilling them is better than rematerialization. */
12036 /* Label references are always constant. */
12041 }
12043 rtx
12045 {
12051 /* Can return in any reg. */
12054 }
12056 /* On AAPCS systems, this is the "struct __va_list". */
12059 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
12060 Return the type to use as __builtin_va_list.
12062 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
12064 struct __va_list
12065 {
12066 void *__stack;
12067 void *__gr_top;
12068 void *__vr_top;
12069 int __gr_offs;
12070 int __vr_offs;
12071 }; */
12073 static tree
12075 {
12076 tree va_list_name;
12079 /* Create the type. */
12081 /* Give it the required name. */
12083 TYPE_DECL,
12085 va_list_type);
12090 /* Create the fields. */
12093 ptr_type_node);
12096 ptr_type_node);
12099 ptr_type_node);
12102 integer_type_node);
12105 integer_type_node);
12107 /* Tell tree-stdarg pass about our internal offset fields.
12108 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
12109 purpose to identify whether the code is updating va_list internal
12110 offset fields through irregular way. */
12132 /* Compute its layout. */
12136 }
12138 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
12139 static void
12141 {
12145 tree t;
12159 {
12162 }
12171 NULL_TREE);
12173 NULL_TREE);
12175 NULL_TREE);
12177 NULL_TREE);
12179 NULL_TREE);
12181 /* Emit code to initialize STACK, which points to the next varargs stack
12182 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
12183 by named arguments. STACK is 8-byte aligned. */
12190 /* Emit code to initialize GRTOP, the top of the GR save area.
12191 virtual_incoming_args_rtx should have been 16 byte aligned. */
12196 /* Emit code to initialize VRTOP, the top of the VR save area.
12197 This address is gr_save_area_bytes below GRTOP, rounded
12198 down to the next 16-byte boundary. */
12208 /* Emit code to initialize GROFF, the offset from GRTOP of the
12209 next GPR argument. */
12214 /* Likewise emit code to initialize VROFF, the offset from FTOP
12215 of the next VR argument. */
12219 }
12221 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
12223 static tree
12226 {
12227 tree addr;
12233 machine_mode mode;
12260 type,
12264 {
12265 /* No frontends can create types with variable-sized modes, so we
12266 shouldn't be asked to pass or return them. */
12269 /* TYPE passed in fp/simd registers. */
12281 {
12284 }
12287 {
12289 }
12290 }
12291 else
12292 {
12293 /* TYPE passed in general registers. */
12306 {
12308 }
12309 }
12311 /* Get a local temporary for the field value. */
12314 /* Emit code to branch if off >= 0. */
12320 {
12321 /* Emit: offs = (offs + 15) & -16. */
12327 }
12328 else
12331 /* Update ap.__[g|v]r_offs */
12336 /* String up. */
12340 /* [cond2] if (ap.__[g|v]r_offs > 0) */
12345 /* String up: make sure the assignment happens before the use. */
12349 /* Prepare the trees handling the argument that is passed on the stack;
12350 the top level node will store in ON_STACK. */
12353 {
12354 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
12359 }
12360 else
12362 /* Advance ap.__stack */
12367 /* String up roundup and advance. */
12370 /* String up with arg */
12372 /* Big-endianness related address adjustment. */
12375 {
12379 }
12384 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
12394 {
12395 /* type ha; // treat as "struct {ftype field[n];}"
12396 ... [computing offs]
12397 for (i = 0; i <nregs; ++i, offs += 16)
12398 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
12399 return ha; */
12403 /* Declare a local variable. */
12407 /* Establish the base type. */
12409 {
12428 {
12432 }
12436 }
12438 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
12446 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
12448 {
12458 }
12462 }
12472 }
12474 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
12476 static void
12480 {
12482 CUMULATIVE_ARGS local_cum;
12486 /* The caller has advanced CUM up to, but not beyond, the last named
12487 argument. Advance a local copy of CUM past the last "real" named
12488 argument, to find out how many registers are left over. */
12492 /* Found out how many registers we need to save.
12493 Honor tree-stdvar analysis results. */
12502 {
12505 }
12508 {
12510 {
12513 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
12521 }
12523 {
12524 /* We can't use move_block_from_reg, because it will use
12525 the wrong mode, storing D regs only. */
12529 /* Set OFF to the offset from virtual_incoming_args_rtx of
12530 the first vector register. The VR save area lies below
12531 the GR one, and is aligned to 16 bytes. */
12538 {
12546 }
12547 }
12548 }
12550 /* We don't save the size into *PRETEND_SIZE because we want to avoid
12551 any complication of having crtl->args.pretend_args_size changed. */
12556 }
12558 static void
12560 {
12563 {
12565 {
12568 }
12569 }
12572 {
12575 }
12576 }
12578 /* Walk down the type tree of TYPE counting consecutive base elements.
12579 If *MODEP is VOIDmode, then set it to the first valid floating point
12580 type. If a non-floating point type is found, or if a floating point
12581 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
12582 otherwise return the count in the sub-tree. */
12583 static int
12585 {
12586 machine_mode mode;
12587 HOST_WIDE_INT size;
12590 {
12620 /* Use V2SImode and V4SImode as representatives of all 64-bit
12621 and 128-bit vector types. */
12624 {
12633 }
12638 /* Vector modes are considered to be opaque: two vectors are
12639 equivalent for the purposes of being homogeneous aggregates
12640 if they are the same size. */
12647 {
12651 /* Can't handle incomplete types nor sizes that are not
12652 fixed. */
12659 || !index
12670 /* There must be no padding. */
12676 }
12679 {
12682 tree field;
12684 /* Can't handle incomplete types nor sizes that are not
12685 fixed. */
12691 {
12699 }
12701 /* There must be no padding. */
12707 }
12711 {
12712 /* These aren't very interesting except in a degenerate case. */
12715 tree field;
12717 /* Can't handle incomplete types nor sizes that are not
12718 fixed. */
12724 {
12732 }
12734 /* There must be no padding. */
12740 }
12744 }
12747 }
12749 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
12750 type as described in AAPCS64 \S 4.1.2.
12752 See the comment above aarch64_composite_type_p for the notes on MODE. */
12754 static bool
12756 machine_mode mode)
12757 {
12767 }
12769 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
12770 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
12771 array types. The C99 floating-point complex types are also considered
12772 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
12773 types, which are GCC extensions and out of the scope of AAPCS64, are
12774 treated as composite types here as well.
12776 Note that MODE itself is not sufficient in determining whether a type
12777 is such a composite type or not. This is because
12778 stor-layout.c:compute_record_mode may have already changed the MODE
12779 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
12780 structure with only one field may have its MODE set to the mode of the
12781 field. Also an integer mode whose size matches the size of the
12782 RECORD_TYPE type may be used to substitute the original mode
12783 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
12784 solely relied on. */
12786 static bool
12788 machine_mode mode)
12789 {
12802 }
12804 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
12805 shall be passed or returned in simd/fp register(s) (providing these
12806 parameter passing registers are available).
12808 Upon successful return, *COUNT returns the number of needed registers,
12809 *BASE_MODE returns the mode of the individual register and when IS_HAF
12810 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
12811 floating-point aggregate or a homogeneous short-vector aggregate. */
12813 static bool
12815 const_tree type,
12819 {
12827 {
12830 }
12832 {
12836 }
12838 {
12842 {
12845 }
12846 else
12848 }
12849 else
12854 }
12856 /* Implement TARGET_STRUCT_VALUE_RTX. */
12858 static rtx
12861 {
12863 }
12865 /* Implements target hook vector_mode_supported_p. */
12866 static bool
12868 {
12871 }
12873 /* Return appropriate SIMD container
12874 for MODE within a vector of WIDTH bits. */
12875 static machine_mode
12877 {
12880 {
12897 }
12901 {
12904 {
12921 }
12922 else
12924 {
12937 }
12938 }
12940 }
12942 /* Return 128-bit container as the preferred SIMD mode for MODE. */
12943 static machine_mode
12945 {
12948 }
12950 /* Return a list of possible vector sizes for the vectorizer
12951 to iterate over. */
12952 static void
12954 {
12959 }
12961 /* Implement TARGET_MANGLE_TYPE. */
12965 {
12966 /* The AArch64 ABI documents say that "__va_list" has to be
12967 managled as if it is in the "std" namespace. */
12971 /* Half-precision float. */
12975 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
12976 builtin types. */
12980 /* Use the default mangling. */
12982 }
12984 /* Find the first rtx_insn before insn that will generate an assembly
12985 instruction. */
12989 {
12993 do
12994 {
12996 }
13000 }
13002 static bool
13004 {
13006 /* A number of these may be AArch32 only. */
13011 };
13014 {
13017 }
13020 }
13022 /* Check if there is a register dependency between a load and the insn
13023 for which we hold recog_data. */
13025 static bool
13027 {
13028 rtx load_reg;
13038 {
13044 }
13046 }
13049 /* When working around the Cortex-A53 erratum 835769,
13050 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
13051 instruction and has a preceding memory instruction such that a NOP
13052 should be inserted between them. */
13054 bool
13056 {
13059 rtx body;
13072 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
13073 Restore recog state to INSN to avoid state corruption. */
13081 /* If the previous insn is a memory op and there is no dependency between
13082 it and the DImode madd, emit a NOP between them. If body is NULL then we
13083 have a complex memory operation, probably a load/store pair.
13084 Be conservative for now and emit a NOP. */
13091 }
13094 /* Implement FINAL_PRESCAN_INSN. */
13096 void
13098 {
13101 }
13104 /* Return true if BASE_OR_STEP is a valid immediate operand for an SVE INDEX
13105 instruction. */
13107 bool
13109 {
13112 }
13114 /* Return true if X is a valid immediate for the SVE ADD and SUB
13115 instructions. Negate X first if NEGATE_P is true. */
13117 bool
13119 {
13120 rtx elt;
13134 }
13136 /* Return true if X is a valid immediate operand for an SVE logical
13137 instruction such as AND. */
13139 bool
13141 {
13142 rtx elt;
13148 }
13150 /* Return true if X is a valid immediate for the SVE DUP and CPY
13151 instructions. */
13153 bool
13155 {
13156 rtx elt;
13166 }
13168 /* Return true if X is a valid immediate operand for an SVE CMP instruction.
13169 SIGNED_P says whether the operand is signed rather than unsigned. */
13171 bool
13173 {
13174 rtx elt;
13178 && (signed_p
13181 }
13183 /* Return true if X is a valid immediate operand for an SVE FADD or FSUB
13184 instruction. Negate X first if NEGATE_P is true. */
13186 bool
13188 {
13189 rtx elt;
13190 REAL_VALUE_TYPE r;
13206 }
13208 /* Return true if X is a valid immediate operand for an SVE FMUL
13209 instruction. */
13211 bool
13213 {
13214 rtx elt;
13216 /* GCC will never generate a multiply with an immediate of 2, so there is no
13217 point testing for it (even though it is a valid constant). */
13221 }
13223 /* Return true if replicating VAL32 is a valid 2-byte or 4-byte immediate
13224 for the Advanced SIMD operation described by WHICH and INSN. If INFO
13225 is nonnull, use it to describe valid immediates. */
13226 static bool
13231 {
13232 /* Try a 4-byte immediate with LSL. */
13235 {
13240 }
13242 /* Try a 2-byte immediate with LSL. */
13247 {
13252 }
13254 /* Try a 4-byte immediate with MSL, except for cases that MVN
13255 can handle. */
13258 {
13261 {
13266 }
13267 }
13270 }
13272 /* Return true if replicating VAL64 is a valid immediate for the
13273 Advanced SIMD operation described by WHICH. If INFO is nonnull,
13274 use it to describe valid immediates. */
13275 static bool
13279 {
13285 {
13296 /* Try using a replicated byte. */
13300 {
13304 }
13305 }
13307 /* Try using a bit-to-bytemask. */
13309 {
13312 {
13316 }
13318 {
13322 }
13323 }
13325 }
13327 /* Return true if replicating VAL64 gives a valid immediate for an SVE MOV
13328 instruction. If INFO is nonnull, use it to describe valid immediates. */
13330 static bool
13333 {
13337 {
13341 {
13346 }
13347 }
13350 {
13351 /* DUP with no shift. */
13355 }
13357 {
13358 /* DUP with LSL #8. */
13362 }
13364 {
13365 /* DUPM. */
13369 }
13371 }
13373 /* Return true if OP is a valid SIMD immediate for the operation
13374 described by WHICH. If INFO is nonnull, use it to describe valid
13375 immediates. */
13376 bool
13379 {
13393 {
13402 }
13406 else
13409 /* Handle PFALSE and PTRUE. */
13414 scalar_float_mode elt_float_mode;
13417 {
13421 {
13425 }
13426 }
13434 /* Expand the vector constant out into a byte vector, with the least
13435 significant byte of the register first. */
13439 {
13440 /* The vector is provided in gcc endian-neutral fashion.
13441 For aarch64_be Advanced SIMD, it must be laid out in the vector
13442 register in reverse order. */
13454 {
13457 }
13458 }
13460 /* The immediate must repeat every eight bytes. */
13466 /* Get the repeating 8-byte value as an integer. No endian correction
13467 is needed here because bytes is already in lsb-first order. */
13475 else
13477 }
13479 /* Check whether X is a VEC_SERIES-like constant that starts at 0 and
13480 has a step in the range of INDEX. Return the index expression if so,
13481 otherwise return null. */
13482 rtx
13484 {
13491 }
13493 /* Check of immediate shift constants are within range. */
13494 bool
13496 {
13500 else
13502 }
13504 /* Return the bitmask CONST_INT to select the bits required by a zero extract
13505 operation of width WIDTH at bit position POS. */
13507 rtx
13509 {
13513 unsigned HOST_WIDE_INT mask
13516 }
13518 bool
13520 {
13539 }
13541 /* Return a const_int vector of VAL. */
13542 rtx
13544 {
13547 }
13549 /* Check OP is a legal scalar immediate for the MOVI instruction. */
13551 bool
13553 {
13554 machine_mode vmode;
13559 }
13561 /* Construct and return a PARALLEL RTX vector with elements numbering the
13562 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
13563 the vector - from the perspective of the architecture. This does not
13564 line up with GCC's perspective on lane numbers, so we end up with
13565 different masks depending on our target endian-ness. The diagram
13566 below may help. We must draw the distinction when building masks
13567 which select one half of the vector. An instruction selecting
13568 architectural low-lanes for a big-endian target, must be described using
13569 a mask selecting GCC high-lanes.
13571 Big-Endian Little-Endian
13573 GCC 0 1 2 3 3 2 1 0
13574 | x | x | x | x | | x | x | x | x |
13575 Architecture 3 2 1 0 3 2 1 0
13577 Low Mask: { 2, 3 } { 0, 1 }
13578 High Mask: { 0, 1 } { 2, 3 }
13580 MODE Is the mode of the vector and NUNITS is the number of units in it. */
13582 rtx
13584 {
13589 rtx t1;
13594 else
13602 }
13604 /* Check OP for validity as a PARALLEL RTX vector with elements
13605 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
13606 from the perspective of the architecture. See the diagram above
13607 aarch64_simd_vect_par_cnst_half for more details. */
13609 bool
13612 {
13626 {
13633 }
13635 }
13637 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
13638 HIGH (exclusive). */
13639 void
13641 const_tree exp)
13642 {
13643 HOST_WIDE_INT lane;
13648 {
13651 else
13653 }
13654 }
13656 /* Peform endian correction on lane number N, which indexes a vector
13657 of mode MODE, and return the result as an SImode rtx. */
13659 rtx
13661 {
13663 }
13665 /* Return TRUE if OP is a valid vector addressing mode. */
13667 bool
13669 {
13672 }
13674 /* Return true if OP is a valid MEM operand for an SVE LD1R instruction. */
13676 bool
13678 {
13680 scalar_mode mode;
13687 }
13689 /* Return true if OP is a valid MEM operand for an SVE LDR instruction.
13690 The conditions for STR are the same. */
13691 bool
13693 {
13700 }
13702 /* Return true if OP is a valid MEM operand for an SVE_STRUCT mode.
13703 We need to be able to access the individual pieces, so the range
13704 is different from LD[234] and ST[234]. */
13705 bool
13707 {
13714 ADDR_QUERY_ANY)
13722 }
13724 /* Emit a register copy from operand to operand, taking care not to
13725 early-clobber source registers in the process.
13727 COUNT is the number of components into which the copy needs to be
13728 decomposed. */
13729 void
13732 {
13742 else
13746 }
13748 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
13749 one of VSTRUCT modes: OI, CI, or XI. */
13750 int
13752 {
13753 /* This is only used (and only meaningful) for Advanced SIMD, not SVE. */
13755 }
13757 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
13758 alignment of a vector to 128 bits. SVE predicates have an alignment of
13759 16 bits. */
13760 static HOST_WIDE_INT
13762 {
13764 /* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can
13765 be set for non-predicate vectors of booleans. Modes are the most
13766 direct way we have of identifying real SVE predicate types. */
13770 }
13772 /* Implement target hook TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT. */
13773 static HOST_WIDE_INT
13775 {
13777 {
13778 /* If the length of the vector is fixed, try to align to that length,
13779 otherwise don't try to align at all. */
13780 HOST_WIDE_INT result;
13784 }
13786 }
13788 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
13789 static bool
13791 {
13795 /* For fixed-length vectors, check that the vectorizer will aim for
13796 full-vector alignment. This isn't true for generic GCC vectors
13797 that are wider than the ABI maximum of 128 bits. */
13803 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
13805 }
13807 /* Return true if the vector misalignment factor is supported by the
13808 target. */
13809 static bool
13813 {
13815 {
13816 /* Return if movmisalign pattern is not supported for this mode. */
13820 /* Misalignment factor is unknown at compile time. */
13823 }
13825 is_packed);
13826 }
13828 /* If VALS is a vector constant that can be loaded into a register
13829 using DUP, generate instructions to do so and return an RTX to
13830 assign to the register. Otherwise return NULL_RTX. */
13831 static rtx
13833 {
13836 rtx x;
13841 /* We can load this constant by using DUP and a constant in a
13842 single ARM register. This will be cheaper than a vector
13843 load. */
13846 }
13849 /* Generate code to load VALS, which is a PARALLEL containing only
13850 constants (for vec_init) or CONST_VECTOR, efficiently into a
13851 register. Returns an RTX to copy into the register, or NULL_RTX
13852 for a PARALLEL that can not be converted into a CONST_VECTOR. */
13853 static rtx
13855 {
13857 rtx const_dup;
13865 {
13866 /* A CONST_VECTOR must contain only CONST_INTs and
13867 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
13868 Only store valid constants in a CONST_VECTOR. */
13871 {
13874 n_const++;
13875 }
13878 }
13879 else
13884 /* Load using MOVI/MVNI. */
13887 /* Loaded using DUP. */
13890 /* Load from constant pool. We can not take advantage of single-cycle
13891 LD1 because we need a PC-relative addressing mode. */
13893 else
13894 /* A PARALLEL containing something not valid inside CONST_VECTOR.
13895 We can not construct an initializer. */
13897 }
13899 /* Expand a vector initialisation sequence, such that TARGET is
13900 initialised to contain VALS. */
13902 void
13904 {
13907 /* The number of vector elements. */
13909 /* The number of vector elements which are not constant. */
13912 /* The first element of vals. */
13916 /* Count the number of variable elements to initialise. */
13918 {
13922 else
13926 }
13928 /* No variable elements, hand off to aarch64_simd_make_constant which knows
13929 how best to handle this. */
13931 {
13934 {
13937 }
13938 }
13940 /* Splat a single non-constant element if we can. */
13942 {
13946 }
13951 /* If there are only variable elements, try to optimize
13952 the insertion using dup for the most common element
13953 followed by insertions. */
13955 /* The algorithm will fill matches[*][0] with the earliest matching element,
13956 and matches[X][1] with the count of duplicate elements (if X is the
13957 earliest element which has duplicates). */
13960 {
13963 {
13965 {
13967 {
13971 }
13972 }
13973 }
13978 {
13981 }
13983 /* Create a duplicate of the most common element, unless all elements
13984 are equally useless to us, in which case just immediately set the
13985 vector register using the first element. */
13988 {
13989 /* For vectors of two 64-bit elements, we can do even better. */
13994 {
13997 /* Combine can pick up this case, but handling it directly
13998 here leaves clearer RTL.
14000 This is load_pair_lanes<mode>, and also gives us a clean-up
14001 for store_pair_lanes<mode>. */
14004 && !STRICT_ALIGNMENT
14009 {
14010 rtx t;
14013 else
14017 }
14018 }
14019 /* The subreg-move sequence below will move into lane zero of the
14020 vector register. For big-endian we want that position to hold
14021 the last element of VALS. */
14025 }
14026 else
14027 {
14030 }
14032 /* Insert the rest. */
14034 {
14040 }
14042 }
14044 /* Initialise a vector which is part-variable. We want to first try
14045 to build those lanes which are constant in the most efficient way we
14046 can. */
14048 {
14051 /* Load constant part of vector. We really don't care what goes into the
14052 parts we will overwrite, but we're more likely to be able to load the
14053 constant efficiently if it has fewer, larger, repeating parts
14054 (see aarch64_simd_valid_immediate). */
14056 {
14062 {
14063 /* Look in the copied vector, as more elements are const. */
14066 {
14069 }
14070 }
14072 }
14074 }
14076 /* Insert the variable lanes directly. */
14078 {
14084 }
14085 }
14087 static unsigned HOST_WIDE_INT
14089 {
14093 }
14095 /* Select a format to encode pointers in exception handling data. */
14096 int
14098 {
14101 {
14107 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
14108 for everything. */
14112 /* No assumptions here. 8-byte relocs required. */
14115 }
14117 }
14119 /* The last .arch and .tune assembly strings that we printed. */
14123 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
14124 by the function fndecl. */
14126 void
14128 tree fndecl)
14129 {
14135 else
14146 /* Only update the assembler .arch string if it is distinct from the last
14147 such string we printed. */
14150 {
14153 }
14155 /* Print the cpu name we're tuning for in the comments, might be
14156 useful to readers of the generated asm. Do it only when it changes
14157 from function to function and verbose assembly is requested. */
14162 {
14166 }
14168 /* Don't forget the type directive for ELF. */
14171 }
14173 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
14175 static void
14177 {
14194 }
14196 /* Emit load exclusive. */
14198 static void
14201 {
14205 {
14212 }
14215 }
14217 /* Emit store exclusive. */
14219 static void
14222 {
14226 {
14233 }
14236 }
14238 /* Mark the previous jump instruction as unlikely. */
14240 static void
14242 {
14245 }
14247 /* Expand a compare and swap pattern. */
14249 void
14251 {
14256 gen_cas_fn gen;
14258 {
14259 gen_aarch64_compare_and_swapqi,
14260 gen_aarch64_compare_and_swaphi,
14261 gen_aarch64_compare_and_swapsi,
14262 gen_aarch64_compare_and_swapdi
14263 };
14265 {
14266 gen_aarch64_compare_and_swapqi_lse,
14267 gen_aarch64_compare_and_swaphi_lse,
14268 gen_aarch64_compare_and_swapsi_lse,
14269 gen_aarch64_compare_and_swapdi_lse
14270 };
14283 /* Normally the succ memory model must be stronger than fail, but in the
14284 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
14285 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
14292 {
14295 /* For short modes, we're going to perform the comparison in SImode,
14296 so do the zero-extension now. */
14300 /* Fall through. */
14304 /* Force the value into a register if needed. */
14311 }
14314 {
14321 }
14324 else
14335 }
14337 /* Test whether the target supports using a atomic load-operate instruction.
14338 CODE is the operation and AFTER is TRUE if the data in memory after the
14339 operation should be returned and FALSE if the data before the operation
14340 should be returned. Returns FALSE if the operation isn't supported by the
14341 architecture. */
14343 bool
14345 {
14350 {
14360 }
14361 }
14363 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
14364 sequence implementing an atomic operation. */
14366 static void
14368 {
14375 {
14377 }
14378 }
14380 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
14381 for the data in memory. EXPECTED is the value expected to be in memory.
14382 DESIRED is the value to store to memory. MEM is the memory location. MODEL
14383 is the memory ordering to use. */
14385 void
14388 rtx model)
14389 {
14391 machine_mode mode;
14396 {
14403 }
14405 /* Move the expected value into the CAS destination register. */
14408 /* Emit the CAS. */
14411 /* Compare the expected value with the value loaded by the CAS, to establish
14412 whether the swap was made. */
14414 }
14416 /* Split a compare and swap pattern. */
14418 void
14420 {
14422 machine_mode mode;
14427 rtx model_rtx;
14439 /* When OLDVAL is zero and we want the strong version we can emit a tighter
14440 loop:
14441 .label1:
14442 LD[A]XR rval, [mem]
14443 CBNZ rval, .label2
14444 ST[L]XR scratch, newval, [mem]
14445 CBNZ scratch, .label1
14446 .label2:
14447 CMP rval, 0. */
14452 {
14455 }
14458 /* The initial load can be relaxed for a __sync operation since a final
14459 barrier will be emitted to stop code hoisting. */
14463 else
14467 {
14472 }
14473 else
14474 {
14480 }
14485 {
14490 }
14491 else
14492 {
14496 }
14499 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
14500 to set the condition flags. If this is not used it will be removed by
14501 later passes. */
14503 {
14507 }
14508 /* Emit any final barrier needed for a __sync operation. */
14511 }
14513 /* Emit a BIC instruction. */
14515 static void
14517 {
14522 {
14527 }
14530 }
14532 /* Emit an atomic swap. */
14534 static void
14537 {
14541 {
14548 }
14551 }
14553 /* Operations supported by aarch64_emit_atomic_load_op. */
14555 enum aarch64_atomic_load_op_code
14556 {
14560 AARCH64_LDOP_BIC /* A & ~B */
14561 };
14563 /* Emit an atomic load-operate. */
14565 static void
14569 {
14572 {
14573 gen_aarch64_atomic_loadaddqi,
14574 gen_aarch64_atomic_loadaddhi,
14575 gen_aarch64_atomic_loadaddsi,
14576 gen_aarch64_atomic_loadadddi
14577 };
14579 {
14580 gen_aarch64_atomic_loadeorqi,
14581 gen_aarch64_atomic_loadeorhi,
14582 gen_aarch64_atomic_loadeorsi,
14583 gen_aarch64_atomic_loadeordi
14584 };
14586 {
14587 gen_aarch64_atomic_loadsetqi,
14588 gen_aarch64_atomic_loadsethi,
14589 gen_aarch64_atomic_loadsetsi,
14590 gen_aarch64_atomic_loadsetdi
14591 };
14593 {
14594 gen_aarch64_atomic_loadclrqi,
14595 gen_aarch64_atomic_loadclrhi,
14596 gen_aarch64_atomic_loadclrsi,
14597 gen_aarch64_atomic_loadclrdi
14598 };
14599 aarch64_atomic_load_op_fn gen;
14603 {
14610 }
14613 {
14620 }
14623 }
14625 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
14626 location to store the data read from memory. OUT_RESULT is the location to
14627 store the result of the operation. MEM is the memory location to read and
14628 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
14629 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
14630 be NULL. */
14632 void
14635 {
14639 aarch64_atomic_load_op_code ldop_code;
14640 rtx src;
14641 rtx x;
14649 /* Make sure the value is in a register, putting it into a destination
14650 register if it needs to be manipulated. */
14653 {
14656 }
14657 else
14661 /* Preprocess the data for the operation as necessary. If the operation is
14662 a SET then emit a swap instruction and finish. */
14664 {
14670 /* Negate the value and treat it as a PLUS. */
14671 {
14672 rtx neg_src;
14674 /* Resize the value if necessary. */
14683 }
14684 /* Fall-through. */
14698 {
14699 rtx not_src;
14701 /* Resize the value if necessary. */
14710 }
14715 /* The operation can't be done with atomic instructions. */
14717 }
14721 /* If necessary, calculate the data in memory after the update by redoing the
14722 operation from values in registers. */
14727 {
14731 }
14736 {
14752 }
14757 }
14759 /* Split an atomic operation. */
14761 void
14764 {
14770 rtx x;
14772 /* Split the atomic operation into a sequence. */
14780 else
14784 /* The initial load can be relaxed for a __sync operation since a final
14785 barrier will be emitted to stop code hoisting. */
14789 else
14793 {
14807 {
14810 }
14811 /* Fall through. */
14817 }
14827 /* Emit any final barrier needed for a __sync operation. */
14830 }
14832 static void
14834 {
14835 /* Half-precision float operations. The compiler handles all operations
14836 with NULL libfuncs by converting to SFmode. */
14838 /* Conversions. */
14842 /* Arithmetic. */
14849 /* Comparisons. */
14857 }
14859 /* Target hook for c_mode_for_suffix. */
14860 static machine_mode
14862 {
14867 }
14869 /* We can only represent floating point constants which will fit in
14870 "quarter-precision" values. These values are characterised by
14871 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
14872 by:
14874 (-1)^s * (n/16) * 2^r
14876 Where:
14877 's' is the sign bit.
14878 'n' is an integer in the range 16 <= n <= 31.
14879 'r' is an integer in the range -3 <= r <= 4. */
14881 /* Return true iff X can be represented by a quarter-precision
14882 floating point immediate operand X. Note, we cannot represent 0.0. */
14883 bool
14885 {
14886 /* This represents our current view of how many bits
14887 make up the mantissa. */
14897 /* We don't support HFmode constants yet. */
14903 /* We cannot represent infinities, NaNs or +/-zero. We won't
14904 know if we have +zero until we analyse the mantissa, but we
14905 can reject the other invalid values. */
14910 /* Extract exponent. */
14914 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
14915 highest (sign) bit, with a fixed binary point at bit point_pos.
14916 m1 holds the low part of the mantissa, m2 the high part.
14917 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
14918 bits for the mantissa, this can fail (low bits will be lost). */
14922 /* If the low part of the mantissa has bits set we cannot represent
14923 the value. */
14926 /* We have rejected the lower HOST_WIDE_INT, so update our
14927 understanding of how many bits lie in the mantissa and
14928 look only at the high HOST_WIDE_INT. */
14932 /* We can only represent values with a mantissa of the form 1.xxxx. */
14937 /* Having filtered unrepresentable values, we may now remove all
14938 but the highest 5 bits. */
14941 /* We cannot represent the value 0.0, so reject it. This is handled
14942 elsewhere. */
14946 /* Then, as bit 4 is always set, we can mask it off, leaving
14947 the mantissa in the range [0, 15]. */
14951 /* GCC internally does not use IEEE754-like encoding (where normalized
14952 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
14953 Our mantissa values are shifted 4 places to the left relative to
14954 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
14955 by 5 places to correct for GCC's representation. */
14959 }
14961 /* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
14962 immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
14963 output MOVI/MVNI, ORR or BIC immediate. */
14967 {
14977 /* This will return true to show const_vector is legal for use as either
14978 a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
14979 It will also update INFO to show how the immediate should be generated.
14980 WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
14988 {
14990 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
14991 move immediate path. */
14994 else
14995 {
15004 else
15008 }
15009 }
15014 {
15024 else
15028 }
15029 else
15030 {
15031 /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
15037 else
15041 }
15043 }
15047 {
15049 /* If a floating point number was passed and we desire to use it in an
15050 integer mode do the conversion to integer. */
15052 {
15057 }
15059 machine_mode vmode;
15060 /* use a 64 bit mode for everything except for DI/DF mode, where we use
15061 a 128 bit vector mode. */
15067 }
15069 /* Return the output string to use for moving immediate CONST_VECTOR
15070 into an SVE register. */
15074 {
15085 {
15090 }
15093 {
15096 else
15097 {
15107 }
15108 }
15113 }
15115 /* Return the asm format for a PTRUE instruction whose destination has
15116 mode MODE. SUFFIX is the element size suffix. */
15120 {
15125 else
15128 }
15130 /* Split operands into moves from op[1] + op[2] into op[0]. */
15132 void
15134 {
15145 {
15146 /* No-op move. Can't split to nothing; emit something. */
15149 }
15151 /* Preserve register attributes for variable tracking. */
15156 /* Special case of reversed high/low parts. */
15159 {
15163 }
15165 {
15166 /* Try to avoid unnecessary moves if part of the result
15167 is in the right place already. */
15172 }
15173 else
15174 {
15179 }
15180 }
15182 /* vec_perm support. */
15184 struct expand_vec_perm_d
15185 {
15187 vec_perm_indices perm;
15188 machine_mode vmode;
15192 };
15194 /* Generate a variable permutation. */
15196 static void
15198 {
15209 {
15211 {
15212 /* Expand the argument to a V16QI mode by duplicating it. */
15216 }
15217 else
15218 {
15220 }
15221 }
15222 else
15223 {
15224 rtx pair;
15227 {
15231 }
15232 else
15233 {
15237 }
15238 }
15239 }
15241 /* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL.
15242 NELT is the number of elements in the vector. */
15244 void
15247 {
15250 rtx mask;
15252 /* The TBL instruction does not use a modulo index, so we must take care
15253 of that ourselves. */
15258 /* For big-endian, we also need to reverse the index within the vector
15259 (but not which vector). */
15261 {
15262 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
15267 }
15269 }
15271 /* Generate (set TARGET (unspec [OP0 OP1] CODE)). */
15273 static void
15275 {
15279 }
15281 /* Expand an SVE vec_perm with the given operands. */
15283 void
15285 {
15288 /* Enforced by the pattern condition. */
15291 /* Note: vec_perm indices are supposed to wrap when they go beyond the
15292 size of the two value vectors, i.e. the upper bits of the indices
15293 are effectively ignored. SVE TBL instead produces 0 for any
15294 out-of-range indices, so we need to modulo all the vec_perm indices
15295 to ensure they are all in range. */
15298 /* Check if the sel only references the first values vector. */
15301 {
15304 }
15306 /* Check if the two values vectors are the same. */
15308 {
15314 }
15316 /* Run TBL on for each value vector and combine the results. */
15323 {
15328 }
15335 else
15337 }
15339 /* Recognize patterns suitable for the TRN instructions. */
15340 static bool
15342 {
15343 HOST_WIDE_INT odd;
15351 /* Note that these are little-endian tests.
15352 We correct for big-endian later. */
15359 /* Success! */
15365 /* We don't need a big-endian lane correction for SVE; see the comment
15366 at the head of aarch64-sve.md for details. */
15368 {
15371 }
15377 }
15379 /* Recognize patterns suitable for the UZP instructions. */
15380 static bool
15382 {
15383 HOST_WIDE_INT odd;
15390 /* Note that these are little-endian tests.
15391 We correct for big-endian later. */
15397 /* Success! */
15403 /* We don't need a big-endian lane correction for SVE; see the comment
15404 at the head of aarch64-sve.md for details. */
15406 {
15409 }
15415 }
15417 /* Recognize patterns suitable for the ZIP instructions. */
15418 static bool
15420 {
15429 /* Note that these are little-endian tests.
15430 We correct for big-endian later. */
15438 /* Success! */
15444 /* We don't need a big-endian lane correction for SVE; see the comment
15445 at the head of aarch64-sve.md for details. */
15447 {
15450 }
15456 }
15458 /* Recognize patterns for the EXT insn. */
15460 static bool
15462 {
15463 HOST_WIDE_INT location;
15464 rtx offset;
15466 /* The first element always refers to the first vector.
15467 Check if the extracted indices are increasing by one. */
15473 /* Success! */
15477 /* The case where (location == 0) is a no-op for both big- and little-endian,
15478 and is removed by the mid-end at optimization levels -O1 and higher.
15480 We don't need a big-endian lane correction for SVE; see the comment
15481 at the head of aarch64-sve.md for details. */
15483 {
15484 /* After setup, we want the high elements of the first vector (stored
15485 at the LSB end of the register), and the low elements of the second
15486 vector (stored at the MSB end of the register). So swap. */
15488 /* location != 0 (above), so safe to assume (nelt - location) < nelt.
15489 to_constant () is safe since this is restricted to Advanced SIMD
15490 vectors. */
15492 }
15498 UNSPEC_EXT));
15500 }
15502 /* Recognize patterns for the REV{64,32,16} insns, which reverse elements
15503 within each 64-bit, 32-bit or 16-bit granule. */
15505 static bool
15507 {
15508 HOST_WIDE_INT diff;
15510 machine_mode pred_mode;
15519 {
15522 }
15524 {
15527 }
15529 {
15532 }
15533 else
15541 /* Success! */
15547 {
15550 UNSPEC_MERGE_PTRUE);
15551 }
15554 }
15556 /* Recognize patterns for the REV insn, which reverses elements within
15557 a full vector. */
15559 static bool
15561 {
15570 /* Success! */
15577 }
15579 static bool
15581 {
15583 rtx in0;
15584 HOST_WIDE_INT elt;
15586 rtx lane;
15596 /* Success! */
15600 /* The generic preparation in aarch64_expand_vec_perm_const_1
15601 swaps the operand order and the permute indices if it finds
15602 d->perm[0] to be in the second operand. Thus, we can always
15603 use d->op0 and need not do any extra arithmetic to get the
15604 correct lane number. */
15612 }
15614 static bool
15616 {
15620 /* Make sure that the indices are constant. */
15629 /* Generic code will try constant permutation twice. Once with the
15630 original mode and again with the elements lowered to QImode.
15631 So wait and don't do the selector expansion ourselves. */
15635 /* to_constant is safe since this routine is specific to Advanced SIMD
15636 vectors. */
15639 /* If big-endian and two vectors we end up with a weird mixed-endian
15640 mode on NEON. Reverse the index within each word but not the word
15641 itself. to_constant is safe because we checked is_constant above. */
15651 }
15653 /* Try to implement D using an SVE TBL instruction. */
15655 static bool
15657 {
15660 /* Permuting two variable-length vectors could overflow the
15661 index range. */
15672 }
15674 static bool
15676 {
15677 /* The pattern matching functions above are written to look for a small
15678 number to begin the sequence (0, 1, N/2). If we begin with an index
15679 from the second operand, we can swap the operands. */
15682 {
15685 }
15691 {
15710 }
15712 }
15714 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
15716 static bool
15719 {
15722 /* Check whether the mask can be applied to a single vector. */
15726 {
15729 }
15731 {
15734 }
15735 else
15755 }
15757 /* Generate a byte permute mask for a register of mode MODE,
15758 which has NUNITS units. */
15760 rtx
15762 {
15763 /* We have to reverse each vector because we dont have
15764 a permuted load that can reverse-load according to ABI rules. */
15765 rtx mask;
15778 }
15780 /* Return true if X is a valid second operand for the SVE instruction
15781 that implements integer comparison OP_CODE. */
15783 static bool
15785 {
15790 {
15805 }
15806 }
15808 /* Use predicated SVE instructions to implement the equivalent of:
15810 (set TARGET OP)
15812 given that PTRUE is an all-true predicate of the appropriate mode. */
15814 static void
15816 {
15819 UNSPEC_MERGE_PTRUE);
15822 }
15824 /* Likewise, but also clobber the condition codes. */
15826 static void
15828 {
15831 UNSPEC_MERGE_PTRUE);
15834 }
15836 /* Return the UNSPEC_COND_* code for comparison CODE. */
15838 static unsigned int
15840 {
15842 {
15857 }
15858 }
15860 /* Emit:
15862 (set TARGET (unspec [PRED OP0 OP1] UNSPEC_COND_<X>))
15864 where <X> is the operation associated with comparison CODE. This form
15865 of instruction is used when (and (CODE OP0 OP1) PRED) would have different
15866 semantics, such as when PRED might not be all-true and when comparing
15867 inactive lanes could have side effects. */
15869 static void
15872 {
15877 }
15879 /* Expand an SVE integer comparison using the SVE equivalent of:
15881 (set TARGET (CODE OP0 OP1)). */
15883 void
15885 {
15895 }
15897 /* Emit the SVE equivalent of:
15899 (set TMP1 (CODE1 OP0 OP1))
15900 (set TMP2 (CODE2 OP0 OP1))
15901 (set TARGET (ior:PRED_MODE TMP1 TMP2))
15903 PTRUE is an all-true predicate with the same mode as TARGET. */
15905 static void
15908 {
15917 }
15919 /* Emit the SVE equivalent of:
15921 (set TMP (CODE OP0 OP1))
15922 (set TARGET (not TMP))
15924 PTRUE is an all-true predicate with the same mode as TARGET. */
15926 static void
15929 {
15935 }
15937 /* Expand an SVE floating-point comparison using the SVE equivalent of:
15939 (set TARGET (CODE OP0 OP1))
15941 If CAN_INVERT_P is true, the caller can also handle inverted results;
15942 return true if the result is in fact inverted. */
15944 bool
15947 {
15953 {
15955 /* UNORDERED has no immediate form. */
15957 /* fall through */
15964 {
15965 /* There is native support for the comparison. */
15969 }
15972 /* This is a trapping operation (LT or GT). */
15978 {
15979 /* This would trap for signaling NaNs. */
15983 }
15984 /* fall through */
15990 {
15991 /* Work out which elements are ordered. */
15996 /* Test the opposite condition for the ordered elements,
15997 then invert the result. */
16000 else
16003 {
16007 }
16012 }
16016 /* ORDERED has no immediate form. */
16022 }
16024 /* There is native support for the inverse comparison. */
16027 {
16031 }
16034 }
16036 /* Expand an SVE vcond pattern with operands OPS. DATA_MODE is the mode
16037 of the data being selected and CMP_MODE is the mode of the values being
16038 compared. */
16040 void
16043 {
16044 machine_mode pred_mode
16049 {
16053 }
16054 else
16059 }
16061 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
16062 true. However due to issues with register allocation it is preferable
16063 to avoid tieing integer scalar and FP scalar modes. Executing integer
16064 operations in general registers is better than treating them as scalar
16065 vector operations. This reduces latency and avoids redundant int<->FP
16066 moves. So tie modes if they are either the same class, or vector modes
16067 with other vector modes, vector structs or any scalar mode. */
16069 static bool
16071 {
16075 /* We specifically want to allow elements of "structure" modes to
16076 be tieable to the structure. This more general condition allows
16077 other rarer situations too. The reason we don't extend this to
16078 predicate modes is that there are no predicate structure modes
16079 nor any specific instructions for extracting part of a predicate
16080 register. */
16085 /* Also allow any scalar modes with vectors. */
16091 }
16093 /* Return a new RTX holding the result of moving POINTER forward by
16094 AMOUNT bytes. */
16096 static rtx
16098 {
16103 }
16105 /* Return a new RTX holding the result of moving POINTER forward by the
16106 size of the mode it points to. */
16108 static rtx
16110 {
16112 }
16114 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
16115 MODE bytes. */
16117 static void
16119 machine_mode mode)
16120 {
16123 /* "Cast" the pointers to the correct mode. */
16126 /* Emit the memcpy. */
16129 /* Move the pointers forward. */
16132 }
16134 /* Expand movmem, as if from a __builtin_memcpy. Return true if
16135 we succeed, otherwise return false. */
16137 bool
16139 {
16143 rtx base;
16146 /* When optimizing for size, give a better estimate of the length of a
16147 memcpy call, but use the default otherwise. */
16150 /* We can't do anything smart if the amount to copy is not constant. */
16156 /* Try to keep the number of instructions low. For cases below 16 bytes we
16157 need to make at most two moves. For cases above 16 bytes it will be one
16158 move for each 16 byte chunk, then at most two additional moves. */
16168 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
16169 1-byte chunk. */
16171 {
16173 {
16176 }
16182 }
16184 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
16185 4-byte chunk, partially overlapping with the previously copied chunk. */
16187 {
16191 {
16197 }
16199 }
16201 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
16202 them, then (if applicable) an 8-byte chunk. */
16204 {
16206 {
16209 }
16210 else
16211 {
16214 }
16215 }
16217 /* Finish the final bytes of the copy. We can always do this in one
16218 instruction. We either copy the exact amount we need, or partially
16219 overlap with the previous chunk we copied and copy 8-bytes. */
16228 else
16229 {
16231 {
16235 }
16236 else
16237 {
16243 }
16244 }
16247 }
16249 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
16250 SImode stores. Handle the case when the constant has identical
16251 bottom and top halves. This is beneficial when the two stores can be
16252 merged into an STP and we avoid synthesising potentially expensive
16253 immediates twice. Return true if such a split is possible. */
16255 bool
16257 {
16266 unsigned int orig_cost
16268 unsigned int lo_cost
16271 /* We want to transform:
16272 MOV x1, 49370
16273 MOVK x1, 0x140, lsl 16
16274 MOVK x1, 0xc0da, lsl 32
16275 MOVK x1, 0x140, lsl 48
16276 STR x1, [x0]
16277 into:
16278 MOV w1, 49370
16279 MOVK w1, 0x140, lsl 16
16280 STP w1, w1, [x0]
16281 So we want to perform this only when we save two instructions
16282 or more. When optimizing for size, however, accept any code size
16283 savings we can. */
16298 /* Don't emit an explicit store pair as this may not be always profitable.
16299 Let the sched-fusion logic decide whether to merge them. */
16304 }
16306 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
16308 static unsigned HOST_WIDE_INT
16310 {
16312 }
16314 static rtx
16317 {
16321 insn_code icode;
16332 {
16360 }
16365 {
16368 }
16377 {
16380 }
16386 }
16388 static rtx
16391 {
16395 insn_code icode;
16407 {
16435 }
16440 {
16443 }
16451 {
16456 }
16467 {
16470 }
16476 }
16478 #undef TARGET_GEN_CCMP_FIRST
16479 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
16481 #undef TARGET_GEN_CCMP_NEXT
16482 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
16484 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
16485 instruction fusion of some sort. */
16487 static bool
16489 {
16491 }
16494 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
16495 should be kept together during scheduling. */
16497 static bool
16499 {
16500 rtx set_dest;
16503 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
16510 {
16511 /* We are trying to match:
16512 prev (mov) == (set (reg r0) (const_int imm16))
16513 curr (movk) == (set (zero_extract (reg r0)
16514 (const_int 16)
16515 (const_int 16))
16516 (const_int imm16_1)) */
16528 {
16530 }
16531 }
16534 {
16536 /* We're trying to match:
16537 prev (adrp) == (set (reg r1)
16538 (high (symbol_ref ("SYM"))))
16539 curr (add) == (set (reg r0)
16540 (lo_sum (reg r1)
16541 (symbol_ref ("SYM"))))
16542 Note that r0 need not necessarily be the same as r1, especially
16543 during pre-regalloc scheduling. */
16547 {
16555 }
16556 }
16559 {
16561 /* We're trying to match:
16562 prev (movk) == (set (zero_extract (reg r0)
16563 (const_int 16)
16564 (const_int 32))
16565 (const_int imm16_1))
16566 curr (movk) == (set (zero_extract (reg r0)
16567 (const_int 16)
16568 (const_int 48))
16569 (const_int imm16_2)) */
16585 }
16587 {
16588 /* We're trying to match:
16589 prev (adrp) == (set (reg r0)
16590 (high (symbol_ref ("SYM"))))
16591 curr (ldr) == (set (reg r1)
16592 (mem (lo_sum (reg r0)
16593 (symbol_ref ("SYM")))))
16594 or
16595 curr (ldr) == (set (reg r1)
16596 (zero_extend (mem
16597 (lo_sum (reg r0)
16598 (symbol_ref ("SYM")))))) */
16601 {
16614 }
16615 }
16623 {
16627 rtx cc_reg_1;
16632 && prev
16634 {
16635 /* FIXME: this misses some which is considered simple arthematic
16636 instructions for ThunderX. Simple shifts are missed here. */
16642 }
16643 }
16646 && curr_set
16649 {
16650 /* We're trying to match:
16651 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
16652 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
16653 (const_int 0))
16654 (label_ref ("SYM"))
16655 (pc)) */
16662 {
16663 /* Fuse ALU operations followed by conditional branch instruction. */
16665 {
16686 }
16687 }
16688 }
16691 }
16693 /* Return true iff the instruction fusion described by OP is enabled. */
16695 bool
16697 {
16699 }
16701 /* If MEM is in the form of [base+offset], extract the two parts
16702 of address and set to BASE and OFFSET, otherwise return false
16703 after clearing BASE and OFFSET. */
16705 bool
16707 {
16708 rtx addr;
16715 {
16719 }
16723 {
16727 }
16733 }
16735 /* Types for scheduling fusion. */
16736 enum sched_fusion_type
16737 {
16739 SCHED_FUSION_LD_SIGN_EXTEND,
16740 SCHED_FUSION_LD_ZERO_EXTEND,
16741 SCHED_FUSION_LD,
16742 SCHED_FUSION_ST,
16743 SCHED_FUSION_NUM
16744 };
16746 /* If INSN is a load or store of address in the form of [base+offset],
16747 extract the two parts and set to BASE and OFFSET. Return scheduling
16748 fusion type this INSN is. */
16750 static enum sched_fusion_type
16752 {
16770 {
16775 }
16777 {
16782 }
16787 {
16790 }
16791 else
16798 }
16800 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
16802 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
16803 and PRI are only calculated for these instructions. For other instruction,
16804 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
16805 type instruction fusion can be added by returning different priorities.
16807 It's important that irrelevant instructions get the largest FUSION_PRI. */
16809 static void
16812 {
16822 {
16826 }
16828 /* Set FUSION_PRI according to fusion type and base register. */
16831 /* Calculate PRI. */
16834 /* INSN with smaller offset goes first. */
16838 else
16843 }
16845 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
16846 Adjust priority of sha1h instructions so they are scheduled before
16847 other SHA1 instructions. */
16849 static int
16851 {
16855 {
16860 }
16863 }
16865 /* Given OPERANDS of consecutive load/store, check if we can merge
16866 them into ldp/stp. LOAD is true if they are load instructions.
16867 MODE is the mode of memory operands. */
16869 bool
16871 machine_mode mode)
16872 {
16878 {
16886 }
16887 else
16888 {
16893 }
16895 /* The mems cannot be volatile. */
16899 /* If we have SImode and slow unaligned ldp,
16900 check the alignment to be at least 8 byte. */
16904 && !optimize_size
16908 /* Check if the addresses are in the form of [base+offset]. */
16916 /* Check if the bases are same. */
16920 /* The operands must be of the same size. */
16926 /* We should only be trying this for fixed-sized modes. There is no
16927 SVE LDP/STP instruction. */
16929 /* Check if the offsets are consecutive. */
16933 /* Check if the addresses are clobbered by load. */
16935 {
16939 /* In increasing order, the last load can clobber the address. */
16942 }
16944 /* One of the memory accesses must be a mempair operand.
16945 If it is not the first one, they need to be swapped by the
16946 peephole. */
16953 else
16958 else
16961 /* Check if the registers are of same class. */
16966 }
16968 /* Given OPERANDS of consecutive load/store that can be merged,
16969 swap them if they are not in ascending order. */
16970 void
16972 {
16977 {
16980 }
16981 else
16982 {
16985 }
16994 {
16995 /* Irrespective of whether this is a load or a store,
16996 we do the same swap. */
16999 }
17000 }
17002 /* Taking X and Y to be HOST_WIDE_INT pointers, return the result of a
17003 comparison between the two. */
17004 int
17006 {
17009 }
17011 /* Taking X and Y to be pairs of RTX, one pointing to a MEM rtx and the
17012 other pointing to a REG rtx containing an offset, compare the offsets
17013 of the two pairs.
17015 Return:
17017 1 iff offset (X) > offset (Y)
17018 0 iff offset (X) == offset (Y)
17019 -1 iff offset (X) < offset (Y) */
17020 int
17022 {
17029 else
17034 else
17037 /* Extract the offsets. */
17044 }
17046 /* Given OPERANDS of consecutive load/store, check if we can merge
17047 them into ldp/stp by adjusting the offset. LOAD is true if they
17048 are load instructions. MODE is the mode of memory operands.
17050 Given below consecutive stores:
17052 str w1, [xb, 0x100]
17053 str w1, [xb, 0x104]
17054 str w1, [xb, 0x108]
17055 str w1, [xb, 0x10c]
17057 Though the offsets are out of the range supported by stp, we can
17058 still pair them after adjusting the offset, like:
17060 add scratch, xb, 0x100
17061 stp w1, w1, [scratch]
17062 stp w1, w1, [scratch, 0x8]
17064 The peephole patterns detecting this opportunity should guarantee
17065 the scratch register is avaliable. */
17067 bool
17069 scalar_mode mode)
17070 {
17077 {
17089 /* Do not attempt to merge the loads if the loads clobber each other. */
17094 }
17095 else
17096 {
17105 }
17106 /* Skip if memory operand is by itslef valid for ldp/stp. */
17110 /* The mems cannot be volatile. */
17115 /* Check if the addresses are in the form of [base+offset]. */
17129 /* Check if the bases are same. */
17141 /* Check if the offsets can be put in the right order to do a ldp/stp. */
17148 /* Check that offsets are within range of each other. The ldp/stp
17149 instructions have 7 bit immediate offsets, so use 0x80. */
17153 /* The offsets must be aligned with respect to each other. */
17157 /* Check if the addresses are clobbered by load. */
17164 /* If we have SImode and slow unaligned ldp,
17165 check the alignment to be at least 8 byte. */
17169 && !optimize_size
17175 else
17180 else
17185 else
17190 else
17193 /* Check if the registers are of same class. */
17198 }
17200 /* Given OPERANDS of consecutive load/store, this function pairs them
17201 into LDP/STP after adjusting the offset. It depends on the fact
17202 that the operands can be sorted so the offsets are correct for STP.
17203 MODE is the mode of memory operands. CODE is the rtl operator
17204 which should be applied to all memory operands, it's SIGN_EXTEND,
17205 ZERO_EXTEND or UNKNOWN. */
17207 bool
17210 {
17217 /* We make changes on a copy as we may still bail out. */
17221 /* Sort the operands. */
17225 {
17230 }
17231 else
17232 {
17238 }
17245 /* Adjust offset so it can fit in LDP/STP instruction. */
17253 /* The base offset is optimally half way between the two STP/LDP offsets. */
17256 else
17257 /* However, due to issues with negative LDP/STP offset generation for
17258 larger modes, for DF, DI and vector modes. we must not use negative
17259 addresses smaller than 9 signed unadjusted bits can store. This
17260 provides the most range in this case. */
17263 /* Adjust the base so that it is aligned with the addresses but still
17264 optimal. */
17266 /* Fix the offset, bearing in mind we want to make it bigger not
17267 smaller. */
17270 /* The negative range of LDP/STP is one larger than the positive range. */
17273 /* Check if base offset is too big or too small. We can attempt to resolve
17274 this issue by setting it to the maximum value and seeing if the offsets
17275 still fit. */
17277 {
17279 /* We must still make sure that the base offset is aligned with respect
17280 to the address. But it may may not be made any bigger. */
17282 }
17284 /* Likewise for the case where the base is too small. */
17286 {
17289 }
17291 /* Offset of the first STP/LDP. */
17294 /* Offset of the second STP/LDP. */
17297 /* The offsets must be within the range of the LDP/STP instructions. */
17316 {
17321 }
17323 {
17328 }
17331 {
17340 }
17341 else
17342 {
17351 }
17353 /* Emit adjusting instruction. */
17355 /* Emit ldp/stp instructions. */
17363 }
17365 /* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
17366 it isn't worth branching around empty masked ops (including masked
17367 stores). */
17369 static bool
17371 {
17373 }
17375 /* Return 1 if pseudo register should be created and used to hold
17376 GOT address for PIC code. */
17378 bool
17380 {
17382 }
17384 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
17386 static int
17388 {
17390 {
17397 }
17400 }
17403 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
17404 return the log2 of that value. Otherwise return -1. */
17406 int
17408 {
17423 }
17425 /* If X is a vector of equal CONST_DOUBLE values and that value is
17426 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
17428 int
17430 {
17448 }
17450 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
17451 to float.
17453 __fp16 always promotes through this hook.
17454 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
17455 through the generic excess precision logic rather than here. */
17457 static tree
17459 {
17465 }
17467 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
17469 static bool
17471 optimization_type opt_type)
17472 {
17474 {
17480 }
17481 }
17483 /* Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook. */
17485 static unsigned int
17488 {
17489 /* Polynomial invariant 1 == (VG / 2) - 1. */
17494 }
17496 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
17497 if MODE is HFmode, and punt to the generic implementation otherwise. */
17499 static bool
17501 {
17505 }
17507 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
17508 if MODE is HFmode, and punt to the generic implementation otherwise. */
17510 static bool
17512 {
17516 }
17518 /* Set the value of FLT_EVAL_METHOD.
17519 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
17521 0: evaluate all operations and constants, whose semantic type has at
17522 most the range and precision of type float, to the range and
17523 precision of float; evaluate all other operations and constants to
17524 the range and precision of the semantic type;
17526 N, where _FloatN is a supported interchange floating type
17527 evaluate all operations and constants, whose semantic type has at
17528 most the range and precision of _FloatN type, to the range and
17529 precision of the _FloatN type; evaluate all other operations and
17530 constants to the range and precision of the semantic type;
17532 If we have the ARMv8.2-A extensions then we support _Float16 in native
17533 precision, so we should set this to 16. Otherwise, we support the type,
17534 but want to evaluate expressions in float precision, so set this to
17535 0. */
17537 static enum flt_eval_method
17539 {
17541 {
17544 /* We can calculate either in 16-bit range and precision or
17545 32-bit range and precision. Make that decision based on whether
17546 we have native support for the ARMv8.2-A 16-bit floating-point
17547 instructions or not. */
17549 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
17555 }
17557 }
17559 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
17560 scheduled for speculative execution. Reject the long-running division
17561 and square-root instructions. */
17563 static bool
17565 {
17567 {
17585 }
17586 }
17588 /* Implement TARGET_COMPUTE_PRESSURE_CLASSES. */
17590 static int
17592 {
17596 /* PR_REGS isn't a useful pressure class because many predicate pseudo
17597 registers need to go in PR_LO_REGS at some point during their
17598 lifetime. Splitting it into two halves has the effect of making
17599 all predicates count against PR_LO_REGS, so that we try whenever
17600 possible to restrict the number of live predicates to 8. This
17601 greatly reduces the amount of spilling in certain loops. */
17605 }
17607 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
17609 static bool
17612 {
17614 {
17618 /* Don't allow changes between SVE data modes and non-SVE modes.
17619 See the comment at the head of aarch64-sve.md for details. */
17623 /* Don't allow changes in element size: lane 0 of the new vector
17624 would not then be lane 0 of the old vector. See the comment
17625 above aarch64_maybe_expand_sve_subreg_move for a more detailed
17626 description.
17628 In the worst case, this forces a register to be spilled in
17629 one mode and reloaded in the other, which handles the
17630 endianness correctly. */
17633 }
17635 }
17637 /* Implement TARGET_EARLY_REMAT_MODES. */
17639 static void
17641 {
17642 /* SVE values are not normally live across a call, so it should be
17643 worth doing early rematerialization even in VL-specific mode. */
17645 {
17650 }
17651 }
17653 /* Target-specific selftests. */
17655 #if CHECKING_P
17659 /* Selftest for the RTL loader.
17660 Verify that the RTL loader copes with a dump from
17661 print_rtx_function. This is essentially just a test that class
17662 function_reader can handle a real dump, but it also verifies
17663 that lookup_reg_by_dump_name correctly handles hard regs.
17664 The presence of hard reg names in the dump means that the test is
17665 target-specific, hence it is in this file. */
17667 static void
17669 {
17681 /* Verify crtl->return_rtx. */
17685 }
17687 /* Run all target-specific selftests. */
17689 static void
17691 {
17693 }
17699 #undef TARGET_ADDRESS_COST
17700 #define TARGET_ADDRESS_COST aarch64_address_cost
17702 /* This hook will determines whether unnamed bitfields affect the alignment
17703 of the containing structure. The hook returns true if the structure
17704 should inherit the alignment requirements of an unnamed bitfield's
17705 type. */
17706 #undef TARGET_ALIGN_ANON_BITFIELD
17707 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
17709 #undef TARGET_ASM_ALIGNED_DI_OP
17712 #undef TARGET_ASM_ALIGNED_HI_OP
17715 #undef TARGET_ASM_ALIGNED_SI_OP
17718 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
17719 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
17720 hook_bool_const_tree_hwi_hwi_const_tree_true
17722 #undef TARGET_ASM_FILE_START
17723 #define TARGET_ASM_FILE_START aarch64_start_file
17725 #undef TARGET_ASM_OUTPUT_MI_THUNK
17726 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
17728 #undef TARGET_ASM_SELECT_RTX_SECTION
17729 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
17731 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
17732 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
17734 #undef TARGET_BUILD_BUILTIN_VA_LIST
17735 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
17737 #undef TARGET_CALLEE_COPIES
17738 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
17740 #undef TARGET_CAN_ELIMINATE
17741 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
17743 #undef TARGET_CAN_INLINE_P
17744 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
17746 #undef TARGET_CANNOT_FORCE_CONST_MEM
17747 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
17749 #undef TARGET_CASE_VALUES_THRESHOLD
17750 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
17752 #undef TARGET_CONDITIONAL_REGISTER_USAGE
17753 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
17755 /* Only the least significant bit is used for initialization guard
17756 variables. */
17757 #undef TARGET_CXX_GUARD_MASK_BIT
17758 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
17760 #undef TARGET_C_MODE_FOR_SUFFIX
17761 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
17763 #ifdef TARGET_BIG_ENDIAN_DEFAULT
17764 #undef TARGET_DEFAULT_TARGET_FLAGS
17765 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
17766 #endif
17768 #undef TARGET_CLASS_MAX_NREGS
17769 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
17771 #undef TARGET_BUILTIN_DECL
17772 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
17774 #undef TARGET_BUILTIN_RECIPROCAL
17775 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
17777 #undef TARGET_C_EXCESS_PRECISION
17778 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
17780 #undef TARGET_EXPAND_BUILTIN
17781 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
17783 #undef TARGET_EXPAND_BUILTIN_VA_START
17784 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
17786 #undef TARGET_FOLD_BUILTIN
17787 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
17789 #undef TARGET_FUNCTION_ARG
17790 #define TARGET_FUNCTION_ARG aarch64_function_arg
17792 #undef TARGET_FUNCTION_ARG_ADVANCE
17793 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
17795 #undef TARGET_FUNCTION_ARG_BOUNDARY
17796 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
17798 #undef TARGET_FUNCTION_ARG_PADDING
17799 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
17801 #undef TARGET_GET_RAW_RESULT_MODE
17802 #define TARGET_GET_RAW_RESULT_MODE aarch64_get_reg_raw_mode
17803 #undef TARGET_GET_RAW_ARG_MODE
17804 #define TARGET_GET_RAW_ARG_MODE aarch64_get_reg_raw_mode
17806 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
17807 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
17809 #undef TARGET_FUNCTION_VALUE
17810 #define TARGET_FUNCTION_VALUE aarch64_function_value
17812 #undef TARGET_FUNCTION_VALUE_REGNO_P
17813 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
17815 #undef TARGET_GIMPLE_FOLD_BUILTIN
17816 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
17818 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
17819 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
17821 #undef TARGET_INIT_BUILTINS
17822 #define TARGET_INIT_BUILTINS aarch64_init_builtins
17824 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
17825 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
17826 aarch64_ira_change_pseudo_allocno_class
17828 #undef TARGET_LEGITIMATE_ADDRESS_P
17829 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
17831 #undef TARGET_LEGITIMATE_CONSTANT_P
17832 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
17834 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
17835 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
17836 aarch64_legitimize_address_displacement
17838 #undef TARGET_LIBGCC_CMP_RETURN_MODE
17839 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
17841 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
17842 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
17843 aarch64_libgcc_floating_mode_supported_p
17845 #undef TARGET_MANGLE_TYPE
17846 #define TARGET_MANGLE_TYPE aarch64_mangle_type
17848 #undef TARGET_MEMORY_MOVE_COST
17849 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
17851 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
17852 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
17854 #undef TARGET_MUST_PASS_IN_STACK
17855 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
17857 /* This target hook should return true if accesses to volatile bitfields
17858 should use the narrowest mode possible. It should return false if these
17859 accesses should use the bitfield container type. */
17860 #undef TARGET_NARROW_VOLATILE_BITFIELD
17861 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
17863 #undef TARGET_OPTION_OVERRIDE
17864 #define TARGET_OPTION_OVERRIDE aarch64_override_options
17866 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
17867 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
17868 aarch64_override_options_after_change
17870 #undef TARGET_OPTION_SAVE
17871 #define TARGET_OPTION_SAVE aarch64_option_save
17873 #undef TARGET_OPTION_RESTORE
17874 #define TARGET_OPTION_RESTORE aarch64_option_restore
17876 #undef TARGET_OPTION_PRINT
17877 #define TARGET_OPTION_PRINT aarch64_option_print
17879 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
17880 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
17882 #undef TARGET_SET_CURRENT_FUNCTION
17883 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
17885 #undef TARGET_PASS_BY_REFERENCE
17886 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
17888 #undef TARGET_PREFERRED_RELOAD_CLASS
17889 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
17891 #undef TARGET_SCHED_REASSOCIATION_WIDTH
17892 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
17894 #undef TARGET_PROMOTED_TYPE
17895 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
17897 #undef TARGET_SECONDARY_RELOAD
17898 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
17900 #undef TARGET_SHIFT_TRUNCATION_MASK
17901 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
17903 #undef TARGET_SETUP_INCOMING_VARARGS
17904 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
17906 #undef TARGET_STRUCT_VALUE_RTX
17907 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
17909 #undef TARGET_REGISTER_MOVE_COST
17910 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
17912 #undef TARGET_RETURN_IN_MEMORY
17913 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
17915 #undef TARGET_RETURN_IN_MSB
17916 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
17918 #undef TARGET_RTX_COSTS
17919 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
17921 #undef TARGET_SCALAR_MODE_SUPPORTED_P
17922 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
17924 #undef TARGET_SCHED_ISSUE_RATE
17925 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
17927 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
17928 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
17929 aarch64_sched_first_cycle_multipass_dfa_lookahead
17931 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
17932 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
17933 aarch64_first_cycle_multipass_dfa_lookahead_guard
17935 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
17936 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
17937 aarch64_get_separate_components
17939 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
17940 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
17941 aarch64_components_for_bb
17943 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
17944 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
17945 aarch64_disqualify_components
17947 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
17948 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
17949 aarch64_emit_prologue_components
17951 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
17952 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
17953 aarch64_emit_epilogue_components
17955 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
17956 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
17957 aarch64_set_handled_components
17959 #undef TARGET_TRAMPOLINE_INIT
17960 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
17962 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
17963 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
17965 #undef TARGET_VECTOR_MODE_SUPPORTED_P
17966 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
17968 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
17969 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
17970 aarch64_builtin_support_vector_misalignment
17972 #undef TARGET_ARRAY_MODE
17973 #define TARGET_ARRAY_MODE aarch64_array_mode
17975 #undef TARGET_ARRAY_MODE_SUPPORTED_P
17976 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
17978 #undef TARGET_VECTORIZE_ADD_STMT_COST
17979 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
17981 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
17982 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
17983 aarch64_builtin_vectorization_cost
17985 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
17986 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
17988 #undef TARGET_VECTORIZE_BUILTINS
17989 #define TARGET_VECTORIZE_BUILTINS
17991 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
17992 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
17993 aarch64_builtin_vectorized_function
17995 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
17996 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
17997 aarch64_autovectorize_vector_sizes
17999 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
18000 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
18001 aarch64_atomic_assign_expand_fenv
18003 /* Section anchor support. */
18005 #undef TARGET_MIN_ANCHOR_OFFSET
18006 #define TARGET_MIN_ANCHOR_OFFSET -256
18008 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
18009 byte offset; we can do much more for larger data types, but have no way
18010 to determine the size of the access. We assume accesses are aligned. */
18011 #undef TARGET_MAX_ANCHOR_OFFSET
18012 #define TARGET_MAX_ANCHOR_OFFSET 4095
18014 #undef TARGET_VECTOR_ALIGNMENT
18015 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
18017 #undef TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT
18018 #define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
18019 aarch64_vectorize_preferred_vector_alignment
18020 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
18021 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
18022 aarch64_simd_vector_alignment_reachable
18024 /* vec_perm support. */
18026 #undef TARGET_VECTORIZE_VEC_PERM_CONST
18027 #define TARGET_VECTORIZE_VEC_PERM_CONST \
18028 aarch64_vectorize_vec_perm_const
18030 #undef TARGET_VECTORIZE_GET_MASK_MODE
18031 #define TARGET_VECTORIZE_GET_MASK_MODE aarch64_get_mask_mode
18032 #undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
18033 #define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE \
18034 aarch64_empty_mask_is_expensive
18036 #undef TARGET_INIT_LIBFUNCS
18037 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
18039 #undef TARGET_FIXED_CONDITION_CODE_REGS
18040 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
18042 #undef TARGET_FLAGS_REGNUM
18043 #define TARGET_FLAGS_REGNUM CC_REGNUM
18045 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
18046 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
18048 #undef TARGET_ASAN_SHADOW_OFFSET
18049 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
18051 #undef TARGET_LEGITIMIZE_ADDRESS
18052 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
18054 #undef TARGET_SCHED_CAN_SPECULATE_INSN
18055 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
18057 #undef TARGET_CAN_USE_DOLOOP_P
18058 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
18060 #undef TARGET_SCHED_ADJUST_PRIORITY
18061 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
18063 #undef TARGET_SCHED_MACRO_FUSION_P
18064 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
18066 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
18067 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
18069 #undef TARGET_SCHED_FUSION_PRIORITY
18070 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
18072 #undef TARGET_UNSPEC_MAY_TRAP_P
18073 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
18075 #undef TARGET_USE_PSEUDO_PIC_REG
18076 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
18078 #undef TARGET_PRINT_OPERAND
18079 #define TARGET_PRINT_OPERAND aarch64_print_operand
18081 #undef TARGET_PRINT_OPERAND_ADDRESS
18082 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
18084 #undef TARGET_OPTAB_SUPPORTED_P
18085 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
18087 #undef TARGET_OMIT_STRUCT_RETURN_REG
18088 #define TARGET_OMIT_STRUCT_RETURN_REG true
18090 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
18091 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE \
18092 aarch64_dwarf_poly_indeterminate_value
18094 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
18095 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
18096 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
18098 #undef TARGET_HARD_REGNO_NREGS
18099 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
18100 #undef TARGET_HARD_REGNO_MODE_OK
18101 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
18103 #undef TARGET_MODES_TIEABLE_P
18104 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
18106 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
18107 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
18108 aarch64_hard_regno_call_part_clobbered
18110 #undef TARGET_CONSTANT_ALIGNMENT
18111 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
18113 #undef TARGET_COMPUTE_PRESSURE_CLASSES
18114 #define TARGET_COMPUTE_PRESSURE_CLASSES aarch64_compute_pressure_classes
18116 #undef TARGET_CAN_CHANGE_MODE_CLASS
18117 #define TARGET_CAN_CHANGE_MODE_CLASS aarch64_can_change_mode_class
18119 #undef TARGET_SELECT_EARLY_REMAT_MODES
18120 #define TARGET_SELECT_EARLY_REMAT_MODES aarch64_select_early_remat_modes
18122 #if CHECKING_P
18123 #undef TARGET_RUN_TARGET_SELFTESTS
18124 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests