| blob | 805c430c2480bcbe88c6ee00ed24fa684f6f24ce |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
110 #ifndef CHECK_STACK_LIMIT
111 #define CHECK_STACK_LIMIT (-1)
112 #endif
114 /* Return index of given mode in mult and division cost tables. */
115 #define MODE_INDEX(mode) \
116 ((mode) == QImode ? 0 \
117 : (mode) == HImode ? 1 \
118 : (mode) == SImode ? 2 \
119 : (mode) == DImode ? 3 \
120 : 4)
122 /* Processor costs (relative to an add) */
123 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
124 #define COSTS_N_BYTES(N) ((N) * 2)
126 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
135 const
158 in QImode, HImode and SImode.
159 Relative to reg-reg move (2). */
163 in SFmode, DFmode and XFmode */
165 in SFmode, DFmode and XFmode */
168 in SImode and DImode */
170 in SImode and DImode */
173 in SImode, DImode and TImode */
175 in SImode, DImode and TImode */
188 ix86_size_memcpy,
189 ix86_size_memset,
201 };
203 /* Processor costs (relative to an add) */
206 DUMMY_STRINGOP_ALGS};
209 DUMMY_STRINGOP_ALGS};
211 static const
234 in QImode, HImode and SImode.
235 Relative to reg-reg move (2). */
239 in SFmode, DFmode and XFmode */
241 in SFmode, DFmode and XFmode */
244 in SImode and DImode */
246 in SImode and DImode */
249 in SImode, DImode and TImode */
251 in SImode, DImode and TImode */
264 i386_memcpy,
265 i386_memset,
277 };
281 DUMMY_STRINGOP_ALGS};
284 DUMMY_STRINGOP_ALGS};
286 static const
309 in QImode, HImode and SImode.
310 Relative to reg-reg move (2). */
314 in SFmode, DFmode and XFmode */
316 in SFmode, DFmode and XFmode */
319 in SImode and DImode */
321 in SImode and DImode */
324 in SImode, DImode and TImode */
326 in SImode, DImode and TImode */
329 shared for code and data, so 4kB is
330 not really precise. */
341 i486_memcpy,
342 i486_memset,
354 };
358 DUMMY_STRINGOP_ALGS};
361 DUMMY_STRINGOP_ALGS};
363 static const
386 in QImode, HImode and SImode.
387 Relative to reg-reg move (2). */
391 in SFmode, DFmode and XFmode */
393 in SFmode, DFmode and XFmode */
396 in SImode and DImode */
398 in SImode and DImode */
401 in SImode, DImode and TImode */
403 in SImode, DImode and TImode */
416 pentium_memcpy,
417 pentium_memset,
429 };
431 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
432 (we ensure the alignment). For small blocks inline loop is still a
433 noticeable win, for bigger blocks either rep movsl or rep movsb is
434 way to go. Rep movsb has apparently more expensive startup time in CPU,
435 but after 4K the difference is down in the noise. */
440 DUMMY_STRINGOP_ALGS};
445 DUMMY_STRINGOP_ALGS};
446 static const
469 in QImode, HImode and SImode.
470 Relative to reg-reg move (2). */
474 in SFmode, DFmode and XFmode */
476 in SFmode, DFmode and XFmode */
479 in SImode and DImode */
481 in SImode and DImode */
484 in SImode, DImode and TImode */
486 in SImode, DImode and TImode */
499 pentiumpro_memcpy,
500 pentiumpro_memset,
512 };
516 DUMMY_STRINGOP_ALGS};
519 DUMMY_STRINGOP_ALGS};
520 static const
543 in QImode, HImode and SImode.
544 Relative to reg-reg move (2). */
548 in SFmode, DFmode and XFmode */
550 in SFmode, DFmode and XFmode */
554 in SImode and DImode */
556 in SImode and DImode */
559 in SImode, DImode and TImode */
561 in SImode, DImode and TImode */
574 geode_memcpy,
575 geode_memset,
587 };
591 DUMMY_STRINGOP_ALGS};
594 DUMMY_STRINGOP_ALGS};
595 static const
618 in QImode, HImode and SImode.
619 Relative to reg-reg move (2). */
623 in SFmode, DFmode and XFmode */
625 in SFmode, DFmode and XFmode */
628 in SImode and DImode */
630 in SImode and DImode */
633 in SImode, DImode and TImode */
635 in SImode, DImode and TImode */
639 have integrated l2 cache, but
640 optimizing for k6 is not important
641 enough to worry about that. */
651 k6_memcpy,
652 k6_memset,
664 };
666 /* For some reason, Athlon deals better with REP prefix (relative to loops)
667 compared to K8. Alignment becomes important after 8 bytes for memcpy and
668 128 bytes for memset. */
671 DUMMY_STRINGOP_ALGS};
674 DUMMY_STRINGOP_ALGS};
675 static const
698 in QImode, HImode and SImode.
699 Relative to reg-reg move (2). */
703 in SFmode, DFmode and XFmode */
705 in SFmode, DFmode and XFmode */
708 in SImode and DImode */
710 in SImode and DImode */
713 in SImode, DImode and TImode */
715 in SImode, DImode and TImode */
728 athlon_memcpy,
729 athlon_memset,
741 };
743 /* K8 has optimized REP instruction for medium sized blocks, but for very
744 small blocks it is better to use loop. For large blocks, libcall can
745 do nontemporary accesses and beat inline considerably. */
756 static const
779 in QImode, HImode and SImode.
780 Relative to reg-reg move (2). */
784 in SFmode, DFmode and XFmode */
786 in SFmode, DFmode and XFmode */
789 in SImode and DImode */
791 in SImode and DImode */
794 in SImode, DImode and TImode */
796 in SImode, DImode and TImode */
801 /* New AMD processors never drop prefetches; if they cannot be performed
802 immediately, they are queued. We set number of simultaneous prefetches
803 to a large constant to reflect this (it probably is not a good idea not
804 to limit number of prefetches at all, as their execution also takes some
805 time). */
815 k8_memcpy,
816 k8_memset,
828 };
830 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
831 very small blocks it is better to use loop. For large blocks, libcall can
832 do nontemporary accesses and beat inline considerably. */
865 in QImode, HImode and SImode.
866 Relative to reg-reg move (2). */
870 in SFmode, DFmode and XFmode */
872 in SFmode, DFmode and XFmode */
875 in SImode and DImode */
877 in SImode and DImode */
880 in SImode, DImode and TImode */
882 in SImode, DImode and TImode */
884 /* On K8:
885 MOVD reg64, xmmreg Double FSTORE 4
886 MOVD reg32, xmmreg Double FSTORE 4
887 On AMDFAM10:
888 MOVD reg64, xmmreg Double FADD 3
889 1/1 1/1
890 MOVD reg32, xmmreg Double FADD 3
891 1/1 1/1 */
895 /* New AMD processors never drop prefetches; if they cannot be performed
896 immediately, they are queued. We set number of simultaneous prefetches
897 to a large constant to reflect this (it probably is not a good idea not
898 to limit number of prefetches at all, as their execution also takes some
899 time). */
909 amdfam10_memcpy,
910 amdfam10_memset,
922 };
924 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
925 very small blocks it is better to use loop. For large blocks, libcall
926 can do nontemporary accesses and beat inline considerably. */
960 in QImode, HImode and SImode.
961 Relative to reg-reg move (2). */
965 in SFmode, DFmode and XFmode */
967 in SFmode, DFmode and XFmode */
970 in SImode and DImode */
972 in SImode and DImode */
975 in SImode, DImode and TImode */
977 in SImode, DImode and TImode */
979 /* On K8:
980 MOVD reg64, xmmreg Double FSTORE 4
981 MOVD reg32, xmmreg Double FSTORE 4
982 On AMDFAM10:
983 MOVD reg64, xmmreg Double FADD 3
984 1/1 1/1
985 MOVD reg32, xmmreg Double FADD 3
986 1/1 1/1 */
990 /* New AMD processors never drop prefetches; if they cannot be performed
991 immediately, they are queued. We set number of simultaneous prefetches
992 to a large constant to reflect this (it probably is not a good idea not
993 to limit number of prefetches at all, as their execution also takes some
994 time). */
1004 bdver1_memcpy,
1005 bdver1_memset,
1017 };
1019 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1020 very small blocks it is better to use loop. For large blocks, libcall
1021 can do nontemporary accesses and beat inline considerably. */
1056 in QImode, HImode and SImode.
1057 Relative to reg-reg move (2). */
1061 in SFmode, DFmode and XFmode */
1063 in SFmode, DFmode and XFmode */
1066 in SImode and DImode */
1068 in SImode and DImode */
1071 in SImode, DImode and TImode */
1073 in SImode, DImode and TImode */
1075 /* On K8:
1076 MOVD reg64, xmmreg Double FSTORE 4
1077 MOVD reg32, xmmreg Double FSTORE 4
1078 On AMDFAM10:
1079 MOVD reg64, xmmreg Double FADD 3
1080 1/1 1/1
1081 MOVD reg32, xmmreg Double FADD 3
1082 1/1 1/1 */
1086 /* New AMD processors never drop prefetches; if they cannot be performed
1087 immediately, they are queued. We set number of simultaneous prefetches
1088 to a large constant to reflect this (it probably is not a good idea not
1089 to limit number of prefetches at all, as their execution also takes some
1090 time). */
1100 bdver2_memcpy,
1101 bdver2_memset,
1113 };
1116 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1117 very small blocks it is better to use loop. For large blocks, libcall
1118 can do nontemporary accesses and beat inline considerably. */
1151 in QImode, HImode and SImode.
1152 Relative to reg-reg move (2). */
1156 in SFmode, DFmode and XFmode */
1158 in SFmode, DFmode and XFmode */
1161 in SImode and DImode */
1163 in SImode and DImode */
1166 in SImode, DImode and TImode */
1168 in SImode, DImode and TImode */
1173 /* New AMD processors never drop prefetches; if they cannot be performed
1174 immediately, they are queued. We set number of simultaneous prefetches
1175 to a large constant to reflect this (it probably is not a good idea not
1176 to limit number of prefetches at all, as their execution also takes some
1177 time). */
1187 bdver3_memcpy,
1188 bdver3_memset,
1200 };
1202 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1203 very small blocks it is better to use loop. For large blocks, libcall
1204 can do nontemporary accesses and beat inline considerably. */
1237 in QImode, HImode and SImode.
1238 Relative to reg-reg move (2). */
1242 in SFmode, DFmode and XFmode */
1244 in SFmode, DFmode and XFmode */
1247 in SImode and DImode */
1249 in SImode and DImode */
1252 in SImode, DImode and TImode */
1254 in SImode, DImode and TImode */
1259 /* New AMD processors never drop prefetches; if they cannot be performed
1260 immediately, they are queued. We set number of simultaneous prefetches
1261 to a large constant to reflect this (it probably is not a good idea not
1262 to limit number of prefetches at all, as their execution also takes some
1263 time). */
1273 bdver4_memcpy,
1274 bdver4_memset,
1286 };
1288 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1289 very small blocks it is better to use loop. For large blocks, libcall can
1290 do nontemporary accesses and beat inline considerably. */
1323 in QImode, HImode and SImode.
1324 Relative to reg-reg move (2). */
1328 in SFmode, DFmode and XFmode */
1330 in SFmode, DFmode and XFmode */
1333 in SImode and DImode */
1335 in SImode and DImode */
1338 in SImode, DImode and TImode */
1340 in SImode, DImode and TImode */
1342 /* On K8:
1343 MOVD reg64, xmmreg Double FSTORE 4
1344 MOVD reg32, xmmreg Double FSTORE 4
1345 On AMDFAM10:
1346 MOVD reg64, xmmreg Double FADD 3
1347 1/1 1/1
1348 MOVD reg32, xmmreg Double FADD 3
1349 1/1 1/1 */
1362 btver1_memcpy,
1363 btver1_memset,
1375 };
1409 in QImode, HImode and SImode.
1410 Relative to reg-reg move (2). */
1414 in SFmode, DFmode and XFmode */
1416 in SFmode, DFmode and XFmode */
1419 in SImode and DImode */
1421 in SImode and DImode */
1424 in SImode, DImode and TImode */
1426 in SImode, DImode and TImode */
1428 /* On K8:
1429 MOVD reg64, xmmreg Double FSTORE 4
1430 MOVD reg32, xmmreg Double FSTORE 4
1431 On AMDFAM10:
1432 MOVD reg64, xmmreg Double FADD 3
1433 1/1 1/1
1434 MOVD reg32, xmmreg Double FADD 3
1435 1/1 1/1 */
1447 btver2_memcpy,
1448 btver2_memset,
1460 };
1464 DUMMY_STRINGOP_ALGS};
1468 DUMMY_STRINGOP_ALGS};
1470 static const
1493 in QImode, HImode and SImode.
1494 Relative to reg-reg move (2). */
1498 in SFmode, DFmode and XFmode */
1500 in SFmode, DFmode and XFmode */
1503 in SImode and DImode */
1505 in SImode and DImode */
1508 in SImode, DImode and TImode */
1510 in SImode, DImode and TImode */
1523 pentium4_memcpy,
1524 pentium4_memset,
1536 };
1549 static const
1572 in QImode, HImode and SImode.
1573 Relative to reg-reg move (2). */
1577 in SFmode, DFmode and XFmode */
1579 in SFmode, DFmode and XFmode */
1582 in SImode and DImode */
1584 in SImode and DImode */
1587 in SImode, DImode and TImode */
1589 in SImode, DImode and TImode */
1602 nocona_memcpy,
1603 nocona_memset,
1615 };
1626 static const
1649 in QImode, HImode and SImode.
1650 Relative to reg-reg move (2). */
1654 in SFmode, DFmode and XFmode */
1656 in SFmode, DFmode and XFmode */
1659 in SImode and DImode */
1661 in SImode and DImode */
1664 in SImode, DImode and TImode */
1666 in SImode, DImode and TImode */
1679 atom_memcpy,
1680 atom_memset,
1692 };
1703 static const
1726 in QImode, HImode and SImode.
1727 Relative to reg-reg move (2). */
1731 in SFmode, DFmode and XFmode */
1733 in SFmode, DFmode and XFmode */
1736 in SImode and DImode */
1738 in SImode and DImode */
1741 in SImode, DImode and TImode */
1743 in SImode, DImode and TImode */
1756 slm_memcpy,
1757 slm_memset,
1769 };
1780 static const
1803 in QImode, HImode and SImode.
1804 Relative to reg-reg move (2). */
1808 in SFmode, DFmode and XFmode */
1810 in SFmode, DFmode and XFmode */
1813 in SImode and DImode */
1815 in SImode and DImode */
1818 in SImode, DImode and TImode */
1820 in SImode, DImode and TImode */
1833 intel_memcpy,
1834 intel_memset,
1846 };
1848 /* Generic should produce code tuned for Core-i7 (and newer chips)
1849 and btver1 (and newer chips). */
1861 static const
1864 /* On all chips taken into consideration lea is 2 cycles and more. With
1865 this cost however our current implementation of synth_mult results in
1866 use of unnecessary temporary registers causing regression on several
1867 SPECfp benchmarks. */
1888 in QImode, HImode and SImode.
1889 Relative to reg-reg move (2). */
1893 in SFmode, DFmode and XFmode */
1895 in SFmode, DFmode and XFmode */
1898 in SImode and DImode */
1900 in SImode and DImode */
1903 in SImode, DImode and TImode */
1905 in SImode, DImode and TImode */
1911 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1912 value is increased to perhaps more appropriate value of 5. */
1920 generic_memcpy,
1921 generic_memset,
1933 };
1935 /* core_cost should produce code tuned for Core familly of CPUs. */
1948 static const
1951 /* On all chips taken into consideration lea is 2 cycles and more. With
1952 this cost however our current implementation of synth_mult results in
1953 use of unnecessary temporary registers causing regression on several
1954 SPECfp benchmarks. */
1975 in QImode, HImode and SImode.
1976 Relative to reg-reg move (2). */
1980 in SFmode, DFmode and XFmode */
1982 in SFmode, DFmode and XFmode */
1985 in SImode and DImode */
1987 in SImode and DImode */
1990 in SImode, DImode and TImode */
1992 in SImode, DImode and TImode */
1998 /* FIXME perhaps more appropriate value is 5. */
2006 core_memcpy,
2007 core_memset,
2019 };
2022 /* Set by -mtune. */
2025 /* Set by -mtune or -Os. */
2028 /* Processor feature/optimization bitmasks. */
2029 #define m_386 (1<<PROCESSOR_I386)
2030 #define m_486 (1<<PROCESSOR_I486)
2031 #define m_PENT (1<<PROCESSOR_PENTIUM)
2032 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2033 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2034 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2035 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2036 #define m_CORE2 (1<<PROCESSOR_CORE2)
2037 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2038 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2039 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2040 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2041 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2042 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2043 #define m_INTEL (1<<PROCESSOR_INTEL)
2045 #define m_GEODE (1<<PROCESSOR_GEODE)
2046 #define m_K6 (1<<PROCESSOR_K6)
2047 #define m_K6_GEODE (m_K6 | m_GEODE)
2048 #define m_K8 (1<<PROCESSOR_K8)
2049 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2050 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2051 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2052 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2053 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2054 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2055 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2056 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2057 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2058 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2059 #define m_BTVER (m_BTVER1 | m_BTVER2)
2060 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2062 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2065 #undef DEF_TUNE
2066 #define DEF_TUNE(tune, name, selector) name,
2068 #undef DEF_TUNE
2069 };
2071 /* Feature tests against the various tunings. */
2074 /* Feature tests against the various tunings used to create ix86_tune_features
2075 based on the processor mask. */
2077 #undef DEF_TUNE
2078 #define DEF_TUNE(tune, name, selector) selector,
2080 #undef DEF_TUNE
2081 };
2083 /* Feature tests against the various architecture variations. */
2086 /* Feature tests against the various architecture variations, used to create
2087 ix86_arch_features based on the processor mask. */
2089 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2092 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2095 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2098 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2101 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2103 };
2105 /* In case the average insn count for single function invocation is
2106 lower than this constant, emit fast (but longer) prologue and
2107 epilogue code. */
2108 #define FAST_PROLOGUE_INSN_COUNT 20
2110 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2115 /* Array of the smallest class containing reg number REGNO, indexed by
2116 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2119 {
2120 /* ax, dx, cx, bx */
2122 /* si, di, bp, sp */
2124 /* FP registers */
2127 /* arg pointer */
2128 NON_Q_REGS,
2129 /* flags, fpsr, fpcr, frame */
2131 /* SSE registers */
2134 /* MMX registers */
2137 /* REX registers */
2140 /* SSE REX registers */
2143 /* AVX-512 SSE registers */
2148 /* Mask registers. */
2151 /* MPX bound registers */
2153 };
2155 /* The "default" register map used in 32bit mode. */
2158 {
2170 };
2172 /* The "default" register map used in 64bit mode. */
2175 {
2187 };
2189 /* Define the register numbers to be used in Dwarf debugging information.
2190 The SVR4 reference port C compiler uses the following register numbers
2191 in its Dwarf output code:
2192 0 for %eax (gcc regno = 0)
2193 1 for %ecx (gcc regno = 2)
2194 2 for %edx (gcc regno = 1)
2195 3 for %ebx (gcc regno = 3)
2196 4 for %esp (gcc regno = 7)
2197 5 for %ebp (gcc regno = 6)
2198 6 for %esi (gcc regno = 4)
2199 7 for %edi (gcc regno = 5)
2200 The following three DWARF register numbers are never generated by
2201 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2202 believes these numbers have these meanings.
2203 8 for %eip (no gcc equivalent)
2204 9 for %eflags (gcc regno = 17)
2205 10 for %trapno (no gcc equivalent)
2206 It is not at all clear how we should number the FP stack registers
2207 for the x86 architecture. If the version of SDB on x86/svr4 were
2208 a bit less brain dead with respect to floating-point then we would
2209 have a precedent to follow with respect to DWARF register numbers
2210 for x86 FP registers, but the SDB on x86/svr4 is so completely
2211 broken with respect to FP registers that it is hardly worth thinking
2212 of it as something to strive for compatibility with.
2213 The version of x86/svr4 SDB I have at the moment does (partially)
2214 seem to believe that DWARF register number 11 is associated with
2215 the x86 register %st(0), but that's about all. Higher DWARF
2216 register numbers don't seem to be associated with anything in
2217 particular, and even for DWARF regno 11, SDB only seems to under-
2218 stand that it should say that a variable lives in %st(0) (when
2219 asked via an `=' command) if we said it was in DWARF regno 11,
2220 but SDB still prints garbage when asked for the value of the
2221 variable in question (via a `/' command).
2222 (Also note that the labels SDB prints for various FP stack regs
2223 when doing an `x' command are all wrong.)
2224 Note that these problems generally don't affect the native SVR4
2225 C compiler because it doesn't allow the use of -O with -g and
2226 because when it is *not* optimizing, it allocates a memory
2227 location for each floating-point variable, and the memory
2228 location is what gets described in the DWARF AT_location
2229 attribute for the variable in question.
2230 Regardless of the severe mental illness of the x86/svr4 SDB, we
2231 do something sensible here and we use the following DWARF
2232 register numbers. Note that these are all stack-top-relative
2233 numbers.
2234 11 for %st(0) (gcc regno = 8)
2235 12 for %st(1) (gcc regno = 9)
2236 13 for %st(2) (gcc regno = 10)
2237 14 for %st(3) (gcc regno = 11)
2238 15 for %st(4) (gcc regno = 12)
2239 16 for %st(5) (gcc regno = 13)
2240 17 for %st(6) (gcc regno = 14)
2241 18 for %st(7) (gcc regno = 15)
2242 */
2244 {
2256 };
2258 /* Define parameter passing and return registers. */
2261 {
2263 };
2266 {
2268 };
2271 {
2273 };
2275 /* Additional registers that are clobbered by SYSV calls. */
2278 {
2283 };
2285 /* Define the structure for the machine field in struct function. */
2290 rtx rtl;
2292 };
2294 /* Structure describing stack frame layout.
2295 Stack grows downward:
2297 [arguments]
2298 <- ARG_POINTER
2299 saved pc
2301 saved static chain if ix86_static_chain_on_stack
2303 saved frame pointer if frame_pointer_needed
2304 <- HARD_FRAME_POINTER
2305 [saved regs]
2306 <- regs_save_offset
2307 [padding0]
2309 [saved SSE regs]
2310 <- sse_regs_save_offset
2311 [padding1] |
2312 | <- FRAME_POINTER
2313 [va_arg registers] |
2314 |
2315 [frame] |
2316 |
2317 [padding2] | = to_allocate
2318 <- STACK_POINTER
2319 */
2320 struct ix86_frame
2321 {
2328 /* The offsets relative to ARG_POINTER. */
2329 HOST_WIDE_INT frame_pointer_offset;
2330 HOST_WIDE_INT hard_frame_pointer_offset;
2331 HOST_WIDE_INT stack_pointer_offset;
2332 HOST_WIDE_INT hfp_save_offset;
2333 HOST_WIDE_INT reg_save_offset;
2334 HOST_WIDE_INT sse_reg_save_offset;
2336 /* When save_regs_using_mov is set, emit prologue using
2337 move instead of push instructions. */
2339 };
2341 /* Which cpu are we scheduling for. */
2344 /* Which cpu are we optimizing for. */
2347 /* Which instruction set architecture to use. */
2350 /* True if processor has SSE prefetch instruction. */
2353 /* -mstackrealign option */
2370 /* Preferred alignment for stack boundary in bits. */
2373 /* Alignment for incoming stack boundary in bits specified at
2374 command line. */
2377 /* Default alignment for incoming stack boundary in bits. */
2380 /* Alignment for incoming stack boundary in bits. */
2383 /* Calling abi specific va_list type nodes. */
2387 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2391 /* Fence to use after loop using movnt. */
2392 tree x86_mfence;
2394 /* Register class used for passing given 64bit part of the argument.
2395 These represent classes as documented by the PS ABI, with the exception
2396 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2397 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2399 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2400 whenever possible (upper half does contain padding). */
2401 enum x86_64_reg_class
2402 {
2403 X86_64_NO_CLASS,
2404 X86_64_INTEGER_CLASS,
2405 X86_64_INTEGERSI_CLASS,
2406 X86_64_SSE_CLASS,
2407 X86_64_SSESF_CLASS,
2408 X86_64_SSEDF_CLASS,
2409 X86_64_SSEUP_CLASS,
2410 X86_64_X87_CLASS,
2411 X86_64_X87UP_CLASS,
2412 X86_64_COMPLEX_X87_CLASS,
2413 X86_64_MEMORY_CLASS
2414 };
2416 #define MAX_CLASSES 8
2418 /* Table of constants used by fldpi, fldln2, etc.... */
2422 \f
2427 const_tree);
2439 enum ix86_function_specific_strings
2440 {
2441 IX86_FUNCTION_SPECIFIC_ARCH,
2442 IX86_FUNCTION_SPECIFIC_TUNE,
2443 IX86_FUNCTION_SPECIFIC_MAX
2444 };
2465 \f
2466 #ifndef SUBTARGET32_DEFAULT_CPU
2468 #endif
2470 /* Whether -mtune= or -march= were specified */
2474 /* Vectorization library interface and handlers. */
2480 /* Processor target table, indexed by processor number */
2481 struct ptt
2482 {
2490 };
2492 /* This table must be in sync with enum processor_type in i386.h. */
2494 {
2520 };
2521 \f
2522 static unsigned int
2524 {
2527 /* vzeroupper instructions are inserted immediately after reload to
2528 account for possible spills from 256bit registers. The pass
2529 reuses mode switching infrastructure by re-running mode insertion
2530 pass, so disable entities that have already been processed. */
2536 /* Call optimize_mode_switching. */
2539 }
2544 {
2554 };
2557 {
2561 {}
2563 /* opt_pass methods: */
2565 {
2567 }
2570 {
2572 }
2578 rtl_opt_pass *
2580 {
2582 }
2584 /* Return true if a red-zone is in use. */
2588 {
2590 }
2591 \f
2592 /* Return a string that documents the current -m options. The caller is
2593 responsible for freeing the string. */
2599 {
2600 struct ix86_target_opts
2601 {
2604 };
2606 /* This table is ordered so that options like -msse4.2 that imply
2607 preceding options while match those first. */
2609 {
2658 };
2660 /* Flag options. */
2662 {
2691 };
2708 /* Add -march= option. */
2710 {
2713 }
2715 /* Add -mtune= option. */
2717 {
2720 }
2722 /* Add -m32/-m64/-mx32. */
2724 {
2727 else
2729 isa &= ~ (OPTION_MASK_ISA_64BIT
2730 | OPTION_MASK_ABI_64
2732 }
2733 else
2737 /* Pick out the options in isa options. */
2739 {
2741 {
2744 }
2745 }
2748 {
2751 isa);
2752 }
2754 /* Add flag options. */
2756 {
2758 {
2761 }
2762 }
2765 {
2768 }
2770 /* Add -fpmath= option. */
2772 {
2775 {
2790 }
2791 }
2793 /* Any options? */
2799 /* Size the string. */
2803 {
2808 }
2810 /* Build the string. */
2815 {
2822 {
2824 line_len++;
2827 {
2831 }
2832 }
2836 {
2840 }
2841 }
2847 }
2849 /* Return true, if profiling code should be emitted before
2850 prologue. Otherwise it returns false.
2851 Note: For x86 with "hotfix" it is sorried. */
2852 static bool
2854 {
2856 }
2858 /* Function that is callable from the debugger to print the current
2859 options. */
2860 void ATTRIBUTE_UNUSED
2862 {
2868 {
2871 }
2872 else
2876 }
2879 #define DEF_ENUM
2880 #define DEF_ALG(alg, name) #name,
2882 #undef DEF_ENUM
2883 #undef DEF_ALG
2884 };
2886 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2887 The string is of the following form (or comma separated list of it):
2889 strategy_alg:max_size:[align|noalign]
2891 where the full size range for the strategy is either [0, max_size] or
2892 [min_size, max_size], in which min_size is the max_size + 1 of the
2893 preceding range. The last size range must have max_size == -1.
2895 Examples:
2897 1.
2898 -mmemcpy-strategy=libcall:-1:noalign
2900 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2903 2.
2904 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2906 This is to tell the compiler to use the following strategy for memset
2907 1) when the expected size is between [1, 16], use rep_8byte strategy;
2908 2) when the size is between [17, 2048], use vector_loop;
2909 3) when the size is > 2048, use libcall. */
2911 struct stringop_size_range
2912 {
2914 stringop_alg alg;
2916 };
2918 static void
2920 {
2928 else
2933 do
2934 {
2944 {
2948 }
2951 {
2955 }
2962 {
2964 alg_name,
2967 }
2975 else
2976 {
2980 }
2981 n++;
2983 }
2987 {
2992 }
2995 {
2999 }
3001 /* Now override the default algs array. */
3003 {
3009 }
3010 }
3012 \f
3013 /* parse -mtune-ctrl= option. When DUMP is true,
3014 print the features that are explicitly set. */
3016 static void
3018 {
3026 do
3027 {
3034 {
3035 curr_feature_string++;
3037 }
3039 {
3041 {
3047 }
3048 }
3053 }
3056 }
3058 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3059 processor type. */
3061 static void
3063 {
3068 {
3071 else
3073 }
3076 {
3081 }
3084 }
3087 /* Override various settings based on options. If MAIN_ARGS_P, the
3088 options are from the command line, otherwise they are from
3089 attributes. */
3091 static void
3095 {
3103 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3104 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3105 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3106 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3107 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3108 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3109 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3110 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3111 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3112 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3113 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3114 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3115 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3116 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3117 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3118 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3119 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3120 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3121 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3122 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3123 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3124 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3125 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3126 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3127 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3128 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3129 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3130 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3131 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3132 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3133 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3134 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3135 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3136 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3137 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3138 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3139 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3140 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3141 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3142 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3143 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3144 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3145 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3146 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3147 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3148 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3149 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3150 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3151 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3152 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3153 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3154 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3155 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3157 #define PTA_CORE2 \
3158 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3159 | PTA_CX16 | PTA_FXSR)
3160 #define PTA_NEHALEM \
3161 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3162 #define PTA_WESTMERE \
3163 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3164 #define PTA_SANDYBRIDGE \
3165 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3166 #define PTA_IVYBRIDGE \
3167 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3168 #define PTA_HASWELL \
3169 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3170 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3171 #define PTA_BROADWELL \
3172 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3173 #define PTA_BONNELL \
3174 (PTA_CORE2 | PTA_MOVBE)
3175 #define PTA_SILVERMONT \
3176 (PTA_WESTMERE | PTA_MOVBE)
3178 /* if this reaches 64, need to widen struct pta flags below */
3180 static struct pta
3181 {
3186 }
3188 {
3222 PTA_SANDYBRIDGE},
3224 PTA_SANDYBRIDGE},
3226 PTA_IVYBRIDGE},
3228 PTA_IVYBRIDGE},
3319 PTA_64BIT
3321 };
3323 /* -mrecip options. */
3324 static struct
3325 {
3328 }
3330 {
3337 };
3341 /* Set up prefix/suffix so the error messages refer to either the command
3342 line argument, or the attribute(target). */
3344 {
3348 }
3349 else
3350 {
3354 }
3356 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3357 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3360 #ifdef TARGET_BI_ARCH
3361 else
3362 {
3363 #if TARGET_BI_ARCH == 1
3364 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3365 is on and OPTION_MASK_ABI_X32 is off. We turn off
3366 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3367 -mx32. */
3370 #else
3371 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3372 on and OPTION_MASK_ABI_64 is off. We turn off
3373 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3374 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3378 #endif
3379 }
3380 #endif
3383 {
3384 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3385 OPTION_MASK_ABI_64 for TARGET_X32. */
3388 }
3391 | OPTION_MASK_ABI_X32
3394 {
3395 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3396 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3399 }
3401 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3402 SUBTARGET_OVERRIDE_OPTIONS;
3403 #endif
3405 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3406 SUBSUBTARGET_OVERRIDE_OPTIONS;
3407 #endif
3409 /* -fPIC is the default for x86_64. */
3413 /* Need to check -mtune=generic first. */
3415 {
3416 /* As special support for cross compilers we read -mtune=native
3417 as -mtune=generic. With native compilers we won't see the
3418 -mtune=native, as it was changed by the driver. */
3420 {
3422 }
3427 }
3428 else
3429 {
3433 {
3434 opts->x_ix86_tune_string
3437 }
3439 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3440 or defaulted. We need to use a sensible tune option. */
3442 {
3444 }
3445 }
3449 {
3450 /* rep; movq isn't available in 32-bit code. */
3453 }
3456 opts->x_ix86_arch_string
3459 else
3463 {
3471 }
3472 else
3479 /* For targets using ms ABI enable ms-extensions, if not
3480 explicit turned off. For non-ms ABI we turn off this
3481 option. */
3486 {
3488 {
3532 {
3535 }
3543 }
3544 }
3545 else
3546 {
3547 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3548 use of rip-relative addressing. This eliminates fixups that
3549 would otherwise be needed if this object is to be placed in a
3550 DLL, and is essentially just as efficient as direct addressing. */
3556 else
3558 }
3560 {
3563 }
3571 {
3574 /* Default cpu tuning to the architecture. */
3740 }
3764 {
3768 {
3770 {
3772 {
3780 }
3781 else
3784 }
3785 }
3786 /* Intel CPUs have always interpreted SSE prefetch instructions as
3787 NOPs; so, we can enable SSE prefetch instructions even when
3788 -mtune (rather than -march) points us to a processor that has them.
3789 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3790 higher processors. */
3795 }
3803 #ifndef USE_IX86_FRAME_POINTER
3804 #define USE_IX86_FRAME_POINTER 0
3805 #endif
3807 #ifndef USE_X86_64_FRAME_POINTER
3808 #define USE_X86_64_FRAME_POINTER 0
3809 #endif
3811 /* Set the default values for switches whose default depends on TARGET_64BIT
3812 in case they weren't overwritten by command line options. */
3814 {
3822 opts->x_flag_unwind_tables
3826 }
3827 else
3828 {
3830 opts->x_flag_omit_frame_pointer
3836 }
3841 else
3844 /* Arrange to set up i386_stack_locals for all functions. */
3847 /* Validate -mregparm= value. */
3849 {
3853 {
3857 }
3858 }
3862 /* Default align_* from the processor table. */
3864 {
3867 }
3869 {
3872 }
3874 {
3876 }
3878 /* Provide default for -mbranch-cost= value. */
3883 {
3884 opts->x_target_flags
3887 /* Enable by default the SSE and MMX builtins. Do allow the user to
3888 explicitly disable any of these. In particular, disabling SSE and
3889 MMX for kernel code is extremely useful. */
3891 opts->x_ix86_isa_flags
3898 }
3899 else
3900 {
3901 opts->x_target_flags
3905 opts->x_ix86_isa_flags
3908 /* i386 ABI does not specify red zone. It still makes sense to use it
3909 when programmer takes care to stack from being destroyed. */
3912 }
3914 /* Keep nonleaf frame pointers. */
3920 /* If we're doing fast math, we don't care about comparison order
3921 wrt NaNs. This lets us use a shorter comparison sequence. */
3925 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3926 since the insns won't need emulation. */
3930 /* Likewise, if the target doesn't have a 387, or we've specified
3931 software floating point, don't use 387 inline intrinsics. */
3935 /* Turn on MMX builtins for -msse. */
3937 opts->x_ix86_isa_flags
3940 /* Enable SSE prefetch. */
3945 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3948 opts->x_ix86_isa_flags
3951 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3954 opts->x_ix86_isa_flags
3957 /* Enable lzcnt instruction for -mabm. */
3959 opts->x_ix86_isa_flags
3962 /* Validate -mpreferred-stack-boundary= value or default it to
3963 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3966 {
3973 {
3977 else
3980 }
3981 else
3982 ix86_preferred_stack_boundary
3984 }
3986 /* Set the default value for -mstackrealign. */
3992 /* Validate -mincoming-stack-boundary= value or default it to
3993 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3996 {
4003 else
4004 {
4005 ix86_user_incoming_stack_boundary
4007 ix86_incoming_stack_boundary
4009 }
4010 }
4012 #ifndef NO_PROFILE_COUNTERS
4015 #endif
4019 /* Accept -msseregparm only if at least SSE support is enabled. */
4025 {
4027 {
4029 {
4032 }
4035 {
4038 }
4039 }
4040 }
4041 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4042 fpmath=387. The second is however default at many targets since the
4043 extra 80bit precision of temporaries is considered to be part of ABI.
4044 Overwrite the default at least for -ffast-math.
4045 TODO: -mfpmath=both seems to produce same performing code with bit
4046 smaller binaries. It is however not clear if register allocation is
4047 ready for this setting.
4048 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4049 codegen. We may switch to 387 with -ffast-math for size optimized
4050 functions. */
4054 else
4057 /* If the i387 is disabled, then do not return values in it. */
4061 /* Use external vectorized library in vectorizing intrinsics. */
4064 {
4075 }
4082 /* If stack probes are required, the space used for large function
4083 arguments on the stack must also be probed, so enable
4084 -maccumulate-outgoing-args so this happens in the prologue. */
4087 {
4092 }
4094 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4095 {
4101 }
4103 /* When scheduling description is not available, disable scheduler pass
4104 so it won't slow down the compilation and make x87 code slower. */
4125 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4127 && HAVE_prefetch
4132 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4133 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4138 {
4141 {
4143 ix86_gen_tls_local_dynamic_base_64
4145 }
4146 else
4147 {
4149 ix86_gen_tls_local_dynamic_base_64
4151 }
4152 }
4153 else
4157 {
4167 }
4168 else
4169 {
4179 }
4181 #ifdef USE_IX86_CLD
4182 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4185 #endif
4188 {
4193 }
4195 {
4199 }
4201 {
4202 #if defined(PROFILE_BEFORE_PROLOGUE)
4204 #else
4206 #endif
4207 }
4209 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4210 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4211 AVX unaligned load/store. */
4213 {
4223 /* Enable 128-bit AVX instruction generation
4224 for the auto-vectorizer. */
4228 }
4231 {
4238 {
4241 {
4243 q++;
4244 }
4245 else
4250 else
4251 {
4254 {
4257 }
4260 {
4264 }
4265 }
4270 else
4272 }
4273 }
4280 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4281 for 64-bit Bionic. */
4286 ? MASK_LONG_DOUBLE_128
4289 /* Only one of them can be active. */
4293 /* Save the initial options in case the user does function specific
4294 options. */
4296 target_option_default_node = target_option_current_node
4299 /* Handle stack protector */
4301 opts->x_ix86_stack_protector_guard
4304 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4306 {
4310 }
4313 {
4317 }
4318 }
4320 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4322 static void
4324 {
4326 struct register_pass_info insert_vzeroupper_info
4329 };
4334 /* This needs to be done at start up. It's convenient to do it here. */
4336 }
4338 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4341 {
4345 }
4347 /* Update register usage after having seen the compiler flags. */
4349 static void
4351 {
4355 /* The PIC register, if it exists, is fixed. */
4360 /* For 32-bit targets, squash the REX registers. */
4362 {
4369 }
4371 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4379 {
4380 /* Set/reset conditionally defined registers from
4381 CALL_USED_REGISTERS initializer. */
4385 /* Calculate registers of CLOBBERED_REGS register set
4386 as call used registers from GENERAL_REGS register set. */
4390 }
4392 /* If MMX is disabled, squash the registers. */
4398 /* If SSE is disabled, squash the registers. */
4404 /* If the FPU is disabled, squash the registers. */
4410 /* If AVX512F is disabled, squash the registers. */
4412 {
4418 }
4420 /* If MPX is disabled, squash the registers. */
4424 }
4426 \f
4427 /* Save the current options */
4429 static void
4432 {
4467 /* The fields are char but the variables are not; make sure the
4468 values fit in the fields. */
4473 }
4475 /* Restore the current options */
4477 static void
4480 {
4486 /* We don't change -fPIC. */
4523 /* Recreate the arch feature tests if the arch changed */
4525 {
4530 }
4532 /* Recreate the tune optimization tests */
4535 }
4537 /* Print the current options */
4539 static void
4542 {
4560 {
4563 }
4564 }
4566 \f
4567 /* Inner function to process the attribute((target(...))), take an argument and
4568 set the current options from the argument. If we have a list, recursively go
4569 over the list. */
4571 static bool
4576 {
4580 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4581 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4582 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4583 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4584 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4586 enum ix86_opt_type
4587 {
4588 ix86_opt_unknown,
4589 ix86_opt_yes,
4590 ix86_opt_no,
4591 ix86_opt_str,
4592 ix86_opt_enum,
4593 ix86_opt_isa
4594 };
4596 static const struct
4597 {
4604 /* isa options */
4653 /* enum options */
4656 /* string options */
4660 /* flag options */
4662 OPT_mcld,
4663 MASK_CLD),
4666 OPT_mfancy_math_387,
4667 MASK_NO_FANCY_MATH_387),
4670 OPT_mieee_fp,
4671 MASK_IEEE_FP),
4674 OPT_minline_all_stringops,
4675 MASK_INLINE_ALL_STRINGOPS),
4678 OPT_minline_stringops_dynamically,
4679 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4682 OPT_mno_align_stringops,
4683 MASK_NO_ALIGN_STRINGOPS),
4686 OPT_mrecip,
4687 MASK_RECIP),
4689 };
4691 /* If this is a list, recurse to get the options. */
4693 {
4700 enum_opts_set))
4704 }
4707 {
4710 }
4712 /* Handle multiple arguments separated by commas. */
4716 {
4730 {
4734 }
4735 else
4736 {
4739 }
4741 /* Recognize no-xxx. */
4743 {
4747 }
4748 else
4751 /* Find the option. */
4755 {
4763 {
4768 }
4769 }
4771 /* Process the option. */
4773 {
4776 }
4779 {
4785 }
4788 {
4794 else
4796 }
4799 {
4801 {
4804 }
4805 else
4807 }
4810 {
4818 global_dc);
4819 else
4820 {
4823 }
4824 }
4826 else
4828 }
4831 }
4833 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4835 tree
4839 {
4854 /* Process each of the options on the chain. */
4859 /* If the changed options are different from the default, rerun
4860 ix86_option_override_internal, and then save the options away.
4861 The string options are are attribute options, and will be undone
4862 when we copy the save structure. */
4868 {
4869 /* If we are using the default tune= or arch=, undo the string assigned,
4870 and use the default. */
4881 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4886 {
4889 }
4891 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4894 /* Add any builtin functions with the new isa if any. */
4897 /* Save the current options unless we are validating options for
4898 #pragma. */
4905 /* Free up memory allocated to hold the strings */
4908 }
4911 }
4913 /* Hook to validate attribute((target("string"))). */
4915 static bool
4918 tree args,
4920 {
4925 /* attribute((target("default"))) does nothing, beyond
4926 affecting multi-versioning. */
4935 /* Get the optimization options of the current function. */
4941 /* Init func_options. */
4949 /* Initialize func_options to the default before its target options can
4950 be set. */
4963 {
4968 }
4971 }
4973 \f
4974 /* Hook to determine if one function can safely inline another. */
4976 static bool
4978 {
4983 /* If callee has no option attributes, then it is ok to inline. */
4987 /* If caller has no option attributes, but callee does then it is not ok to
4988 inline. */
4992 else
4993 {
4997 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4998 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4999 function. */
5004 /* See if we have the same non-isa options. */
5008 /* See if arch, tune, etc. are the same. */
5021 else
5023 }
5026 }
5028 \f
5029 /* Remember the last target of ix86_set_current_function. */
5032 /* Set target globals to default. */
5034 static void
5036 {
5037 tree old_tree = (ix86_previous_fndecl
5042 {
5050 else
5053 }
5054 }
5056 /* Invalidate ix86_previous_fndecl cache. */
5057 void
5059 {
5062 }
5064 /* Establish appropriate back-end context for processing the function
5065 FNDECL. The argument might be NULL to indicate processing at top
5066 level, outside of any function scope. */
5067 static void
5069 {
5070 /* Only change the context if the function changes. This hook is called
5071 several times in the course of compiling a function, and we don't want to
5072 slow things down too much or call target_reinit when it isn't safe. */
5074 {
5075 tree old_tree = (ix86_previous_fndecl
5079 tree new_tree = (fndecl
5084 ;
5087 {
5092 else
5095 }
5100 }
5101 }
5103 \f
5104 /* Return true if this goes in large data/bss. */
5106 static bool
5108 {
5112 /* Functions are never large data. */
5116 /* Automatic variables are never large data. */
5121 {
5127 }
5128 else
5129 {
5132 /* If this is an incomplete type with size 0, then we can't put it
5133 in data because it might be too big when completed. Also,
5134 int_size_in_bytes returns -1 if size can vary or is larger than
5135 an integer in which case also it is safer to assume that it goes in
5136 large data. */
5139 }
5142 }
5144 /* Switch to the appropriate section for output of DECL.
5145 DECL is either a `VAR_DECL' node or a constant of some sort.
5146 RELOC indicates whether forming the initial value of DECL requires
5147 link-time relocations. */
5152 {
5154 {
5158 {
5192 /* We don't split these for medium model. Place them into
5193 default sections and hope for best. */
5195 }
5197 {
5198 /* We might get called with string constants, but get_named_section
5199 doesn't like them as they are not DECLs. Also, we need to set
5200 flags in that case. */
5204 }
5205 }
5207 }
5209 /* Select a set of attributes for section NAME based on the properties
5210 of DECL and whether or not RELOC indicates that DECL's initializer
5211 might contain runtime relocations. */
5213 static unsigned int ATTRIBUTE_UNUSED
5215 {
5229 }
5231 /* Build up a unique section name, expressed as a
5232 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5233 RELOC indicates whether the initial value of EXP requires
5234 link-time relocations. */
5236 static void ATTRIBUTE_UNUSED
5238 {
5240 {
5242 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5246 {
5270 /* We don't split these for medium model. Place them into
5271 default sections and hope for best. */
5273 }
5275 {
5282 /* If we're using one_only, then there needs to be a .gnu.linkonce
5283 prefix to the section name. */
5290 }
5291 }
5293 }
5295 #ifdef COMMON_ASM_OP
5296 /* This says how to output assembler code to declare an
5297 uninitialized external linkage data object.
5299 For medium model x86-64 we need to use .largecomm opcode for
5300 large objects. */
5301 void
5305 {
5309 else
5314 }
5315 #endif
5317 /* Utility function for targets to use in implementing
5318 ASM_OUTPUT_ALIGNED_BSS. */
5320 void
5323 {
5327 else
5330 #ifdef ASM_DECLARE_OBJECT_NAME
5333 #else
5334 /* Standard thing is just output label for the object. */
5338 }
5339 \f
5340 /* Decide whether we must probe the stack before any space allocation
5341 on this target. It's essentially TARGET_STACK_PROBE except when
5342 -fstack-check causes the stack to be already probed differently. */
5344 bool
5346 {
5347 /* Do not probe the stack twice if static stack checking is enabled. */
5352 }
5353 \f
5354 /* Decide whether we can make a sibling call to a function. DECL is the
5355 declaration of the function being targeted by the call and EXP is the
5356 CALL_EXPR representing the call. */
5358 static bool
5360 {
5364 /* If we are generating position-independent code, we cannot sibcall
5365 optimize any indirect call, or a direct call to a global function,
5366 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5368 && !TARGET_64BIT
5369 && flag_pic
5373 /* If we need to align the outgoing stack, then sibcalling would
5374 unalign the stack, which may break the called function. */
5380 {
5383 }
5384 else
5385 {
5386 /* We're looking at the CALL_EXPR, we need the type of the function. */
5391 }
5393 /* Check that the return value locations are the same. Like
5394 if we are returning floats on the 80387 register stack, we cannot
5395 make a sibcall from a function that doesn't return a float to a
5396 function that does or, conversely, from a function that does return
5397 a float to a function that doesn't; the necessary stack adjustment
5398 would not be executed. This is also the place we notice
5399 differences in the return value ABI. Note that it is ok for one
5400 of the functions to have void return type as long as the return
5401 value of the other is passed in a register. */
5406 {
5409 }
5411 ;
5416 {
5417 /* The SYSV ABI has more call-clobbered registers;
5418 disallow sibcalls from MS to SYSV. */
5422 }
5423 else
5424 {
5425 /* If this call is indirect, we'll need to be able to use a
5426 call-clobbered register for the address of the target function.
5427 Make sure that all such registers are not used for passing
5428 parameters. Note that DLLIMPORT functions are indirect. */
5431 {
5433 {
5434 /* ??? Need to count the actual number of registers to be used,
5435 not the possible number of registers. Fix later. */
5437 }
5438 }
5439 }
5441 /* Otherwise okay. That also includes certain types of indirect calls. */
5443 }
5445 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5446 and "sseregparm" calling convention attributes;
5447 arguments as in struct attribute_spec.handler. */
5449 static tree
5451 tree args,
5454 {
5459 {
5461 name);
5464 }
5466 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5468 {
5469 tree cst;
5472 {
5474 }
5477 {
5479 }
5483 {
5486 name);
5488 }
5490 {
5494 }
5497 }
5500 {
5501 /* Do not warn when emulating the MS ABI. */
5506 name);
5509 }
5511 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5513 {
5515 {
5517 }
5519 {
5521 }
5523 {
5525 }
5527 {
5529 }
5530 }
5532 /* Can combine stdcall with fastcall (redundant), regparm and
5533 sseregparm. */
5535 {
5537 {
5539 }
5541 {
5543 }
5545 {
5547 }
5548 }
5550 /* Can combine cdecl with regparm and sseregparm. */
5552 {
5554 {
5556 }
5558 {
5560 }
5562 {
5564 }
5565 }
5567 {
5570 name);
5572 {
5574 }
5576 {
5578 }
5580 {
5582 }
5583 }
5585 /* Can combine sseregparm with all attributes. */
5588 }
5590 /* The transactional memory builtins are implicitly regparm or fastcall
5591 depending on the ABI. Override the generic do-nothing attribute that
5592 these builtins were declared with, and replace it with one of the two
5593 attributes that we expect elsewhere. */
5595 static tree
5598 {
5599 tree alt;
5601 /* In no case do we want to add the placeholder attribute. */
5604 /* The 64-bit ABI is unchanged for transactional memory. */
5608 /* ??? Is there a better way to validate 32-bit windows? We have
5609 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5612 else
5613 {
5616 }
5620 }
5622 /* This function determines from TYPE the calling-convention. */
5624 unsigned int
5626 {
5629 tree attrs;
5636 {
5646 /* Regparam isn't allowed for thiscall and fastcall. */
5648 {
5653 }
5657 }
5664 || is_stdarg
5670 }
5672 /* Return 0 if the attributes for two types are incompatible, 1 if they
5673 are compatible, and 2 if they are nearly compatible (which causes a
5674 warning to be generated). */
5676 static int
5678 {
5694 }
5695 \f
5696 /* Return the regparm value for a function with the indicated TYPE and DECL.
5697 DECL may be NULL when calling function indirectly
5698 or considering a libcall. */
5700 static int
5702 {
5703 tree attr;
5714 {
5717 {
5720 }
5721 }
5727 /* Use register calling convention for local functions when possible. */
5730 /* Caller and callee must agree on the calling convention, so
5731 checking here just optimize means that with
5732 __attribute__((optimize (...))) caller could use regparm convention
5733 and callee not, or vice versa. Instead look at whether the callee
5734 is optimized or not. */
5737 {
5738 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5741 {
5744 /* Make sure no regparm register is taken by a
5745 fixed register variable. */
5750 /* We don't want to use regparm(3) for nested functions as
5751 these use a static chain pointer in the third argument. */
5755 /* In 32-bit mode save a register for the split stack. */
5759 /* Each fixed register usage increases register pressure,
5760 so less registers should be used for argument passing.
5761 This functionality can be overriden by an explicit
5762 regparm value. */
5765 globals++;
5767 local_regparm
5772 }
5773 }
5776 }
5778 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5779 DFmode (2) arguments in SSE registers for a function with the
5780 indicated TYPE and DECL. DECL may be NULL when calling function
5781 indirectly or considering a libcall. Otherwise return 0. */
5783 static int
5785 {
5788 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5789 by the sseregparm attribute. */
5792 {
5794 {
5796 {
5800 else
5803 }
5805 }
5808 }
5810 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5811 (and DFmode for SSE2) arguments in SSE registers. */
5814 {
5815 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5819 }
5822 }
5824 /* Return true if EAX is live at the start of the function. Used by
5825 ix86_expand_prologue to determine if we need special help before
5826 calling allocate_stack_worker. */
5828 static bool
5830 {
5831 /* Cheat. Don't bother working forward from ix86_function_regparm
5832 to the function type to whether an actual argument is located in
5833 eax. Instead just look at cfg info, which is still close enough
5834 to correct at this point. This gives false positives for broken
5835 functions that might use uninitialized data that happens to be
5836 allocated in eax, but who cares? */
5838 }
5840 static bool
5842 {
5843 tree attr;
5846 {
5852 /* For 32-bit MS-ABI the default is to keep aggregate
5853 return pointer. */
5856 }
5858 }
5860 /* Value is the number of bytes of arguments automatically
5861 popped when returning from a subroutine call.
5862 FUNDECL is the declaration node of the function (as a tree),
5863 FUNTYPE is the data type of the function (as a tree),
5864 or for a library call it is an identifier node for the subroutine name.
5865 SIZE is the number of bytes of arguments passed on the stack.
5867 On the 80386, the RTD insn may be used to pop them if the number
5868 of args is fixed, but if the number is variable then the caller
5869 must pop them all. RTD can't be used for library calls now
5870 because the library is compiled with the Unix compiler.
5871 Use of RTD is a selectable option, since it is incompatible with
5872 standard Unix calling sequences. If the option is not selected,
5873 the caller must always pop the args.
5875 The attribute stdcall is equivalent to RTD on a per module basis. */
5877 static int
5879 {
5882 /* None of the 64-bit ABIs pop arguments. */
5893 /* Lose any fake structure return argument if it is passed on the stack. */
5896 {
5900 }
5903 }
5905 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5907 static bool
5909 {
5910 /* Check operand constraints in case hard registers were propagated
5911 into insn pattern. This check prevents combine pass from
5912 generating insn patterns with invalid hard register operands.
5913 These invalid insns can eventually confuse reload to error out
5914 with a spill failure. See also PRs 46829 and 46843. */
5916 {
5925 {
5933 /* For pre-AVX disallow unaligned loads/stores where the
5934 instructions don't support it. */
5938 {
5942 }
5944 /* A unary operator may be accepted by the predicate, but it
5945 is irrelevant for matching constraints. */
5950 {
5958 }
5965 /* Operand has no constraints, anything is OK. */
5970 {
5975 && operands_match_p
5979 {
5982 }
5983 }
5987 }
5988 }
5991 }
5992 \f
5993 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5995 static unsigned HOST_WIDE_INT
5997 {
6001 }
6002 \f
6003 /* Argument support functions. */
6005 /* Return true when register may be used to pass function parameters. */
6006 bool
6008 {
6013 {
6017 else
6023 }
6029 /* TODO: The function should depend on current function ABI but
6030 builtins.c would need updating then. Therefore we use the
6031 default ABI. */
6033 /* RAX is used as hidden argument to va_arg functions. */
6039 else
6046 }
6048 /* Return if we do not know how to pass TYPE solely in registers. */
6050 static bool
6052 {
6056 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6057 The layout_type routine is crafty and tries to trick us into passing
6058 currently unsupported vector types on the stack by using TImode. */
6061 }
6063 /* It returns the size, in bytes, of the area reserved for arguments passed
6064 in registers for the function represented by fndecl dependent to the used
6065 abi format. */
6066 int
6068 {
6072 else
6077 }
6079 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6080 call abi used. */
6081 enum calling_abi
6083 {
6085 {
6088 {
6091 }
6095 }
6097 }
6099 /* We add this as a workaround in order to use libc_has_function
6100 hook in i386.md. */
6101 bool
6103 {
6105 }
6107 static bool
6109 {
6111 {
6115 else
6117 }
6119 }
6121 static enum calling_abi
6123 {
6127 }
6129 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6130 call abi used. */
6131 enum calling_abi
6133 {
6137 }
6139 /* Write the extra assembler code needed to declare a function properly. */
6141 void
6143 tree decl)
6144 {
6148 {
6154 }
6156 #ifdef SUBTARGET_ASM_UNWIND_INIT
6158 #endif
6162 /* Output magic byte marker, if hot-patch attribute is set. */
6164 {
6166 {
6167 /* leaq [%rsp + 0], %rsp */
6170 }
6171 else
6172 {
6173 /* movl.s %edi, %edi
6174 push %ebp
6175 movl.s %esp, %ebp */
6178 }
6179 }
6180 }
6182 /* regclass.c */
6185 /* Implementation of call abi switching target hook. Specific to FNDECL
6186 the specific call register sets are set. See also
6187 ix86_conditional_register_usage for more details. */
6188 void
6190 {
6193 else
6195 }
6197 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6198 expensive re-initialization of init_regs each time we switch function context
6199 since this is needed only during RTL expansion. */
6200 static void
6202 {
6206 }
6208 /* Return 1 if pseudo register should be created and used to hold
6209 GOT address for PIC code. */
6210 static bool
6212 {
6219 }
6221 /* Initialize large model PIC register. */
6223 static void
6225 {
6227 rtx tmp_reg;
6236 label));
6240 }
6242 /* Create and initialize PIC register if required. */
6243 static void
6245 {
6246 edge entry_edge;
6255 {
6258 else
6260 }
6261 else
6262 {
6263 /* If there is future mcount call in the function it is more profitable
6264 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6273 }
6281 }
6283 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6284 for a call to a function whose data type is FNTYPE.
6285 For a library call, FNTYPE is 0. */
6287 void
6291 tree fndecl,
6293 {
6299 {
6302 }
6303 else
6304 {
6307 }
6311 /* Set up the number of registers to use for passing arguments. */
6314 {
6316 ? X86_64_REGPARM_MAX
6318 }
6320 {
6323 {
6325 ? X86_64_SSE_REGPARM_MAX
6327 }
6328 }
6336 /* Because type might mismatch in between caller and callee, we need to
6337 use actual type of function for local calls.
6338 FIXME: cgraph_analyze can be told to actually record if function uses
6339 va_start so for local functions maybe_vaarg can be made aggressive
6340 helping K&R code.
6341 FIXME: once typesytem is fixed, we won't need this code anymore. */
6354 {
6355 /* If there are variable arguments, then we won't pass anything
6356 in registers in 32-bit mode. */
6358 {
6367 }
6369 /* Use ecx and edx registers if function has fastcall attribute,
6370 else look for regparm information. */
6372 {
6375 {
6378 }
6380 {
6383 }
6384 else
6386 }
6388 /* Set up the number of SSE registers used for passing SFmode
6389 and DFmode arguments. Warn for mismatching ABI. */
6391 }
6392 }
6394 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6395 But in the case of vector types, it is some vector mode.
6397 When we have only some of our vector isa extensions enabled, then there
6398 are some modes for which vector_mode_supported_p is false. For these
6399 modes, the generic vector support in gcc will choose some non-vector mode
6400 in order to implement the type. By computing the natural mode, we'll
6401 select the proper ABI location for the operand and not depend on whatever
6402 the middle-end decides to do with these vector types.
6404 The midde-end can't deal with the vector types > 16 bytes. In this
6405 case, we return the original mode and warn ABI change if CUM isn't
6406 NULL.
6408 If INT_RETURN is true, warn ABI change if the vector mode isn't
6409 available for function return value. */
6411 static machine_mode
6414 {
6418 {
6421 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6423 {
6428 else
6431 /* Get the mode which has this inner mode and number of units. */
6435 {
6437 {
6442 {
6446 }
6448 {
6452 }
6455 }
6457 {
6462 {
6466 }
6468 {
6472 }
6475 }
6478 {
6483 {
6487 }
6489 {
6493 }
6494 }
6496 {
6501 {
6505 }
6507 {
6511 }
6512 }
6514 }
6517 }
6518 }
6521 }
6523 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6524 this may not agree with the mode that the type system has chosen for the
6525 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6526 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6528 static rtx
6531 {
6532 rtx tmp;
6536 else
6537 {
6541 }
6544 }
6546 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6547 of this code is to classify each 8bytes of incoming argument by the register
6548 class and assign registers accordingly. */
6550 /* Return the union class of CLASS1 and CLASS2.
6551 See the x86-64 PS ABI for details. */
6553 static enum x86_64_reg_class
6555 {
6556 /* Rule #1: If both classes are equal, this is the resulting class. */
6560 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6561 the other class. */
6567 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6571 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6579 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6580 MEMORY is used. */
6589 /* Rule #6: Otherwise class SSE is used. */
6591 }
6593 /* Classify the argument of type TYPE and mode MODE.
6594 CLASSES will be filled by the register class used to pass each word
6595 of the operand. The number of words is returned. In case the parameter
6596 should be passed in memory, 0 is returned. As a special case for zero
6597 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6599 BIT_OFFSET is used internally for handling records and specifies offset
6600 of the offset in bits modulo 512 to avoid overflow cases.
6602 See the x86-64 PS ABI for details.
6603 */
6605 static int
6608 {
6609 HOST_WIDE_INT bytes =
6611 int words
6614 /* Variable sized entities are always passed/returned in memory. */
6623 {
6625 tree field;
6628 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6635 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6636 signalize memory class, so handle it as special case. */
6638 {
6641 }
6643 /* Classify each field of record and merge classes. */
6645 {
6647 /* And now merge the fields of structure. */
6649 {
6651 {
6657 /* Bitfields are always classified as integer. Handle them
6658 early, since later code would consider them to be
6659 misaligned integers. */
6661 {
6670 }
6671 else
6672 {
6677 /* Flexible array member is ignored. */
6684 {
6688 {
6691 "the ABI of passing struct with"
6692 " a flexible array member has"
6694 }
6696 }
6698 subclasses,
6708 }
6709 }
6710 }
6714 /* Arrays are handled as small records. */
6715 {
6722 /* The partial classes are now full classes. */
6733 }
6736 /* Unions are similar to RECORD_TYPE but offset is always 0.
6737 */
6739 {
6741 {
6749 bit_offset);
6754 }
6755 }
6760 }
6763 {
6764 /* When size > 16 bytes, if the first one isn't
6765 X86_64_SSE_CLASS or any other ones aren't
6766 X86_64_SSEUP_CLASS, everything should be passed in
6767 memory. */
6774 }
6776 /* Final merger cleanup. */
6778 {
6779 /* If one class is MEMORY, everything should be passed in
6780 memory. */
6784 /* The X86_64_SSEUP_CLASS should be always preceded by
6785 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6789 {
6790 /* The first one should never be X86_64_SSEUP_CLASS. */
6793 }
6795 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6796 everything should be passed in memory. */
6799 {
6802 /* The first one should never be X86_64_X87UP_CLASS. */
6805 {
6808 "the ABI of passing union with long double"
6810 }
6812 }
6813 }
6815 }
6817 /* Compute alignment needed. We align all types to natural boundaries with
6818 exception of XFmode that is aligned to 64bits. */
6820 {
6829 /* Misaligned fields are always returned in memory. */
6832 }
6834 /* for V1xx modes, just use the base mode */
6839 /* Classification of atomic types. */
6841 {
6857 {
6860 /* Analyze last 128 bits only. */
6864 {
6867 }
6869 {
6872 }
6874 {
6878 }
6880 {
6883 }
6884 else
6886 }
6893 /* OImode shouldn't be used directly. */
6900 else
6918 else
6919 {
6923 {
6926 "the ABI of passing structure with complex float"
6928 }
6931 }
6940 /* This modes is larger than 16 bytes. */
6998 else
7002 }
7003 }
7005 /* Examine the argument and return set number of register required in each
7006 class. Return true iff parameter should be passed in memory. */
7008 static bool
7011 {
7022 {
7043 }
7046 }
7048 /* Construct container for the argument used by GCC interface. See
7049 FUNCTION_ARG for the detailed description. */
7051 static rtx
7055 {
7056 /* The following variables hold the static issued_error state. */
7061 machine_mode tmpmode;
7070 rtx ret;
7081 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7082 some less clueful developer tries to use floating-point anyway. */
7084 {
7086 {
7088 {
7091 }
7092 }
7094 {
7097 }
7099 }
7101 /* Likewise, error if the ABI requires us to return values in the
7102 x87 registers and the user specified -mno-80387. */
7108 {
7110 {
7113 }
7115 }
7117 /* First construct simple cases. Avoid SCmode, since we want to use
7118 single register to pass this type. */
7121 {
7136 /* Zero sized array, struct or class. */
7140 }
7179 /* Otherwise figure out the entries of the PARALLEL. */
7181 {
7185 {
7190 /* Merge TImodes on aligned occasions here too. */
7192 tmpmode
7196 else
7198 /* We've requested 24 bytes we
7199 don't have mode for. Use DImode. */
7206 intreg++;
7214 sse_regno++;
7222 sse_regno++;
7227 {
7233 {
7235 i++;
7236 }
7237 else
7262 }
7268 sse_regno++;
7272 }
7273 }
7275 /* Empty aligned struct, union or class. */
7283 }
7285 /* Update the data in CUM to advance over an argument of mode MODE
7286 and data type TYPE. (TYPE is null for libcalls where that information
7287 may not be available.)
7289 Return a number of integer regsiters advanced over. */
7291 static int
7294 HOST_WIDE_INT words)
7295 {
7299 {
7306 /* FALLTHRU */
7318 {
7321 }
7325 /* OImode shouldn't be used directly. */
7334 /* FALLTHRU */
7356 {
7361 {
7364 }
7365 }
7375 {
7380 {
7383 }
7384 }
7386 }
7389 }
7391 static int
7394 {
7397 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7404 {
7410 }
7411 else
7412 {
7417 }
7418 }
7420 static int
7422 HOST_WIDE_INT words)
7423 {
7424 /* Otherwise, this should be passed indirect. */
7429 {
7433 }
7435 }
7437 /* Update the data in CUM to advance over an argument of mode MODE and
7438 data type TYPE. (TYPE is null for libcalls where that information
7439 may not be available.) */
7441 static void
7444 {
7451 else
7460 {
7461 /* If we pass bounds in BT then just update remained bounds count. */
7463 {
7466 }
7468 /* Update remained number of bounds to force. */
7475 }
7477 /* The first arg not going to Bounds Tables resets this counter. */
7479 /* For unnamed args we always pass bounds to avoid bounds mess when
7480 passed and received types do not match. If bounds do not follow
7481 unnamed arg, still pretend required number of bounds were passed. */
7483 {
7486 }
7492 else
7495 /* For stdarg we expect bounds to be passed for each value passed
7496 in register. */
7499 /* For pointers passed in memory we expect bounds passed in Bounds
7500 Table. */
7503 }
7505 /* Define where to put the arguments to a function.
7506 Value is zero to push the argument on the stack,
7507 or a hard register in which to store the argument.
7509 MODE is the argument's machine mode.
7510 TYPE is the data type of the argument (as a tree).
7511 This is null for libcalls where that information may
7512 not be available.
7513 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7514 the preceding args and about the function being called.
7515 NAMED is nonzero if this argument is a named parameter
7516 (otherwise it is an extra parameter matching an ellipsis). */
7518 static rtx
7522 {
7523 /* Avoid the AL settings for the Unix64 ABI. */
7528 {
7535 /* FALLTHRU */
7541 {
7544 /* Fastcall allocates the first two DWORD (SImode) or
7545 smaller arguments to ECX and EDX if it isn't an
7546 aggregate type . */
7548 {
7554 /* ECX not EAX is the first allocated register. */
7557 }
7559 }
7568 /* FALLTHRU */
7570 /* In 32bit, we pass TImode in xmm registers. */
7578 {
7582 }
7587 /* OImode and XImode shouldn't be used directly. */
7603 {
7607 }
7617 {
7621 }
7623 }
7626 }
7628 static rtx
7631 {
7632 /* Handle a hidden AL argument containing number of registers
7633 for varargs x86-64 functions. */
7637 ? X86_64_SSE_REGPARM_MAX
7642 {
7658 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7662 }
7668 }
7670 static rtx
7673 HOST_WIDE_INT bytes)
7674 {
7677 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7678 We use value of -2 to specify that current function call is MSABI. */
7682 /* If we've run out of registers, it goes on the stack. */
7688 /* Only floating point modes are passed in anything but integer regs. */
7690 {
7693 else
7694 {
7697 /* Unnamed floating parameters are passed in both the
7698 SSE and integer registers. */
7704 }
7705 }
7706 /* Handle aggregated types passed in register. */
7708 {
7713 }
7716 }
7718 /* Return where to put the arguments to a function.
7719 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7721 MODE is the argument's machine mode. TYPE is the data type of the
7722 argument. It is null for libcalls where that information may not be
7723 available. CUM gives information about the preceding args and about
7724 the function being called. NAMED is nonzero if this argument is a
7725 named parameter (otherwise it is an extra parameter matching an
7726 ellipsis). */
7728 static rtx
7731 {
7735 rtx arg;
7737 /* All pointer bounds argumntas are handled separately here. */
7740 {
7741 /* Return NULL if bounds are forced to go in Bounds Table. */
7744 /* Return the next available bound reg if any. */
7747 /* Return the next special slot number otherwise. */
7748 else
7752 }
7756 else
7760 /* To simplify the code below, represent vector types with a vector mode
7761 even if MMX/SSE are not active. */
7769 else
7773 }
7775 /* A C expression that indicates when an argument must be passed by
7776 reference. If nonzero for an argument, a copy of that argument is
7777 made in memory and a pointer to the argument is passed instead of
7778 the argument itself. The pointer is passed in whatever way is
7779 appropriate for passing a pointer to that type. */
7781 static bool
7784 {
7787 /* See Windows x64 Software Convention. */
7789 {
7792 {
7793 /* Arrays are passed by reference. */
7798 {
7799 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7800 are passed by reference. */
7802 }
7803 }
7805 /* __m128 is passed by reference. */
7811 }
7812 }
7817 }
7819 /* Return true when TYPE should be 128bit aligned for 32bit argument
7820 passing ABI. XXX: This function is obsolete and is only used for
7821 checking psABI compatibility with previous versions of GCC. */
7823 static bool
7825 {
7837 {
7838 /* Walk the aggregates recursively. */
7840 {
7844 {
7845 tree field;
7847 /* Walk all the structure fields. */
7849 {
7853 }
7855 }
7858 /* Just for use if some languages passes arrays by value. */
7865 }
7866 }
7868 }
7870 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7871 XXX: This function is obsolete and is only used for checking psABI
7872 compatibility with previous versions of GCC. */
7874 static unsigned int
7877 {
7878 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7879 natural boundaries. */
7881 {
7882 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7883 make an exception for SSE modes since these require 128bit
7884 alignment.
7886 The handling here differs from field_alignment. ICC aligns MMX
7887 arguments to 4 byte boundaries, while structure fields are aligned
7888 to 8 byte boundaries. */
7890 {
7893 }
7894 else
7895 {
7898 }
7899 }
7903 }
7905 /* Return true when TYPE should be 128bit aligned for 32bit argument
7906 passing ABI. */
7908 static bool
7910 {
7920 {
7921 /* Walk the aggregates recursively. */
7923 {
7927 {
7928 tree field;
7930 /* Walk all the structure fields. */
7932 field;
7934 {
7938 }
7940 }
7943 /* Just for use if some languages passes arrays by value. */
7950 }
7951 }
7952 else
7956 }
7958 /* Gives the alignment boundary, in bits, of an argument with the
7959 specified mode and type. */
7961 static unsigned int
7963 {
7966 {
7967 /* Since the main variant type is used for call, we convert it to
7968 the main variant type. */
7971 }
7972 else
7976 else
7977 {
7982 {
7983 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7985 {
7988 }
7994 }
7997 && !warned
7999 saved_align))
8000 {
8003 "The ABI for passing parameters with %d-byte"
8006 }
8007 }
8010 }
8012 /* Return true if N is a possible register number of function value. */
8014 static bool
8016 {
8018 {
8030 /* Complex values are returned in %st(0)/%st(1) pair. */
8033 /* TODO: The function should depend on current function ABI but
8034 builtins.c would need updating then. Therefore we use the
8035 default ABI. */
8040 /* Complex values are returned in %xmm0/%xmm1 pair. */
8049 }
8052 }
8054 /* Define how to find the value returned by a function.
8055 VALTYPE is the data type of the value (as a tree).
8056 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8057 otherwise, FUNC is 0. */
8059 static rtx
8062 {
8065 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8066 we normally prevent this case when mmx is not available. However
8067 some ABIs may require the result to be returned like DImode. */
8071 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8072 we prevent this case when sse is not available. However some ABIs
8073 may require the result to be returned like integer TImode. */
8078 /* 32-byte vector modes in %ymm0. */
8082 /* 64-byte vector modes in %zmm0. */
8086 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8089 else
8090 /* Most things go in %eax. */
8093 /* Override FP return register with %xmm0 for local functions when
8094 SSE math is enabled or for functions with sseregparm attribute. */
8096 {
8101 }
8103 /* OImode shouldn't be used directly. */
8107 }
8109 static rtx
8111 const_tree valtype)
8112 {
8113 rtx ret;
8115 /* Handle libcalls, which don't provide a type node. */
8117 {
8121 {
8140 }
8143 }
8145 {
8146 /* Pointers are always returned in word_mode. */
8148 }
8154 /* For zero sized structures, construct_container returns NULL, but we
8155 need to keep rest of compiler happy by returning meaningful value. */
8160 }
8162 static rtx
8164 const_tree valtype)
8165 {
8169 {
8171 {
8190 }
8191 }
8193 }
8195 static rtx
8198 {
8213 else
8215 }
8217 static rtx
8219 {
8225 }
8227 /* Return an RTX representing a place where a function returns
8228 or recieves pointer bounds or NULL if no bounds are returned.
8230 VALTYPE is a data type of a value returned by the function.
8232 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8233 or FUNCTION_TYPE of the function.
8235 If OUTGOING is false, return a place in which the caller will
8236 see the return value. Otherwise, return a place where a
8237 function returns a value. */
8239 static rtx
8241 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8243 {
8249 {
8250 bitmap slots;
8252 bitmap_iterator bi;
8260 {
8265 }
8271 }
8272 else
8276 }
8278 /* Pointer function arguments and return values are promoted to
8279 word_mode. */
8281 static machine_mode
8285 {
8287 {
8290 }
8292 for_return);
8293 }
8295 /* Return true if a structure, union or array with MODE containing FIELD
8296 should be accessed using BLKmode. */
8298 static bool
8300 {
8301 /* Union with XFmode must be in BLKmode. */
8305 }
8307 rtx
8309 {
8311 }
8313 /* Return true iff type is returned in memory. */
8315 static bool
8317 {
8318 #ifdef SUBTARGET_RETURN_IN_MEMORY
8320 #else
8322 HOST_WIDE_INT size;
8328 {
8330 {
8333 /* __m128 is returned in xmm0. */
8342 /* Otherwise, the size must be exactly in [1248]. */
8344 }
8345 else
8346 {
8351 }
8352 }
8353 else
8354 {
8364 {
8365 /* User-created vectors small enough to fit in EAX. */
8369 /* Unless ABI prescibes otherwise,
8370 MMX/3dNow values are returned in MM0 if available. */
8375 /* SSE values are returned in XMM0 if available. */
8379 /* AVX values are returned in YMM0 if available. */
8383 /* AVX512F values are returned in ZMM0 if available. */
8386 }
8394 /* OImode shouldn't be used directly. */
8398 }
8399 #endif
8400 }
8402 \f
8403 /* Create the va_list data type. */
8405 /* Returns the calling convention specific va_list date type.
8406 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8408 static tree
8410 {
8413 /* For i386 we use plain pointer to argument area. */
8423 unsigned_type_node);
8426 unsigned_type_node);
8429 ptr_type_node);
8432 ptr_type_node);
8451 /* The correct type is an array type of one element. */
8453 }
8455 /* Setup the builtin va_list data type and for 64-bit the additional
8456 calling convention specific va_list data types. */
8458 static tree
8460 {
8463 /* Initialize abi specific va_list builtin types. */
8465 {
8466 tree t;
8468 {
8473 }
8474 else
8475 {
8480 }
8482 {
8487 }
8488 else
8489 {
8494 }
8495 }
8498 }
8500 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8502 static void
8504 {
8506 alias_set_type set;
8509 /* GPR size of varargs save area. */
8512 else
8515 /* FPR size of varargs save area. We don't need it if we don't pass
8516 anything in SSE registers. */
8519 else
8533 {
8541 }
8544 {
8545 machine_mode smode;
8547 rtx test;
8549 /* Now emit code to save SSE registers. The AX parameter contains number
8550 of SSE parameter registers used to call this function, though all we
8551 actually check here is the zero/non-zero status. */
8556 label));
8558 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8559 we used movdqa (i.e. TImode) instead? Perhaps even better would
8560 be if we could determine the real mode of the data, via a hook
8561 into pass_stdarg. Ignore all that for now. */
8571 {
8580 }
8583 }
8584 }
8586 static void
8588 {
8592 /* Reset to zero, as there might be a sysv vaarg used
8593 before. */
8598 {
8609 }
8610 }
8612 static void
8615 {
8617 CUMULATIVE_ARGS next_cum;
8618 tree fntype;
8620 /* This argument doesn't appear to be used anymore. Which is good,
8621 because the old code here didn't suppress rtl generation. */
8629 /* For varargs, we do not want to skip the dummy va_dcl argument.
8630 For stdargs, we do want to skip the last named argument. */
8638 else
8640 }
8642 static void
8645 tree type,
8648 {
8650 CUMULATIVE_ARGS next_cum;
8651 tree fntype;
8652 rtx save_area;
8657 /* Do nothing if we use plain pointer to argument area. */
8663 /* For varargs, we do not want to skip the dummy va_dcl argument.
8664 For stdargs, we do want to skip the last named argument. */
8678 {
8683 rtx bounds;
8687 else
8688 {
8689 rtx ldx_addr =
8696 }
8702 bnd_reg++;
8703 }
8704 }
8707 /* Checks if TYPE is of kind va_list char *. */
8709 static bool
8711 {
8712 tree canonic;
8714 /* For 32-bit it is always true. */
8720 }
8722 /* Implement va_start. */
8724 static void
8726 {
8730 tree type;
8731 rtx ovf_rtx;
8735 {
8738 /* When we are splitting the stack, we can't refer to the stack
8739 arguments using internal_arg_pointer, because they may be on
8740 the old stack. The split stack prologue will arrange to
8741 leave a pointer to the old stack arguments in a scratch
8742 register, which we here copy to a pseudo-register. The split
8743 stack prologue can't set the pseudo-register directly because
8744 it (the prologue) runs before any registers have been saved. */
8748 {
8749 rtx reg;
8763 }
8764 }
8766 /* Only 64bit target needs something special. */
8768 {
8771 else
8772 {
8782 /* Store zero bounds for va_list. */
8786 next));
8788 }
8790 }
8799 /* The following should be folded into the MEM_REF offset. */
8809 /* Count number of gp and fp argument registers used. */
8815 {
8821 }
8824 {
8830 }
8832 /* Find the overflow area. */
8836 else
8842 /* Store zero bounds for overflow area pointer. */
8851 {
8852 /* Find the register save area.
8853 Prologue of the function save it right above stack frame. */
8859 /* Store zero bounds for save area pointer. */
8866 }
8867 }
8869 /* Implement va_arg. */
8871 static tree
8874 {
8881 rtx container;
8883 tree ptrtype;
8884 machine_mode nat_mode;
8887 /* Only 64bit target needs something special. */
8911 {
8924 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8926 {
8929 }
8937 }
8939 /* Pull the value out of the saved registers. */
8944 {
8958 /* In case we are passing structure, verify that it is consecutive block
8959 on the register save area. If not we need to do moves. */
8961 {
8962 /* Verify that all registers are strictly consecutive */
8964 {
8968 {
8973 }
8974 }
8975 else
8976 {
8980 {
8985 }
8986 }
8987 }
8989 {
8992 }
8993 else
8994 {
8997 }
8999 /* First ensure that we fit completely in registers. */
9001 {
9008 }
9010 {
9018 }
9020 /* Compute index to start of area used for integer regs. */
9022 {
9023 /* int_addr = gpr + sav; */
9026 }
9028 {
9029 /* sse_addr = fpr + sav; */
9032 }
9034 {
9038 /* addr = &temp; */
9043 {
9047 tree piece_type;
9048 tree addr_type;
9049 tree daddr_type;
9058 {
9063 }
9067 else
9074 {
9077 }
9078 else
9079 {
9082 }
9089 {
9094 }
9095 else
9096 {
9097 tree copy
9102 }
9104 }
9105 }
9108 {
9112 }
9115 {
9119 }
9124 }
9126 /* ... otherwise out of the overflow area. */
9128 /* When we align parameter on stack for caller, if the parameter
9129 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9130 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9131 here with caller. */
9136 /* Care for on-stack alignment if needed. */
9139 else
9140 {
9145 }
9162 }
9163 \f
9164 /* Return true if OPNUM's MEM should be matched
9165 in movabs* patterns. */
9167 bool
9169 {
9181 }
9182 \f
9183 /* Initialize the table of extra 80387 mathematical constants. */
9185 static void
9187 {
9189 {
9195 };
9199 {
9201 /* Ensure each constant is rounded to XFmode precision. */
9204 }
9207 }
9209 /* Return non-zero if the constant is something that
9210 can be loaded with a special instruction. */
9212 int
9214 {
9217 REAL_VALUE_TYPE r;
9229 /* For XFmode constants, try to find a special 80387 instruction when
9230 optimizing for size or on those CPUs that benefit from them. */
9233 {
9242 }
9244 /* Load of the constant -0.0 or -1.0 will be split as
9245 fldz;fchs or fld1;fchs sequence. */
9252 }
9254 /* Return the opcode of the special instruction to be used to load
9255 the constant X. */
9259 {
9261 {
9281 }
9282 }
9284 /* Return the CONST_DOUBLE representing the 80387 constant that is
9285 loaded by the specified special instruction. The argument IDX
9286 matches the return value from standard_80387_constant_p. */
9288 rtx
9290 {
9297 {
9308 }
9311 XFmode);
9312 }
9314 /* Return 1 if X is all 0s and 2 if x is all 1s
9315 in supported SSE/AVX vector mode. */
9317 int
9319 {
9326 {
9347 }
9350 }
9352 /* Return the opcode of the special instruction to be used to load
9353 the constant X. */
9357 {
9359 {
9362 {
9389 }
9399 else
9404 }
9406 }
9408 /* Returns true if OP contains a symbol reference */
9410 bool
9412 {
9421 {
9423 {
9429 }
9433 }
9436 }
9438 /* Return true if it is appropriate to emit `ret' instructions in the
9439 body of a function. Do this only if the epilogue is simple, needing a
9440 couple of insns. Prior to reloading, we can't tell how many registers
9441 must be saved, so return false then. Return false if there is no frame
9442 marker to de-allocate. */
9444 bool
9446 {
9452 /* Don't allow more than 32k pop, since that's all we can do
9453 with one instruction. */
9460 }
9461 \f
9462 /* Value should be nonzero if functions must have frame pointers.
9463 Zero means the frame pointer need not be set up (and parms may
9464 be accessed via the stack pointer) in functions that seem suitable. */
9466 static bool
9468 {
9469 /* If we accessed previous frames, then the generated code expects
9470 to be able to access the saved ebp value in our frame. */
9474 /* Several x86 os'es need a frame pointer for other reasons,
9475 usually pertaining to setjmp. */
9479 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9483 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9484 allocation is 4GB. */
9488 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9489 turns off the frame pointer by default. Turn it back on now if
9490 we've not got a leaf function. */
9500 }
9502 /* Record that the current function accesses previous call frames. */
9504 void
9506 {
9508 }
9509 \f
9510 #ifndef USE_HIDDEN_LINKONCE
9511 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9512 # define USE_HIDDEN_LINKONCE 1
9513 # else
9514 # define USE_HIDDEN_LINKONCE 0
9515 # endif
9516 #endif
9520 /* Fills in the label name that should be used for a pc thunk for
9521 the given register. */
9523 static void
9525 {
9530 else
9532 }
9535 /* This function generates code for -fpic that loads %ebx with
9536 the return address of the caller and then returns. */
9538 static void
9540 {
9545 {
9547 tree decl;
9563 #if TARGET_MACHO
9565 {
9574 }
9575 else
9576 #endif
9578 {
9589 }
9590 else
9591 {
9594 }
9600 /* Make sure unwind info is emitted for the thunk if needed. */
9603 /* Pad stack IP move with 4 instructions (two NOPs count
9604 as one instruction). */
9606 {
9611 }
9622 }
9626 }
9628 /* Emit code for the SET_GOT patterns. */
9632 {
9638 {
9639 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9644 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9645 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9646 an unadorned address. */
9651 }
9656 {
9658 /* We don't need a pic base, we're not producing pic. */
9665 }
9666 else
9667 {
9676 #if TARGET_MACHO
9677 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9678 This is what will be referenced by the Mach-O PIC subsystem. */
9682 /* When we are restoring the pic base at the site of a nonlocal label,
9683 and we decided to emit the pic base above, we will still output a
9684 local label used for calculating the correction offset (even though
9685 the offset will be 0 in that case). */
9689 #endif
9690 }
9696 }
9698 /* Generate an "push" pattern for input ARG. */
9700 static rtx
9702 {
9715 stack_pointer_rtx)),
9716 arg);
9717 }
9719 /* Generate an "pop" pattern for input ARG. */
9721 static rtx
9723 {
9728 arg,
9731 stack_pointer_rtx)));
9732 }
9734 /* Return >= 0 if there is an unused call-clobbered register available
9735 for the entire function. */
9737 static unsigned int
9739 {
9746 {
9748 /* Can't use the same register for both PIC and DRAP. */
9751 else
9756 }
9759 }
9761 /* Return TRUE if we need to save REGNO. */
9763 static bool
9765 {
9768 {
9770 {
9771 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
9772 _mcount in prologue. */
9775 }
9782 }
9785 {
9788 {
9794 }
9795 }
9806 }
9808 /* Return number of saved general prupose registers. */
9810 static int
9812 {
9818 nregs ++;
9820 }
9822 /* Return number of saved SSE registrers. */
9824 static int
9826 {
9834 nregs ++;
9836 }
9838 /* Given FROM and TO register numbers, say whether this elimination is
9839 allowed. If stack alignment is needed, we can only replace argument
9840 pointer with hard frame pointer, or replace frame pointer with stack
9841 pointer. Otherwise, frame pointer elimination is automatically
9842 handled and all other eliminations are valid. */
9844 static bool
9846 {
9852 else
9854 }
9856 /* Return the offset between two registers, one to be eliminated, and the other
9857 its replacement, at the start of a routine. */
9859 HOST_WIDE_INT
9861 {
9870 else
9871 {
9879 }
9880 }
9882 /* In a dynamically-aligned function, we can't know the offset from
9883 stack pointer to frame pointer, so we must ensure that setjmp
9884 eliminates fp against the hard fp (%ebp) rather than trying to
9885 index from %esp up to the top of the frame across a gap that is
9886 of unknown (at compile-time) size. */
9887 static rtx
9889 {
9891 }
9893 /* When using -fsplit-stack, the allocation routines set a field in
9894 the TCB to the bottom of the stack plus this much space, measured
9895 in bytes. */
9897 #define SPLIT_STACK_AVAILABLE 256
9899 /* Fill structure ix86_frame about frame of currently computed function. */
9901 static void
9903 {
9905 HOST_WIDE_INT offset;
9908 HOST_WIDE_INT to_allocate;
9913 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9914 function prologues and leaf. */
9918 {
9921 }
9922 /* preferred_stack_boundary is never updated for call
9923 expanded from tls descriptor. Update it here. We don't update it in
9924 expand stage because according to the comments before
9925 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
9926 away. */
9929 {
9933 }
9942 /* For SEH we have to limit the amount of code movement into the prologue.
9943 At present we do this via a BLOCKAGE, at which point there's very little
9944 scheduling that can be done, which means that there's very little point
9945 in doing anything except PUSHs. */
9949 /* During reload iteration the amount of registers saved can change.
9950 Recompute the value as needed. Do not recompute when amount of registers
9951 didn't change as reload does multiple calls to the function and does not
9952 expect the decision to change within single iteration. */
9955 {
9961 /* The fast prologue uses move instead of push to save registers. This
9962 is significantly longer, but also executes faster as modern hardware
9963 can execute the moves in parallel, but can't do that for push/pop.
9965 Be careful about choosing what prologue to emit: When function takes
9966 many instructions to execute we may use slow version as well as in
9967 case function is known to be outside hot spot (this is known with
9968 feedback only). Weight the size of function by number of registers
9969 to save as it is cheap to use one or two push instructions but very
9970 slow to use many of them. */
9974 || (flag_branch_probabilities
9977 else
9980 }
9982 frame->save_regs_using_mov
9984 /* If static stack checking is enabled and done with probes,
9985 the registers need to be saved before allocating the frame. */
9988 /* Skip return address. */
9991 /* Skip pushed static chain. */
9995 /* Skip saved base pointer. */
10000 /* The traditional frame pointer location is at the top of the frame. */
10003 /* Register save area */
10007 /* On SEH target, registers are pushed just before the frame pointer
10008 location. */
10012 /* Align and set SSE register save area. */
10014 {
10015 /* The only ABI that has saved SSE registers (Win64) also has a
10016 16-byte aligned default stack, and thus we don't need to be
10017 within the re-aligned local stack frame to save them. */
10021 }
10024 /* The re-aligned stack starts here. Values before this point are not
10025 directly comparable with values below this point. In order to make
10026 sure that no value happens to be the same before and after, force
10027 the alignment computation below to add a non-zero value. */
10031 /* Va-arg area */
10035 /* Align start of frame for local function. */
10044 /* Frame pointer points here. */
10049 /* Add outgoing arguments area. Can be skipped if we eliminated
10050 all the function calls as dead code.
10051 Skipping is however impossible when function calls alloca. Alloca
10052 expander assumes that last crtl->outgoing_args_size
10053 of stack frame are unused. */
10057 {
10060 }
10061 else
10064 /* Align stack boundary. Only needed if we're calling another function
10065 or using alloca. */
10070 /* We've reached end of stack frame. */
10073 /* Size prologue needs to allocate. */
10084 {
10090 }
10091 else
10095 /* The SEH frame pointer location is near the bottom of the frame.
10096 This is enforced by the fact that the difference between the
10097 stack pointer and the frame pointer is limited to 240 bytes in
10098 the unwind data structure. */
10100 {
10101 HOST_WIDE_INT diff;
10103 /* If we can leave the frame pointer where it is, do so. Also, returns
10104 the establisher frame for __builtin_frame_address (0). */
10109 {
10110 /* Ideally we'd determine what portion of the local stack frame
10111 (within the constraint of the lowest 240) is most heavily used.
10112 But without that complication, simply bias the frame pointer
10113 by 128 bytes so as to maximize the amount of the local stack
10114 frame that is addressable with 8-bit offsets. */
10116 }
10117 }
10118 }
10120 /* This is semi-inlined memory_address_length, but simplified
10121 since we know that we're always dealing with reg+offset, and
10122 to avoid having to create and discard all that rtl. */
10126 {
10130 {
10131 /* EBP and R13 cannot be encoded without an offset. */
10133 }
10137 /* ESP and R12 must be encoded with a SIB byte. */
10139 len++;
10142 }
10144 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10145 The valid base registers are taken from CFUN->MACHINE->FS. */
10147 static rtx
10149 {
10155 {
10156 /* Choose the base register most likely to allow the most scheduling
10157 opportunities. Generally FP is valid throughout the function,
10158 while DRAP must be reloaded within the epilogue. But choose either
10159 over the SP due to increased encoding size. */
10162 {
10165 }
10167 {
10170 }
10172 {
10175 }
10176 }
10177 else
10178 {
10179 HOST_WIDE_INT toffset;
10182 /* Choose the base register with the smallest address encoding.
10183 With a tie, choose FP > DRAP > SP. */
10185 {
10189 }
10191 {
10195 {
10199 }
10200 }
10202 {
10206 {
10210 }
10211 }
10212 }
10216 }
10218 /* Emit code to save registers in the prologue. */
10220 static void
10222 {
10224 rtx insn;
10228 {
10231 }
10232 }
10234 /* Emit a single register save at CFA - CFA_OFFSET. */
10236 static void
10238 HOST_WIDE_INT cfa_offset)
10239 {
10247 /* For SSE saves, we need to indicate the 128-bit alignment. */
10258 /* When saving registers into a re-aligned local stack frame, avoid
10259 any tricky guessing by dwarf2out. */
10261 {
10265 {
10266 /* A bit of a hack. We force the DRAP register to be saved in
10267 the re-aligned stack frame, which provides us with a copy
10268 of the CFA that will last past the prologue. Install it. */
10274 }
10275 else
10276 {
10277 /* The frame pointer is a stable reference within the
10278 aligned frame. Use it. */
10285 }
10286 }
10288 /* The memory may not be relative to the current CFA register,
10289 which means that we may need to generate a new pattern for
10290 use by the unwind info. */
10292 {
10297 }
10298 }
10300 /* Emit code to save registers using MOV insns.
10301 First register is stored at CFA - CFA_OFFSET. */
10302 static void
10304 {
10309 {
10312 }
10313 }
10315 /* Emit code to save SSE registers using MOV insns.
10316 First register is stored at CFA - CFA_OFFSET. */
10317 static void
10319 {
10324 {
10327 }
10328 }
10332 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10333 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10334 Don't add the note if the previously saved value will be left untouched
10335 within stack red-zone till return, as unwinders can find the same value
10336 in the register and on the stack. */
10338 static void
10340 {
10346 {
10349 }
10350 else
10351 queued_cfa_restores
10353 }
10355 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10357 static void
10359 {
10360 rtx last;
10364 ;
10369 }
10371 /* Expand prologue or epilogue stack adjustment.
10372 The pattern exist to put a dependency on all ebp-based memory accesses.
10373 STYLE should be negative if instructions should be marked as frame related,
10374 zero if %r11 register is live and cannot be freely used and positive
10375 otherwise. */
10377 static void
10380 {
10382 rtx insn;
10389 else
10390 {
10391 rtx tmp;
10392 /* r11 is used by indirect sibcall return as well, set before the
10393 epilogue and used after the epilogue. */
10396 else
10397 {
10401 }
10407 }
10414 {
10415 rtx r;
10425 }
10427 {
10430 {
10434 }
10435 }
10438 {
10443 {
10446 }
10448 {
10451 }
10452 else
10453 {
10454 /* Else there are two possibilities: SP itself, which we set
10455 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10456 taken care of this by hand along the eh_return path. */
10459 }
10463 }
10464 }
10466 /* Find an available register to be used as dynamic realign argument
10467 pointer regsiter. Such a register will be written in prologue and
10468 used in begin of body, so it must not be
10469 1. parameter passing register.
10470 2. GOT pointer.
10471 We reuse static-chain register if it is available. Otherwise, we
10472 use DI for i386 and R13 for x86-64. We chose R13 since it has
10473 shorter encoding.
10475 Return: the regno of chosen register. */
10477 static unsigned int
10479 {
10483 {
10484 /* Use R13 for nested function or function need static chain.
10485 Since function with tail call may use any caller-saved
10486 registers in epilogue, DRAP must not use caller-saved
10487 register in such case. */
10492 }
10493 else
10494 {
10495 /* Use DI for nested function or function need static chain.
10496 Since function with tail call may use any caller-saved
10497 registers in epilogue, DRAP must not use caller-saved
10498 register in such case. */
10502 /* Reuse static chain register if it isn't used for parameter
10503 passing. */
10505 {
10509 }
10511 }
10512 }
10514 /* Return minimum incoming stack alignment. */
10516 static unsigned int
10518 {
10521 /* Prefer the one specified at command line. */
10524 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10525 if -mstackrealign is used, it isn't used for sibcall check and
10526 estimated stack alignment is 128bit. */
10528 && !TARGET_64BIT
10529 && ix86_force_align_arg_pointer
10532 else
10535 /* Incoming stack alignment can be changed on individual functions
10536 via force_align_arg_pointer attribute. We use the smallest
10537 incoming stack boundary. */
10543 /* The incoming stack frame has to be aligned at least at
10544 parm_stack_boundary. */
10548 /* Stack at entrance of main is aligned by runtime. We use the
10549 smallest incoming stack boundary. */
10557 }
10559 /* Update incoming stack boundary and estimated stack alignment. */
10561 static void
10563 {
10564 ix86_incoming_stack_boundary
10567 /* x86_64 vararg needs 16byte stack alignment for register save
10568 area. */
10573 }
10575 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10576 needed or an rtx for DRAP otherwise. */
10578 static rtx
10580 {
10585 {
10586 /* Assign DRAP to vDRAP and returns vDRAP */
10588 rtx drap_vreg;
10589 rtx arg_ptr;
10602 {
10605 }
10607 }
10608 else
10610 }
10612 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10614 static rtx
10616 {
10618 }
10621 rtx reg;
10623 };
10625 /* Return a short-lived scratch register for use on function entry.
10626 In 32-bit mode, it is valid only after the registers are saved
10627 in the prologue. This register must be released by means of
10628 release_scratch_register_on_entry once it is dead. */
10630 static void
10632 {
10638 {
10639 /* We always use R11 in 64-bit mode. */
10641 }
10642 else
10643 {
10645 bool fastcall_p
10647 bool thiscall_p
10651 int drap_regno
10654 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10655 for the static chain register. */
10659 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10660 for the static chain register. */
10665 /* ecx is the static chain register. */
10667 && !static_chain_p
10672 /* esi is the static chain register. */
10678 else
10679 {
10682 }
10683 }
10687 {
10690 }
10691 }
10693 /* Release a scratch register obtained from the preceding function. */
10695 static void
10697 {
10699 {
10703 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10709 }
10710 }
10712 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10714 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10716 static void
10718 {
10719 /* We skip the probe for the first interval + a small dope of 4 words and
10720 probe that many bytes past the specified size to maintain a protection
10721 area at the botton of the stack. */
10725 /* See if we have a constant small number of probes to generate. If so,
10726 that's the easy case. The run-time loop is made up of 11 insns in the
10727 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10728 for n # of intervals. */
10730 {
10734 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10735 values of N from 1 until it exceeds SIZE. If only one probe is
10736 needed, this will not generate any code. Then adjust and probe
10737 to PROBE_INTERVAL + SIZE. */
10739 {
10741 {
10744 }
10745 else
10752 }
10756 else
10764 /* Adjust back to account for the additional first interval. */
10768 }
10770 /* Otherwise, do the same as above, but in a loop. Note that we must be
10771 extra careful with variables wrapping around because we might be at
10772 the very top (or the very bottom) of the address space and we have
10773 to be able to handle this case properly; in particular, we use an
10774 equality test for the loop condition. */
10775 else
10776 {
10777 HOST_WIDE_INT rounded_size;
10783 /* Step 1: round SIZE to the previous multiple of the interval. */
10788 /* Step 2: compute initial and final value of the loop counter. */
10790 /* SP = SP_0 + PROBE_INTERVAL. */
10795 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10799 stack_pointer_rtx)));
10802 /* Step 3: the loop
10804 while (SP != LAST_ADDR)
10805 {
10806 SP = SP + PROBE_INTERVAL
10807 probe at SP
10808 }
10810 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10811 values of N from 1 until it is equal to ROUNDED_SIZE. */
10816 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10817 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10820 {
10825 }
10827 /* Adjust back to account for the additional first interval. */
10833 }
10837 /* Even if the stack pointer isn't the CFA register, we need to correctly
10838 describe the adjustments made to it, in particular differentiate the
10839 frame-related ones from the frame-unrelated ones. */
10841 {
10854 }
10856 /* Make sure nothing is scheduled before we are done. */
10858 }
10860 /* Adjust the stack pointer up to REG while probing it. */
10864 {
10874 /* Jump to END_LAB if SP == LAST_ADDR. */
10882 /* SP = SP + PROBE_INTERVAL. */
10886 /* Probe at SP. */
10897 }
10899 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10900 inclusive. These are offsets from the current stack pointer. */
10902 static void
10904 {
10905 /* See if we have a constant small number of probes to generate. If so,
10906 that's the easy case. The run-time loop is made up of 7 insns in the
10907 generic case while the compile-time loop is made up of n insns for n #
10908 of intervals. */
10910 {
10911 HOST_WIDE_INT i;
10913 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10914 it exceeds SIZE. If only one probe is needed, this will not
10915 generate any code. Then probe at FIRST + SIZE. */
10922 }
10924 /* Otherwise, do the same as above, but in a loop. Note that we must be
10925 extra careful with variables wrapping around because we might be at
10926 the very top (or the very bottom) of the address space and we have
10927 to be able to handle this case properly; in particular, we use an
10928 equality test for the loop condition. */
10929 else
10930 {
10937 /* Step 1: round SIZE to the previous multiple of the interval. */
10942 /* Step 2: compute initial and final value of the loop counter. */
10944 /* TEST_OFFSET = FIRST. */
10947 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10951 /* Step 3: the loop
10953 while (TEST_ADDR != LAST_ADDR)
10954 {
10955 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10956 probe at TEST_ADDR
10957 }
10959 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10960 until it is equal to ROUNDED_SIZE. */
10965 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10966 that SIZE is equal to ROUNDED_SIZE. */
10971 stack_pointer_rtx,
10976 }
10978 /* Make sure nothing is scheduled before we are done. */
10980 }
10982 /* Probe a range of stack addresses from REG to END, inclusive. These are
10983 offsets from the current stack pointer. */
10987 {
10997 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11005 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11009 /* Probe at TEST_ADDR. */
11022 }
11024 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11025 to be generated in correct form. */
11026 static void
11028 {
11029 /* Check if stack realign is really needed after reload, and
11030 stores result in cfun */
11031 unsigned int incoming_stack_boundary
11040 {
11041 /* After stack_realign_needed is finalized, we can't no longer
11042 change it. */
11045 }
11047 /* If the only reason for frame_pointer_needed is that we conservatively
11048 assumed stack realignment might be needed, but in the end nothing that
11049 needed the stack alignment had been spilled, clear frame_pointer_needed
11050 and say we don't need stack realignment. */
11052 && frame_pointer_needed
11054 && flag_omit_frame_pointer
11056 && !ix86_current_function_calls_tls_descriptor
11065 {
11067 basic_block bb;
11074 HARD_FRAME_POINTER_REGNUM);
11076 {
11081 set_up_by_prologue))
11082 {
11086 }
11087 }
11089 /* If drap has been set, but it actually isn't live at the start
11090 of the function, there is no reason to set it up. */
11092 {
11095 {
11098 }
11099 }
11100 else
11115 }
11119 }
11121 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11123 static void
11125 {
11131 {
11134 {
11140 }
11141 }
11142 }
11144 /* Expand the prologue into a bunch of separate insns. */
11146 void
11148 {
11152 HOST_WIDE_INT allocate;
11158 /* DRAP should not coexist with stack_realign_fp */
11163 /* Initialize CFA state for before the prologue. */
11167 /* Track SP offset to the CFA. We continue tracking this after we've
11168 swapped the CFA register away from SP. In the case of re-alignment
11169 this is fudged; we're interested to offsets within the local frame. */
11176 {
11177 /* We should have already generated an error for any use of
11178 ms_hook on a nested function. */
11181 /* Check if profiling is active and we shall use profiling before
11182 prologue variant. If so sorry. */
11187 /* In ix86_asm_output_function_label we emitted:
11188 8b ff movl.s %edi,%edi
11189 55 push %ebp
11190 8b ec movl.s %esp,%ebp
11192 This matches the hookable function prologue in Win32 API
11193 functions in Microsoft Windows XP Service Pack 2 and newer.
11194 Wine uses this to enable Windows apps to hook the Win32 API
11195 functions provided by Wine.
11197 What that means is that we've already set up the frame pointer. */
11201 {
11204 /* We've decided to use the frame pointer already set up.
11205 Describe this to the unwinder by pretending that both
11206 push and mov insns happen right here.
11208 Putting the unwind info here at the end of the ms_hook
11209 is done so that we can make absolutely certain we get
11210 the required byte sequence at the start of the function,
11211 rather than relying on an assembler that can produce
11212 the exact encoding required.
11214 However it does mean (in the unpatched case) that we have
11215 a 1 insn window where the asynchronous unwind info is
11216 incorrect. However, if we placed the unwind info at
11217 its correct location we would have incorrect unwind info
11218 in the patched case. Which is probably all moot since
11219 I don't expect Wine generates dwarf2 unwind info for the
11220 system libraries that use this feature. */
11226 stack_pointer_rtx);
11234 /* Note that gen_push incremented m->fs.cfa_offset, even
11235 though we didn't emit the push insn here. */
11239 }
11240 else
11241 {
11242 /* The frame pointer is not needed so pop %ebp again.
11243 This leaves us with a pristine state. */
11245 }
11246 }
11248 /* The first insn of a function that accepts its static chain on the
11249 stack is to push the register that would be filled in by a direct
11250 call. This insn will be skipped by the trampoline. */
11252 {
11256 /* We don't want to interpret this push insn as a register save,
11257 only as a stack adjustment. The real copy of the register as
11258 a save will be done later, if needed. */
11263 }
11265 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11266 of DRAP is needed and stack realignment is really needed after reload */
11268 {
11271 /* Only need to push parameter pointer reg if it is caller saved. */
11273 {
11274 /* Push arg pointer reg */
11277 }
11279 /* Grab the argument pointer. */
11286 /* Align the stack. */
11288 stack_pointer_rtx,
11292 /* Replicate the return address on the stack so that return
11293 address can be reached via (argp - 1) slot. This is needed
11294 to implement macro RETURN_ADDR_RTX and intrinsic function
11295 expand_builtin_return_addr etc. */
11301 /* For the purposes of frame and register save area addressing,
11302 we've started over with a new frame. */
11305 }
11311 {
11312 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11313 slower on all targets. Also sdb doesn't like it. */
11317 /* Push registers now, before setting the frame pointer
11318 on SEH target. */
11320 && TARGET_SEH
11322 {
11326 }
11329 {
11337 }
11338 }
11341 {
11342 /* If saving registers via PUSH, do so now. */
11344 {
11348 }
11350 /* When using red zone we may start register saving before allocating
11351 the stack frame saving one cycle of the prologue. However, avoid
11352 doing this if we have to probe the stack; at least on x86_64 the
11353 stack probe can turn into a call that clobbers a red zone location. */
11355 && (! TARGET_STACK_PROBE
11357 {
11360 }
11361 }
11364 {
11368 /* The computation of the size of the re-aligned stack frame means
11369 that we must allocate the size of the register save area before
11370 performing the actual alignment. Otherwise we cannot guarantee
11371 that there's enough storage above the realignment point. */
11378 /* Align the stack. */
11380 stack_pointer_rtx,
11383 /* For the purposes of register save area addressing, the stack
11384 pointer is no longer valid. As for the value of sp_offset,
11385 see ix86_compute_frame_layout, which we need to match in order
11386 to pass verification of stack_pointer_offset at the end. */
11389 }
11394 {
11395 /* We start to count from ARG_POINTER. */
11398 /* If it was realigned, take into account the fake frame. */
11400 {
11407 /* This over-estimates by 1 minimal-stack-alignment-unit but
11408 mitigates that by counting in the new return address slot. */
11409 current_function_dynamic_stack_size
11411 }
11414 }
11416 /* On SEH target with very large frame size, allocate an area to save
11417 SSE registers (as the very large allocation won't be described). */
11421 {
11422 HOST_WIDE_INT sse_size =
11427 /* No need to do stack checking as the area will be immediately
11428 written. */
11435 }
11437 /* The stack has already been decremented by the instruction calling us
11438 so probe if the size is non-negative to preserve the protection area. */
11440 {
11441 /* We expect the registers to be saved when probes are used. */
11445 {
11448 {
11451 }
11452 }
11453 else
11454 {
11461 {
11463 {
11466 }
11467 else
11469 }
11470 else
11471 {
11473 {
11477 }
11478 else
11480 }
11481 }
11482 }
11485 ;
11488 {
11492 }
11493 else
11494 {
11506 {
11509 /* Note that SEH directives need to continue tracking the stack
11510 pointer even after the frame pointer has been set up. */
11512 {
11516 }
11517 }
11520 {
11525 {
11529 }
11530 }
11535 /* Use the fact that AX still contains ALLOCATE. */
11537 ? gen_pro_epilogue_adjust_stack_di_sub
11544 {
11552 }
11555 /* Use stack_pointer_rtx for relative addressing so that code
11556 works for realigned stack, too. */
11558 {
11565 }
11567 {
11572 }
11573 }
11576 /* If we havn't already set up the frame pointer, do so now. */
11578 {
11590 }
11597 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11598 in PROLOGUE. */
11600 {
11606 /* Deleting already emmitted SET_GOT if exist and allocated to
11607 REAL_PIC_OFFSET_TABLE_REGNUM. */
11609 }
11612 {
11613 /* vDRAP is setup but after reload it turns out stack realign
11614 isn't necessary, here we will emit prologue to setup DRAP
11615 without stack realign adjustment */
11618 }
11620 /* Prevent instructions from being scheduled into register save push
11621 sequence when access to the redzone area is done through frame pointer.
11622 The offset between the frame pointer and the stack pointer is calculated
11623 relative to the value of the stack pointer at the end of the function
11624 prologue, and moving instructions that access redzone area via frame
11625 pointer inside push sequence violates this assumption. */
11629 /* Emit cld instruction if stringops are used in the function. */
11633 /* SEH requires that the prologue end within 256 bytes of the start of
11634 the function. Prevent instruction schedules that would extend that.
11635 Further, prevent alloca modifications to the stack pointer from being
11636 combined with prologue modifications. */
11639 }
11641 /* Emit code to restore REG using a POP insn. */
11643 static void
11645 {
11654 {
11655 /* Previously we'd represented the CFA as an expression
11656 like *(%ebp - 8). We've just popped that value from
11657 the stack, which means we need to reset the CFA to
11658 the drap register. This will remain until we restore
11659 the stack pointer. */
11663 /* This means that the DRAP register is valid for addressing too. */
11666 }
11669 {
11676 }
11678 /* When the frame pointer is the CFA, and we pop it, we are
11679 swapping back to the stack pointer as the CFA. This happens
11680 for stack frames that don't allocate other data, so we assume
11681 the stack pointer is now pointing at the return address, i.e.
11682 the function entry state, which makes the offset be 1 word. */
11684 {
11687 {
11695 }
11696 }
11697 }
11699 /* Emit code to restore saved registers using POP insns. */
11701 static void
11703 {
11709 }
11711 /* Emit code and notes for the LEAVE instruction. */
11713 static void
11715 {
11727 {
11735 }
11738 }
11740 /* Emit code to restore saved registers using MOV insns.
11741 First register is restored from CFA - CFA_OFFSET. */
11742 static void
11745 {
11751 {
11760 {
11761 /* Previously we'd represented the CFA as an expression
11762 like *(%ebp - 8). We've just popped that value from
11763 the stack, which means we need to reset the CFA to
11764 the drap register. This will remain until we restore
11765 the stack pointer. */
11769 /* This means that the DRAP register is valid for addressing. */
11771 }
11772 else
11776 }
11777 }
11779 /* Emit code to restore saved registers using MOV insns.
11780 First register is restored from CFA - CFA_OFFSET. */
11781 static void
11784 {
11789 {
11791 rtx mem;
11801 }
11802 }
11804 /* Restore function stack, frame, and registers. */
11806 void
11808 {
11824 /* The FP must be valid if the frame pointer is present. */
11829 /* We must have *some* valid pointer to the stack frame. */
11832 /* The DRAP is never valid at this point. */
11835 /* See the comment about red zone and frame
11836 pointer usage in ix86_expand_prologue. */
11843 /* Determine the CFA offset of the end of the red-zone. */
11846 {
11847 /* The red-zone begins below the return address. */
11850 /* When the register save area is in the aligned portion of
11851 the stack, determine the maximum runtime displacement that
11852 matches up with the aligned frame. */
11856 }
11858 /* Special care must be taken for the normal return case of a function
11859 using eh_return: the eax and edx registers are marked as saved, but
11860 not restored along this path. Adjust the save location to match. */
11864 /* EH_RETURN requires the use of moves to function properly. */
11867 /* SEH requires the use of pops to identify the epilogue. */
11870 /* If we're only restoring one register and sp is not valid then
11871 using a move instruction to restore the register since it's
11872 less work than reloading sp and popping the register. */
11885 && TARGET_USE_LEAVE
11889 else
11893 {
11894 /* Ensure that the entire register save area is addressable via
11895 the stack pointer, if we will restore via sp. */
11900 {
11904 style,
11906 }
11907 }
11909 /* If there are any SSE registers to restore, then we have to do it
11910 via moves, since there's obviously no pop for SSE regs. */
11916 {
11917 rtx t;
11922 /* eh_return epilogues need %ecx added to the stack pointer. */
11924 {
11927 /* Stack align doesn't work with eh_return. */
11929 /* Neither does regparm nested functions. */
11933 {
11941 /* Note that we use SA as a temporary CFA, as the return
11942 address is at the proper place relative to it. We
11943 pretend this happens at the FP restore insn because
11944 prior to this insn the FP would be stored at the wrong
11945 offset relative to SA, and after this insn we have no
11946 other reasonable register to use for the CFA. We don't
11947 bother resetting the CFA to the SP for the duration of
11948 the return insn. */
11961 }
11962 else
11963 {
11971 {
11975 UNITS_PER_WORD));
11977 }
11978 }
11981 }
11982 }
11983 else
11984 {
11985 /* SEH requires that the function end with (1) a stack adjustment
11986 if necessary, (2) a sequence of pops, and (3) a return or
11987 jump instruction. Prevent insns from the function body from
11988 being scheduled into this sequence. */
11990 {
11991 /* Prevent a catch region from being adjacent to the standard
11992 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11993 several other flags that would be interesting to test are
11994 not yet set up. */
11997 else
11999 }
12001 /* First step is to deallocate the stack frame so that we can
12002 pop the registers. Also do it on SEH target for very large
12003 frame as the emitted instructions aren't allowed by the ABI in
12004 epilogues. */
12006 || (TARGET_SEH
12009 {
12014 }
12016 {
12020 style,
12022 }
12025 }
12027 /* If we used a stack pointer and haven't already got rid of it,
12028 then do so now. */
12030 {
12031 /* If the stack pointer is valid and pointing at the frame
12032 pointer store address, then we only need a pop. */
12035 /* Leave results in shorter dependency chains on CPUs that are
12036 able to grok it fast. */
12041 else
12042 {
12044 hard_frame_pointer_rtx,
12047 }
12048 }
12051 {
12053 rtx insn;
12079 }
12081 /* At this point the stack pointer must be valid, and we must have
12082 restored all of the registers. We may not have deallocated the
12083 entire stack frame. We've delayed this until now because it may
12084 be possible to merge the local stack deallocation with the
12085 deallocation forced by ix86_static_chain_on_stack. */
12090 {
12094 }
12095 else
12098 /* Sibcall epilogues don't want a return instruction. */
12100 {
12103 }
12106 {
12109 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12110 address, do explicit add, and jump indirectly to the caller. */
12113 {
12115 rtx insn;
12117 /* There is no "pascal" calling convention in any 64bit ABI. */
12134 }
12135 else
12137 }
12138 else
12141 /* Restore the state back to the state from the prologue,
12142 so that it's correct for the next epilogue. */
12144 }
12146 /* Reset from the function's potential modifications. */
12148 static void
12150 {
12154 #if TARGET_MACHO
12155 /* Mach-O doesn't support labels at the end of objects, so if
12156 it looks like we might want one, insert a NOP. */
12157 {
12163 {
12164 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12165 notes only, instead set their CODE_LABEL_NUMBER to -1,
12166 otherwise there would be code generation differences
12167 in between -g and -g0. */
12171 }
12181 }
12182 #endif
12184 }
12186 /* Return a scratch register to use in the split stack prologue. The
12187 split stack prologue is used for -fsplit-stack. It is the first
12188 instructions in the function, even before the regular prologue.
12189 The scratch register can be any caller-saved register which is not
12190 used for parameters or for the static chain. */
12192 static unsigned int
12194 {
12197 else
12198 {
12211 {
12213 {
12217 }
12219 }
12221 {
12225 }
12227 {
12230 else
12231 {
12233 {
12237 }
12239 }
12240 }
12241 else
12242 {
12243 /* FIXME: We could make this work by pushing a register
12244 around the addition and comparison. */
12247 }
12248 }
12249 }
12251 /* A SYMBOL_REF for the function which allocates new stackspace for
12252 -fsplit-stack. */
12256 /* A SYMBOL_REF for the more stack function when using the large
12257 model. */
12261 /* Handle -fsplit-stack. These are the first instructions in the
12262 function, even before the regular prologue. */
12264 void
12266 {
12268 HOST_WIDE_INT allocate;
12274 rtx fn;
12282 /* This is the label we will branch to if we have enough stack
12283 space. We expect the basic block reordering pass to reverse this
12284 branch if optimizing, so that we branch in the unlikely case. */
12287 /* We need to compare the stack pointer minus the frame size with
12288 the stack boundary in the TCB. The stack boundary always gives
12289 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12290 can compare directly. Otherwise we need to do an addition. */
12293 UNSPEC_STACK_CHECK);
12298 else
12299 {
12301 rtx offset;
12303 /* We need a scratch register to hold the stack pointer minus
12304 the required frame size. Since this is the very start of the
12305 function, the scratch register can be any caller-saved
12306 register which is not used for parameters. */
12313 {
12314 /* We don't use ix86_gen_add3 in this case because it will
12315 want to split to lea, but when not optimizing the insn
12316 will not be split after this point. */
12319 offset)));
12320 }
12321 else
12322 {
12325 stack_pointer_rtx));
12326 }
12328 }
12334 /* Mark the jump as very likely to be taken. */
12339 {
12342 }
12345 /* Get more stack space. We pass in the desired stack space and the
12346 size of the arguments to copy to the new stack. In 32-bit mode
12347 we push the parameters; __morestack will return on a new stack
12348 anyhow. In 64-bit mode we pass the parameters in r10 and
12349 r11. */
12354 {
12360 /* If this function uses a static chain, it will be in %r10.
12361 Preserve it across the call to __morestack. */
12363 {
12364 rtx rax;
12369 }
12373 {
12374 HOST_WIDE_INT argval;
12377 /* When using the large model we need to load the address
12378 into a register, and we've run out of registers. So we
12379 switch to a different calling convention, and we call a
12380 different function: __morestack_large. We pass the
12381 argument size in the upper 32 bits of r10 and pass the
12382 frame size in the lower 32 bits. */
12387 {
12388 split_stack_fn_large =
12391 }
12393 {
12395 rtx x;
12404 UNSPEC_GOT);
12410 }
12411 else
12418 }
12419 else
12420 {
12424 }
12427 }
12428 else
12429 {
12432 }
12438 /* In order to make call/return prediction work right, we now need
12439 to execute a return instruction. See
12440 libgcc/config/i386/morestack.S for the details on how this works.
12442 For flow purposes gcc must not see this as a return
12443 instruction--we need control flow to continue at the subsequent
12444 label. Therefore, we use an unspec. */
12448 /* If we are in 64-bit mode and this function uses a static chain,
12449 we saved %r10 in %rax before calling _morestack. */
12454 /* If this function calls va_start, we need to store a pointer to
12455 the arguments on the old stack, because they may not have been
12456 all copied to the new stack. At this point the old stack can be
12457 found at the frame pointer value used by __morestack, because
12458 __morestack has set that up before calling back to us. Here we
12459 store that pointer in a scratch register, and in
12460 ix86_expand_prologue we store the scratch register in a stack
12461 slot. */
12463 {
12465 rtx frame_reg;
12472 /* 64-bit:
12473 fp -> old fp value
12474 return address within this function
12475 return address of caller of this function
12476 stack arguments
12477 So we add three words to get to the stack arguments.
12479 32-bit:
12480 fp -> old fp value
12481 return address within this function
12482 first argument to __morestack
12483 second argument to __morestack
12484 return address of caller of this function
12485 stack arguments
12486 So we add five words to get to the stack arguments.
12487 */
12498 }
12503 /* If this function calls va_start, we now have to set the scratch
12504 register for the case where we do not call __morestack. In this
12505 case we need to set it based on the stack pointer. */
12507 {
12514 }
12515 }
12517 /* We may have to tell the dataflow pass that the split stack prologue
12518 is initializing a scratch register. */
12520 static void
12522 {
12524 {
12527 }
12528 }
12529 \f
12530 /* Extract the parts of an RTL expression that is a valid memory address
12531 for an instruction. Return 0 if the structure of the address is
12532 grossly off. Return -1 if the address contains ASHIFT, so it is not
12533 strictly valid, but still used for computing length of lea instruction. */
12535 int
12537 {
12542 rtx tmp;
12546 /* Allow zero-extended SImode addresses,
12547 they will be emitted with addr32 prefix. */
12549 {
12552 {
12556 }
12559 {
12566 }
12567 }
12569 /* Allow SImode subregs of DImode addresses,
12570 they will be emitted with addr32 prefix. */
12572 {
12575 {
12579 }
12580 }
12585 {
12588 else
12590 }
12592 {
12597 do
12598 {
12603 }
12610 {
12613 {
12638 /* FALLTHRU */
12642 && TARGET_TLS_DIRECT_SEG_REFS
12645 else
12652 /* FALLTHRU */
12659 else
12674 }
12675 }
12676 }
12678 {
12681 }
12683 {
12684 /* We're called for lea too, which implements ashift on occasion. */
12694 }
12695 else
12699 {
12701 ;
12704 ;
12705 else
12707 }
12709 /* Extract the integral value of scale. */
12711 {
12715 }
12720 /* Avoid useless 0 displacement. */
12724 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12729 {
12732 }
12734 /* Special case: %ebp cannot be encoded as a base without a displacement.
12735 Similarly %r13. */
12737 && base_reg
12746 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12747 Avoid this by transforming to [%esi+0].
12748 Reload calls address legitimization without cfun defined, so we need
12749 to test cfun for being non-NULL. */
12755 /* Special case: encode reg+reg instead of reg*2. */
12759 /* Special case: scaling cannot be encoded without base or displacement. */
12770 }
12771 \f
12772 /* Return cost of the memory address x.
12773 For i386, it is better to use a complex address than let gcc copy
12774 the address into a reg and make a new pseudo. But not if the address
12775 requires to two regs - that would mean more pseudos with longer
12776 lifetimes. */
12777 static int
12779 {
12791 /* Attempt to minimize number of registers in the address. */
12797 cost++;
12799 /* When address base or index is "pic_offset_table_rtx" we don't increase
12800 address cost. When a memopt with "pic_offset_table_rtx" is not invariant
12801 itself it most likely means that base or index is not invariant.
12802 Therefore only "pic_offset_table_rtx" could be hoisted out, which is not
12803 profitable for x86. */
12805 && (!pic_offset_table_rtx
12809 && (!pic_offset_table_rtx
12813 cost++;
12815 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12816 since it's predecode logic can't detect the length of instructions
12817 and it degenerates to vector decoded. Increase cost of such
12818 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12819 to split such addresses or even refuse such addresses at all.
12821 Following addressing modes are affected:
12822 [base+scale*index]
12823 [scale*index+disp]
12824 [base+index]
12826 The first and last case may be avoidable by explicitly coding the zero in
12827 memory address, but I don't have AMD-K6 machine handy to check this
12828 theory. */
12837 }
12838 \f
12839 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12840 this is used for to form addresses to local data when -fPIC is in
12841 use. */
12843 static bool
12845 {
12848 }
12850 /* Determine if a given RTX is a valid constant. We already know this
12851 satisfies CONSTANT_P. */
12853 static bool
12855 {
12856 /* Pointer bounds constants are not valid. */
12861 {
12866 {
12870 }
12875 /* Only some unspecs are valid as "constants". */
12878 {
12894 }
12896 /* We must have drilled down to a symbol. */
12901 /* FALLTHRU */
12904 /* TLS symbols are never valid. */
12908 /* DLLIMPORT symbols are never valid. */
12913 #if TARGET_MACHO
12914 /* mdynamic-no-pic */
12917 #endif
12933 }
12935 /* Otherwise we handle everything else in the move patterns. */
12937 }
12939 /* Determine if it's legal to put X into the constant pool. This
12940 is not possible for the address of thread-local symbols, which
12941 is checked above. */
12943 static bool
12945 {
12946 /* We can always put integral constants and vectors in memory. */
12948 {
12956 }
12958 }
12960 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12961 otherwise zero. */
12963 static bool
12965 {
12971 }
12974 /* Nonzero if the constant value X is a legitimate general operand
12975 when generating PIC code. It is given that flag_pic is on and
12976 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12978 bool
12980 {
12981 rtx inner;
12984 {
12991 /* Only some unspecs are valid as "constants". */
12994 {
13007 }
13008 /* FALLTHRU */
13016 }
13017 }
13019 /* Determine if a given CONST RTX is a valid memory displacement
13020 in PIC mode. */
13022 bool
13024 {
13027 /* In 64bit mode we can allow direct addresses of symbols and labels
13028 when they are not dynamic symbols. */
13030 {
13034 {
13058 /* FALLTHRU */
13061 /* TLS references should always be enclosed in UNSPEC.
13062 The dllimported symbol needs always to be resolved. */
13068 {
13076 /* Function-symbols need to be resolved only for
13077 large-model.
13078 For the small-model we don't need to resolve anything
13079 here. */
13084 /* Non-external symbols don't need to be resolved for
13085 large, and medium-model. */
13090 }
13099 }
13100 }
13106 {
13107 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13108 of GOT tables. We should not need these anyway. */
13120 }
13124 {
13129 }
13138 {
13142 /* We need to check for both symbols and labels because VxWorks loads
13143 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13144 details. */
13148 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13149 While ABI specify also 32bit relocation but we don't produce it in
13150 small PIC model at all. */
13172 }
13175 }
13177 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
13178 replace the input X, or the original X if no replacement is called for.
13179 The output parameter *WIN is 1 if the calling macro should goto WIN,
13180 0 if it should not. */
13182 bool
13185 {
13186 /* Reload can generate:
13188 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
13189 (reg:DI 97))
13190 (reg:DI 2 cx))
13192 This RTX is rejected from ix86_legitimate_address_p due to
13193 non-strictness of base register 97. Following this rejection,
13194 reload pushes all three components into separate registers,
13195 creating invalid memory address RTX.
13197 Following code reloads only the invalid part of the
13198 memory address RTX. */
13204 {
13210 {
13215 }
13219 {
13224 }
13228 }
13231 }
13233 /* Determine if op is suitable RTX for an address register.
13234 Return naked register if a register or a register subreg is
13235 found, otherwise return NULL_RTX. */
13237 static rtx
13239 {
13242 /* Only SImode or DImode registers can form the address. */
13249 {
13257 /* Don't allow SUBREGs that span more than a word. It can
13258 lead to spill failures when the register is one word out
13259 of a two word structure. */
13263 /* Allow only SUBREGs of non-eliminable hard registers. */
13266 }
13268 /* Op is not a register. */
13270 }
13272 /* Recognizes RTL expressions that are valid memory addresses for an
13273 instruction. The MODE argument is the machine mode for the MEM
13274 expression that wants to use this address.
13276 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13277 convert common non-canonical forms to canonical form so that they will
13278 be recognized. */
13280 static bool
13282 {
13285 HOST_WIDE_INT scale;
13289 /* Decomposition failed. */
13298 /* Validate base register. */
13300 {
13308 /* Base is not valid. */
13310 }
13312 /* Validate index register. */
13314 {
13322 /* Index is not valid. */
13324 }
13326 /* Index and base should have the same mode. */
13331 /* Address override works only on the (%reg) part of %fs:(%reg). */
13337 /* Validate scale factor. */
13339 {
13341 /* Scale without index. */
13345 /* Scale is not a valid multiplier. */
13347 }
13349 /* Validate displacement. */
13351 {
13356 {
13357 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13358 used. While ABI specify also 32bit relocations, we don't produce
13359 them at all and use IP relative instead. */
13366 /* 64bit address unspec. */
13386 /* Invalid address unspec. */
13388 }
13391 && (flag_pic
13392 || (TARGET_MACHO
13393 #if TARGET_MACHO
13394 && MACHOPIC_INDIRECT
13396 #endif
13397 )))
13398 {
13400 is_legitimate_pic:
13402 {
13403 /* foo@dtpoff(%rX) is ok. */
13410 /* Non-constant pic memory reference. */
13412 }
13415 /* Displacement is an invalid pic construct. */
13417 #if TARGET_MACHO
13420 /* displacment must be referenced via non_lazy_pointer */
13422 #endif
13424 /* This code used to verify that a symbolic pic displacement
13425 includes the pic_offset_table_rtx register.
13427 While this is good idea, unfortunately these constructs may
13428 be created by "adds using lea" optimization for incorrect
13429 code like:
13431 int a;
13432 int foo(int i)
13433 {
13434 return *(&a+i);
13435 }
13437 This code is nonsensical, but results in addressing
13438 GOT table with pic_offset_table_rtx base. We can't
13439 just refuse it easily, since it gets matched by
13440 "addsi3" pattern, that later gets split to lea in the
13441 case output register differs from input. While this
13442 can be handled by separate addsi pattern for this case
13443 that never results in lea, this seems to be easier and
13444 correct fix for crash to disable this test. */
13445 }
13452 /* Displacement is not constant. */
13456 /* Displacement is out of range. */
13458 /* In x32 mode, constant addresses are sign extended to 64bit, so
13459 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13464 }
13466 /* Everything looks valid. */
13468 }
13470 /* Determine if a given RTX is a valid constant address. */
13472 bool
13474 {
13476 }
13477 \f
13478 /* Return a unique alias set for the GOT. */
13480 static alias_set_type
13482 {
13487 }
13489 /* Set regs_ever_live for PIC base address register
13490 to true if required. */
13491 static void
13493 {
13496 }
13498 /* Return a legitimate reference for ORIG (an address) using the
13499 register REG. If REG is 0, a new pseudo is generated.
13501 There are two types of references that must be handled:
13503 1. Global data references must load the address from the GOT, via
13504 the PIC reg. An insn is emitted to do this load, and the reg is
13505 returned.
13507 2. Static data references, constant pool addresses, and code labels
13508 compute the address as an offset from the GOT, whose base is in
13509 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13510 differentiate them from global data objects. The returned
13511 address is the PIC reg + an unspec constant.
13513 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13514 reg also appears in the address. */
13516 static rtx
13518 {
13522 #if TARGET_MACHO
13524 {
13527 /* Use the generic Mach-O PIC machinery. */
13529 }
13530 #endif
13533 {
13537 }
13543 {
13544 rtx tmpreg;
13545 /* This symbol may be referenced via a displacement from the PIC
13546 base address (@GOTOFF). */
13552 {
13554 UNSPEC_GOTOFF);
13556 }
13557 else
13562 else
13567 {
13571 }
13572 else
13574 }
13576 {
13577 /* This symbol may be referenced via a displacement from the PIC
13578 base address (@GOTOFF). */
13584 {
13586 UNSPEC_GOTOFF);
13588 }
13589 else
13595 {
13598 }
13599 }
13601 /* We can't use @GOTOFF for text labels on VxWorks;
13602 see gotoff_operand. */
13604 {
13609 /* For x64 PE-COFF there is no GOT table. So we use address
13610 directly. */
13612 {
13620 }
13622 {
13630 /* Use directly gen_movsi, otherwise the address is loaded
13631 into register for CSE. We don't want to CSE this addresses,
13632 instead we CSE addresses from the GOT table, so skip this. */
13635 }
13636 else
13637 {
13638 /* This symbol must be referenced via a load from the
13639 Global Offset Table (@GOT). */
13654 }
13655 }
13656 else
13657 {
13660 {
13662 {
13665 }
13666 else
13668 }
13670 {
13673 /* We must match stuff we generate before. Assume the only
13674 unspecs that can get here are ours. Not that we could do
13675 anything with them anyway.... */
13681 }
13683 {
13686 /* Check first to see if this is a constant offset from a @GOTOFF
13687 symbol reference. */
13690 {
13692 {
13695 UNSPEC_GOTOFF);
13701 {
13704 }
13705 }
13706 else
13707 {
13710 {
13714 }
13715 }
13716 }
13717 else
13718 {
13721 new_rtx
13725 {
13728 {
13731 new_rtx
13733 }
13734 else
13736 }
13737 else
13738 {
13741 {
13744 }
13746 }
13747 }
13748 }
13749 }
13751 }
13752 \f
13753 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13755 static rtx
13757 {
13761 {
13766 }
13772 }
13774 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13778 static rtx
13780 {
13782 {
13788 }
13791 {
13793 UNSPEC_PLTOFF);
13796 }
13799 }
13801 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13805 rtx
13807 {
13809 {
13810 ix86_tls_module_base_symbol
13815 }
13818 }
13820 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13821 false if we expect this to be used for a memory address and true if
13822 we expect to load the address into a register. */
13824 static rtx
13826 {
13832 /* Fall back to global dynamic model if tool chain cannot support local
13833 dynamic. */
13840 {
13845 {
13848 else
13849 {
13852 }
13853 }
13856 {
13859 else
13869 }
13870 else
13871 {
13875 {
13880 emit_call_insn
13890 }
13891 else
13893 }
13900 {
13903 else
13904 {
13907 }
13908 }
13911 {
13916 else
13922 }
13923 else
13924 {
13928 {
13931 rtx eqv;
13934 emit_call_insn
13939 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13940 share the LD_BASE result with other LD model accesses. */
13942 UNSPEC_TLS_LD_BASE);
13946 }
13947 else
13949 }
13957 {
13964 }
13969 {
13971 {
13972 /* The Sun linker took the AMD64 TLS spec literally
13973 and can only handle %rax as destination of the
13974 initial executable code sequence. */
13979 }
13981 /* Generate DImode references to avoid %fs:(%reg32)
13982 problems and linker IE->LE relaxation bug. */
13986 }
13988 {
13992 }
13994 {
13998 }
13999 else
14000 {
14003 }
14013 {
14018 }
14019 else
14020 {
14024 }
14034 {
14038 }
14039 else
14040 {
14044 }
14049 }
14052 }
14054 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14055 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14056 unique refptr-DECL symbol corresponding to symbol DECL. */
14059 {
14063 {
14065 }
14067 static void
14069 {
14075 else
14077 }
14078 };
14082 static tree
14084 {
14090 tree to;
14091 rtx rtl;
14118 else
14131 {
14133 #ifdef SUB_TARGET_RECORD_STUB
14135 #endif
14136 }
14145 }
14147 /* Expand SYMBOL into its corresponding far-addresse symbol.
14148 WANT_REG is true if we require the result be a register. */
14150 static rtx
14152 {
14153 tree imp_decl;
14154 rtx x;
14163 }
14165 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14166 true if we require the result be a register. */
14168 static rtx
14170 {
14171 tree imp_decl;
14172 rtx x;
14181 }
14183 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14184 is true if we require the result be a register. */
14186 static rtx
14188 {
14193 {
14200 {
14203 }
14204 }
14220 {
14223 }
14225 }
14227 /* Try machine-dependent ways of modifying an illegitimate address
14228 to be legitimate. If we find one, return the new, valid address.
14229 This macro is used in only one place: `memory_address' in explow.c.
14231 OLDX is the address as it was before break_out_memory_refs was called.
14232 In some cases it is useful to look at this to decide what needs to be done.
14234 It is always safe for this macro to do nothing. It exists to recognize
14235 opportunities to optimize the output.
14237 For the 80386, we handle X+REG by loading X into a register R and
14238 using R+REG. R will go in a general reg and indexing will be used.
14239 However, if REG is a broken-out memory address or multiplication,
14240 nothing needs to be done because REG can certainly go in a general reg.
14242 When -fpic is used, special handling is needed for symbolic references.
14243 See comments by legitimize_pic_address in i386.c for details. */
14245 static rtx
14247 {
14258 {
14262 }
14265 {
14269 }
14274 #if TARGET_MACHO
14277 #endif
14279 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14283 {
14288 }
14291 {
14292 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14297 {
14303 }
14308 {
14314 }
14316 /* Put multiply first if it isn't already. */
14318 {
14323 }
14325 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14326 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14327 created by virtual register instantiation, register elimination, and
14328 similar optimizations. */
14330 {
14336 }
14338 /* Canonicalize
14339 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14340 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14345 {
14346 rtx constant;
14350 {
14353 }
14355 {
14358 }
14359 else
14363 {
14370 }
14371 }
14377 {
14380 }
14383 {
14386 }
14394 {
14397 }
14403 {
14407 {
14410 }
14414 }
14417 {
14421 {
14424 }
14428 }
14429 }
14432 }
14433 \f
14434 /* Print an integer constant expression in assembler syntax. Addition
14435 and subtraction are the only arithmetic that may appear in these
14436 expressions. FILE is the stdio stream to write to, X is the rtx, and
14437 CODE is the operand print code from the output string. */
14439 static void
14441 {
14445 {
14454 else
14455 {
14458 /* Mark the decl as referenced so that cgraph will
14459 output the function. */
14463 #if TARGET_MACHO
14467 #endif
14469 }
14477 /* FALLTHRU */
14488 /* This used to output parentheses around the expression,
14489 but that does not work on the 386 (either ATT or BSD assembler). */
14495 {
14496 /* We can use %d if the number is <32 bits and positive. */
14501 else
14503 }
14504 else
14505 /* We can't handle floating point constants;
14506 TARGET_PRINT_OPERAND must handle them. */
14511 /* Some assemblers need integer constants to appear first. */
14513 {
14517 }
14518 else
14519 {
14524 }
14539 {
14543 }
14548 {
14567 /* FIXME: This might be @TPOFF in Sun ld too. */
14576 else
14586 else
14592 #if TARGET_MACHO
14597 #endif
14601 }
14606 }
14607 }
14609 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14610 We need to emit DTP-relative relocations. */
14612 static void ATTRIBUTE_UNUSED
14614 {
14619 {
14627 }
14628 }
14630 /* Return true if X is a representation of the PIC register. This copes
14631 with calls from ix86_find_base_term, where the register might have
14632 been replaced by a cselib value. */
14634 static bool
14636 {
14643 {
14651 }
14652 else
14654 }
14656 /* Helper function for ix86_delegitimize_address.
14657 Attempt to delegitimize TLS local-exec accesses. */
14659 static rtx
14661 {
14686 {
14691 }
14697 }
14699 /* In the name of slightly smaller debug output, and to cater to
14700 general assembler lossage, recognize PIC+GOTOFF and turn it back
14701 into a direct symbol reference.
14703 On Darwin, this is necessary to avoid a crash, because Darwin
14704 has a different PIC label for each routine but the DWARF debugging
14705 information is not associated with any particular routine, so it's
14706 necessary to remove references to the PIC label from RTL stored by
14707 the DWARF output code. */
14709 static rtx
14711 {
14713 /* addend is NULL or some rtx if x is something+GOTOFF where
14714 something doesn't include the PIC register. */
14716 /* reg_addend is NULL or a multiple of some register. */
14718 /* const_addend is NULL or a const_int. */
14720 /* This is the result, or NULL. */
14729 {
14736 {
14742 }
14749 {
14752 {
14757 }
14759 }
14764 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14765 and -mcmodel=medium -fpic. */
14766 }
14773 /* %ebx + GOT/GOTOFF */
14774 ;
14776 {
14777 /* %ebx + %reg * scale + GOT/GOTOFF */
14783 else
14784 {
14787 }
14788 }
14789 else
14795 {
14798 }
14819 {
14820 /* If the rest of original X doesn't involve the PIC register, add
14821 addend and subtract pic_offset_table_rtx. This can happen e.g.
14822 for code like:
14823 leal (%ebx, %ecx, 4), %ecx
14824 ...
14825 movl foo@GOTOFF(%ecx), %edx
14826 in which case we return (%ecx - %ebx) + foo
14827 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
14828 and reload has completed. */
14832 pic_offset_table_rtx),
14833 result);
14835 {
14839 }
14840 else
14842 }
14844 {
14848 }
14850 }
14852 /* If X is a machine specific address (i.e. a symbol or label being
14853 referenced as a displacement from the GOT implemented using an
14854 UNSPEC), then return the base term. Otherwise return X. */
14856 rtx
14858 {
14859 rtx term;
14862 {
14876 }
14879 }
14880 \f
14881 static void
14884 {
14888 {
14891 }
14896 {
14899 {
14918 }
14922 {
14941 }
14948 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14949 Those same assemblers have the same but opposite lossage on cmov. */
14952 else
14957 {
14970 }
14977 else
14982 {
14995 }
15002 else
15012 else
15023 }
15025 }
15027 /* Print the name of register X to FILE based on its machine mode and number.
15028 If CODE is 'w', pretend the mode is HImode.
15029 If CODE is 'b', pretend the mode is QImode.
15030 If CODE is 'k', pretend the mode is SImode.
15031 If CODE is 'q', pretend the mode is DImode.
15032 If CODE is 'x', pretend the mode is V4SFmode.
15033 If CODE is 't', pretend the mode is V8SFmode.
15034 If CODE is 'g', pretend the mode is V16SFmode.
15035 If CODE is 'h', pretend the reg is the 'high' byte register.
15036 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15037 If CODE is 'd', duplicate the operand for AVX instruction.
15038 */
15040 void
15042 {
15051 {
15055 }
15082 else
15085 /* Irritatingly, AMD extended registers use different naming convention
15086 from the normal registers: "r%d[bwd]" */
15088 {
15093 {
15107 /* no suffix */
15112 }
15114 }
15118 {
15121 {
15124 }
15125 /* FALLTHRU */
15131 /* FALLTHRU */
15134 normal:
15149 {
15154 }
15157 {
15162 }
15166 }
15170 {
15173 else
15175 }
15176 }
15178 /* Meaning of CODE:
15179 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15180 C -- print opcode suffix for set/cmov insn.
15181 c -- like C, but print reversed condition
15182 F,f -- likewise, but for floating-point.
15183 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15184 otherwise nothing
15185 R -- print embeded rounding and sae.
15186 r -- print only sae.
15187 z -- print the opcode suffix for the size of the current operand.
15188 Z -- likewise, with special suffixes for x87 instructions.
15189 * -- print a star (in certain assembler syntax)
15190 A -- print an absolute memory reference.
15191 E -- print address with DImode register names if TARGET_64BIT.
15192 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15193 s -- print a shift double count, followed by the assemblers argument
15194 delimiter.
15195 b -- print the QImode name of the register for the indicated operand.
15196 %b0 would print %al if operands[0] is reg 0.
15197 w -- likewise, print the HImode name of the register.
15198 k -- likewise, print the SImode name of the register.
15199 q -- likewise, print the DImode name of the register.
15200 x -- likewise, print the V4SFmode name of the register.
15201 t -- likewise, print the V8SFmode name of the register.
15202 g -- likewise, print the V16SFmode name of the register.
15203 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15204 y -- print "st(0)" instead of "st" as a register.
15205 d -- print duplicated register operand for AVX instruction.
15206 D -- print condition for SSE cmp instruction.
15207 P -- if PIC, print an @PLT suffix.
15208 p -- print raw symbol name.
15209 X -- don't print any sort of PIC '@' suffix for a symbol.
15210 & -- print some in-use local-dynamic symbol name.
15211 H -- print a memory address offset by 8; used for sse high-parts
15212 Y -- print condition for XOP pcom* instruction.
15213 + -- print a branch hint as 'cs' or 'ds' prefix
15214 ; -- print a semicolon (after prefixes due to bug in older gas).
15215 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15216 @ -- print a segment register of thread base pointer load
15217 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15218 ! -- print MPX prefix for jxx/call/ret instructions if required.
15219 */
15221 void
15223 {
15225 {
15227 {
15230 {
15236 /* Intel syntax. For absolute addresses, registers should not
15237 be surrounded by braces. */
15239 {
15244 }
15249 }
15255 /* Wrap address in an UNSPEC to declare special handling. */
15293 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15298 {
15312 output_operand_lossage
15315 }
15318 #endif
15323 {
15324 /* Opcodes don't get size suffixes if using Intel opcodes. */
15329 {
15347 output_operand_lossage
15350 }
15351 }
15354 warning
15356 /* FALLTHRU */
15359 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15364 {
15366 {
15368 #ifdef HAVE_AS_IX86_FILDS
15370 #endif
15378 #ifdef HAVE_AS_IX86_FILDQ
15380 #else
15382 #endif
15387 }
15388 }
15390 {
15391 /* 387 opcodes don't get size suffixes
15392 if the operands are registers. */
15397 {
15413 }
15414 }
15415 else
15416 {
15417 output_operand_lossage
15420 }
15422 output_operand_lossage
15443 {
15446 }
15451 {
15502 }
15506 /* Little bit of braindamage here. The SSE compare instructions
15507 does use completely different names for the comparisons that the
15508 fp conditional moves. */
15510 {
15513 {
15516 }
15522 {
15525 }
15531 {
15534 }
15543 {
15546 }
15552 {
15555 }
15561 {
15564 }
15575 }
15580 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15583 #endif
15588 {
15592 }
15596 file);
15601 {
15605 }
15606 /* It doesn't actually matter what mode we use here, as we're
15607 only going to use this for printing. */
15609 /* Output 'qword ptr' for intel assembler dialect. */
15618 #ifdef HAVE_AS_IX86_HLE
15620 #else
15622 #endif
15624 #ifdef HAVE_AS_IX86_HLE
15626 #else
15628 #endif
15629 /* We do not want to print value of the operand. */
15658 {
15673 }
15686 {
15691 else
15694 }
15697 {
15698 rtx x;
15707 {
15712 {
15714 bool cputaken
15717 /* Emit hints only in the case default branch prediction
15718 heuristics would fail. */
15720 {
15721 /* We use 3e (DS) prefix for taken branches and
15722 2e (CS) prefix for not taken branches. */
15725 else
15727 }
15728 }
15729 }
15731 }
15734 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15736 #endif
15743 /* The kernel uses a different segment register for performance
15744 reasons; a system call would not have to trash the userspace
15745 segment register, which would be expensive. */
15748 else
15768 }
15769 }
15775 {
15776 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15779 {
15782 {
15791 else
15798 }
15800 /* Check for explicit size override (codes 'b', 'w', 'k',
15801 'q' and 'x') */
15815 }
15818 /* Avoid (%rip) for call operands. */
15824 else
15826 }
15829 {
15830 REAL_VALUE_TYPE r;
15838 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15842 else
15844 }
15847 {
15848 REAL_VALUE_TYPE r;
15857 }
15859 /* These float cases don't actually occur as immediate operands. */
15861 {
15866 }
15868 else
15869 {
15870 /* We have patterns that allow zero sets of memory, for instance.
15871 In 64-bit mode, we should probably support all 8-byte vectors,
15872 since we can in fact encode that into an immediate. */
15874 {
15877 }
15880 {
15882 {
15885 }
15888 {
15891 else
15893 }
15894 }
15899 else
15901 }
15902 }
15904 static bool
15906 {
15909 }
15910 \f
15911 /* Print a memory operand whose address is ADDR. */
15913 static void
15915 {
15924 {
15931 }
15933 {
15937 }
15939 {
15943 {
15946 }
15949 }
15951 {
15956 }
15957 else
15968 {
15979 }
15981 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15983 {
15995 }
15997 {
15998 /* Displacement only requires special attention. */
16001 {
16005 }
16008 else
16010 }
16011 else
16012 {
16013 /* Print SImode register names to force addr32 prefix. */
16015 {
16016 #ifdef ENABLE_CHECKING
16019 {
16030 }
16031 #endif
16034 }
16036 && TARGET_X32
16037 && disp
16040 {
16041 /* X32 runs in 64-bit mode, where displacement, DISP, in
16042 address DISP(%r64), is encoded as 32-bit immediate sign-
16043 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16044 address is %r64 + 0xffffffffbffffd00. When %r64 <
16045 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16046 which is invalid for x32. The correct address is %r64
16047 - 0x40000300 == 0xf7ffdd64. To properly encode
16048 -0x40000300(%r64) for x32, we zero-extend negative
16049 displacement by forcing addr32 prefix which truncates
16050 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16051 zero-extend all negative displacements, including -1(%rsp).
16052 However, for small negative displacements, sign-extension
16053 won't cause overflow. We only zero-extend negative
16054 displacements if they < -16*1024*1024, which is also used
16055 to check legitimate address displacements for PIC. */
16057 }
16060 {
16062 {
16067 else
16069 }
16075 {
16080 }
16082 }
16083 else
16084 {
16088 {
16089 /* Pull out the offset of a symbol; print any symbol itself. */
16093 {
16097 }
16105 else
16107 }
16111 {
16114 {
16118 }
16119 }
16122 else
16126 {
16131 }
16133 }
16134 }
16135 }
16137 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16139 static bool
16141 {
16142 rtx op;
16149 {
16152 /* FIXME: This might be @TPOFF in Sun ld. */
16163 else
16175 else
16182 #if TARGET_MACHO
16188 #endif
16191 {
16196 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16198 #else
16200 #endif
16203 }
16208 }
16211 }
16212 \f
16213 /* Split one or more double-mode RTL references into pairs of half-mode
16214 references. The RTL can be REG, offsettable MEM, integer constant, or
16215 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16216 split and "num" is its length. lo_half and hi_half are output arrays
16217 that parallel "operands". */
16219 void
16222 {
16223 machine_mode half_mode;
16227 {
16236 }
16241 {
16244 /* simplify_subreg refuse to split volatile memory addresses,
16245 but we still have to handle it. */
16247 {
16250 }
16251 else
16252 {
16259 }
16260 }
16261 }
16262 \f
16263 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16264 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16265 is the expression of the binary operation. The output may either be
16266 emitted here, or returned to the caller, like all output_* functions.
16268 There is no guarantee that the operands are the same mode, as they
16269 might be within FLOAT or FLOAT_EXTEND expressions. */
16271 #ifndef SYSV386_COMPAT
16272 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16273 wants to fix the assemblers because that causes incompatibility
16274 with gcc. No-one wants to fix gcc because that causes
16275 incompatibility with assemblers... You can use the option of
16276 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16277 #define SYSV386_COMPAT 1
16278 #endif
16282 {
16288 #ifdef ENABLE_CHECKING
16289 /* Even if we do not want to check the inputs, this documents input
16290 constraints. Which helps in understanding the following code. */
16300 else
16302 #endif
16305 {
16310 else
16319 else
16328 else
16337 else
16344 }
16347 {
16349 {
16353 else
16355 }
16356 else
16357 {
16361 else
16363 }
16365 }
16369 {
16373 {
16377 }
16379 /* know operands[0] == operands[1]. */
16382 {
16385 }
16388 {
16390 /* How is it that we are storing to a dead operand[2]?
16391 Well, presumably operands[1] is dead too. We can't
16392 store the result to st(0) as st(0) gets popped on this
16393 instruction. Instead store to operands[2] (which I
16394 think has to be st(1)). st(1) will be popped later.
16395 gcc <= 2.8.1 didn't have this check and generated
16396 assembly code that the Unixware assembler rejected. */
16398 else
16401 }
16405 else
16412 {
16415 }
16418 {
16421 }
16424 {
16425 #if SYSV386_COMPAT
16426 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16427 derived assemblers, confusingly reverse the direction of
16428 the operation for fsub{r} and fdiv{r} when the
16429 destination register is not st(0). The Intel assembler
16430 doesn't have this brain damage. Read !SYSV386_COMPAT to
16431 figure out what the hardware really does. */
16434 else
16436 #else
16438 /* As above for fmul/fadd, we can't store to st(0). */
16440 else
16442 #endif
16444 }
16447 {
16448 #if SYSV386_COMPAT
16451 else
16453 #else
16456 else
16458 #endif
16460 }
16463 {
16466 else
16469 }
16471 {
16472 #if SYSV386_COMPAT
16474 #else
16476 #endif
16477 }
16478 else
16479 {
16480 #if SYSV386_COMPAT
16482 #else
16484 #endif
16485 }
16490 }
16494 }
16496 /* Check if a 256bit AVX register is referenced inside of EXP. */
16498 static bool
16500 {
16506 }
16508 /* Return needed mode for entity in optimize_mode_switching pass. */
16510 static int
16512 {
16514 {
16515 rtx link;
16517 /* Needed mode is set to AVX_U128_CLEAN if there are
16518 no 256bit modes used in function arguments. */
16520 link;
16522 {
16524 {
16529 }
16530 }
16533 }
16535 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16536 changes state only when a 256bit register is written to, but we need
16537 to prevent the compiler from moving optimal insertion point above
16538 eventual read from 256bit register. */
16545 }
16547 /* Return mode that i387 must be switched into
16548 prior to the execution of insn. */
16550 static int
16552 {
16555 /* The mode UNINITIALIZED is used to store control word after a
16556 function call or ASM pattern. The mode ANY specify that function
16557 has no requirements on the control word and make no changes in the
16558 bits we are interested in. */
16572 {
16595 }
16598 }
16600 /* Return mode that entity must be switched into
16601 prior to the execution of insn. */
16603 static int
16605 {
16607 {
16617 }
16619 }
16621 /* Check if a 256bit AVX register is referenced in stores. */
16623 static void
16625 {
16627 {
16630 }
16631 }
16633 /* Calculate mode of upper 128bit AVX registers after the insn. */
16635 static int
16637 {
16644 /* We know that state is clean after CALL insn if there are no
16645 256bit registers used in the function return register. */
16647 {
16652 }
16654 /* Otherwise, return current mode. Remember that if insn
16655 references AVX 256bit registers, the mode was already changed
16656 to DIRTY from MODE_NEEDED. */
16658 }
16660 /* Return the mode that an insn results in. */
16662 int
16664 {
16666 {
16676 }
16677 }
16679 static int
16681 {
16682 tree arg;
16684 /* Entry mode is set to AVX_U128_DIRTY if there are
16685 256bit modes used in function arguments. */
16688 {
16693 }
16696 }
16698 /* Return a mode that ENTITY is assumed to be
16699 switched to at function entry. */
16701 static int
16703 {
16705 {
16715 }
16716 }
16718 static int
16720 {
16723 /* Exit mode is set to AVX_U128_DIRTY if there are
16724 256bit modes used in the function return register. */
16729 }
16731 /* Return a mode that ENTITY is assumed to be
16732 switched to at function exit. */
16734 static int
16736 {
16738 {
16748 }
16749 }
16751 static int
16753 {
16755 }
16757 /* Output code to initialize control word copies used by trunc?f?i and
16758 rounding patterns. CURRENT_MODE is set to current control word,
16759 while NEW_MODE is set to new control word. */
16761 static void
16763 {
16765 rtx new_mode;
16776 {
16778 {
16780 /* round toward zero (truncate) */
16786 /* round down toward -oo */
16793 /* round up toward +oo */
16800 /* mask precision exception for nearbyint() */
16807 }
16808 }
16809 else
16810 {
16812 {
16814 /* round toward zero (truncate) */
16820 /* round down toward -oo */
16826 /* round up toward +oo */
16832 /* mask precision exception for nearbyint() */
16839 }
16840 }
16846 }
16848 /* Emit vzeroupper. */
16850 void
16852 {
16855 /* Cancel automatic vzeroupper insertion if there are
16856 live call-saved SSE registers at the insertion point. */
16868 }
16870 /* Generate one or more insns to set ENTITY to MODE. */
16872 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16873 is the set of hard registers live at the point where the insn(s)
16874 are to be inserted. */
16876 static void
16878 HARD_REG_SET regs_live)
16879 {
16881 {
16896 }
16897 }
16899 /* Output code for INSN to convert a float to a signed int. OPERANDS
16900 are the insn operands. The output may be [HSD]Imode and the input
16901 operand may be [SDX]Fmode. */
16905 {
16910 /* Jump through a hoop or two for DImode, since the hardware has no
16911 non-popping instruction. We used to do this a different way, but
16912 that was somewhat fragile and broke with post-reload splitters. */
16922 else
16923 {
16928 else
16932 }
16935 }
16937 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16938 have the values zero or one, indicates the ffreep insn's operand
16939 from the OPERANDS array. */
16943 {
16945 #ifdef HAVE_AS_IX86_FFREEP
16947 #else
16948 {
16958 }
16959 #endif
16962 }
16965 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16966 should be used. UNORDERED_P is true when fucom should be used. */
16970 {
16976 {
16979 }
16980 else
16981 {
16984 }
16987 {
16991 else
16993 else
16996 else
16998 }
17005 {
17007 {
17010 }
17011 else
17013 }
17016 && stack_top_dies
17019 {
17020 /* If both the top of the 387 stack dies, and the other operand
17021 is also a stack register that dies, then this must be a
17022 `fcompp' float compare */
17025 {
17026 /* There is no double popping fcomi variant. Fortunately,
17027 eflags is immune from the fstp's cc clobbering. */
17030 else
17033 }
17034 else
17035 {
17038 else
17040 }
17041 }
17042 else
17043 {
17044 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17047 {
17055 NULL,
17056 NULL,
17063 NULL,
17064 NULL,
17065 NULL,
17066 NULL
17067 };
17082 }
17083 }
17085 void
17087 {
17090 #ifdef ASM_QUAD
17093 #else
17095 #endif
17098 }
17100 void
17102 {
17105 #ifdef ASM_QUAD
17108 #else
17110 #endif
17111 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17117 #if TARGET_MACHO
17119 {
17123 }
17124 #endif
17125 else
17128 }
17129 \f
17130 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17131 for the target. */
17133 void
17135 {
17136 rtx tmp;
17138 /* We play register width games, which are only valid after reload. */
17141 /* Avoid HImode and its attendant prefix byte. */
17147 {
17150 }
17153 }
17155 /* X is an unchanging MEM. If it is a constant pool reference, return
17156 the constant pool rtx, else NULL. */
17158 rtx
17160 {
17167 }
17169 void
17171 {
17179 {
17180 rtx tmp;
17184 {
17190 }
17193 }
17197 {
17200 rtx tmp;
17205 else
17209 {
17216 }
17217 }
17221 {
17223 {
17224 #if TARGET_MACHO
17225 /* dynamic-no-pic */
17227 {
17228 rtx temp = ((reload_in_progress
17236 }
17238 {
17242 }
17245 else
17246 {
17254 }
17255 /* dynamic-no-pic */
17256 #endif
17257 }
17258 else
17259 {
17263 {
17269 }
17270 }
17271 }
17272 else
17273 {
17284 /* Force large constants in 64bit compilation into register
17285 to get them CSEed. */
17297 {
17298 /* If we are loading a floating point constant to a register,
17299 force the value to memory now, since we'll get better code
17300 out the back end. */
17304 {
17309 }
17310 }
17311 }
17314 }
17316 void
17318 {
17325 /* Force constants other than zero into memory. We do not know how
17326 the instructions used to build constants modify the upper 64 bits
17327 of the register, once we have that information we may be able
17328 to handle some of them more efficiently. */
17337 /* We need to check memory alignment for SSE mode since attribute
17338 can make operands unaligned. */
17343 {
17346 /* ix86_expand_vector_move_misalign() does not like constants ... */
17352 /* ... nor both arguments in memory. */
17360 }
17362 /* Make operand1 a register if it isn't already. */
17366 {
17369 }
17372 }
17374 /* Split 32-byte AVX unaligned load and store if needed. */
17376 static void
17378 {
17379 rtx m;
17383 machine_mode mode;
17386 {
17407 }
17410 {
17412 {
17419 }
17420 /* Normal *mov<mode>_internal pattern will handle
17421 unaligned loads just fine if misaligned_operand
17422 is true, and without the UNSPEC it can be combined
17423 with arithmetic instructions. */
17426 else
17428 }
17430 {
17432 {
17437 }
17438 else
17440 }
17441 else
17443 }
17445 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17446 straight to ix86_expand_vector_move. */
17447 /* Code generation for scalar reg-reg moves of single and double precision data:
17448 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17449 movaps reg, reg
17450 else
17451 movss reg, reg
17452 if (x86_sse_partial_reg_dependency == true)
17453 movapd reg, reg
17454 else
17455 movsd reg, reg
17457 Code generation for scalar loads of double precision data:
17458 if (x86_sse_split_regs == true)
17459 movlpd mem, reg (gas syntax)
17460 else
17461 movsd mem, reg
17463 Code generation for unaligned packed loads of single precision data
17464 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17465 if (x86_sse_unaligned_move_optimal)
17466 movups mem, reg
17468 if (x86_sse_partial_reg_dependency == true)
17469 {
17470 xorps reg, reg
17471 movlps mem, reg
17472 movhps mem+8, reg
17473 }
17474 else
17475 {
17476 movlps mem, reg
17477 movhps mem+8, reg
17478 }
17480 Code generation for unaligned packed loads of double precision data
17481 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17482 if (x86_sse_unaligned_move_optimal)
17483 movupd mem, reg
17485 if (x86_sse_split_regs == true)
17486 {
17487 movlpd mem, reg
17488 movhpd mem+8, reg
17489 }
17490 else
17491 {
17492 movsd mem, reg
17493 movhpd mem+8, reg
17494 }
17495 */
17497 void
17499 {
17508 {
17510 {
17514 {
17516 {
17519 }
17520 else
17522 }
17524 /* FALLTHRU */
17528 {
17543 }
17549 else
17557 }
17560 }
17564 {
17566 {
17570 {
17572 {
17575 }
17576 else
17578 }
17580 /* FALLTHRU */
17590 }
17593 }
17596 {
17597 /* Normal *mov<mode>_internal pattern will handle
17598 unaligned loads just fine if misaligned_operand
17599 is true, and without the UNSPEC it can be combined
17600 with arithmetic instructions. */
17606 /* ??? If we have typed data, then it would appear that using
17607 movdqu is the only way to get unaligned data loaded with
17608 integer type. */
17610 {
17612 {
17615 }
17617 /* We will eventually emit movups based on insn attributes. */
17621 }
17623 {
17624 rtx zero;
17627 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17628 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17630 {
17631 /* We will eventually emit movups based on insn attributes. */
17634 }
17636 /* When SSE registers are split into halves, we can avoid
17637 writing to the top half twice. */
17639 {
17642 }
17643 else
17644 {
17645 /* ??? Not sure about the best option for the Intel chips.
17646 The following would seem to satisfy; the register is
17647 entirely cleared, breaking the dependency chain. We
17648 then store to the upper half, with a dependency depth
17649 of one. A rumor has it that Intel recommends two movsd
17650 followed by an unpacklpd, but this is unconfirmed. And
17651 given that the dependency depth of the unpacklpd would
17652 still be one, I'm not sure why this would be better. */
17654 }
17660 }
17661 else
17662 {
17663 rtx t;
17666 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17667 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17669 {
17671 {
17674 }
17681 }
17685 else
17690 else
17699 }
17700 }
17702 {
17704 {
17707 /* We will eventually emit movups based on insn attributes. */
17709 }
17711 {
17713 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17714 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17716 /* We will eventually emit movups based on insn attributes. */
17718 else
17719 {
17724 }
17725 }
17726 else
17727 {
17732 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17733 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17735 {
17738 }
17739 else
17740 {
17745 }
17746 }
17747 }
17748 else
17750 }
17752 /* Helper function of ix86_fixup_binary_operands to canonicalize
17753 operand order. Returns true if the operands should be swapped. */
17755 static bool
17757 rtx operands[])
17758 {
17763 /* If the operation is not commutative, we can't do anything. */
17767 /* Highest priority is that src1 should match dst. */
17773 /* Next highest priority is that immediate constants come second. */
17779 /* Lowest priority is that memory references should come second. */
17786 }
17789 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17790 destination to use for the operation. If different from the true
17791 destination in operands[0], a copy operation will be required. */
17793 rtx
17795 rtx operands[])
17796 {
17801 /* Canonicalize operand order. */
17803 {
17804 /* It is invalid to swap operands of different modes. */
17808 }
17810 /* Both source operands cannot be in memory. */
17812 {
17813 /* Optimization: Only read from memory once. */
17815 {
17818 }
17821 else
17823 }
17825 /* If the destination is memory, and we do not have matching source
17826 operands, do things in registers. */
17830 /* Source 1 cannot be a constant. */
17834 /* Source 1 cannot be a non-matching memory. */
17838 /* Improve address combine. */
17847 }
17849 /* Similarly, but assume that the destination has already been
17850 set up properly. */
17852 void
17855 {
17858 }
17860 /* Attempt to expand a binary operator. Make the expansion closer to the
17861 actual machine, then just general_operand, which will allow 3 separate
17862 memory references (one output, two input) in a single insn. */
17864 void
17866 rtx operands[])
17867 {
17874 /* Emit the instruction. */
17878 {
17879 /* Reload doesn't know about the flags register, and doesn't know that
17880 it doesn't want to clobber it. We can only do this with PLUS. */
17883 }
17887 {
17888 /* This is going to be an LEA; avoid splitting it later. */
17890 }
17891 else
17892 {
17895 }
17897 /* Fix up the destination if needed. */
17900 }
17902 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17903 the given OPERANDS. */
17905 void
17907 rtx operands[])
17908 {
17911 {
17914 }
17916 {
17919 }
17920 /* Optimize (__m128i) d | (__m128i) e and similar code
17921 when d and e are float vectors into float vector logical
17922 insn. In C/C++ without using intrinsics there is no other way
17923 to express vector logical operation on float vectors than
17924 to cast them temporarily to integer vectors. */
17926 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17935 {
17936 rtx dst;
17938 {
17947 {
17950 }
17951 else
17952 {
17957 }
17968 }
17969 }
17978 }
17980 /* Return TRUE or FALSE depending on whether the binary operator meets the
17981 appropriate constraints. */
17983 bool
17986 {
17991 /* Both source operands cannot be in memory. */
17995 /* Canonicalize operand order for commutative operators. */
17999 /* If the destination is memory, we must have a matching source operand. */
18003 /* Source 1 cannot be a constant. */
18007 /* Source 1 cannot be a non-matching memory. */
18009 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18017 }
18019 /* Attempt to expand a unary operator. Make the expansion closer to the
18020 actual machine, then just general_operand, which will allow 2 separate
18021 memory references (one output, one input) in a single insn. */
18023 void
18025 rtx operands[])
18026 {
18033 /* If the destination is memory, and we do not have matching source
18034 operands, do things in registers. */
18037 {
18040 else
18042 }
18044 /* When source operand is memory, destination must match. */
18048 /* Emit the instruction. */
18052 {
18053 /* Reload doesn't know about the flags register, and doesn't know that
18054 it doesn't want to clobber it. */
18057 }
18058 else
18059 {
18062 }
18064 /* Fix up the destination if needed. */
18067 }
18069 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18070 divisor are within the range [0-255]. */
18072 void
18075 {
18084 {
18097 }
18104 /* Use 8bit unsigned divimod if dividend and divisor are within
18105 the range [0-255]. */
18114 pc_rtx);
18119 /* Generate original signed/unsigned divimod. */
18124 /* Branch to the end. */
18128 /* Generate 8bit unsigned divide. */
18130 /* Don't use operands[0] for result of 8bit divide since not all
18131 registers support QImode ZERO_EXTRACT. */
18138 {
18141 }
18142 else
18143 {
18146 }
18148 /* Extract remainder from AH. */
18152 else
18153 {
18154 /* Need a new scratch register since the old one has result
18155 of 8bit divide. */
18159 }
18162 /* Zero extend quotient from AL. */
18168 }
18170 #define LEA_MAX_STALL (3)
18171 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18173 /* Increase given DISTANCE in half-cycles according to
18174 dependencies between PREV and NEXT instructions.
18175 Add 1 half-cycle if there is no dependency and
18176 go to next cycle if there is some dependecy. */
18178 static unsigned int
18180 {
18196 }
18198 /* Function checks if instruction INSN defines register number
18199 REGNO1 or REGNO2. */
18201 static bool
18203 rtx insn)
18204 {
18205 df_ref def;
18215 }
18217 /* Function checks if instruction INSN uses register number
18218 REGNO as a part of address expression. */
18220 static bool
18222 {
18223 df_ref use;
18230 }
18232 /* Search backward for non-agu definition of register number REGNO1
18233 or register number REGNO2 in basic block starting from instruction
18234 START up to head of basic block or instruction INSN.
18236 Function puts true value into *FOUND var if definition was found
18237 and false otherwise.
18239 Distance in half-cycles between START and found instruction or head
18240 of BB is added to DISTANCE and returned. */
18242 static int
18246 {
18256 {
18258 {
18261 {
18264 {
18267 }
18268 }
18271 }
18276 }
18279 }
18281 /* Search backward for non-agu definition of register number REGNO1
18282 or register number REGNO2 in INSN's basic block until
18283 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18284 2. Reach neighbour BBs boundary, or
18285 3. Reach agu definition.
18286 Returns the distance between the non-agu definition point and INSN.
18287 If no definition point, returns -1. */
18289 static int
18292 {
18303 {
18304 edge e;
18305 edge_iterator ei;
18310 {
18313 }
18319 else
18320 {
18325 {
18326 int bb_dist
18332 {
18339 }
18340 }
18343 }
18344 }
18346 /* get_attr_type may modify recog data. We want to make sure
18347 that recog data is valid for instruction INSN, on which
18348 distance_non_agu_define is called. INSN is unchanged here. */
18355 }
18357 /* Return the distance in half-cycles between INSN and the next
18358 insn that uses register number REGNO in memory address added
18359 to DISTANCE. Return -1 if REGNO0 is set.
18361 Put true value into *FOUND if register usage was found and
18362 false otherwise.
18363 Put true value into *REDEFINED if register redefinition was
18364 found and false otherwise. */
18366 static int
18370 {
18379 {
18382 /* If insn and start belong to the same bb, set prev to insn,
18383 so the call to increase_distance will increase the distance
18384 between insns by 1. */
18386 }
18391 {
18393 {
18396 {
18397 /* Return DISTANCE if OP0 is used in memory
18398 address in NEXT. */
18401 }
18404 {
18405 /* Return -1 if OP0 is set in NEXT. */
18408 }
18411 }
18417 }
18420 }
18422 /* Return the distance between INSN and the next insn that uses
18423 register number REGNO0 in memory address. Return -1 if no such
18424 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18426 static int
18428 {
18440 {
18441 edge e;
18442 edge_iterator ei;
18447 {
18450 }
18456 else
18457 {
18463 {
18464 int bb_dist
18469 {
18476 }
18477 }
18480 }
18481 }
18487 }
18489 /* Define this macro to tune LEA priority vs ADD, it take effect when
18490 there is a dilemma of choicing LEA or ADD
18491 Negative value: ADD is more preferred than LEA
18492 Zero: Netrual
18493 Positive value: LEA is more preferred than ADD*/
18494 #define IX86_LEA_PRIORITY 0
18496 /* Return true if usage of lea INSN has performance advantage
18497 over a sequence of instructions. Instructions sequence has
18498 SPLIT_COST cycles higher latency than lea latency. */
18500 static bool
18503 {
18506 /* For Silvermont if using a 2-source or 3-source LEA for
18507 non-destructive destination purposes, or due to wanting
18508 ability to use SCALE, the use of LEA is justified. */
18510 {
18518 }
18524 {
18525 /* If there is no non AGU operand definition, no AGU
18526 operand usage and split cost is 0 then both lea
18527 and non lea variants have same priority. Currently
18528 we prefer lea for 64 bit code and non lea on 32 bit
18529 code. */
18532 else
18534 }
18536 /* With longer definitions distance lea is more preferable.
18537 Here we change it to take into account splitting cost and
18538 lea priority. */
18541 /* If there is no use in memory addess then we just check
18542 that split cost exceeds AGU stall. */
18546 /* If this insn has both backward non-agu dependence and forward
18547 agu dependence, the one with short distance takes effect. */
18549 }
18551 /* Return true if it is legal to clobber flags by INSN and
18552 false otherwise. */
18554 static bool
18556 {
18558 df_ref use;
18559 bitmap live;
18562 {
18564 {
18571 }
18577 }
18581 }
18583 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18584 move and add to avoid AGU stalls. */
18586 bool
18588 {
18591 /* Check if we need to optimize. */
18595 /* Check it is correct to split here. */
18603 /* We need to split only adds with non destructive
18604 destination operand. */
18607 else
18609 }
18611 /* Return true if we should emit lea instruction instead of mov
18612 instruction. */
18614 bool
18616 {
18619 /* Check if we need to optimize. */
18623 /* Use lea for reg to reg moves only. */
18631 }
18633 /* Return true if we need to split lea into a sequence of
18634 instructions to avoid AGU stalls. */
18636 bool
18638 {
18644 /* Check we need to optimize. */
18648 /* The "at least two components" test below might not catch simple
18649 move or zero extension insns if parts.base is non-NULL and parts.disp
18650 is const0_rtx as the only components in the address, e.g. if the
18651 register is %rbp or %r13. As this test is much cheaper and moves or
18652 zero extensions are the common case, do this check first. */
18658 /* Check if it is OK to split here. */
18665 /* There should be at least two components in the address. */
18670 /* We should not split into add if non legitimate pic
18671 operand is used as displacement. */
18686 /* Compute how many cycles we will add to execution time
18687 if split lea into a sequence of instructions. */
18689 {
18690 /* Have to use mov instruction if non desctructive
18691 destination form is used. */
18695 /* Have to add index to base if both exist. */
18699 /* Have to use shift and adds if scale is 2 or greater. */
18701 {
18706 else
18708 }
18710 /* Have to use add instruction with immediate if
18711 disp is non zero. */
18715 /* Subtract the price of lea. */
18717 }
18721 }
18723 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18724 matches destination. RTX includes clobber of FLAGS_REG. */
18726 static void
18729 {
18736 }
18738 /* Return true if regno1 def is nearest to the insn. */
18740 static bool
18742 {
18749 {
18751 {
18754 }
18760 }
18762 /* None of the regs is defined in the bb. */
18764 }
18766 /* Split lea instructions into a sequence of instructions
18767 which are executed on ALU to avoid AGU stalls.
18768 It is assumed that it is allowed to clobber flags register
18769 at lea position. */
18771 void
18773 {
18789 {
18792 }
18795 {
18798 }
18804 {
18805 /* Case r1 = r1 + ... */
18807 {
18808 /* If we have a case r1 = r1 + C * r2 then we
18809 should use multiplication which is very
18810 expensive. Assume cost model is wrong if we
18811 have such case here. */
18816 }
18817 else
18818 {
18819 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18823 /* Use shift for scaling. */
18832 }
18833 }
18835 {
18838 }
18839 else
18840 {
18842 {
18845 }
18847 {
18850 }
18851 else
18852 {
18857 else
18858 {
18859 rtx tmp1;
18861 /* Find better operand for SET instruction, depending
18862 on which definition is farther from the insn. */
18865 else
18875 }
18878 }
18882 }
18883 }
18885 /* Return true if it is ok to optimize an ADD operation to LEA
18886 operation to avoid flag register consumation. For most processors,
18887 ADD is faster than LEA. For the processors like BONNELL, if the
18888 destination register of LEA holds an actual address which will be
18889 used soon, LEA is better and otherwise ADD is better. */
18891 bool
18893 {
18898 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18906 }
18908 /* Return true if destination reg of SET_BODY is shift count of
18909 USE_BODY. */
18911 static bool
18913 {
18914 rtx set_dest;
18915 rtx shift_rtx;
18918 /* Retrieve destination of SET_BODY. */
18920 {
18929 use_body))
18934 }
18936 /* Retrieve shift count of USE_BODY. */
18938 {
18950 }
18958 {
18961 /* Return true if shift count is dest of SET_BODY. */
18963 {
18964 /* Add check since it can be invoked before register
18965 allocation in pre-reload schedule. */
18971 }
18972 }
18975 }
18977 /* Return true if destination reg of SET_INSN is shift count of
18978 USE_INSN. */
18980 bool
18982 {
18985 }
18987 /* Return TRUE or FALSE depending on whether the unary operator meets the
18988 appropriate constraints. */
18990 bool
18992 machine_mode,
18994 {
18995 /* If one of operands is memory, source and destination must match. */
19001 }
19003 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19004 are ok, keeping in mind the possible movddup alternative. */
19006 bool
19008 {
19014 }
19016 /* Post-reload splitter for converting an SF or DFmode value in an
19017 SSE register into an unsigned SImode. */
19019 void
19021 {
19022 machine_mode vecmode;
19032 /* Load up the value into the low element. We must ensure that the other
19033 elements are valid floats -- zero is the easiest such value. */
19035 {
19038 else
19040 }
19041 else
19042 {
19047 else
19049 }
19069 else
19074 }
19076 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19077 Expects the 64-bit DImode to be supplied in a pair of integral
19078 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19079 -mfpmath=sse, !optimize_size only. */
19081 void
19083 {
19087 rtx x;
19093 {
19096 }
19097 else
19098 {
19102 }
19110 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19113 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19114 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19115 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19116 (0x1.0p84 + double(fp_value_hi_xmm)).
19117 Note these exponents differ by 32. */
19121 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19122 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19131 /* Add the upper and lower DFmode values together. */
19134 else
19135 {
19139 }
19142 }
19144 /* Not used, but eases macroization of patterns. */
19145 void
19147 {
19149 }
19151 /* Convert an unsigned SImode value into a DFmode. Only currently used
19152 for SSE, but applicable anywhere. */
19154 void
19156 {
19157 REAL_VALUE_TYPE TWO31r;
19172 }
19174 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19175 32-bit mode; otherwise we have a direct convert instruction. */
19177 void
19179 {
19180 REAL_VALUE_TYPE TWO32r;
19198 }
19200 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19201 For x86_32, -mfpmath=sse, !optimize_size only. */
19202 void
19204 {
19205 REAL_VALUE_TYPE ONE16r;
19224 }
19226 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19227 a vector of unsigned ints VAL to vector of floats TARGET. */
19229 void
19231 {
19233 REAL_VALUE_TYPE TWO16r;
19240 else
19245 OPTAB_DIRECT);
19256 OPTAB_DIRECT);
19258 OPTAB_DIRECT);
19261 }
19263 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19264 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19265 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19266 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19268 rtx
19270 {
19271 REAL_VALUE_TYPE TWO31r;
19286 {
19292 }
19301 OPTAB_DIRECT);
19302 else
19303 {
19309 OPTAB_DIRECT);
19310 }
19313 }
19315 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19316 then replicate the value for all elements of the vector
19317 register. */
19319 rtx
19321 {
19323 rtvec v;
19324 machine_mode scalar_mode;
19327 {
19360 }
19361 }
19363 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19364 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19365 for an SSE register. If VECT is true, then replicate the mask for
19366 all elements of the vector register. If INVERT is true, then create
19367 a mask excluding the sign bit. */
19369 rtx
19371 {
19375 rtx v;
19376 rtx mask;
19378 /* Find the sign bit, sign extended to 2*HWI. */
19380 {
19404 else
19412 {
19415 }
19416 else
19417 {
19418 rtvec vec;
19424 {
19427 }
19428 else
19438 }
19443 }
19448 /* Force this value into the low part of a fp vector constant. */
19457 }
19459 /* Generate code for floating point ABS or NEG. */
19461 void
19463 rtx operands[])
19464 {
19475 {
19481 }
19483 /* NEG and ABS performed with SSE use bitwise mask operations.
19484 Create the appropriate mask now. */
19487 else
19497 {
19499 rtvec par;
19504 else
19505 {
19508 }
19510 }
19511 else
19513 }
19515 /* Expand a copysign operation. Special case operand 0 being a constant. */
19517 void
19519 {
19533 else
19537 {
19544 {
19547 else
19548 {
19552 }
19553 }
19563 else
19567 }
19568 else
19569 {
19579 else
19583 }
19584 }
19586 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19587 be a constant, and so has already been expanded into a vector constant. */
19589 void
19591 {
19607 {
19610 }
19611 }
19613 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19614 so we have to do two masks. */
19616 void
19618 {
19633 {
19634 /* Shouldn't happen often (it's useless, obviously), but when it does
19635 we'd generate incorrect code if we continue below. */
19638 }
19641 {
19652 }
19653 else
19654 {
19656 {
19658 }
19660 {
19664 }
19668 {
19671 }
19673 {
19678 }
19680 }
19684 }
19686 /* Return TRUE or FALSE depending on whether the first SET in INSN
19687 has source and destination with matching CC modes, and that the
19688 CC mode is at least as constrained as REQ_MODE. */
19690 bool
19692 {
19693 rtx set;
19694 machine_mode set_mode;
19704 {
19714 /* FALLTHRU */
19718 /* FALLTHRU */
19722 /* FALLTHRU */
19736 }
19739 }
19741 /* Generate insn patterns to do an integer compare of OPERANDS. */
19743 static rtx
19745 {
19746 machine_mode cmpmode;
19752 /* This is very simple, but making the interface the same as in the
19753 FP case makes the rest of the code easier. */
19757 /* Return the test that should be put into the flags user, i.e.
19758 the bcc, scc, or cmov instruction. */
19760 }
19762 /* Figure out whether to use ordered or unordered fp comparisons.
19763 Return the appropriate mode to use. */
19765 machine_mode
19767 {
19768 /* ??? In order to make all comparisons reversible, we do all comparisons
19769 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19770 all forms trapping and nontrapping comparisons, we can make inequality
19771 comparisons trapping again, since it results in better code when using
19772 FCOM based compares. */
19774 }
19776 machine_mode
19778 {
19782 {
19785 }
19788 {
19789 /* Only zero flag is needed. */
19793 /* Codes needing carry flag. */
19796 /* Detect overflow checks. They need just the carry flag. */
19800 else
19805 /* Codes possibly doable only with sign flag when
19806 comparing against zero. */
19811 else
19812 /* For other cases Carry flag is not required. */
19814 /* Codes doable only with sign flag when comparing
19815 against zero, but we miss jump instruction for it
19816 so we need to use relational tests against overflow
19817 that thus needs to be zero. */
19822 else
19824 /* strcmp pattern do (use flags) and combine may ask us for proper
19825 mode. */
19830 }
19831 }
19833 /* Return the fixed registers used for condition codes. */
19835 static bool
19837 {
19841 }
19843 /* If two condition code modes are compatible, return a condition code
19844 mode which is compatible with both. Otherwise, return
19845 VOIDmode. */
19847 static machine_mode
19849 {
19866 {
19880 {
19894 }
19898 /* These are only compatible with themselves, which we already
19899 checked above. */
19901 }
19902 }
19905 /* Return a comparison we can do and that it is equivalent to
19906 swap_condition (code) apart possibly from orderedness.
19907 But, never change orderedness if TARGET_IEEE_FP, returning
19908 UNKNOWN in that case if necessary. */
19910 static enum rtx_code
19912 {
19914 {
19925 }
19926 }
19928 /* Return cost of comparison CODE using the best strategy for performance.
19929 All following functions do use number of instructions as a cost metrics.
19930 In future this should be tweaked to compute bytes for optimize_size and
19931 take into account performance of various instructions on various CPUs. */
19933 static int
19935 {
19938 /* The cost of code using bit-twiddling on %ah. */
19940 {
19963 }
19966 {
19973 }
19974 }
19976 /* Return strategy to use for floating-point. We assume that fcomi is always
19977 preferrable where available, since that is also true when looking at size
19978 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19980 enum ix86_fpcmp_strategy
19982 {
19983 /* Do fcomi/sahf based test when profitable. */
19992 }
19994 /* Swap, force into registers, or otherwise massage the two operands
19995 to a fp comparison. The operands are updated in place; the new
19996 comparison code is returned. */
19998 static enum rtx_code
20000 {
20006 /* All of the unordered compare instructions only work on registers.
20007 The same is true of the fcomi compare instructions. The XFmode
20008 compare instructions require registers except when comparing
20009 against zero or when converting operand 1 from fixed point to
20010 floating point. */
20019 {
20022 }
20023 else
20024 {
20025 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20026 things around if they appear profitable, otherwise force op0
20027 into a register. */
20033 {
20036 {
20039 }
20040 }
20046 {
20051 {
20054 }
20055 else
20057 }
20058 }
20060 /* Try to rearrange the comparison to make it cheaper. */
20064 {
20069 }
20074 }
20076 /* Convert comparison codes we use to represent FP comparison to integer
20077 code that will result in proper branch. Return UNKNOWN if no such code
20078 is available. */
20080 enum rtx_code
20082 {
20084 {
20107 }
20108 }
20110 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20112 static rtx
20114 {
20121 /* Do fcomi/sahf based test when profitable. */
20123 {
20128 tmp);
20136 tmp);
20145 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20152 /* In the unordered case, we have to check C2 for NaN's, which
20153 doesn't happen to work out to anything nice combination-wise.
20154 So do some bit twiddling on the value we've got in AH to come
20155 up with an appropriate set of condition codes. */
20159 {
20163 {
20166 }
20167 else
20168 {
20174 }
20179 {
20184 }
20185 else
20186 {
20189 }
20194 {
20197 }
20198 else
20199 {
20203 }
20208 {
20214 }
20215 else
20216 {
20219 }
20224 {
20229 }
20230 else
20231 {
20234 }
20239 {
20244 }
20245 else
20246 {
20249 }
20263 }
20268 }
20270 /* Return the test that should be put into the flags user, i.e.
20271 the bcc, scc, or cmov instruction. */
20274 const0_rtx);
20275 }
20277 static rtx
20279 {
20280 rtx ret;
20286 {
20289 }
20290 else
20294 }
20296 void
20298 {
20300 rtx tmp;
20303 {
20310 simple:
20314 pc_rtx);
20322 /* Expand DImode branch into multiple compare+branch. */
20323 {
20327 machine_mode submode;
20330 {
20333 }
20340 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20341 avoid two branches. This costs one extra insn, so disable when
20342 optimizing for size. */
20347 {
20365 }
20367 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20368 op1 is a constant and the low word is zero, then we can just
20369 examine the high word. Similarly for low word -1 and
20370 less-or-equal-than or greater-than. */
20374 {
20377 {
20380 }
20384 {
20387 }
20391 }
20393 /* Otherwise, we need two or three jumps. */
20402 {
20416 }
20418 /*
20419 * a < b =>
20420 * if (hi(a) < hi(b)) goto true;
20421 * if (hi(a) > hi(b)) goto false;
20422 * if (lo(a) < lo(b)) goto true;
20423 * false:
20424 */
20436 }
20441 }
20442 }
20444 /* Split branch based on floating point condition. */
20445 void
20448 {
20449 rtx condition;
20450 rtx i;
20453 {
20458 }
20461 tmp);
20469 }
20471 void
20473 {
20474 rtx ret;
20481 }
20483 /* Expand comparison setting or clearing carry flag. Return true when
20484 successful and set pop for the operation. */
20485 static bool
20487 {
20488 machine_mode mode =
20491 /* Do not handle double-mode compares that go through special path. */
20496 {
20497 rtx compare_op;
20502 /* Shortcut: following common codes never translate
20503 into carry flag compares. */
20508 /* These comparisons require zero flag; swap operands so they won't. */
20511 {
20514 }
20516 /* Try to expand the comparison and verify that we end up with
20517 carry flag based comparison. This fails to be true only when
20518 we decide to expand comparison using arithmetic that is not
20519 too common scenario. */
20528 else
20537 }
20543 {
20548 /* Convert a==0 into (unsigned)a<1. */
20557 /* Convert a>b into b<a or a>=b-1. */
20561 {
20563 /* Bail out on overflow. We still can swap operands but that
20564 would force loading of the constant into register. */
20569 }
20570 else
20571 {
20574 }
20577 /* Convert a>=0 into (unsigned)a<0x80000000. */
20595 }
20596 /* Swapping operands may cause constant to appear as first operand. */
20598 {
20602 }
20606 }
20608 bool
20610 {
20613 rtx compare_op;
20635 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20636 HImode insns, we'd be swallowed in word prefix ops. */
20642 {
20646 HOST_WIDE_INT diff;
20649 /* Sign bit compares are better done using shifts than we do by using
20650 sbb. */
20653 {
20654 /* Detect overlap between destination and compare sources. */
20658 {
20659 rtx flags;
20668 {
20670 compare_code
20672 }
20674 /* To simplify rest of code, restrict to the GEU case. */
20676 {
20682 }
20683 else
20684 {
20687 reverse_condition_maybe_unordered
20689 else
20692 }
20701 else
20704 }
20705 else
20706 {
20709 else
20710 {
20715 }
20717 }
20720 {
20721 /*
20722 * cmpl op0,op1
20723 * sbbl dest,dest
20724 * [addl dest, ct]
20725 *
20726 * Size 5 - 8.
20727 */
20732 }
20734 {
20735 /*
20736 * cmpl op0,op1
20737 * sbbl dest,dest
20738 * orl $ct, dest
20739 *
20740 * Size 8.
20741 */
20745 }
20747 {
20748 /*
20749 * cmpl op0,op1
20750 * sbbl dest,dest
20751 * notl dest
20752 * [addl dest, cf]
20753 *
20754 * Size 8 - 11.
20755 */
20761 }
20762 else
20763 {
20764 /*
20765 * cmpl op0,op1
20766 * sbbl dest,dest
20767 * [notl dest]
20768 * andl cf - ct, dest
20769 * [addl dest, ct]
20770 *
20771 * Size 8 - 11.
20772 */
20775 {
20779 }
20789 }
20795 }
20798 {
20805 {
20808 /* We may be reversing unordered compare to normal compare, that
20809 is not valid in general (we may convert non-trapping condition
20810 to trapping one), however on i386 we currently emit all
20811 comparisons unordered. */
20814 }
20815 else
20816 {
20819 }
20820 }
20825 {
20830 {
20835 }
20836 }
20838 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20842 {
20843 /* If lea code below could be used, only optimize
20844 if it results in a 2 insn sequence. */
20850 {
20851 /*
20852 * notl op1 (if necessary)
20853 * sarl $31, op1
20854 * orl cf, op1
20855 */
20857 {
20861 }
20872 }
20873 }
20881 {
20882 /*
20883 * xorl dest,dest
20884 * cmpl op1,op2
20885 * setcc dest
20886 * lea cf(dest*(ct-cf)),dest
20887 *
20888 * Size 14.
20889 *
20890 * This also catches the degenerate setcc-only case.
20891 */
20893 rtx tmp;
20899 /* On x86_64 the lea instruction operates on Pmode, so we need
20900 to get arithmetics done in proper mode to match. */
20903 else
20904 {
20905 rtx out1;
20908 nops++;
20910 {
20912 nops++;
20913 }
20914 }
20916 {
20918 nops++;
20919 }
20921 {
20924 else
20926 }
20931 }
20933 /*
20934 * General case: Jumpful:
20935 * xorl dest,dest cmpl op1, op2
20936 * cmpl op1, op2 movl ct, dest
20937 * setcc dest jcc 1f
20938 * decl dest movl cf, dest
20939 * andl (cf-ct),dest 1:
20940 * addl ct,dest
20941 *
20942 * Size 20. Size 14.
20943 *
20944 * This is reasonably steep, but branch mispredict costs are
20945 * high on modern cpus, so consider failing only if optimizing
20946 * for space.
20947 */
20952 {
20954 {
20961 {
20964 /* We may be reversing unordered compare to normal compare,
20965 that is not valid in general (we may convert non-trapping
20966 condition to trapping one), however on i386 we currently
20967 emit all comparisons unordered. */
20969 }
20970 else
20971 {
20975 }
20976 }
20979 {
20980 /* notl op1 (if needed)
20981 sarl $31, op1
20982 andl (cf-ct), op1
20983 addl ct, op1
20985 For x < 0 (resp. x <= -1) there will be no notl,
20986 so if possible swap the constants to get rid of the
20987 complement.
20988 True/false will be -1/0 while code below (store flag
20989 followed by decrement) is 0/-1, so the constants need
20990 to be exchanged once more. */
20993 {
20996 }
20997 else
21001 }
21002 else
21003 {
21007 constm1_rtx,
21009 }
21021 }
21022 }
21025 {
21026 /* Try a few things more with specific constants and a variable. */
21028 optab op;
21034 /* If one of the two operands is an interesting constant, load a
21035 constant with the above and mask it in with a logical operation. */
21038 {
21044 else
21046 }
21048 {
21054 else
21056 }
21057 else
21064 /* Recurse to get the constant loaded. */
21068 /* Mask in the interesting variable. */
21070 OPTAB_WIDEN);
21075 }
21077 /*
21078 * For comparison with above,
21079 *
21080 * movl cf,dest
21081 * movl ct,tmp
21082 * cmpl op1,op2
21083 * cmovcc tmp,dest
21084 *
21085 * Size 15.
21086 */
21108 }
21110 /* Swap, force into registers, or otherwise massage the two operands
21111 to an sse comparison with a mask result. Thus we differ a bit from
21112 ix86_prepare_fp_compare_args which expects to produce a flags result.
21114 The DEST operand exists to help determine whether to commute commutative
21115 operators. The POP0/POP1 operands are updated in place. The new
21116 comparison code is returned, or UNKNOWN if not implementable. */
21118 static enum rtx_code
21121 {
21123 {
21126 /* AVX supports all the needed comparisons. */
21129 /* We have no LTGT as an operator. We could implement it with
21130 NE & ORDERED, but this requires an extra temporary. It's
21131 not clear that it's worth it. */
21138 /* These are supported directly. */
21145 /* AVX has 3 operand comparisons, no need to swap anything. */
21148 /* For commutative operators, try to canonicalize the destination
21149 operand to be first in the comparison - this helps reload to
21150 avoid extra moves. */
21153 /* FALLTHRU */
21159 /* These are not supported directly before AVX, and furthermore
21160 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21161 comparison operands to transform into something that is
21162 supported. */
21169 }
21172 }
21174 /* Detect conditional moves that exactly match min/max operational
21175 semantics. Note that this is IEEE safe, as long as we don't
21176 interchange the operands.
21178 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21179 and TRUE if the operation is successful and instructions are emitted. */
21181 static bool
21184 {
21185 machine_mode mode;
21187 rtx tmp;
21190 ;
21193 else
21200 else
21205 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21206 but MODE may be a vector mode and thus not appropriate. */
21208 {
21210 rtvec v;
21215 }
21216 else
21217 {
21220 }
21224 }
21226 /* Expand an sse vector comparison. Return the register with the result. */
21228 static rtx
21231 {
21235 /* In general case result of comparison can differ from operands' type. */
21236 machine_mode cmp_mode;
21238 /* In AVX512F the result of comparison is an integer mask. */
21240 rtx x;
21243 {
21248 }
21249 else
21262 /* Compare patterns for int modes are unspec in AVX512F only. */
21264 {
21268 {
21277 }
21280 {
21283 }
21284 }
21288 {
21291 }
21292 else
21296 }
21298 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21299 operations. This is used for both scalar and vector conditional moves. */
21301 static void
21303 {
21307 /* In AVX512F the result of comparison is an integer mask. */
21315 {
21317 }
21320 {
21324 }
21327 {
21332 }
21335 {
21339 }
21342 {
21350 op_true,
21351 op_false)));
21352 }
21353 else
21354 {
21364 {
21378 {
21385 }
21400 {
21407 }
21431 }
21434 {
21438 }
21439 else
21440 {
21446 else
21458 }
21459 }
21460 }
21462 /* Expand a floating-point conditional move. Return true if successful. */
21464 bool
21466 {
21474 {
21475 machine_mode cmode;
21477 /* Since we've no cmove for sse registers, don't force bad register
21478 allocation just to gain access to it. Deny movcc when the
21479 comparison mode doesn't match the move mode. */
21498 }
21505 /* The floating point conditional move instructions don't directly
21506 support conditions resulting from a signed integer comparison. */
21510 {
21515 }
21522 }
21524 /* Expand a floating-point vector conditional move; a vcond operation
21525 rather than a movcc operation. */
21527 bool
21529 {
21531 rtx cmp;
21536 {
21537 rtx temp;
21539 {
21556 }
21558 OPTAB_DIRECT);
21561 }
21571 }
21573 /* Expand a signed/unsigned integral vector conditional move. */
21575 bool
21577 {
21587 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21588 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21597 {
21601 {
21607 }
21610 {
21616 }
21617 }
21626 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21630 ;
21631 else
21632 {
21633 /* Canonicalize the comparison to EQ, GT, GTU. */
21635 {
21652 /* FALLTHRU */
21662 }
21664 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21666 {
21668 {
21670 /* SSE4.1 supports EQ. */
21677 /* SSE4.2 supports GT/GTU. */
21684 }
21685 }
21687 /* Unsigned parallel compare is not supported by the hardware.
21688 Play some tricks to turn this into a signed comparison
21689 against 0. */
21691 {
21695 {
21702 {
21707 {
21716 }
21717 /* Subtract (-(INT MAX) - 1) from both operands to make
21718 them signed. */
21729 }
21738 /* Perform a parallel unsigned saturating subtraction. */
21751 }
21752 }
21753 }
21755 /* Allow the comparison to be done in one mode, but the movcc to
21756 happen in another mode. */
21758 {
21761 }
21762 else
21763 {
21769 }
21774 }
21776 /* AVX512F does support 64-byte integer vector operations,
21777 thus the longest vector we are faced with is V64QImode. */
21778 #define MAX_VECT_LEN 64
21780 struct expand_vec_perm_d
21781 {
21784 machine_mode vmode;
21788 };
21790 static bool
21793 {
21794 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21795 expander, so args are either in d, or in op0, op1 etc. */
21801 {
21828 {
21831 }
21835 {
21838 }
21842 {
21845 }
21861 {
21864 }
21868 {
21871 }
21875 {
21878 }
21882 }
21887 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21888 expander, so args are either in d, or in op0, op1 etc. */
21890 {
21898 }
21902 }
21904 /* Expand a variable vector permutation. */
21906 void
21908 {
21919 /* Number of elements in the vector. */
21928 {
21930 {
21931 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21932 an constant shuffle operand. With a tiny bit of effort we can
21933 use VPERMD instead. A re-interpretation stall for V4DFmode is
21934 unfortunate but there's no avoiding it.
21935 Similarly for V16HImode we don't have instructions for variable
21936 shuffling, while for V32QImode we can use after preparing suitable
21937 masks vpshufb; vpshufb; vpermq; vpor. */
21940 {
21944 }
21945 else
21946 {
21950 }
21953 /* Replicate the low bits of the V4DImode mask into V8SImode:
21954 mask = { A B C D }
21955 t1 = { A A B B C C D D }. */
21963 else
21966 /* Multiply the shuffle indicies by two. */
21968 OPTAB_DIRECT);
21970 /* Add one to the odd shuffle indicies:
21971 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21973 {
21976 }
21980 OPTAB_DIRECT);
21982 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
21987 }
21990 {
21992 /* The VPERMD and VPERMPS instructions already properly ignore
21993 the high bits of the shuffle elements. No need for us to
21994 perform an AND ourselves. */
21996 {
22001 }
22002 else
22003 {
22009 }
22016 else
22017 {
22023 }
22027 /* By combining the two 128-bit input vectors into one 256-bit
22028 input vector, we can use VPERMD and VPERMPS for the full
22029 two-operand shuffle. */
22061 /* From mask create two adjusted masks, which contain the same
22062 bits as mask in the low 7 bits of each vector element.
22063 The first mask will have the most significant bit clear
22064 if it requests element from the same 128-bit lane
22065 and MSB set if it requests element from the other 128-bit lane.
22066 The second mask will have the opposite values of the MSB,
22067 and additionally will have its 128-bit lanes swapped.
22068 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22069 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22070 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22071 stands for other 12 bytes. */
22072 /* The bit whether element is from the same lane or the other
22073 lane is bit 4, so shift it up by 3 to the MSB position. */
22077 /* Clear MSB bits from the mask just in case it had them set. */
22079 /* After this t1 will have MSB set for elements from other lane. */
22081 /* Clear bits other than MSB. */
22083 /* Or in the lower bits from mask into t3. */
22085 /* And invert MSB bits in t1, so MSB is set for elements from the same
22086 lane. */
22088 /* Swap 128-bit lanes in t3. */
22093 /* And or in the lower bits from mask into t1. */
22096 {
22097 /* Each of these shuffles will put 0s in places where
22098 element from the other 128-bit lane is needed, otherwise
22099 will shuffle in the requested value. */
22103 /* For t3 the 128-bit lanes are swapped again. */
22108 /* And oring both together leads to the result. */
22115 }
22118 /* Similarly to the above one_operand_shuffle code,
22119 just for repeated twice for each operand. merge_two:
22120 code will merge the two results together. */
22144 }
22145 }
22148 {
22149 /* The XOP VPPERM insn supports three inputs. By ignoring the
22150 one_operand_shuffle special case, we avoid creating another
22151 set of constant vectors in memory. */
22154 /* mask = mask & {2*w-1, ...} */
22156 }
22157 else
22158 {
22159 /* mask = mask & {w-1, ...} */
22161 }
22169 /* For non-QImode operations, convert the word permutation control
22170 into a byte permutation control. */
22172 {
22177 /* Convert mask to vector of chars. */
22180 /* Replicate each of the input bytes into byte positions:
22181 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22182 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22183 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22190 else
22193 /* Convert it into the byte positions by doing
22194 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22200 }
22202 /* The actual shuffle operations all operate on V16QImode. */
22207 {
22214 }
22216 {
22223 }
22224 else
22225 {
22229 /* Shuffle the two input vectors independently. */
22235 merge_two:
22236 /* Then merge them together. The key is whether any given control
22237 element contained a bit set that indicates the second word. */
22241 {
22242 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22243 more shuffle to convert the V2DI input mask into a V4SI
22244 input mask. At which point the masking that expand_int_vcond
22245 will work as desired. */
22253 }
22275 }
22276 }
22278 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22279 true if we should do zero extension, else sign extension. HIGH_P is
22280 true if we want the N/2 high elements, else the low elements. */
22282 void
22284 {
22286 rtx tmp;
22289 {
22295 {
22299 else
22302 extract
22308 else
22311 extract
22317 else
22320 extract
22326 else
22329 extract
22335 else
22338 extract
22344 else
22347 extract
22353 else
22359 else
22365 else
22370 }
22373 {
22376 }
22378 {
22379 /* Shift higher 8 bytes to lower 8 bytes. */
22384 }
22385 else
22389 }
22390 else
22391 {
22395 {
22399 else
22405 else
22411 else
22416 }
22420 else
22427 }
22428 }
22430 /* Expand conditional increment or decrement using adb/sbb instructions.
22431 The default case using setcc followed by the conditional move can be
22432 done by generic code. */
22433 bool
22435 {
22437 rtx flags;
22439 rtx compare_op;
22442 machine_mode mode;
22457 {
22460 }
22463 {
22467 reverse_condition_maybe_unordered
22469 else
22471 }
22475 /* Construct either adc or sbb insn. */
22477 {
22479 {
22494 }
22495 }
22496 else
22497 {
22499 {
22514 }
22515 }
22519 }
22522 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22523 but works for floating pointer parameters and nonoffsetable memories.
22524 For pushes, it returns just stack offsets; the values will be saved
22525 in the right order. Maximally three parts are generated. */
22527 static int
22529 {
22534 else
22540 /* Optimize constant pool reference to immediates. This is used by fp
22541 moves, that force all constants to memory to allow combining. */
22543 {
22547 }
22550 {
22551 /* The only non-offsetable memories we handle are pushes. */
22560 }
22563 {
22565 /* Caution: if we looked through a constant pool memory above,
22566 the operand may actually have a different mode now. That's
22567 ok, since we want to pun this all the way back to an integer. */
22571 }
22574 {
22577 else
22578 {
22582 {
22586 }
22588 {
22593 }
22595 {
22596 REAL_VALUE_TYPE r;
22601 {
22608 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22609 long double may not be 80-bit. */
22618 }
22621 }
22622 else
22624 }
22625 }
22626 else
22627 {
22631 {
22634 {
22638 }
22640 {
22644 }
22646 {
22647 REAL_VALUE_TYPE r;
22653 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22656 = gen_int_mode
22659 DImode);
22660 else
22667 = gen_int_mode
22670 DImode);
22671 else
22673 }
22674 else
22676 }
22677 }
22680 }
22682 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22683 Return false when normal moves are needed; true when all required
22684 insns have been emitted. Operands 2-4 contain the input values
22685 int the correct order; operands 5-7 contain the output values. */
22687 void
22689 {
22697 /* The DFmode expanders may ask us to move double.
22698 For 64bit target this is single move. By hiding the fact
22699 here we simplify i386.md splitters. */
22701 {
22702 /* Optimize constant pool reference to immediates. This is used by
22703 fp moves, that force all constants to memory to allow combining. */
22710 {
22713 }
22714 else
22719 }
22721 /* The only non-offsettable memory we handle is push. */
22724 else
22731 /* When emitting push, take care for source operands on the stack. */
22734 {
22737 /* Compensate for the stack decrement by 4. */
22742 /* src_base refers to the stack pointer and is
22743 automatically decreased by emitted push. */
22747 }
22749 /* We need to do copy in the right order in case an address register
22750 of the source overlaps the destination. */
22752 {
22753 rtx tmp;
22756 {
22760 collisions++;
22761 }
22763 /* Collision in the middle part can be handled by reordering. */
22765 {
22768 }
22772 {
22774 {
22777 }
22778 else
22779 {
22782 }
22783 }
22785 /* If there are more collisions, we can't handle it by reordering.
22786 Do an lea to the last part and use only one colliding move. */
22788 {
22789 rtx base;
22795 /* Handle the case when the last part isn't valid for lea.
22796 Happens in 64-bit mode storing the 12-byte XFmode. */
22803 {
22806 }
22807 }
22808 }
22811 {
22813 {
22815 {
22820 }
22822 {
22825 }
22826 }
22827 else
22828 {
22829 /* In 64bit mode we don't have 32bit push available. In case this is
22830 register, it is OK - we will just use larger counterpart. We also
22831 retype memory - these comes from attempt to avoid REX prefix on
22832 moving of second half of TFmode value. */
22834 {
22836 {
22847 }
22851 }
22852 }
22856 }
22858 /* Choose correct order to not overwrite the source before it is copied. */
22868 {
22870 {
22873 }
22874 }
22875 else
22876 {
22878 {
22881 }
22882 }
22884 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22886 {
22895 }
22901 }
22903 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22904 left shift by a constant, either using a single shift or
22905 a sequence of add instructions. */
22907 static void
22909 {
22915 {
22919 }
22920 else
22921 {
22924 }
22925 }
22927 void
22929 {
22938 {
22943 {
22949 }
22950 else
22951 {
22959 }
22961 }
22968 {
22969 /* Assuming we've chosen a QImode capable registers, then 1 << N
22970 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22972 {
22988 }
22990 /* Otherwise, we can get the same results by manually performing
22991 a bit extract operation on bit 5/6, and then performing the two
22992 shifts. The two methods of getting 0/1 into low/high are exactly
22993 the same size. Avoiding the shift in the bit extract case helps
22994 pentium4 a bit; no one else seems to care much either way. */
22995 else
22996 {
22997 machine_mode half_mode;
23001 HOST_WIDE_INT bits;
23002 rtx x;
23005 {
23011 }
23012 else
23013 {
23019 }
23023 else
23031 }
23036 }
23039 {
23040 /* For -1 << N, we can avoid the shld instruction, because we
23041 know that we're shifting 0...31/63 ones into a -1. */
23045 else
23047 }
23048 else
23049 {
23057 }
23062 {
23068 }
23069 else
23070 {
23075 }
23076 }
23078 void
23080 {
23090 {
23095 {
23101 }
23103 {
23112 }
23113 else
23114 {
23122 }
23123 }
23124 else
23125 {
23137 {
23145 scratch));
23146 }
23147 else
23148 {
23153 }
23154 }
23155 }
23157 void
23159 {
23169 {
23174 {
23181 }
23182 else
23183 {
23191 }
23192 }
23193 else
23194 {
23206 {
23212 scratch));
23213 }
23214 else
23215 {
23220 }
23221 }
23222 }
23224 /* Predict just emitted jump instruction to be taken with probability PROB. */
23225 static void
23227 {
23231 }
23233 /* Helper function for the string operations below. Dest VARIABLE whether
23234 it is aligned to VALUE bytes. If true, jump to the label. */
23237 {
23242 else
23248 else
23251 }
23253 /* Adjust COUNTER by the VALUE. */
23254 static void
23256 {
23261 }
23263 /* Zero extend possibly SImode EXP to Pmode register. */
23264 rtx
23266 {
23268 }
23270 /* Divide COUNTREG by SCALE. */
23271 static rtx
23273 {
23274 rtx sc;
23286 }
23288 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23289 DImode for constant loop counts. */
23291 static machine_mode
23293 {
23301 }
23303 /* Copy the address to a Pmode register. This is used for x32 to
23304 truncate DImode TLS address to a SImode register. */
23306 static rtx
23308 {
23311 else
23312 {
23315 }
23316 }
23318 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23319 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23320 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23321 memory by VALUE (supposed to be in MODE).
23323 The size is rounded down to whole number of chunk size moved at once.
23324 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23327 static void
23332 {
23339 rtx size;
23348 /* Those two should combine. */
23350 {
23354 }
23361 /* This assert could be relaxed - in this case we'll need to compute
23362 smallest power of two, containing in PIECE_SIZE_N and pass it to
23363 offset_address. */
23369 {
23373 /* When unrolling for chips that reorder memory reads and writes,
23374 we can save registers by using single temporary.
23375 Also using 4 temporaries is overkill in 32bit mode. */
23377 {
23379 {
23381 {
23382 destmem =
23384 srcmem =
23386 }
23388 }
23389 }
23390 else
23391 {
23395 {
23398 {
23399 srcmem =
23401 }
23403 }
23405 {
23407 {
23408 destmem =
23410 }
23412 }
23413 }
23414 }
23415 else
23417 {
23419 destmem =
23422 }
23432 {
23438 else
23440 }
23441 else
23449 {
23454 }
23456 }
23458 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23459 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23460 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23461 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23462 ORIG_VALUE is the original value passed to memset to fill the memory with.
23463 Other arguments have same meaning as for previous function. */
23465 static void
23468 rtx count,
23470 {
23471 rtx destexp;
23472 rtx srcexp;
23473 rtx countreg;
23474 HOST_WIDE_INT rounded_count;
23476 /* If possible, it is shorter to use rep movs.
23477 TODO: Maybe it is better to move this logic to decide_alg. */
23488 {
23492 }
23493 else
23496 {
23501 }
23506 {
23509 }
23510 else
23511 {
23515 {
23519 }
23520 else
23523 {
23528 }
23529 else
23530 {
23533 }
23536 }
23537 }
23539 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23540 DESTMEM.
23541 SRC is passed by pointer to be updated on return.
23542 Return value is updated DST. */
23543 static rtx
23545 HOST_WIDE_INT size_to_move)
23546 {
23549 machine_mode move_mode;
23552 /* Find the widest mode in which we could perform moves.
23553 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23554 it until move of such size is supported. */
23559 {
23563 }
23565 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23566 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23568 {
23573 {
23577 }
23578 }
23584 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23588 {
23589 /* We move from memory to memory, so we'll need to do it via
23590 a temporary register. */
23601 piece_size);
23603 piece_size);
23604 }
23606 /* Update DST and SRC rtx. */
23609 }
23611 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23612 static void
23615 {
23618 {
23623 /* For now MAX_SIZE should be a power of 2. This assert could be
23624 relaxed, but it'll require a bit more complicated epilogue
23625 expanding. */
23628 {
23631 }
23633 }
23635 {
23641 }
23643 /* When there are stringops, we can cheaply increase dest and src pointers.
23644 Otherwise we save code size by maintaining offset (zero is readily
23645 available from preceding rep operation) and using x86 addressing modes.
23646 */
23648 {
23650 {
23657 }
23659 {
23666 }
23668 {
23675 }
23676 }
23677 else
23678 {
23680 rtx tmp;
23683 {
23694 }
23696 {
23709 }
23711 {
23720 }
23721 }
23722 }
23724 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23725 with value PROMOTED_VAL.
23726 SRC is passed by pointer to be updated on return.
23727 Return value is updated DST. */
23728 static rtx
23730 HOST_WIDE_INT size_to_move)
23731 {
23734 machine_mode move_mode;
23737 /* Find the widest mode in which we could perform moves.
23738 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23739 it until move of such size is supported. */
23744 {
23747 }
23754 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23758 {
23760 {
23763 piece_size);
23765 }
23773 piece_size);
23774 }
23776 /* Update DST rtx. */
23778 }
23779 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23780 static void
23783 {
23784 count =
23790 }
23792 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23793 static void
23796 {
23797 rtx dest;
23800 {
23805 /* For now MAX_SIZE should be a power of 2. This assert could be
23806 relaxed, but it'll require a bit more complicated epilogue
23807 expanding. */
23810 {
23812 {
23815 else
23817 }
23818 }
23820 }
23822 {
23825 }
23827 {
23830 {
23835 }
23836 else
23837 {
23846 }
23849 }
23851 {
23854 {
23857 }
23858 else
23859 {
23864 }
23867 }
23869 {
23875 }
23877 {
23883 }
23885 {
23891 }
23892 }
23894 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23895 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23896 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23897 ignored.
23898 Return value is updated DESTMEM. */
23899 static rtx
23904 {
23907 {
23909 {
23912 {
23915 else
23917 }
23918 else
23924 }
23925 }
23927 }
23929 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23930 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23931 and jump to DONE_LABEL. */
23932 static void
23938 {
23941 rtx modesize;
23944 /* If we do not have vector value to copy, we must reduce size. */
23946 {
23948 {
23953 }
23954 else
23956 }
23957 else
23958 {
23959 /* Choose appropriate vector mode. */
23965 }
23970 {
23973 else
23974 {
23977 }
23979 }
23985 {
23989 }
23991 {
23994 else
23995 {
23998 }
24000 }
24006 }
24008 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24009 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24010 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24011 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24012 DONE_LABEL is a label after the whole copying sequence. The label is created
24013 on demand if *DONE_LABEL is NULL.
24014 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24015 bounds after the initial copies.
24017 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24018 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24019 we will dispatch to a library call for large blocks.
24021 In pseudocode we do:
24023 if (COUNT < SIZE)
24024 {
24025 Assume that SIZE is 4. Bigger sizes are handled analogously
24026 if (COUNT & 4)
24027 {
24028 copy 4 bytes from SRCPTR to DESTPTR
24029 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24030 goto done_label
24031 }
24032 if (!COUNT)
24033 goto done_label;
24034 copy 1 byte from SRCPTR to DESTPTR
24035 if (COUNT & 2)
24036 {
24037 copy 2 bytes from SRCPTR to DESTPTR
24038 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24039 }
24040 }
24041 else
24042 {
24043 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24044 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24046 OLD_DESPTR = DESTPTR;
24047 Align DESTPTR up to DESIRED_ALIGN
24048 SRCPTR += DESTPTR - OLD_DESTPTR
24049 COUNT -= DEST_PTR - OLD_DESTPTR
24050 if (DYNAMIC_CHECK)
24051 Round COUNT down to multiple of SIZE
24052 << optional caller supplied zero size guard is here >>
24053 << optional caller suppplied dynamic check is here >>
24054 << caller supplied main copy loop is here >>
24055 }
24056 done_label:
24057 */
24058 static void
24061 machine_mode mode,
24071 {
24074 rtx modesize;
24076 rtx mode_value;
24078 /* Chose proper value to copy. */
24081 else
24085 /* See if block is big or small, handle small blocks. */
24087 {
24098 /* Handle sizes > 3. */
24105 /* Nothing to copy? Jump to DONE_LABEL if so */
24109 /* Do a byte copy. */
24113 else
24114 {
24117 }
24119 /* Handle sizes 2 and 3. */
24126 else
24127 {
24132 }
24138 }
24139 else
24143 /* Start memcpy for COUNT >= SIZE. */
24145 {
24148 }
24150 /* Copy first desired_align bytes. */
24156 {
24159 else
24160 {
24163 }
24166 }
24169 /* Copy last SIZE bytes. */
24176 else
24177 {
24183 }
24185 {
24189 else
24190 {
24193 }
24194 }
24196 /* Align destination. */
24198 {
24202 /* Align destptr up, place it to new register. */
24209 /* See how many bytes we skipped. */
24213 /* Adjust srcptr and count. */
24219 /* We copied at most size + prolog_size. */
24222 else
24225 /* Our loops always round down the bock size, but for dispatch to library
24226 we need precise value. */
24230 }
24231 else
24232 {
24234 /* Decrease count, so we won't end up copying last word twice. */
24238 else
24242 }
24243 }
24246 /* This function is like the previous one, except here we know how many bytes
24247 need to be copied. That allows us to update alignment not only of DST, which
24248 is returned, but also of SRC, which is passed as a pointer for that
24249 reason. */
24250 static rtx
24255 {
24263 {
24267 }
24272 {
24274 {
24276 {
24279 else
24281 }
24282 else
24285 }
24286 }
24293 {
24299 {
24302 {
24306 }
24311 }
24315 }
24318 }
24320 /* Return true if ALG can be used in current context.
24321 Assume we expand memset if MEMSET is true. */
24322 static bool
24324 {
24329 /* Algorithms using the rep prefix want at least edi and ecx;
24330 additionally, memset wants eax and memcpy wants esi. Don't
24331 consider such algorithms if the user has appropriated those
24332 registers for their own purposes. */
24339 }
24341 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24342 static enum stringop_alg
24346 {
24357 /* Even if the string operation call is cold, we still might spend a lot
24358 of time processing large blocks. */
24364 else
24370 else
24373 /* See maximal size for user defined algorithm. */
24375 {
24382 }
24384 /* If expected size is not known but max size is small enough
24385 so inline version is a win, set expected size into
24386 the range. */
24391 /* If user specified the algorithm, honnor it if possible. */
24395 /* rep; movq or rep; movl is the smallest variant. */
24397 {
24402 else
24405 }
24406 /* Very tiny blocks are best handled via the loop, REP is expensive to
24407 setup. */
24411 {
24415 {
24416 /* We get here if the algorithms that were not libcall-based
24417 were rep-prefix based and we are unable to use rep prefixes
24418 based on global register usage. Break out of the loop and
24419 use the heuristic below. */
24423 {
24427 {
24430 }
24431 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24432 last non-libcall inline algorithm. */
24434 {
24435 /* When the current size is best to be copied by a libcall,
24436 but we are still forced to inline, run the heuristic below
24437 that will pick code for medium sized blocks. */
24439 {
24442 }
24444 }
24446 {
24449 }
24450 }
24451 }
24452 }
24453 /* When asked to inline the call anyway, try to pick meaningful choice.
24454 We look for maximal size of block that is faster to copy by hand and
24455 take blocks of at most of that size guessing that average size will
24456 be roughly half of the block.
24458 If this turns out to be bad, we might simply specify the preferred
24459 choice in ix86_costs. */
24463 {
24466 /* If there aren't any usable algorithms, then recursing on
24467 smaller sizes isn't going to find anything. Just return the
24468 simple byte-at-a-time copy loop. */
24470 {
24471 /* Pick something reasonable. */
24475 }
24485 }
24488 }
24490 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24491 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24492 static int
24496 machine_mode move_mode)
24497 {
24508 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24509 copying whole cacheline at once. */
24522 }
24525 /* Helper function for memcpy. For QImode value 0xXY produce
24526 0xXYXYXYXY of wide specified by MODE. This is essentially
24527 a * 0x10101010, but we can do slightly better than
24528 synth_mult by unwinding the sequence by hand on CPUs with
24529 slow multiply. */
24530 static rtx
24532 {
24534 rtx tmp;
24541 {
24549 }
24558 nops--;
24563 {
24567 OPTAB_DIRECT);
24568 }
24569 else
24570 {
24576 else
24578 else
24579 {
24582 reg =
24584 }
24594 }
24595 }
24597 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24598 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24599 alignment from ALIGN to DESIRED_ALIGN. */
24600 static rtx
24603 {
24604 rtx promoted_val;
24613 else
24617 }
24619 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24620 operations when profitable. The code depends upon architecture, block size
24621 and alignment, but always has one of the following overall structures:
24623 Aligned move sequence:
24625 1) Prologue guard: Conditional that jumps up to epilogues for small
24626 blocks that can be handled by epilogue alone. This is faster
24627 but also needed for correctness, since prologue assume the block
24628 is larger than the desired alignment.
24630 Optional dynamic check for size and libcall for large
24631 blocks is emitted here too, with -minline-stringops-dynamically.
24633 2) Prologue: copy first few bytes in order to get destination
24634 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24635 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24636 copied. We emit either a jump tree on power of two sized
24637 blocks, or a byte loop.
24639 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24640 with specified algorithm.
24642 4) Epilogue: code copying tail of the block that is too small to be
24643 handled by main body (or up to size guarded by prologue guard).
24645 Misaligned move sequence
24647 1) missaligned move prologue/epilogue containing:
24648 a) Prologue handling small memory blocks and jumping to done_label
24649 (skipped if blocks are known to be large enough)
24650 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24651 needed by single possibly misaligned move
24652 (skipped if alignment is not needed)
24653 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24655 2) Zero size guard dispatching to done_label, if needed
24657 3) dispatch to library call, if needed,
24659 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24660 with specified algorithm. */
24661 bool
24667 {
24668 rtx destreg;
24671 rtx tmp;
24687 /* TODO: Once value ranges are available, fill in proper data. */
24695 /* i386 can do misaligned access on reasonably increased cost. */
24699 /* ALIGN is the minimum of destination and source alignment, but we care here
24700 just about destination alignment. */
24706 {
24709 /* When COUNT is 0, there is nothing to do. */
24712 }
24713 else
24714 {
24723 }
24725 /* Make sure we don't need to care about overflow later on. */
24729 /* Step 0: Decide on preferred algorithm, desired alignment and
24730 size of chunks to be copied by main loop. */
24732 issetmem,
24739 /* For now vector-version of memset is generated only for memory zeroing, as
24740 creating of promoted vector value is very cheap in this case. */
24753 {
24772 /* Find the widest supported mode. */
24778 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24779 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24781 {
24786 }
24798 }
24806 /* Step 1: Prologue guard. */
24808 /* Alignment code needs count to be in register. */
24810 {
24813 {
24814 align_bytes
24818 else
24820 }
24823 }
24826 /* Misaligned move sequences handle both prologue and epilogue at once.
24827 Default code generation results in a smaller code for large alignments
24828 and also avoids redundant job when sizes are known precisely. */
24829 misaligned_prologue_used
24830 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24836 /* Do the cheap promotion to allow better CSE across the
24837 main loop and epilogue (ie one load of the big constant in the
24838 front of all code.
24839 For now the misaligned move sequences do not have fast path
24840 without broadcasting. */
24842 {
24844 {
24850 }
24851 else
24852 {
24855 }
24856 }
24857 /* Misaligned move sequences handles both prologues and epilogues at once.
24858 Default code generation results in smaller code for large alignments and
24859 also avoids redundant job when sizes are known precisely. */
24861 {
24862 /* Misaligned move prologue handled small blocks by itself. */
24863 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24868 desired_align < align
24877 {
24878 /* It is possible that we copied enough so the main loop will not
24879 execute. */
24889 else
24891 }
24892 }
24893 /* Ensure that alignment prologue won't copy past end of block. */
24895 {
24897 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24898 Make sure it is power of 2. */
24901 /* To improve performance of small blocks, we jump around the VAL
24902 promoting mode. This mean that if the promoted VAL is not constant,
24903 we might not use it in the epilogue and have to use byte
24904 loop variant. */
24909 {
24910 /* If main algorithm works on QImode, no epilogue is needed.
24911 For small sizes just don't align anything. */
24914 else
24916 }
24919 {
24926 else
24928 }
24929 }
24931 /* Emit code to decide on runtime whether library call or inline should be
24932 used. */
24934 {
24936 {
24938 {
24942 }
24943 }
24944 else
24945 {
24955 else
24959 }
24960 }
24962 /* Step 2: Alignment prologue. */
24963 /* Do the expensive promotion once we branched off the small blocks. */
24969 {
24971 {
24972 /* Except for the first move in prologue, we no longer know
24973 constant offset in aliasing info. It don't seems to worth
24974 the pain to maintain it for the first move, so throw away
24975 the info early. */
24982 issetmem);
24983 /* At most desired_align - align bytes are copied. */
24986 else
24988 }
24989 else
24990 {
24991 /* If we know how many bytes need to be stored before dst is
24992 sufficiently aligned, maintain aliasing info accurately. */
24994 srcreg,
24995 promoted_val,
24996 vec_promoted_val,
24997 desired_align,
24998 align_bytes,
24999 issetmem);
25006 }
25008 && !min_size
25013 {
25014 /* It is possible that we copied enough so the main loop will not
25015 execute. */
25025 else
25027 }
25028 }
25030 {
25037 }
25041 /* Step 3: Main loop. */
25044 {
25067 }
25068 /* Adjust properly the offset of src and dest memory for aliasing. */
25070 {
25076 }
25077 else
25078 {
25082 }
25084 /* Step 4: Epilogue to copy the remaining bytes. */
25085 epilogue:
25087 {
25088 /* When the main loop is done, COUNT_EXP might hold original count,
25089 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25090 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25091 bytes. Compensate if needed. */
25094 {
25095 tmp =
25098 OPTAB_DIRECT);
25101 }
25104 }
25107 {
25110 epilogue_size_needed);
25111 else
25112 {
25116 epilogue_size_needed);
25117 else
25119 epilogue_size_needed);
25120 }
25121 }
25125 }
25128 /* Expand the appropriate insns for doing strlen if not just doing
25129 repnz; scasb
25131 out = result, initialized with the start address
25132 align_rtx = alignment of the address.
25133 scratch = scratch register, initialized with the startaddress when
25134 not aligned, otherwise undefined
25136 This is just the body. It needs the initializations mentioned above and
25137 some address computing at the end. These things are done in i386.md. */
25139 static void
25141 {
25143 rtx tmp;
25148 rtx mem;
25151 rtx cmp;
25157 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25159 /* Is there a known alignment and is it less than 4? */
25161 {
25164 /* Is there a known alignment and is it not 2? */
25166 {
25170 /* Leave just the 3 lower bits. */
25180 }
25181 else
25182 {
25183 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25184 check if is aligned to 4 - byte. */
25191 }
25195 /* Now compare the bytes. */
25197 /* Compare the first n unaligned byte on a byte per byte basis. */
25201 /* Increment the address. */
25204 /* Not needed with an alignment of 2 */
25206 {
25210 end_0_label);
25215 }
25218 end_0_label);
25221 }
25223 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25224 align this loop. It gives only huge programs, but does not help to
25225 speed up. */
25232 /* This formula yields a nonzero result iff one of the bytes is zero.
25233 This saves three branches inside loop and many cycles. */
25241 align_4_label);
25244 {
25250 /* If zero is not in the first two bytes, move two bytes forward. */
25256 reg,
25257 tmpreg)));
25258 /* Emit lea manually to avoid clobbering of flags. */
25266 reg2,
25267 out)));
25268 }
25269 else
25270 {
25272 /* Is zero in the first two bytes? */
25279 pc_rtx);
25283 /* Not in the first two. Move two bytes forward. */
25289 }
25291 /* Avoid branch in fixing the byte. */
25299 }
25301 /* Expand strlen. */
25303 bool
25305 {
25308 /* The generic case of strlen expander is long. Avoid it's
25309 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25312 && !TARGET_INLINE_ALL_STRINGOPS
25322 {
25323 /* Well it seems that some optimizer does not combine a call like
25324 foo(strlen(bar), strlen(bar));
25325 when the move and the subtraction is done here. It does calculate
25326 the length just once when these instructions are done inside of
25327 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25328 often used and I use one fewer register for the lifetime of
25329 output_strlen_unroll() this is better. */
25335 /* strlensi_unroll_1 returns the address of the zero at the end of
25336 the string, like memchr(), so compute the length by subtracting
25337 the start address. */
25339 }
25340 else
25341 {
25342 rtx unspec;
25344 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25357 /* If .md starts supporting :P, this can be done in .md. */
25363 }
25365 }
25367 /* For given symbol (function) construct code to compute address of it's PLT
25368 entry in large x86-64 PIC model. */
25369 static rtx
25371 {
25384 }
25386 rtx
25388 rtx callarg2,
25390 {
25400 {
25401 #if TARGET_MACHO
25404 #endif
25405 }
25406 else
25407 {
25408 /* Static functions and indirect calls don't need the pic register. */
25410 && (!TARGET_64BIT
25415 {
25419 pic_offset_table_rtx);
25420 }
25421 }
25424 {
25428 }
25431 && !TARGET_PECOFF
25439 {
25442 }
25447 {
25448 /* We should add bounds as destination register in case
25449 pointer with bounds may be returned. */
25451 {
25456 }
25459 }
25463 {
25467 }
25471 {
25472 int const cregs_size
25477 {
25482 }
25483 }
25492 }
25494 /* Output the assembly for a call instruction. */
25498 {
25504 {
25507 /* SEH epilogue detection requires the indirect branch case
25508 to include REX.W. */
25511 else
25516 }
25518 /* SEH unwinding can require an extra nop to be emitted in several
25519 circumstances. Determine if we have one of those. */
25521 {
25525 {
25526 /* If we get to another real insn, we don't need the nop. */
25530 /* If we get to the epilogue note, prevent a catch region from
25531 being adjacent to the standard epilogue sequence. If non-
25532 call-exceptions, we'll have done this during epilogue emission. */
25534 && !flag_non_call_exceptions
25536 {
25539 }
25540 }
25542 /* If we didn't find a real insn following the call, prevent the
25543 unwinder from looking into the next function. */
25546 }
25550 else
25559 }
25560 \f
25561 /* Clear stack slot assignments remembered from previous functions.
25562 This is called from INIT_EXPANDERS once before RTL is emitted for each
25563 function. */
25567 {
25575 }
25577 /* Return a MEM corresponding to a stack slot with mode MODE.
25578 Allocate a new slot if necessary.
25580 The RTL for a function can have several slots available: N is
25581 which slot to use. */
25583 rtx
25585 {
25602 }
25604 static void
25606 {
25612 }
25613 \f
25614 /* Check whether x86 address PARTS is a pc-relative address. */
25616 static bool
25618 {
25626 {
25628 {
25645 }
25646 }
25648 }
25650 /* Calculate the length of the memory address in the instruction encoding.
25651 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25652 or other prefixes. We never generate addr32 prefix for LEA insn. */
25654 int
25656 {
25673 /* If this is not LEA instruction, add the length of addr32 prefix. */
25678 len++;
25692 /* Rule of thumb:
25693 - esp as the base always wants an index,
25694 - ebp as the base always wants a displacement,
25695 - r12 as the base always wants an index,
25696 - r13 as the base always wants a displacement. */
25698 /* Register Indirect. */
25700 {
25701 /* esp (for its index) and ebp (for its displacement) need
25702 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25703 code. */
25710 len++;
25711 }
25713 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25714 is not disp32, but disp32(%rip), so for disp32
25715 SIB byte is needed, unless print_operand_address
25716 optimizes it into disp32(%rip) or (%rip) is implied
25717 by UNSPEC. */
25719 {
25722 len++;
25723 }
25724 else
25725 {
25726 /* Find the length of the displacement constant. */
25728 {
25731 else
25733 }
25734 /* ebp always wants a displacement. Similarly r13. */
25736 len++;
25738 /* An index requires the two-byte modrm form.... */
25740 /* ...like esp (or r12), which always wants an index. */
25744 len++;
25745 }
25748 }
25750 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25751 is set, expect that insn have 8bit immediate alternative. */
25752 int
25754 {
25760 {
25765 {
25768 {
25780 }
25782 {
25785 }
25786 }
25788 {
25798 /* Immediates for DImode instructions are encoded
25799 as 32bit sign extended values. */
25805 }
25806 }
25808 }
25810 /* Compute default value for "length_address" attribute. */
25811 int
25813 {
25817 {
25828 }
25833 {
25836 {
25841 constraints++;
25844 ;
25845 /* Skip ignored operands. */
25848 }
25850 }
25852 }
25854 /* Compute default value for "length_vex" attribute. It includes
25855 2 or 3 byte VEX prefix and 1 opcode byte. */
25857 int
25860 {
25863 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25864 byte VEX prefix. */
25868 /* We can always use 2 byte VEX prefix in 32bit. */
25876 {
25877 /* REX.W bit uses 3 byte VEX prefix. */
25881 }
25882 else
25883 {
25884 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25888 }
25891 }
25892 \f
25893 /* Return the maximum number of instructions a cpu can issue. */
25895 static int
25897 {
25899 {
25930 }
25931 }
25933 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25934 by DEP_INSN and nothing set by DEP_INSN. */
25936 static bool
25938 {
25941 /* Simplify the test for uninteresting insns. */
25949 {
25952 }
25957 {
25960 }
25961 else
25967 /* This test is true if the dependent insn reads the flags but
25968 not any other potentially set register. */
25976 }
25978 /* Return true iff USE_INSN has a memory address with operands set by
25979 SET_INSN. */
25981 bool
25983 {
25988 {
25991 }
25993 }
25995 /* Helper function for exact_store_load_dependency.
25996 Return true if addr is found in insn. */
25997 static bool
25999 {
26006 {
26012 CASE_CONST_ANY:
26021 }
26025 {
26027 {
26037 }
26038 }
26040 }
26042 /* Return true if there exists exact dependency for store & load, i.e.
26043 the same memory address is used in them. */
26044 static bool
26046 {
26060 }
26062 static int
26064 {
26070 /* Anti and output dependencies have zero cost on all CPUs. */
26076 /* If we can't recognize the insns, we can't really do anything. */
26084 {
26086 /* Address Generation Interlock adds a cycle of latency. */
26088 {
26099 }
26103 /* ??? Compares pair with jump/setcc. */
26107 /* Floating point stores require value to be ready one cycle earlier. */
26115 /* INT->FP conversion is expensive. */
26119 /* There is one cycle extra latency between an FP op and a store. */
26129 /* Show ability of reorder buffer to hide latency of load by executing
26130 in parallel with previous instruction in case
26131 previous instruction is not needed to compute the address. */
26134 {
26135 /* Claim moves to take one cycle, as core can issue one load
26136 at time and the next load can start cycle later. */
26141 cost--;
26142 }
26146 /* The esp dependency is resolved before
26147 the instruction is really finished. */
26152 /* INT->FP conversion is expensive. */
26158 /* Show ability of reorder buffer to hide latency of load by executing
26159 in parallel with previous instruction in case
26160 previous instruction is not needed to compute the address. */
26163 {
26164 /* Claim moves to take one cycle, as core can issue one load
26165 at time and the next load can start cycle later. */
26171 else
26173 }
26184 /* Stack engine allows to execute push&pop instructions in parall. */
26188 /* FALLTHRU */
26194 /* Show ability of reorder buffer to hide latency of load by executing
26195 in parallel with previous instruction in case
26196 previous instruction is not needed to compute the address. */
26199 {
26203 /* Because of the difference between the length of integer and
26204 floating unit pipeline preparation stages, the memory operands
26205 for floating point are cheaper.
26207 ??? For Athlon it the difference is most probably 2. */
26210 else
26215 else
26217 }
26224 /* Stack engine allows to execute push&pop instructions in parall. */
26231 /* Show ability of reorder buffer to hide latency of load by executing
26232 in parallel with previous instruction in case
26233 previous instruction is not needed to compute the address. */
26236 {
26239 else
26241 }
26249 /* Increase cost of integer loads. */
26252 {
26255 {
26258 else
26259 {
26260 /* Increase cost of ld/st for short int types only
26261 because of store forwarding issue. */
26265 {
26266 /* Increase cost of store/load insn if exact
26267 dependence exists and it is load insn. */
26272 }
26273 }
26274 }
26275 }
26279 }
26282 }
26284 /* How many alternative schedules to try. This should be as wide as the
26285 scheduling freedom in the DFA, but no wider. Making this value too
26286 large results extra work for the scheduler. */
26288 static int
26290 {
26292 {
26304 /* We use lookahead value 4 for BD both before and after reload
26305 schedules. Plan is to have value 8 included for O3. */
26315 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26316 as many instructions can be executed on a cycle, i.e.,
26317 issue_rate. I wonder why tuning for many CPUs does not do this. */
26320 /* Don't use lookahead for pre-reload schedule to save compile time. */
26325 }
26326 }
26328 /* Return true if target platform supports macro-fusion. */
26330 static bool
26332 {
26334 }
26336 /* Check whether current microarchitecture support macro fusion
26337 for insn pair "CONDGEN + CONDJMP". Refer to
26338 "Intel Architectures Optimization Reference Manual". */
26340 static bool
26342 {
26363 {
26368 {
26372 else
26374 }
26375 }
26382 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26383 supported. */
26390 /* No fusion for RIP-relative address. */
26397 ix86_address parts;
26403 }
26408 /* Check whether conditional jump use Sign or Overflow Flags. */
26416 /* Return true for TYPE_TEST and TYPE_ICMP. */
26421 /* The following is the case that macro-fusion for alu + jmp. */
26425 /* No fusion for alu op with memory destination operand. */
26430 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26431 supported. */
26440 }
26442 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26443 execution. It is applied if
26444 (1) IMUL instruction is on the top of list;
26445 (2) There exists the only producer of independent IMUL instruction in
26446 ready list.
26447 Return index of IMUL producer if it was found and -1 otherwise. */
26448 static int
26450 {
26453 sd_iterator_def sd_it;
26454 dep_t dep;
26461 /* Check that IMUL instruction is on the top of ready list. */
26470 /* Search for producer of independent IMUL instruction. */
26472 {
26476 /* Skip IMUL instruction. */
26486 {
26487 rtx con;
26498 {
26499 sd_iterator_def sd_it1;
26500 dep_t dep1;
26501 /* Check if there is no other dependee for IMUL. */
26504 {
26505 rtx pro;
26511 }
26514 }
26515 }
26518 }
26520 }
26522 /* Try to find the best candidate on the top of ready list if two insns
26523 have the same priority - candidate is best if its dependees were
26524 scheduled earlier. Applied for Silvermont only.
26525 Return true if top 2 insns must be interchanged. */
26526 static bool
26528 {
26531 rtx set;
26532 sd_iterator_def sd_it;
26533 dep_t dep;
26536 #define INSN_TICK(INSN) (HID (INSN)->tick)
26557 {
26560 /* Determine winner more precise. */
26562 {
26563 rtx pro;
26569 }
26571 {
26572 rtx pro;
26578 }
26581 {
26582 /* Determine winner - load must win. */
26588 }
26590 }
26592 #undef INSN_TICK
26593 }
26595 /* Perform possible reodering of ready list for Atom/Silvermont only.
26596 Return issue rate. */
26597 static int
26600 {
26607 /* Set up issue rate. */
26610 /* Do reodering for BONNELL/SILVERMONT only. */
26614 /* Nothing to do if ready list contains only 1 instruction. */
26618 /* Do reodering for post-reload scheduler only. */
26623 {
26628 /* Put IMUL producer (ready[index]) at the top of ready list. */
26634 }
26636 {
26640 /* Swap 2 top elements of ready list. */
26644 }
26646 }
26648 static bool
26651 /* Returns true if lhs of insn is HW function argument register and set up
26652 is_spilled to true if it is likely spilled HW register. */
26653 static bool
26655 {
26656 rtx dst;
26660 /* Call instructions are not movable, ignore it. */
26671 {
26672 /* Is it likely spilled HW register? */
26677 }
26679 }
26681 /* Add output dependencies for chain of function adjacent arguments if only
26682 there is a move to likely spilled HW register. Return first argument
26683 if at least one dependence was added or NULL otherwise. */
26686 {
26694 /* Find nearest to call argument passing instruction. */
26696 {
26705 }
26709 {
26716 {
26719 }
26721 {
26722 /* Add output depdendence between two function arguments if chain
26723 of output arguments contains likely spilled HW registers. */
26727 }
26728 else
26730 }
26734 }
26736 /* Add output or anti dependency from insn to first_arg to restrict its code
26737 motion. */
26738 static void
26740 {
26741 rtx set;
26742 rtx tmp;
26749 {
26750 /* Add output dependency to the first function argument. */
26753 }
26754 /* Add anti dependency. */
26756 }
26758 /* Avoid cross block motion of function argument through adding dependency
26759 from the first non-jump instruction in bb. */
26760 static void
26762 {
26766 {
26768 {
26771 {
26774 }
26775 }
26779 }
26780 }
26782 /* Hook for pre-reload schedule - avoid motion of function arguments
26783 passed in likely spilled HW registers. */
26784 static void
26786 {
26795 {
26798 {
26799 /* Add dependee for first argument to predecessors if only
26800 region contains more than one block. */
26804 /* Skip trivial regions and region head blocks that can have
26805 predecessors outside of region. */
26807 {
26808 edge e;
26809 edge_iterator ei;
26811 /* Regions are SCCs with the exception of selective
26812 scheduling with pipelining of outer blocks enabled.
26813 So also check that immediate predecessors of a non-head
26814 block are in the same region. */
26816 {
26817 /* Avoid creating of loop-carried dependencies through
26818 using topological ordering in the region. */
26822 }
26823 }
26827 }
26828 }
26831 }
26833 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26834 HW registers to maximum, to schedule them at soon as possible. These are
26835 moves from function argument registers at the top of the function entry
26836 and moves from function return value registers after call. */
26837 static int
26839 {
26840 rtx set;
26850 {
26857 }
26860 }
26862 /* Model decoder of Core 2/i7.
26863 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26864 track the instruction fetch block boundaries and make sure that long
26865 (9+ bytes) instructions are assigned to D0. */
26867 /* Maximum length of an insn that can be handled by
26868 a secondary decoder unit. '8' for Core 2/i7. */
26871 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26872 '16' for Core 2/i7. */
26875 /* Maximum number of instructions decoder can handle per cycle.
26876 '6' for Core 2/i7. */
26880 ix86_first_cycle_multipass_data_t;
26882 const_ix86_first_cycle_multipass_data_t;
26884 /* A variable to store target state across calls to max_issue within
26885 one cycle. */
26889 /* Initialize DATA. */
26890 static void
26892 {
26893 ix86_first_cycle_multipass_data_t data
26900 }
26902 /* Advancing the cycle; reset ifetch block counts. */
26903 static void
26905 {
26912 }
26916 /* Filter out insns from ready_try that the core will not be able to issue
26917 on current cycle due to decoder. */
26918 static void
26919 core2i7_first_cycle_multipass_filter_ready_try
26922 {
26924 {
26935 (!first_cycle_insn_p
26937 /* ... or it would not fit into the ifetch block ... */
26939 /* ... or the decoder is full already ... */
26941 /* ... mask the insn out. */
26942 {
26947 }
26948 }
26949 }
26951 /* Prepare for a new round of multipass lookahead scheduling. */
26952 static void
26956 {
26957 ix86_first_cycle_multipass_data_t data
26959 const_ix86_first_cycle_multipass_data_t prev_data
26962 /* Restore the state from the end of the previous round. */
26966 /* Filter instructions that cannot be issued on current cycle due to
26967 decoder restrictions. */
26969 first_cycle_insn_p);
26970 }
26972 /* INSN is being issued in current solution. Account for its impact on
26973 the decoder model. */
26974 static void
26978 {
26979 ix86_first_cycle_multipass_data_t data
26981 const_ix86_first_cycle_multipass_data_t prev_data
26991 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
26993 {
26996 }
26998 {
27002 }
27005 /* Filter out insns from ready_try that the core will not be able to issue
27006 on current cycle due to decoder. */
27009 }
27011 /* Revert the effect on ready_try. */
27012 static void
27016 {
27017 const_ix86_first_cycle_multipass_data_t data
27020 sbitmap_iterator sbi;
27024 {
27026 }
27027 }
27029 /* Save the result of multipass lookahead scheduling for the next round. */
27030 static void
27032 {
27033 const_ix86_first_cycle_multipass_data_t data
27035 ix86_first_cycle_multipass_data_t next_data
27039 {
27042 }
27043 }
27045 /* Deallocate target data. */
27046 static void
27048 {
27049 ix86_first_cycle_multipass_data_t data
27053 {
27057 }
27058 }
27060 /* Prepare for scheduling pass. */
27061 static void
27063 {
27064 /* Install scheduling hooks for current CPU. Some of these hooks are used
27065 in time-critical parts of the scheduler, so we only set them up when
27066 they are actually used. */
27068 {
27073 /* Do not perform multipass scheduling for pre-reload schedule
27074 to save compile time. */
27076 {
27092 /* Set decoder parameters. */
27097 }
27098 /* ... Fall through ... */
27108 }
27109 }
27111 \f
27112 /* Compute the alignment given to a constant that is being placed in memory.
27113 EXP is the constant and ALIGN is the alignment that the object would
27114 ordinarily have.
27115 The value of this function is used instead of that alignment to align
27116 the object. */
27118 int
27120 {
27123 {
27128 }
27134 }
27136 /* Compute the alignment for a static variable.
27137 TYPE is the data type, and ALIGN is the alignment that
27138 the object would ordinarily have. The value of this function is used
27139 instead of that alignment to align the object. */
27141 int
27143 {
27144 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27145 for symbols from other compilation units or symbols that don't need
27146 to bind locally. In order to preserve some ABI compatibility with
27147 those compilers, ensure we don't decrease alignment from what we
27148 used to assume. */
27150 int max_align_compat
27153 /* A data structure, equal or greater than the size of a cache line
27154 (64 bytes in the Pentium 4 and other recent Intel processors, including
27155 processors based on Intel Core microarchitecture) should be aligned
27156 so that its base address is a multiple of a cache line size. */
27158 int max_align
27168 {
27175 }
27177 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27178 to 16byte boundary. */
27180 {
27187 }
27193 {
27198 }
27200 {
27207 }
27212 {
27217 }
27220 {
27225 }
27228 }
27230 /* Compute the alignment for a local variable or a stack slot. EXP is
27231 the data type or decl itself, MODE is the widest mode available and
27232 ALIGN is the alignment that the object would ordinarily have. The
27233 value of this macro is used instead of that alignment to align the
27234 object. */
27236 unsigned int
27239 {
27243 {
27246 }
27247 else
27248 {
27251 }
27253 /* Don't do dynamic stack realignment for long long objects with
27254 -mpreferred-stack-boundary=2. */
27263 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27264 register in MODE. We will return the largest alignment of XF
27265 and DF. */
27267 {
27271 }
27273 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27274 to 16byte boundary. Exact wording is:
27276 An array uses the same alignment as its elements, except that a local or
27277 global array variable of length at least 16 bytes or
27278 a C99 variable-length array variable always has alignment of at least 16 bytes.
27280 This was added to allow use of aligned SSE instructions at arrays. This
27281 rule is meant for static storage (where compiler can not do the analysis
27282 by itself). We follow it for automatic variables only when convenient.
27283 We fully control everything in the function compiled and functions from
27284 other unit can not rely on the alignment.
27286 Exclude va_list type. It is the common case of local array where
27287 we can not benefit from the alignment.
27289 TODO: Probably one should optimize for size only when var is not escaping. */
27292 {
27302 }
27304 {
27309 }
27311 {
27317 }
27322 {
27327 }
27330 {
27336 }
27338 }
27340 /* Compute the minimum required alignment for dynamic stack realignment
27341 purposes for a local variable, parameter or a stack slot. EXP is
27342 the data type or decl itself, MODE is its mode and ALIGN is the
27343 alignment that the object would ordinarily have. */
27345 unsigned int
27348 {
27352 {
27355 }
27356 else
27357 {
27360 }
27365 /* Don't do dynamic stack realignment for long long objects with
27366 -mpreferred-stack-boundary=2. */
27373 }
27374 \f
27375 /* Find a location for the static chain incoming to a nested function.
27376 This is a register, unless all free registers are used by arguments. */
27378 static rtx
27380 {
27383 /* While this function won't be called by the middle-end when a static
27384 chain isn't needed, it's also used throughout the backend so it's
27385 easiest to keep this check centralized. */
27390 {
27391 /* We always use R10 in 64-bit mode. */
27393 }
27394 else
27395 {
27399 /* By default in 32-bit mode we use ECX to pass the static chain. */
27403 {
27406 }
27407 else
27408 {
27411 }
27415 {
27416 /* Fastcall functions use ecx/edx for arguments, which leaves
27417 us with EAX for the static chain.
27418 Thiscall functions use ecx for arguments, which also
27419 leaves us with EAX for the static chain. */
27421 }
27423 {
27424 /* Thiscall functions use ecx for arguments, which leaves
27425 us with EAX and EDX for the static chain.
27426 We are using for abi-compatibility EAX. */
27428 }
27430 {
27431 /* For regparm 3, we have no free call-clobbered registers in
27432 which to store the static chain. In order to implement this,
27433 we have the trampoline push the static chain to the stack.
27434 However, we can't push a value below the return address when
27435 we call the nested function directly, so we have to use an
27436 alternate entry point. For this we use ESI, and have the
27437 alternate entry point push ESI, so that things appear the
27438 same once we're executing the nested function. */
27440 {
27446 }
27448 }
27449 }
27452 }
27454 /* Emit RTL insns to initialize the variable parts of a trampoline.
27455 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27456 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27457 to be passed to the target function. */
27459 static void
27461 {
27469 {
27472 /* Load the function address to r11. Try to load address using
27473 the shorter movl instead of movabs. We may want to support
27474 movq for kernel mode, but kernel does not use trampolines at
27475 the moment. FNADDR is a 32bit address and may not be in
27476 DImode when ptr_mode == SImode. Always use movl in this
27477 case. */
27480 {
27489 }
27490 else
27491 {
27498 }
27500 /* Load static chain using movabs to r10. Use the shorter movl
27501 instead of movabs when ptr_mode == SImode. */
27503 {
27506 }
27507 else
27508 {
27511 }
27520 /* Jump to r11; the last (unused) byte is a nop, only there to
27521 pad the write out to a single 32-bit store. */
27525 }
27526 else
27527 {
27530 /* Depending on the static chain location, either load a register
27531 with a constant, or push the constant to the stack. All of the
27532 instructions are the same size. */
27535 {
27537 {
27544 }
27545 }
27546 else
27561 /* Compute offset from the end of the jmp to the target function.
27562 In the case in which the trampoline stores the static chain on
27563 the stack, we need to skip the first insn which pushes the
27564 (call-saved) register static chain; this push is 1 byte. */
27571 }
27575 #ifdef HAVE_ENABLE_EXECUTE_STACK
27576 #ifdef CHECK_EXECUTE_STACK_ENABLED
27578 #endif
27581 #endif
27582 }
27583 \f
27584 /* The following file contains several enumerations and data structures
27585 built from the definitions in i386-builtin-types.def. */
27589 /* Table for the ix86 builtin non-function types. */
27592 /* Retrieve an element from the above table, building some of
27593 the types lazily. */
27595 static tree
27597 {
27609 {
27610 machine_mode mode;
27617 }
27618 else
27619 {
27625 else
27633 }
27637 }
27639 /* Table for the ix86 builtin function types. */
27642 /* Retrieve an element from the above table, building some of
27643 the types lazily. */
27645 static tree
27647 {
27648 tree type;
27657 {
27665 {
27668 }
27671 }
27672 else
27673 {
27679 }
27683 }
27686 /* Codes for all the SSE/MMX builtins. */
27687 enum ix86_builtins
27688 {
27689 IX86_BUILTIN_ADDPS,
27690 IX86_BUILTIN_ADDSS,
27691 IX86_BUILTIN_DIVPS,
27692 IX86_BUILTIN_DIVSS,
27693 IX86_BUILTIN_MULPS,
27694 IX86_BUILTIN_MULSS,
27695 IX86_BUILTIN_SUBPS,
27696 IX86_BUILTIN_SUBSS,
27698 IX86_BUILTIN_CMPEQPS,
27699 IX86_BUILTIN_CMPLTPS,
27700 IX86_BUILTIN_CMPLEPS,
27701 IX86_BUILTIN_CMPGTPS,
27702 IX86_BUILTIN_CMPGEPS,
27703 IX86_BUILTIN_CMPNEQPS,
27704 IX86_BUILTIN_CMPNLTPS,
27705 IX86_BUILTIN_CMPNLEPS,
27706 IX86_BUILTIN_CMPNGTPS,
27707 IX86_BUILTIN_CMPNGEPS,
27708 IX86_BUILTIN_CMPORDPS,
27709 IX86_BUILTIN_CMPUNORDPS,
27710 IX86_BUILTIN_CMPEQSS,
27711 IX86_BUILTIN_CMPLTSS,
27712 IX86_BUILTIN_CMPLESS,
27713 IX86_BUILTIN_CMPNEQSS,
27714 IX86_BUILTIN_CMPNLTSS,
27715 IX86_BUILTIN_CMPNLESS,
27716 IX86_BUILTIN_CMPORDSS,
27717 IX86_BUILTIN_CMPUNORDSS,
27719 IX86_BUILTIN_COMIEQSS,
27720 IX86_BUILTIN_COMILTSS,
27721 IX86_BUILTIN_COMILESS,
27722 IX86_BUILTIN_COMIGTSS,
27723 IX86_BUILTIN_COMIGESS,
27724 IX86_BUILTIN_COMINEQSS,
27725 IX86_BUILTIN_UCOMIEQSS,
27726 IX86_BUILTIN_UCOMILTSS,
27727 IX86_BUILTIN_UCOMILESS,
27728 IX86_BUILTIN_UCOMIGTSS,
27729 IX86_BUILTIN_UCOMIGESS,
27730 IX86_BUILTIN_UCOMINEQSS,
27732 IX86_BUILTIN_CVTPI2PS,
27733 IX86_BUILTIN_CVTPS2PI,
27734 IX86_BUILTIN_CVTSI2SS,
27735 IX86_BUILTIN_CVTSI642SS,
27736 IX86_BUILTIN_CVTSS2SI,
27737 IX86_BUILTIN_CVTSS2SI64,
27738 IX86_BUILTIN_CVTTPS2PI,
27739 IX86_BUILTIN_CVTTSS2SI,
27740 IX86_BUILTIN_CVTTSS2SI64,
27742 IX86_BUILTIN_MAXPS,
27743 IX86_BUILTIN_MAXSS,
27744 IX86_BUILTIN_MINPS,
27745 IX86_BUILTIN_MINSS,
27747 IX86_BUILTIN_LOADUPS,
27748 IX86_BUILTIN_STOREUPS,
27749 IX86_BUILTIN_MOVSS,
27751 IX86_BUILTIN_MOVHLPS,
27752 IX86_BUILTIN_MOVLHPS,
27753 IX86_BUILTIN_LOADHPS,
27754 IX86_BUILTIN_LOADLPS,
27755 IX86_BUILTIN_STOREHPS,
27756 IX86_BUILTIN_STORELPS,
27758 IX86_BUILTIN_MASKMOVQ,
27759 IX86_BUILTIN_MOVMSKPS,
27760 IX86_BUILTIN_PMOVMSKB,
27762 IX86_BUILTIN_MOVNTPS,
27763 IX86_BUILTIN_MOVNTQ,
27765 IX86_BUILTIN_LOADDQU,
27766 IX86_BUILTIN_STOREDQU,
27768 IX86_BUILTIN_PACKSSWB,
27769 IX86_BUILTIN_PACKSSDW,
27770 IX86_BUILTIN_PACKUSWB,
27772 IX86_BUILTIN_PADDB,
27773 IX86_BUILTIN_PADDW,
27774 IX86_BUILTIN_PADDD,
27775 IX86_BUILTIN_PADDQ,
27776 IX86_BUILTIN_PADDSB,
27777 IX86_BUILTIN_PADDSW,
27778 IX86_BUILTIN_PADDUSB,
27779 IX86_BUILTIN_PADDUSW,
27780 IX86_BUILTIN_PSUBB,
27781 IX86_BUILTIN_PSUBW,
27782 IX86_BUILTIN_PSUBD,
27783 IX86_BUILTIN_PSUBQ,
27784 IX86_BUILTIN_PSUBSB,
27785 IX86_BUILTIN_PSUBSW,
27786 IX86_BUILTIN_PSUBUSB,
27787 IX86_BUILTIN_PSUBUSW,
27789 IX86_BUILTIN_PAND,
27790 IX86_BUILTIN_PANDN,
27791 IX86_BUILTIN_POR,
27792 IX86_BUILTIN_PXOR,
27794 IX86_BUILTIN_PAVGB,
27795 IX86_BUILTIN_PAVGW,
27797 IX86_BUILTIN_PCMPEQB,
27798 IX86_BUILTIN_PCMPEQW,
27799 IX86_BUILTIN_PCMPEQD,
27800 IX86_BUILTIN_PCMPGTB,
27801 IX86_BUILTIN_PCMPGTW,
27802 IX86_BUILTIN_PCMPGTD,
27804 IX86_BUILTIN_PMADDWD,
27806 IX86_BUILTIN_PMAXSW,
27807 IX86_BUILTIN_PMAXUB,
27808 IX86_BUILTIN_PMINSW,
27809 IX86_BUILTIN_PMINUB,
27811 IX86_BUILTIN_PMULHUW,
27812 IX86_BUILTIN_PMULHW,
27813 IX86_BUILTIN_PMULLW,
27815 IX86_BUILTIN_PSADBW,
27816 IX86_BUILTIN_PSHUFW,
27818 IX86_BUILTIN_PSLLW,
27819 IX86_BUILTIN_PSLLD,
27820 IX86_BUILTIN_PSLLQ,
27821 IX86_BUILTIN_PSRAW,
27822 IX86_BUILTIN_PSRAD,
27823 IX86_BUILTIN_PSRLW,
27824 IX86_BUILTIN_PSRLD,
27825 IX86_BUILTIN_PSRLQ,
27826 IX86_BUILTIN_PSLLWI,
27827 IX86_BUILTIN_PSLLDI,
27828 IX86_BUILTIN_PSLLQI,
27829 IX86_BUILTIN_PSRAWI,
27830 IX86_BUILTIN_PSRADI,
27831 IX86_BUILTIN_PSRLWI,
27832 IX86_BUILTIN_PSRLDI,
27833 IX86_BUILTIN_PSRLQI,
27835 IX86_BUILTIN_PUNPCKHBW,
27836 IX86_BUILTIN_PUNPCKHWD,
27837 IX86_BUILTIN_PUNPCKHDQ,
27838 IX86_BUILTIN_PUNPCKLBW,
27839 IX86_BUILTIN_PUNPCKLWD,
27840 IX86_BUILTIN_PUNPCKLDQ,
27842 IX86_BUILTIN_SHUFPS,
27844 IX86_BUILTIN_RCPPS,
27845 IX86_BUILTIN_RCPSS,
27846 IX86_BUILTIN_RSQRTPS,
27847 IX86_BUILTIN_RSQRTPS_NR,
27848 IX86_BUILTIN_RSQRTSS,
27849 IX86_BUILTIN_RSQRTF,
27850 IX86_BUILTIN_SQRTPS,
27851 IX86_BUILTIN_SQRTPS_NR,
27852 IX86_BUILTIN_SQRTSS,
27854 IX86_BUILTIN_UNPCKHPS,
27855 IX86_BUILTIN_UNPCKLPS,
27857 IX86_BUILTIN_ANDPS,
27858 IX86_BUILTIN_ANDNPS,
27859 IX86_BUILTIN_ORPS,
27860 IX86_BUILTIN_XORPS,
27862 IX86_BUILTIN_EMMS,
27863 IX86_BUILTIN_LDMXCSR,
27864 IX86_BUILTIN_STMXCSR,
27865 IX86_BUILTIN_SFENCE,
27867 IX86_BUILTIN_FXSAVE,
27868 IX86_BUILTIN_FXRSTOR,
27869 IX86_BUILTIN_FXSAVE64,
27870 IX86_BUILTIN_FXRSTOR64,
27872 IX86_BUILTIN_XSAVE,
27873 IX86_BUILTIN_XRSTOR,
27874 IX86_BUILTIN_XSAVE64,
27875 IX86_BUILTIN_XRSTOR64,
27877 IX86_BUILTIN_XSAVEOPT,
27878 IX86_BUILTIN_XSAVEOPT64,
27880 IX86_BUILTIN_XSAVEC,
27881 IX86_BUILTIN_XSAVEC64,
27883 IX86_BUILTIN_XSAVES,
27884 IX86_BUILTIN_XRSTORS,
27885 IX86_BUILTIN_XSAVES64,
27886 IX86_BUILTIN_XRSTORS64,
27888 /* 3DNow! Original */
27889 IX86_BUILTIN_FEMMS,
27890 IX86_BUILTIN_PAVGUSB,
27891 IX86_BUILTIN_PF2ID,
27892 IX86_BUILTIN_PFACC,
27893 IX86_BUILTIN_PFADD,
27894 IX86_BUILTIN_PFCMPEQ,
27895 IX86_BUILTIN_PFCMPGE,
27896 IX86_BUILTIN_PFCMPGT,
27897 IX86_BUILTIN_PFMAX,
27898 IX86_BUILTIN_PFMIN,
27899 IX86_BUILTIN_PFMUL,
27900 IX86_BUILTIN_PFRCP,
27901 IX86_BUILTIN_PFRCPIT1,
27902 IX86_BUILTIN_PFRCPIT2,
27903 IX86_BUILTIN_PFRSQIT1,
27904 IX86_BUILTIN_PFRSQRT,
27905 IX86_BUILTIN_PFSUB,
27906 IX86_BUILTIN_PFSUBR,
27907 IX86_BUILTIN_PI2FD,
27908 IX86_BUILTIN_PMULHRW,
27910 /* 3DNow! Athlon Extensions */
27911 IX86_BUILTIN_PF2IW,
27912 IX86_BUILTIN_PFNACC,
27913 IX86_BUILTIN_PFPNACC,
27914 IX86_BUILTIN_PI2FW,
27915 IX86_BUILTIN_PSWAPDSI,
27916 IX86_BUILTIN_PSWAPDSF,
27918 /* SSE2 */
27919 IX86_BUILTIN_ADDPD,
27920 IX86_BUILTIN_ADDSD,
27921 IX86_BUILTIN_DIVPD,
27922 IX86_BUILTIN_DIVSD,
27923 IX86_BUILTIN_MULPD,
27924 IX86_BUILTIN_MULSD,
27925 IX86_BUILTIN_SUBPD,
27926 IX86_BUILTIN_SUBSD,
27928 IX86_BUILTIN_CMPEQPD,
27929 IX86_BUILTIN_CMPLTPD,
27930 IX86_BUILTIN_CMPLEPD,
27931 IX86_BUILTIN_CMPGTPD,
27932 IX86_BUILTIN_CMPGEPD,
27933 IX86_BUILTIN_CMPNEQPD,
27934 IX86_BUILTIN_CMPNLTPD,
27935 IX86_BUILTIN_CMPNLEPD,
27936 IX86_BUILTIN_CMPNGTPD,
27937 IX86_BUILTIN_CMPNGEPD,
27938 IX86_BUILTIN_CMPORDPD,
27939 IX86_BUILTIN_CMPUNORDPD,
27940 IX86_BUILTIN_CMPEQSD,
27941 IX86_BUILTIN_CMPLTSD,
27942 IX86_BUILTIN_CMPLESD,
27943 IX86_BUILTIN_CMPNEQSD,
27944 IX86_BUILTIN_CMPNLTSD,
27945 IX86_BUILTIN_CMPNLESD,
27946 IX86_BUILTIN_CMPORDSD,
27947 IX86_BUILTIN_CMPUNORDSD,
27949 IX86_BUILTIN_COMIEQSD,
27950 IX86_BUILTIN_COMILTSD,
27951 IX86_BUILTIN_COMILESD,
27952 IX86_BUILTIN_COMIGTSD,
27953 IX86_BUILTIN_COMIGESD,
27954 IX86_BUILTIN_COMINEQSD,
27955 IX86_BUILTIN_UCOMIEQSD,
27956 IX86_BUILTIN_UCOMILTSD,
27957 IX86_BUILTIN_UCOMILESD,
27958 IX86_BUILTIN_UCOMIGTSD,
27959 IX86_BUILTIN_UCOMIGESD,
27960 IX86_BUILTIN_UCOMINEQSD,
27962 IX86_BUILTIN_MAXPD,
27963 IX86_BUILTIN_MAXSD,
27964 IX86_BUILTIN_MINPD,
27965 IX86_BUILTIN_MINSD,
27967 IX86_BUILTIN_ANDPD,
27968 IX86_BUILTIN_ANDNPD,
27969 IX86_BUILTIN_ORPD,
27970 IX86_BUILTIN_XORPD,
27972 IX86_BUILTIN_SQRTPD,
27973 IX86_BUILTIN_SQRTSD,
27975 IX86_BUILTIN_UNPCKHPD,
27976 IX86_BUILTIN_UNPCKLPD,
27978 IX86_BUILTIN_SHUFPD,
27980 IX86_BUILTIN_LOADUPD,
27981 IX86_BUILTIN_STOREUPD,
27982 IX86_BUILTIN_MOVSD,
27984 IX86_BUILTIN_LOADHPD,
27985 IX86_BUILTIN_LOADLPD,
27987 IX86_BUILTIN_CVTDQ2PD,
27988 IX86_BUILTIN_CVTDQ2PS,
27990 IX86_BUILTIN_CVTPD2DQ,
27991 IX86_BUILTIN_CVTPD2PI,
27992 IX86_BUILTIN_CVTPD2PS,
27993 IX86_BUILTIN_CVTTPD2DQ,
27994 IX86_BUILTIN_CVTTPD2PI,
27996 IX86_BUILTIN_CVTPI2PD,
27997 IX86_BUILTIN_CVTSI2SD,
27998 IX86_BUILTIN_CVTSI642SD,
28000 IX86_BUILTIN_CVTSD2SI,
28001 IX86_BUILTIN_CVTSD2SI64,
28002 IX86_BUILTIN_CVTSD2SS,
28003 IX86_BUILTIN_CVTSS2SD,
28004 IX86_BUILTIN_CVTTSD2SI,
28005 IX86_BUILTIN_CVTTSD2SI64,
28007 IX86_BUILTIN_CVTPS2DQ,
28008 IX86_BUILTIN_CVTPS2PD,
28009 IX86_BUILTIN_CVTTPS2DQ,
28011 IX86_BUILTIN_MOVNTI,
28012 IX86_BUILTIN_MOVNTI64,
28013 IX86_BUILTIN_MOVNTPD,
28014 IX86_BUILTIN_MOVNTDQ,
28016 IX86_BUILTIN_MOVQ128,
28018 /* SSE2 MMX */
28019 IX86_BUILTIN_MASKMOVDQU,
28020 IX86_BUILTIN_MOVMSKPD,
28021 IX86_BUILTIN_PMOVMSKB128,
28023 IX86_BUILTIN_PACKSSWB128,
28024 IX86_BUILTIN_PACKSSDW128,
28025 IX86_BUILTIN_PACKUSWB128,
28027 IX86_BUILTIN_PADDB128,
28028 IX86_BUILTIN_PADDW128,
28029 IX86_BUILTIN_PADDD128,
28030 IX86_BUILTIN_PADDQ128,
28031 IX86_BUILTIN_PADDSB128,
28032 IX86_BUILTIN_PADDSW128,
28033 IX86_BUILTIN_PADDUSB128,
28034 IX86_BUILTIN_PADDUSW128,
28035 IX86_BUILTIN_PSUBB128,
28036 IX86_BUILTIN_PSUBW128,
28037 IX86_BUILTIN_PSUBD128,
28038 IX86_BUILTIN_PSUBQ128,
28039 IX86_BUILTIN_PSUBSB128,
28040 IX86_BUILTIN_PSUBSW128,
28041 IX86_BUILTIN_PSUBUSB128,
28042 IX86_BUILTIN_PSUBUSW128,
28044 IX86_BUILTIN_PAND128,
28045 IX86_BUILTIN_PANDN128,
28046 IX86_BUILTIN_POR128,
28047 IX86_BUILTIN_PXOR128,
28049 IX86_BUILTIN_PAVGB128,
28050 IX86_BUILTIN_PAVGW128,
28052 IX86_BUILTIN_PCMPEQB128,
28053 IX86_BUILTIN_PCMPEQW128,
28054 IX86_BUILTIN_PCMPEQD128,
28055 IX86_BUILTIN_PCMPGTB128,
28056 IX86_BUILTIN_PCMPGTW128,
28057 IX86_BUILTIN_PCMPGTD128,
28059 IX86_BUILTIN_PMADDWD128,
28061 IX86_BUILTIN_PMAXSW128,
28062 IX86_BUILTIN_PMAXUB128,
28063 IX86_BUILTIN_PMINSW128,
28064 IX86_BUILTIN_PMINUB128,
28066 IX86_BUILTIN_PMULUDQ,
28067 IX86_BUILTIN_PMULUDQ128,
28068 IX86_BUILTIN_PMULHUW128,
28069 IX86_BUILTIN_PMULHW128,
28070 IX86_BUILTIN_PMULLW128,
28072 IX86_BUILTIN_PSADBW128,
28073 IX86_BUILTIN_PSHUFHW,
28074 IX86_BUILTIN_PSHUFLW,
28075 IX86_BUILTIN_PSHUFD,
28077 IX86_BUILTIN_PSLLDQI128,
28078 IX86_BUILTIN_PSLLWI128,
28079 IX86_BUILTIN_PSLLDI128,
28080 IX86_BUILTIN_PSLLQI128,
28081 IX86_BUILTIN_PSRAWI128,
28082 IX86_BUILTIN_PSRADI128,
28083 IX86_BUILTIN_PSRLDQI128,
28084 IX86_BUILTIN_PSRLWI128,
28085 IX86_BUILTIN_PSRLDI128,
28086 IX86_BUILTIN_PSRLQI128,
28088 IX86_BUILTIN_PSLLDQ128,
28089 IX86_BUILTIN_PSLLW128,
28090 IX86_BUILTIN_PSLLD128,
28091 IX86_BUILTIN_PSLLQ128,
28092 IX86_BUILTIN_PSRAW128,
28093 IX86_BUILTIN_PSRAD128,
28094 IX86_BUILTIN_PSRLW128,
28095 IX86_BUILTIN_PSRLD128,
28096 IX86_BUILTIN_PSRLQ128,
28098 IX86_BUILTIN_PUNPCKHBW128,
28099 IX86_BUILTIN_PUNPCKHWD128,
28100 IX86_BUILTIN_PUNPCKHDQ128,
28101 IX86_BUILTIN_PUNPCKHQDQ128,
28102 IX86_BUILTIN_PUNPCKLBW128,
28103 IX86_BUILTIN_PUNPCKLWD128,
28104 IX86_BUILTIN_PUNPCKLDQ128,
28105 IX86_BUILTIN_PUNPCKLQDQ128,
28107 IX86_BUILTIN_CLFLUSH,
28108 IX86_BUILTIN_MFENCE,
28109 IX86_BUILTIN_LFENCE,
28110 IX86_BUILTIN_PAUSE,
28112 IX86_BUILTIN_FNSTENV,
28113 IX86_BUILTIN_FLDENV,
28114 IX86_BUILTIN_FNSTSW,
28115 IX86_BUILTIN_FNCLEX,
28117 IX86_BUILTIN_BSRSI,
28118 IX86_BUILTIN_BSRDI,
28119 IX86_BUILTIN_RDPMC,
28120 IX86_BUILTIN_RDTSC,
28121 IX86_BUILTIN_RDTSCP,
28122 IX86_BUILTIN_ROLQI,
28123 IX86_BUILTIN_ROLHI,
28124 IX86_BUILTIN_RORQI,
28125 IX86_BUILTIN_RORHI,
28127 /* SSE3. */
28128 IX86_BUILTIN_ADDSUBPS,
28129 IX86_BUILTIN_HADDPS,
28130 IX86_BUILTIN_HSUBPS,
28131 IX86_BUILTIN_MOVSHDUP,
28132 IX86_BUILTIN_MOVSLDUP,
28133 IX86_BUILTIN_ADDSUBPD,
28134 IX86_BUILTIN_HADDPD,
28135 IX86_BUILTIN_HSUBPD,
28136 IX86_BUILTIN_LDDQU,
28138 IX86_BUILTIN_MONITOR,
28139 IX86_BUILTIN_MWAIT,
28141 /* SSSE3. */
28142 IX86_BUILTIN_PHADDW,
28143 IX86_BUILTIN_PHADDD,
28144 IX86_BUILTIN_PHADDSW,
28145 IX86_BUILTIN_PHSUBW,
28146 IX86_BUILTIN_PHSUBD,
28147 IX86_BUILTIN_PHSUBSW,
28148 IX86_BUILTIN_PMADDUBSW,
28149 IX86_BUILTIN_PMULHRSW,
28150 IX86_BUILTIN_PSHUFB,
28151 IX86_BUILTIN_PSIGNB,
28152 IX86_BUILTIN_PSIGNW,
28153 IX86_BUILTIN_PSIGND,
28154 IX86_BUILTIN_PALIGNR,
28155 IX86_BUILTIN_PABSB,
28156 IX86_BUILTIN_PABSW,
28157 IX86_BUILTIN_PABSD,
28159 IX86_BUILTIN_PHADDW128,
28160 IX86_BUILTIN_PHADDD128,
28161 IX86_BUILTIN_PHADDSW128,
28162 IX86_BUILTIN_PHSUBW128,
28163 IX86_BUILTIN_PHSUBD128,
28164 IX86_BUILTIN_PHSUBSW128,
28165 IX86_BUILTIN_PMADDUBSW128,
28166 IX86_BUILTIN_PMULHRSW128,
28167 IX86_BUILTIN_PSHUFB128,
28168 IX86_BUILTIN_PSIGNB128,
28169 IX86_BUILTIN_PSIGNW128,
28170 IX86_BUILTIN_PSIGND128,
28171 IX86_BUILTIN_PALIGNR128,
28172 IX86_BUILTIN_PABSB128,
28173 IX86_BUILTIN_PABSW128,
28174 IX86_BUILTIN_PABSD128,
28176 /* AMDFAM10 - SSE4A New Instructions. */
28177 IX86_BUILTIN_MOVNTSD,
28178 IX86_BUILTIN_MOVNTSS,
28179 IX86_BUILTIN_EXTRQI,
28180 IX86_BUILTIN_EXTRQ,
28181 IX86_BUILTIN_INSERTQI,
28182 IX86_BUILTIN_INSERTQ,
28184 /* SSE4.1. */
28185 IX86_BUILTIN_BLENDPD,
28186 IX86_BUILTIN_BLENDPS,
28187 IX86_BUILTIN_BLENDVPD,
28188 IX86_BUILTIN_BLENDVPS,
28189 IX86_BUILTIN_PBLENDVB128,
28190 IX86_BUILTIN_PBLENDW128,
28192 IX86_BUILTIN_DPPD,
28193 IX86_BUILTIN_DPPS,
28195 IX86_BUILTIN_INSERTPS128,
28197 IX86_BUILTIN_MOVNTDQA,
28198 IX86_BUILTIN_MPSADBW128,
28199 IX86_BUILTIN_PACKUSDW128,
28200 IX86_BUILTIN_PCMPEQQ,
28201 IX86_BUILTIN_PHMINPOSUW128,
28203 IX86_BUILTIN_PMAXSB128,
28204 IX86_BUILTIN_PMAXSD128,
28205 IX86_BUILTIN_PMAXUD128,
28206 IX86_BUILTIN_PMAXUW128,
28208 IX86_BUILTIN_PMINSB128,
28209 IX86_BUILTIN_PMINSD128,
28210 IX86_BUILTIN_PMINUD128,
28211 IX86_BUILTIN_PMINUW128,
28213 IX86_BUILTIN_PMOVSXBW128,
28214 IX86_BUILTIN_PMOVSXBD128,
28215 IX86_BUILTIN_PMOVSXBQ128,
28216 IX86_BUILTIN_PMOVSXWD128,
28217 IX86_BUILTIN_PMOVSXWQ128,
28218 IX86_BUILTIN_PMOVSXDQ128,
28220 IX86_BUILTIN_PMOVZXBW128,
28221 IX86_BUILTIN_PMOVZXBD128,
28222 IX86_BUILTIN_PMOVZXBQ128,
28223 IX86_BUILTIN_PMOVZXWD128,
28224 IX86_BUILTIN_PMOVZXWQ128,
28225 IX86_BUILTIN_PMOVZXDQ128,
28227 IX86_BUILTIN_PMULDQ128,
28228 IX86_BUILTIN_PMULLD128,
28230 IX86_BUILTIN_ROUNDSD,
28231 IX86_BUILTIN_ROUNDSS,
28233 IX86_BUILTIN_ROUNDPD,
28234 IX86_BUILTIN_ROUNDPS,
28236 IX86_BUILTIN_FLOORPD,
28237 IX86_BUILTIN_CEILPD,
28238 IX86_BUILTIN_TRUNCPD,
28239 IX86_BUILTIN_RINTPD,
28240 IX86_BUILTIN_ROUNDPD_AZ,
28242 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28243 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28244 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28246 IX86_BUILTIN_FLOORPS,
28247 IX86_BUILTIN_CEILPS,
28248 IX86_BUILTIN_TRUNCPS,
28249 IX86_BUILTIN_RINTPS,
28250 IX86_BUILTIN_ROUNDPS_AZ,
28252 IX86_BUILTIN_FLOORPS_SFIX,
28253 IX86_BUILTIN_CEILPS_SFIX,
28254 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28256 IX86_BUILTIN_PTESTZ,
28257 IX86_BUILTIN_PTESTC,
28258 IX86_BUILTIN_PTESTNZC,
28260 IX86_BUILTIN_VEC_INIT_V2SI,
28261 IX86_BUILTIN_VEC_INIT_V4HI,
28262 IX86_BUILTIN_VEC_INIT_V8QI,
28263 IX86_BUILTIN_VEC_EXT_V2DF,
28264 IX86_BUILTIN_VEC_EXT_V2DI,
28265 IX86_BUILTIN_VEC_EXT_V4SF,
28266 IX86_BUILTIN_VEC_EXT_V4SI,
28267 IX86_BUILTIN_VEC_EXT_V8HI,
28268 IX86_BUILTIN_VEC_EXT_V2SI,
28269 IX86_BUILTIN_VEC_EXT_V4HI,
28270 IX86_BUILTIN_VEC_EXT_V16QI,
28271 IX86_BUILTIN_VEC_SET_V2DI,
28272 IX86_BUILTIN_VEC_SET_V4SF,
28273 IX86_BUILTIN_VEC_SET_V4SI,
28274 IX86_BUILTIN_VEC_SET_V8HI,
28275 IX86_BUILTIN_VEC_SET_V4HI,
28276 IX86_BUILTIN_VEC_SET_V16QI,
28278 IX86_BUILTIN_VEC_PACK_SFIX,
28279 IX86_BUILTIN_VEC_PACK_SFIX256,
28281 /* SSE4.2. */
28282 IX86_BUILTIN_CRC32QI,
28283 IX86_BUILTIN_CRC32HI,
28284 IX86_BUILTIN_CRC32SI,
28285 IX86_BUILTIN_CRC32DI,
28287 IX86_BUILTIN_PCMPESTRI128,
28288 IX86_BUILTIN_PCMPESTRM128,
28289 IX86_BUILTIN_PCMPESTRA128,
28290 IX86_BUILTIN_PCMPESTRC128,
28291 IX86_BUILTIN_PCMPESTRO128,
28292 IX86_BUILTIN_PCMPESTRS128,
28293 IX86_BUILTIN_PCMPESTRZ128,
28294 IX86_BUILTIN_PCMPISTRI128,
28295 IX86_BUILTIN_PCMPISTRM128,
28296 IX86_BUILTIN_PCMPISTRA128,
28297 IX86_BUILTIN_PCMPISTRC128,
28298 IX86_BUILTIN_PCMPISTRO128,
28299 IX86_BUILTIN_PCMPISTRS128,
28300 IX86_BUILTIN_PCMPISTRZ128,
28302 IX86_BUILTIN_PCMPGTQ,
28304 /* AES instructions */
28305 IX86_BUILTIN_AESENC128,
28306 IX86_BUILTIN_AESENCLAST128,
28307 IX86_BUILTIN_AESDEC128,
28308 IX86_BUILTIN_AESDECLAST128,
28309 IX86_BUILTIN_AESIMC128,
28310 IX86_BUILTIN_AESKEYGENASSIST128,
28312 /* PCLMUL instruction */
28313 IX86_BUILTIN_PCLMULQDQ128,
28315 /* AVX */
28316 IX86_BUILTIN_ADDPD256,
28317 IX86_BUILTIN_ADDPS256,
28318 IX86_BUILTIN_ADDSUBPD256,
28319 IX86_BUILTIN_ADDSUBPS256,
28320 IX86_BUILTIN_ANDPD256,
28321 IX86_BUILTIN_ANDPS256,
28322 IX86_BUILTIN_ANDNPD256,
28323 IX86_BUILTIN_ANDNPS256,
28324 IX86_BUILTIN_BLENDPD256,
28325 IX86_BUILTIN_BLENDPS256,
28326 IX86_BUILTIN_BLENDVPD256,
28327 IX86_BUILTIN_BLENDVPS256,
28328 IX86_BUILTIN_DIVPD256,
28329 IX86_BUILTIN_DIVPS256,
28330 IX86_BUILTIN_DPPS256,
28331 IX86_BUILTIN_HADDPD256,
28332 IX86_BUILTIN_HADDPS256,
28333 IX86_BUILTIN_HSUBPD256,
28334 IX86_BUILTIN_HSUBPS256,
28335 IX86_BUILTIN_MAXPD256,
28336 IX86_BUILTIN_MAXPS256,
28337 IX86_BUILTIN_MINPD256,
28338 IX86_BUILTIN_MINPS256,
28339 IX86_BUILTIN_MULPD256,
28340 IX86_BUILTIN_MULPS256,
28341 IX86_BUILTIN_ORPD256,
28342 IX86_BUILTIN_ORPS256,
28343 IX86_BUILTIN_SHUFPD256,
28344 IX86_BUILTIN_SHUFPS256,
28345 IX86_BUILTIN_SUBPD256,
28346 IX86_BUILTIN_SUBPS256,
28347 IX86_BUILTIN_XORPD256,
28348 IX86_BUILTIN_XORPS256,
28349 IX86_BUILTIN_CMPSD,
28350 IX86_BUILTIN_CMPSS,
28351 IX86_BUILTIN_CMPPD,
28352 IX86_BUILTIN_CMPPS,
28353 IX86_BUILTIN_CMPPD256,
28354 IX86_BUILTIN_CMPPS256,
28355 IX86_BUILTIN_CVTDQ2PD256,
28356 IX86_BUILTIN_CVTDQ2PS256,
28357 IX86_BUILTIN_CVTPD2PS256,
28358 IX86_BUILTIN_CVTPS2DQ256,
28359 IX86_BUILTIN_CVTPS2PD256,
28360 IX86_BUILTIN_CVTTPD2DQ256,
28361 IX86_BUILTIN_CVTPD2DQ256,
28362 IX86_BUILTIN_CVTTPS2DQ256,
28363 IX86_BUILTIN_EXTRACTF128PD256,
28364 IX86_BUILTIN_EXTRACTF128PS256,
28365 IX86_BUILTIN_EXTRACTF128SI256,
28366 IX86_BUILTIN_VZEROALL,
28367 IX86_BUILTIN_VZEROUPPER,
28368 IX86_BUILTIN_VPERMILVARPD,
28369 IX86_BUILTIN_VPERMILVARPS,
28370 IX86_BUILTIN_VPERMILVARPD256,
28371 IX86_BUILTIN_VPERMILVARPS256,
28372 IX86_BUILTIN_VPERMILPD,
28373 IX86_BUILTIN_VPERMILPS,
28374 IX86_BUILTIN_VPERMILPD256,
28375 IX86_BUILTIN_VPERMILPS256,
28376 IX86_BUILTIN_VPERMIL2PD,
28377 IX86_BUILTIN_VPERMIL2PS,
28378 IX86_BUILTIN_VPERMIL2PD256,
28379 IX86_BUILTIN_VPERMIL2PS256,
28380 IX86_BUILTIN_VPERM2F128PD256,
28381 IX86_BUILTIN_VPERM2F128PS256,
28382 IX86_BUILTIN_VPERM2F128SI256,
28383 IX86_BUILTIN_VBROADCASTSS,
28384 IX86_BUILTIN_VBROADCASTSD256,
28385 IX86_BUILTIN_VBROADCASTSS256,
28386 IX86_BUILTIN_VBROADCASTPD256,
28387 IX86_BUILTIN_VBROADCASTPS256,
28388 IX86_BUILTIN_VINSERTF128PD256,
28389 IX86_BUILTIN_VINSERTF128PS256,
28390 IX86_BUILTIN_VINSERTF128SI256,
28391 IX86_BUILTIN_LOADUPD256,
28392 IX86_BUILTIN_LOADUPS256,
28393 IX86_BUILTIN_STOREUPD256,
28394 IX86_BUILTIN_STOREUPS256,
28395 IX86_BUILTIN_LDDQU256,
28396 IX86_BUILTIN_MOVNTDQ256,
28397 IX86_BUILTIN_MOVNTPD256,
28398 IX86_BUILTIN_MOVNTPS256,
28399 IX86_BUILTIN_LOADDQU256,
28400 IX86_BUILTIN_STOREDQU256,
28401 IX86_BUILTIN_MASKLOADPD,
28402 IX86_BUILTIN_MASKLOADPS,
28403 IX86_BUILTIN_MASKSTOREPD,
28404 IX86_BUILTIN_MASKSTOREPS,
28405 IX86_BUILTIN_MASKLOADPD256,
28406 IX86_BUILTIN_MASKLOADPS256,
28407 IX86_BUILTIN_MASKSTOREPD256,
28408 IX86_BUILTIN_MASKSTOREPS256,
28409 IX86_BUILTIN_MOVSHDUP256,
28410 IX86_BUILTIN_MOVSLDUP256,
28411 IX86_BUILTIN_MOVDDUP256,
28413 IX86_BUILTIN_SQRTPD256,
28414 IX86_BUILTIN_SQRTPS256,
28415 IX86_BUILTIN_SQRTPS_NR256,
28416 IX86_BUILTIN_RSQRTPS256,
28417 IX86_BUILTIN_RSQRTPS_NR256,
28419 IX86_BUILTIN_RCPPS256,
28421 IX86_BUILTIN_ROUNDPD256,
28422 IX86_BUILTIN_ROUNDPS256,
28424 IX86_BUILTIN_FLOORPD256,
28425 IX86_BUILTIN_CEILPD256,
28426 IX86_BUILTIN_TRUNCPD256,
28427 IX86_BUILTIN_RINTPD256,
28428 IX86_BUILTIN_ROUNDPD_AZ256,
28430 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28431 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28432 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28434 IX86_BUILTIN_FLOORPS256,
28435 IX86_BUILTIN_CEILPS256,
28436 IX86_BUILTIN_TRUNCPS256,
28437 IX86_BUILTIN_RINTPS256,
28438 IX86_BUILTIN_ROUNDPS_AZ256,
28440 IX86_BUILTIN_FLOORPS_SFIX256,
28441 IX86_BUILTIN_CEILPS_SFIX256,
28442 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28444 IX86_BUILTIN_UNPCKHPD256,
28445 IX86_BUILTIN_UNPCKLPD256,
28446 IX86_BUILTIN_UNPCKHPS256,
28447 IX86_BUILTIN_UNPCKLPS256,
28449 IX86_BUILTIN_SI256_SI,
28450 IX86_BUILTIN_PS256_PS,
28451 IX86_BUILTIN_PD256_PD,
28452 IX86_BUILTIN_SI_SI256,
28453 IX86_BUILTIN_PS_PS256,
28454 IX86_BUILTIN_PD_PD256,
28456 IX86_BUILTIN_VTESTZPD,
28457 IX86_BUILTIN_VTESTCPD,
28458 IX86_BUILTIN_VTESTNZCPD,
28459 IX86_BUILTIN_VTESTZPS,
28460 IX86_BUILTIN_VTESTCPS,
28461 IX86_BUILTIN_VTESTNZCPS,
28462 IX86_BUILTIN_VTESTZPD256,
28463 IX86_BUILTIN_VTESTCPD256,
28464 IX86_BUILTIN_VTESTNZCPD256,
28465 IX86_BUILTIN_VTESTZPS256,
28466 IX86_BUILTIN_VTESTCPS256,
28467 IX86_BUILTIN_VTESTNZCPS256,
28468 IX86_BUILTIN_PTESTZ256,
28469 IX86_BUILTIN_PTESTC256,
28470 IX86_BUILTIN_PTESTNZC256,
28472 IX86_BUILTIN_MOVMSKPD256,
28473 IX86_BUILTIN_MOVMSKPS256,
28475 /* AVX2 */
28476 IX86_BUILTIN_MPSADBW256,
28477 IX86_BUILTIN_PABSB256,
28478 IX86_BUILTIN_PABSW256,
28479 IX86_BUILTIN_PABSD256,
28480 IX86_BUILTIN_PACKSSDW256,
28481 IX86_BUILTIN_PACKSSWB256,
28482 IX86_BUILTIN_PACKUSDW256,
28483 IX86_BUILTIN_PACKUSWB256,
28484 IX86_BUILTIN_PADDB256,
28485 IX86_BUILTIN_PADDW256,
28486 IX86_BUILTIN_PADDD256,
28487 IX86_BUILTIN_PADDQ256,
28488 IX86_BUILTIN_PADDSB256,
28489 IX86_BUILTIN_PADDSW256,
28490 IX86_BUILTIN_PADDUSB256,
28491 IX86_BUILTIN_PADDUSW256,
28492 IX86_BUILTIN_PALIGNR256,
28493 IX86_BUILTIN_AND256I,
28494 IX86_BUILTIN_ANDNOT256I,
28495 IX86_BUILTIN_PAVGB256,
28496 IX86_BUILTIN_PAVGW256,
28497 IX86_BUILTIN_PBLENDVB256,
28498 IX86_BUILTIN_PBLENDVW256,
28499 IX86_BUILTIN_PCMPEQB256,
28500 IX86_BUILTIN_PCMPEQW256,
28501 IX86_BUILTIN_PCMPEQD256,
28502 IX86_BUILTIN_PCMPEQQ256,
28503 IX86_BUILTIN_PCMPGTB256,
28504 IX86_BUILTIN_PCMPGTW256,
28505 IX86_BUILTIN_PCMPGTD256,
28506 IX86_BUILTIN_PCMPGTQ256,
28507 IX86_BUILTIN_PHADDW256,
28508 IX86_BUILTIN_PHADDD256,
28509 IX86_BUILTIN_PHADDSW256,
28510 IX86_BUILTIN_PHSUBW256,
28511 IX86_BUILTIN_PHSUBD256,
28512 IX86_BUILTIN_PHSUBSW256,
28513 IX86_BUILTIN_PMADDUBSW256,
28514 IX86_BUILTIN_PMADDWD256,
28515 IX86_BUILTIN_PMAXSB256,
28516 IX86_BUILTIN_PMAXSW256,
28517 IX86_BUILTIN_PMAXSD256,
28518 IX86_BUILTIN_PMAXUB256,
28519 IX86_BUILTIN_PMAXUW256,
28520 IX86_BUILTIN_PMAXUD256,
28521 IX86_BUILTIN_PMINSB256,
28522 IX86_BUILTIN_PMINSW256,
28523 IX86_BUILTIN_PMINSD256,
28524 IX86_BUILTIN_PMINUB256,
28525 IX86_BUILTIN_PMINUW256,
28526 IX86_BUILTIN_PMINUD256,
28527 IX86_BUILTIN_PMOVMSKB256,
28528 IX86_BUILTIN_PMOVSXBW256,
28529 IX86_BUILTIN_PMOVSXBD256,
28530 IX86_BUILTIN_PMOVSXBQ256,
28531 IX86_BUILTIN_PMOVSXWD256,
28532 IX86_BUILTIN_PMOVSXWQ256,
28533 IX86_BUILTIN_PMOVSXDQ256,
28534 IX86_BUILTIN_PMOVZXBW256,
28535 IX86_BUILTIN_PMOVZXBD256,
28536 IX86_BUILTIN_PMOVZXBQ256,
28537 IX86_BUILTIN_PMOVZXWD256,
28538 IX86_BUILTIN_PMOVZXWQ256,
28539 IX86_BUILTIN_PMOVZXDQ256,
28540 IX86_BUILTIN_PMULDQ256,
28541 IX86_BUILTIN_PMULHRSW256,
28542 IX86_BUILTIN_PMULHUW256,
28543 IX86_BUILTIN_PMULHW256,
28544 IX86_BUILTIN_PMULLW256,
28545 IX86_BUILTIN_PMULLD256,
28546 IX86_BUILTIN_PMULUDQ256,
28547 IX86_BUILTIN_POR256,
28548 IX86_BUILTIN_PSADBW256,
28549 IX86_BUILTIN_PSHUFB256,
28550 IX86_BUILTIN_PSHUFD256,
28551 IX86_BUILTIN_PSHUFHW256,
28552 IX86_BUILTIN_PSHUFLW256,
28553 IX86_BUILTIN_PSIGNB256,
28554 IX86_BUILTIN_PSIGNW256,
28555 IX86_BUILTIN_PSIGND256,
28556 IX86_BUILTIN_PSLLDQI256,
28557 IX86_BUILTIN_PSLLWI256,
28558 IX86_BUILTIN_PSLLW256,
28559 IX86_BUILTIN_PSLLDI256,
28560 IX86_BUILTIN_PSLLD256,
28561 IX86_BUILTIN_PSLLQI256,
28562 IX86_BUILTIN_PSLLQ256,
28563 IX86_BUILTIN_PSRAWI256,
28564 IX86_BUILTIN_PSRAW256,
28565 IX86_BUILTIN_PSRADI256,
28566 IX86_BUILTIN_PSRAD256,
28567 IX86_BUILTIN_PSRLDQI256,
28568 IX86_BUILTIN_PSRLWI256,
28569 IX86_BUILTIN_PSRLW256,
28570 IX86_BUILTIN_PSRLDI256,
28571 IX86_BUILTIN_PSRLD256,
28572 IX86_BUILTIN_PSRLQI256,
28573 IX86_BUILTIN_PSRLQ256,
28574 IX86_BUILTIN_PSUBB256,
28575 IX86_BUILTIN_PSUBW256,
28576 IX86_BUILTIN_PSUBD256,
28577 IX86_BUILTIN_PSUBQ256,
28578 IX86_BUILTIN_PSUBSB256,
28579 IX86_BUILTIN_PSUBSW256,
28580 IX86_BUILTIN_PSUBUSB256,
28581 IX86_BUILTIN_PSUBUSW256,
28582 IX86_BUILTIN_PUNPCKHBW256,
28583 IX86_BUILTIN_PUNPCKHWD256,
28584 IX86_BUILTIN_PUNPCKHDQ256,
28585 IX86_BUILTIN_PUNPCKHQDQ256,
28586 IX86_BUILTIN_PUNPCKLBW256,
28587 IX86_BUILTIN_PUNPCKLWD256,
28588 IX86_BUILTIN_PUNPCKLDQ256,
28589 IX86_BUILTIN_PUNPCKLQDQ256,
28590 IX86_BUILTIN_PXOR256,
28591 IX86_BUILTIN_MOVNTDQA256,
28592 IX86_BUILTIN_VBROADCASTSS_PS,
28593 IX86_BUILTIN_VBROADCASTSS_PS256,
28594 IX86_BUILTIN_VBROADCASTSD_PD256,
28595 IX86_BUILTIN_VBROADCASTSI256,
28596 IX86_BUILTIN_PBLENDD256,
28597 IX86_BUILTIN_PBLENDD128,
28598 IX86_BUILTIN_PBROADCASTB256,
28599 IX86_BUILTIN_PBROADCASTW256,
28600 IX86_BUILTIN_PBROADCASTD256,
28601 IX86_BUILTIN_PBROADCASTQ256,
28602 IX86_BUILTIN_PBROADCASTB128,
28603 IX86_BUILTIN_PBROADCASTW128,
28604 IX86_BUILTIN_PBROADCASTD128,
28605 IX86_BUILTIN_PBROADCASTQ128,
28606 IX86_BUILTIN_VPERMVARSI256,
28607 IX86_BUILTIN_VPERMDF256,
28608 IX86_BUILTIN_VPERMVARSF256,
28609 IX86_BUILTIN_VPERMDI256,
28610 IX86_BUILTIN_VPERMTI256,
28611 IX86_BUILTIN_VEXTRACT128I256,
28612 IX86_BUILTIN_VINSERT128I256,
28613 IX86_BUILTIN_MASKLOADD,
28614 IX86_BUILTIN_MASKLOADQ,
28615 IX86_BUILTIN_MASKLOADD256,
28616 IX86_BUILTIN_MASKLOADQ256,
28617 IX86_BUILTIN_MASKSTORED,
28618 IX86_BUILTIN_MASKSTOREQ,
28619 IX86_BUILTIN_MASKSTORED256,
28620 IX86_BUILTIN_MASKSTOREQ256,
28621 IX86_BUILTIN_PSLLVV4DI,
28622 IX86_BUILTIN_PSLLVV2DI,
28623 IX86_BUILTIN_PSLLVV8SI,
28624 IX86_BUILTIN_PSLLVV4SI,
28625 IX86_BUILTIN_PSRAVV8SI,
28626 IX86_BUILTIN_PSRAVV4SI,
28627 IX86_BUILTIN_PSRLVV4DI,
28628 IX86_BUILTIN_PSRLVV2DI,
28629 IX86_BUILTIN_PSRLVV8SI,
28630 IX86_BUILTIN_PSRLVV4SI,
28632 IX86_BUILTIN_GATHERSIV2DF,
28633 IX86_BUILTIN_GATHERSIV4DF,
28634 IX86_BUILTIN_GATHERDIV2DF,
28635 IX86_BUILTIN_GATHERDIV4DF,
28636 IX86_BUILTIN_GATHERSIV4SF,
28637 IX86_BUILTIN_GATHERSIV8SF,
28638 IX86_BUILTIN_GATHERDIV4SF,
28639 IX86_BUILTIN_GATHERDIV8SF,
28640 IX86_BUILTIN_GATHERSIV2DI,
28641 IX86_BUILTIN_GATHERSIV4DI,
28642 IX86_BUILTIN_GATHERDIV2DI,
28643 IX86_BUILTIN_GATHERDIV4DI,
28644 IX86_BUILTIN_GATHERSIV4SI,
28645 IX86_BUILTIN_GATHERSIV8SI,
28646 IX86_BUILTIN_GATHERDIV4SI,
28647 IX86_BUILTIN_GATHERDIV8SI,
28649 /* AVX512F */
28650 IX86_BUILTIN_SI512_SI256,
28651 IX86_BUILTIN_PD512_PD256,
28652 IX86_BUILTIN_PS512_PS256,
28653 IX86_BUILTIN_SI512_SI,
28654 IX86_BUILTIN_PD512_PD,
28655 IX86_BUILTIN_PS512_PS,
28656 IX86_BUILTIN_ADDPD512,
28657 IX86_BUILTIN_ADDPS512,
28658 IX86_BUILTIN_ADDSD_ROUND,
28659 IX86_BUILTIN_ADDSS_ROUND,
28660 IX86_BUILTIN_ALIGND512,
28661 IX86_BUILTIN_ALIGNQ512,
28662 IX86_BUILTIN_BLENDMD512,
28663 IX86_BUILTIN_BLENDMPD512,
28664 IX86_BUILTIN_BLENDMPS512,
28665 IX86_BUILTIN_BLENDMQ512,
28666 IX86_BUILTIN_BROADCASTF32X4_512,
28667 IX86_BUILTIN_BROADCASTF64X4_512,
28668 IX86_BUILTIN_BROADCASTI32X4_512,
28669 IX86_BUILTIN_BROADCASTI64X4_512,
28670 IX86_BUILTIN_BROADCASTSD512,
28671 IX86_BUILTIN_BROADCASTSS512,
28672 IX86_BUILTIN_CMPD512,
28673 IX86_BUILTIN_CMPPD512,
28674 IX86_BUILTIN_CMPPS512,
28675 IX86_BUILTIN_CMPQ512,
28676 IX86_BUILTIN_CMPSD_MASK,
28677 IX86_BUILTIN_CMPSS_MASK,
28678 IX86_BUILTIN_COMIDF,
28679 IX86_BUILTIN_COMISF,
28680 IX86_BUILTIN_COMPRESSPD512,
28681 IX86_BUILTIN_COMPRESSPDSTORE512,
28682 IX86_BUILTIN_COMPRESSPS512,
28683 IX86_BUILTIN_COMPRESSPSSTORE512,
28684 IX86_BUILTIN_CVTDQ2PD512,
28685 IX86_BUILTIN_CVTDQ2PS512,
28686 IX86_BUILTIN_CVTPD2DQ512,
28687 IX86_BUILTIN_CVTPD2PS512,
28688 IX86_BUILTIN_CVTPD2UDQ512,
28689 IX86_BUILTIN_CVTPH2PS512,
28690 IX86_BUILTIN_CVTPS2DQ512,
28691 IX86_BUILTIN_CVTPS2PD512,
28692 IX86_BUILTIN_CVTPS2PH512,
28693 IX86_BUILTIN_CVTPS2UDQ512,
28694 IX86_BUILTIN_CVTSD2SS_ROUND,
28695 IX86_BUILTIN_CVTSI2SD64,
28696 IX86_BUILTIN_CVTSI2SS32,
28697 IX86_BUILTIN_CVTSI2SS64,
28698 IX86_BUILTIN_CVTSS2SD_ROUND,
28699 IX86_BUILTIN_CVTTPD2DQ512,
28700 IX86_BUILTIN_CVTTPD2UDQ512,
28701 IX86_BUILTIN_CVTTPS2DQ512,
28702 IX86_BUILTIN_CVTTPS2UDQ512,
28703 IX86_BUILTIN_CVTUDQ2PD512,
28704 IX86_BUILTIN_CVTUDQ2PS512,
28705 IX86_BUILTIN_CVTUSI2SD32,
28706 IX86_BUILTIN_CVTUSI2SD64,
28707 IX86_BUILTIN_CVTUSI2SS32,
28708 IX86_BUILTIN_CVTUSI2SS64,
28709 IX86_BUILTIN_DIVPD512,
28710 IX86_BUILTIN_DIVPS512,
28711 IX86_BUILTIN_DIVSD_ROUND,
28712 IX86_BUILTIN_DIVSS_ROUND,
28713 IX86_BUILTIN_EXPANDPD512,
28714 IX86_BUILTIN_EXPANDPD512Z,
28715 IX86_BUILTIN_EXPANDPDLOAD512,
28716 IX86_BUILTIN_EXPANDPDLOAD512Z,
28717 IX86_BUILTIN_EXPANDPS512,
28718 IX86_BUILTIN_EXPANDPS512Z,
28719 IX86_BUILTIN_EXPANDPSLOAD512,
28720 IX86_BUILTIN_EXPANDPSLOAD512Z,
28721 IX86_BUILTIN_EXTRACTF32X4,
28722 IX86_BUILTIN_EXTRACTF64X4,
28723 IX86_BUILTIN_EXTRACTI32X4,
28724 IX86_BUILTIN_EXTRACTI64X4,
28725 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28726 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28727 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28728 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28729 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28730 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28731 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28732 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28733 IX86_BUILTIN_GETEXPPD512,
28734 IX86_BUILTIN_GETEXPPS512,
28735 IX86_BUILTIN_GETEXPSD128,
28736 IX86_BUILTIN_GETEXPSS128,
28737 IX86_BUILTIN_GETMANTPD512,
28738 IX86_BUILTIN_GETMANTPS512,
28739 IX86_BUILTIN_GETMANTSD128,
28740 IX86_BUILTIN_GETMANTSS128,
28741 IX86_BUILTIN_INSERTF32X4,
28742 IX86_BUILTIN_INSERTF64X4,
28743 IX86_BUILTIN_INSERTI32X4,
28744 IX86_BUILTIN_INSERTI64X4,
28745 IX86_BUILTIN_LOADAPD512,
28746 IX86_BUILTIN_LOADAPS512,
28747 IX86_BUILTIN_LOADDQUDI512,
28748 IX86_BUILTIN_LOADDQUSI512,
28749 IX86_BUILTIN_LOADUPD512,
28750 IX86_BUILTIN_LOADUPS512,
28751 IX86_BUILTIN_MAXPD512,
28752 IX86_BUILTIN_MAXPS512,
28753 IX86_BUILTIN_MAXSD_ROUND,
28754 IX86_BUILTIN_MAXSS_ROUND,
28755 IX86_BUILTIN_MINPD512,
28756 IX86_BUILTIN_MINPS512,
28757 IX86_BUILTIN_MINSD_ROUND,
28758 IX86_BUILTIN_MINSS_ROUND,
28759 IX86_BUILTIN_MOVAPD512,
28760 IX86_BUILTIN_MOVAPS512,
28761 IX86_BUILTIN_MOVDDUP512,
28762 IX86_BUILTIN_MOVDQA32LOAD512,
28763 IX86_BUILTIN_MOVDQA32STORE512,
28764 IX86_BUILTIN_MOVDQA32_512,
28765 IX86_BUILTIN_MOVDQA64LOAD512,
28766 IX86_BUILTIN_MOVDQA64STORE512,
28767 IX86_BUILTIN_MOVDQA64_512,
28768 IX86_BUILTIN_MOVNTDQ512,
28769 IX86_BUILTIN_MOVNTDQA512,
28770 IX86_BUILTIN_MOVNTPD512,
28771 IX86_BUILTIN_MOVNTPS512,
28772 IX86_BUILTIN_MOVSHDUP512,
28773 IX86_BUILTIN_MOVSLDUP512,
28774 IX86_BUILTIN_MULPD512,
28775 IX86_BUILTIN_MULPS512,
28776 IX86_BUILTIN_MULSD_ROUND,
28777 IX86_BUILTIN_MULSS_ROUND,
28778 IX86_BUILTIN_PABSD512,
28779 IX86_BUILTIN_PABSQ512,
28780 IX86_BUILTIN_PADDD512,
28781 IX86_BUILTIN_PADDQ512,
28782 IX86_BUILTIN_PANDD512,
28783 IX86_BUILTIN_PANDND512,
28784 IX86_BUILTIN_PANDNQ512,
28785 IX86_BUILTIN_PANDQ512,
28786 IX86_BUILTIN_PBROADCASTD512,
28787 IX86_BUILTIN_PBROADCASTD512_GPR,
28788 IX86_BUILTIN_PBROADCASTMB512,
28789 IX86_BUILTIN_PBROADCASTMW512,
28790 IX86_BUILTIN_PBROADCASTQ512,
28791 IX86_BUILTIN_PBROADCASTQ512_GPR,
28792 IX86_BUILTIN_PBROADCASTQ512_MEM,
28793 IX86_BUILTIN_PCMPEQD512_MASK,
28794 IX86_BUILTIN_PCMPEQQ512_MASK,
28795 IX86_BUILTIN_PCMPGTD512_MASK,
28796 IX86_BUILTIN_PCMPGTQ512_MASK,
28797 IX86_BUILTIN_PCOMPRESSD512,
28798 IX86_BUILTIN_PCOMPRESSDSTORE512,
28799 IX86_BUILTIN_PCOMPRESSQ512,
28800 IX86_BUILTIN_PCOMPRESSQSTORE512,
28801 IX86_BUILTIN_PEXPANDD512,
28802 IX86_BUILTIN_PEXPANDD512Z,
28803 IX86_BUILTIN_PEXPANDDLOAD512,
28804 IX86_BUILTIN_PEXPANDDLOAD512Z,
28805 IX86_BUILTIN_PEXPANDQ512,
28806 IX86_BUILTIN_PEXPANDQ512Z,
28807 IX86_BUILTIN_PEXPANDQLOAD512,
28808 IX86_BUILTIN_PEXPANDQLOAD512Z,
28809 IX86_BUILTIN_PMAXSD512,
28810 IX86_BUILTIN_PMAXSQ512,
28811 IX86_BUILTIN_PMAXUD512,
28812 IX86_BUILTIN_PMAXUQ512,
28813 IX86_BUILTIN_PMINSD512,
28814 IX86_BUILTIN_PMINSQ512,
28815 IX86_BUILTIN_PMINUD512,
28816 IX86_BUILTIN_PMINUQ512,
28817 IX86_BUILTIN_PMOVDB512,
28818 IX86_BUILTIN_PMOVDB512_MEM,
28819 IX86_BUILTIN_PMOVDW512,
28820 IX86_BUILTIN_PMOVDW512_MEM,
28821 IX86_BUILTIN_PMOVQB512,
28822 IX86_BUILTIN_PMOVQB512_MEM,
28823 IX86_BUILTIN_PMOVQD512,
28824 IX86_BUILTIN_PMOVQD512_MEM,
28825 IX86_BUILTIN_PMOVQW512,
28826 IX86_BUILTIN_PMOVQW512_MEM,
28827 IX86_BUILTIN_PMOVSDB512,
28828 IX86_BUILTIN_PMOVSDB512_MEM,
28829 IX86_BUILTIN_PMOVSDW512,
28830 IX86_BUILTIN_PMOVSDW512_MEM,
28831 IX86_BUILTIN_PMOVSQB512,
28832 IX86_BUILTIN_PMOVSQB512_MEM,
28833 IX86_BUILTIN_PMOVSQD512,
28834 IX86_BUILTIN_PMOVSQD512_MEM,
28835 IX86_BUILTIN_PMOVSQW512,
28836 IX86_BUILTIN_PMOVSQW512_MEM,
28837 IX86_BUILTIN_PMOVSXBD512,
28838 IX86_BUILTIN_PMOVSXBQ512,
28839 IX86_BUILTIN_PMOVSXDQ512,
28840 IX86_BUILTIN_PMOVSXWD512,
28841 IX86_BUILTIN_PMOVSXWQ512,
28842 IX86_BUILTIN_PMOVUSDB512,
28843 IX86_BUILTIN_PMOVUSDB512_MEM,
28844 IX86_BUILTIN_PMOVUSDW512,
28845 IX86_BUILTIN_PMOVUSDW512_MEM,
28846 IX86_BUILTIN_PMOVUSQB512,
28847 IX86_BUILTIN_PMOVUSQB512_MEM,
28848 IX86_BUILTIN_PMOVUSQD512,
28849 IX86_BUILTIN_PMOVUSQD512_MEM,
28850 IX86_BUILTIN_PMOVUSQW512,
28851 IX86_BUILTIN_PMOVUSQW512_MEM,
28852 IX86_BUILTIN_PMOVZXBD512,
28853 IX86_BUILTIN_PMOVZXBQ512,
28854 IX86_BUILTIN_PMOVZXDQ512,
28855 IX86_BUILTIN_PMOVZXWD512,
28856 IX86_BUILTIN_PMOVZXWQ512,
28857 IX86_BUILTIN_PMULDQ512,
28858 IX86_BUILTIN_PMULLD512,
28859 IX86_BUILTIN_PMULUDQ512,
28860 IX86_BUILTIN_PORD512,
28861 IX86_BUILTIN_PORQ512,
28862 IX86_BUILTIN_PROLD512,
28863 IX86_BUILTIN_PROLQ512,
28864 IX86_BUILTIN_PROLVD512,
28865 IX86_BUILTIN_PROLVQ512,
28866 IX86_BUILTIN_PRORD512,
28867 IX86_BUILTIN_PRORQ512,
28868 IX86_BUILTIN_PRORVD512,
28869 IX86_BUILTIN_PRORVQ512,
28870 IX86_BUILTIN_PSHUFD512,
28871 IX86_BUILTIN_PSLLD512,
28872 IX86_BUILTIN_PSLLDI512,
28873 IX86_BUILTIN_PSLLQ512,
28874 IX86_BUILTIN_PSLLQI512,
28875 IX86_BUILTIN_PSLLVV16SI,
28876 IX86_BUILTIN_PSLLVV8DI,
28877 IX86_BUILTIN_PSRAD512,
28878 IX86_BUILTIN_PSRADI512,
28879 IX86_BUILTIN_PSRAQ512,
28880 IX86_BUILTIN_PSRAQI512,
28881 IX86_BUILTIN_PSRAVV16SI,
28882 IX86_BUILTIN_PSRAVV8DI,
28883 IX86_BUILTIN_PSRLD512,
28884 IX86_BUILTIN_PSRLDI512,
28885 IX86_BUILTIN_PSRLQ512,
28886 IX86_BUILTIN_PSRLQI512,
28887 IX86_BUILTIN_PSRLVV16SI,
28888 IX86_BUILTIN_PSRLVV8DI,
28889 IX86_BUILTIN_PSUBD512,
28890 IX86_BUILTIN_PSUBQ512,
28891 IX86_BUILTIN_PTESTMD512,
28892 IX86_BUILTIN_PTESTMQ512,
28893 IX86_BUILTIN_PTESTNMD512,
28894 IX86_BUILTIN_PTESTNMQ512,
28895 IX86_BUILTIN_PUNPCKHDQ512,
28896 IX86_BUILTIN_PUNPCKHQDQ512,
28897 IX86_BUILTIN_PUNPCKLDQ512,
28898 IX86_BUILTIN_PUNPCKLQDQ512,
28899 IX86_BUILTIN_PXORD512,
28900 IX86_BUILTIN_PXORQ512,
28901 IX86_BUILTIN_RCP14PD512,
28902 IX86_BUILTIN_RCP14PS512,
28903 IX86_BUILTIN_RCP14SD,
28904 IX86_BUILTIN_RCP14SS,
28905 IX86_BUILTIN_RNDSCALEPD,
28906 IX86_BUILTIN_RNDSCALEPS,
28907 IX86_BUILTIN_RNDSCALESD,
28908 IX86_BUILTIN_RNDSCALESS,
28909 IX86_BUILTIN_RSQRT14PD512,
28910 IX86_BUILTIN_RSQRT14PS512,
28911 IX86_BUILTIN_RSQRT14SD,
28912 IX86_BUILTIN_RSQRT14SS,
28913 IX86_BUILTIN_SCALEFPD512,
28914 IX86_BUILTIN_SCALEFPS512,
28915 IX86_BUILTIN_SCALEFSD,
28916 IX86_BUILTIN_SCALEFSS,
28917 IX86_BUILTIN_SHUFPD512,
28918 IX86_BUILTIN_SHUFPS512,
28919 IX86_BUILTIN_SHUF_F32x4,
28920 IX86_BUILTIN_SHUF_F64x2,
28921 IX86_BUILTIN_SHUF_I32x4,
28922 IX86_BUILTIN_SHUF_I64x2,
28923 IX86_BUILTIN_SQRTPD512,
28924 IX86_BUILTIN_SQRTPD512_MASK,
28925 IX86_BUILTIN_SQRTPS512_MASK,
28926 IX86_BUILTIN_SQRTPS_NR512,
28927 IX86_BUILTIN_SQRTSD_ROUND,
28928 IX86_BUILTIN_SQRTSS_ROUND,
28929 IX86_BUILTIN_STOREAPD512,
28930 IX86_BUILTIN_STOREAPS512,
28931 IX86_BUILTIN_STOREDQUDI512,
28932 IX86_BUILTIN_STOREDQUSI512,
28933 IX86_BUILTIN_STOREUPD512,
28934 IX86_BUILTIN_STOREUPS512,
28935 IX86_BUILTIN_SUBPD512,
28936 IX86_BUILTIN_SUBPS512,
28937 IX86_BUILTIN_SUBSD_ROUND,
28938 IX86_BUILTIN_SUBSS_ROUND,
28939 IX86_BUILTIN_UCMPD512,
28940 IX86_BUILTIN_UCMPQ512,
28941 IX86_BUILTIN_UNPCKHPD512,
28942 IX86_BUILTIN_UNPCKHPS512,
28943 IX86_BUILTIN_UNPCKLPD512,
28944 IX86_BUILTIN_UNPCKLPS512,
28945 IX86_BUILTIN_VCVTSD2SI32,
28946 IX86_BUILTIN_VCVTSD2SI64,
28947 IX86_BUILTIN_VCVTSD2USI32,
28948 IX86_BUILTIN_VCVTSD2USI64,
28949 IX86_BUILTIN_VCVTSS2SI32,
28950 IX86_BUILTIN_VCVTSS2SI64,
28951 IX86_BUILTIN_VCVTSS2USI32,
28952 IX86_BUILTIN_VCVTSS2USI64,
28953 IX86_BUILTIN_VCVTTSD2SI32,
28954 IX86_BUILTIN_VCVTTSD2SI64,
28955 IX86_BUILTIN_VCVTTSD2USI32,
28956 IX86_BUILTIN_VCVTTSD2USI64,
28957 IX86_BUILTIN_VCVTTSS2SI32,
28958 IX86_BUILTIN_VCVTTSS2SI64,
28959 IX86_BUILTIN_VCVTTSS2USI32,
28960 IX86_BUILTIN_VCVTTSS2USI64,
28961 IX86_BUILTIN_VFMADDPD512_MASK,
28962 IX86_BUILTIN_VFMADDPD512_MASK3,
28963 IX86_BUILTIN_VFMADDPD512_MASKZ,
28964 IX86_BUILTIN_VFMADDPS512_MASK,
28965 IX86_BUILTIN_VFMADDPS512_MASK3,
28966 IX86_BUILTIN_VFMADDPS512_MASKZ,
28967 IX86_BUILTIN_VFMADDSD3_ROUND,
28968 IX86_BUILTIN_VFMADDSS3_ROUND,
28969 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28970 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28971 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28972 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28973 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28974 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
28975 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
28976 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
28977 IX86_BUILTIN_VFMSUBPD512_MASK3,
28978 IX86_BUILTIN_VFMSUBPS512_MASK3,
28979 IX86_BUILTIN_VFMSUBSD3_MASK3,
28980 IX86_BUILTIN_VFMSUBSS3_MASK3,
28981 IX86_BUILTIN_VFNMADDPD512_MASK,
28982 IX86_BUILTIN_VFNMADDPS512_MASK,
28983 IX86_BUILTIN_VFNMSUBPD512_MASK,
28984 IX86_BUILTIN_VFNMSUBPD512_MASK3,
28985 IX86_BUILTIN_VFNMSUBPS512_MASK,
28986 IX86_BUILTIN_VFNMSUBPS512_MASK3,
28987 IX86_BUILTIN_VPCLZCNTD512,
28988 IX86_BUILTIN_VPCLZCNTQ512,
28989 IX86_BUILTIN_VPCONFLICTD512,
28990 IX86_BUILTIN_VPCONFLICTQ512,
28991 IX86_BUILTIN_VPERMDF512,
28992 IX86_BUILTIN_VPERMDI512,
28993 IX86_BUILTIN_VPERMI2VARD512,
28994 IX86_BUILTIN_VPERMI2VARPD512,
28995 IX86_BUILTIN_VPERMI2VARPS512,
28996 IX86_BUILTIN_VPERMI2VARQ512,
28997 IX86_BUILTIN_VPERMILPD512,
28998 IX86_BUILTIN_VPERMILPS512,
28999 IX86_BUILTIN_VPERMILVARPD512,
29000 IX86_BUILTIN_VPERMILVARPS512,
29001 IX86_BUILTIN_VPERMT2VARD512,
29002 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29003 IX86_BUILTIN_VPERMT2VARPD512,
29004 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29005 IX86_BUILTIN_VPERMT2VARPS512,
29006 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29007 IX86_BUILTIN_VPERMT2VARQ512,
29008 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29009 IX86_BUILTIN_VPERMVARDF512,
29010 IX86_BUILTIN_VPERMVARDI512,
29011 IX86_BUILTIN_VPERMVARSF512,
29012 IX86_BUILTIN_VPERMVARSI512,
29013 IX86_BUILTIN_VTERNLOGD512_MASK,
29014 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29015 IX86_BUILTIN_VTERNLOGQ512_MASK,
29016 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29018 /* Mask arithmetic operations */
29019 IX86_BUILTIN_KAND16,
29020 IX86_BUILTIN_KANDN16,
29021 IX86_BUILTIN_KNOT16,
29022 IX86_BUILTIN_KOR16,
29023 IX86_BUILTIN_KORTESTC16,
29024 IX86_BUILTIN_KORTESTZ16,
29025 IX86_BUILTIN_KUNPCKBW,
29026 IX86_BUILTIN_KXNOR16,
29027 IX86_BUILTIN_KXOR16,
29028 IX86_BUILTIN_KMOV16,
29030 /* AVX512VL. */
29031 IX86_BUILTIN_PMOVUSQD256_MEM,
29032 IX86_BUILTIN_PMOVUSQD128_MEM,
29033 IX86_BUILTIN_PMOVSQD256_MEM,
29034 IX86_BUILTIN_PMOVSQD128_MEM,
29035 IX86_BUILTIN_PMOVQD256_MEM,
29036 IX86_BUILTIN_PMOVQD128_MEM,
29037 IX86_BUILTIN_PMOVUSQW256_MEM,
29038 IX86_BUILTIN_PMOVUSQW128_MEM,
29039 IX86_BUILTIN_PMOVSQW256_MEM,
29040 IX86_BUILTIN_PMOVSQW128_MEM,
29041 IX86_BUILTIN_PMOVQW256_MEM,
29042 IX86_BUILTIN_PMOVQW128_MEM,
29043 IX86_BUILTIN_PMOVUSQB256_MEM,
29044 IX86_BUILTIN_PMOVUSQB128_MEM,
29045 IX86_BUILTIN_PMOVSQB256_MEM,
29046 IX86_BUILTIN_PMOVSQB128_MEM,
29047 IX86_BUILTIN_PMOVQB256_MEM,
29048 IX86_BUILTIN_PMOVQB128_MEM,
29049 IX86_BUILTIN_PMOVUSDW256_MEM,
29050 IX86_BUILTIN_PMOVUSDW128_MEM,
29051 IX86_BUILTIN_PMOVSDW256_MEM,
29052 IX86_BUILTIN_PMOVSDW128_MEM,
29053 IX86_BUILTIN_PMOVDW256_MEM,
29054 IX86_BUILTIN_PMOVDW128_MEM,
29055 IX86_BUILTIN_PMOVUSDB256_MEM,
29056 IX86_BUILTIN_PMOVUSDB128_MEM,
29057 IX86_BUILTIN_PMOVSDB256_MEM,
29058 IX86_BUILTIN_PMOVSDB128_MEM,
29059 IX86_BUILTIN_PMOVDB256_MEM,
29060 IX86_BUILTIN_PMOVDB128_MEM,
29061 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29062 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29063 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29064 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29065 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29066 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29067 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29068 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29069 IX86_BUILTIN_LOADAPD256_MASK,
29070 IX86_BUILTIN_LOADAPD128_MASK,
29071 IX86_BUILTIN_LOADAPS256_MASK,
29072 IX86_BUILTIN_LOADAPS128_MASK,
29073 IX86_BUILTIN_STOREAPD256_MASK,
29074 IX86_BUILTIN_STOREAPD128_MASK,
29075 IX86_BUILTIN_STOREAPS256_MASK,
29076 IX86_BUILTIN_STOREAPS128_MASK,
29077 IX86_BUILTIN_LOADUPD256_MASK,
29078 IX86_BUILTIN_LOADUPD128_MASK,
29079 IX86_BUILTIN_LOADUPS256_MASK,
29080 IX86_BUILTIN_LOADUPS128_MASK,
29081 IX86_BUILTIN_STOREUPD256_MASK,
29082 IX86_BUILTIN_STOREUPD128_MASK,
29083 IX86_BUILTIN_STOREUPS256_MASK,
29084 IX86_BUILTIN_STOREUPS128_MASK,
29085 IX86_BUILTIN_LOADDQUDI256_MASK,
29086 IX86_BUILTIN_LOADDQUDI128_MASK,
29087 IX86_BUILTIN_LOADDQUSI256_MASK,
29088 IX86_BUILTIN_LOADDQUSI128_MASK,
29089 IX86_BUILTIN_LOADDQUHI256_MASK,
29090 IX86_BUILTIN_LOADDQUHI128_MASK,
29091 IX86_BUILTIN_LOADDQUQI256_MASK,
29092 IX86_BUILTIN_LOADDQUQI128_MASK,
29093 IX86_BUILTIN_STOREDQUDI256_MASK,
29094 IX86_BUILTIN_STOREDQUDI128_MASK,
29095 IX86_BUILTIN_STOREDQUSI256_MASK,
29096 IX86_BUILTIN_STOREDQUSI128_MASK,
29097 IX86_BUILTIN_STOREDQUHI256_MASK,
29098 IX86_BUILTIN_STOREDQUHI128_MASK,
29099 IX86_BUILTIN_STOREDQUQI256_MASK,
29100 IX86_BUILTIN_STOREDQUQI128_MASK,
29101 IX86_BUILTIN_COMPRESSPDSTORE256,
29102 IX86_BUILTIN_COMPRESSPDSTORE128,
29103 IX86_BUILTIN_COMPRESSPSSTORE256,
29104 IX86_BUILTIN_COMPRESSPSSTORE128,
29105 IX86_BUILTIN_PCOMPRESSQSTORE256,
29106 IX86_BUILTIN_PCOMPRESSQSTORE128,
29107 IX86_BUILTIN_PCOMPRESSDSTORE256,
29108 IX86_BUILTIN_PCOMPRESSDSTORE128,
29109 IX86_BUILTIN_EXPANDPDLOAD256,
29110 IX86_BUILTIN_EXPANDPDLOAD128,
29111 IX86_BUILTIN_EXPANDPSLOAD256,
29112 IX86_BUILTIN_EXPANDPSLOAD128,
29113 IX86_BUILTIN_PEXPANDQLOAD256,
29114 IX86_BUILTIN_PEXPANDQLOAD128,
29115 IX86_BUILTIN_PEXPANDDLOAD256,
29116 IX86_BUILTIN_PEXPANDDLOAD128,
29117 IX86_BUILTIN_EXPANDPDLOAD256Z,
29118 IX86_BUILTIN_EXPANDPDLOAD128Z,
29119 IX86_BUILTIN_EXPANDPSLOAD256Z,
29120 IX86_BUILTIN_EXPANDPSLOAD128Z,
29121 IX86_BUILTIN_PEXPANDQLOAD256Z,
29122 IX86_BUILTIN_PEXPANDQLOAD128Z,
29123 IX86_BUILTIN_PEXPANDDLOAD256Z,
29124 IX86_BUILTIN_PEXPANDDLOAD128Z,
29125 IX86_BUILTIN_PALIGNR256_MASK,
29126 IX86_BUILTIN_PALIGNR128_MASK,
29127 IX86_BUILTIN_MOVDQA64_256_MASK,
29128 IX86_BUILTIN_MOVDQA64_128_MASK,
29129 IX86_BUILTIN_MOVDQA32_256_MASK,
29130 IX86_BUILTIN_MOVDQA32_128_MASK,
29131 IX86_BUILTIN_MOVAPD256_MASK,
29132 IX86_BUILTIN_MOVAPD128_MASK,
29133 IX86_BUILTIN_MOVAPS256_MASK,
29134 IX86_BUILTIN_MOVAPS128_MASK,
29135 IX86_BUILTIN_MOVDQUHI256_MASK,
29136 IX86_BUILTIN_MOVDQUHI128_MASK,
29137 IX86_BUILTIN_MOVDQUQI256_MASK,
29138 IX86_BUILTIN_MOVDQUQI128_MASK,
29139 IX86_BUILTIN_MINPS128_MASK,
29140 IX86_BUILTIN_MAXPS128_MASK,
29141 IX86_BUILTIN_MINPD128_MASK,
29142 IX86_BUILTIN_MAXPD128_MASK,
29143 IX86_BUILTIN_MAXPD256_MASK,
29144 IX86_BUILTIN_MAXPS256_MASK,
29145 IX86_BUILTIN_MINPD256_MASK,
29146 IX86_BUILTIN_MINPS256_MASK,
29147 IX86_BUILTIN_MULPS128_MASK,
29148 IX86_BUILTIN_DIVPS128_MASK,
29149 IX86_BUILTIN_MULPD128_MASK,
29150 IX86_BUILTIN_DIVPD128_MASK,
29151 IX86_BUILTIN_DIVPD256_MASK,
29152 IX86_BUILTIN_DIVPS256_MASK,
29153 IX86_BUILTIN_MULPD256_MASK,
29154 IX86_BUILTIN_MULPS256_MASK,
29155 IX86_BUILTIN_ADDPD128_MASK,
29156 IX86_BUILTIN_ADDPD256_MASK,
29157 IX86_BUILTIN_ADDPS128_MASK,
29158 IX86_BUILTIN_ADDPS256_MASK,
29159 IX86_BUILTIN_SUBPD128_MASK,
29160 IX86_BUILTIN_SUBPD256_MASK,
29161 IX86_BUILTIN_SUBPS128_MASK,
29162 IX86_BUILTIN_SUBPS256_MASK,
29163 IX86_BUILTIN_XORPD256_MASK,
29164 IX86_BUILTIN_XORPD128_MASK,
29165 IX86_BUILTIN_XORPS256_MASK,
29166 IX86_BUILTIN_XORPS128_MASK,
29167 IX86_BUILTIN_ORPD256_MASK,
29168 IX86_BUILTIN_ORPD128_MASK,
29169 IX86_BUILTIN_ORPS256_MASK,
29170 IX86_BUILTIN_ORPS128_MASK,
29171 IX86_BUILTIN_BROADCASTF32x2_256,
29172 IX86_BUILTIN_BROADCASTI32x2_256,
29173 IX86_BUILTIN_BROADCASTI32x2_128,
29174 IX86_BUILTIN_BROADCASTF64X2_256,
29175 IX86_BUILTIN_BROADCASTI64X2_256,
29176 IX86_BUILTIN_BROADCASTF32X4_256,
29177 IX86_BUILTIN_BROADCASTI32X4_256,
29178 IX86_BUILTIN_EXTRACTF32X4_256,
29179 IX86_BUILTIN_EXTRACTI32X4_256,
29180 IX86_BUILTIN_DBPSADBW256,
29181 IX86_BUILTIN_DBPSADBW128,
29182 IX86_BUILTIN_CVTTPD2QQ256,
29183 IX86_BUILTIN_CVTTPD2QQ128,
29184 IX86_BUILTIN_CVTTPD2UQQ256,
29185 IX86_BUILTIN_CVTTPD2UQQ128,
29186 IX86_BUILTIN_CVTPD2QQ256,
29187 IX86_BUILTIN_CVTPD2QQ128,
29188 IX86_BUILTIN_CVTPD2UQQ256,
29189 IX86_BUILTIN_CVTPD2UQQ128,
29190 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29191 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29192 IX86_BUILTIN_CVTTPS2QQ256,
29193 IX86_BUILTIN_CVTTPS2QQ128,
29194 IX86_BUILTIN_CVTTPS2UQQ256,
29195 IX86_BUILTIN_CVTTPS2UQQ128,
29196 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29197 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29198 IX86_BUILTIN_CVTTPS2UDQ256,
29199 IX86_BUILTIN_CVTTPS2UDQ128,
29200 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29201 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29202 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29203 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29204 IX86_BUILTIN_CVTPD2DQ256_MASK,
29205 IX86_BUILTIN_CVTPD2DQ128_MASK,
29206 IX86_BUILTIN_CVTDQ2PD256_MASK,
29207 IX86_BUILTIN_CVTDQ2PD128_MASK,
29208 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29209 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29210 IX86_BUILTIN_CVTDQ2PS256_MASK,
29211 IX86_BUILTIN_CVTDQ2PS128_MASK,
29212 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29213 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29214 IX86_BUILTIN_CVTPS2PD256_MASK,
29215 IX86_BUILTIN_CVTPS2PD128_MASK,
29216 IX86_BUILTIN_PBROADCASTB256_MASK,
29217 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29218 IX86_BUILTIN_PBROADCASTB128_MASK,
29219 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29220 IX86_BUILTIN_PBROADCASTW256_MASK,
29221 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29222 IX86_BUILTIN_PBROADCASTW128_MASK,
29223 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29224 IX86_BUILTIN_PBROADCASTD256_MASK,
29225 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29226 IX86_BUILTIN_PBROADCASTD128_MASK,
29227 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29228 IX86_BUILTIN_PBROADCASTQ256_MASK,
29229 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29230 IX86_BUILTIN_PBROADCASTQ256_MEM_MASK,
29231 IX86_BUILTIN_PBROADCASTQ128_MASK,
29232 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29233 IX86_BUILTIN_PBROADCASTQ128_MEM_MASK,
29234 IX86_BUILTIN_BROADCASTSS256,
29235 IX86_BUILTIN_BROADCASTSS128,
29236 IX86_BUILTIN_BROADCASTSD256,
29237 IX86_BUILTIN_EXTRACTF64X2_256,
29238 IX86_BUILTIN_EXTRACTI64X2_256,
29239 IX86_BUILTIN_INSERTF32X4_256,
29240 IX86_BUILTIN_INSERTI32X4_256,
29241 IX86_BUILTIN_PMOVSXBW256_MASK,
29242 IX86_BUILTIN_PMOVSXBW128_MASK,
29243 IX86_BUILTIN_PMOVSXBD256_MASK,
29244 IX86_BUILTIN_PMOVSXBD128_MASK,
29245 IX86_BUILTIN_PMOVSXBQ256_MASK,
29246 IX86_BUILTIN_PMOVSXBQ128_MASK,
29247 IX86_BUILTIN_PMOVSXWD256_MASK,
29248 IX86_BUILTIN_PMOVSXWD128_MASK,
29249 IX86_BUILTIN_PMOVSXWQ256_MASK,
29250 IX86_BUILTIN_PMOVSXWQ128_MASK,
29251 IX86_BUILTIN_PMOVSXDQ256_MASK,
29252 IX86_BUILTIN_PMOVSXDQ128_MASK,
29253 IX86_BUILTIN_PMOVZXBW256_MASK,
29254 IX86_BUILTIN_PMOVZXBW128_MASK,
29255 IX86_BUILTIN_PMOVZXBD256_MASK,
29256 IX86_BUILTIN_PMOVZXBD128_MASK,
29257 IX86_BUILTIN_PMOVZXBQ256_MASK,
29258 IX86_BUILTIN_PMOVZXBQ128_MASK,
29259 IX86_BUILTIN_PMOVZXWD256_MASK,
29260 IX86_BUILTIN_PMOVZXWD128_MASK,
29261 IX86_BUILTIN_PMOVZXWQ256_MASK,
29262 IX86_BUILTIN_PMOVZXWQ128_MASK,
29263 IX86_BUILTIN_PMOVZXDQ256_MASK,
29264 IX86_BUILTIN_PMOVZXDQ128_MASK,
29265 IX86_BUILTIN_REDUCEPD256_MASK,
29266 IX86_BUILTIN_REDUCEPD128_MASK,
29267 IX86_BUILTIN_REDUCEPS256_MASK,
29268 IX86_BUILTIN_REDUCEPS128_MASK,
29269 IX86_BUILTIN_REDUCESD_MASK,
29270 IX86_BUILTIN_REDUCESS_MASK,
29271 IX86_BUILTIN_VPERMVARHI256_MASK,
29272 IX86_BUILTIN_VPERMVARHI128_MASK,
29273 IX86_BUILTIN_VPERMT2VARHI256,
29274 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29275 IX86_BUILTIN_VPERMT2VARHI128,
29276 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29277 IX86_BUILTIN_VPERMI2VARHI256,
29278 IX86_BUILTIN_VPERMI2VARHI128,
29279 IX86_BUILTIN_RCP14PD256,
29280 IX86_BUILTIN_RCP14PD128,
29281 IX86_BUILTIN_RCP14PS256,
29282 IX86_BUILTIN_RCP14PS128,
29283 IX86_BUILTIN_RSQRT14PD256_MASK,
29284 IX86_BUILTIN_RSQRT14PD128_MASK,
29285 IX86_BUILTIN_RSQRT14PS256_MASK,
29286 IX86_BUILTIN_RSQRT14PS128_MASK,
29287 IX86_BUILTIN_SQRTPD256_MASK,
29288 IX86_BUILTIN_SQRTPD128_MASK,
29289 IX86_BUILTIN_SQRTPS256_MASK,
29290 IX86_BUILTIN_SQRTPS128_MASK,
29291 IX86_BUILTIN_PADDB128_MASK,
29292 IX86_BUILTIN_PADDW128_MASK,
29293 IX86_BUILTIN_PADDD128_MASK,
29294 IX86_BUILTIN_PADDQ128_MASK,
29295 IX86_BUILTIN_PSUBB128_MASK,
29296 IX86_BUILTIN_PSUBW128_MASK,
29297 IX86_BUILTIN_PSUBD128_MASK,
29298 IX86_BUILTIN_PSUBQ128_MASK,
29299 IX86_BUILTIN_PADDSB128_MASK,
29300 IX86_BUILTIN_PADDSW128_MASK,
29301 IX86_BUILTIN_PSUBSB128_MASK,
29302 IX86_BUILTIN_PSUBSW128_MASK,
29303 IX86_BUILTIN_PADDUSB128_MASK,
29304 IX86_BUILTIN_PADDUSW128_MASK,
29305 IX86_BUILTIN_PSUBUSB128_MASK,
29306 IX86_BUILTIN_PSUBUSW128_MASK,
29307 IX86_BUILTIN_PADDB256_MASK,
29308 IX86_BUILTIN_PADDW256_MASK,
29309 IX86_BUILTIN_PADDD256_MASK,
29310 IX86_BUILTIN_PADDQ256_MASK,
29311 IX86_BUILTIN_PADDSB256_MASK,
29312 IX86_BUILTIN_PADDSW256_MASK,
29313 IX86_BUILTIN_PADDUSB256_MASK,
29314 IX86_BUILTIN_PADDUSW256_MASK,
29315 IX86_BUILTIN_PSUBB256_MASK,
29316 IX86_BUILTIN_PSUBW256_MASK,
29317 IX86_BUILTIN_PSUBD256_MASK,
29318 IX86_BUILTIN_PSUBQ256_MASK,
29319 IX86_BUILTIN_PSUBSB256_MASK,
29320 IX86_BUILTIN_PSUBSW256_MASK,
29321 IX86_BUILTIN_PSUBUSB256_MASK,
29322 IX86_BUILTIN_PSUBUSW256_MASK,
29323 IX86_BUILTIN_SHUF_F64x2_256,
29324 IX86_BUILTIN_SHUF_I64x2_256,
29325 IX86_BUILTIN_SHUF_I32x4_256,
29326 IX86_BUILTIN_SHUF_F32x4_256,
29327 IX86_BUILTIN_PMOVWB128,
29328 IX86_BUILTIN_PMOVWB256,
29329 IX86_BUILTIN_PMOVSWB128,
29330 IX86_BUILTIN_PMOVSWB256,
29331 IX86_BUILTIN_PMOVUSWB128,
29332 IX86_BUILTIN_PMOVUSWB256,
29333 IX86_BUILTIN_PMOVDB128,
29334 IX86_BUILTIN_PMOVDB256,
29335 IX86_BUILTIN_PMOVSDB128,
29336 IX86_BUILTIN_PMOVSDB256,
29337 IX86_BUILTIN_PMOVUSDB128,
29338 IX86_BUILTIN_PMOVUSDB256,
29339 IX86_BUILTIN_PMOVDW128,
29340 IX86_BUILTIN_PMOVDW256,
29341 IX86_BUILTIN_PMOVSDW128,
29342 IX86_BUILTIN_PMOVSDW256,
29343 IX86_BUILTIN_PMOVUSDW128,
29344 IX86_BUILTIN_PMOVUSDW256,
29345 IX86_BUILTIN_PMOVQB128,
29346 IX86_BUILTIN_PMOVQB256,
29347 IX86_BUILTIN_PMOVSQB128,
29348 IX86_BUILTIN_PMOVSQB256,
29349 IX86_BUILTIN_PMOVUSQB128,
29350 IX86_BUILTIN_PMOVUSQB256,
29351 IX86_BUILTIN_PMOVQW128,
29352 IX86_BUILTIN_PMOVQW256,
29353 IX86_BUILTIN_PMOVSQW128,
29354 IX86_BUILTIN_PMOVSQW256,
29355 IX86_BUILTIN_PMOVUSQW128,
29356 IX86_BUILTIN_PMOVUSQW256,
29357 IX86_BUILTIN_PMOVQD128,
29358 IX86_BUILTIN_PMOVQD256,
29359 IX86_BUILTIN_PMOVSQD128,
29360 IX86_BUILTIN_PMOVSQD256,
29361 IX86_BUILTIN_PMOVUSQD128,
29362 IX86_BUILTIN_PMOVUSQD256,
29363 IX86_BUILTIN_RANGEPD256,
29364 IX86_BUILTIN_RANGEPD128,
29365 IX86_BUILTIN_RANGEPS256,
29366 IX86_BUILTIN_RANGEPS128,
29367 IX86_BUILTIN_GETEXPPS256,
29368 IX86_BUILTIN_GETEXPPD256,
29369 IX86_BUILTIN_GETEXPPS128,
29370 IX86_BUILTIN_GETEXPPD128,
29371 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29372 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29373 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29374 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29375 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29376 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29377 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29378 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29379 IX86_BUILTIN_PABSQ256,
29380 IX86_BUILTIN_PABSQ128,
29381 IX86_BUILTIN_PABSD256_MASK,
29382 IX86_BUILTIN_PABSD128_MASK,
29383 IX86_BUILTIN_PMULHRSW256_MASK,
29384 IX86_BUILTIN_PMULHRSW128_MASK,
29385 IX86_BUILTIN_PMULHUW128_MASK,
29386 IX86_BUILTIN_PMULHUW256_MASK,
29387 IX86_BUILTIN_PMULHW256_MASK,
29388 IX86_BUILTIN_PMULHW128_MASK,
29389 IX86_BUILTIN_PMULLW256_MASK,
29390 IX86_BUILTIN_PMULLW128_MASK,
29391 IX86_BUILTIN_PMULLQ256,
29392 IX86_BUILTIN_PMULLQ128,
29393 IX86_BUILTIN_ANDPD256_MASK,
29394 IX86_BUILTIN_ANDPD128_MASK,
29395 IX86_BUILTIN_ANDPS256_MASK,
29396 IX86_BUILTIN_ANDPS128_MASK,
29397 IX86_BUILTIN_ANDNPD256_MASK,
29398 IX86_BUILTIN_ANDNPD128_MASK,
29399 IX86_BUILTIN_ANDNPS256_MASK,
29400 IX86_BUILTIN_ANDNPS128_MASK,
29401 IX86_BUILTIN_PSLLWI128_MASK,
29402 IX86_BUILTIN_PSLLDI128_MASK,
29403 IX86_BUILTIN_PSLLQI128_MASK,
29404 IX86_BUILTIN_PSLLW128_MASK,
29405 IX86_BUILTIN_PSLLD128_MASK,
29406 IX86_BUILTIN_PSLLQ128_MASK,
29407 IX86_BUILTIN_PSLLWI256_MASK ,
29408 IX86_BUILTIN_PSLLW256_MASK,
29409 IX86_BUILTIN_PSLLDI256_MASK,
29410 IX86_BUILTIN_PSLLD256_MASK,
29411 IX86_BUILTIN_PSLLQI256_MASK,
29412 IX86_BUILTIN_PSLLQ256_MASK,
29413 IX86_BUILTIN_PSRADI128_MASK,
29414 IX86_BUILTIN_PSRAD128_MASK,
29415 IX86_BUILTIN_PSRADI256_MASK,
29416 IX86_BUILTIN_PSRAD256_MASK,
29417 IX86_BUILTIN_PSRAQI128_MASK,
29418 IX86_BUILTIN_PSRAQ128_MASK,
29419 IX86_BUILTIN_PSRAQI256_MASK,
29420 IX86_BUILTIN_PSRAQ256_MASK,
29421 IX86_BUILTIN_PANDD256,
29422 IX86_BUILTIN_PANDD128,
29423 IX86_BUILTIN_PSRLDI128_MASK,
29424 IX86_BUILTIN_PSRLD128_MASK,
29425 IX86_BUILTIN_PSRLDI256_MASK,
29426 IX86_BUILTIN_PSRLD256_MASK,
29427 IX86_BUILTIN_PSRLQI128_MASK,
29428 IX86_BUILTIN_PSRLQ128_MASK,
29429 IX86_BUILTIN_PSRLQI256_MASK,
29430 IX86_BUILTIN_PSRLQ256_MASK,
29431 IX86_BUILTIN_PANDQ256,
29432 IX86_BUILTIN_PANDQ128,
29433 IX86_BUILTIN_PANDND256,
29434 IX86_BUILTIN_PANDND128,
29435 IX86_BUILTIN_PANDNQ256,
29436 IX86_BUILTIN_PANDNQ128,
29437 IX86_BUILTIN_PORD256,
29438 IX86_BUILTIN_PORD128,
29439 IX86_BUILTIN_PORQ256,
29440 IX86_BUILTIN_PORQ128,
29441 IX86_BUILTIN_PXORD256,
29442 IX86_BUILTIN_PXORD128,
29443 IX86_BUILTIN_PXORQ256,
29444 IX86_BUILTIN_PXORQ128,
29445 IX86_BUILTIN_PACKSSWB256_MASK,
29446 IX86_BUILTIN_PACKSSWB128_MASK,
29447 IX86_BUILTIN_PACKUSWB256_MASK,
29448 IX86_BUILTIN_PACKUSWB128_MASK,
29449 IX86_BUILTIN_RNDSCALEPS256,
29450 IX86_BUILTIN_RNDSCALEPD256,
29451 IX86_BUILTIN_RNDSCALEPS128,
29452 IX86_BUILTIN_RNDSCALEPD128,
29453 IX86_BUILTIN_VTERNLOGQ256_MASK,
29454 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29455 IX86_BUILTIN_VTERNLOGD256_MASK,
29456 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29457 IX86_BUILTIN_VTERNLOGQ128_MASK,
29458 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29459 IX86_BUILTIN_VTERNLOGD128_MASK,
29460 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29461 IX86_BUILTIN_SCALEFPD256,
29462 IX86_BUILTIN_SCALEFPS256,
29463 IX86_BUILTIN_SCALEFPD128,
29464 IX86_BUILTIN_SCALEFPS128,
29465 IX86_BUILTIN_VFMADDPD256_MASK,
29466 IX86_BUILTIN_VFMADDPD256_MASK3,
29467 IX86_BUILTIN_VFMADDPD256_MASKZ,
29468 IX86_BUILTIN_VFMADDPD128_MASK,
29469 IX86_BUILTIN_VFMADDPD128_MASK3,
29470 IX86_BUILTIN_VFMADDPD128_MASKZ,
29471 IX86_BUILTIN_VFMADDPS256_MASK,
29472 IX86_BUILTIN_VFMADDPS256_MASK3,
29473 IX86_BUILTIN_VFMADDPS256_MASKZ,
29474 IX86_BUILTIN_VFMADDPS128_MASK,
29475 IX86_BUILTIN_VFMADDPS128_MASK3,
29476 IX86_BUILTIN_VFMADDPS128_MASKZ,
29477 IX86_BUILTIN_VFMSUBPD256_MASK3,
29478 IX86_BUILTIN_VFMSUBPD128_MASK3,
29479 IX86_BUILTIN_VFMSUBPS256_MASK3,
29480 IX86_BUILTIN_VFMSUBPS128_MASK3,
29481 IX86_BUILTIN_VFNMADDPD256_MASK,
29482 IX86_BUILTIN_VFNMADDPD128_MASK,
29483 IX86_BUILTIN_VFNMADDPS256_MASK,
29484 IX86_BUILTIN_VFNMADDPS128_MASK,
29485 IX86_BUILTIN_VFNMSUBPD256_MASK,
29486 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29487 IX86_BUILTIN_VFNMSUBPD128_MASK,
29488 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29489 IX86_BUILTIN_VFNMSUBPS256_MASK,
29490 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29491 IX86_BUILTIN_VFNMSUBPS128_MASK,
29492 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29493 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29494 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29495 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29496 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29497 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29498 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29499 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29500 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29501 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29502 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29503 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29504 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29505 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29506 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29507 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29508 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29509 IX86_BUILTIN_INSERTF64X2_256,
29510 IX86_BUILTIN_INSERTI64X2_256,
29511 IX86_BUILTIN_PSRAVV16HI,
29512 IX86_BUILTIN_PSRAVV8HI,
29513 IX86_BUILTIN_PMADDUBSW256_MASK,
29514 IX86_BUILTIN_PMADDUBSW128_MASK,
29515 IX86_BUILTIN_PMADDWD256_MASK,
29516 IX86_BUILTIN_PMADDWD128_MASK,
29517 IX86_BUILTIN_PSRLVV16HI,
29518 IX86_BUILTIN_PSRLVV8HI,
29519 IX86_BUILTIN_CVTPS2DQ256_MASK,
29520 IX86_BUILTIN_CVTPS2DQ128_MASK,
29521 IX86_BUILTIN_CVTPS2UDQ256,
29522 IX86_BUILTIN_CVTPS2UDQ128,
29523 IX86_BUILTIN_CVTPS2QQ256,
29524 IX86_BUILTIN_CVTPS2QQ128,
29525 IX86_BUILTIN_CVTPS2UQQ256,
29526 IX86_BUILTIN_CVTPS2UQQ128,
29527 IX86_BUILTIN_GETMANTPS256,
29528 IX86_BUILTIN_GETMANTPS128,
29529 IX86_BUILTIN_GETMANTPD256,
29530 IX86_BUILTIN_GETMANTPD128,
29531 IX86_BUILTIN_MOVDDUP256_MASK,
29532 IX86_BUILTIN_MOVDDUP128_MASK,
29533 IX86_BUILTIN_MOVSHDUP256_MASK,
29534 IX86_BUILTIN_MOVSHDUP128_MASK,
29535 IX86_BUILTIN_MOVSLDUP256_MASK,
29536 IX86_BUILTIN_MOVSLDUP128_MASK,
29537 IX86_BUILTIN_CVTQQ2PS256,
29538 IX86_BUILTIN_CVTQQ2PS128,
29539 IX86_BUILTIN_CVTUQQ2PS256,
29540 IX86_BUILTIN_CVTUQQ2PS128,
29541 IX86_BUILTIN_CVTQQ2PD256,
29542 IX86_BUILTIN_CVTQQ2PD128,
29543 IX86_BUILTIN_CVTUQQ2PD256,
29544 IX86_BUILTIN_CVTUQQ2PD128,
29545 IX86_BUILTIN_VPERMT2VARQ256,
29546 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29547 IX86_BUILTIN_VPERMT2VARD256,
29548 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29549 IX86_BUILTIN_VPERMI2VARQ256,
29550 IX86_BUILTIN_VPERMI2VARD256,
29551 IX86_BUILTIN_VPERMT2VARPD256,
29552 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29553 IX86_BUILTIN_VPERMT2VARPS256,
29554 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29555 IX86_BUILTIN_VPERMI2VARPD256,
29556 IX86_BUILTIN_VPERMI2VARPS256,
29557 IX86_BUILTIN_VPERMT2VARQ128,
29558 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29559 IX86_BUILTIN_VPERMT2VARD128,
29560 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29561 IX86_BUILTIN_VPERMI2VARQ128,
29562 IX86_BUILTIN_VPERMI2VARD128,
29563 IX86_BUILTIN_VPERMT2VARPD128,
29564 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29565 IX86_BUILTIN_VPERMT2VARPS128,
29566 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29567 IX86_BUILTIN_VPERMI2VARPD128,
29568 IX86_BUILTIN_VPERMI2VARPS128,
29569 IX86_BUILTIN_PSHUFB256_MASK,
29570 IX86_BUILTIN_PSHUFB128_MASK,
29571 IX86_BUILTIN_PSHUFHW256_MASK,
29572 IX86_BUILTIN_PSHUFHW128_MASK,
29573 IX86_BUILTIN_PSHUFLW256_MASK,
29574 IX86_BUILTIN_PSHUFLW128_MASK,
29575 IX86_BUILTIN_PSHUFD256_MASK,
29576 IX86_BUILTIN_PSHUFD128_MASK,
29577 IX86_BUILTIN_SHUFPD256_MASK,
29578 IX86_BUILTIN_SHUFPD128_MASK,
29579 IX86_BUILTIN_SHUFPS256_MASK,
29580 IX86_BUILTIN_SHUFPS128_MASK,
29581 IX86_BUILTIN_PROLVQ256,
29582 IX86_BUILTIN_PROLVQ128,
29583 IX86_BUILTIN_PROLQ256,
29584 IX86_BUILTIN_PROLQ128,
29585 IX86_BUILTIN_PRORVQ256,
29586 IX86_BUILTIN_PRORVQ128,
29587 IX86_BUILTIN_PRORQ256,
29588 IX86_BUILTIN_PRORQ128,
29589 IX86_BUILTIN_PSRAVQ128,
29590 IX86_BUILTIN_PSRAVQ256,
29591 IX86_BUILTIN_PSLLVV4DI_MASK,
29592 IX86_BUILTIN_PSLLVV2DI_MASK,
29593 IX86_BUILTIN_PSLLVV8SI_MASK,
29594 IX86_BUILTIN_PSLLVV4SI_MASK,
29595 IX86_BUILTIN_PSRAVV8SI_MASK,
29596 IX86_BUILTIN_PSRAVV4SI_MASK,
29597 IX86_BUILTIN_PSRLVV4DI_MASK,
29598 IX86_BUILTIN_PSRLVV2DI_MASK,
29599 IX86_BUILTIN_PSRLVV8SI_MASK,
29600 IX86_BUILTIN_PSRLVV4SI_MASK,
29601 IX86_BUILTIN_PSRAWI256_MASK,
29602 IX86_BUILTIN_PSRAW256_MASK,
29603 IX86_BUILTIN_PSRAWI128_MASK,
29604 IX86_BUILTIN_PSRAW128_MASK,
29605 IX86_BUILTIN_PSRLWI256_MASK,
29606 IX86_BUILTIN_PSRLW256_MASK,
29607 IX86_BUILTIN_PSRLWI128_MASK,
29608 IX86_BUILTIN_PSRLW128_MASK,
29609 IX86_BUILTIN_PRORVD256,
29610 IX86_BUILTIN_PROLVD256,
29611 IX86_BUILTIN_PRORD256,
29612 IX86_BUILTIN_PROLD256,
29613 IX86_BUILTIN_PRORVD128,
29614 IX86_BUILTIN_PROLVD128,
29615 IX86_BUILTIN_PRORD128,
29616 IX86_BUILTIN_PROLD128,
29617 IX86_BUILTIN_FPCLASSPD256,
29618 IX86_BUILTIN_FPCLASSPD128,
29619 IX86_BUILTIN_FPCLASSSD,
29620 IX86_BUILTIN_FPCLASSPS256,
29621 IX86_BUILTIN_FPCLASSPS128,
29622 IX86_BUILTIN_FPCLASSSS,
29623 IX86_BUILTIN_CVTB2MASK128,
29624 IX86_BUILTIN_CVTB2MASK256,
29625 IX86_BUILTIN_CVTW2MASK128,
29626 IX86_BUILTIN_CVTW2MASK256,
29627 IX86_BUILTIN_CVTD2MASK128,
29628 IX86_BUILTIN_CVTD2MASK256,
29629 IX86_BUILTIN_CVTQ2MASK128,
29630 IX86_BUILTIN_CVTQ2MASK256,
29631 IX86_BUILTIN_CVTMASK2B128,
29632 IX86_BUILTIN_CVTMASK2B256,
29633 IX86_BUILTIN_CVTMASK2W128,
29634 IX86_BUILTIN_CVTMASK2W256,
29635 IX86_BUILTIN_CVTMASK2D128,
29636 IX86_BUILTIN_CVTMASK2D256,
29637 IX86_BUILTIN_CVTMASK2Q128,
29638 IX86_BUILTIN_CVTMASK2Q256,
29639 IX86_BUILTIN_PCMPEQB128_MASK,
29640 IX86_BUILTIN_PCMPEQB256_MASK,
29641 IX86_BUILTIN_PCMPEQW128_MASK,
29642 IX86_BUILTIN_PCMPEQW256_MASK,
29643 IX86_BUILTIN_PCMPEQD128_MASK,
29644 IX86_BUILTIN_PCMPEQD256_MASK,
29645 IX86_BUILTIN_PCMPEQQ128_MASK,
29646 IX86_BUILTIN_PCMPEQQ256_MASK,
29647 IX86_BUILTIN_PCMPGTB128_MASK,
29648 IX86_BUILTIN_PCMPGTB256_MASK,
29649 IX86_BUILTIN_PCMPGTW128_MASK,
29650 IX86_BUILTIN_PCMPGTW256_MASK,
29651 IX86_BUILTIN_PCMPGTD128_MASK,
29652 IX86_BUILTIN_PCMPGTD256_MASK,
29653 IX86_BUILTIN_PCMPGTQ128_MASK,
29654 IX86_BUILTIN_PCMPGTQ256_MASK,
29655 IX86_BUILTIN_PTESTMB128,
29656 IX86_BUILTIN_PTESTMB256,
29657 IX86_BUILTIN_PTESTMW128,
29658 IX86_BUILTIN_PTESTMW256,
29659 IX86_BUILTIN_PTESTMD128,
29660 IX86_BUILTIN_PTESTMD256,
29661 IX86_BUILTIN_PTESTMQ128,
29662 IX86_BUILTIN_PTESTMQ256,
29663 IX86_BUILTIN_PTESTNMB128,
29664 IX86_BUILTIN_PTESTNMB256,
29665 IX86_BUILTIN_PTESTNMW128,
29666 IX86_BUILTIN_PTESTNMW256,
29667 IX86_BUILTIN_PTESTNMD128,
29668 IX86_BUILTIN_PTESTNMD256,
29669 IX86_BUILTIN_PTESTNMQ128,
29670 IX86_BUILTIN_PTESTNMQ256,
29671 IX86_BUILTIN_PBROADCASTMB128,
29672 IX86_BUILTIN_PBROADCASTMB256,
29673 IX86_BUILTIN_PBROADCASTMW128,
29674 IX86_BUILTIN_PBROADCASTMW256,
29675 IX86_BUILTIN_COMPRESSPD256,
29676 IX86_BUILTIN_COMPRESSPD128,
29677 IX86_BUILTIN_COMPRESSPS256,
29678 IX86_BUILTIN_COMPRESSPS128,
29679 IX86_BUILTIN_PCOMPRESSQ256,
29680 IX86_BUILTIN_PCOMPRESSQ128,
29681 IX86_BUILTIN_PCOMPRESSD256,
29682 IX86_BUILTIN_PCOMPRESSD128,
29683 IX86_BUILTIN_EXPANDPD256,
29684 IX86_BUILTIN_EXPANDPD128,
29685 IX86_BUILTIN_EXPANDPS256,
29686 IX86_BUILTIN_EXPANDPS128,
29687 IX86_BUILTIN_PEXPANDQ256,
29688 IX86_BUILTIN_PEXPANDQ128,
29689 IX86_BUILTIN_PEXPANDD256,
29690 IX86_BUILTIN_PEXPANDD128,
29691 IX86_BUILTIN_EXPANDPD256Z,
29692 IX86_BUILTIN_EXPANDPD128Z,
29693 IX86_BUILTIN_EXPANDPS256Z,
29694 IX86_BUILTIN_EXPANDPS128Z,
29695 IX86_BUILTIN_PEXPANDQ256Z,
29696 IX86_BUILTIN_PEXPANDQ128Z,
29697 IX86_BUILTIN_PEXPANDD256Z,
29698 IX86_BUILTIN_PEXPANDD128Z,
29699 IX86_BUILTIN_PMAXSD256_MASK,
29700 IX86_BUILTIN_PMINSD256_MASK,
29701 IX86_BUILTIN_PMAXUD256_MASK,
29702 IX86_BUILTIN_PMINUD256_MASK,
29703 IX86_BUILTIN_PMAXSD128_MASK,
29704 IX86_BUILTIN_PMINSD128_MASK,
29705 IX86_BUILTIN_PMAXUD128_MASK,
29706 IX86_BUILTIN_PMINUD128_MASK,
29707 IX86_BUILTIN_PMAXSQ256_MASK,
29708 IX86_BUILTIN_PMINSQ256_MASK,
29709 IX86_BUILTIN_PMAXUQ256_MASK,
29710 IX86_BUILTIN_PMINUQ256_MASK,
29711 IX86_BUILTIN_PMAXSQ128_MASK,
29712 IX86_BUILTIN_PMINSQ128_MASK,
29713 IX86_BUILTIN_PMAXUQ128_MASK,
29714 IX86_BUILTIN_PMINUQ128_MASK,
29715 IX86_BUILTIN_PMINSB256_MASK,
29716 IX86_BUILTIN_PMINUB256_MASK,
29717 IX86_BUILTIN_PMAXSB256_MASK,
29718 IX86_BUILTIN_PMAXUB256_MASK,
29719 IX86_BUILTIN_PMINSB128_MASK,
29720 IX86_BUILTIN_PMINUB128_MASK,
29721 IX86_BUILTIN_PMAXSB128_MASK,
29722 IX86_BUILTIN_PMAXUB128_MASK,
29723 IX86_BUILTIN_PMINSW256_MASK,
29724 IX86_BUILTIN_PMINUW256_MASK,
29725 IX86_BUILTIN_PMAXSW256_MASK,
29726 IX86_BUILTIN_PMAXUW256_MASK,
29727 IX86_BUILTIN_PMINSW128_MASK,
29728 IX86_BUILTIN_PMINUW128_MASK,
29729 IX86_BUILTIN_PMAXSW128_MASK,
29730 IX86_BUILTIN_PMAXUW128_MASK,
29731 IX86_BUILTIN_VPCONFLICTQ256,
29732 IX86_BUILTIN_VPCONFLICTD256,
29733 IX86_BUILTIN_VPCLZCNTQ256,
29734 IX86_BUILTIN_VPCLZCNTD256,
29735 IX86_BUILTIN_UNPCKHPD256_MASK,
29736 IX86_BUILTIN_UNPCKHPD128_MASK,
29737 IX86_BUILTIN_UNPCKHPS256_MASK,
29738 IX86_BUILTIN_UNPCKHPS128_MASK,
29739 IX86_BUILTIN_UNPCKLPD256_MASK,
29740 IX86_BUILTIN_UNPCKLPD128_MASK,
29741 IX86_BUILTIN_UNPCKLPS256_MASK,
29742 IX86_BUILTIN_VPCONFLICTQ128,
29743 IX86_BUILTIN_VPCONFLICTD128,
29744 IX86_BUILTIN_VPCLZCNTQ128,
29745 IX86_BUILTIN_VPCLZCNTD128,
29746 IX86_BUILTIN_UNPCKLPS128_MASK,
29747 IX86_BUILTIN_ALIGND256,
29748 IX86_BUILTIN_ALIGNQ256,
29749 IX86_BUILTIN_ALIGND128,
29750 IX86_BUILTIN_ALIGNQ128,
29751 IX86_BUILTIN_CVTPS2PH256_MASK,
29752 IX86_BUILTIN_CVTPS2PH_MASK,
29753 IX86_BUILTIN_CVTPH2PS_MASK,
29754 IX86_BUILTIN_CVTPH2PS256_MASK,
29755 IX86_BUILTIN_PUNPCKHDQ128_MASK,
29756 IX86_BUILTIN_PUNPCKHDQ256_MASK,
29757 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
29758 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
29759 IX86_BUILTIN_PUNPCKLDQ128_MASK,
29760 IX86_BUILTIN_PUNPCKLDQ256_MASK,
29761 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
29762 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
29763 IX86_BUILTIN_PUNPCKHBW128_MASK,
29764 IX86_BUILTIN_PUNPCKHBW256_MASK,
29765 IX86_BUILTIN_PUNPCKHWD128_MASK,
29766 IX86_BUILTIN_PUNPCKHWD256_MASK,
29767 IX86_BUILTIN_PUNPCKLBW128_MASK,
29768 IX86_BUILTIN_PUNPCKLBW256_MASK,
29769 IX86_BUILTIN_PUNPCKLWD128_MASK,
29770 IX86_BUILTIN_PUNPCKLWD256_MASK,
29771 IX86_BUILTIN_PSLLVV16HI,
29772 IX86_BUILTIN_PSLLVV8HI,
29773 IX86_BUILTIN_PACKSSDW256_MASK,
29774 IX86_BUILTIN_PACKSSDW128_MASK,
29775 IX86_BUILTIN_PACKUSDW256_MASK,
29776 IX86_BUILTIN_PACKUSDW128_MASK,
29777 IX86_BUILTIN_PAVGB256_MASK,
29778 IX86_BUILTIN_PAVGW256_MASK,
29779 IX86_BUILTIN_PAVGB128_MASK,
29780 IX86_BUILTIN_PAVGW128_MASK,
29781 IX86_BUILTIN_VPERMVARSF256_MASK,
29782 IX86_BUILTIN_VPERMVARDF256_MASK,
29783 IX86_BUILTIN_VPERMDF256_MASK,
29784 IX86_BUILTIN_PABSB256_MASK,
29785 IX86_BUILTIN_PABSB128_MASK,
29786 IX86_BUILTIN_PABSW256_MASK,
29787 IX86_BUILTIN_PABSW128_MASK,
29788 IX86_BUILTIN_VPERMILVARPD_MASK,
29789 IX86_BUILTIN_VPERMILVARPS_MASK,
29790 IX86_BUILTIN_VPERMILVARPD256_MASK,
29791 IX86_BUILTIN_VPERMILVARPS256_MASK,
29792 IX86_BUILTIN_VPERMILPD_MASK,
29793 IX86_BUILTIN_VPERMILPS_MASK,
29794 IX86_BUILTIN_VPERMILPD256_MASK,
29795 IX86_BUILTIN_VPERMILPS256_MASK,
29796 IX86_BUILTIN_BLENDMQ256,
29797 IX86_BUILTIN_BLENDMD256,
29798 IX86_BUILTIN_BLENDMPD256,
29799 IX86_BUILTIN_BLENDMPS256,
29800 IX86_BUILTIN_BLENDMQ128,
29801 IX86_BUILTIN_BLENDMD128,
29802 IX86_BUILTIN_BLENDMPD128,
29803 IX86_BUILTIN_BLENDMPS128,
29804 IX86_BUILTIN_BLENDMW256,
29805 IX86_BUILTIN_BLENDMB256,
29806 IX86_BUILTIN_BLENDMW128,
29807 IX86_BUILTIN_BLENDMB128,
29808 IX86_BUILTIN_PMULLD256_MASK,
29809 IX86_BUILTIN_PMULLD128_MASK,
29810 IX86_BUILTIN_PMULUDQ256_MASK,
29811 IX86_BUILTIN_PMULDQ256_MASK,
29812 IX86_BUILTIN_PMULDQ128_MASK,
29813 IX86_BUILTIN_PMULUDQ128_MASK,
29814 IX86_BUILTIN_CVTPD2PS256_MASK,
29815 IX86_BUILTIN_CVTPD2PS_MASK,
29816 IX86_BUILTIN_VPERMVARSI256_MASK,
29817 IX86_BUILTIN_VPERMVARDI256_MASK,
29818 IX86_BUILTIN_VPERMDI256_MASK,
29819 IX86_BUILTIN_CMPQ256,
29820 IX86_BUILTIN_CMPD256,
29821 IX86_BUILTIN_UCMPQ256,
29822 IX86_BUILTIN_UCMPD256,
29823 IX86_BUILTIN_CMPB256,
29824 IX86_BUILTIN_CMPW256,
29825 IX86_BUILTIN_UCMPB256,
29826 IX86_BUILTIN_UCMPW256,
29827 IX86_BUILTIN_CMPPD256_MASK,
29828 IX86_BUILTIN_CMPPS256_MASK,
29829 IX86_BUILTIN_CMPQ128,
29830 IX86_BUILTIN_CMPD128,
29831 IX86_BUILTIN_UCMPQ128,
29832 IX86_BUILTIN_UCMPD128,
29833 IX86_BUILTIN_CMPB128,
29834 IX86_BUILTIN_CMPW128,
29835 IX86_BUILTIN_UCMPB128,
29836 IX86_BUILTIN_UCMPW128,
29837 IX86_BUILTIN_CMPPD128_MASK,
29838 IX86_BUILTIN_CMPPS128_MASK,
29840 IX86_BUILTIN_GATHER3SIV8SF,
29841 IX86_BUILTIN_GATHER3SIV4SF,
29842 IX86_BUILTIN_GATHER3SIV4DF,
29843 IX86_BUILTIN_GATHER3SIV2DF,
29844 IX86_BUILTIN_GATHER3DIV8SF,
29845 IX86_BUILTIN_GATHER3DIV4SF,
29846 IX86_BUILTIN_GATHER3DIV4DF,
29847 IX86_BUILTIN_GATHER3DIV2DF,
29848 IX86_BUILTIN_GATHER3SIV8SI,
29849 IX86_BUILTIN_GATHER3SIV4SI,
29850 IX86_BUILTIN_GATHER3SIV4DI,
29851 IX86_BUILTIN_GATHER3SIV2DI,
29852 IX86_BUILTIN_GATHER3DIV8SI,
29853 IX86_BUILTIN_GATHER3DIV4SI,
29854 IX86_BUILTIN_GATHER3DIV4DI,
29855 IX86_BUILTIN_GATHER3DIV2DI,
29856 IX86_BUILTIN_SCATTERSIV8SF,
29857 IX86_BUILTIN_SCATTERSIV4SF,
29858 IX86_BUILTIN_SCATTERSIV4DF,
29859 IX86_BUILTIN_SCATTERSIV2DF,
29860 IX86_BUILTIN_SCATTERDIV8SF,
29861 IX86_BUILTIN_SCATTERDIV4SF,
29862 IX86_BUILTIN_SCATTERDIV4DF,
29863 IX86_BUILTIN_SCATTERDIV2DF,
29864 IX86_BUILTIN_SCATTERSIV8SI,
29865 IX86_BUILTIN_SCATTERSIV4SI,
29866 IX86_BUILTIN_SCATTERSIV4DI,
29867 IX86_BUILTIN_SCATTERSIV2DI,
29868 IX86_BUILTIN_SCATTERDIV8SI,
29869 IX86_BUILTIN_SCATTERDIV4SI,
29870 IX86_BUILTIN_SCATTERDIV4DI,
29871 IX86_BUILTIN_SCATTERDIV2DI,
29873 /* AVX512DQ. */
29874 IX86_BUILTIN_RANGESD128,
29875 IX86_BUILTIN_RANGESS128,
29876 IX86_BUILTIN_KUNPCKWD,
29877 IX86_BUILTIN_KUNPCKDQ,
29878 IX86_BUILTIN_BROADCASTF32x2_512,
29879 IX86_BUILTIN_BROADCASTI32x2_512,
29880 IX86_BUILTIN_BROADCASTF64X2_512,
29881 IX86_BUILTIN_BROADCASTI64X2_512,
29882 IX86_BUILTIN_BROADCASTF32X8_512,
29883 IX86_BUILTIN_BROADCASTI32X8_512,
29884 IX86_BUILTIN_EXTRACTF64X2_512,
29885 IX86_BUILTIN_EXTRACTF32X8,
29886 IX86_BUILTIN_EXTRACTI64X2_512,
29887 IX86_BUILTIN_EXTRACTI32X8,
29888 IX86_BUILTIN_REDUCEPD512_MASK,
29889 IX86_BUILTIN_REDUCEPS512_MASK,
29890 IX86_BUILTIN_PMULLQ512,
29891 IX86_BUILTIN_XORPD512,
29892 IX86_BUILTIN_XORPS512,
29893 IX86_BUILTIN_ORPD512,
29894 IX86_BUILTIN_ORPS512,
29895 IX86_BUILTIN_ANDPD512,
29896 IX86_BUILTIN_ANDPS512,
29897 IX86_BUILTIN_ANDNPD512,
29898 IX86_BUILTIN_ANDNPS512,
29899 IX86_BUILTIN_INSERTF32X8,
29900 IX86_BUILTIN_INSERTI32X8,
29901 IX86_BUILTIN_INSERTF64X2_512,
29902 IX86_BUILTIN_INSERTI64X2_512,
29903 IX86_BUILTIN_FPCLASSPD512,
29904 IX86_BUILTIN_FPCLASSPS512,
29905 IX86_BUILTIN_CVTD2MASK512,
29906 IX86_BUILTIN_CVTQ2MASK512,
29907 IX86_BUILTIN_CVTMASK2D512,
29908 IX86_BUILTIN_CVTMASK2Q512,
29909 IX86_BUILTIN_CVTPD2QQ512,
29910 IX86_BUILTIN_CVTPS2QQ512,
29911 IX86_BUILTIN_CVTPD2UQQ512,
29912 IX86_BUILTIN_CVTPS2UQQ512,
29913 IX86_BUILTIN_CVTQQ2PS512,
29914 IX86_BUILTIN_CVTUQQ2PS512,
29915 IX86_BUILTIN_CVTQQ2PD512,
29916 IX86_BUILTIN_CVTUQQ2PD512,
29917 IX86_BUILTIN_CVTTPS2QQ512,
29918 IX86_BUILTIN_CVTTPS2UQQ512,
29919 IX86_BUILTIN_CVTTPD2QQ512,
29920 IX86_BUILTIN_CVTTPD2UQQ512,
29921 IX86_BUILTIN_RANGEPS512,
29922 IX86_BUILTIN_RANGEPD512,
29924 /* AVX512BW. */
29925 IX86_BUILTIN_PACKUSDW512,
29926 IX86_BUILTIN_PACKSSDW512,
29927 IX86_BUILTIN_LOADDQUHI512_MASK,
29928 IX86_BUILTIN_LOADDQUQI512_MASK,
29929 IX86_BUILTIN_PSLLDQ512,
29930 IX86_BUILTIN_PSRLDQ512,
29931 IX86_BUILTIN_STOREDQUHI512_MASK,
29932 IX86_BUILTIN_STOREDQUQI512_MASK,
29933 IX86_BUILTIN_PALIGNR512,
29934 IX86_BUILTIN_PALIGNR512_MASK,
29935 IX86_BUILTIN_MOVDQUHI512_MASK,
29936 IX86_BUILTIN_MOVDQUQI512_MASK,
29937 IX86_BUILTIN_PSADBW512,
29938 IX86_BUILTIN_DBPSADBW512,
29939 IX86_BUILTIN_PBROADCASTB512,
29940 IX86_BUILTIN_PBROADCASTB512_GPR,
29941 IX86_BUILTIN_PBROADCASTW512,
29942 IX86_BUILTIN_PBROADCASTW512_GPR,
29943 IX86_BUILTIN_PMOVSXBW512_MASK,
29944 IX86_BUILTIN_PMOVZXBW512_MASK,
29945 IX86_BUILTIN_VPERMVARHI512_MASK,
29946 IX86_BUILTIN_VPERMT2VARHI512,
29947 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
29948 IX86_BUILTIN_VPERMI2VARHI512,
29949 IX86_BUILTIN_PAVGB512,
29950 IX86_BUILTIN_PAVGW512,
29951 IX86_BUILTIN_PADDB512,
29952 IX86_BUILTIN_PSUBB512,
29953 IX86_BUILTIN_PSUBSB512,
29954 IX86_BUILTIN_PADDSB512,
29955 IX86_BUILTIN_PSUBUSB512,
29956 IX86_BUILTIN_PADDUSB512,
29957 IX86_BUILTIN_PSUBW512,
29958 IX86_BUILTIN_PADDW512,
29959 IX86_BUILTIN_PSUBSW512,
29960 IX86_BUILTIN_PADDSW512,
29961 IX86_BUILTIN_PSUBUSW512,
29962 IX86_BUILTIN_PADDUSW512,
29963 IX86_BUILTIN_PMAXUW512,
29964 IX86_BUILTIN_PMAXSW512,
29965 IX86_BUILTIN_PMINUW512,
29966 IX86_BUILTIN_PMINSW512,
29967 IX86_BUILTIN_PMAXUB512,
29968 IX86_BUILTIN_PMAXSB512,
29969 IX86_BUILTIN_PMINUB512,
29970 IX86_BUILTIN_PMINSB512,
29971 IX86_BUILTIN_PMOVWB512,
29972 IX86_BUILTIN_PMOVSWB512,
29973 IX86_BUILTIN_PMOVUSWB512,
29974 IX86_BUILTIN_PMULHRSW512_MASK,
29975 IX86_BUILTIN_PMULHUW512_MASK,
29976 IX86_BUILTIN_PMULHW512_MASK,
29977 IX86_BUILTIN_PMULLW512_MASK,
29978 IX86_BUILTIN_PSLLWI512_MASK,
29979 IX86_BUILTIN_PSLLW512_MASK,
29980 IX86_BUILTIN_PACKSSWB512,
29981 IX86_BUILTIN_PACKUSWB512,
29982 IX86_BUILTIN_PSRAVV32HI,
29983 IX86_BUILTIN_PMADDUBSW512_MASK,
29984 IX86_BUILTIN_PMADDWD512_MASK,
29985 IX86_BUILTIN_PSRLVV32HI,
29986 IX86_BUILTIN_PUNPCKHBW512,
29987 IX86_BUILTIN_PUNPCKHWD512,
29988 IX86_BUILTIN_PUNPCKLBW512,
29989 IX86_BUILTIN_PUNPCKLWD512,
29990 IX86_BUILTIN_PSHUFB512,
29991 IX86_BUILTIN_PSHUFHW512,
29992 IX86_BUILTIN_PSHUFLW512,
29993 IX86_BUILTIN_PSRAWI512,
29994 IX86_BUILTIN_PSRAW512,
29995 IX86_BUILTIN_PSRLWI512,
29996 IX86_BUILTIN_PSRLW512,
29997 IX86_BUILTIN_CVTB2MASK512,
29998 IX86_BUILTIN_CVTW2MASK512,
29999 IX86_BUILTIN_CVTMASK2B512,
30000 IX86_BUILTIN_CVTMASK2W512,
30001 IX86_BUILTIN_PCMPEQB512_MASK,
30002 IX86_BUILTIN_PCMPEQW512_MASK,
30003 IX86_BUILTIN_PCMPGTB512_MASK,
30004 IX86_BUILTIN_PCMPGTW512_MASK,
30005 IX86_BUILTIN_PTESTMB512,
30006 IX86_BUILTIN_PTESTMW512,
30007 IX86_BUILTIN_PTESTNMB512,
30008 IX86_BUILTIN_PTESTNMW512,
30009 IX86_BUILTIN_PSLLVV32HI,
30010 IX86_BUILTIN_PABSB512,
30011 IX86_BUILTIN_PABSW512,
30012 IX86_BUILTIN_BLENDMW512,
30013 IX86_BUILTIN_BLENDMB512,
30014 IX86_BUILTIN_CMPB512,
30015 IX86_BUILTIN_CMPW512,
30016 IX86_BUILTIN_UCMPB512,
30017 IX86_BUILTIN_UCMPW512,
30019 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30020 where all operands are 32-byte or 64-byte wide respectively. */
30021 IX86_BUILTIN_GATHERALTSIV4DF,
30022 IX86_BUILTIN_GATHERALTDIV8SF,
30023 IX86_BUILTIN_GATHERALTSIV4DI,
30024 IX86_BUILTIN_GATHERALTDIV8SI,
30025 IX86_BUILTIN_GATHER3ALTDIV16SF,
30026 IX86_BUILTIN_GATHER3ALTDIV16SI,
30027 IX86_BUILTIN_GATHER3ALTSIV4DF,
30028 IX86_BUILTIN_GATHER3ALTDIV8SF,
30029 IX86_BUILTIN_GATHER3ALTSIV4DI,
30030 IX86_BUILTIN_GATHER3ALTDIV8SI,
30031 IX86_BUILTIN_GATHER3ALTSIV8DF,
30032 IX86_BUILTIN_GATHER3ALTSIV8DI,
30033 IX86_BUILTIN_GATHER3DIV16SF,
30034 IX86_BUILTIN_GATHER3DIV16SI,
30035 IX86_BUILTIN_GATHER3DIV8DF,
30036 IX86_BUILTIN_GATHER3DIV8DI,
30037 IX86_BUILTIN_GATHER3SIV16SF,
30038 IX86_BUILTIN_GATHER3SIV16SI,
30039 IX86_BUILTIN_GATHER3SIV8DF,
30040 IX86_BUILTIN_GATHER3SIV8DI,
30041 IX86_BUILTIN_SCATTERDIV16SF,
30042 IX86_BUILTIN_SCATTERDIV16SI,
30043 IX86_BUILTIN_SCATTERDIV8DF,
30044 IX86_BUILTIN_SCATTERDIV8DI,
30045 IX86_BUILTIN_SCATTERSIV16SF,
30046 IX86_BUILTIN_SCATTERSIV16SI,
30047 IX86_BUILTIN_SCATTERSIV8DF,
30048 IX86_BUILTIN_SCATTERSIV8DI,
30050 /* AVX512PF */
30051 IX86_BUILTIN_GATHERPFQPD,
30052 IX86_BUILTIN_GATHERPFDPS,
30053 IX86_BUILTIN_GATHERPFDPD,
30054 IX86_BUILTIN_GATHERPFQPS,
30055 IX86_BUILTIN_SCATTERPFDPD,
30056 IX86_BUILTIN_SCATTERPFDPS,
30057 IX86_BUILTIN_SCATTERPFQPD,
30058 IX86_BUILTIN_SCATTERPFQPS,
30060 /* AVX-512ER */
30061 IX86_BUILTIN_EXP2PD_MASK,
30062 IX86_BUILTIN_EXP2PS_MASK,
30063 IX86_BUILTIN_EXP2PS,
30064 IX86_BUILTIN_RCP28PD,
30065 IX86_BUILTIN_RCP28PS,
30066 IX86_BUILTIN_RCP28SD,
30067 IX86_BUILTIN_RCP28SS,
30068 IX86_BUILTIN_RSQRT28PD,
30069 IX86_BUILTIN_RSQRT28PS,
30070 IX86_BUILTIN_RSQRT28SD,
30071 IX86_BUILTIN_RSQRT28SS,
30073 /* SHA builtins. */
30074 IX86_BUILTIN_SHA1MSG1,
30075 IX86_BUILTIN_SHA1MSG2,
30076 IX86_BUILTIN_SHA1NEXTE,
30077 IX86_BUILTIN_SHA1RNDS4,
30078 IX86_BUILTIN_SHA256MSG1,
30079 IX86_BUILTIN_SHA256MSG2,
30080 IX86_BUILTIN_SHA256RNDS2,
30082 /* CLFLUSHOPT instructions. */
30083 IX86_BUILTIN_CLFLUSHOPT,
30085 /* TFmode support builtins. */
30086 IX86_BUILTIN_INFQ,
30087 IX86_BUILTIN_HUGE_VALQ,
30088 IX86_BUILTIN_FABSQ,
30089 IX86_BUILTIN_COPYSIGNQ,
30091 /* Vectorizer support builtins. */
30092 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30093 IX86_BUILTIN_CPYSGNPS,
30094 IX86_BUILTIN_CPYSGNPD,
30095 IX86_BUILTIN_CPYSGNPS256,
30096 IX86_BUILTIN_CPYSGNPS512,
30097 IX86_BUILTIN_CPYSGNPD256,
30098 IX86_BUILTIN_CPYSGNPD512,
30099 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30100 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30103 /* FMA4 instructions. */
30104 IX86_BUILTIN_VFMADDSS,
30105 IX86_BUILTIN_VFMADDSD,
30106 IX86_BUILTIN_VFMADDPS,
30107 IX86_BUILTIN_VFMADDPD,
30108 IX86_BUILTIN_VFMADDPS256,
30109 IX86_BUILTIN_VFMADDPD256,
30110 IX86_BUILTIN_VFMADDSUBPS,
30111 IX86_BUILTIN_VFMADDSUBPD,
30112 IX86_BUILTIN_VFMADDSUBPS256,
30113 IX86_BUILTIN_VFMADDSUBPD256,
30115 /* FMA3 instructions. */
30116 IX86_BUILTIN_VFMADDSS3,
30117 IX86_BUILTIN_VFMADDSD3,
30119 /* XOP instructions. */
30120 IX86_BUILTIN_VPCMOV,
30121 IX86_BUILTIN_VPCMOV_V2DI,
30122 IX86_BUILTIN_VPCMOV_V4SI,
30123 IX86_BUILTIN_VPCMOV_V8HI,
30124 IX86_BUILTIN_VPCMOV_V16QI,
30125 IX86_BUILTIN_VPCMOV_V4SF,
30126 IX86_BUILTIN_VPCMOV_V2DF,
30127 IX86_BUILTIN_VPCMOV256,
30128 IX86_BUILTIN_VPCMOV_V4DI256,
30129 IX86_BUILTIN_VPCMOV_V8SI256,
30130 IX86_BUILTIN_VPCMOV_V16HI256,
30131 IX86_BUILTIN_VPCMOV_V32QI256,
30132 IX86_BUILTIN_VPCMOV_V8SF256,
30133 IX86_BUILTIN_VPCMOV_V4DF256,
30135 IX86_BUILTIN_VPPERM,
30137 IX86_BUILTIN_VPMACSSWW,
30138 IX86_BUILTIN_VPMACSWW,
30139 IX86_BUILTIN_VPMACSSWD,
30140 IX86_BUILTIN_VPMACSWD,
30141 IX86_BUILTIN_VPMACSSDD,
30142 IX86_BUILTIN_VPMACSDD,
30143 IX86_BUILTIN_VPMACSSDQL,
30144 IX86_BUILTIN_VPMACSSDQH,
30145 IX86_BUILTIN_VPMACSDQL,
30146 IX86_BUILTIN_VPMACSDQH,
30147 IX86_BUILTIN_VPMADCSSWD,
30148 IX86_BUILTIN_VPMADCSWD,
30150 IX86_BUILTIN_VPHADDBW,
30151 IX86_BUILTIN_VPHADDBD,
30152 IX86_BUILTIN_VPHADDBQ,
30153 IX86_BUILTIN_VPHADDWD,
30154 IX86_BUILTIN_VPHADDWQ,
30155 IX86_BUILTIN_VPHADDDQ,
30156 IX86_BUILTIN_VPHADDUBW,
30157 IX86_BUILTIN_VPHADDUBD,
30158 IX86_BUILTIN_VPHADDUBQ,
30159 IX86_BUILTIN_VPHADDUWD,
30160 IX86_BUILTIN_VPHADDUWQ,
30161 IX86_BUILTIN_VPHADDUDQ,
30162 IX86_BUILTIN_VPHSUBBW,
30163 IX86_BUILTIN_VPHSUBWD,
30164 IX86_BUILTIN_VPHSUBDQ,
30166 IX86_BUILTIN_VPROTB,
30167 IX86_BUILTIN_VPROTW,
30168 IX86_BUILTIN_VPROTD,
30169 IX86_BUILTIN_VPROTQ,
30170 IX86_BUILTIN_VPROTB_IMM,
30171 IX86_BUILTIN_VPROTW_IMM,
30172 IX86_BUILTIN_VPROTD_IMM,
30173 IX86_BUILTIN_VPROTQ_IMM,
30175 IX86_BUILTIN_VPSHLB,
30176 IX86_BUILTIN_VPSHLW,
30177 IX86_BUILTIN_VPSHLD,
30178 IX86_BUILTIN_VPSHLQ,
30179 IX86_BUILTIN_VPSHAB,
30180 IX86_BUILTIN_VPSHAW,
30181 IX86_BUILTIN_VPSHAD,
30182 IX86_BUILTIN_VPSHAQ,
30184 IX86_BUILTIN_VFRCZSS,
30185 IX86_BUILTIN_VFRCZSD,
30186 IX86_BUILTIN_VFRCZPS,
30187 IX86_BUILTIN_VFRCZPD,
30188 IX86_BUILTIN_VFRCZPS256,
30189 IX86_BUILTIN_VFRCZPD256,
30191 IX86_BUILTIN_VPCOMEQUB,
30192 IX86_BUILTIN_VPCOMNEUB,
30193 IX86_BUILTIN_VPCOMLTUB,
30194 IX86_BUILTIN_VPCOMLEUB,
30195 IX86_BUILTIN_VPCOMGTUB,
30196 IX86_BUILTIN_VPCOMGEUB,
30197 IX86_BUILTIN_VPCOMFALSEUB,
30198 IX86_BUILTIN_VPCOMTRUEUB,
30200 IX86_BUILTIN_VPCOMEQUW,
30201 IX86_BUILTIN_VPCOMNEUW,
30202 IX86_BUILTIN_VPCOMLTUW,
30203 IX86_BUILTIN_VPCOMLEUW,
30204 IX86_BUILTIN_VPCOMGTUW,
30205 IX86_BUILTIN_VPCOMGEUW,
30206 IX86_BUILTIN_VPCOMFALSEUW,
30207 IX86_BUILTIN_VPCOMTRUEUW,
30209 IX86_BUILTIN_VPCOMEQUD,
30210 IX86_BUILTIN_VPCOMNEUD,
30211 IX86_BUILTIN_VPCOMLTUD,
30212 IX86_BUILTIN_VPCOMLEUD,
30213 IX86_BUILTIN_VPCOMGTUD,
30214 IX86_BUILTIN_VPCOMGEUD,
30215 IX86_BUILTIN_VPCOMFALSEUD,
30216 IX86_BUILTIN_VPCOMTRUEUD,
30218 IX86_BUILTIN_VPCOMEQUQ,
30219 IX86_BUILTIN_VPCOMNEUQ,
30220 IX86_BUILTIN_VPCOMLTUQ,
30221 IX86_BUILTIN_VPCOMLEUQ,
30222 IX86_BUILTIN_VPCOMGTUQ,
30223 IX86_BUILTIN_VPCOMGEUQ,
30224 IX86_BUILTIN_VPCOMFALSEUQ,
30225 IX86_BUILTIN_VPCOMTRUEUQ,
30227 IX86_BUILTIN_VPCOMEQB,
30228 IX86_BUILTIN_VPCOMNEB,
30229 IX86_BUILTIN_VPCOMLTB,
30230 IX86_BUILTIN_VPCOMLEB,
30231 IX86_BUILTIN_VPCOMGTB,
30232 IX86_BUILTIN_VPCOMGEB,
30233 IX86_BUILTIN_VPCOMFALSEB,
30234 IX86_BUILTIN_VPCOMTRUEB,
30236 IX86_BUILTIN_VPCOMEQW,
30237 IX86_BUILTIN_VPCOMNEW,
30238 IX86_BUILTIN_VPCOMLTW,
30239 IX86_BUILTIN_VPCOMLEW,
30240 IX86_BUILTIN_VPCOMGTW,
30241 IX86_BUILTIN_VPCOMGEW,
30242 IX86_BUILTIN_VPCOMFALSEW,
30243 IX86_BUILTIN_VPCOMTRUEW,
30245 IX86_BUILTIN_VPCOMEQD,
30246 IX86_BUILTIN_VPCOMNED,
30247 IX86_BUILTIN_VPCOMLTD,
30248 IX86_BUILTIN_VPCOMLED,
30249 IX86_BUILTIN_VPCOMGTD,
30250 IX86_BUILTIN_VPCOMGED,
30251 IX86_BUILTIN_VPCOMFALSED,
30252 IX86_BUILTIN_VPCOMTRUED,
30254 IX86_BUILTIN_VPCOMEQQ,
30255 IX86_BUILTIN_VPCOMNEQ,
30256 IX86_BUILTIN_VPCOMLTQ,
30257 IX86_BUILTIN_VPCOMLEQ,
30258 IX86_BUILTIN_VPCOMGTQ,
30259 IX86_BUILTIN_VPCOMGEQ,
30260 IX86_BUILTIN_VPCOMFALSEQ,
30261 IX86_BUILTIN_VPCOMTRUEQ,
30263 /* LWP instructions. */
30264 IX86_BUILTIN_LLWPCB,
30265 IX86_BUILTIN_SLWPCB,
30266 IX86_BUILTIN_LWPVAL32,
30267 IX86_BUILTIN_LWPVAL64,
30268 IX86_BUILTIN_LWPINS32,
30269 IX86_BUILTIN_LWPINS64,
30271 IX86_BUILTIN_CLZS,
30273 /* RTM */
30274 IX86_BUILTIN_XBEGIN,
30275 IX86_BUILTIN_XEND,
30276 IX86_BUILTIN_XABORT,
30277 IX86_BUILTIN_XTEST,
30279 /* MPX */
30280 IX86_BUILTIN_BNDMK,
30281 IX86_BUILTIN_BNDSTX,
30282 IX86_BUILTIN_BNDLDX,
30283 IX86_BUILTIN_BNDCL,
30284 IX86_BUILTIN_BNDCU,
30285 IX86_BUILTIN_BNDRET,
30286 IX86_BUILTIN_BNDNARROW,
30287 IX86_BUILTIN_BNDINT,
30288 IX86_BUILTIN_SIZEOF,
30289 IX86_BUILTIN_BNDLOWER,
30290 IX86_BUILTIN_BNDUPPER,
30292 /* BMI instructions. */
30293 IX86_BUILTIN_BEXTR32,
30294 IX86_BUILTIN_BEXTR64,
30295 IX86_BUILTIN_CTZS,
30297 /* TBM instructions. */
30298 IX86_BUILTIN_BEXTRI32,
30299 IX86_BUILTIN_BEXTRI64,
30301 /* BMI2 instructions. */
30302 IX86_BUILTIN_BZHI32,
30303 IX86_BUILTIN_BZHI64,
30304 IX86_BUILTIN_PDEP32,
30305 IX86_BUILTIN_PDEP64,
30306 IX86_BUILTIN_PEXT32,
30307 IX86_BUILTIN_PEXT64,
30309 /* ADX instructions. */
30310 IX86_BUILTIN_ADDCARRYX32,
30311 IX86_BUILTIN_ADDCARRYX64,
30313 /* SBB instructions. */
30314 IX86_BUILTIN_SBB32,
30315 IX86_BUILTIN_SBB64,
30317 /* FSGSBASE instructions. */
30318 IX86_BUILTIN_RDFSBASE32,
30319 IX86_BUILTIN_RDFSBASE64,
30320 IX86_BUILTIN_RDGSBASE32,
30321 IX86_BUILTIN_RDGSBASE64,
30322 IX86_BUILTIN_WRFSBASE32,
30323 IX86_BUILTIN_WRFSBASE64,
30324 IX86_BUILTIN_WRGSBASE32,
30325 IX86_BUILTIN_WRGSBASE64,
30327 /* RDRND instructions. */
30328 IX86_BUILTIN_RDRAND16_STEP,
30329 IX86_BUILTIN_RDRAND32_STEP,
30330 IX86_BUILTIN_RDRAND64_STEP,
30332 /* RDSEED instructions. */
30333 IX86_BUILTIN_RDSEED16_STEP,
30334 IX86_BUILTIN_RDSEED32_STEP,
30335 IX86_BUILTIN_RDSEED64_STEP,
30337 /* F16C instructions. */
30338 IX86_BUILTIN_CVTPH2PS,
30339 IX86_BUILTIN_CVTPH2PS256,
30340 IX86_BUILTIN_CVTPS2PH,
30341 IX86_BUILTIN_CVTPS2PH256,
30343 /* CFString built-in for darwin */
30344 IX86_BUILTIN_CFSTRING,
30346 /* Builtins to get CPU type and supported features. */
30347 IX86_BUILTIN_CPU_INIT,
30348 IX86_BUILTIN_CPU_IS,
30349 IX86_BUILTIN_CPU_SUPPORTS,
30351 /* Read/write FLAGS register built-ins. */
30352 IX86_BUILTIN_READ_FLAGS,
30353 IX86_BUILTIN_WRITE_FLAGS,
30355 IX86_BUILTIN_MAX
30356 };
30358 /* Table for the ix86 builtin decls. */
30361 /* Table of all of the builtin functions that are possible with different ISA's
30362 but are waiting to be built until a function is declared to use that
30363 ISA. */
30372 };
30377 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30378 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30379 function decl in the ix86_builtins array. Returns the function decl or
30380 NULL_TREE, if the builtin was not added.
30382 If the front end has a special hook for builtin functions, delay adding
30383 builtin functions that aren't in the current ISA until the ISA is changed
30384 with function specific optimization. Doing so, can save about 300K for the
30385 default compiler. When the builtin is expanded, check at that time whether
30386 it is valid.
30388 If the front end doesn't have a special hook, record all builtins, even if
30389 it isn't an instruction set in the current ISA in case the user uses
30390 function specific options for a different ISA, so that we don't get scope
30391 errors if a builtin is added in the middle of a function scope. */
30397 {
30401 {
30410 {
30416 }
30417 else
30418 {
30426 }
30427 }
30430 }
30432 /* Like def_builtin, but also marks the function decl "const". */
30437 {
30441 else
30445 }
30447 /* Add any new builtin functions for a given ISA that may not have been
30448 declared. This saves a bit of space compared to adding all of the
30449 declarations to the tree, even if we didn't use them. */
30451 static void
30453 {
30457 {
30460 {
30463 /* Don't define the builtin again. */
30469 NULL_TREE);
30476 NULL_TREE);
30479 }
30480 }
30481 }
30483 /* Bits for builtin_description.flag. */
30485 /* Set when we don't support the comparison natively, and should
30486 swap_comparison in order to support it. */
30487 #define BUILTIN_DESC_SWAP_OPERANDS 1
30489 struct builtin_description
30490 {
30497 };
30500 {
30501 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30502 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30503 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30504 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30505 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30506 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30507 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30508 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30509 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30510 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30511 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30512 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30513 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30514 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30515 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30517 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30518 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30519 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30522 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30523 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30524 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30525 };
30528 {
30529 /* SSE4.2 */
30530 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30531 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30532 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30533 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30534 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30535 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30536 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30537 };
30540 {
30541 /* SSE4.2 */
30542 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30543 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30544 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30545 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30546 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30547 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30548 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30549 };
30551 /* Special builtins with variable number of arguments. */
30553 {
30554 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30555 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30556 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30558 /* 80387 (for use internally for atomic compound assignment). */
30559 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30560 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30561 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30562 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30564 /* MMX */
30565 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30567 /* 3DNow! */
30568 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30570 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30571 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30572 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30573 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30574 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30575 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30576 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30577 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30578 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30580 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30581 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30582 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30583 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30584 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30585 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30586 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30587 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30589 /* SSE */
30590 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30591 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30592 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30594 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30595 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30596 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30597 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30599 /* SSE or 3DNow!A */
30600 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30601 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30603 /* SSE2 */
30604 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30605 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30606 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30607 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30608 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30609 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30610 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30611 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30612 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30613 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30615 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30616 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30618 /* SSE3 */
30619 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30621 /* SSE4.1 */
30622 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30624 /* SSE4A */
30625 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30626 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30628 /* AVX */
30629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30632 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30633 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30634 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30636 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30638 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30639 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30640 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30641 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30642 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30643 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30644 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30646 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30647 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30648 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30650 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
30651 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
30652 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
30653 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
30654 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
30655 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
30656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
30657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
30659 /* AVX2 */
30660 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
30661 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
30662 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
30663 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
30664 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
30665 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
30666 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
30667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
30668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
30670 /* AVX512F */
30671 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30672 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30673 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30674 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30675 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30676 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30677 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30678 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30679 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30680 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30681 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30682 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30683 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30684 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30685 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30686 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30687 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30688 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30689 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30690 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30691 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
30692 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
30693 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
30694 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
30695 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30696 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30697 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30698 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30699 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30700 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30701 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30702 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30703 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30704 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30705 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30706 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30707 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30708 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30709 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30710 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30711 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30712 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30713 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30714 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30715 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30716 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30717 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30719 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
30720 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
30721 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
30722 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
30723 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
30724 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
30726 /* FSGSBASE */
30727 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30728 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30729 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30730 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30731 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30732 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30733 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30734 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30736 /* RTM */
30737 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30738 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
30739 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
30741 /* AVX512BW */
30742 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
30743 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
30744 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
30745 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
30747 /* AVX512VL */
30748 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
30749 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
30750 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
30751 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
30752 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30753 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30754 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30755 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30756 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30757 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30758 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30759 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30760 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30761 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30762 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30763 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30764 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30765 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30766 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30767 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30768 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30769 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30770 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30771 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30772 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30773 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30774 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30775 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30776 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30777 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30778 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30779 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30780 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30781 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30782 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30783 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30784 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
30785 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
30786 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
30787 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
30788 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30789 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30790 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30791 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30792 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30793 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30794 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30795 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30796 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30797 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30798 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30799 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30800 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30801 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30802 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30803 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30804 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30805 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30806 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30807 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30808 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30809 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30810 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30811 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30812 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30813 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30814 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30815 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30816 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30817 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30818 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30819 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30820 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30821 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30822 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30823 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30824 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30825 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30826 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30827 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30828 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30829 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30830 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30831 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30832 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30833 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30834 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30835 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30836 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30837 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30838 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30839 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30840 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30841 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30842 };
30844 /* Builtins with variable number of arguments. */
30846 {
30847 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
30848 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
30849 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
30850 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30851 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30852 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30853 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30855 /* MMX */
30856 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30857 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30858 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30859 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30860 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30861 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30863 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30864 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30865 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30866 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30867 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30868 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30869 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30870 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30872 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30873 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30875 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30876 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30877 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30878 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30880 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30881 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30882 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30883 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30884 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30885 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30887 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30888 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30889 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30890 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30891 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
30892 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
30894 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
30895 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
30896 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
30898 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
30900 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
30901 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
30902 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
30903 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
30904 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
30905 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
30907 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
30908 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
30909 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
30910 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
30911 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
30912 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
30914 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
30915 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
30916 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
30917 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
30919 /* 3DNow! */
30920 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
30921 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
30922 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
30923 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
30925 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30926 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30927 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30928 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
30929 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
30930 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
30931 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30932 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30933 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30934 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30935 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30936 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30937 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30938 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30939 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30941 /* 3DNow!A */
30942 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
30943 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
30944 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
30945 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
30946 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30947 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30949 /* SSE */
30950 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
30951 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30952 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30953 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30954 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30955 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30956 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
30957 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
30958 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
30959 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
30960 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
30961 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
30963 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30965 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30966 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30967 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30968 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30969 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30970 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30971 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30972 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30974 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
30975 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
30976 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
30977 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
30978 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
30979 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
30980 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
30981 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
30982 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
30983 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
30984 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
30985 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
30986 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
30987 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
30988 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
30989 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
30990 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
30991 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
30992 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
30993 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
30995 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30996 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30997 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30998 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31000 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31001 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31002 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31003 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31005 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31007 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31008 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31009 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31010 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31011 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31013 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31014 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31015 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31017 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31019 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31020 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31021 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31023 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31024 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31026 /* SSE MMX or 3Dnow!A */
31027 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31028 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31029 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31031 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31032 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31033 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31034 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31036 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31037 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31039 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31041 /* SSE2 */
31042 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31044 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31045 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31046 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31047 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31048 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31050 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31051 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31052 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31053 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31054 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31056 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31058 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31059 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31060 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31061 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31063 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31064 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31065 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31067 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31068 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31069 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31070 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31071 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31072 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31073 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31074 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31076 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31077 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31078 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31079 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31080 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31081 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31082 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31083 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31084 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31085 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31086 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31087 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31088 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31089 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31090 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31091 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31092 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31093 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31094 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31095 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31097 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31098 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31099 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31100 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31102 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31103 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31104 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31105 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31107 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31109 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31110 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31111 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31113 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31115 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31116 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31117 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31118 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31119 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31120 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31121 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31122 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31124 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31125 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31126 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31127 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31128 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31129 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31130 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31131 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31133 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31134 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31136 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31137 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31138 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31139 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31141 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31142 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31144 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31145 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31146 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31147 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31148 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31149 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31151 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31152 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31153 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31154 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31156 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31157 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31158 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31159 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31160 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31161 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31162 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31163 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31165 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31166 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31167 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31169 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31170 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31172 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31173 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31175 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31177 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31178 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31179 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31180 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31182 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31183 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31184 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31185 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31186 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31187 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31188 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31191 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31192 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31193 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31194 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31195 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31196 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31198 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31199 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31200 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31201 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31203 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31204 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31205 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31207 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31209 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31211 /* SSE2 MMX */
31212 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31213 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31215 /* SSE3 */
31216 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31217 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31219 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31220 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31221 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31222 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31223 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31224 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31226 /* SSSE3 */
31227 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31228 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31229 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31230 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31231 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31232 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31234 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31235 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31236 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31237 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31238 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31239 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31240 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31241 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31242 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31243 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31244 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31245 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31246 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31247 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31248 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31249 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31250 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31251 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31252 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31253 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31254 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31255 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31256 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31257 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31259 /* SSSE3. */
31260 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31261 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31263 /* SSE4.1 */
31264 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31265 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31266 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31267 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31268 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31269 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31270 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31271 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31272 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31273 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31275 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31276 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31277 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31278 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31279 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31280 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31281 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31282 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31283 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31284 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31285 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31286 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31287 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31289 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31290 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31291 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31292 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31293 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31294 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31295 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31296 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31297 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31298 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31299 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31300 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31302 /* SSE4.1 */
31303 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31304 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31305 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31306 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31308 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31309 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31310 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31311 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31313 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31314 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31316 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31317 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31319 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31320 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31321 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31322 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31324 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31325 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31327 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31328 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31330 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31331 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31332 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31334 /* SSE4.2 */
31335 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31336 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31337 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31338 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31339 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31341 /* SSE4A */
31342 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31343 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31344 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31345 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31347 /* AES */
31348 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31349 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31351 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31352 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31353 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31354 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31356 /* PCLMUL */
31357 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31359 /* AVX */
31360 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31361 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31362 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31363 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31364 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31365 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31366 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31367 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31368 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31369 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31370 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31371 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31372 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31373 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31374 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31375 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31376 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31377 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31378 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31379 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31380 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31381 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31382 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31383 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31384 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31385 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31387 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31388 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31389 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31390 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31392 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31393 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31394 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31395 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31396 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31397 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31398 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31399 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31400 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31401 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31402 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31403 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31404 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31405 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31406 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31407 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31408 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31409 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31410 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31411 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31412 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31413 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31414 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31415 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31416 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31417 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31418 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31419 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31420 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31421 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31422 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31423 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31424 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31425 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31427 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31428 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31429 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31431 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31432 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31433 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31434 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31435 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31437 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31439 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31440 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31442 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31443 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31444 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31445 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31447 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31448 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31450 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31451 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31453 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31454 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31455 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31456 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31458 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31459 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31461 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31462 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31464 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31465 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31466 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31467 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31469 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31470 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31471 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31472 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31473 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31474 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31476 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31477 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31478 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31479 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31480 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31481 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31482 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31483 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31484 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31485 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31486 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31487 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31488 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31489 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31490 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31492 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31493 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31495 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31496 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31498 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31500 /* AVX2 */
31501 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31502 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31503 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31504 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31505 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31506 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31507 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31508 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31509 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31510 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31511 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31512 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31513 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31514 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31515 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31516 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31517 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31518 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31519 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31520 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31521 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31522 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31523 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31524 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31525 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31526 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31527 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31528 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31529 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31530 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31531 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31532 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31533 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31534 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31535 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31536 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31537 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31538 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31539 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31540 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31541 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31542 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31543 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31544 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31545 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31546 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31547 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31548 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31549 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31550 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31551 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31552 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31553 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31554 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31555 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31556 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31557 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31558 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31559 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31560 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31561 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31562 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31563 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31564 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31565 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31566 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31567 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31568 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31569 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31570 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31571 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31572 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31573 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31574 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31575 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31576 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31577 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31578 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31579 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31580 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31581 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31582 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31583 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31584 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31585 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31586 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31587 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31588 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31589 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31590 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31591 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31592 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31593 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31594 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31595 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31596 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31597 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31598 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31599 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31600 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31601 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31602 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31603 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31604 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31605 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31606 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31607 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31608 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31609 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31610 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31611 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31612 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31613 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31614 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31615 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31616 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31617 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31618 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31619 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31620 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31621 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31622 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31623 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31624 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31625 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31626 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31627 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31628 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31629 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31630 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31631 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31632 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31633 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31634 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31635 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31636 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31637 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31638 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31639 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31640 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31641 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31642 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31643 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31644 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31645 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31646 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31648 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31650 /* BMI */
31651 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31652 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31653 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31655 /* TBM */
31656 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31657 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31659 /* F16C */
31660 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
31661 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
31662 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
31663 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
31665 /* BMI2 */
31666 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31667 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31668 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31669 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31670 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31671 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31673 /* AVX512F */
31674 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
31675 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
31676 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
31677 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
31678 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
31679 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
31680 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31681 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31682 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31683 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31684 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31685 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31686 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31687 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
31688 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31689 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
31690 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
31691 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31692 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31693 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31694 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31695 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31696 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31697 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
31698 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31699 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
31700 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31701 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31702 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31703 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31704 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
31705 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
31706 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
31707 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
31708 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
31709 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
31710 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
31711 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
31712 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31713 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31714 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31715 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31716 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31717 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31718 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31719 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31720 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31721 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31722 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31723 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31724 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31725 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31726 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31727 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31728 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
31729 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
31730 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
31731 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
31732 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31733 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31734 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31735 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31736 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31737 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31738 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31739 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31740 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31741 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31742 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31743 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31744 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31745 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31746 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31747 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31748 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31749 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31750 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31751 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31752 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31753 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31754 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31755 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31756 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31757 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31758 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31759 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31760 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31761 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31762 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31763 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31764 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31765 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31766 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31767 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31768 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31769 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31770 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31771 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31772 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31773 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31774 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31775 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31776 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31777 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31778 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31779 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31780 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31781 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31782 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31783 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31784 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31785 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31786 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31787 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31788 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31789 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31790 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31791 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31792 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31793 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31794 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31795 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31796 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31797 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31798 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31799 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31800 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31801 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31802 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31803 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31804 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31805 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31806 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31807 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31808 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31809 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31810 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31811 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31812 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31813 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31814 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31815 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31816 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31817 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31818 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31819 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31820 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31821 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31822 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31823 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31824 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31825 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31826 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31827 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31828 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31829 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31830 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31831 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31832 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31833 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31834 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31835 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31836 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31837 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31838 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31839 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31840 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31841 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31842 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31843 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31844 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31845 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31846 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31847 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31848 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31849 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31850 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31851 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31852 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
31853 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31854 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31855 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31856 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31857 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31858 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31859 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
31860 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
31861 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31862 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31863 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31864 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31865 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31866 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31867 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
31868 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
31869 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
31870 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
31872 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
31873 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
31874 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
31875 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
31876 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
31877 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
31878 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
31879 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
31881 /* Mask arithmetic operations */
31882 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31883 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31884 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
31885 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31886 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31887 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31888 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
31889 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31890 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31891 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
31893 /* SHA */
31894 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31895 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31896 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31897 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31898 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31899 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31900 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
31902 /* AVX512VL. */
31903 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
31904 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
31905 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
31906 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
31907 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
31908 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
31909 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
31910 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
31911 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
31912 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
31913 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
31914 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
31915 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
31916 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
31917 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31918 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31919 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31920 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31921 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31922 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31923 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31924 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31925 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31926 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31927 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31928 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31929 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31930 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31931 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31932 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31933 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31934 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31935 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31936 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31937 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31938 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31939 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31940 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31941 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31942 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31943 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31944 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31945 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31946 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31947 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31948 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31949 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
31950 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
31951 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
31952 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
31953 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
31954 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
31955 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
31956 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
31957 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
31958 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
31959 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
31960 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
31961 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
31962 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
31963 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
31964 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
31965 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
31966 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
31967 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
31968 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
31969 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
31970 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
31971 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
31972 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
31973 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
31974 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
31975 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
31976 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
31977 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
31978 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
31979 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
31980 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
31981 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
31982 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
31983 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
31984 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
31985 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
31986 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
31987 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
31988 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
31989 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
31990 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
31991 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
31992 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
31993 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
31994 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
31995 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
31996 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
31997 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
31998 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
31999 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32000 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32001 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32002 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32003 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32004 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32005 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32006 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32007 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32008 { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv4di_mask, "__builtin_ia32_pbroadcastq256_mem_mask", IX86_BUILTIN_PBROADCASTQ256_MEM_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32009 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32010 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32011 { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv2di_mask, "__builtin_ia32_pbroadcastq128_mem_mask", IX86_BUILTIN_PBROADCASTQ128_MEM_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32012 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32013 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32014 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32015 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32016 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32017 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32018 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32019 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32020 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32021 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32022 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32023 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32024 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32025 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32026 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32027 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32028 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32029 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32030 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32031 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32032 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32033 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32034 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32035 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32036 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32037 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32038 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32039 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32040 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32041 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32042 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32043 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32044 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32045 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32046 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32047 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32048 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32049 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32050 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32051 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32052 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32053 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32054 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32055 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32056 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32057 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32058 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32059 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32060 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32061 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32062 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32063 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32064 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32065 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32066 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32067 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32068 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32069 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32070 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32071 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32072 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32073 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32074 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32075 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32076 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32077 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32078 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32079 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32080 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32081 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32082 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32083 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32084 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32085 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32086 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32087 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32088 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32089 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32090 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32091 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32092 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32093 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32094 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32095 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32096 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32097 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32098 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32099 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32100 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32101 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32102 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32103 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32104 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32105 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32106 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32107 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32108 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32109 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32110 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32111 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32112 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32113 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32114 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32115 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32116 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32117 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32118 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32119 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32120 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32121 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32122 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32123 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32124 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32125 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32126 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32127 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32128 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32129 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32130 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32131 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32132 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32133 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32134 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32135 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32136 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32137 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32138 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32139 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32140 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32141 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32142 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32143 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32144 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32145 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32146 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32147 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32148 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32149 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32150 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32151 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32152 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32153 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32154 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32155 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32156 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32157 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32158 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32159 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32160 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32161 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32162 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32163 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32164 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32165 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32166 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32167 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32168 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32169 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32170 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32171 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32172 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32173 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32174 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32175 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32176 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32177 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32178 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32179 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32180 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32181 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32182 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32183 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32184 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32185 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32186 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32189 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32190 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32191 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32192 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32193 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32194 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32195 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32196 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32197 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32198 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32199 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32200 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32201 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32202 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32203 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32204 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32205 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32206 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32207 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32208 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32209 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32210 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32211 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32212 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32213 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32214 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32215 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32216 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32217 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32218 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32219 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32220 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32221 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32222 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32223 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32224 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32225 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32226 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32227 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32228 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32229 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32230 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32231 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32232 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32233 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32234 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32235 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32236 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32237 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32238 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32239 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32240 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32241 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32242 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32243 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32244 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32245 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32246 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32247 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32248 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32249 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32250 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32251 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32252 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32253 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32254 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32255 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32256 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32257 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32258 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32259 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32260 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32261 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32262 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32263 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32264 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32265 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32266 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32267 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32268 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32269 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32270 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32271 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32272 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32273 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32274 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32275 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32276 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32277 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32278 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32279 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32280 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32281 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32282 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32283 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32284 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32285 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32286 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32287 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32288 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32289 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32290 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32291 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32292 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32293 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32294 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32295 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32296 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32297 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32298 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32299 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32300 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32301 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32302 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32303 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32304 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32305 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32306 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32307 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32308 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32309 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32310 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32311 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32312 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32313 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32314 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32315 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32316 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32317 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32318 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32319 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32320 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32321 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32322 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32323 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32324 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32325 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32326 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32327 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32330 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32331 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32334 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32339 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32340 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32341 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32342 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32343 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32344 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32347 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32348 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32349 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32350 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32351 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32352 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32353 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32354 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32355 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32356 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32357 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32358 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32359 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32360 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32361 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32362 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32363 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32364 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32365 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32366 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32367 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32368 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32369 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32370 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32371 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32372 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32373 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32374 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32377 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32378 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32379 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32380 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32381 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32382 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32383 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32384 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32385 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32386 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32387 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32394 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32395 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32396 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32397 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32398 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32399 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32400 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32401 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32402 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32403 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32404 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32405 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32406 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32407 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32408 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32409 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32410 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32411 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32412 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32413 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32414 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32415 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32416 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32417 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32418 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32419 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32420 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32421 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32422 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32423 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32424 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32425 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32426 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32427 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32428 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32429 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32430 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32431 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32432 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32433 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32434 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32435 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32436 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32437 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32438 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32439 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32440 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32441 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32442 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32443 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32444 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32445 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32446 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32447 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32448 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32449 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32450 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32451 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32452 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32453 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32454 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32455 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32456 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32457 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32458 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32459 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32460 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32461 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32464 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32465 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32466 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32469 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32470 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32471 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32472 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32473 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32474 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32475 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32476 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32479 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32480 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32481 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32482 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32483 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32484 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32485 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32486 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32487 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32488 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32489 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32490 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32491 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32492 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32493 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32494 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32495 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32496 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32497 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32498 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32499 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32500 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32501 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32502 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32503 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32504 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32505 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32506 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32507 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32508 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32509 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32510 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32511 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32512 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32514 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32515 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32516 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32517 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32518 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32519 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32520 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32521 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32522 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32523 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32524 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32525 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32526 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32527 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32528 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32529 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32533 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32534 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32535 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32536 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32537 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32539 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32540 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32541 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32542 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32543 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32544 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32545 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32546 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32547 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32548 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32549 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32550 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32551 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32552 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32553 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32554 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32555 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32556 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32557 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32558 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32559 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32562 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32563 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32564 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32565 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32566 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32567 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32568 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32570 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32571 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32572 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32573 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32574 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32575 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32576 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32577 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32578 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32579 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32580 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32581 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32582 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32583 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32584 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32585 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32586 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32587 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32588 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32589 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32590 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32591 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32592 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32593 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32594 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32595 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32596 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32597 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32598 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32599 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32600 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32601 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32602 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32603 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32604 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32606 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32607 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32608 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32609 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32610 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32611 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32612 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32613 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32614 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32618 /* AVX512DQ. */
32619 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32620 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32621 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32622 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32623 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32624 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32625 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32626 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32627 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32628 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32629 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32630 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32631 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32632 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32633 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32634 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32635 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32636 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32637 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32638 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32639 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32640 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32641 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32642 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32643 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32644 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32645 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32646 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32647 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32648 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
32649 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
32651 /* AVX512BW. */
32652 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
32653 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
32654 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32655 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32656 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32657 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32658 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
32659 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
32660 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32661 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32662 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
32663 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
32664 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
32665 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
32666 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
32667 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
32668 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32669 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32670 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32671 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32672 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32673 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32674 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32675 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32676 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32677 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32678 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32679 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32680 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32681 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32682 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32683 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32684 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32685 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32686 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32687 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32688 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32689 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32690 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32691 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32692 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32693 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32694 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32695 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32696 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32697 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32698 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32699 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32700 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32701 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32702 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32703 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32704 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32705 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32706 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32707 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32708 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
32709 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
32710 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32711 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32712 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32713 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32714 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32715 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32716 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32717 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32718 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32719 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32720 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32721 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32722 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
32723 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
32724 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
32725 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
32726 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32727 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32728 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32729 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32730 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32731 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32732 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32733 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32734 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32735 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32736 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32737 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32738 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32739 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32740 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32741 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32742 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32743 };
32745 /* Builtins with rounding support. */
32747 {
32748 /* AVX512F */
32749 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32750 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32751 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32752 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32753 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
32754 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
32755 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
32756 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
32757 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
32758 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
32759 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32760 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32761 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
32762 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32763 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
32764 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32765 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
32766 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32767 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
32768 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
32769 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
32770 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
32771 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
32772 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32773 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32774 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32775 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32776 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32777 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
32778 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
32779 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
32780 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32781 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32782 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32783 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32784 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32785 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32786 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32787 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32788 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32789 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32790 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32791 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32792 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32793 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32794 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32795 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32796 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32797 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32798 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32799 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32800 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32801 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32802 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32803 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32804 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32805 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32806 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32807 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32808 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32809 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32810 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32811 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32812 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32813 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32814 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32815 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32816 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32817 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32818 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32819 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32820 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32821 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32822 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32823 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32824 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32825 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32826 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32827 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32828 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32829 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
32830 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
32831 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
32832 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
32833 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
32834 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
32835 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
32836 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32837 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
32838 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
32839 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
32840 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
32841 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
32842 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
32843 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
32844 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32845 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32846 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32847 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32848 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32849 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32850 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
32851 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
32852 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32853 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32854 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32855 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32856 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32857 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32858 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32859 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32860 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32861 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32862 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32863 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32864 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32865 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32866 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32867 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32869 /* AVX512ER */
32870 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32871 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32872 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32873 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32874 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32875 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32876 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32877 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32878 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32879 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32881 /* AVX512DQ. */
32882 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32883 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32884 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32885 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32886 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32887 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32888 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
32889 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
32890 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
32891 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
32892 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32893 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32894 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32895 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32896 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
32897 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
32898 };
32900 /* Bultins for MPX. */
32902 {
32903 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
32904 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
32905 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
32906 };
32908 /* Const builtins for MPX. */
32910 {
32911 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
32912 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
32913 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
32914 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
32915 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
32916 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
32917 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
32918 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
32919 };
32921 /* FMA4 and XOP. */
32922 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
32923 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
32924 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
32925 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
32926 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
32927 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
32928 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
32929 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
32930 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
32931 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
32932 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
32933 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
32934 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
32935 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
32936 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
32937 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
32938 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
32939 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
32940 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
32941 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
32942 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
32943 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
32944 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
32945 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
32946 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
32947 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
32948 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
32949 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
32950 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
32951 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
32952 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
32953 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
32954 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
32955 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
32956 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
32957 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
32958 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
32959 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
32960 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
32961 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
32962 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
32963 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
32964 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
32965 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
32966 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
32967 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
32968 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
32969 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
32970 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
32971 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
32972 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
32973 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
32976 {
33017 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33018 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33019 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33020 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33021 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33022 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33023 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33025 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33026 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33027 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33028 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33029 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33030 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33031 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33033 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33035 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33036 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33037 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33038 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33039 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33040 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33041 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33042 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33043 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33044 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33045 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33046 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33048 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33049 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33050 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33051 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33052 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33053 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33054 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33055 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33056 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33057 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33058 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33059 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33060 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33061 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33062 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33063 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33065 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33066 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33067 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33068 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33069 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33070 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33072 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33073 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33074 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33075 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33076 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33077 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33078 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33079 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33080 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33081 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33082 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33083 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33084 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33085 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33086 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33088 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33089 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33090 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33091 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33092 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33093 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33094 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33096 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33097 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33098 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33099 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33100 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33101 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33102 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33104 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33105 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33106 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33107 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33108 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33109 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33110 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33112 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33113 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33114 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33115 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33116 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33117 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33118 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33120 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33121 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33122 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33123 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33124 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33125 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33126 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33128 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33129 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33130 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33131 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33132 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33133 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33134 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33136 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33137 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33138 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33139 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33140 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33141 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33142 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33144 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33145 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33146 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33147 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33148 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33149 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33150 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33152 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33153 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33154 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33155 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33156 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33157 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33158 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33159 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33161 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33162 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33163 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33164 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33165 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33166 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33167 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33168 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33170 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33171 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33172 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33173 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33175 };
33176 \f
33177 /* TM vector builtins. */
33179 /* Reuse the existing x86-specific `struct builtin_description' cause
33180 we're lazy. Add casts to make them fit. */
33182 {
33183 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33184 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33185 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33186 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33187 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33188 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33189 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33191 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33192 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33193 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33194 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33195 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33196 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33197 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33199 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33200 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33201 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33202 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33203 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33204 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33205 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33207 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33208 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33209 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33210 };
33212 /* TM callbacks. */
33214 /* Return the builtin decl needed to load a vector of TYPE. */
33216 static tree
33218 {
33220 {
33222 {
33229 }
33230 }
33232 }
33234 /* Return the builtin decl needed to store a vector of TYPE. */
33236 static tree
33238 {
33240 {
33242 {
33249 }
33250 }
33252 }
33253 \f
33254 /* Initialize the transactional memory vector load/store builtins. */
33256 static void
33258 {
33262 tree decl;
33269 /* If there are no builtins defined, we must be compiling in a
33270 language without trans-mem support. */
33274 /* Use whatever attributes a normal TM load has. */
33278 /* Use whatever attributes a normal TM store has. */
33282 /* Use whatever attributes a normal TM log has. */
33290 {
33294 {
33302 {
33305 }
33307 {
33310 }
33311 else
33312 {
33315 }
33317 /* The builtin without the prefix for
33318 calling it directly. */
33320 attrs);
33321 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33322 set the TYPE_ATTRIBUTES. */
33326 }
33327 }
33328 }
33330 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33331 in the current target ISA to allow the user to compile particular modules
33332 with different target specific options that differ from the command line
33333 options. */
33334 static void
33336 {
33341 /* Add all special builtins with variable number of operands. */
33345 {
33351 }
33353 /* Add all builtins with variable number of operands. */
33357 {
33363 }
33365 /* Add all builtins with rounding. */
33369 {
33375 }
33377 /* pcmpestr[im] insns. */
33381 {
33384 else
33387 }
33389 /* pcmpistr[im] insns. */
33393 {
33396 else
33399 }
33401 /* comi/ucomi insns. */
33403 {
33406 else
33409 }
33411 /* SSE */
33417 /* SSE or 3DNow!A */
33420 IX86_BUILTIN_MASKMOVQ);
33422 /* SSE2 */
33431 /* SSE3. */
33437 /* AES */
33451 /* PCLMUL */
33455 /* RDRND */
33462 IX86_BUILTIN_RDRAND64_STEP);
33464 /* AVX2 */
33466 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33467 IX86_BUILTIN_GATHERSIV2DF);
33470 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33471 IX86_BUILTIN_GATHERSIV4DF);
33474 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33475 IX86_BUILTIN_GATHERDIV2DF);
33478 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33479 IX86_BUILTIN_GATHERDIV4DF);
33482 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33483 IX86_BUILTIN_GATHERSIV4SF);
33486 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33487 IX86_BUILTIN_GATHERSIV8SF);
33490 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33491 IX86_BUILTIN_GATHERDIV4SF);
33494 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33495 IX86_BUILTIN_GATHERDIV8SF);
33498 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33499 IX86_BUILTIN_GATHERSIV2DI);
33502 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33503 IX86_BUILTIN_GATHERSIV4DI);
33506 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33507 IX86_BUILTIN_GATHERDIV2DI);
33510 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33511 IX86_BUILTIN_GATHERDIV4DI);
33514 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33515 IX86_BUILTIN_GATHERSIV4SI);
33518 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33519 IX86_BUILTIN_GATHERSIV8SI);
33522 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33523 IX86_BUILTIN_GATHERDIV4SI);
33526 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33527 IX86_BUILTIN_GATHERDIV8SI);
33530 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33531 IX86_BUILTIN_GATHERALTSIV4DF);
33534 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33535 IX86_BUILTIN_GATHERALTDIV8SF);
33538 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33539 IX86_BUILTIN_GATHERALTSIV4DI);
33542 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33543 IX86_BUILTIN_GATHERALTDIV8SI);
33545 /* AVX512F */
33547 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33548 IX86_BUILTIN_GATHER3SIV16SF);
33551 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33552 IX86_BUILTIN_GATHER3SIV8DF);
33555 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33556 IX86_BUILTIN_GATHER3DIV16SF);
33559 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33560 IX86_BUILTIN_GATHER3DIV8DF);
33563 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33564 IX86_BUILTIN_GATHER3SIV16SI);
33567 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33568 IX86_BUILTIN_GATHER3SIV8DI);
33571 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33572 IX86_BUILTIN_GATHER3DIV16SI);
33575 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33576 IX86_BUILTIN_GATHER3DIV8DI);
33579 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33580 IX86_BUILTIN_GATHER3ALTSIV8DF);
33583 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33584 IX86_BUILTIN_GATHER3ALTDIV16SF);
33587 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33588 IX86_BUILTIN_GATHER3ALTSIV8DI);
33591 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33592 IX86_BUILTIN_GATHER3ALTDIV16SI);
33595 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33596 IX86_BUILTIN_SCATTERSIV16SF);
33599 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33600 IX86_BUILTIN_SCATTERSIV8DF);
33603 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33604 IX86_BUILTIN_SCATTERDIV16SF);
33607 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33608 IX86_BUILTIN_SCATTERDIV8DF);
33611 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33612 IX86_BUILTIN_SCATTERSIV16SI);
33615 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33616 IX86_BUILTIN_SCATTERSIV8DI);
33619 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
33620 IX86_BUILTIN_SCATTERDIV16SI);
33623 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
33624 IX86_BUILTIN_SCATTERDIV8DI);
33626 /* AVX512VL */
33628 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
33629 IX86_BUILTIN_GATHER3SIV2DF);
33632 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
33633 IX86_BUILTIN_GATHER3SIV4DF);
33636 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
33637 IX86_BUILTIN_GATHER3DIV2DF);
33640 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
33641 IX86_BUILTIN_GATHER3DIV4DF);
33644 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
33645 IX86_BUILTIN_GATHER3SIV4SF);
33648 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
33649 IX86_BUILTIN_GATHER3SIV8SF);
33652 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
33653 IX86_BUILTIN_GATHER3DIV4SF);
33656 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
33657 IX86_BUILTIN_GATHER3DIV8SF);
33660 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
33661 IX86_BUILTIN_GATHER3SIV2DI);
33664 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
33665 IX86_BUILTIN_GATHER3SIV4DI);
33668 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
33669 IX86_BUILTIN_GATHER3DIV2DI);
33672 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
33673 IX86_BUILTIN_GATHER3DIV4DI);
33676 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
33677 IX86_BUILTIN_GATHER3SIV4SI);
33680 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
33681 IX86_BUILTIN_GATHER3SIV8SI);
33684 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
33685 IX86_BUILTIN_GATHER3DIV4SI);
33688 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
33689 IX86_BUILTIN_GATHER3DIV8SI);
33692 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
33693 IX86_BUILTIN_GATHER3ALTSIV4DF);
33696 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
33697 IX86_BUILTIN_GATHER3ALTDIV8SF);
33700 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
33701 IX86_BUILTIN_GATHER3ALTSIV4DI);
33704 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
33705 IX86_BUILTIN_GATHER3ALTDIV8SI);
33708 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
33709 IX86_BUILTIN_SCATTERSIV8SF);
33712 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
33713 IX86_BUILTIN_SCATTERSIV4SF);
33716 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
33717 IX86_BUILTIN_SCATTERSIV4DF);
33720 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
33721 IX86_BUILTIN_SCATTERSIV2DF);
33724 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
33725 IX86_BUILTIN_SCATTERDIV8SF);
33728 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
33729 IX86_BUILTIN_SCATTERDIV4SF);
33732 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
33733 IX86_BUILTIN_SCATTERDIV4DF);
33736 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
33737 IX86_BUILTIN_SCATTERDIV2DF);
33740 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
33741 IX86_BUILTIN_SCATTERSIV8SI);
33744 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
33745 IX86_BUILTIN_SCATTERSIV4SI);
33748 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
33749 IX86_BUILTIN_SCATTERSIV4DI);
33752 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
33753 IX86_BUILTIN_SCATTERSIV2DI);
33756 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
33757 IX86_BUILTIN_SCATTERDIV8SI);
33760 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
33761 IX86_BUILTIN_SCATTERDIV4SI);
33764 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
33765 IX86_BUILTIN_SCATTERDIV4DI);
33768 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
33769 IX86_BUILTIN_SCATTERDIV2DI);
33771 /* AVX512PF */
33773 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33774 IX86_BUILTIN_GATHERPFDPD);
33776 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33777 IX86_BUILTIN_GATHERPFDPS);
33779 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33780 IX86_BUILTIN_GATHERPFQPD);
33782 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33783 IX86_BUILTIN_GATHERPFQPS);
33785 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33786 IX86_BUILTIN_SCATTERPFDPD);
33788 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33789 IX86_BUILTIN_SCATTERPFDPS);
33791 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33792 IX86_BUILTIN_SCATTERPFQPD);
33794 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33795 IX86_BUILTIN_SCATTERPFQPS);
33797 /* SHA */
33813 /* RTM. */
33817 /* MMX access to the vec_init patterns. */
33822 V4HI_FTYPE_HI_HI_HI_HI,
33823 IX86_BUILTIN_VEC_INIT_V4HI);
33826 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
33827 IX86_BUILTIN_VEC_INIT_V8QI);
33829 /* Access to the vec_extract patterns. */
33851 /* Access to the vec_set patterns. */
33872 /* RDSEED */
33881 /* ADCX */
33886 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
33887 IX86_BUILTIN_ADDCARRYX64);
33889 /* SBB */
33894 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
33895 IX86_BUILTIN_SBB64);
33897 /* Read/write FLAGS. */
33907 /* CLFLUSHOPT. */
33911 /* Add FMA4 multi-arg argument instructions */
33913 {
33919 }
33920 }
33922 static void
33924 {
33927 tree decl;
33933 {
33940 /* With no leaf and nothrow flags for MPX builtins
33941 abnormal edges may follow its call when setjmp
33942 presents in the function. Since we may have a lot
33943 of MPX builtins calls it causes lots of useless
33944 edges and enormous PHI nodes. To avoid this we mark
33945 MPX builtins as leaf and nothrow. */
33947 {
33949 NULL_TREE);
33951 }
33952 else
33953 {
33956 }
33957 }
33962 {
33970 {
33972 NULL_TREE);
33974 }
33975 else
33976 {
33979 }
33980 }
33981 }
33983 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
33984 to return a pointer to VERSION_DECL if the outcome of the expression
33985 formed by PREDICATE_CHAIN is true. This function will be called during
33986 version dispatch to decide which function version to execute. It returns
33987 the basic block at the end, to which more conditions can be added. */
33989 static basic_block
33992 {
33993 gimple return_stmt;
33995 gimple convert_stmt;
33996 gimple call_cond_stmt;
33997 gimple if_else_stmt;
34003 gimple_seq gseq;
34020 {
34028 }
34031 {
34046 else
34047 {
34048 gimple assign_stmt;
34049 /* Use MIN_EXPR to check if any integer is zero?.
34050 and_expr_var = min_expr <cond_var, and_expr_var> */
34058 }
34059 }
34062 integer_zero_node,
34092 }
34094 /* This parses the attribute arguments to target in DECL and determines
34095 the right builtin to use to match the platform specification.
34096 It returns the priority value for this version decl. If PREDICATE_LIST
34097 is not NULL, it stores the list of cpu features that need to be checked
34098 before dispatching this function. */
34100 static unsigned int
34102 {
34103 tree attrs;
34105 tree target_node;
34112 /* Priority of i386 features, greater value is higher priority. This is
34113 used to decide the order in which function dispatch must happen. For
34114 instance, a version specialized for SSE4.2 should be checked for dispatch
34115 before a version for SSE3, as SSE4.2 implies SSE3. */
34116 enum feature_priority
34117 {
34119 P_MMX,
34120 P_SSE,
34121 P_SSE2,
34122 P_SSE3,
34123 P_SSSE3,
34124 P_PROC_SSSE3,
34125 P_SSE4_A,
34126 P_PROC_SSE4_A,
34127 P_SSE4_1,
34128 P_SSE4_2,
34129 P_PROC_SSE4_2,
34130 P_POPCNT,
34131 P_AVX,
34132 P_PROC_AVX,
34133 P_FMA4,
34134 P_XOP,
34135 P_PROC_XOP,
34136 P_FMA,
34137 P_PROC_FMA,
34138 P_AVX2,
34139 P_PROC_AVX2
34140 };
34144 /* These are the target attribute strings for which a dispatcher is
34145 available, from fold_builtin_cpu. */
34147 static struct _feature_list
34148 {
34151 }
34153 {
34168 };
34171 static unsigned int NUM_FEATURES
34187 /* Return priority zero for default function. */
34191 /* Handle arch= if specified. For priority, set it to be 1 more than
34192 the best instruction set the processor can handle. For instance, if
34193 there is a version for atom and a version for ssse3 (the highest ISA
34194 priority for atom), the atom version must be checked for dispatch
34195 before the ssse3 version. */
34197 {
34207 {
34209 {
34217 else
34218 /* We translate "arch=corei7" and "arch=nehalem" to
34219 "corei7" so that it will be mapped to M_INTEL_COREI7
34220 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34227 else
34234 else
34274 }
34275 }
34280 {
34284 }
34287 {
34289 /* For a C string literal the length includes the trailing NULL. */
34292 predicate_chain);
34293 }
34294 }
34296 /* Process feature name. */
34303 {
34304 /* Do not process "arch=" */
34306 {
34309 }
34311 {
34313 {
34315 {
34320 predicate_chain);
34321 }
34322 /* Find the maximum priority feature. */
34327 }
34328 }
34330 {
34334 }
34336 }
34340 {
34343 attrs_str);
34345 }
34347 {
34350 }
34353 }
34355 /* This compares the priority of target features in function DECL1
34356 and DECL2. It returns positive value if DECL1 is higher priority,
34357 negative value if DECL2 is higher priority and 0 if they are the
34358 same. */
34360 static int
34362 {
34367 }
34369 /* V1 and V2 point to function versions with different priorities
34370 based on the target ISA. This function compares their priorities. */
34372 static int
34374 {
34376 {
34377 tree version_decl;
34378 tree predicate_chain;
34385 }
34387 /* This function generates the dispatch function for
34388 multi-versioned functions. DISPATCH_DECL is the function which will
34389 contain the dispatch logic. FNDECLS are the function choices for
34390 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34391 in DISPATCH_DECL in which the dispatch code is generated. */
34393 static int
34397 {
34398 tree default_decl;
34399 gimple ifunc_cpu_init_stmt;
34400 gimple_seq gseq;
34402 tree ele;
34408 struct _function_version_info
34409 {
34410 tree version_decl;
34411 tree predicate_chain;
34419 /*fndecls_p is actually a vector. */
34422 /* At least one more version other than the default. */
34429 /* The first version in the vector is the default decl. */
34435 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34436 constructors, so explicity call __builtin_cpu_init here. */
34447 {
34451 /* Get attribute string, parse it and find the right predicate decl.
34452 The predicate function could be a lengthy combination of many
34453 features, like arch-type and various isa-variants. */
34464 actual_versions++;
34465 }
34467 /* Sort the versions according to descending order of dispatch priority. The
34468 priority is based on the ISA. This is not a perfect solution. There
34469 could still be ambiguity. If more than one function version is suitable
34470 to execute, which one should be dispatched? In future, allow the user
34471 to specify a dispatch priority next to the version. */
34481 /* dispatch default version at the end. */
34487 }
34489 /* Comparator function to be used in qsort routine to sort attribute
34490 specification strings to "target". */
34492 static int
34494 {
34498 }
34500 /* ARGLIST is the argument to target attribute. This function tokenizes
34501 the comma separated arguments, sorts them and returns a string which
34502 is a unique identifier for the comma separated arguments. It also
34503 replaces non-identifier characters "=,-" with "_". */
34507 {
34508 tree arg;
34517 {
34522 argnum++;
34525 argnum++;
34526 }
34531 {
34537 }
34539 /* Replace "=,-" with "_". */
34552 {
34554 i++;
34556 }
34563 {
34568 }
34573 }
34575 /* This function changes the assembler name for functions that are
34576 versions. If DECL is a function version and has a "target"
34577 attribute, it appends the attribute string to its assembler name. */
34579 static tree
34581 {
34582 tree version_attr;
34590 "Function versions cannot be marked as gnu_inline,"
34599 /* target attribute string cannot be NULL. */
34603 version_string
34614 /* Allow assembler name to be modified if already set. */
34622 }
34624 /* This function returns true if FN1 and FN2 are versions of the same function,
34625 that is, the target strings of the function decls are different. This assumes
34626 that FN1 and FN2 have the same signature. */
34628 static bool
34630 {
34642 /* At least one function decl should have the target attribute specified. */
34646 /* Diagnose missing target attribute if one of the decls is already
34647 multi-versioned. */
34649 {
34651 {
34653 {
34658 }
34661 fn2);
34664 /* Prevent diagnosing of the same error multiple times. */
34669 }
34671 }
34676 /* The sorted target strings must be different for fn1 and fn2
34677 to be versions. */
34680 else
34687 }
34689 static tree
34691 {
34692 /* For function version, add the target suffix to the assembler name. */
34696 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
34698 #endif
34701 }
34703 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
34704 is true, append the full path name of the source file. */
34708 {
34716 /* Get a unique name that can be used globally without any chances
34717 of collision at link time. */
34727 /* Use '.' to concatenate names as it is demangler friendly. */
34730 suffix);
34731 else
34735 }
34737 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34739 /* Make a dispatcher declaration for the multi-versioned function DECL.
34740 Calls to DECL function will be replaced with calls to the dispatcher
34741 by the front-end. Return the decl created. */
34743 static tree
34745 {
34746 tree func_decl;
34766 /* Mark this func as external, the resolver will flip it again if
34767 it gets generated. */
34769 /* This will be of type IFUNCs have to be externally visible. */
34773 }
34775 #endif
34777 /* Returns true if decl is multi-versioned and DECL is the default function,
34778 that is it is not tagged with target specific optimization. */
34780 static bool
34782 {
34791 }
34793 /* Make a dispatcher declaration for the multi-versioned function DECL.
34794 Calls to DECL function will be replaced with calls to the dispatcher
34795 by the front-end. Returns the decl of the dispatcher function. */
34797 static tree
34799 {
34821 /* Find the default version and make it the first node. */
34823 /* Go to the beginning of the chain. */
34828 {
34833 }
34835 /* If there is no default node, just return NULL. */
34839 /* Make default info the first node. */
34841 {
34848 }
34852 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34854 {
34859 /* Right now, the dispatching is done via ifunc. */
34865 dispatcher_version_info
34870 /* Set the dispatcher for all the versions. */
34873 {
34876 }
34877 }
34878 else
34879 #endif
34880 {
34882 "multiversioning needs ifunc which is not supported "
34884 }
34887 }
34889 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
34890 it to CHAIN. */
34892 static tree
34894 {
34895 tree attr_name;
34896 tree attr_arg_name;
34897 tree attr_args;
34898 tree attr;
34905 }
34907 /* Make the resolver function decl to dispatch the versions of
34908 a multi-versioned function, DEFAULT_DECL. Create an
34909 empty basic block in the resolver and store the pointer in
34910 EMPTY_BB. Return the decl of the resolver function. */
34912 static tree
34916 {
34921 /* IFUNC's have to be globally visible. So, if the default_decl is
34922 not, then the name of the IFUNC should be made unique. */
34926 /* Append the filename to the resolver function if the versions are
34927 not externally visible. This is because the resolver function has
34928 to be externally visible for the loader to find it. So, appending
34929 the filename will prevent conflicts with a resolver function from
34930 another module which is based on the same version name. */
34933 /* The resolver function should return a (void *). */
34944 /* IFUNC resolvers have to be externally visible. */
34948 /* Resolver is not external, body is generated. */
34958 {
34959 /* In this case, each translation unit with a call to this
34960 versioned function will put out a resolver. Ensure it
34961 is comdat to keep just one copy. */
34964 }
34965 /* Build result decl and add to function_decl. */
34981 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
34985 /* Create the alias for dispatch to resolver here. */
34986 /*cgraph_create_function_alias (dispatch_decl, decl);*/
34990 }
34992 /* Generate the dispatching code body to dispatch multi-versioned function
34993 DECL. The target hook is called to process the "target" attributes and
34994 provide the code to dispatch the right function at run-time. NODE points
34995 to the dispatcher decl whose body will be created. */
34997 static tree
34999 {
35000 tree resolver_decl;
35001 basic_block empty_bb;
35002 tree default_ver_decl;
35018 /* The first version in the chain corresponds to the default version. */
35021 /* node is going to be an alias, so remove the finalized bit. */
35035 {
35037 /* Check for virtual functions here again, as by this time it should
35038 have been determined if this function needs a vtable index or
35039 not. This happens for methods in derived classes that override
35040 virtual methods in base classes but are not explicitly marked as
35041 virtual. */
35046 }
35052 }
35053 /* This builds the processor_model struct type defined in
35054 libgcc/config/i386/cpuinfo.c */
35056 static tree
35058 {
35065 /* The first 3 fields are unsigned int. */
35067 {
35073 }
35075 /* The last field is an array of unsigned integers of size one. */
35086 }
35088 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35090 static tree
35092 {
35093 tree new_decl;
35096 VAR_DECL,
35098 type);
35111 }
35113 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35114 into an integer defined in libgcc/config/i386/cpuinfo.c */
35116 static tree
35118 {
35124 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35125 enum processor_features
35126 {
35128 F_MMX,
35129 F_POPCNT,
35130 F_SSE,
35131 F_SSE2,
35132 F_SSE3,
35133 F_SSSE3,
35134 F_SSE4_1,
35135 F_SSE4_2,
35136 F_AVX,
35137 F_AVX2,
35138 F_SSE4_A,
35139 F_FMA4,
35140 F_XOP,
35141 F_FMA,
35142 F_MAX
35143 };
35145 /* These are the values for vendor types and cpu types and subtypes
35146 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35147 the corresponding start value. */
35148 enum processor_model
35149 {
35151 M_AMD,
35152 M_CPU_TYPE_START,
35153 M_INTEL_BONNELL,
35154 M_INTEL_CORE2,
35155 M_INTEL_COREI7,
35156 M_AMDFAM10H,
35157 M_AMDFAM15H,
35158 M_INTEL_SILVERMONT,
35159 M_AMD_BTVER1,
35160 M_AMD_BTVER2,
35161 M_CPU_SUBTYPE_START,
35162 M_INTEL_COREI7_NEHALEM,
35163 M_INTEL_COREI7_WESTMERE,
35164 M_INTEL_COREI7_SANDYBRIDGE,
35165 M_AMDFAM10H_BARCELONA,
35166 M_AMDFAM10H_SHANGHAI,
35167 M_AMDFAM10H_ISTANBUL,
35168 M_AMDFAM15H_BDVER1,
35169 M_AMDFAM15H_BDVER2,
35170 M_AMDFAM15H_BDVER3,
35171 M_AMDFAM15H_BDVER4,
35172 M_INTEL_COREI7_IVYBRIDGE,
35173 M_INTEL_COREI7_HASWELL
35174 };
35176 static struct _arch_names_table
35177 {
35180 }
35182 {
35207 };
35209 static struct _isa_names_table
35210 {
35213 }
35215 {
35231 };
35245 {
35246 /* *args must be a expr that can contain other EXPRS leading to a
35247 STRING_CST. */
35249 {
35252 }
35254 }
35259 {
35260 tree ref;
35261 tree field;
35262 tree final;
35265 unsigned int NUM_ARCH_NAMES
35274 {
35278 }
35283 /* CPU types are stored in the next field. */
35286 {
35289 }
35291 /* CPU subtypes are stored in the next field. */
35293 {
35296 }
35298 /* Get the appropriate field in __cpu_model. */
35302 /* Check the value. */
35306 }
35308 {
35309 tree ref;
35310 tree array_elt;
35311 tree field;
35312 tree final;
35315 unsigned int NUM_ISA_NAMES
35324 {
35328 }
35331 /* Get the last field, which is __cpu_features. */
35335 /* Get the appropriate field: __cpu_model.__cpu_features */
35339 /* Access the 0th element of __cpu_features array. */
35344 /* Return __cpu_model.__cpu_features[0] & field_val */
35348 }
35350 }
35352 static tree
35355 {
35357 {
35362 {
35365 }
35366 }
35368 #ifdef SUBTARGET_FOLD_BUILTIN
35370 #endif
35373 }
35375 /* Make builtins to detect cpu type and features supported. NAME is
35376 the builtin name, CODE is the builtin code, and FTYPE is the function
35377 type of the builtin. */
35379 static void
35382 {
35383 tree decl;
35384 tree type;
35392 }
35394 /* Make builtins to get CPU type and features supported. The created
35395 builtins are :
35397 __builtin_cpu_init (), to detect cpu type and features,
35398 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35399 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35400 */
35402 static void
35404 {
35411 }
35413 /* Internal method for ix86_init_builtins. */
35415 static void
35417 {
35429 sysv_va_ref =
35432 fnvoid_va_end_ms =
35434 fnvoid_va_start_ms =
35436 fnvoid_va_end_sysv =
35438 fnvoid_va_start_sysv =
35440 NULL_TREE);
35441 fnvoid_va_copy_ms =
35443 NULL_TREE);
35444 fnvoid_va_copy_sysv =
35460 }
35462 static void
35464 {
35467 /* The __float80 type. */
35470 {
35471 /* The __float80 type. */
35476 }
35479 /* The __float128 type. */
35485 /* This macro is built by i386-builtin-types.awk. */
35486 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35487 }
35489 static void
35491 {
35492 tree t;
35496 /* Builtins to get CPU type and features. */
35499 /* TFmode support builtins. */
35505 /* We will expand them to normal call if SSE isn't available since
35506 they are used by libgcc. */
35526 #ifdef SUBTARGET_INIT_BUILTINS
35527 SUBTARGET_INIT_BUILTINS;
35528 #endif
35529 }
35531 /* Return the ix86 builtin for CODE. */
35533 static tree
35535 {
35540 }
35542 /* Errors in the source file can cause expand_expr to return const0_rtx
35543 where we expect a vector. To avoid crashing, use one of the vector
35544 clear instructions. */
35545 static rtx
35547 {
35551 }
35553 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35555 static rtx
35557 {
35558 rtx pat;
35578 {
35582 }
35596 }
35598 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
35600 static rtx
35604 {
35605 rtx pat;
35613 rtx op;
35614 machine_mode mode;
35620 {
35700 }
35710 {
35717 {
35719 {
35722 {
35740 xop_rotl:
35742 {
35745 gcc_checking_assert
35747 }
35748 else
35749 {
35750 gcc_checking_assert
35761 }
35765 }
35766 }
35767 }
35768 else
35769 {
35770 non_constant:
35774 /* If we aren't optimizing, only allow one memory operand to be
35775 generated. */
35777 num_memory++;
35785 }
35789 }
35792 {
35803 else
35804 {
35810 }
35823 }
35830 }
35832 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
35833 insns with vec_merge. */
35835 static rtx
35837 rtx target)
35838 {
35839 rtx pat;
35866 }
35868 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
35870 static rtx
35873 {
35874 rtx pat;
35879 rtx op2;
35890 /* Swap operands if we have a comparison that isn't available in
35891 hardware. */
35893 {
35898 }
35918 }
35920 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
35922 static rtx
35924 rtx target)
35925 {
35926 rtx pat;
35940 /* Swap operands if we have a comparison that isn't available in
35941 hardware. */
35964 const0_rtx)));
35967 }
35969 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
35971 static rtx
35973 rtx target)
35974 {
35975 rtx pat;
36000 }
36002 static rtx
36005 {
36006 rtx pat;
36011 rtx op2;
36038 }
36040 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36042 static rtx
36044 rtx target)
36045 {
36046 rtx pat;
36079 const0_rtx)));
36082 }
36084 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36086 static rtx
36089 {
36090 rtx pat;
36128 {
36131 }
36134 {
36143 }
36145 {
36154 }
36155 else
36156 {
36163 }
36171 {
36176 emit_insn
36180 FLAGS_REG),
36181 const0_rtx)));
36183 }
36184 else
36186 }
36189 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36191 static rtx
36194 {
36195 rtx pat;
36223 {
36226 }
36229 {
36238 }
36240 {
36249 }
36250 else
36251 {
36258 }
36266 {
36271 emit_insn
36275 FLAGS_REG),
36276 const0_rtx)));
36278 }
36279 else
36281 }
36283 /* Subroutine of ix86_expand_builtin to take care of insns with
36284 variable number of operands. */
36286 static rtx
36289 {
36295 struct
36296 {
36297 rtx op;
36298 machine_mode mode;
36309 {
37019 }
37024 {
37027 }
37030 {
37037 }
37038 else
37039 {
37042 }
37045 {
37052 {
37053 /* SIMD shift insns take either an 8-bit immediate or
37054 register as count. But builtin functions take int as
37055 count. If count doesn't match, we put it in register. */
37057 {
37061 }
37062 }
37065 {
37068 {
37177 {
37181 {
37184 }
37190 }
37192 }
37193 }
37194 else
37195 {
37199 /* If we aren't optimizing, only allow one memory operand to
37200 be generated. */
37202 num_memory++;
37205 {
37208 }
37209 else
37210 {
37213 }
37214 }
37218 }
37221 {
37246 }
37253 }
37255 /* Transform pattern of following layout:
37256 (parallel [
37257 set (A B)
37258 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37259 ])
37260 into:
37261 (set (A B))
37263 Or:
37264 (parallel [ A B
37265 ...
37266 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37267 ...
37268 ])
37269 into:
37270 (parallel [ A B ... ]) */
37272 static rtx
37274 {
37281 {
37290 }
37291 else
37292 {
37298 {
37303 }
37305 /* No more than 1 occurence was removed. */
37309 }
37310 }
37312 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37313 with rounding. */
37314 static rtx
37317 {
37334 /* See avxintrin.h for values. */
37336 {
37340 };
37342 {
37347 };
37350 {
37353 }
37355 {
37358 }
37361 {
37364 }
37387 ? CODE_FOR_sse_ucomi_round
37394 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37396 {
37402 }
37403 else
37404 {
37407 }
37413 set_dst,
37414 const0_rtx)));
37417 }
37419 static rtx
37422 {
37423 rtx pat;
37425 struct
37426 {
37427 rtx op;
37428 machine_mode mode;
37437 {
37520 }
37530 {
37537 {
37539 {
37541 {
37557 }
37558 }
37559 }
37561 {
37563 {
37566 }
37568 /* If there is no rounding use normal version of the pattern. */
37571 }
37572 else
37573 {
37578 {
37581 }
37582 else
37583 {
37586 }
37587 }
37591 }
37594 {
37619 }
37629 }
37631 /* Subroutine of ix86_expand_builtin to take care of special insns
37632 with variable number of operands. */
37634 static rtx
37637 {
37638 tree arg;
37642 struct
37643 {
37644 rtx op;
37645 machine_mode mode;
37654 {
37694 {
37702 }
37721 /* Reserve memory operand for target. */
37724 {
37725 /* These builtins and instructions require the memory
37726 to be properly aligned. */
37745 }
37774 {
37775 /* These builtins and instructions require the memory
37776 to be properly aligned. */
37793 }
37794 /* FALLTHRU */
37832 /* Reserve memory operand for target. */
37859 {
37860 /* These builtins and instructions require the memory
37861 to be properly aligned. */
37884 }
37897 }
37902 {
37907 {
37910 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
37911 on it. Try to improve it using get_pointer_alignment,
37912 and if the special builtin is one that requires strict
37913 mode alignment, also from it's GET_MODE_ALIGNMENT.
37914 Failure to do so could lead to ix86_legitimate_combined_insn
37915 rejecting all changes to such insns. */
37921 }
37922 else
37925 }
37926 else
37927 {
37934 }
37937 {
37946 {
37948 {
37954 else
37957 }
37958 }
37959 else
37960 {
37962 {
37963 /* This must be the memory operand. */
37966 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
37967 on it. Try to improve it using get_pointer_alignment,
37968 and if the special builtin is one that requires strict
37969 mode alignment, also from it's GET_MODE_ALIGNMENT.
37970 Failure to do so could lead to ix86_legitimate_combined_insn
37971 rejecting all changes to such insns. */
37977 }
37978 else
37979 {
37980 /* This must be register. */
37986 else
37987 {
37990 }
37991 }
37992 }
37996 }
37999 {
38014 }
38020 }
38022 /* Return the integer constant in ARG. Constrain it to be in the range
38023 of the subparts of VEC_TYPE; issue an error if not. */
38025 static int
38027 {
38032 {
38035 }
38038 }
38040 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38041 ix86_expand_vector_init. We DO have language-level syntax for this, in
38042 the form of (type){ init-list }. Except that since we can't place emms
38043 instructions from inside the compiler, we can't allow the use of MMX
38044 registers unless the user explicitly asks for it. So we do *not* define
38045 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38046 we have builtins invoked by mmintrin.h that gives us license to emit
38047 these sorts of instructions. */
38049 static rtx
38051 {
38061 {
38064 }
38071 }
38073 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38074 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38075 had a language-level syntax for referencing vector elements. */
38077 static rtx
38079 {
38083 rtx op0;
38103 }
38105 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38106 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38107 a language-level syntax for referencing vector elements. */
38109 static rtx
38111 {
38135 /* OP0 is the source of these builtin functions and shouldn't be
38136 modified. Create a copy, use it and return it as target. */
38142 }
38144 /* Emit conditional move of SRC to DST with condition
38145 OP1 CODE OP2. */
38146 static void
38148 {
38149 rtx t;
38152 {
38157 }
38158 else
38159 {
38165 }
38166 }
38168 /* Choose max of DST and SRC and put it to DST. */
38169 static void
38171 {
38173 }
38175 /* Expand an expression EXP that calls a built-in function,
38176 with result going to TARGET if that's convenient
38177 (and in mode MODE if that's convenient).
38178 SUBTARGET may be used as the target for computing one of EXP's operands.
38179 IGNORE is nonzero if the value is to be ignored. */
38181 static rtx
38184 {
38194 /* For CPU builtins that can be folded, fold first and expand the fold. */
38196 {
38198 {
38199 /* Make it call __cpu_indicator_init in libgcc. */
38205 }
38208 {
38213 }
38214 }
38216 /* Determine whether the builtin function is available under the current ISA.
38217 Originally the builtin was not created if it wasn't applicable to the
38218 current ISA based on the command line switches. With function specific
38219 options, we need to check in the context of the function making the call
38220 whether it is supported. */
38223 {
38229 else
38230 {
38234 }
38236 }
38239 {
38257 /* Builtin arg1 is size of block but instruction op1 should
38258 be (size - 1). */
38349 /* If no bounds were specified for returned value,
38350 then use INIT bounds. It usually happens when
38351 some built-in function is expanded. */
38353 {
38362 }
38368 {
38371 /* Return value and lb. */
38373 /* Bounds. */
38375 /* Size. */
38382 /* Size was passed but we need to use (size - 1) as for bndmk. */
38386 /* Add LB to size and inverse to get UB. */
38396 /* We need to move bounds to memory before any computations. */
38399 else
38400 {
38403 }
38405 /* Generate mem expression to be used for access to LB and UB. */
38411 /* Compute LB. */
38416 /* Compute UB. UB is stored in 1's complement form. Therefore
38417 we also use max here. */
38426 }
38429 {
38447 /* Put first bounds to temporaries. */
38451 {
38455 }
38456 else
38457 {
38461 }
38463 /* Put second bounds to temporaries. */
38467 {
38471 }
38472 else
38473 {
38477 }
38479 /* Compute LB. */
38483 /* Compute UB. UB is stored in 1's complement form. Therefore
38484 we also use max here. */
38491 }
38494 {
38495 tree name;
38496 rtx symbol;
38514 }
38517 {
38528 /* We need to move bounds to memory first. */
38531 else
38532 {
38535 }
38537 /* Generate mem expression to access LB and load it. */
38542 }
38545 {
38556 /* We need to move bounds to memory first. */
38559 else
38560 {
38563 }
38565 /* Generate mem expression to access UB. */
38568 /* We need to inverse all bits of UB. */
38575 }
38580 ? CODE_FOR_mmx_maskmovq
38582 /* Note the arg order is different from the operand order. */
38693 {
38694 REAL_VALUE_TYPE inf;
38695 rtx tmp;
38707 }
38717 {
38723 insn = (TARGET_64BIT
38727 }
38729 {
38730 insn = (TARGET_64BIT
38734 }
38735 else
38736 {
38739 insn = (TARGET_64BIT
38747 {
38750 }
38752 }
38755 {
38756 /* mode is VOIDmode if __builtin_rd* has been called
38757 without lhs. */
38761 }
38764 {
38769 }
38782 {
38803 }
38809 {
38812 }
38838 {
38841 }
38847 {
38851 {
38890 }
38895 }
38896 else
38897 {
38899 {
38920 }
38922 }
38952 ? CODE_FOR_tbm_bextri_si
38955 {
38958 }
38959 else
38960 {
38969 }
38985 rdrand_step:
38992 {
38995 }
39001 /* Emit SImode conditional move. */
39003 {
39006 }
39009 else
39017 const0_rtx);
39036 rdseed_step:
39043 {
39046 }
39052 const0_rtx);
39081 addcarryx:
39089 /* Generate CF from input operand. */
39094 /* Gen ADCX instruction to compute X+Y+CF. */
39109 /* Store the result. */
39112 {
39115 }
39118 /* Return current CF value. */
39160 kortest:
39174 /* Emit kortest. */
39176 /* And use setcc to return result from flags. */
39434 gather_gen:
39435 rtx half;
39448 /* Note the arg order is different from the operand order. */
39459 else
39463 {
39487 else
39494 {
39499 }
39508 else
39515 {
39520 }
39524 }
39526 /* Force memory operand only with base register here. But we
39527 don't want to do it on memory operand for other builtin
39528 functions. */
39538 {
39541 }
39542 else
39543 {
39546 }
39548 {
39551 }
39553 /* Optimize. If mask is known to have all high bits set,
39554 replace op0 with pc_rtx to signal that the instruction
39555 overwrites the whole destination and doesn't use its
39556 previous contents. */
39558 {
39560 {
39563 }
39565 {
39568 {
39572 negative++;
39575 negative++;
39576 }
39579 }
39582 {
39583 /* Recognize also when mask is like:
39584 __v2df src = _mm_setzero_pd ();
39585 __v2df mask = _mm_cmpeq_pd (src, src);
39586 or
39587 __v8sf src = _mm256_setzero_ps ();
39588 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
39589 as that is a cheaper way to load all ones into
39590 a register than having to load a constant from
39591 memory. */
39594 {
39599 {
39606 /* FALLTHRU */
39616 }
39617 }
39618 }
39619 }
39627 {
39653 }
39656 scatter_gen:
39672 /* Force memory operand only with base register here. But we
39673 don't want to do it on memory operand for other builtin
39674 functions. */
39681 {
39684 }
39685 else
39686 {
39689 }
39698 {
39701 }
39710 vec_prefetch_gen:
39728 {
39731 }
39733 {
39736 }
39741 /* Force memory operand only with base register here. But we
39742 don't want to do it on memory operand for other builtin
39743 functions. */
39750 {
39753 }
39756 {
39759 }
39775 {
39778 }
39784 }
39797 {
39801 /* Emit a normal call if SSE isn't available. */
39805 }
39834 }
39836 /* This returns the target-specific builtin with code CODE if
39837 current_function_decl has visibility on this builtin, which is checked
39838 using isa flags. Returns NULL_TREE otherwise. */
39841 {
39845 /* Determine the isa flags of current_function_decl. */
39857 else
39859 }
39861 /* Return function decl for target specific builtin
39862 for given MPX builtin passed i FCODE. */
39863 static tree
39865 {
39867 {
39903 }
39906 }
39908 /* Helper function for ix86_load_bounds and ix86_store_bounds.
39910 Return an address to be used to load/store bounds for pointer
39911 passed in SLOT.
39913 SLOT_NO is an integer constant holding number of a target
39914 dependent special slot to be used in case SLOT is not a memory.
39916 SPECIAL_BASE is a pointer to be used as a base of fake address
39917 to access special slots in Bounds Table. SPECIAL_BASE[-1],
39918 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
39920 static rtx
39922 {
39925 /* NULL slot means we pass bounds for pointer not passed to the
39926 function at all. Register slot means we pass pointer in a
39927 register. In both these cases bounds are passed via Bounds
39928 Table. Since we do not have actual pointer stored in memory,
39929 we have to use fake addresses to access Bounds Table. We
39930 start with (special_base - sizeof (void*)) and decrease this
39931 address by pointer size to get addresses for other slots. */
39933 {
39937 }
39938 /* If pointer is passed in a memory then its address is used to
39939 access Bounds Table. */
39941 {
39945 }
39946 else
39950 }
39952 /* Expand pass uses this hook to load bounds for function parameter
39953 PTR passed in SLOT in case its bounds are not passed in a register.
39955 If SLOT is a memory, then bounds are loaded as for regular pointer
39956 loaded from memory. PTR may be NULL in case SLOT is a memory.
39957 In such case value of PTR (if required) may be loaded from SLOT.
39959 If SLOT is NULL or a register then SLOT_NO is an integer constant
39960 holding number of the target dependent special slot which should be
39961 used to obtain bounds.
39963 Return loaded bounds. */
39965 static rtx
39967 {
39969 rtx addr;
39971 /* Get address to be used to access Bounds Table. Special slots start
39972 at the location of return address of the current function. */
39975 /* Load pointer value from a memory if we don't have it. */
39977 {
39980 }
39987 }
39989 /* Expand pass uses this hook to store BOUNDS for call argument PTR
39990 passed in SLOT in case BOUNDS are not passed in a register.
39992 If SLOT is a memory, then BOUNDS are stored as for regular pointer
39993 stored in memory. PTR may be NULL in case SLOT is a memory.
39994 In such case value of PTR (if required) may be loaded from SLOT.
39996 If SLOT is NULL or a register then SLOT_NO is an integer constant
39997 holding number of the target dependent special slot which should be
39998 used to store BOUNDS. */
40000 static void
40002 {
40003 rtx addr;
40005 /* Get address to be used to access Bounds Table. Special slots start
40006 at the location of return address of a called function. */
40009 /* Load pointer value from a memory if we don't have it. */
40011 {
40014 }
40023 }
40025 /* Load and return bounds returned by function in SLOT. */
40027 static rtx
40029 {
40030 rtx res;
40037 }
40039 /* Store BOUNDS returned by function into SLOT. */
40041 static void
40043 {
40046 }
40048 /* Returns a function decl for a vectorized version of the builtin function
40049 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40050 if it is not available. */
40052 static tree
40054 tree type_in)
40055 {
40071 {
40074 {
40081 }
40086 {
40089 }
40094 {
40101 }
40107 /* The round insn does not trap on denormals. */
40112 {
40119 }
40125 /* The round insn does not trap on denormals. */
40130 {
40135 }
40141 /* The round insn does not trap on denormals. */
40146 {
40153 }
40159 /* The round insn does not trap on denormals. */
40164 {
40169 }
40176 {
40181 }
40188 {
40193 }
40199 /* The round insn does not trap on denormals. */
40204 {
40211 }
40217 /* The round insn does not trap on denormals. */
40222 {
40227 }
40232 {
40239 }
40244 {
40251 }
40255 /* The round insn does not trap on denormals. */
40260 {
40265 }
40269 /* The round insn does not trap on denormals. */
40274 {
40279 }
40283 /* The round insn does not trap on denormals. */
40288 {
40293 }
40297 /* The round insn does not trap on denormals. */
40302 {
40307 }
40311 /* The round insn does not trap on denormals. */
40316 {
40321 }
40325 /* The round insn does not trap on denormals. */
40330 {
40335 }
40339 /* The round insn does not trap on denormals. */
40344 {
40349 }
40353 /* The round insn does not trap on denormals. */
40358 {
40363 }
40367 /* The round insn does not trap on denormals. */
40372 {
40377 }
40381 /* The round insn does not trap on denormals. */
40386 {
40391 }
40396 {
40401 }
40406 {
40411 }
40416 }
40418 /* Dispatch to a handler for a vectorization library. */
40421 type_in);
40424 }
40426 /* Handler for an SVML-style interface to
40427 a library with vectorized intrinsics. */
40429 static tree
40431 {
40439 /* The SVML is suitable for unsafe math only. */
40452 {
40499 }
40508 {
40511 }
40512 else
40515 /* Convert to uppercase. */
40520 args;
40522 arity++;
40526 else
40529 /* Build a function declaration for the vectorized function. */
40538 }
40540 /* Handler for an ACML-style interface to
40541 a library with vectorized intrinsics. */
40543 static tree
40545 {
40553 /* The ACML is 64bits only and suitable for unsafe math only as
40554 it does not correctly support parts of IEEE with the required
40555 precision such as denormals. */
40569 {
40599 }
40606 args;
40608 arity++;
40612 else
40615 /* Build a function declaration for the vectorized function. */
40624 }
40626 /* Returns a decl of a function that implements gather load with
40627 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
40628 Return NULL_TREE if it is not available. */
40630 static tree
40633 {
40649 /* v*gather* insn sign extends index to pointer mode. */
40661 {
40665 else
40671 else
40677 else
40683 else
40689 else
40695 else
40701 else
40707 else
40713 else
40719 else
40725 else
40731 else
40736 }
40739 }
40741 /* Returns a code for a target-specific builtin that implements
40742 reciprocal of the function, or NULL_TREE if not available. */
40744 static tree
40746 {
40753 /* Machine dependent builtins. */
40755 {
40756 /* Vectorized version of sqrt to rsqrt conversion. */
40765 }
40766 else
40767 /* Normal builtins. */
40769 {
40770 /* Sqrt to rsqrt conversion. */
40776 }
40777 }
40778 \f
40779 /* Helper for avx_vpermilps256_operand et al. This is also used by
40780 the expansion functions to turn the parallel back into a mask.
40781 The return value is 0 for no match and the imm8+1 for a match. */
40783 int
40785 {
40793 /* Validate that all of the elements are constants, and not totally
40794 out of range. Copy the data into an integral array to make the
40795 subsequent checks easier. */
40797 {
40807 }
40810 {
40812 /* In the 512-bit DFmode case, we can only move elements within
40813 a 128-bit lane. First fill the second part of the mask,
40814 then fallthru. */
40816 {
40820 }
40822 {
40826 }
40827 /* FALLTHRU */
40830 /* In the 256-bit DFmode case, we can only move elements within
40831 a 128-bit lane. */
40833 {
40837 }
40839 {
40843 }
40847 /* In 512 bit SFmode case, permutation in the upper 256 bits
40848 must mirror the permutation in the lower 256-bits. */
40852 /* FALLTHRU */
40855 /* In 256 bit SFmode case, we have full freedom of
40856 movement within the low 128-bit lane, but the high 128-bit
40857 lane must mirror the exact same pattern. */
40862 /* FALLTHRU */
40866 /* In the 128-bit case, we've full freedom in the placement of
40867 the elements from the source operand. */
40874 }
40876 /* Make sure success has a non-zero value by adding one. */
40878 }
40880 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
40881 the expansion functions to turn the parallel back into a mask.
40882 The return value is 0 for no match and the imm8+1 for a match. */
40884 int
40886 {
40894 /* Validate that all of the elements are constants, and not totally
40895 out of range. Copy the data into an integral array to make the
40896 subsequent checks easier. */
40898 {
40908 }
40910 /* Validate that the halves of the permute are halves. */
40918 /* Reconstruct the mask. */
40920 {
40926 }
40928 /* Make sure success has a non-zero value by adding one. */
40930 }
40931 \f
40932 /* Return a register priority for hard reg REGNO. */
40933 static int
40935 {
40936 /* ebp and r13 as the base always wants a displacement, r12 as the
40937 base always wants an index. So discourage their usage in an
40938 address. */
40943 /* New x86-64 int registers result in bigger code size. Discourage
40944 them. */
40947 /* New x86-64 SSE registers result in bigger code size. Discourage
40948 them. */
40951 /* Usage of AX register results in smaller code. Prefer it. */
40955 }
40957 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
40959 Put float CONST_DOUBLE in the constant pool instead of fp regs.
40960 QImode must go into class Q_REGS.
40961 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
40962 movdf to do mem-to-mem moves through integer regs. */
40964 static reg_class_t
40966 {
40969 /* We're only allowed to return a subclass of CLASS. Many of the
40970 following checks fail for NO_REGS, so eliminate that early. */
40974 /* All classes can load zeros. */
40978 /* Force constants into memory if we are loading a (nonzero) constant into
40979 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
40980 instructions to load from a constant. */
40987 /* Prefer SSE regs only, if we can use them for math. */
40991 /* Floating-point constants need more complex checks. */
40993 {
40994 /* General regs can load everything. */
40998 /* Floats can load 0 and 1 plus some others. Note that we eliminated
40999 zero above. We only want to wind up preferring 80387 registers if
41000 we plan on doing computation with them. */
41003 {
41004 /* Limit class to non-sse. */
41013 }
41016 }
41018 /* Generally when we see PLUS here, it's the function invariant
41019 (plus soft-fp const_int). Which can only be computed into general
41020 regs. */
41024 /* QImode constants are easy to load, but non-constant QImode data
41025 must go into Q_REGS. */
41027 {
41033 }
41036 }
41038 /* Discourage putting floating-point values in SSE registers unless
41039 SSE math is being used, and likewise for the 387 registers. */
41040 static reg_class_t
41042 {
41045 /* Restrict the output reload class to the register bank that we are doing
41046 math on. If we would like not to return a subset of CLASS, reject this
41047 alternative: if reload cannot do this, it will still use its choice. */
41053 {
41058 else
41060 }
41063 }
41065 static reg_class_t
41068 {
41069 /* Double-word spills from general registers to non-offsettable memory
41070 references (zero-extended addresses) require special handling. */
41076 {
41078 ? CODE_FOR_reload_noff_load
41080 /* Add the cost of moving address to a temporary. */
41084 }
41086 /* QImode spills from non-QI registers require
41087 intermediate register on 32bit targets. */
41093 {
41098 else
41104 /* Return Q_REGS if the operand is in memory. */
41107 }
41109 /* This condition handles corner case where an expression involving
41110 pointers gets vectorized. We're trying to use the address of a
41111 stack slot as a vector initializer.
41113 (set (reg:V2DI 74 [ vect_cst_.2 ])
41114 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41116 Eventually frame gets turned into sp+offset like this:
41118 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41119 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41120 (const_int 392 [0x188]))))
41122 That later gets turned into:
41124 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41125 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41126 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41128 We'll have the following reload recorded:
41130 Reload 0: reload_in (DI) =
41131 (plus:DI (reg/f:DI 7 sp)
41132 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41133 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41134 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41135 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41136 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41137 reload_reg_rtx: (reg:V2DI 22 xmm1)
41139 Which isn't going to work since SSE instructions can't handle scalar
41140 additions. Returning GENERAL_REGS forces the addition into integer
41141 register and reload can handle subsequent reloads without problems. */
41149 }
41151 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41153 static bool
41155 {
41157 {
41173 }
41176 }
41178 /* If we are copying between general and FP registers, we need a memory
41179 location. The same is true for SSE and MMX registers.
41181 To optimize register_move_cost performance, allow inline variant.
41183 The macro can't work reliably when one of the CLASSES is class containing
41184 registers from multiple units (SSE, MMX, integer). We avoid this by never
41185 combining those units in single alternative in the machine description.
41186 Ensure that this constraint holds to avoid unexpected surprises.
41188 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41189 enforce these sanity checks. */
41194 {
41203 {
41206 }
41211 /* Between mask and general, we have moves no larger than word size. */
41216 /* ??? This is a lie. We do have moves between mmx/general, and for
41217 mmx/sse2. But by saying we need secondary memory we discourage the
41218 register allocator from using the mmx registers unless needed. */
41223 {
41224 /* SSE1 doesn't have any direct moves from other classes. */
41228 /* If the target says that inter-unit moves are more expensive
41229 than moving through memory, then don't generate them. */
41234 /* Between SSE and general, we have moves no larger than word size. */
41237 }
41240 }
41242 bool
41245 {
41247 }
41249 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41251 On the 80386, this is the size of MODE in words,
41252 except in the FP regs, where a single reg is always enough. */
41254 static unsigned char
41256 {
41258 {
41263 else
41265 }
41266 else
41267 {
41270 else
41272 }
41273 }
41275 /* Return true if the registers in CLASS cannot represent the change from
41276 modes FROM to TO. */
41278 bool
41281 {
41285 /* x87 registers can't do subreg at all, as all values are reformatted
41286 to extended precision. */
41291 {
41292 /* Vector registers do not support QI or HImode loads. If we don't
41293 disallow a change to these modes, reload will assume it's ok to
41294 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41295 the vec_dupv4hi pattern. */
41298 }
41301 }
41303 /* Return the cost of moving data of mode M between a
41304 register and memory. A value of 2 is the default; this cost is
41305 relative to those in `REGISTER_MOVE_COST'.
41307 This function is used extensively by register_move_cost that is used to
41308 build tables at startup. Make it inline in this case.
41309 When IN is 2, return maximum of in and out move cost.
41311 If moving between registers and memory is more expensive than
41312 between two registers, you should define this macro to express the
41313 relative cost.
41315 Model also increased moving costs of QImode registers in non
41316 Q_REGS classes.
41317 */
41321 {
41324 {
41327 {
41339 }
41343 }
41345 {
41348 {
41360 }
41364 }
41366 {
41369 {
41378 }
41382 }
41384 {
41387 {
41393 else
41398 }
41399 else
41400 {
41405 else
41407 }
41414 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41421 else
41425 }
41426 }
41428 static int
41431 {
41433 }
41436 /* Return the cost of moving data from a register in class CLASS1 to
41437 one in class CLASS2.
41439 It is not required that the cost always equal 2 when FROM is the same as TO;
41440 on some machines it is expensive to move between registers if they are not
41441 general registers. */
41443 static int
41445 reg_class_t class2_i)
41446 {
41450 /* In case we require secondary memory, compute cost of the store followed
41451 by load. In order to avoid bad register allocation choices, we need
41452 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41455 {
41461 /* In case of copying from general_purpose_register we may emit multiple
41462 stores followed by single load causing memory size mismatch stall.
41463 Count this as arbitrarily high cost of 20. */
41468 /* In the case of FP/MMX moves, the registers actually overlap, and we
41469 have to switch modes in order to treat them differently. */
41475 }
41477 /* Moves between SSE/MMX and integer unit are expensive. */
41481 /* ??? By keeping returned value relatively high, we limit the number
41482 of moves between integer and MMX/SSE registers for all targets.
41483 Additionally, high value prevents problem with x86_modes_tieable_p(),
41484 where integer modes in MMX/SSE registers are not tieable
41485 because of missing QImode and HImode moves to, from or between
41486 MMX/SSE registers. */
41496 }
41498 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41499 MODE. */
41501 bool
41503 {
41504 /* Flags and only flags can only hold CCmode values. */
41519 {
41520 /* We implement the move patterns for all vector modes into and
41521 out of SSE registers, even when no operation instructions
41522 are available. */
41524 /* For AVX-512 we allow, regardless of regno:
41525 - XI mode
41526 - any of 512-bit wide vector mode
41527 - any scalar mode. */
41534 /* TODO check for QI/HI scalars. */
41535 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
41543 /* xmm16-xmm31 are only available for AVX-512. */
41547 /* OImode and AVX modes are available only when AVX is enabled. */
41554 }
41556 {
41557 /* We implement the move patterns for 3DNOW modes even in MMX mode,
41558 so if the register is available at all, then we can move data of
41559 the given mode into or out of it. */
41562 }
41565 {
41566 /* Take care for QImode values - they can be in non-QI regs,
41567 but then they do cause partial register stalls. */
41572 /* LRA checks if the hard register is OK for the given mode.
41573 QImode values can live in non-QI regs, so we allow all
41574 registers here. */
41578 }
41579 /* We handle both integer and floats in the general purpose registers. */
41586 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
41587 on to use that value in smaller contexts, this can easily force a
41588 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
41589 supporting DImode, allow it. */
41594 }
41596 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
41597 tieable integer mode. */
41599 static bool
41601 {
41603 {
41616 }
41617 }
41619 /* Return true if MODE1 is accessible in a register that can hold MODE2
41620 without copying. That is, all register classes that can hold MODE2
41621 can also hold MODE1. */
41623 bool
41625 {
41633 /* MODE2 being XFmode implies fp stack or general regs, which means we
41634 can tie any smaller floating point modes to it. Note that we do not
41635 tie this with TFmode. */
41639 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
41640 that we can tie it with SFmode. */
41644 /* If MODE2 is only appropriate for an SSE register, then tie with
41645 any other mode acceptable to SSE registers. */
41655 /* If MODE2 is appropriate for an MMX register, then tie
41656 with any other mode acceptable to MMX registers. */
41663 }
41665 /* Return the cost of moving between two registers of mode MODE. */
41667 static int
41669 {
41673 {
41705 }
41707 /* Return the cost of moving between two registers of mode MODE,
41708 assuming that the move will be in pieces of at most UNITS bytes. */
41710 }
41712 /* Compute a (partial) cost for rtx X. Return true if the complete
41713 cost has been computed, and false if subexpressions should be
41714 scanned. In either case, *TOTAL contains the cost result. */
41716 static bool
41719 {
41720 rtx mask;
41727 {
41731 {
41734 }
41746 && !(TARGET_64BIT
41751 else
41757 {
41760 }
41762 {
41772 }
41774 {
41777 {
41786 }
41787 }
41788 /* Fall back to (MEM (SYMBOL_REF)), since that's where
41789 it'll probably end up. Add a penalty for size. */
41796 /* The zero extensions is often completely free on x86_64, so make
41797 it as cheap as possible. */
41803 else
41815 {
41818 {
41821 }
41824 {
41827 }
41828 }
41829 /* FALLTHRU */
41836 {
41837 /* ??? Should be SSE vector operation cost. */
41838 /* At least for published AMD latencies, this really is the same
41839 as the latency for a simple fpu operation like fabs. */
41840 /* V*QImode is emulated with 1-11 insns. */
41842 {
41845 {
41846 /* For XOP we use vpshab, which requires a broadcast of the
41847 value to the variable shift insn. For constants this
41848 means a V16Q const in mem; even when we can perform the
41849 shift with one insn set the cost to prefer paddb. */
41851 {
41856 }
41858 }
41862 }
41863 else
41865 }
41867 {
41869 {
41872 else
41874 }
41875 else
41876 {
41879 else
41881 }
41882 }
41883 else
41884 {
41889 {
41890 /* Return the cost after shift-and truncation. */
41893 }
41894 else
41896 }
41900 {
41901 rtx sub;
41906 /* ??? SSE scalar/vector cost should be used here. */
41907 /* ??? Bald assumption that fma has the same cost as fmul. */
41911 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
41922 }
41926 {
41927 /* ??? SSE scalar cost should be used here. */
41930 }
41932 {
41935 }
41937 {
41938 /* ??? SSE vector cost should be used here. */
41941 }
41943 {
41944 /* V*QImode is emulated with 7-13 insns. */
41946 {
41953 }
41954 /* V*DImode is emulated with 5-8 insns. */
41956 {
41959 else
41961 }
41962 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
41963 insns, including two PMULUDQ. */
41966 else
41969 }
41970 else
41971 {
41976 {
41979 nbits++;
41980 }
41981 else
41982 /* This is arbitrary. */
41985 /* Compute costs correctly for widening multiplication. */
41989 {
41996 {
42000 else
42002 }
42006 }
42014 }
42021 /* ??? SSE cost should be used here. */
42026 /* ??? SSE vector cost should be used here. */
42028 else
42035 {
42040 {
42043 {
42051 }
42052 }
42055 {
42058 {
42064 }
42065 }
42067 {
42075 }
42076 }
42077 /* FALLTHRU */
42081 {
42082 /* ??? SSE cost should be used here. */
42085 }
42087 {
42090 }
42092 {
42093 /* ??? SSE vector cost should be used here. */
42096 }
42097 /* FALLTHRU */
42104 {
42111 }
42112 /* FALLTHRU */
42116 {
42117 /* ??? SSE cost should be used here. */
42120 }
42122 {
42125 }
42127 {
42128 /* ??? SSE vector cost should be used here. */
42131 }
42132 /* FALLTHRU */
42136 {
42137 /* ??? Should be SSE vector operation cost. */
42138 /* At least for published AMD latencies, this really is the same
42139 as the latency for a simple fpu operation like fabs. */
42141 }
42144 else
42153 {
42154 /* This kind of construct is implemented using test[bwl].
42155 Treat it as if we had an AND. */
42160 }
42170 /* ??? SSE cost should be used here. */
42175 /* ??? SSE vector cost should be used here. */
42181 /* ??? SSE cost should be used here. */
42186 /* ??? SSE vector cost should be used here. */
42198 /* ??? Assume all of these vector manipulation patterns are
42199 recognizable. In which case they all pretty much have the
42200 same cost. */
42205 /* This is masked instruction, assume the same cost,
42206 as nonmasked variant. */
42209 else
42215 }
42216 }
42218 #if TARGET_MACHO
42222 /* Given a symbol name and its associated stub, write out the
42223 definition of the stub. */
42225 void
42227 {
42232 /* For 64-bit we shouldn't get here. */
42235 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42252 else
42259 {
42261 }
42263 {
42264 /* PIC stub. */
42265 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42271 }
42272 else
42275 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42276 it needs no stub-binding-helper. */
42283 {
42286 }
42287 else
42292 /* N.B. Keep the correspondence of these
42293 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42294 old-pic/new-pic/non-pic stubs; altering this will break
42295 compatibility with existing dylibs. */
42297 {
42298 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42300 }
42301 else
42302 /* 16-byte -mdynamic-no-pic stub. */
42308 }
42311 /* Order the registers for register allocator. */
42313 void
42315 {
42319 /* First allocate the local general purpose registers. */
42324 /* Global general purpose registers. */
42329 /* x87 registers come first in case we are doing FP math
42330 using them. */
42335 /* SSE registers. */
42341 /* Extended REX SSE registers. */
42345 /* Mask register. */
42349 /* MPX bound registers. */
42353 /* x87 registers. */
42361 /* Initialize the rest of array as we do not allocate some registers
42362 at all. */
42365 }
42367 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42368 in struct attribute_spec handler. */
42369 static tree
42371 tree args,
42374 {
42379 {
42381 name);
42384 }
42386 {
42388 name);
42391 }
42393 {
42394 tree cst;
42398 {
42401 name);
42403 }
42406 {
42409 name);
42411 }
42414 }
42417 }
42419 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42420 struct attribute_spec.handler. */
42421 static tree
42424 {
42429 {
42431 name);
42434 }
42436 /* Can combine regparm with all attributes but fastcall. */
42438 {
42440 {
42442 }
42445 }
42447 {
42449 {
42451 }
42454 }
42457 }
42459 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42460 struct attribute_spec.handler. */
42461 static tree
42464 {
42467 {
42470 }
42471 else
42475 {
42477 name);
42479 }
42485 {
42487 name);
42489 }
42492 }
42494 static tree
42497 {
42499 {
42501 name);
42503 }
42505 }
42507 static bool
42509 {
42513 }
42515 /* Returns an expression indicating where the this parameter is
42516 located on entry to the FUNCTION. */
42518 static rtx
42520 {
42526 {
42531 else
42534 }
42539 {
42546 {
42551 }
42552 else
42553 {
42556 {
42562 }
42563 }
42565 }
42569 }
42571 /* Determine whether x86_output_mi_thunk can succeed. */
42573 static bool
42575 const_tree function)
42576 {
42577 /* 64-bit can handle anything. */
42581 /* For 32-bit, everything's fine if we have one free register. */
42585 /* Need a free register for vcall_offset. */
42589 /* Need a free register for GOT references. */
42593 /* Otherwise ok. */
42595 }
42597 /* Output the assembler code for a thunk function. THUNK_DECL is the
42598 declaration for the thunk function itself, FUNCTION is the decl for
42599 the target function. DELTA is an immediate constant offset to be
42600 added to THIS. If VCALL_OFFSET is nonzero, the word at
42601 *(*this + vcall_offset) should be added to THIS. */
42603 static void
42606 {
42614 else
42615 {
42621 else
42623 }
42627 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
42628 pull it in now and let DELTA benefit. */
42632 {
42633 /* Put the this parameter into %eax. */
42636 }
42637 else
42640 /* Adjust the this parameter by a fixed constant. */
42642 {
42647 {
42649 {
42653 }
42654 }
42657 }
42659 /* Adjust the this parameter by a value stored in the vtable. */
42661 {
42671 /* Adjust the this parameter. */
42675 {
42679 }
42686 vcall_mem));
42687 else
42689 }
42691 /* If necessary, drop THIS back to its stack slot. */
42697 {
42700 ;
42701 else
42702 {
42706 }
42707 }
42708 else
42709 {
42711 ;
42712 #if TARGET_MACHO
42714 {
42717 }
42719 else
42720 {
42728 }
42729 }
42731 /* Our sibling call patterns do not allow memories, because we have no
42732 predicate that can distinguish between frame and non-frame memory.
42733 For our purposes here, we can get away with (ab)using a jump pattern,
42734 because we're going to do no optimization. */
42736 {
42738 {
42744 }
42745 else
42747 }
42748 else
42749 {
42751 {
42752 // CM_LARGE_PIC always uses pseudo PIC register which is
42753 // uninitialized. Since FUNCTION is local and calling it
42754 // doesn't go through PLT, we use scratch register %r11 as
42755 // PIC register and initialize it here.
42760 }
42763 {
42769 }
42775 }
42778 /* Emit just enough of rest_of_compilation to get the insns emitted.
42779 Note that use_thunk calls assemble_start_function et al. */
42785 }
42787 static void
42789 {
42793 #if TARGET_MACHO
42795 #endif
42802 }
42804 int
42806 {
42807 machine_mode mode;
42818 }
42820 /* Print call to TARGET to FILE. */
42822 static void
42824 {
42827 else
42829 }
42831 /* Output assembler code to FILE to increment profiler label # LABELNO
42832 for profiling a function entry. */
42833 void
42835 {
42839 {
42840 #ifndef NO_PROFILE_COUNTERS
42842 #endif
42846 else
42848 }
42850 {
42851 #ifndef NO_PROFILE_COUNTERS
42854 #endif
42856 }
42857 else
42858 {
42859 #ifndef NO_PROFILE_COUNTERS
42862 #endif
42864 }
42867 {
42871 }
42872 }
42874 /* We don't have exact information about the insn sizes, but we may assume
42875 quite safely that we are informed about all 1 byte insns and memory
42876 address sizes. This is enough to eliminate unnecessary padding in
42877 99% of cases. */
42879 static int
42881 {
42887 /* Discard alignments we've emit and jump instructions. */
42892 /* Important case - calls are always 5 bytes.
42893 It is common to have many calls in the row. */
42902 /* For normal instructions we rely on get_attr_length being exact,
42903 with a few exceptions. */
42905 {
42909 {
42919 /* Otherwise trust get_attr_length. */
42921 }
42926 }
42929 else
42931 }
42933 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
42935 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
42936 window. */
42938 static void
42940 {
42945 /* Look for all minimal intervals of instructions containing 4 jumps.
42946 The intervals are bounded by START and INSN. NBYTES is the total
42947 size of instructions in the interval including INSN and not including
42948 START. When the NBYTES is smaller than 16 bytes, it is possible
42949 that the end of START and INSN ends up in the same 16byte page.
42951 The smallest offset in the page INSN can start is the case where START
42952 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
42953 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
42955 Don't consider asm goto as jump, while it can contain a jump, it doesn't
42956 have to, control transfer to label(s) can be performed through other
42957 means, and also we estimate minimum length of all asm stmts as 0. */
42959 {
42963 {
42969 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
42970 already in the current 16 byte page, because otherwise
42971 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
42972 bytes to reach 16 byte boundary. */
42980 {
42982 {
42987 else
42990 }
42991 }
42993 }
43002 njumps++;
43003 else
43007 {
43012 else
43015 }
43022 {
43029 }
43030 }
43031 }
43032 #endif
43034 /* AMD Athlon works faster
43035 when RET is not destination of conditional jump or directly preceded
43036 by other jump instruction. We avoid the penalty by inserting NOP just
43037 before the RET instructions in such cases. */
43038 static void
43040 {
43041 edge e;
43042 edge_iterator ei;
43045 {
43058 {
43059 edge e;
43060 edge_iterator ei;
43065 {
43068 }
43069 }
43071 {
43077 /* Empty functions get branch mispredict even when
43078 the jump destination is not visible to us. */
43081 }
43083 {
43086 }
43087 }
43088 }
43090 /* Count the minimum number of instructions in BB. Return 4 if the
43091 number of instructions >= 4. */
43093 static int
43095 {
43099 /* Count number of instructions in this block. Return 4 if the number
43100 of instructions >= 4. */
43102 {
43103 /* Only happen in exit blocks. */
43111 {
43112 insn_count++;
43115 }
43116 }
43119 }
43122 /* Count the minimum number of instructions in code path in BB.
43123 Return 4 if the number of instructions >= 4. */
43125 static int
43127 {
43128 edge e;
43129 edge_iterator ei;
43132 /* Only bother counting instructions along paths with no
43133 more than 2 basic blocks between entry and exit. Given
43134 that BB has an edge to exit, determine if a predecessor
43135 of BB has an edge from entry. If so, compute the number
43136 of instructions in the predecessor block. If there
43137 happen to be multiple such blocks, compute the minimum. */
43140 {
43141 edge prev_e;
43142 edge_iterator prev_ei;
43145 {
43148 }
43150 {
43152 {
43157 }
43158 }
43159 }
43165 }
43167 /* Pad short function to 4 instructions. */
43169 static void
43171 {
43172 edge e;
43173 edge_iterator ei;
43176 {
43179 {
43182 /* Pad short function. */
43184 {
43187 /* Find epilogue. */
43196 /* Two NOPs count as one instruction. */
43199 }
43200 }
43201 }
43202 }
43204 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43205 the epilogue, the Windows system unwinder will apply epilogue logic and
43206 produce incorrect offsets. This can be avoided by adding a nop between
43207 the last insn that can throw and the first insn of the epilogue. */
43209 static void
43211 {
43212 edge e;
43213 edge_iterator ei;
43216 {
43219 /* Find the beginning of the epilogue. */
43226 /* We only care about preceding insns that can throw. */
43231 /* Do not separate calls from their debug information. */
43237 else
43241 }
43242 }
43244 /* Implement machine specific optimizations. We implement padding of returns
43245 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43246 static void
43248 {
43249 /* We are freeing block_for_insn in the toplev to keep compatibility
43250 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43257 {
43262 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43265 #endif
43266 }
43267 }
43269 /* Return nonzero when QImode register that must be represented via REX prefix
43270 is used. */
43271 bool
43273 {
43281 }
43283 /* Return true when INSN mentions register that must be encoded using REX
43284 prefix. */
43285 bool
43287 {
43290 {
43295 }
43297 }
43299 /* If profitable, negate (without causing overflow) integer constant
43300 of mode MODE at location LOC. Return true in this case. */
43301 bool
43303 {
43304 HOST_WIDE_INT val;
43310 {
43312 /* DImode x86_64 constants must fit in 32 bits. */
43325 }
43327 /* Avoid overflows. */
43333 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43334 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43337 {
43340 }
43343 }
43345 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43346 optabs would emit if we didn't have TFmode patterns. */
43348 void
43350 {
43385 }
43386 \f
43392 /* Get a vector mode of the same size as the original but with elements
43393 twice as wide. This is only guaranteed to apply to integral vectors. */
43397 {
43398 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43403 }
43405 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43406 fill target with val via vec_duplicate. */
43408 static bool
43410 {
43413 rtx dup;
43415 /* First attempt to recognize VAL as-is. */
43419 {
43421 /* If that fails, force VAL into a register. */
43432 }
43434 }
43436 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43437 with all elements equal to VAR. Return true if successful. */
43439 static bool
43442 {
43446 {
43451 /* FALLTHRU */
43471 {
43472 rtx x;
43479 }
43492 {
43496 permute:
43504 /* Extend to SImode using a paradoxical SUBREG. */
43508 /* Insert the SImode value as low element of a V4SImode vector. */
43517 }
43528 widen:
43529 /* Replicate the value once into the next wider mode and recurse. */
43530 {
43532 rtx x;
43549 }
43555 else
43556 {
43565 }
43572 else
43573 {
43582 }
43587 }
43588 }
43590 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43591 whose ONE_VAR element is VAR, and other elements are zero. Return true
43592 if successful. */
43594 static bool
43597 {
43598 machine_mode vsimode;
43599 rtx new_target;
43604 {
43606 /* For SSE4.1, we normally use vector set. But if the second
43607 element is zero and inter-unit moves are OK, we use movq
43608 instead. */
43610 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
43632 /* Use ix86_expand_vector_set in 64bit mode only. */
43637 }
43640 {
43645 }
43648 {
43653 /* FALLTHRU */
43668 else
43675 {
43676 /* We need to shuffle the value to the correct position, so
43677 create a new pseudo to store the intermediate result. */
43679 /* With SSE2, we can use the integer shuffle insns. */
43681 {
43683 const1_rtx,
43690 }
43692 /* Otherwise convert the intermediate result to V4SFmode and
43693 use the SSE1 shuffle instructions. */
43695 {
43698 }
43699 else
43703 const1_rtx,
43712 }
43727 widen:
43731 /* Zero extend the variable element to SImode and recurse. */
43744 }
43745 }
43747 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43748 consisting of the values in VALS. It is known that all elements
43749 except ONE_VAR are constants. Return true if successful. */
43751 static bool
43754 {
43756 machine_mode wmode;
43764 {
43769 /* For the two element vectors, it's just as easy to use
43770 the general case. */
43774 /* Use ix86_expand_vector_set in 64bit mode only. */
43796 widen:
43797 /* There's no way to set one QImode entry easily. Combine
43798 the variable value with its adjacent constant value, and
43799 promote to an HImode set. */
43802 {
43807 }
43808 else
43809 {
43812 }
43826 }
43831 }
43833 /* A subroutine of ix86_expand_vector_init_general. Use vector
43834 concatenate to handle the most general case: all values variable,
43835 and none identical. */
43837 static void
43840 {
43843 rtvec v;
43847 {
43850 {
43895 }
43908 {
43923 }
43928 {
43947 }
43952 {
43965 }
43968 half:
43969 /* FIXME: We process inputs backward to help RA. PR 36222. */
43973 {
43978 }
43982 {
43986 {
43990 }
43993 {
43997 }
44000 }
44002 {
44005 {
44009 }
44012 }
44013 else
44019 }
44020 }
44022 /* A subroutine of ix86_expand_vector_init_general. Use vector
44023 interleave to handle the most general case: all values variable,
44024 and none identical. */
44026 static void
44029 {
44038 {
44059 }
44062 {
44063 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44067 /* Insert the SImode value as low element of V4SImode vector. */
44071 op0),
44073 const1_rtx);
44076 /* Cast the V4SImode vector back to a vector in orignal mode. */
44080 /* Load even elements into the second position. */
44084 const1_rtx));
44086 /* Cast vector to FIRST_IMODE vector. */
44089 }
44091 /* Interleave low FIRST_IMODE vectors. */
44093 {
44097 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44100 }
44102 /* Interleave low SECOND_IMODE vectors. */
44104 {
44107 {
44112 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44113 vector. */
44116 }
44119 /* FALLTHRU */
44126 /* Cast the SECOND_IMODE vector back to a vector on original
44127 mode. */
44134 }
44135 }
44137 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44138 all values variable, and none identical. */
44140 static void
44143 {
44150 {
44155 /* FALLTHRU */
44183 half:
44207 quarter:
44236 /* FALLTHRU */
44242 /* Don't use ix86_expand_vector_init_interleave if we can't
44243 move from GPR to SSE register directly. */
44259 }
44261 {
44263 machine_mode inner_mode;
44273 {
44277 {
44283 else
44284 {
44289 }
44290 }
44293 }
44298 {
44304 }
44306 {
44312 }
44313 else
44315 }
44316 }
44318 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44319 instructions unless MMX_OK is true. */
44321 void
44323 {
44330 rtx x;
44333 {
44343 }
44345 /* Constants are best loaded from the constant pool. */
44347 {
44350 }
44352 /* If all values are identical, broadcast the value. */
44358 /* Values where only one field is non-constant are best loaded from
44359 the pool and overwritten via move later. */
44361 {
44365 one_var))
44370 }
44373 }
44375 void
44377 {
44380 machine_mode half_mode;
44382 rtx tmp;
44384 = {
44391 };
44393 = {
44400 };
44404 {
44408 {
44413 else
44417 }
44429 else
44435 {
44438 /* For the two element vectors, we implement a VEC_CONCAT with
44439 the extraction of the other element. */
44446 else
44451 }
44460 {
44466 /* tmp = target = A B C D */
44468 /* target = A A B B */
44470 /* target = X A B B */
44472 /* target = A X C D */
44479 /* tmp = target = A B C D */
44481 /* tmp = X B C D */
44483 /* target = A B X D */
44490 /* tmp = target = A B C D */
44492 /* tmp = X B C D */
44494 /* target = A B X D */
44502 }
44510 /* Element 0 handled by vec_merge below. */
44512 {
44515 }
44518 {
44519 /* With SSE2, use integer shuffles to swap element 0 and ELT,
44520 store into element 0, then shuffle them back. */
44537 }
44538 else
44539 {
44540 /* For SSE1, we have to reuse the V4SF code. */
44544 }
44597 half:
44598 /* Compute offset. */
44604 /* Extract the half. */
44608 /* Put val in tmp at elt. */
44611 /* Put it back. */
44617 {
44624 }
44625 else
44629 {
44636 }
44637 else
44641 {
44648 }
44649 else
44653 {
44660 }
44661 else
44665 {
44672 }
44673 else
44677 {
44684 }
44685 else
44690 }
44693 {
44697 }
44698 else
44699 {
44708 }
44709 }
44711 void
44713 {
44717 rtx tmp;
44720 {
44725 /* FALLTHRU */
44738 {
44758 }
44770 {
44772 {
44792 }
44796 }
44797 else
44798 {
44799 /* For SSE1, we have to reuse the V4SF code. */
44803 }
44819 {
44823 else
44827 }
44832 {
44836 else
44840 }
44845 {
44849 else
44853 }
44858 {
44862 else
44866 }
44871 {
44875 else
44879 }
44884 {
44888 else
44892 }
44897 {
44901 else
44905 }
44910 {
44914 else
44918 }
44925 else
44934 else
44943 else
44952 else
44958 /* ??? Could extract the appropriate HImode element and shift. */
44961 }
44964 {
44968 /* Let the rtl optimizers know about the zero extension performed. */
44970 {
44973 }
44976 }
44977 else
44978 {
44985 }
44986 }
44988 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
44989 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
44990 The upper bits of DEST are undefined, though they shouldn't cause
44991 exceptions (some bits from src or all zeros are ok). */
44993 static void
44995 {
44998 {
45002 else
45020 else
45027 else
45035 {
45040 const1_rtx);
45041 }
45042 else
45043 {
45047 }
45069 else
45091 }
45095 }
45097 /* Expand a vector reduction. FN is the binary pattern to reduce;
45098 DEST is the destination; IN is the input vector. */
45100 void
45102 {
45107 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45111 {
45114 }
45119 {
45124 else
45128 }
45129 }
45130 \f
45131 /* Target hook for scalar_mode_supported_p. */
45132 static bool
45134 {
45139 else
45141 }
45143 /* Implements target hook vector_mode_supported_p. */
45144 static bool
45146 {
45160 }
45162 /* Implement target hook libgcc_floating_mode_supported_p. */
45163 static bool
45165 {
45167 {
45174 #ifdef IX86_NO_LIBGCC_TFMODE
45176 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45178 #else
45180 #endif
45184 }
45185 }
45187 /* Target hook for c_mode_for_suffix. */
45188 static machine_mode
45190 {
45197 }
45199 /* Worker function for TARGET_MD_ASM_CLOBBERS.
45201 We do this in the new i386 backend to maintain source compatibility
45202 with the old cc0-based compiler. */
45204 static tree
45206 {
45208 clobbers);
45210 clobbers);
45212 }
45214 /* Implements target vector targetm.asm.encode_section_info. */
45216 static void ATTRIBUTE_UNUSED
45218 {
45223 }
45225 /* Worker function for REVERSE_CONDITION. */
45227 enum rtx_code
45229 {
45233 }
45235 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45236 to OPERANDS[0]. */
45240 {
45242 {
45245 {
45249 }
45253 }
45255 {
45259 else
45260 {
45261 /* There is no non-popping store to memory for XFmode.
45262 So if we need one, follow the store with a load. */
45265 else
45267 }
45268 }
45269 else
45271 }
45273 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45274 FP status register is set. */
45276 void
45278 {
45280 rtx temp;
45285 {
45290 }
45291 else
45292 {
45297 }
45301 pc_rtx);
45306 }
45308 /* Output code to perform a log1p XFmode calculation. */
45311 {
45317 rtx test;
45323 XFmode));
45337 }
45339 /* Emit code for round calculation. */
45341 {
45348 rtx insn;
45353 {
45365 }
45368 {
45389 }
45397 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
45399 /* scratch = fxam(op1) */
45402 UNSPEC_FXAM)));
45403 /* e1 = fabs(op1) */
45406 /* e2 = e1 + 0.5 */
45411 /* res = floor(e2) */
45413 {
45418 }
45419 else
45423 {
45426 {
45433 UNSPEC_TRUNC_NOOP)));
45434 }
45450 }
45452 /* flags = signbit(a) */
45455 /* if (flags) then res = -res */
45459 pc_rtx);
45470 }
45472 /* Output code to perform a Newton-Rhapson approximation of a single precision
45473 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
45476 {
45484 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
45488 /* x0 = rcp(b) estimate */
45492 UNSPEC_RCP14)));
45493 else
45496 UNSPEC_RCP)));
45498 /* e0 = x0 * b */
45502 /* e0 = x0 * e0 */
45506 /* e1 = x0 + x0 */
45510 /* x1 = e1 - e0 */
45514 /* res = a * x1 */
45517 }
45519 /* Output code to perform a Newton-Rhapson approximation of a
45520 single precision floating point [reciprocal] square root. */
45524 {
45526 REAL_VALUE_TYPE r;
45543 {
45546 /* There is no 512-bit rsqrt. There is however rsqrt14. */
45549 }
45551 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
45552 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
45556 /* x0 = rsqrt(a) estimate */
45559 unspec)));
45561 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
45563 {
45571 /* Handle masked compare. */
45573 {
45575 /* Imm value 0x4 corresponds to not-equal comparison. */
45578 }
45579 else
45580 {
45586 }
45587 }
45589 /* e0 = x0 * a */
45592 /* e1 = e0 * x0 */
45596 /* e2 = e1 - 3. */
45603 /* e3 = -.5 * x0 */
45606 else
45607 /* e3 = -.5 * e0 */
45610 /* ret = e2 * e3 */
45613 }
45615 #ifdef TARGET_SOLARIS
45616 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
45618 static void
45620 tree decl)
45621 {
45622 /* With Binutils 2.15, the "@unwind" marker must be specified on
45623 every occurrence of the ".eh_frame" section, not just the first
45624 one. */
45627 {
45631 }
45633 #ifndef USE_GAS
45635 {
45638 }
45639 #endif
45642 }
45645 /* Return the mangling of TYPE if it is an extended fundamental type. */
45649 {
45657 {
45659 /* __float128 is "g". */
45662 /* "long double" or __float80 is "e". */
45666 }
45667 }
45669 /* For 32-bit code we can save PIC register setup by using
45670 __stack_chk_fail_local hidden function instead of calling
45671 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
45672 register, so it is better to call __stack_chk_fail directly. */
45674 static tree ATTRIBUTE_UNUSED
45676 {
45677 return TARGET_64BIT
45680 }
45682 /* Select a format to encode pointers in exception handling data. CODE
45683 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
45684 true if the symbol may be affected by dynamic relocations.
45686 ??? All x86 object file formats are capable of representing this.
45687 After all, the relocation needed is the same as for the call insn.
45688 Whether or not a particular assembler allows us to enter such, I
45689 guess we'll have to see. */
45690 int
45692 {
45694 {
45701 }
45706 }
45707 \f
45708 /* Expand copysign from SIGN to the positive value ABS_VALUE
45709 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
45710 the sign-bit. */
45711 static void
45713 {
45717 {
45718 machine_mode vmode;
45724 else
45729 {
45730 /* We need to generate a scalar mode mask in this case. */
45735 }
45736 }
45737 else
45743 }
45745 /* Expand fabs (OP0) and return a new rtx that holds the result. The
45746 mask for masking out the sign-bit is stored in *SMASK, if that is
45747 non-null. */
45748 static rtx
45750 {
45759 else
45763 {
45764 /* We need to generate a scalar mode mask in this case. */
45769 }
45777 }
45779 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
45780 swapping the operands if SWAP_OPERANDS is true. The expanded
45781 code is a forward jump to a newly created label in case the
45782 comparison is true. The generated label rtx is returned. */
45786 {
45789 rtx tmp;
45805 }
45807 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
45808 using comparison code CODE. Operands are swapped for the comparison if
45809 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
45810 static rtx
45813 {
45826 }
45828 /* Generate and return a rtx of mode MODE for 2**n where n is the number
45829 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
45830 static rtx
45832 {
45833 REAL_VALUE_TYPE TWO52r;
45834 rtx TWO52;
45841 }
45843 /* Expand SSE sequence for computing lround from OP1 storing
45844 into OP0. */
45845 void
45847 {
45848 /* C code for the stuff we're doing below:
45849 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
45850 return (long)tmp;
45851 */
45855 rtx adj;
45857 /* load nextafter (0.5, 0.0) */
45862 /* adj = copysign (0.5, op1) */
45866 /* adj = op1 + adj */
45869 /* op0 = (imode)adj */
45871 }
45873 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
45874 into OPERAND0. */
45875 void
45877 {
45878 /* C code for the stuff we're doing below (for do_floor):
45879 xi = (long)op1;
45880 xi -= (double)xi > op1 ? 1 : 0;
45881 return xi;
45882 */
45888 /* reg = (long)op1 */
45892 /* freg = (double)reg */
45896 /* ireg = (freg > op1) ? ireg - 1 : ireg */
45907 }
45909 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
45910 result in OPERAND0. */
45911 void
45913 {
45914 /* C code for the stuff we're doing below:
45915 xa = fabs (operand1);
45916 if (!isless (xa, 2**52))
45917 return operand1;
45918 xa = xa + 2**52 - 2**52;
45919 return copysign (xa, operand1);
45920 */
45928 /* xa = abs (operand1) */
45931 /* if (!isless (xa, TWO52)) goto label; */
45944 }
45946 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
45947 into OPERAND0. */
45948 void
45950 {
45951 /* C code for the stuff we expand below.
45952 double xa = fabs (x), x2;
45953 if (!isless (xa, TWO52))
45954 return x;
45955 xa = xa + TWO52 - TWO52;
45956 x2 = copysign (xa, x);
45957 Compensate. Floor:
45958 if (x2 > x)
45959 x2 -= 1;
45960 Compensate. Ceil:
45961 if (x2 < x)
45962 x2 -= -1;
45963 return x2;
45964 */
45971 /* Temporary for holding the result, initialized to the input
45972 operand to ease control flow. */
45976 /* xa = abs (operand1) */
45979 /* if (!isless (xa, TWO52)) goto label; */
45982 /* xa = xa + TWO52 - TWO52; */
45986 /* xa = copysign (xa, operand1) */
45989 /* generate 1.0 or -1.0 */
45994 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
45998 /* We always need to subtract here to preserve signed zero. */
46007 }
46009 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46010 into OPERAND0. */
46011 void
46013 {
46014 /* C code for the stuff we expand below.
46015 double xa = fabs (x), x2;
46016 if (!isless (xa, TWO52))
46017 return x;
46018 x2 = (double)(long)x;
46019 Compensate. Floor:
46020 if (x2 > x)
46021 x2 -= 1;
46022 Compensate. Ceil:
46023 if (x2 < x)
46024 x2 += 1;
46025 if (HONOR_SIGNED_ZEROS (mode))
46026 return copysign (x2, x);
46027 return x2;
46028 */
46035 /* Temporary for holding the result, initialized to the input
46036 operand to ease control flow. */
46040 /* xa = abs (operand1) */
46043 /* if (!isless (xa, TWO52)) goto label; */
46046 /* xa = (double)(long)x */
46051 /* generate 1.0 */
46054 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46069 }
46071 /* Expand SSE sequence for computing round from OPERAND1 storing
46072 into OPERAND0. Sequence that works without relying on DImode truncation
46073 via cvttsd2siq that is only available on 64bit targets. */
46074 void
46076 {
46077 /* C code for the stuff we expand below.
46078 double xa = fabs (x), xa2, x2;
46079 if (!isless (xa, TWO52))
46080 return x;
46081 Using the absolute value and copying back sign makes
46082 -0.0 -> -0.0 correct.
46083 xa2 = xa + TWO52 - TWO52;
46084 Compensate.
46085 dxa = xa2 - xa;
46086 if (dxa <= -0.5)
46087 xa2 += 1;
46088 else if (dxa > 0.5)
46089 xa2 -= 1;
46090 x2 = copysign (xa2, x);
46091 return x2;
46092 */
46099 /* Temporary for holding the result, initialized to the input
46100 operand to ease control flow. */
46104 /* xa = abs (operand1) */
46107 /* if (!isless (xa, TWO52)) goto label; */
46110 /* xa2 = xa + TWO52 - TWO52; */
46114 /* dxa = xa2 - xa; */
46117 /* generate 0.5, 1.0 and -0.5 */
46123 /* Compensate. */
46125 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46130 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46136 /* res = copysign (xa2, operand1) */
46143 }
46145 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46146 into OPERAND0. */
46147 void
46149 {
46150 /* C code for SSE variant we expand below.
46151 double xa = fabs (x), x2;
46152 if (!isless (xa, TWO52))
46153 return x;
46154 x2 = (double)(long)x;
46155 if (HONOR_SIGNED_ZEROS (mode))
46156 return copysign (x2, x);
46157 return x2;
46158 */
46165 /* Temporary for holding the result, initialized to the input
46166 operand to ease control flow. */
46170 /* xa = abs (operand1) */
46173 /* if (!isless (xa, TWO52)) goto label; */
46176 /* x = (double)(long)x */
46188 }
46190 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46191 into OPERAND0. */
46192 void
46194 {
46199 /* C code for SSE variant we expand below.
46200 double xa = fabs (x), x2;
46201 if (!isless (xa, TWO52))
46202 return x;
46203 xa2 = xa + TWO52 - TWO52;
46204 Compensate:
46205 if (xa2 > xa)
46206 xa2 -= 1.0;
46207 x2 = copysign (xa2, x);
46208 return x2;
46209 */
46213 /* Temporary for holding the result, initialized to the input
46214 operand to ease control flow. */
46218 /* xa = abs (operand1) */
46221 /* if (!isless (xa, TWO52)) goto label; */
46224 /* res = xa + TWO52 - TWO52; */
46229 /* generate 1.0 */
46232 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46240 /* res = copysign (res, operand1) */
46247 }
46249 /* Expand SSE sequence for computing round from OPERAND1 storing
46250 into OPERAND0. */
46251 void
46253 {
46254 /* C code for the stuff we're doing below:
46255 double xa = fabs (x);
46256 if (!isless (xa, TWO52))
46257 return x;
46258 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46259 return copysign (xa, x);
46260 */
46267 /* Temporary for holding the result, initialized to the input
46268 operand to ease control flow. */
46276 /* load nextafter (0.5, 0.0) */
46281 /* xa = xa + 0.5 */
46285 /* xa = (double)(int64_t)xa */
46290 /* res = copysign (xa, operand1) */
46297 }
46299 /* Expand SSE sequence for computing round
46300 from OP1 storing into OP0 using sse4 round insn. */
46301 void
46303 {
46312 {
46323 }
46325 /* round (a) = trunc (a + copysign (0.5, a)) */
46327 /* load nextafter (0.5, 0.0) */
46333 /* e1 = copysign (0.5, op1) */
46337 /* e2 = op1 + e1 */
46340 /* res = trunc (e2) */
46345 }
46346 \f
46348 /* Table of valid machine attributes. */
46350 {
46351 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46352 affects_type_identity } */
46353 /* Stdcall attribute says callee is responsible for popping arguments
46354 if they are not variable. */
46357 /* Fastcall attribute says callee is responsible for popping arguments
46358 if they are not variable. */
46361 /* Thiscall attribute says callee is responsible for popping arguments
46362 if they are not variable. */
46365 /* Cdecl attribute says the callee is a normal C declaration */
46368 /* Regparm attribute specifies how many integer arguments are to be
46369 passed in registers. */
46372 /* Sseregparm attribute says we are using x86_64 calling conventions
46373 for FP arguments. */
46376 /* The transactional memory builtins are implicitly regparm or fastcall
46377 depending on the ABI. Override the generic do-nothing attribute that
46378 these builtins were declared with. */
46381 /* force_align_arg_pointer says this function realigns the stack at entry. */
46384 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46389 #endif
46394 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46395 SUBTARGET_ATTRIBUTE_TABLE,
46396 #endif
46397 /* ms_abi and sysv_abi calling convention function attributes. */
46404 /* End element. */
46406 };
46408 /* Implement targetm.vectorize.builtin_vectorization_cost. */
46409 static int
46412 {
46416 {
46461 }
46462 }
46464 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
46465 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
46466 insn every time. */
46470 /* Initialize vselect_insn. */
46472 static void
46474 {
46476 rtx x;
46487 }
46489 /* Construct (set target (vec_select op0 (parallel perm))) and
46490 return true if that's a valid instruction in the active ISA. */
46492 static bool
46495 {
46521 }
46523 /* Similar, but generate a vec_concat from op0 and op1 as well. */
46525 static bool
46529 {
46530 machine_mode v2mode;
46531 rtx x;
46546 }
46548 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46549 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
46551 static bool
46553 {
46563 ;
46565 ;
46567 ;
46569 ;
46570 else
46573 /* This is a blend, not a permute. Elements must stay in their
46574 respective lanes. */
46576 {
46580 }
46585 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
46586 decision should be extracted elsewhere, so that we only try that
46587 sequence once all budget==3 options have been tried. */
46594 {
46624 /* See if bytes move in pairs so we can use pblendw with
46625 an immediate argument, rather than pblendvb with a vector
46626 argument. */
46629 {
46630 use_pblendvb:
46634 finish_pblendvb:
46640 else
46645 }
46650 /* FALLTHRU */
46652 do_subreg:
46659 /* See if bytes move in pairs. If not, vpblendvb must be used. */
46663 /* See if bytes move in quadruplets. If yes, vpblendd
46664 with immediate can be used. */
46669 {
46670 /* See if bytes move the same in both lanes. If yes,
46671 vpblendw with immediate can be used. */
46676 /* Use vpblendw. */
46681 }
46683 /* Use vpblendd. */
46690 /* See if words move in pairs. If yes, vpblendd can be used. */
46695 {
46696 /* See if words move the same in both lanes. If not,
46697 vpblendvb must be used. */
46700 {
46701 /* Use vpblendvb. */
46711 }
46713 /* Use vpblendw. */
46717 }
46719 /* Use vpblendd. */
46726 /* Use vpblendd. */
46734 }
46736 /* This matches five different patterns with the different modes. */
46744 }
46746 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46747 in terms of the variable form of vpermilps.
46749 Note that we will have already failed the immediate input vpermilps,
46750 which requires that the high and low part shuffle be identical; the
46751 variable form doesn't require that. */
46753 static bool
46755 {
46762 /* We can only permute within the 128-bit lane. */
46764 {
46768 }
46774 {
46777 /* Within each 128-bit lane, the elements of op0 are numbered
46778 from 0 and the elements of op1 are numbered from 4. */
46785 }
46792 }
46794 /* Return true if permutation D can be performed as VMODE permutation
46795 instead. */
46797 static bool
46799 {
46814 else
46820 }
46822 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46823 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
46825 static bool
46827 {
46836 {
46838 {
46841 {
46845 /* Use vperm2i128 insn. The pattern uses
46846 V4DImode instead of V2TImode. */
46859 }
46861 }
46862 }
46863 else
46864 {
46866 {
46869 }
46871 {
46875 /* V4DImode should be already handled through
46876 expand_vselect by vpermq instruction. */
46883 {
46884 /* First see if vpermq can be used for
46885 V8SImode/V16HImode/V32QImode. */
46887 {
46895 {
46899 }
46901 }
46903 /* Next see if vpermd can be used. */
46906 }
46907 /* Or if vpermps can be used. */
46912 {
46913 /* vpshufb only works intra lanes, it is not
46914 possible to shuffle bytes in between the lanes. */
46918 }
46919 }
46921 {
46925 /* If vpermq didn't work, vpshufb won't work either. */
46933 {
46934 /* First see if vpermq can be used for
46935 V16SImode/V32HImode/V64QImode. */
46937 {
46945 {
46949 }
46951 }
46953 /* Next see if vpermd can be used. */
46956 }
46957 /* Or if vpermps can be used. */
46961 {
46962 /* vpshufb only works intra lanes, it is not
46963 possible to shuffle bytes in between the lanes. */
46967 }
46968 }
46969 else
46971 }
46982 else
46983 {
46991 else
46995 {
46999 }
47000 }
47011 {
47026 else
47028 }
47029 else
47030 {
47033 }
47038 }
47040 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47041 in a single instruction. */
47043 static bool
47045 {
47049 /* Check plain VEC_SELECT first, because AVX has instructions that could
47050 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47051 input where SEL+CONCAT may not. */
47053 {
47059 {
47065 }
47068 {
47072 }
47074 {
47075 /* Use vpbroadcast{b,w,d}. */
47078 {
47121 /* For other modes prefer other shuffles this function creates. */
47123 }
47125 {
47129 }
47130 }
47135 /* There are plenty of patterns in sse.md that are written for
47136 SEL+CONCAT and are not replicated for a single op. Perhaps
47137 that should be changed, to avoid the nastiness here. */
47139 /* Recognize interleave style patterns, which means incrementing
47140 every other permutation operand. */
47142 {
47145 }
47150 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47152 {
47154 {
47159 }
47164 }
47165 }
47167 /* Finally, try the fully general two operand permute. */
47172 /* Recognize interleave style patterns with reversed operands. */
47174 {
47176 {
47180 else
47183 }
47188 }
47190 /* Try the SSE4.1 blend variable merge instructions. */
47194 /* Try one of the AVX vpermil variable permutations. */
47198 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47199 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47203 /* Try the AVX2 vpalignr instruction. */
47207 /* Try the AVX512F vpermi2 instructions. */
47212 }
47214 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47215 in terms of a pair of pshuflw + pshufhw instructions. */
47217 static bool
47219 {
47227 /* The two permutations only operate in 64-bit lanes. */
47238 /* Emit the pshuflw. */
47245 /* Emit the pshufhw. */
47253 }
47255 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47256 the permutation using the SSSE3 palignr instruction. This succeeds
47257 when all of the elements in PERM fit within one vector and we merely
47258 need to shift them down so that a single vector permutation has a
47259 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47260 the vpalignr instruction itself can perform the requested permutation. */
47262 static bool
47264 {
47271 /* Even with AVX, palignr only operates on 128-bit vectors,
47272 in AVX2 palignr operates on both 128-bit lanes. */
47282 {
47286 {
47289 }
47298 }
47301 {
47310 }
47312 /* Given that we have SSSE3, we know we'll be able to implement the
47313 single operand permutation after the palignr with pshufb for
47314 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47315 first. */
47321 {
47326 }
47330 {
47336 else
47341 }
47347 /* For AVX2, test whether we can permute the result in one instruction. */
47349 {
47354 }
47358 {
47362 }
47363 else
47364 {
47369 shift));
47370 }
47374 /* Test for the degenerate case where the alignment by itself
47375 produces the desired permutation. */
47377 {
47380 }
47386 }
47388 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
47389 the permutation using the SSE4_1 pblendv instruction. Potentially
47390 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
47392 static bool
47394 {
47400 /* Use the same checks as in expand_vec_perm_blend. */
47404 ;
47406 ;
47408 ;
47409 else
47412 /* Figure out where permutation elements stay not in their
47413 respective lanes. */
47415 {
47419 }
47420 /* We can pblend the part where elements stay not in their
47421 respective lanes only when these elements are all in one
47422 half of a permutation.
47423 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
47424 lanes, but both 8 and 9 >= 8
47425 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
47426 respective lanes and 8 >= 8, but 2 not. */
47432 /* First we apply one operand permutation to the part where
47433 elements stay not in their respective lanes. */
47437 else
47447 else
47452 /* Next we put permuted elements into their positions. */
47456 else
47466 }
47470 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47471 a two vector permutation into a single vector permutation by using
47472 an interleave operation to merge the vectors. */
47474 static bool
47476 {
47485 {
47488 }
47490 {
47493 /* For 32-byte modes allow even d->one_operand_p.
47494 The lack of cross-lane shuffling in some instructions
47495 might prevent a single insn shuffle. */
47498 /* If expand_vec_perm_interleave3 can expand this into
47499 a 3 insn sequence, give up and let it be expanded as
47500 3 insn sequence. While that is one insn longer,
47501 it doesn't need a memory operand and in the common
47502 case that both interleave low and high permutations
47503 with the same operands are adjacent needs 4 insns
47504 for both after CSE. */
47507 }
47508 else
47511 /* Examine from whence the elements come. */
47520 {
47523 /* Split the two input vectors into 4 halves. */
47529 /* If the elements from the low halves use interleave low, and similarly
47530 for interleave high. If the elements are from mis-matched halves, we
47531 can use shufps for V4SF/V4SI or do a DImode shuffle. */
47533 {
47534 /* punpckl* */
47536 {
47541 }
47544 }
47546 {
47547 /* punpckh* */
47549 {
47554 }
47557 }
47559 {
47560 /* shufps */
47562 {
47567 }
47569 {
47570 /* shufpd */
47575 }
47576 }
47578 {
47579 /* shufps */
47581 {
47586 }
47588 {
47589 /* shufpd */
47594 }
47595 }
47596 else
47598 }
47599 else
47600 {
47605 /* Split the two input vectors into 8 quarters. */
47611 {
47614 }
47617 {
47621 }
47623 {
47626 }
47629 {
47631 {
47632 /* Attempt to increase the likelihood that dfinal
47633 shuffle will be intra-lane. */
47637 }
47639 /* vperm2f128 or vperm2i128. */
47641 {
47646 }
47651 {
47655 {
47658 }
47659 }
47660 }
47665 {
47666 /* vpunpckl* */
47668 {
47677 }
47678 }
47681 {
47682 /* vpunpckh* */
47684 {
47693 }
47694 }
47695 else
47697 }
47699 /* Use the remapping array set up above to move the elements from their
47700 swizzled locations into their final destinations. */
47703 {
47706 /* If same_halves is true, both halves of the remapped vector are the
47707 same. Avoid cross-lane accesses if possible. */
47709 {
47712 }
47713 else
47715 }
47717 {
47720 }
47724 /* Test if the final remap can be done with a single insn. For V4SFmode or
47725 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
47738 {
47741 }
47748 }
47750 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47751 a single vector cross-lane permutation into vpermq followed
47752 by any of the single insn permutations. */
47754 static bool
47756 {
47770 {
47773 }
47776 {
47781 }
47794 {
47801 }
47808 {
47813 ;
47816 else
47818 }
47827 }
47829 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
47830 a vector permutation using two instructions, vperm2f128 resp.
47831 vperm2i128 followed by any single in-lane permutation. */
47833 static bool
47835 {
47849 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
47850 immediate. For perm < 16 the second permutation uses
47851 d->op0 as first operand, for perm >= 16 it uses d->op1
47852 as first operand. The second operand is the result of
47853 vperm2[fi]128. */
47855 {
47856 /* Ignore permutations which do not move anything cross-lane. */
47858 {
47859 /* The second shuffle for e.g. V4DFmode has
47860 0123 and ABCD operands.
47861 Ignore AB23, as 23 is already in the second lane
47862 of the first operand. */
47864 /* And 01CD, as 01 is in the first lane of the first
47865 operand. */
47867 /* And 4567, as then the vperm2[fi]128 doesn't change
47868 anything on the original 4567 second operand. */
47870 }
47871 else
47872 {
47873 /* The second shuffle for e.g. V4DFmode has
47874 4567 and ABCD operands.
47875 Ignore AB67, as 67 is already in the second lane
47876 of the first operand. */
47878 /* And 45CD, as 45 is in the first lane of the first
47879 operand. */
47881 /* And 0123, as then the vperm2[fi]128 doesn't change
47882 anything on the original 0123 first operand. */
47884 }
47887 {
47893 else
47895 }
47898 {
47902 }
47903 else
47907 {
47911 /* Found a usable second shuffle. dfirst will be
47912 vperm2f128 on d->op0 and d->op1. */
47924 /* And dsecond is some single insn shuffle, taking
47925 d->op0 and result of vperm2f128 (if perm < 16) or
47926 d->op1 and result of vperm2f128 (otherwise). */
47935 }
47937 /* For one operand, the only useful vperm2f128 permutation is 0x01
47938 aka lanes swap. */
47941 }
47944 }
47946 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47947 a two vector permutation using 2 intra-lane interleave insns
47948 and cross-lane shuffle for 32-byte vectors. */
47950 static bool
47952 {
47959 ;
47961 ;
47962 else
47977 {
47981 else
47987 else
47993 else
47999 else
48005 else
48011 else
48016 }
48020 }
48022 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48023 a single vector permutation using a single intra-lane vector
48024 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48025 the non-swapped and swapped vectors together. */
48027 static bool
48029 {
48037 || TARGET_AVX2
48046 {
48053 }
48088 }
48090 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48091 permutation using two vperm2f128, followed by a vshufpd insn blending
48092 the two vectors together. */
48094 static bool
48096 {
48139 }
48141 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48142 permutation with two pshufb insns and an ior. We should have already
48143 failed all two instruction sequences. */
48145 static bool
48147 {
48161 /* Generate two permutation masks. If the required element is within
48162 the given vector it is shuffled into the proper lane. If the required
48163 element is in the other vector, force a zero into the lane by setting
48164 bit 7 in the permutation mask. */
48167 {
48174 {
48177 }
48178 }
48202 }
48204 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48205 with two vpshufb insns, vpermq and vpor. We should have already failed
48206 all two or three instruction sequences. */
48208 static bool
48210 {
48225 /* Generate two permutation masks. If the required element is within
48226 the same lane, it is shuffled in. If the required element from the
48227 other lane, force a zero by setting bit 7 in the permutation mask.
48228 In the other mask the mask has non-negative elements if element
48229 is requested from the other lane, but also moved to the other lane,
48230 so that the result of vpshufb can have the two V2TImode halves
48231 swapped. */
48234 {
48239 {
48242 }
48243 }
48252 /* Swap the 128-byte lanes of h into hp. */
48256 const1_rtx));
48273 }
48275 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48276 and extract-odd permutations of two V32QImode and V16QImode operand
48277 with two vpshufb insns, vpor and vpermq. We should have already
48278 failed all two or three instruction sequences. */
48280 static bool
48282 {
48301 /* Generate two permutation masks. In the first permutation mask
48302 the first quarter will contain indexes for the first half
48303 of the op0, the second quarter will contain bit 7 set, third quarter
48304 will contain indexes for the second half of the op0 and the
48305 last quarter bit 7 set. In the second permutation mask
48306 the first quarter will contain bit 7 set, the second quarter
48307 indexes for the first half of the op1, the third quarter bit 7 set
48308 and last quarter indexes for the second half of the op1.
48309 I.e. the first mask e.g. for V32QImode extract even will be:
48310 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48311 (all values masked with 0xf except for -128) and second mask
48312 for extract even will be
48313 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48316 {
48322 {
48325 }
48326 }
48345 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48353 }
48355 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48356 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
48357 with two "and" and "pack" or two "shift" and "pack" insns. We should
48358 have already failed all two instruction sequences. */
48360 static bool
48362 {
48366 machine_mode half_mode;
48375 {
48377 /* Required for "pack". */
48388 /* No check as all instructions are SSE2. */
48419 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
48420 general shuffles. */
48422 }
48424 /* Check that permutation is even or odd. */
48439 {
48446 }
48447 else
48448 {
48455 }
48456 /* In AVX2 for 256 bit case we need to permute pack result. */
48458 {
48464 const0_rtx,
48465 const2_rtx,
48466 const1_rtx,
48469 }
48470 else
48474 }
48476 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
48477 and extract-odd permutations. */
48479 static bool
48481 {
48485 {
48492 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48496 /* Now an unpck[lh]pd will produce the result required. */
48499 else
48505 {
48514 /* Shuffle within the 128-bit lanes to produce:
48515 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
48519 /* Shuffle the lanes around to produce:
48520 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
48524 /* Shuffle within the 128-bit lanes to produce:
48525 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
48528 /* Shuffle within the 128-bit lanes to produce:
48529 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
48532 /* Shuffle the lanes around to produce:
48533 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
48536 }
48543 /* These are always directly implementable by expand_vec_perm_1. */
48551 else
48552 {
48555 /* We need 2*log2(N)-1 operations to achieve odd/even
48556 with interleave. */
48565 else
48568 }
48580 {
48585 else
48590 {
48595 }
48597 }
48605 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48609 /* Now an vpunpck[lh]qdq will produce the result required. */
48612 else
48619 {
48624 else
48629 {
48634 }
48636 }
48647 /* Shuffle the lanes around into
48648 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
48656 /* Swap the 2nd and 3rd position in each lane into
48657 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
48663 /* Now an vpunpck[lh]qdq will produce
48664 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
48668 else
48677 }
48680 }
48682 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48683 extract-even and extract-odd permutations. */
48685 static bool
48687 {
48699 }
48701 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
48702 permutations. We assume that expand_vec_perm_1 has already failed. */
48704 static bool
48706 {
48714 {
48717 /* These are special-cased in sse.md so that we can optionally
48718 use the vbroadcast instruction. They expand to two insns
48719 if the input happens to be in a register. */
48726 /* These are always implementable using standard shuffle patterns. */
48731 /* These can be implemented via interleave. We save one insn by
48732 stopping once we have promoted to V4SImode and then use pshufd. */
48735 do
48736 {
48737 rtx dest;
48743 {
48747 }
48754 }
48769 /* For AVX2 broadcasts of the first element vpbroadcast* or
48770 vpermq should be used by expand_vec_perm_1. */
48776 }
48777 }
48779 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48780 broadcast permutations. */
48782 static bool
48784 {
48796 }
48798 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
48799 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
48800 all the shorter instruction sequences. */
48802 static bool
48804 {
48820 /* Generate 4 permutation masks. If the required element is within
48821 the same lane, it is shuffled in. If the required element from the
48822 other lane, force a zero by setting bit 7 in the permutation mask.
48823 In the other mask the mask has non-negative elements if element
48824 is requested from the other lane, but also moved to the other lane,
48825 so that the result of vpshufb can have the two V2TImode halves
48826 swapped. */
48829 {
48834 }
48840 {
48848 }
48851 {
48853 {
48856 }
48863 }
48865 /* Swap the 128-byte lanes of h[X]. */
48867 {
48873 const1_rtx));
48875 }
48878 {
48880 {
48883 }
48889 }
48892 {
48894 {
48898 }
48901 }
48911 }
48913 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
48914 With all of the interface bits taken care of, perform the expansion
48915 in D and return true on success. */
48917 static bool
48919 {
48920 /* Try a single instruction expansion. */
48924 /* Try sequences of two instructions. */
48947 /* Try sequences of three instructions. */
48964 /* Try sequences of four instructions. */
48972 /* ??? Look for narrow permutations whose element orderings would
48973 allow the promotion to a wider mode. */
48975 /* ??? Look for sequences of interleave or a wider permute that place
48976 the data into the correct lanes for a half-vector shuffle like
48977 pshuf[lh]w or vpermilps. */
48979 /* ??? Look for sequences of interleave that produce the desired results.
48980 The combinatorics of punpck[lh] get pretty ugly... */
48985 /* Even longer sequences. */
48990 }
48992 /* If a permutation only uses one operand, make it clear. Returns true
48993 if the permutation references both operands. */
48995 static bool
48997 {
49005 {
49011 {
49014 }
49015 /* The elements of PERM do not suggest that only the first operand
49016 is used, but both operands are identical. Allow easier matching
49017 of the permutation by folding the permutation into the single
49018 input vector. */
49019 /* FALLTHRU */
49030 }
49033 }
49035 bool
49037 {
49042 rtx sel;
49059 {
49064 }
49071 /* If the selector says both arguments are needed, but the operands are the
49072 same, the above tried to expand with one_operand_p and flattened selector.
49073 If that didn't work, retry without one_operand_p; we succeeded with that
49074 during testing. */
49076 {
49080 }
49083 }
49085 /* Implement targetm.vectorize.vec_perm_const_ok. */
49087 static bool
49090 {
49099 /* Given sufficient ISA support we can just return true here
49100 for selected vector modes. */
49102 {
49108 /* All implementable with a single vpermi2 insn. */
49113 /* All implementable with a single vpermi2 insn. */
49121 /* All implementable with a single vpermi2 insn. */
49126 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49131 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49138 /* All implementable with a single vpperm insn. */
49141 /* All implementable with 2 pshufb + 1 ior. */
49147 /* All implementable with shufpd or unpck[lh]pd. */
49151 }
49153 /* Extract the values from the vector CST into the permutation
49154 array in D. */
49157 {
49161 }
49163 /* For all elements from second vector, fold the elements to first. */
49168 /* Check whether the mask can be applied to the vector type. */
49171 /* Implementable with shufps or pshufd. */
49175 /* Otherwise we have to go through the motions and see if we can
49176 figure out how to generate the requested permutation. */
49187 }
49189 void
49191 {
49206 /* We'll either be able to implement the permutation directly... */
49210 /* ... or we use the special-case patterns. */
49212 }
49214 static void
49216 {
49231 {
49234 }
49236 /* Note that for AVX this isn't one instruction. */
49239 }
49242 /* Expand a vector operation CODE for a V*QImode in terms of the
49243 same operation on V*HImode. */
49245 void
49247 {
49249 machine_mode himode;
49259 {
49277 }
49281 {
49283 /* Unpack data such that we've got a source byte in each low byte of
49284 each word. We don't care what goes into the high byte of each word.
49285 Rather than trying to get zero in there, most convenient is to let
49286 it be a copy of the low byte. */
49291 /* FALLTHRU */
49303 /* FALLTHRU */
49313 }
49315 /* Perform the operation. */
49322 /* Merge the data back into the right place. */
49332 {
49333 /* For SSE2, we used an full interleave, so the desired
49334 results are in the even elements. */
49337 }
49338 else
49339 {
49340 /* For AVX, the interleave used above was not cross-lane. So the
49341 extraction is evens but with the second and third quarter swapped.
49342 Happily, that is even one insn shorter than even extraction. */
49345 }
49352 }
49354 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
49355 if op is CONST_VECTOR with all odd elements equal to their
49356 preceding element. */
49358 static bool
49360 {
49370 }
49372 void
49375 {
49378 rtx x;
49386 /* We only play even/odd games with vectors of SImode. */
49389 /* If we're looking for the odd results, shift those members down to
49390 the even slots. For some cpus this is faster than a PSHUFD. */
49392 {
49393 /* For XOP use vpmacsdqh, but only for smult, as it is only
49394 signed. */
49396 {
49400 }
49411 }
49414 {
49417 else
49419 }
49421 {
49424 else
49426 }
49431 else
49432 {
49435 /* The easiest way to implement this without PMULDQ is to go through
49436 the motions as if we are performing a full 64-bit multiply. With
49437 the exception that we need to do less shuffling of the elements. */
49439 /* Compute the sign-extension, aka highparts, of the two operands. */
49445 /* Multiply LO(A) * HI(B), and vice-versa. */
49451 /* Multiply LO(A) * LO(B). */
49455 /* Combine and shift the highparts into place. */
49460 /* Combine high and low parts. */
49463 }
49465 }
49467 void
49470 {
49476 {
49481 {
49482 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
49483 shuffle the elements once so that all elements are in the right
49484 place for immediate use: { A C B D }. */
49489 }
49490 else
49491 {
49492 /* Put the elements into place for the multiply. */
49496 }
49501 /* Shuffle the elements between the lanes. After this we
49502 have { A B E F | C D G H } for each operand. */
49512 /* Shuffle the elements within the lanes. After this we
49513 have { A A B B | C C D D } or { E E F F | G G H H }. */
49554 }
49555 }
49557 void
49559 {
49569 /* Move the results in element 2 down to element 1; we don't care
49570 what goes in elements 2 and 3. Then we can merge the parts
49571 back together with an interleave.
49573 Note that two other sequences were tried:
49574 (1) Use interleaves at the start instead of psrldq, which allows
49575 us to use a single shufps to merge things back at the end.
49576 (2) Use shufps here to combine the two vectors, then pshufd to
49577 put the elements in the correct order.
49578 In both cases the cost of the reformatting stall was too high
49579 and the overall sequence slower. */
49590 }
49592 void
49594 {
49605 {
49606 /* op1: A,B,C,D, op2: E,F,G,H */
49615 /* t1: B,A,D,C */
49622 /* t2: (B*E),(A*F),(D*G),(C*H) */
49625 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
49628 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
49631 /* Multiply lower parts and add all */
49638 }
49639 else
49640 {
49641 machine_mode nmode;
49645 {
49648 }
49650 {
49653 }
49655 {
49658 }
49659 else
49663 /* Multiply low parts. */
49667 /* Shift input vectors right 32 bits so we can multiply high parts. */
49672 /* Multiply high parts by low parts. */
49678 /* Combine and shift the highparts back. */
49682 /* Combine high and low parts. */
49684 }
49688 }
49690 /* Return 1 if control tansfer instruction INSN
49691 should be encoded with bnd prefix.
49692 If insn is NULL then return 1 when control
49693 transfer instructions should be prefixed with
49694 bnd by default for current function. */
49696 bool
49698 {
49699 /* For call insns check special flag. */
49701 {
49705 }
49707 /* All other insns are prefixed only if function is instrumented. */
49709 }
49711 /* Calculate integer abs() using only SSE2 instructions. */
49713 void
49715 {
49720 {
49721 /* For 32-bit signed integer X, the best way to calculate the absolute
49722 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
49734 /* For 16-bit signed integer X, the best way to calculate the absolute
49735 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
49743 /* For 8-bit signed integer X, the best way to calculate the absolute
49744 value of X is min ((unsigned char) X, (unsigned char) (-X)),
49745 as SSE2 provides the PMINUB insn. */
49755 }
49759 }
49761 /* Expand an insert into a vector register through pinsr insn.
49762 Return true if successful. */
49764 bool
49766 {
49774 {
49777 }
49783 {
49788 {
49795 {
49827 }
49841 }
49845 }
49846 }
49847 \f
49848 /* This function returns the calling abi specific va_list type node.
49849 It returns the FNDECL specific va_list type. */
49851 static tree
49853 {
49860 else
49862 }
49864 /* Returns the canonical va_list type specified by TYPE. If there
49865 is no valid TYPE provided, it return NULL_TREE. */
49867 static tree
49869 {
49872 /* Resolve references and pointers to va_list type. */
49881 {
49886 {
49887 /* If va_list is an array type, the argument may have decayed
49888 to a pointer type, e.g. by being passed to another function.
49889 In that case, unwrap both types so that we can compare the
49890 underlying records. */
49893 {
49896 }
49897 }
49904 {
49905 /* If va_list is an array type, the argument may have decayed
49906 to a pointer type, e.g. by being passed to another function.
49907 In that case, unwrap both types so that we can compare the
49908 underlying records. */
49911 {
49914 }
49915 }
49922 {
49923 /* If va_list is an array type, the argument may have decayed
49924 to a pointer type, e.g. by being passed to another function.
49925 In that case, unwrap both types so that we can compare the
49926 underlying records. */
49929 {
49932 }
49933 }
49937 }
49939 }
49941 /* Iterate through the target-specific builtin types for va_list.
49942 IDX denotes the iterator, *PTREE is set to the result type of
49943 the va_list builtin, and *PNAME to its internal type.
49944 Returns zero if there is no element for this index, otherwise
49945 IDX should be increased upon the next call.
49946 Note, do not iterate a base builtin's name like __builtin_va_list.
49947 Used from c_common_nodes_and_builtins. */
49949 static int
49951 {
49953 {
49955 {
49968 }
49969 }
49972 }
49974 #undef TARGET_SCHED_DISPATCH
49975 #define TARGET_SCHED_DISPATCH has_dispatch
49976 #undef TARGET_SCHED_DISPATCH_DO
49977 #define TARGET_SCHED_DISPATCH_DO do_dispatch
49978 #undef TARGET_SCHED_REASSOCIATION_WIDTH
49979 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
49980 #undef TARGET_SCHED_REORDER
49981 #define TARGET_SCHED_REORDER ix86_sched_reorder
49982 #undef TARGET_SCHED_ADJUST_PRIORITY
49983 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
49984 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
49985 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
49986 ix86_dependencies_evaluation_hook
49988 /* The size of the dispatch window is the total number of bytes of
49989 object code allowed in a window. */
49990 #define DISPATCH_WINDOW_SIZE 16
49992 /* Number of dispatch windows considered for scheduling. */
49993 #define MAX_DISPATCH_WINDOWS 3
49995 /* Maximum number of instructions in a window. */
49996 #define MAX_INSN 4
49998 /* Maximum number of immediate operands in a window. */
49999 #define MAX_IMM 4
50001 /* Maximum number of immediate bits allowed in a window. */
50002 #define MAX_IMM_SIZE 128
50004 /* Maximum number of 32 bit immediates allowed in a window. */
50005 #define MAX_IMM_32 4
50007 /* Maximum number of 64 bit immediates allowed in a window. */
50008 #define MAX_IMM_64 2
50010 /* Maximum total of loads or prefetches allowed in a window. */
50011 #define MAX_LOAD 2
50013 /* Maximum total of stores allowed in a window. */
50014 #define MAX_STORE 1
50016 #undef BIG
50017 #define BIG 100
50020 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50023 disp_load,
50024 disp_store,
50025 disp_load_store,
50026 disp_prefetch,
50027 disp_imm,
50028 disp_imm_32,
50029 disp_imm_64,
50030 disp_branch,
50031 disp_cmp,
50032 disp_jcc,
50033 disp_last
50034 };
50036 /* Number of allowable groups in a dispatch window. It is an array
50037 indexed by dispatch_group enum. 100 is used as a big number,
50038 because the number of these kind of operations does not have any
50039 effect in dispatch window, but we need them for other reasons in
50040 the table. */
50043 };
50049 };
50051 /* Instruction path. */
50057 last_path
50058 };
50060 /* sched_insn_info defines a window to the instructions scheduled in
50061 the basic block. It contains a pointer to the insn_info table and
50062 the instruction scheduled.
50064 Windows are allocated for each basic block and are linked
50065 together. */
50067 rtx insn;
50074 /* Linked list of dispatch windows. This is a two way list of
50075 dispatch windows of a basic block. It contains information about
50076 the number of uops in the window and the total number of
50077 instructions and of bytes in the object code for this dispatch
50078 window. */
50096 /* Immediate valuse used in an insn. */
50098 {
50107 /* Get dispatch group of insn. */
50109 static enum dispatch_group
50111 {
50127 }
50129 /* Return true if insn is a compare instruction. */
50131 static bool
50133 {
50141 }
50143 /* Return true if a dispatch violation encountered. */
50145 static bool
50147 {
50151 }
50153 /* Return true if insn is a branch instruction. */
50155 static bool
50157 {
50159 }
50161 /* Return true if insn is a prefetch instruction. */
50163 static bool
50165 {
50167 }
50169 /* This function initializes a dispatch window and the list container holding a
50170 pointer to the window. */
50172 static void
50174 {
50180 else
50198 {
50204 }
50206 }
50208 /* This function allocates and initializes a dispatch window and the
50209 list container holding a pointer to the window. */
50213 {
50218 }
50220 /* This routine initializes the dispatch scheduling information. It
50221 initiates building dispatch scheduler tables and constructs the
50222 first dispatch window. */
50224 static void
50226 {
50227 /* Allocate a dispatch list and a window. */
50232 }
50234 /* This function returns true if a branch is detected. End of a basic block
50235 does not have to be a branch, but here we assume only branches end a
50236 window. */
50238 static bool
50240 {
50242 }
50244 /* This function is called when the end of a window processing is reached. */
50246 static void
50248 {
50251 {
50256 }
50258 }
50260 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50261 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50262 for 48 bytes of instructions. Note that these windows are not dispatch
50263 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50267 {
50269 {
50274 }
50280 }
50282 /* Compute number of immediate operands of an instruction. */
50284 static void
50286 {
50293 {
50300 else
50311 {
50314 }
50319 }
50320 }
50322 /* Return total size of immediate operands of an instruction along with number
50323 of corresponding immediate-operands. It initializes its parameters to zero
50324 befor calling FIND_CONSTANT.
50325 INSN is the input instruction. IMM is the total of immediates.
50326 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
50327 bit immediates. */
50329 static int
50331 {
50339 }
50341 /* This function indicates if an operand of an instruction is an
50342 immediate. */
50344 static bool
50346 {
50355 }
50357 /* Return single or double path for instructions. */
50359 static enum insn_path
50361 {
50371 }
50373 /* Return insn dispatch group. */
50375 static enum dispatch_group
50377 {
50395 }
50397 /* Count number of GROUP restricted instructions in a dispatch
50398 window WINDOW_LIST. */
50400 static int
50402 {
50413 {
50432 }
50445 }
50447 /* This function returns true if insn satisfies dispatch rules on the
50448 last window scheduled. */
50450 static bool
50452 {
50460 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
50461 instructions should be given the lowest priority in the
50462 scheduling process in Haifa scheduler to make sure they will be
50463 scheduled in the same dispatch window as the reference to them. */
50467 /* Check nonrestricted. */
50471 /* Get last dispatch window. */
50476 {
50481 /* Window 1 is full. Go for next window. */
50483 }
50490 /* See if it fits in the first window. */
50492 {
50493 /* The first widow should have only single and double path
50494 uops. */
50500 }
50502 }
50504 /* Add an instruction INSN with NUM_UOPS micro-operations to the
50505 dispatch window WINDOW_LIST. */
50507 static void
50509 {
50527 /* Initialize window with new instruction. */
50548 {
50551 }
50552 }
50554 /* Adds a scheduled instruction, INSN, to the current dispatch window.
50555 If the total bytes of instructions or the number of instructions in
50556 the window exceed allowable, it allocates a new window. */
50558 static void
50560 {
50583 /* Get the last dispatch window. */
50591 else
50594 /* If current window is full, get a new window.
50595 Window number zero is full, if MAX_INSN uops are scheduled in it.
50596 Window number one is full, if window zero's bytes plus window
50597 one's bytes is 32, or if the bytes of the new instruction added
50598 to the total makes it greater than 48, or it has already MAX_INSN
50599 instructions in it. */
50608 {
50611 }
50614 {
50618 {
50621 }
50622 }
50624 {
50629 {
50632 }
50635 }
50636 else
50640 {
50641 /* End of basic block is reached do end-basic-block process. */
50644 }
50645 }
50647 /* Print the dispatch window, WINDOW_NUM, to FILE. */
50649 DEBUG_FUNCTION static void
50651 {
50657 else
50671 {
50674 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
50680 }
50681 }
50683 /* Print to stdout a dispatch window. */
50685 DEBUG_FUNCTION void
50687 {
50689 }
50691 /* Print INSN dispatch information to FILE. */
50693 DEBUG_FUNCTION static void
50695 {
50718 }
50720 /* Print to STDERR the status of the ready list with respect to
50721 dispatch windows. */
50723 DEBUG_FUNCTION void
50725 {
50733 }
50735 /* This routine is the driver of the dispatch scheduler. */
50737 static void
50739 {
50744 }
50746 /* Return TRUE if Dispatch Scheduling is supported. */
50748 static bool
50750 {
50754 {
50770 }
50773 }
50775 /* Implementation of reassociation_width target hook used by
50776 reassoc phase to identify parallelism level in reassociated
50777 tree. Statements tree_code is passed in OPC. Arguments type
50778 is passed in MODE.
50780 Currently parallel reassociation is enabled for Atom
50781 processors only and we set reassociation width to be 2
50782 because Atom may issue up to 2 instructions per cycle.
50784 Return value should be fixed if parallel reassociation is
50785 enabled for other processors. */
50787 static int
50789 {
50792 /* Vector part. */
50794 {
50797 else
50799 }
50801 /* Scalar part. */
50808 }
50810 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
50811 place emms and femms instructions. */
50813 static machine_mode
50815 {
50820 {
50839 else
50851 /* FALLTHRU */
50855 }
50856 }
50858 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
50859 vectors. If AVX512F is enabled then try vectorizing with 512bit,
50860 256bit and 128bit vectors. */
50862 static unsigned int
50864 {
50867 }
50869 \f
50871 /* Return class of registers which could be used for pseudo of MODE
50872 and of class RCLASS for spilling instead of memory. Return NO_REGS
50873 if it is not possible or non-profitable. */
50874 static reg_class_t
50876 {
50882 }
50884 /* Implement targetm.vectorize.init_cost. */
50888 {
50892 }
50894 /* Implement targetm.vectorize.add_stmt_cost. */
50896 static unsigned
50900 {
50907 /* Statements in an inner loop relative to the loop being
50908 vectorized are weighted more heavily. The value here is
50909 arbitrary and could potentially be improved with analysis. */
50915 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
50916 for Silvermont as it has out of order integer pipeline and can execute
50917 2 scalar instruction per tick, but has in order SIMD pipeline. */
50920 {
50924 }
50929 }
50931 /* Implement targetm.vectorize.finish_cost. */
50933 static void
50936 {
50941 }
50943 /* Implement targetm.vectorize.destroy_cost_data. */
50945 static void
50947 {
50949 }
50951 /* Validate target specific memory model bits in VAL. */
50953 static unsigned HOST_WIDE_INT
50955 {
50962 {
50966 }
50969 {
50973 }
50975 {
50979 }
50981 }
50983 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
50984 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
50985 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
50986 or number of vecsize_mangle variants that should be emitted. */
50988 static int
50992 {
50999 {
51003 }
51008 {
51015 /* case SCmode: */
51016 /* case DCmode: */
51022 }
51024 tree t;
51028 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51030 {
51037 /* case SCmode: */
51038 /* case DCmode: */
51044 }
51047 {
51048 /* Parse here processor clause. If not present, default to 'b'. */
51050 }
51052 {
51053 /* If the function isn't exported, we can pick up just one ISA
51054 for the clones. */
51059 else
51062 }
51063 else
51064 {
51067 }
51069 {
51082 }
51084 {
51087 else
51092 }
51094 }
51096 /* Add target attribute to SIMD clone NODE if needed. */
51098 static void
51100 {
51104 {
51119 }
51129 }
51131 /* If SIMD clone NODE can't be used in a vectorized loop
51132 in current function, return -1, otherwise return a badness of using it
51133 (0 if it is most desirable from vecsize_mangle point of view, 1
51134 slightly less desirable, etc.). */
51136 static int
51138 {
51140 {
51158 }
51159 }
51161 /* This function adjusts the unroll factor based on
51162 the hardware capabilities. For ex, bdver3 has
51163 a loop buffer which makes unrolling of smaller
51164 loops less important. This function decides the
51165 unroll factor using number of memory references
51166 (value 32 is used) as a heuristic. */
51168 static unsigned
51170 {
51179 /* Count the number of memory references within the loop body.
51180 This value determines the unrolling factor for bdver3 and bdver4
51181 architectures. */
51190 {
51195 else
51197 }
51204 }
51207 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51209 static bool
51211 {
51212 /* For x87 floating point with standard excess precision handling,
51213 there is no adddf3 pattern (since x87 floating point only has
51214 XFmode operations) so the default hook implementation gets this
51215 wrong. */
51217 }
51219 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51221 static void
51223 {
51228 {
51243 hold_fnclex);
51256 }
51258 {
51267 mxcsr_orig_var,
51277 ldmxcsr_hold_call);
51280 else
51285 ldmxcsr_clear_call);
51286 else
51290 stxmcsr_update_call);
51292 {
51298 exceptions_assign);
51299 }
51300 else
51305 ldmxcsr_update_call);
51306 }
51307 tree atomic_feraiseexcept
51312 atomic_feraiseexcept_call);
51313 }
51315 /* Return mode to be used for bounds or VOIDmode
51316 if bounds are not supported. */
51318 static enum machine_mode
51320 {
51321 /* Do not support pointer checker if MPX
51322 is not enabled. */
51324 {
51329 }
51332 }
51334 /* Return constant used to statically initialize constant bounds.
51336 This function is used to create special bound values. For now
51337 only INIT bounds and NONE bounds are expected. More special
51338 values may be added later. */
51340 static tree
51342 {
51348 /* This function is supposed to be used to create INIT and
51349 NONE bounds only. */
51354 }
51356 /* Generate a list of statements STMTS to initialize pointer bounds
51357 variable VAR with bounds LB and UB. Return the number of generated
51358 statements. */
51360 static int
51362 {
51380 }
51382 /* Initialize the GCC target structure. */
51383 #undef TARGET_RETURN_IN_MEMORY
51384 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
51386 #undef TARGET_LEGITIMIZE_ADDRESS
51387 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
51389 #undef TARGET_ATTRIBUTE_TABLE
51390 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
51391 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
51392 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
51393 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51394 # undef TARGET_MERGE_DECL_ATTRIBUTES
51395 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
51396 #endif
51398 #undef TARGET_COMP_TYPE_ATTRIBUTES
51399 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
51401 #undef TARGET_INIT_BUILTINS
51402 #define TARGET_INIT_BUILTINS ix86_init_builtins
51403 #undef TARGET_BUILTIN_DECL
51404 #define TARGET_BUILTIN_DECL ix86_builtin_decl
51405 #undef TARGET_EXPAND_BUILTIN
51406 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
51408 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
51409 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
51410 ix86_builtin_vectorized_function
51412 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
51413 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
51415 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
51416 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
51418 #undef TARGET_VECTORIZE_BUILTIN_GATHER
51419 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
51421 #undef TARGET_BUILTIN_RECIPROCAL
51422 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
51424 #undef TARGET_ASM_FUNCTION_EPILOGUE
51425 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
51427 #undef TARGET_ENCODE_SECTION_INFO
51428 #ifndef SUBTARGET_ENCODE_SECTION_INFO
51429 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
51430 #else
51431 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
51432 #endif
51434 #undef TARGET_ASM_OPEN_PAREN
51436 #undef TARGET_ASM_CLOSE_PAREN
51439 #undef TARGET_ASM_BYTE_OP
51440 #define TARGET_ASM_BYTE_OP ASM_BYTE
51442 #undef TARGET_ASM_ALIGNED_HI_OP
51443 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
51444 #undef TARGET_ASM_ALIGNED_SI_OP
51445 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
51446 #ifdef ASM_QUAD
51447 #undef TARGET_ASM_ALIGNED_DI_OP
51448 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
51449 #endif
51451 #undef TARGET_PROFILE_BEFORE_PROLOGUE
51452 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
51454 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
51455 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
51457 #undef TARGET_ASM_UNALIGNED_HI_OP
51458 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
51459 #undef TARGET_ASM_UNALIGNED_SI_OP
51460 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
51461 #undef TARGET_ASM_UNALIGNED_DI_OP
51462 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
51464 #undef TARGET_PRINT_OPERAND
51465 #define TARGET_PRINT_OPERAND ix86_print_operand
51466 #undef TARGET_PRINT_OPERAND_ADDRESS
51467 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
51468 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
51469 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
51470 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
51471 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
51473 #undef TARGET_SCHED_INIT_GLOBAL
51474 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
51475 #undef TARGET_SCHED_ADJUST_COST
51476 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
51477 #undef TARGET_SCHED_ISSUE_RATE
51478 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
51479 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
51480 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
51481 ia32_multipass_dfa_lookahead
51482 #undef TARGET_SCHED_MACRO_FUSION_P
51483 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
51484 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
51485 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
51487 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
51488 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
51490 #undef TARGET_MEMMODEL_CHECK
51491 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
51493 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
51494 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
51496 #ifdef HAVE_AS_TLS
51497 #undef TARGET_HAVE_TLS
51498 #define TARGET_HAVE_TLS true
51499 #endif
51500 #undef TARGET_CANNOT_FORCE_CONST_MEM
51501 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
51502 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
51503 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
51505 #undef TARGET_DELEGITIMIZE_ADDRESS
51506 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
51508 #undef TARGET_MS_BITFIELD_LAYOUT_P
51509 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
51511 #if TARGET_MACHO
51512 #undef TARGET_BINDS_LOCAL_P
51513 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
51514 #endif
51515 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51516 #undef TARGET_BINDS_LOCAL_P
51517 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
51518 #endif
51520 #undef TARGET_ASM_OUTPUT_MI_THUNK
51521 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
51522 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
51523 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
51525 #undef TARGET_ASM_FILE_START
51526 #define TARGET_ASM_FILE_START x86_file_start
51528 #undef TARGET_OPTION_OVERRIDE
51529 #define TARGET_OPTION_OVERRIDE ix86_option_override
51531 #undef TARGET_REGISTER_MOVE_COST
51532 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
51533 #undef TARGET_MEMORY_MOVE_COST
51534 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
51535 #undef TARGET_RTX_COSTS
51536 #define TARGET_RTX_COSTS ix86_rtx_costs
51537 #undef TARGET_ADDRESS_COST
51538 #define TARGET_ADDRESS_COST ix86_address_cost
51540 #undef TARGET_FIXED_CONDITION_CODE_REGS
51541 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
51542 #undef TARGET_CC_MODES_COMPATIBLE
51543 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
51545 #undef TARGET_MACHINE_DEPENDENT_REORG
51546 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
51548 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
51549 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
51551 #undef TARGET_BUILD_BUILTIN_VA_LIST
51552 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
51554 #undef TARGET_FOLD_BUILTIN
51555 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
51557 #undef TARGET_COMPARE_VERSION_PRIORITY
51558 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
51560 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
51561 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
51562 ix86_generate_version_dispatcher_body
51564 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
51565 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
51566 ix86_get_function_versions_dispatcher
51568 #undef TARGET_ENUM_VA_LIST_P
51569 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
51571 #undef TARGET_FN_ABI_VA_LIST
51572 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
51574 #undef TARGET_CANONICAL_VA_LIST_TYPE
51575 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
51577 #undef TARGET_EXPAND_BUILTIN_VA_START
51578 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
51580 #undef TARGET_MD_ASM_CLOBBERS
51581 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
51583 #undef TARGET_PROMOTE_PROTOTYPES
51584 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
51585 #undef TARGET_SETUP_INCOMING_VARARGS
51586 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
51587 #undef TARGET_MUST_PASS_IN_STACK
51588 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
51589 #undef TARGET_FUNCTION_ARG_ADVANCE
51590 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
51591 #undef TARGET_FUNCTION_ARG
51592 #define TARGET_FUNCTION_ARG ix86_function_arg
51593 #undef TARGET_INIT_PIC_REG
51594 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
51595 #undef TARGET_USE_PSEUDO_PIC_REG
51596 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
51597 #undef TARGET_FUNCTION_ARG_BOUNDARY
51598 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
51599 #undef TARGET_PASS_BY_REFERENCE
51600 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
51601 #undef TARGET_INTERNAL_ARG_POINTER
51602 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
51603 #undef TARGET_UPDATE_STACK_BOUNDARY
51604 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
51605 #undef TARGET_GET_DRAP_RTX
51606 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
51607 #undef TARGET_STRICT_ARGUMENT_NAMING
51608 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
51609 #undef TARGET_STATIC_CHAIN
51610 #define TARGET_STATIC_CHAIN ix86_static_chain
51611 #undef TARGET_TRAMPOLINE_INIT
51612 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
51613 #undef TARGET_RETURN_POPS_ARGS
51614 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
51616 #undef TARGET_LEGITIMATE_COMBINED_INSN
51617 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
51619 #undef TARGET_ASAN_SHADOW_OFFSET
51620 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
51622 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
51623 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
51625 #undef TARGET_SCALAR_MODE_SUPPORTED_P
51626 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
51628 #undef TARGET_VECTOR_MODE_SUPPORTED_P
51629 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
51631 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
51632 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
51633 ix86_libgcc_floating_mode_supported_p
51635 #undef TARGET_C_MODE_FOR_SUFFIX
51636 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
51638 #ifdef HAVE_AS_TLS
51639 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
51640 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
51641 #endif
51643 #ifdef SUBTARGET_INSERT_ATTRIBUTES
51644 #undef TARGET_INSERT_ATTRIBUTES
51645 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
51646 #endif
51648 #undef TARGET_MANGLE_TYPE
51649 #define TARGET_MANGLE_TYPE ix86_mangle_type
51651 #if !TARGET_MACHO
51652 #undef TARGET_STACK_PROTECT_FAIL
51653 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
51654 #endif
51656 #undef TARGET_FUNCTION_VALUE
51657 #define TARGET_FUNCTION_VALUE ix86_function_value
51659 #undef TARGET_FUNCTION_VALUE_REGNO_P
51660 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
51662 #undef TARGET_PROMOTE_FUNCTION_MODE
51663 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
51665 #undef TARGET_MEMBER_TYPE_FORCES_BLK
51666 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
51668 #undef TARGET_INSTANTIATE_DECLS
51669 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
51671 #undef TARGET_SECONDARY_RELOAD
51672 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
51674 #undef TARGET_CLASS_MAX_NREGS
51675 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
51677 #undef TARGET_PREFERRED_RELOAD_CLASS
51678 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
51679 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
51680 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
51681 #undef TARGET_CLASS_LIKELY_SPILLED_P
51682 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
51684 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
51685 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
51686 ix86_builtin_vectorization_cost
51687 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
51688 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
51689 ix86_vectorize_vec_perm_const_ok
51690 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
51691 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
51692 ix86_preferred_simd_mode
51693 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
51694 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
51695 ix86_autovectorize_vector_sizes
51696 #undef TARGET_VECTORIZE_INIT_COST
51697 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
51698 #undef TARGET_VECTORIZE_ADD_STMT_COST
51699 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
51700 #undef TARGET_VECTORIZE_FINISH_COST
51701 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
51702 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
51703 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
51705 #undef TARGET_SET_CURRENT_FUNCTION
51706 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
51708 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
51709 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
51711 #undef TARGET_OPTION_SAVE
51712 #define TARGET_OPTION_SAVE ix86_function_specific_save
51714 #undef TARGET_OPTION_RESTORE
51715 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
51717 #undef TARGET_OPTION_PRINT
51718 #define TARGET_OPTION_PRINT ix86_function_specific_print
51720 #undef TARGET_OPTION_FUNCTION_VERSIONS
51721 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
51723 #undef TARGET_CAN_INLINE_P
51724 #define TARGET_CAN_INLINE_P ix86_can_inline_p
51726 #undef TARGET_EXPAND_TO_RTL_HOOK
51727 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
51729 #undef TARGET_LEGITIMATE_ADDRESS_P
51730 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
51732 #undef TARGET_LRA_P
51733 #define TARGET_LRA_P hook_bool_void_true
51735 #undef TARGET_REGISTER_PRIORITY
51736 #define TARGET_REGISTER_PRIORITY ix86_register_priority
51738 #undef TARGET_REGISTER_USAGE_LEVELING_P
51739 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
51741 #undef TARGET_LEGITIMATE_CONSTANT_P
51742 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
51744 #undef TARGET_FRAME_POINTER_REQUIRED
51745 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
51747 #undef TARGET_CAN_ELIMINATE
51748 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
51750 #undef TARGET_EXTRA_LIVE_ON_ENTRY
51751 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
51753 #undef TARGET_ASM_CODE_END
51754 #define TARGET_ASM_CODE_END ix86_code_end
51756 #undef TARGET_CONDITIONAL_REGISTER_USAGE
51757 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
51759 #if TARGET_MACHO
51760 #undef TARGET_INIT_LIBFUNCS
51761 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
51762 #endif
51764 #undef TARGET_LOOP_UNROLL_ADJUST
51765 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
51767 #undef TARGET_SPILL_CLASS
51768 #define TARGET_SPILL_CLASS ix86_spill_class
51770 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
51771 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
51772 ix86_simd_clone_compute_vecsize_and_simdlen
51774 #undef TARGET_SIMD_CLONE_ADJUST
51775 #define TARGET_SIMD_CLONE_ADJUST \
51776 ix86_simd_clone_adjust
51778 #undef TARGET_SIMD_CLONE_USABLE
51779 #define TARGET_SIMD_CLONE_USABLE \
51780 ix86_simd_clone_usable
51782 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
51783 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
51784 ix86_float_exceptions_rounding_supported_p
51786 #undef TARGET_MODE_EMIT
51787 #define TARGET_MODE_EMIT ix86_emit_mode_set
51789 #undef TARGET_MODE_NEEDED
51790 #define TARGET_MODE_NEEDED ix86_mode_needed
51792 #undef TARGET_MODE_AFTER
51793 #define TARGET_MODE_AFTER ix86_mode_after
51795 #undef TARGET_MODE_ENTRY
51796 #define TARGET_MODE_ENTRY ix86_mode_entry
51798 #undef TARGET_MODE_EXIT
51799 #define TARGET_MODE_EXIT ix86_mode_exit
51801 #undef TARGET_MODE_PRIORITY
51802 #define TARGET_MODE_PRIORITY ix86_mode_priority
51804 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
51805 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
51807 #undef TARGET_LOAD_BOUNDS_FOR_ARG
51808 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
51810 #undef TARGET_STORE_BOUNDS_FOR_ARG
51811 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
51813 #undef TARGET_LOAD_RETURNED_BOUNDS
51814 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
51816 #undef TARGET_STORE_RETURNED_BOUNDS
51817 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
51819 #undef TARGET_CHKP_BOUND_MODE
51820 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
51822 #undef TARGET_BUILTIN_CHKP_FUNCTION
51823 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
51825 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
51826 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
51828 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
51829 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
51831 #undef TARGET_CHKP_INITIALIZE_BOUNDS
51832 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
51834 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
51835 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
51837 #undef TARGET_OFFLOAD_OPTIONS
51838 #define TARGET_OFFLOAD_OPTIONS \
51839 ix86_offload_options
51842 \f