| blob | ed1ad45de838436d580a8efe11c7e56f17fe9557 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with modified_between_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
109 /* Number of attempts to combine instructions in this function. */
113 /* Number of attempts that got as far as substitution in this function. */
117 /* Number of instructions combined with added SETs in this function. */
121 /* Number of instructions combined in this function. */
125 /* Totals over entire compilation. */
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
145 \f
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
160 following ways:
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
175 register's value
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
180 table.
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
198 rtx last_set_value;
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
205 /* Record the value of label_tick when the value for register n is placed in
206 last_set_value. */
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
233 zero.
235 If an entry is zero, it means that we don't know anything special. */
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
250 value. */
253 };
258 /* One plus the highest pseudo for which we track REG_N_SETS.
259 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
260 but during combine_split_insns new pseudos can be created. As we don't have
261 updated DF information in that case, it is hard to initialize the array
262 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
263 so instead of growing the arrays, just assume all newly created pseudos
264 during combine might be set multiple times. */
268 /* Record the luid of the last insn that invalidated memory
269 (anything that writes memory, and subroutine calls, but not pushes). */
273 /* Record the luid of the last CALL_INSN
274 so we can tell whether a potential combination crosses any calls. */
278 /* When `subst' is called, this is the insn that is being modified
279 (by combining in a previous insn). The PATTERN of this insn
280 is still the old pattern partially modified and it should not be
281 looked at, but this may be used to examine the successors of the insn
282 to judge whether a simplification is valid. */
286 /* This is the lowest LUID that `subst' is currently dealing with.
287 get_last_value will not return a value if the register was set at or
288 after this LUID. If not for this mechanism, we could get confused if
289 I2 or I1 in try_combine were an insn that used the old value of a register
290 to obtain a new value. In that case, we might erroneously get the
291 new value of the register when we wanted the old one. */
295 /* This contains any hard registers that are used in newpat; reg_dead_at_p
296 must consider all these registers to be always live. */
300 /* This is an insn to which a LOG_LINKS entry has been added. If this
301 insn is the earlier than I2 or I3, combine should rescan starting at
302 that location. */
306 /* And similarly, for notes. */
310 /* Basic block in which we are performing combines. */
314 \f
315 /* Length of the currently allocated uid_insn_cost array. */
319 /* The following array records the insn_cost for every insn
320 in the instruction stream. */
324 /* The following array records the LOG_LINKS for every insn in the
325 instruction stream as struct insn_link pointers. */
331 };
337 {
341 }
343 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
344 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
346 #define FOR_EACH_LOG_LINK(L, INSN) \
347 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
349 /* Links for LOG_LINKS are allocated from this obstack. */
353 /* Allocate a link. */
357 {
365 }
367 /* Incremented for each basic block. */
371 /* Reset to label_tick for each extended basic block in scanning order. */
375 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
376 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
380 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
381 be safely used. It is zero while computing them and after combine has
382 completed. This former test prevents propagating values based on
383 previously set values, which can be incorrect if a variable is modified
384 in a loop. */
388 \f
389 /* Record one modification to rtl structure
390 to be undone by storing old_contents into *where. */
394 struct undo
395 {
400 };
402 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
403 num_undo says how many are currently recorded.
405 other_insn is nonzero if we have modified some other insn in the process
406 of working on subst_insn. It must be verified too. */
408 struct undobuf
409 {
413 };
417 /* Number of times the pseudo being substituted for
418 was found and replaced. */
423 scalar_int_mode,
426 scalar_int_mode,
498 \f
500 /* It is not safe to use ordinary gen_lowpart in combine.
501 See comments in gen_lowpart_for_combine. */
502 #undef RTL_HOOKS_GEN_LOWPART
503 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
505 /* Our implementation of gen_lowpart never emits a new pseudo. */
506 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
507 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
509 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
510 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
512 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
513 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
515 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
516 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
520 \f
521 /* Convenience wrapper for the canonicalize_comparison target hook.
522 Target hooks cannot use enum rtx_code. */
526 {
530 }
532 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
533 PATTERN cannot be split. Otherwise, it returns an insn sequence.
534 This is a wrapper around split_insns which ensures that the
535 reg_stat vector is made larger if the splitter creates a new
536 register. */
540 {
549 }
551 /* This is used by find_single_use to locate an rtx in LOC that
552 contains exactly one use of DEST, which is typically either a REG
553 or CC0. It returns a pointer to the innermost rtx expression
554 containing DEST. Appearances of DEST that are being used to
555 totally replace it are not counted. */
559 {
568 {
572 CASE_CONST_ANY:
577 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
578 of a REG that occupies all of the REG, the insn uses DEST if
579 it is mentioned in the destination or the source. Otherwise, we
580 need just check the source. */
597 }
599 /* If it wasn't one of the common cases above, check each expression and
600 vector of this code. Look for a unique usage of DEST. */
604 {
606 {
611 else
617 /* Duplicate usage. */
619 }
621 {
625 {
631 else
638 }
639 }
640 }
643 }
646 /* See if DEST, produced in INSN, is used only a single time in the
647 sequel. If so, return a pointer to the innermost rtx expression in which
648 it is used.
650 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
652 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
653 care about REG_DEAD notes or LOG_LINKS.
655 Otherwise, we find the single use by finding an insn that has a
656 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
657 only referenced once in that insn, we know that it must be the first
658 and last insn referencing DEST. */
662 {
663 basic_block bb;
669 {
679 }
689 {
695 {
700 }
701 }
704 }
705 \f
706 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
707 insn. The substitution can be undone by undo_all. If INTO is already
708 set to NEWVAL, do not record this change. Because computing NEWVAL might
709 also call SUBST, we have to compute it before we put anything into
710 the undo table. */
712 static void
714 {
721 /* We'd like to catch as many invalid transformations here as
722 possible. Unfortunately, there are way too many mode changes
723 that are perfectly valid, so we'd waste too much effort for
724 little gain doing the checks here. Focus on catching invalid
725 transformations involving integer constants. */
728 {
729 /* Sanity check that we're replacing oldval with a CONST_INT
730 that is a valid sign-extension for the original mode. */
734 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
735 CONST_INT is not valid, because after the replacement, the
736 original mode would be gone. Unfortunately, we can't tell
737 when do_SUBST is called to replace the operand thereof, so we
738 perform this test on oldval instead, checking whether an
739 invalid replacement took place before we got here. */
744 }
748 else
757 }
759 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
761 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
762 for the value of a HOST_WIDE_INT value (including CONST_INT) is
763 not safe. */
765 static void
767 {
776 else
785 }
787 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
789 /* Similar to SUBST, but just substitute the mode. This is used when
790 changing the mode of a pseudo-register, so that any other
791 references to the entry in the regno_reg_rtx array will change as
792 well. */
794 static void
796 {
805 else
814 }
816 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
818 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
820 static void
822 {
831 else
840 }
842 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843 \f
844 /* Subroutine of try_combine. Determine whether the replacement patterns
845 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
846 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
847 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
848 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
849 of all the instructions can be estimated and the replacements are more
850 expensive than the original sequence. */
852 static bool
855 {
860 /* Lookup the original insn_costs. */
865 {
868 {
872 }
873 else
874 {
878 }
879 }
880 else
881 {
884 }
886 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
887 correct that. */
892 /* Calculate the replacement insn_costs. */
901 {
911 }
912 else
913 {
916 }
919 {
928 optimize_this_for_speed_p);
932 {
935 }
936 else
938 }
940 /* Disallow this combination if both new_cost and old_cost are greater than
941 zero, and new_cost is greater than old cost. */
945 {
964 else
966 }
971 /* Update the uid_insn_cost array with the replacement costs. */
975 {
979 }
982 }
985 /* Delete any insns that copy a register to itself.
986 Return true if the CFG was changed. */
988 static bool
990 {
992 basic_block bb;
997 {
999 {
1002 {
1007 }
1008 }
1009 }
1012 }
1014 \f
1015 /* Return false if we do not want to (or cannot) combine DEF. */
1016 static bool
1018 {
1019 /* Do not consider if it is pre/post modification in MEM. */
1025 /* Do not combine frame pointer adjustments. */
1028 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1036 }
1038 /* Return false if we do not want to (or cannot) combine USE. */
1039 static bool
1041 {
1042 /* Do not consider the usage of the stack pointer by function call. */
1047 }
1049 /* Fill in log links field for all insns. */
1051 static void
1053 {
1054 basic_block bb;
1061 /* Pass through each block from the end, recording the uses of each
1062 register and establishing log links when def is encountered.
1063 Note that we do not clear next_use array in order to save time,
1064 so we have to test whether the use is in the same basic block as def.
1066 There are a few cases below when we do not consider the definition or
1067 usage -- these are taken from original flow.c did. Don't ask me why it is
1068 done this way; I don't know and if it works, I don't want to know. */
1071 {
1073 {
1077 /* Log links are created only once. */
1081 {
1097 /* flow.c claimed:
1099 We don't build a LOG_LINK for hard registers contained
1100 in ASM_OPERANDs. If these registers get replaced,
1101 we might wind up changing the semantics of the insn,
1102 even if reload can make what appear to be valid
1103 assignments later. */
1108 /* Don't add duplicate links between instructions. */
1117 }
1122 }
1123 }
1126 }
1128 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1129 true if we found a LOG_LINK that proves that A feeds B. This only works
1130 if there are no instructions between A and B which could have a link
1131 depending on A, since in that case we would not record a link for B.
1132 We also check the implicit dependency created by a cc0 setter/user
1133 pair. */
1135 static bool
1137 {
1145 }
1146 \f
1147 /* Main entry point for combiner. F is the first insn of the function.
1148 NREGS is the first unused pseudo-reg number.
1150 Return nonzero if the CFG was changed (e.g. if the combiner has
1151 turned an indirect jump instruction into a direct jump). */
1152 static int
1154 {
1159 basic_block last_bb;
1179 /* Allocate array for insn info. */
1187 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1188 problems when, for example, we have j <<= 1 in a loop. */
1193 /* Scan all SETs and see if we can deduce anything about what
1194 bits are known to be zero for some registers and how many copies
1195 of the sign bit are known to exist for those registers.
1197 Also set any known values so that we can use it while searching
1198 for what bits are known to be set. */
1201 /* Allow the entry block and the first block to fall into the same EBB.
1202 Conceptually the incoming promotions are assigned to the entry block. */
1207 {
1212 label_tick++;
1220 {
1221 rtx links;
1233 insn);
1235 /* Record the current insn_cost of this instruction. */
1238 {
1241 }
1242 }
1243 }
1247 /* Now scan all the insns in forward order. */
1255 {
1258 /* Ignore instruction combination in basic blocks that are going to
1259 be removed as unreachable anyway. See PR82386. */
1267 label_tick++;
1277 {
1291 /* See if we know about function return values before this
1292 insn based upon SUBREG flags. */
1295 /* See if we can find hardregs and subreg of pseudos in
1296 narrower modes. This could help turning TRUNCATEs
1297 into SUBREGs. */
1300 /* Try this insn with each insn it links back to. */
1306 {
1309 }
1311 /* Try each sequence of three linked insns ending with this one. */
1315 {
1318 /* If the linked insn has been replaced by a note, then there
1319 is no point in pursuing this chain any further. */
1327 {
1330 }
1331 }
1333 /* Try to combine a jump insn that uses CC0
1334 with a preceding insn that sets CC0, and maybe with its
1335 logical predecessor as well.
1336 This is how we make decrement-and-branch insns.
1337 We need this special code because data flow connections
1338 via CC0 do not get entered in LOG_LINKS. */
1345 {
1356 }
1358 /* Do the same for an insn that explicitly references CC0. */
1365 {
1376 }
1378 /* Finally, see if any of the insns that this insn links to
1379 explicitly references CC0. If so, try this insn, that insn,
1380 and its predecessor if it sets CC0. */
1382 {
1394 }
1396 /* Try combining an insn with two different insns whose results it
1397 uses. */
1407 {
1410 }
1412 /* Try four-instruction combinations. */
1415 {
1419 /* If the linked insn has been replaced by a note, then there
1420 is no point in pursuing this chain any further. */
1425 {
1429 /* I0 -> I1 -> I2 -> I3. */
1435 {
1438 }
1439 /* I0, I1 -> I2, I2 -> I3. */
1446 {
1449 }
1450 }
1453 {
1457 /* I0 -> I2; I1, I2 -> I3. */
1463 {
1466 }
1467 /* I0 -> I1; I1, I2 -> I3. */
1473 {
1476 }
1477 }
1478 }
1480 /* Try this insn with each REG_EQUAL note it links back to. */
1482 {
1489 /* Avoid using a register that may already been marked
1490 dead by an earlier instruction. */
1498 {
1499 /* Temporarily replace the set's source with the
1500 contents of the REG_EQUAL note. The insn will
1501 be deleted or recognized by try_combine. */
1512 last_combined_insn);
1515 {
1518 }
1521 }
1522 }
1527 retry:
1528 ;
1529 }
1530 }
1537 /* Clean up. */
1543 {
1546 {
1549 }
1551 }
1561 /* Make recognizer allow volatile MEMs again. */
1565 }
1567 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1569 static void
1571 {
1577 }
1578 \f
1579 /* Set up any promoted values for incoming argument registers. */
1581 static void
1583 {
1584 tree arg;
1589 {
1594 /* Only continue if the incoming argument is in a register. */
1598 /* Determine, if possible, whether all call sites of the current
1599 function lie within the current compilation unit. (This does
1600 take into account the exporting of a function via taking its
1601 address, and so forth.) */
1602 strictly_local
1605 /* The mode and signedness of the argument before any promotions happen
1606 (equal to the mode of the pseudo holding it at that stage). */
1610 /* The mode and signedness of the argument after any source language and
1611 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1615 /* The mode and signedness of the argument as it is actually passed,
1616 see assign_parm_setup_reg in function.c. */
1620 /* The mode of the register in which the argument is being passed. */
1623 /* Eliminate sign extensions in the callee when:
1624 (a) A mode promotion has occurred; */
1627 /* (b) The mode of the register is the same as the mode of
1628 the argument as it is passed; */
1631 /* (c) There's no language level extension; */
1633 ;
1634 /* (c.1) All callers are from the current compilation unit. If that's
1635 the case we don't have to rely on an ABI, we only have to know
1636 what we're generating right now, and we know that we will do the
1637 mode1 to mode2 promotion with the given sign. */
1640 /* (c.2) The combination of the two promotions is useful. This is
1641 true when the signs match, or if the first promotion is unsigned.
1642 In the later case, (sign_extend (zero_extend x)) is the same as
1643 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1649 /* Record that the value was promoted from mode1 to mode3,
1650 so that any sign extension at the head of the current
1651 function may be eliminated. */
1655 }
1656 }
1658 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1659 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1660 because some machines (maybe most) will actually do the sign-extension and
1661 this is the conservative approach.
1663 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1664 kludge. */
1666 static rtx
1668 {
1669 scalar_int_mode int_mode;
1678 }
1680 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1681 and SET. */
1683 static void
1685 rtx x)
1686 {
1696 {
1700 }
1702 /* Don't call nonzero_bits if it cannot change anything. */
1704 {
1713 }
1715 /* Don't call num_sign_bit_copies if it cannot change anything. */
1717 {
1720 {
1724 }
1727 }
1728 }
1730 /* Called via note_stores. If X is a pseudo that is narrower than
1731 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1733 If we are setting only a portion of X and we can't figure out what
1734 portion, assume all bits will be used since we don't know what will
1735 be happening.
1737 Similarly, set how many bits of X are known to be copies of the sign bit
1738 at all locations in the function. This is the smallest number implied
1739 by any set of X. */
1741 static void
1743 {
1745 scalar_int_mode mode;
1749 /* If this register is undefined at the start of the file, we can't
1750 say what its contents were. */
1751 && ! REGNO_REG_SET_P
1755 {
1759 {
1763 }
1765 /* If this register is being initialized using itself, and the
1766 register is uninitialized in this basic block, and there are
1767 no LOG_LINKS which set the register, then part of the
1768 register is uninitialized. In that case we can't assume
1769 anything about the number of nonzero bits.
1771 ??? We could do better if we checked this in
1772 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1773 could avoid making assumptions about the insn which initially
1774 sets the register, while still using the information in other
1775 insns. We would have to be careful to check every insn
1776 involved in the combination. */
1782 {
1789 {
1793 }
1794 }
1796 /* If this is a complex assignment, see if we can convert it into a
1797 simple assignment. */
1800 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1801 set what we know about X. */
1807 else
1808 {
1811 }
1812 }
1813 }
1814 \f
1815 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1816 optionally insns that were previously combined into I3 or that will be
1817 combined into the merger of INSN and I3. The order is PRED, PRED2,
1818 INSN, SUCC, SUCC2, I3.
1820 Return 0 if the combination is not allowed for any reason.
1822 If the combination is allowed, *PDEST will be set to the single
1823 destination of INSN and *PSRC to the single source, and this function
1824 will return 1. */
1826 static int
1830 {
1835 rtx link;
1840 {
1842 {
1847 }
1852 }
1856 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1857 or a PARALLEL consisting of such a SET and CLOBBERs.
1859 If INSN has CLOBBER parallel parts, ignore them for our processing.
1860 By definition, these happen during the execution of the insn. When it
1861 is merged with another insn, all bets are off. If they are, in fact,
1862 needed and aren't also supplied in I3, they may be added by
1863 recog_for_combine. Otherwise, it won't match.
1865 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1866 note.
1868 Get the source and destination of INSN. If more than one, can't
1869 combine. */
1875 {
1877 {
1881 {
1882 /* This is important to combine floating point insns
1883 for the SH4 port. */
1885 /* Combining an isolated USE doesn't make sense.
1886 We depend here on combinable_i3pat to reject them. */
1887 /* The code below this loop only verifies that the inputs of
1888 the SET in INSN do not change. We call reg_set_between_p
1889 to verify that the REG in the USE does not change between
1890 I3 and INSN.
1891 If the USE in INSN was for a pseudo register, the matching
1892 insn pattern will likely match any register; combining this
1893 with any other USE would only be safe if we knew that the
1894 used registers have identical values, or if there was
1895 something to tell them apart, e.g. different modes. For
1896 now, we forgo such complicated tests and simply disallow
1897 combining of USES of pseudo registers with any other USE. */
1900 {
1905 do
1906 {
1916 }
1918 }
1921 /* We can ignore CLOBBERs. */
1926 /* Ignore SETs whose result isn't used but not those that
1927 have side-effects. */
1933 /* If we have already found a SET, this is a second one and
1934 so we cannot combine with this insn. */
1942 /* Anything else means we can't combine. */
1944 }
1945 }
1948 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1949 so don't do anything with it. */
1952 }
1953 else
1959 /* The simplification in expand_field_assignment may call back to
1960 get_last_value, so set safe guard here. */
1966 /* Do not eliminate user-specified register if it is in an
1967 asm input because we may break the register asm usage defined
1968 in GCC manual if allow to do so.
1969 Be aware that this may cover more cases than we expect but this
1970 should be harmless. */
1975 /* Don't eliminate a store in the stack pointer. */
1977 /* Don't combine with an insn that sets a register to itself if it has
1978 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1980 /* Can't merge an ASM_OPERANDS. */
1982 /* Can't merge a function call. */
1984 /* Don't eliminate a function call argument. */
1990 /* Don't substitute into an incremented register. */
1994 /* Don't substitute into a non-local goto, this confuses CFG. */
1996 /* Make sure that DEST is not used after INSN but before SUCC, or
1997 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1998 || (!all_adjacent
1999 && ((succ2
2004 || (succ
2005 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
2006 that case SUCC is not in the insn stream, so use SUCC2
2007 instead for this test. */
2009 succ2
2012 /* Make sure that the value that is to be substituted for the register
2013 does not use any registers whose values alter in between. However,
2014 If the insns are adjacent, a use can't cross a set even though we
2015 think it might (this can happen for a sequence of insns each setting
2016 the same destination; last_set of that register might point to
2017 a NOTE). If INSN has a REG_EQUIV note, the register is always
2018 equivalent to the memory so the substitution is valid even if there
2019 are intervening stores. Also, don't move a volatile asm or
2020 UNSPEC_VOLATILE across any other insns. */
2021 || (! all_adjacent
2027 /* Don't combine across a CALL_INSN, because that would possibly
2028 change whether the life span of some REGs crosses calls or not,
2029 and it is a pain to update that information.
2030 Exception: if source is a constant, moving it later can't hurt.
2031 Accept that as a special case. */
2035 /* DEST must either be a REG or CC0. */
2037 {
2038 /* If register alignment is being enforced for multi-word items in all
2039 cases except for parameters, it is possible to have a register copy
2040 insn referencing a hard register that is not allowed to contain the
2041 mode being copied and which would not be valid as an operand of most
2042 insns. Eliminate this problem by not combining with such an insn.
2044 Also, on some machines we don't want to extend the life of a hard
2045 register. */
2050 /* Don't extend the life of a hard register unless it is
2051 user variable (if we have few registers) or it can't
2052 fit into the desired register (meaning something special
2053 is going on).
2054 Also avoid substituting a return register into I3, because
2055 reload can't handle a conflict with constraints of other
2056 inputs. */
2061 }
2069 {
2072 /* If the clobber represents an earlyclobber operand, we must not
2073 substitute an expression containing the clobbered register.
2074 As we do not analyze the constraint strings here, we have to
2075 make the conservative assumption. However, if the register is
2076 a fixed hard reg, the clobber cannot represent any operand;
2077 we leave it up to the machine description to either accept or
2078 reject use-and-clobber patterns. */
2084 }
2086 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2087 or not), reject, unless nothing volatile comes between it and I3 */
2090 {
2091 /* Make sure neither succ nor succ2 contains a volatile reference. */
2096 /* We'll check insns between INSN and I3 below. */
2097 }
2099 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2100 to be an explicit register variable, and was chosen for a reason. */
2106 /* If INSN contains volatile references (specifically volatile MEMs),
2107 we cannot combine across any other volatile references.
2108 Even if INSN doesn't contain volatile references, any intervening
2109 volatile insn might affect machine state. */
2112 ? volatile_refs_p
2119 /* If INSN contains an autoincrement or autodecrement, make sure that
2120 register is not used between there and I3, and not already used in
2121 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2122 Also insist that I3 not be a jump if using LRA; if it were one
2123 and the incremented register were spilled, we would lose.
2124 Reload handles this correctly. */
2142 /* Don't combine an insn that follows a CC0-setting insn.
2143 An insn that uses CC0 must not be separated from the one that sets it.
2144 We do, however, allow I2 to follow a CC0-setting insn if that insn
2145 is passed as I1; in that case it will be deleted also.
2146 We also allow combining in this case if all the insns are adjacent
2147 because that would leave the two CC0 insns adjacent as well.
2148 It would be more logical to test whether CC0 occurs inside I1 or I2,
2149 but that would be much slower, and this ought to be equivalent. */
2152 {
2157 }
2159 /* If we get here, we have passed all the tests and the combination is
2160 to be allowed. */
2166 }
2167 \f
2168 /* LOC is the location within I3 that contains its pattern or the component
2169 of a PARALLEL of the pattern. We validate that it is valid for combining.
2171 One problem is if I3 modifies its output, as opposed to replacing it
2172 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2173 doing so would produce an insn that is not equivalent to the original insns.
2175 Consider:
2177 (set (reg:DI 101) (reg:DI 100))
2178 (set (subreg:SI (reg:DI 101) 0) <foo>)
2180 This is NOT equivalent to:
2182 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2183 (set (reg:DI 101) (reg:DI 100))])
2185 Not only does this modify 100 (in which case it might still be valid
2186 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2188 We can also run into a problem if I2 sets a register that I1
2189 uses and I1 gets directly substituted into I3 (not via I2). In that
2190 case, we would be getting the wrong value of I2DEST into I3, so we
2191 must reject the combination. This case occurs when I2 and I1 both
2192 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2193 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2194 of a SET must prevent combination from occurring. The same situation
2195 can occur for I0, in which case I0_NOT_IN_SRC is set.
2197 Before doing the above check, we first try to expand a field assignment
2198 into a set of logical operations.
2200 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2201 we place a register that is both set and used within I3. If more than one
2202 such register is detected, we fail.
2204 Return 1 if the combination is valid, zero otherwise. */
2206 static int
2209 {
2213 {
2218 rtx subdest;
2225 /* Check for the case where I3 modifies its output, as discussed
2226 above. We don't want to prevent pseudos from being combined
2227 into the address of a MEM, so only prevent the combination if
2228 i1 or i2 set the same MEM. */
2238 /* This is the same test done in can_combine_p except we can't test
2239 all_adjacent; we don't have to, since this instruction will stay
2240 in place, thus we are not considering increasing the lifetime of
2241 INNER_DEST.
2243 Also, if this insn sets a function argument, combining it with
2244 something that might need a spill could clobber a previous
2245 function argument; the all_adjacent test in can_combine_p also
2246 checks this; here, we do a more specific test for this case. */
2256 /* If DEST is used in I3, it is being killed in this insn, so
2257 record that for later. We have to consider paradoxical
2258 subregs here, since they kill the whole register, but we
2259 ignore partial subregs, STRICT_LOW_PART, etc.
2260 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2261 STACK_POINTER_REGNUM, since these are always considered to be
2262 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2270 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2276 {
2281 }
2282 }
2285 {
2292 }
2295 }
2296 \f
2297 /* Return 1 if X is an arithmetic expression that contains a multiplication
2298 and division. We don't count multiplications by powers of two here. */
2300 static int
2302 {
2304 {
2320 }
2321 }
2322 \f
2323 /* Determine whether INSN can be used in a combination. Return nonzero if
2324 not. This is used in try_combine to detect early some cases where we
2325 can't perform combinations. */
2327 static int
2329 {
2330 rtx set;
2333 /* If this isn't really an insn, we can't do anything.
2334 This can occur when flow deletes an insn that it has merged into an
2335 auto-increment address. */
2339 /* Never combine loads and stores involving hard regs that are likely
2340 to be spilled. The register allocator can usually handle such
2341 reg-reg moves by tying. If we allow the combiner to make
2342 substitutions of likely-spilled regs, reload might die.
2343 As an exception, we allow combinations involving fixed regs; these are
2344 not available to the register allocator so there's no risk involved. */
2358 #ifdef LEAF_REGISTERS
2360 #else
2361 )
2362 #endif
2369 }
2371 struct likely_spilled_retval_info
2372 {
2375 };
2377 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2378 hard registers that are known to be written to / clobbered in full. */
2379 static void
2381 {
2398 else
2401 }
2403 /* Return nonzero iff part of the return value is live during INSN, and
2404 it is likely spilled. This can happen when more than one insn is needed
2405 to copy the return value, e.g. when we consider to combine into the
2406 second copy insn for a complex value. */
2408 static int
2410 {
2412 rtx reg;
2415 /* We assume here that no machine mode needs more than
2416 32 hard registers when the value overlaps with a register
2417 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2432 /* Disregard parts of the return value that are set later. */
2441 /* Check if any of the (probably) live return value registers is
2442 likely spilled. */
2443 nregs --;
2444 do
2445 {
2451 }
2453 /* Adjust INSN after we made a change to its destination.
2455 Changing the destination can invalidate notes that say something about
2456 the results of the insn and a LOG_LINK pointing to the insn. */
2458 static void
2460 {
2461 /* For notes, be conservative and simply remove them. */
2464 /* The new insn will have a destination that was previously the destination
2465 of an insn just above it. Call distribute_links to make a LOG_LINK from
2466 the next use of that destination. */
2482 }
2484 /* Return TRUE if combine can reuse reg X in mode MODE.
2485 ADDED_SETS is nonzero if the original set is still required. */
2486 static bool
2488 {
2494 /* Don't change between modes with different underlying register sizes,
2495 since this could lead to invalid subregs. */
2501 /* Allow hard registers if the new mode is legal, and occupies no more
2502 registers than the old mode. */
2507 /* Or a pseudo that is only used once. */
2510 && !added_sets
2512 }
2515 /* Check whether X, the destination of a set, refers to part of
2516 the register specified by REG. */
2518 static bool
2520 {
2521 /* Check that reg is an integer mode register. */
2532 }
2534 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2535 Note that the INSN should be deleted *after* removing dead edges, so
2536 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2537 but not for a (set (pc) (label_ref FOO)). */
2539 static void
2541 {
2549 {
2554 /* Remove barriers from the footer if there are any. */
2557 {
2560 else
2564 }
2567 }
2568 }
2570 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2571 by an arbitrary number of CLOBBERs. */
2572 static bool
2574 {
2589 {
2596 }
2598 }
2600 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2601 CLOBBERs), can be split into individual SETs in that order, without
2602 changing semantics. */
2603 static bool
2605 {
2613 {
2622 }
2625 }
2627 /* Return whether X is just a single_set, with the source
2628 a general_operand. */
2629 static bool
2631 {
2637 }
2639 /* Callback function to count autoincs. */
2641 static int
2643 {
2647 }
2649 /* Try to combine the insns I0, I1 and I2 into I3.
2650 Here I0, I1 and I2 appear earlier than I3.
2651 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2652 I3.
2654 If we are combining more than two insns and the resulting insn is not
2655 recognized, try splitting it into two insns. If that happens, I2 and I3
2656 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2657 Otherwise, I0, I1 and I2 are pseudo-deleted.
2659 Return 0 if the combination does not work. Then nothing is changed.
2660 If we did the combination, return the insn at which combine should
2661 resume scanning.
2663 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2664 new direct jump instruction.
2666 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2667 been I3 passed to an earlier try_combine within the same basic
2668 block. */
2673 {
2674 /* New patterns for I3 and I2, respectively. */
2678 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2679 dead. */
2681 /* Total number of SETs to put into I3. */
2683 /* Nonzero if I2's or I1's body now appears in I3. */
2685 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2687 /* Contains I3 if the destination of I3 is used in its source, which means
2688 that the old life of I3 is being killed. If that usage is placed into
2689 I2 and not in I3, a REG_DEAD note must be made. */
2691 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2693 /* Copy of SET_SRC of I1 and I0, if needed. */
2695 /* Set if I2DEST was reused as a scratch register. */
2697 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2699 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2704 /* Notes that must be added to REG_NOTES in I3 and I2. */
2706 /* Notes that we substituted I3 into I2 instead of the normal case. */
2708 /* Notes that I1, I2 or I3 is a MULT operation. */
2718 rtx temp_expr;
2721 rtx new_other_notes;
2725 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2726 never be). */
2730 /* Only try four-insn combinations when there's high likelihood of
2731 success. Look for simple insns, such as loads of constants or
2732 binary operations involving a constant. */
2734 {
2744 {
2747 rtx src;
2752 {
2755 }
2757 ngood++;
2760 nshift++;
2761 }
2763 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2764 are likely manipulating its value. Ideally we'll be able to combine
2765 all four insns into a bitfield insertion of some kind.
2767 Note the source in I0 might be inside a sign/zero extension and the
2768 memory modes in I0 and I3 might be different. So extract the address
2769 from the destination of I3 and search for it in the source of I0.
2771 In the event that there's a match but the source/dest do not actually
2772 refer to the same memory, the worst that happens is we try some
2773 combinations that we wouldn't have otherwise. */
2775 /* Ensure the source of SET0 is a MEM, possibly buried inside
2776 an extension. */
2782 /* Ensure the destination of SET3 is a MEM. */
2784 /* Would it be better to extract the base address for the MEM
2785 in SET3 and look for that? I don't have cases where it matters
2786 but I could envision such cases. */
2792 }
2794 /* Exit early if one of the insns involved can't be used for
2795 combinations. */
2806 combine_attempts++;
2809 /* Reset the hard register usage information. */
2813 {
2820 else
2830 }
2832 /* If multiple insns feed into one of I2 or I3, they can be in any
2833 order. To simplify the code below, reorder them in sequence. */
2844 /* First check for one important special case that the code below will
2845 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2846 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2847 we may be able to replace that destination with the destination of I3.
2848 This occurs in the common code where we compute both a quotient and
2849 remainder into a structure, in which case we want to do the computation
2850 directly into the structure to avoid register-register copies.
2852 Note that this case handles both multiple sets in I2 and also cases
2853 where I2 has a number of CLOBBERs inside the PARALLEL.
2855 We make very conservative checks below and only try to handle the
2856 most common cases of this. For example, we only handle the case
2857 where I2 and I3 are adjacent to avoid making difficult register
2858 usage tests. */
2866 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2867 below would need to check what is inside (and reg_overlap_mentioned_p
2868 doesn't support those codes anyway). Don't allow those destinations;
2869 the resulting insn isn't likely to be recognized anyway. */
2875 {
2878 /* Make sure that the destination of I3,
2879 which we are going to substitute into one output of I2,
2880 is not used within another output of I2. We must avoid making this:
2881 (parallel [(set (mem (reg 69)) ...)
2882 (set (reg 69) ...)])
2883 which is not well-defined as to order of actions.
2884 (Besides, reload can't handle output reloads for this.)
2886 The problem can also happen if the dest of I3 is a memory ref,
2887 if another dest in I2 is an indirect memory ref.
2889 Neither can this PARALLEL be an asm. We do not allow combining
2890 that usually (see can_combine_p), so do not here either. */
2893 {
2902 }
2908 {
2909 combine_merges++;
2919 /* Replace the dest in I2 with our dest and make the resulting
2920 insn the new pattern for I3. Then skip to where we validate
2921 the pattern. Everything was set up above. */
2926 }
2927 }
2929 /* If I2 is setting a pseudo to a constant and I3 is setting some
2930 sub-part of it to another constant, merge them by making a new
2931 constant. */
2939 {
2946 {
2951 {
2957 }
2958 }
2959 else
2960 {
2964 {
2967 }
2968 }
2971 {
2972 /* If this is the low part, we're done. */
2974 ;
2975 /* Handle the case where inner is twice the size of outer. */
2979 /* Otherwise give up for now. */
2980 else
2982 }
2985 {
2993 combine_merges++;
3000 /* Replace the source in I2 with the new constant and make the
3001 resulting insn the new pattern for I3. Then skip to where we
3002 validate the pattern. Everything was set up above. */
3008 /* The dest of I3 has been replaced with the dest of I2. */
3011 }
3012 }
3014 /* If we have no I1 and I2 looks like:
3015 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
3016 (set Y OP)])
3017 make up a dummy I1 that is
3018 (set Y OP)
3019 and change I2 to be
3020 (set (reg:CC X) (compare:CC Y (const_int 0)))
3022 (We can ignore any trailing CLOBBERs.)
3024 This undoes a previous combination and allows us to match a branch-and-
3025 decrement insn. */
3037 {
3038 /* We make I1 with the same INSN_UID as I2. This gives it
3039 the same DF_INSN_LUID for value tracking. Our fake I1 will
3040 never appear in the insn stream so giving it the same INSN_UID
3041 as I2 will not cause a problem. */
3054 }
3056 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3057 make those two SETs separate I1 and I2 insns, and make an I0 that is
3058 the original I1. */
3066 {
3067 /* If there is no I1, there is no I0 either. */
3070 /* We make I1 with the same INSN_UID as I2. This gives it
3071 the same DF_INSN_LUID for value tracking. Our fake I1 will
3072 never appear in the insn stream so giving it the same INSN_UID
3073 as I2 will not cause a problem. */
3081 }
3083 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
3085 {
3090 }
3092 {
3097 }
3099 {
3104 }
3106 /* Record whether i2 and i3 are trivial moves. */
3110 /* Record whether I2DEST is used in I2SRC and similarly for the other
3111 cases. Knowing this will help in register status updating below. */
3122 /* For the earlier insns, determine which of the subsequent ones they
3123 feed. */
3130 /* Ensure that I3's pattern can be the destination of combines. */
3136 {
3139 }
3141 /* See if any of the insns is a MULT operation. Unless one is, we will
3142 reject a combination that is, since it must be slower. Be conservative
3143 here. */
3151 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3152 We used to do this EXCEPT in one case: I3 has a post-inc in an
3153 output operand. However, that exception can give rise to insns like
3154 mov r3,(r3)+
3155 which is a famous insn on the PDP-11 where the value of r3 used as the
3156 source was model-dependent. Avoid this sort of thing. */
3158 #if 0
3164 /* It's not the exception. */
3165 #endif
3167 {
3168 rtx link;
3174 {
3177 }
3178 }
3180 /* See if the SETs in I1 or I2 need to be kept around in the merged
3181 instruction: whenever the value set there is still needed past I3.
3182 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3184 For the SET in I1, we have two cases: if I1 and I2 independently feed
3185 into I3, the set in I1 needs to be kept around unless I1DEST dies
3186 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3187 in I1 needs to be kept around unless I1DEST dies or is set in either
3188 I2 or I3. The same considerations apply to I0. */
3195 else
3203 else
3206 /* We are about to copy insns for the case where they need to be kept
3207 around. Check that they can be copied in the merged instruction. */
3213 {
3216 }
3218 /* Count how many auto_inc expressions there were in the original insns;
3219 we need to have the same number in the resulting patterns. */
3228 /* If the set in I2 needs to be kept around, we must make a copy of
3229 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3230 PATTERN (I2), we are only substituting for the original I1DEST, not into
3231 an already-substituted copy. This also prevents making self-referential
3232 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3233 I2DEST. */
3236 {
3239 else
3241 }
3244 {
3247 else
3249 }
3252 {
3255 else
3257 }
3259 combine_merges++;
3261 /* Substitute in the latest insn for the regs set by the earlier ones. */
3267 /* Many machines that don't use CC0 have insns that can both perform an
3268 arithmetic operation and set the condition code. These operations will
3269 be represented as a PARALLEL with the first element of the vector
3270 being a COMPARE of an arithmetic operation with the constant zero.
3271 The second element of the vector will set some pseudo to the result
3272 of the same arithmetic operation. If we simplify the COMPARE, we won't
3273 match such a pattern and so will generate an extra insn. Here we test
3274 for this case, where both the comparison and the operation result are
3275 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3276 I2SRC. Later we will make the PARALLEL that contains I2. */
3282 {
3283 rtx newpat_dest;
3289 scalar_int_mode mode;
3298 {
3304 }
3306 /* Do the rest only if op1 is const0_rtx, which may be the
3307 result of simplification. */
3309 {
3310 /* If a single use of the CC is found, prepare to modify it
3311 when SELECT_CC_MODE returns a new CC-class mode, or when
3312 the above simplify_compare_const() returned a new comparison
3313 operator. undobuf.other_insn is assigned the CC use insn
3314 when modifying it. */
3316 {
3317 #ifdef SELECT_CC_MODE
3318 machine_mode new_mode
3323 {
3328 else
3329 {
3332 }
3333 }
3334 #endif
3335 /* Cases for modifying the CC-using comparison. */
3337 /* ??? Do we need to verify the zero rtx? */
3339 {
3340 /* Replace cc_use_loc with entire new RTX. */
3345 }
3347 {
3348 /* Just replace the CC reg with a new mode. */
3351 }
3352 }
3354 /* Now we modify the current newpat:
3355 First, SET_DEST(newpat) is updated if the CC mode has been
3356 altered. For targets without SELECT_CC_MODE, this should be
3357 optimized away. */
3360 /* This is always done to propagate i2src into newpat. */
3363 /* Create new version of i2pat if needed; the below PARALLEL
3364 creation needs this to work correctly. */
3368 }
3369 }
3372 {
3373 /* It is possible that the source of I2 or I1 may be performing
3374 an unneeded operation, such as a ZERO_EXTEND of something
3375 that is known to have the high part zero. Handle that case
3376 by letting subst look at the inner insns.
3378 Another way to do this would be to have a function that tries
3379 to simplify a single insn instead of merging two or more
3380 insns. We don't do this because of the potential of infinite
3381 loops and because of the potential extra memory required.
3382 However, doing it the way we are is a bit of a kludge and
3383 doesn't catch all cases.
3385 But only do this if -fexpensive-optimizations since it slows
3386 things down and doesn't usually win.
3388 This is not done in the COMPARE case above because the
3389 unmodified I2PAT is used in the PARALLEL and so a pattern
3390 with a modified I2SRC would not match. */
3393 {
3394 /* Pass pc_rtx so no substitutions are done, just
3395 simplifications. */
3397 {
3400 }
3404 }
3409 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3410 copy of I2SRC each time we substitute it, in order to avoid creating
3411 self-referential RTL when we will be substituting I1SRC for I1DEST
3412 later. Likewise if I0 feeds into I2, either directly or indirectly
3413 through I1, and I0DEST is in I0SRC. */
3420 /* Record whether I2's body now appears within I3's body. */
3422 }
3424 /* If we already got a failure, don't try to do more. Otherwise, try to
3425 substitute I1 if we have it. */
3428 {
3429 /* Before we can do this substitution, we must redo the test done
3430 above (see detailed comments there) that ensures I1DEST isn't
3431 mentioned in any SETs in NEWPAT that are field assignments. */
3434 {
3437 }
3442 /* If the following substitution will modify I1SRC, make a copy of it
3443 for the case where it is substituted for I1DEST in I2PAT later. */
3447 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3448 copy of I1SRC each time we substitute it, in order to avoid creating
3449 self-referential RTL when we will be substituting I0SRC for I0DEST
3450 later. */
3455 /* Record whether I1's body now appears within I3's body. */
3457 }
3459 /* Likewise for I0 if we have it. */
3462 {
3465 {
3468 }
3470 /* If the following substitution will modify I0SRC, make a copy of it
3471 for the case where it is substituted for I0DEST in I1PAT later. */
3474 /* And a copy for I0DEST in I2PAT substitution. */
3483 }
3486 {
3491 {
3496 }
3497 }
3499 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3500 to count all the ways that I2SRC and I1SRC can be used. */
3511 /* Fail if we tried to make a new register. */
3513 /* Fail if we couldn't do something and have a CLOBBER. */
3515 /* Fail if this new pattern is a MULT and we didn't have one before
3516 at the outer level. */
3519 {
3522 }
3524 /* If the actions of the earlier insns must be kept
3525 in addition to substituting them into the latest one,
3526 we must make a new PARALLEL for the latest insn
3527 to hold additional the SETs. */
3530 {
3532 combine_extras++;
3535 {
3541 }
3542 else
3543 {
3548 }
3554 {
3560 }
3562 {
3571 }
3572 }
3574 validate_replacement:
3576 /* Note which hard regs this insn has as inputs. */
3579 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3580 consider splitting this pattern, we might need these clobbers. */
3583 {
3589 }
3591 /* We have recognized nothing yet. */
3594 /* See if this is a PARALLEL of two SETs where one SET's destination is
3595 a register that is unused and this isn't marked as an instruction that
3596 might trap in an EH region. In that case, we just need the other SET.
3597 We prefer this over the PARALLEL.
3599 This can occur when simplifying a divmod insn. We *must* test for this
3600 case here because the code below that splits two independent SETs doesn't
3601 handle this case correctly when it updates the register status.
3603 It's pointless doing this if we originally had two sets, one from
3604 i3, and one from i2. Combining then splitting the parallel results
3605 in the original i2 again plus an invalid insn (which we delete).
3606 The net effect is only to move instructions around, which makes
3607 debug info less accurate.
3609 If the remaining SET came from I2 its destination should not be used
3610 between I2 and I3. See PR82024. */
3615 {
3626 {
3629 }
3638 {
3643 {
3649 }
3650 }
3654 }
3656 /* Is the result of combination a valid instruction? */
3660 /* If we were combining three insns and the result is a simple SET
3661 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3662 insns. There are two ways to do this. It can be split using a
3663 machine-specific method (like when you have an addition of a large
3664 constant) or by combine in the function find_split_point. */
3668 {
3672 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3673 use I2DEST as a scratch register will help. In the latter case,
3674 convert I2DEST to the mode of the source of NEWPAT if we can. */
3678 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3679 inputs of NEWPAT. */
3681 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3682 possible to try that as a scratch reg. This would require adding
3683 more code to make it work though. */
3686 {
3689 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3690 (temporarily, until we are committed to this instruction
3691 combination) does not work: for example, any call to nonzero_bits
3692 on the register (from a splitter in the MD file, for example)
3693 will get the old information, which is invalid.
3695 Since nowadays we can create registers during combine just fine,
3696 we should just create a new one here, not reuse i2dest. */
3698 /* First try to split using the original register as a
3699 scratch register. */
3703 i2dest)));
3706 /* If that didn't work, try changing the mode of I2DEST if
3707 we can. */
3712 {
3714 rtx ni2dest;
3718 else
3719 {
3722 }
3724 parallel = (gen_rtx_PARALLEL
3728 ni2dest))));
3733 {
3741 }
3742 }
3745 }
3747 /* If recog_for_combine has discarded clobbers, try to use them
3748 again for the split. */
3750 {
3753 }
3756 {
3761 }
3765 {
3775 /* If I2 or I3 has multiple SETs, we won't know how to track
3776 register status, so don't use these insns. If I2's destination
3777 is used between I2 and I3, we also can't use these insns. */
3787 /* It is possible that both insns now set the destination of I3.
3788 If so, we must show an extra use of it. */
3791 {
3810 }
3811 }
3813 /* If we can split it and use I2DEST, go ahead and see if that
3814 helps things be recognized. Verify that none of the registers
3815 are set between I2 and I3. */
3819 /* We need I2DEST in the proper mode. If it is a hard register
3820 or the only use of a pseudo, we can change its mode.
3821 Make sure we don't change a hard register to have a mode that
3822 isn't valid for it, or change the number of registers. */
3829 /* We can't overwrite I2DEST if its value is still used by
3830 NEWPAT. */
3832 {
3841 /* *SPLIT may be part of I2SRC, so make sure we have the
3842 original expression around for later debug processing.
3843 We should not need I2SRC any more in other cases. */
3846 else
3849 /* Get NEWDEST as a register in the proper mode. We have already
3850 validated that we can do this. */
3852 {
3855 else
3856 {
3859 }
3860 }
3862 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3863 an ASHIFT. This can occur if it was inside a PLUS and hence
3864 appeared to be a memory address. This is a kludge. */
3869 {
3873 /* Update split_code because we may not have a multiply
3874 anymore. */
3876 }
3878 /* Similarly for (plus (mult FOO (const_int pow2))). */
3884 {
3889 i_rtx));
3890 /* Update split_code because we may not have a multiply
3891 anymore. */
3893 }
3895 #ifdef INSN_SCHEDULING
3896 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3897 be written as a ZERO_EXTEND. */
3899 {
3900 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3901 what it really is. */
3906 else
3909 }
3910 #endif
3912 /* Attempt to split binary operators using arithmetic identities. */
3916 {
3923 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3925 {
3930 }
3931 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3938 {
3944 /* Split both "((X op Y) op X) op Y" and
3945 "((X op Y) op Y) op X" as "T op T" where T is
3946 "X op Y". */
3949 {
3954 }
3955 /* Split "((X op X) op Y) op Y)" as "T op T" where
3956 T is "X op Y". */
3958 {
3964 }
3965 }
3966 }
3969 {
3972 }
3976 /* recog_for_combine might have added CLOBBERs to newi2pat.
3977 Make sure NEWPAT does not depend on the clobbered regs. */
3981 {
3984 {
3987 }
3988 }
3990 /* If the split point was a MULT and we didn't have one before,
3991 don't use one now. */
3994 }
3995 }
3997 /* Check for a case where we loaded from memory in a narrow mode and
3998 then sign extended it, but we need both registers. In that case,
3999 we have a PARALLEL with both loads from the same memory location.
4000 We can split this into a load from memory followed by a register-register
4001 copy. This saves at least one insn, more if register allocation can
4002 eliminate the copy.
4004 We cannot do this if the destination of the first assignment is a
4005 condition code register or cc0. We eliminate this case by making sure
4006 the SET_DEST and SET_SRC have the same mode.
4008 We cannot do this if the destination of the second assignment is
4009 a register that we have already assumed is zero-extended. Similarly
4010 for a SUBREG of such a register. */
4029 BITS_PER_WORD)
4031 HOST_BITS_PER_INT)
4039 BITS_PER_WORD)
4041 HOST_BITS_PER_INT)
4048 {
4049 rtx ni2dest;
4063 }
4065 /* Similarly, check for a case where we have a PARALLEL of two independent
4066 SETs but we started with three insns. In this case, we can do the sets
4067 as two separate insns. This case occurs when some SET allows two
4068 other insns to combine, but the destination of that SET is still live.
4070 Also do this if we started with two insns and (at least) one of the
4071 resulting sets is a noop; this noop will be deleted later.
4073 Also do this if we started with two insns neither of which was a simple
4074 move. */
4081 && (i1
4095 {
4099 /* Normally, it doesn't matter which of the two is done first,
4100 but the one that references cc0 can't be the second, and
4101 one which uses any regs/memory set in between i2 and i3 can't
4102 be first. The PARALLEL might also have been pre-existing in i3,
4103 so we need to make sure that we won't wrongly hoist a SET to i2
4104 that would conflict with a death note present in there, or would
4105 have its dest modified between i2 and i3. */
4114 /* If I3 is a jump, ensure that set0 is a jump so that
4115 we do not create invalid RTL. */
4117 )
4118 {
4121 }
4130 /* If I3 is a jump, ensure that set1 is a jump so that
4131 we do not create invalid RTL. */
4133 )
4134 {
4137 }
4138 else
4139 {
4142 }
4147 {
4148 /* recog_for_combine might have added CLOBBERs to newi2pat.
4149 Make sure NEWPAT does not depend on the clobbered regs. */
4151 {
4154 {
4157 {
4160 }
4161 }
4162 }
4168 }
4169 }
4171 /* If it still isn't recognized, fail and change things back the way they
4172 were. */
4174 /* Is the result a reasonable ASM_OPERANDS? */
4176 {
4179 }
4181 /* If we had to change another insn, make sure it is valid also. */
4183 {
4191 {
4194 }
4195 }
4197 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4198 they are adjacent to each other or not. */
4200 {
4204 {
4207 }
4208 }
4210 /* Only allow this combination if insn_cost reports that the
4211 replacement instructions are cheaper than the originals. */
4213 {
4216 }
4219 {
4224 {
4229 /* Temporarily revert mode back. */
4233 {
4234 /* If we used i2dest as a scratch register with a
4235 different mode, substitute it for the original
4236 i2src while its original mode is temporarily
4237 restored, and then clear i2scratch so that we don't
4238 do it again later. */
4240 this_basic_block);
4242 /* Put back the new mode. */
4244 }
4245 else
4246 {
4251 {
4254 }
4255 else
4256 {
4263 }
4265 /* We're dealing with a reg that changed mode but not
4266 meaning, so we want to turn it into a subreg for
4267 the new mode. However, because of REG sharing and
4268 because its mode had already changed, we have to do
4269 it in two steps. First, replace any debug uses of
4270 reg, with its original mode temporarily restored,
4271 with this copy we have created; then, replace the
4272 copy with the SUBREG of the original shared reg,
4273 once again changed to the new mode. */
4275 this_basic_block);
4279 this_basic_block);
4280 }
4281 }
4282 }
4284 /* If we will be able to accept this, we have made a
4285 change to the destination of I3. This requires us to
4286 do a few adjustments. */
4289 {
4292 }
4294 /* We now know that we can do this combination. Merge the insns and
4295 update the status of registers and LOG_LINKS. */
4298 {
4303 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4304 ensure that they are still valid. Then add any non-duplicate
4305 notes added by recog_for_combine. */
4307 {
4316 /* Simply drop equal note since it may be no longer valid
4317 for other_insn. It may be possible to record that CC
4318 register is changed and only discard those notes, but
4319 in practice it's unnecessary complication and doesn't
4320 give any meaningful improvement.
4322 See PR78559. */
4326 }
4330 NULL_RTX);
4331 }
4334 {
4335 /* I3 now uses what used to be its destination and which is now
4336 I2's destination. This requires us to do a few adjustments. */
4339 }
4342 {
4343 /* We might need a LOG_LINK from I3 to I2. But then we used to
4344 have one, so we still will.
4346 However, some later insn might be using I2's dest and have
4347 a LOG_LINK pointing at I3. We should change it to point at
4348 I2 instead. */
4350 /* newi2pat is usually a SET here; however, recog_for_combine might
4351 have added some clobbers. */
4359 {
4364 !done
4365 && insn
4369 {
4373 {
4377 }
4378 }
4379 }
4380 }
4382 {
4387 /* Compute which registers we expect to eliminate. newi2pat may be setting
4388 either i3dest or i2dest, so we must check it. */
4391 || !i2dest_killed
4393 /* For i1, we need to compute both local elimination and global
4394 elimination information with respect to newi2pat because i1dest
4395 may be the same as i3dest, in which case newi2pat may be setting
4396 i1dest. Global information is used when distributing REG_DEAD
4397 note for i2 and i3, in which case it does matter if newi2pat sets
4398 i1dest or not.
4400 Local information is used when distributing REG_DEAD note for i1,
4401 in which case it doesn't matter if newi2pat sets i1dest or not.
4402 See PR62151, if we have four insns combination:
4403 i0: r0 <- i0src
4404 i1: r1 <- i1src (using r0)
4405 REG_DEAD (r0)
4406 i2: r0 <- i2src (using r1)
4407 i3: r3 <- i3src (using r0)
4408 ix: using r0
4409 From i1's point of view, r0 is eliminated, no matter if it is set
4410 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4411 should be discarded.
4413 Note local information only affects cases in forms like "I1->I2->I3",
4414 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4415 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4416 i0dest anyway. */
4418 || !i1dest_killed
4423 /* Same case as i1. */
4430 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4431 clear them. */
4439 /* Ensure that we do not have something that should not be shared but
4440 occurs multiple times in the new insns. Check this by first
4441 resetting all the `used' flags and then copying anything is shared. */
4465 {
4468 {
4470 {
4471 /* I2SRC must still be meaningful at this point. Some
4472 splitting operations can invalidate I2SRC, but those
4473 operations do not apply to calls. */
4477 }
4484 }
4485 }
4490 /* We had one special case above where I2 had more than one set and
4491 we replaced a destination of one of those sets with the destination
4492 of I3. In that case, we have to update LOG_LINKS of insns later
4493 in this basic block. Note that this (expensive) case is rare.
4495 Also, in this case, we must pretend that all REG_NOTEs for I2
4496 actually came from I3, so that REG_UNUSED notes from I2 will be
4497 properly handled. */
4500 {
4509 temp_insn
4519 {
4524 }
4525 else
4528 }
4536 {
4539 this_basic_block);
4542 }
4543 else
4544 {
4547 this_basic_block);
4549 }
4552 {
4557 this_basic_block);
4559 }
4562 {
4567 this_basic_block);
4569 }
4571 /* Get death notes for everything that is now used in either I3 or
4572 I2 and used to die in a previous insn. If we built two new
4573 patterns, move from I1 to I2 then I2 to I3 so that we get the
4574 proper movement on registers that I2 modifies. */
4580 else
4586 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4603 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4604 know these are REG_UNUSED and want them to go to the desired insn,
4605 so we always pass it as i3. */
4609 NULL_RTX);
4613 NULL_RTX);
4615 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4616 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4617 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4618 in that case, it might delete I2. Similarly for I2 and I1.
4619 Show an additional death due to the REG_DEAD note we make here. If
4620 we discard it in distribute_notes, we will decrement it again. */
4623 {
4628 else
4631 }
4634 {
4639 else
4642 }
4645 {
4650 else
4653 }
4656 {
4661 else
4664 }
4672 {
4677 /* The insn that used to set this register doesn't exist, and
4678 this life of the register may not exist either. See if one of
4679 I3's links points to an insn that sets I2DEST. If it does,
4680 that is now the last known value for I2DEST. If we don't update
4681 this and I2 set the register to a value that depended on its old
4682 contents, we will get confused. If this insn is used, thing
4683 will be set correctly in combine_instructions. */
4691 /* If the reg formerly set in I2 died only once and that was in I3,
4692 zero its use count so it won't make `reload' do any work. */
4695 && ! i2dest_in_i2src
4698 }
4701 {
4714 && ! i1dest_in_i1src
4717 }
4720 {
4733 && ! i0dest_in_i0src
4736 }
4738 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4739 been made to this insn. The order is important, because newi2pat
4740 can affect nonzero_bits of newpat. */
4744 }
4747 {
4749 {
4752 }
4754 }
4757 {
4759 {
4762 }
4764 }
4767 {
4769 {
4772 }
4774 }
4777 {
4779 {
4782 }
4784 }
4787 {
4789 {
4792 }
4794 }
4796 /* Set new_direct_jump_p if a new return or simple jump instruction
4797 has been created. Adjust the CFG accordingly. */
4799 {
4803 }
4808 {
4811 }
4815 {
4821 }
4826 {
4832 }
4834 /* A noop might also need cleaning up of CFG, if it comes from the
4835 simplification of a jump. */
4840 {
4843 }
4850 {
4853 }
4855 combine_successes++;
4865 }
4866 \f
4867 /* Get a marker for undoing to the current state. */
4871 {
4873 }
4875 /* Undo the modifications up to the marker. */
4877 static void
4879 {
4883 {
4888 {
4903 }
4907 }
4910 }
4912 /* Undo all the modifications recorded in undobuf. */
4914 static void
4916 {
4918 }
4920 /* We've committed to accepting the changes we made. Move all
4921 of the undos to the free list. */
4923 static void
4925 {
4929 {
4933 }
4935 }
4936 \f
4937 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4938 where we have an arithmetic expression and return that point. LOC will
4939 be inside INSN.
4941 try_combine will call this function to see if an insn can be split into
4942 two insns. */
4946 {
4956 /* First special-case some codes. */
4958 {
4960 #ifdef INSN_SCHEDULING
4961 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4962 point. */
4965 #endif
4969 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4970 using LO_SUM and HIGH. */
4973 {
4981 }
4983 /* If we have a PLUS whose second operand is a constant and the
4984 address is not valid, perhaps we can split it up using
4985 the machine-specific way to split large constants. We use
4986 the first pseudo-reg (one of the virtual regs) as a placeholder;
4987 it will not remain in the result. */
4992 {
4995 subst_insn);
4997 /* This should have produced two insns, each of which sets our
4998 placeholder. If the source of the second is a valid address,
4999 we can put both sources together and make a split point
5000 in the middle. */
5013 && memory_address_addr_space_p
5016 {
5020 /* Replace the placeholder in SRC2 with SRC1. If we can
5021 find where in SRC2 it was placed, that can become our
5022 split point and we can replace this address with SRC2.
5023 Just try two obvious places. */
5034 {
5037 }
5038 }
5040 /* If that didn't work and we have a nested plus, like:
5041 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
5042 is valid address, try to split (REG1 * CONST1). */
5049 {
5054 {
5057 }
5059 }
5066 {
5071 {
5074 }
5076 }
5078 /* If that didn't work, perhaps the first operand is complex and
5079 needs to be computed separately, so make a split point there.
5080 This will occur on machines that just support REG + CONST
5081 and have a constant moved through some previous computation. */
5086 }
5088 /* If we have a PLUS whose first operand is complex, try computing it
5089 separately by making a split there. */
5100 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
5101 ZERO_EXTRACT, the most likely reason why this doesn't match is that
5102 we need to put the operand into a register. So split at that
5103 point. */
5113 /* See if we can split SET_SRC as it stands. */
5118 /* See if we can split SET_DEST as it stands. */
5123 /* See if this is a bitfield assignment with everything constant. If
5124 so, this is an IOR of an AND, so split it into that. */
5136 {
5142 rtx or_mask;
5151 else
5152 {
5158 or_mask));
5159 }
5166 }
5168 /* Otherwise, see if this is an operation that we can split into two.
5169 If so, try to split that. */
5173 {
5175 /* If we are AND'ing with a large constant that is only a single
5176 bit and the result is only being used in a context where we
5177 need to know if it is zero or nonzero, replace it with a bit
5178 extraction. This will avoid the large constant, which might
5179 have taken more than one insn to make. If the constant were
5180 not a valid argument to the AND but took only one insn to make,
5181 this is no worse, but if it took more than one insn, it will
5182 be better. */
5192 {
5197 {
5200 }
5201 }
5205 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5206 is known to be on, this can be converted into a NEG of a shift. */
5212 {
5219 pos_rtx)));
5224 }
5230 /* We can't optimize if either mode is a partial integer
5231 mode as we don't know how many bits are significant
5232 in those modes. */
5248 {
5256 }
5261 }
5267 {
5268 /* For unsigned, we have a choice of a shift followed by an
5269 AND or two shifts. Use two shifts for field sizes where the
5270 constant might be too large. We assume here that we can
5271 always at least get 8-bit constants in an AND insn, which is
5272 true for every current RISC. */
5275 {
5276 unsigned HOST_WIDE_INT mask
5281 gen_rtx_LSHIFTRT
5288 }
5289 else
5290 {
5294 gen_rtx_fmt_ee
5304 }
5305 }
5307 /* See if this is a simple operation with a constant as the second
5308 operand. It might be that this constant is out of range and hence
5309 could be used as a split point. */
5317 /* Finally, see if this is a simple operation with its first operand
5318 not in a register. The operation might require this operand in a
5319 register, so return it as a split point. We can always do this
5320 because if the first operand were another operation, we would have
5321 already found it as a split point. */
5330 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5331 it is better to write this as (not (ior A B)) so we can split it.
5332 Similarly for IOR. */
5334 {
5342 }
5344 /* Many RISC machines have a large set of logical insns. If the
5345 second operand is a NOT, put it first so we will try to split the
5346 other operand first. */
5348 {
5352 }
5357 /* Canonicalization can produce (minus A (mult B C)), where C is a
5358 constant. It may be better to try splitting (plus (mult B -C) A)
5359 instead if this isn't a multiply by a power of two. */
5363 {
5371 mode)),
5374 }
5376 /* Split at a multiply-accumulate instruction. However if this is
5377 the SET_SRC, we likely do not have such an instruction and it's
5378 worthless to try this split. */
5387 }
5389 /* Otherwise, select our actions depending on our rtx class. */
5391 {
5397 /* fall through */
5405 /* fall through */
5407 /* Some machines have (and (shift ...) ...) insns. If X is not
5408 an AND, but XEXP (X, 0) is, use it as our split point. */
5418 /* Otherwise, we don't have a split point. */
5420 }
5421 }
5422 \f
5423 /* Throughout X, replace FROM with TO, and return the result.
5424 The result is TO if X is FROM;
5425 otherwise the result is X, but its contents may have been modified.
5426 If they were modified, a record was made in undobuf so that
5427 undo_all will (among other things) return X to its original state.
5429 If the number of changes necessary is too much to record to undo,
5430 the excess changes are not made, so the result is invalid.
5431 The changes already made can still be undone.
5432 undobuf.num_undo is incremented for such changes, so by testing that
5433 the caller can tell whether the result is valid.
5435 `n_occurrences' is incremented each time FROM is replaced.
5437 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5439 IN_COND is nonzero if we are at the top level of a condition.
5441 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5442 by copying if `n_occurrences' is nonzero. */
5444 static rtx
5446 {
5451 rtx new_rtx;
5453 /* Two expressions are equal if they are identical copies of a shared
5454 RTX or if they are both registers with the same register number
5455 and mode. */
5457 #define COMBINE_RTX_EQUAL_P(X,Y) \
5458 ((X) == (Y) \
5459 || (REG_P (X) && REG_P (Y) \
5460 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5462 /* Do not substitute into clobbers of regs -- this will never result in
5463 valid RTL. */
5468 {
5469 n_occurrences++;
5471 }
5473 /* If X and FROM are the same register but different modes, they
5474 will not have been seen as equal above. However, the log links code
5475 will make a LOG_LINKS entry for that case. If we do nothing, we
5476 will try to rerecognize our original insn and, when it succeeds,
5477 we will delete the feeding insn, which is incorrect.
5479 So force this insn not to match in this (rare) case. */
5484 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5485 of which may contain things that can be combined. */
5489 /* It is possible to have a subexpression appear twice in the insn.
5490 Suppose that FROM is a register that appears within TO.
5491 Then, after that subexpression has been scanned once by `subst',
5492 the second time it is scanned, TO may be found. If we were
5493 to scan TO here, we would find FROM within it and create a
5494 self-referent rtl structure which is completely wrong. */
5498 /* Parallel asm_operands need special attention because all of the
5499 inputs are shared across the arms. Furthermore, unsharing the
5500 rtl results in recognition failures. Failure to handle this case
5501 specially can result in circular rtl.
5503 Solve this by doing a normal pass across the first entry of the
5504 parallel, and only processing the SET_DESTs of the subsequent
5505 entries. Ug. */
5510 {
5513 /* If this substitution failed, this whole thing fails. */
5521 {
5527 {
5530 /* If this substitution failed, this whole thing fails. */
5536 }
5537 }
5538 }
5539 else
5540 {
5544 /* We don't need to process a SET_DEST that is a register, CC0,
5545 or PC, so set up to skip this common case. All other cases
5546 where we want to suppress replacing something inside a
5547 SET_SRC are handled via the IN_DEST operand. */
5554 /* Trying to simplify the operands of a widening MULT is not likely
5555 to create RTL matching a machine insn. */
5567 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5568 constant. */
5573 {
5575 {
5578 {
5580 {
5583 n_occurrences++;
5584 }
5585 else
5586 {
5588 unique_copy);
5590 /* If this substitution failed, this whole thing
5591 fails. */
5595 }
5598 }
5599 }
5601 {
5602 /* If this is a register being set, ignore it. */
5609 ;
5612 {
5613 /* In general, don't install a subreg involving two
5614 modes not tieable. It can worsen register
5615 allocation, and can even make invalid reload
5616 insns, since the reg inside may need to be copied
5617 from in the outside mode, and that may be invalid
5618 if it is an fp reg copied in integer mode.
5620 We allow two exceptions to this: It is valid if
5621 it is inside another SUBREG and the mode of that
5622 SUBREG and the mode of the inside of TO is
5623 tieable and it is valid if X is a SET that copies
5624 FROM to CC0. */
5632 && (!HAVE_cc0
5647 n_occurrences++;
5648 }
5649 else
5650 /* If we are in a SET_DEST, suppress most cases unless we
5651 have gone inside a MEM, in which case we want to
5652 simplify the address. We assume here that things that
5653 are actually part of the destination have their inner
5654 parts in the first expression. This is true for SUBREG,
5655 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5656 things aside from REG and MEM that should appear in a
5657 SET_DEST. */
5659 (((in_dest
5665 unique_copy);
5667 /* If we found that we will have to reject this combination,
5668 indicate that by returning the CLOBBER ourselves, rather than
5669 an expression containing it. This will speed things up as
5670 well as prevent accidents where two CLOBBERs are considered
5671 to be equal, thus producing an incorrect simplification. */
5677 {
5685 }
5691 {
5693 new_rtx,
5697 }
5698 else
5700 }
5701 }
5702 }
5704 /* Check if we are loading something from the constant pool via float
5705 extension; in this case we would undo compress_float_constant
5706 optimization and degenerate constant load to an immediate value. */
5710 {
5714 }
5716 /* Try to simplify X. If the simplification changed the code, it is likely
5717 that further simplification will help, so loop, but limit the number
5718 of repetitions that will be performed. */
5721 {
5722 /* If X is sufficiently simple, don't bother trying to do anything
5723 with it. */
5732 /* We no longer know the original mode of operand 0 since we
5733 have changed the form of X) */
5735 }
5738 }
5739 \f
5740 /* If X is a commutative operation whose operands are not in the canonical
5741 order, use substitutions to swap them. */
5743 static void
5745 {
5748 {
5752 }
5753 }
5755 /* Simplify X, a piece of RTL. We just operate on the expression at the
5756 outer level; call `subst' to simplify recursively. Return the new
5757 expression.
5759 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5760 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5761 of a condition. */
5763 static rtx
5766 {
5769 scalar_int_mode int_mode;
5770 rtx temp;
5773 /* If this is a commutative operation, put a constant last and a complex
5774 expression first. We don't need to do this for comparisons here. */
5777 /* Try to fold this expression in case we have constants that weren't
5778 present before. */
5781 {
5789 {
5792 {
5796 }
5799 }
5812 }
5815 {
5820 }
5822 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5823 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5824 things. Check for cases where both arms are testing the same
5825 condition.
5827 Don't do anything if all operands are very simple. */
5840 {
5845 /* If everything is a comparison, what we have is highly unlikely
5846 to be simpler, so don't use it. */
5849 /* Similarly, if we end up with one of the expressions the same
5850 as the original, it is certainly not simpler. */
5853 {
5860 /* Simplify the alternative arms; this may collapse the true and
5861 false arms to store-flag values. Be careful to use copy_rtx
5862 here since true_rtx or false_rtx might share RTL with x as a
5863 result of the if_then_else_cond call above. */
5867 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5868 is unlikely to be simpler. */
5871 {
5874 /* Restarting if we generate a store-flag expression will cause
5875 us to loop. Just drop through in this case. */
5877 /* If the result values are STORE_FLAG_VALUE and zero, we can
5878 just make the comparison operation. */
5889 /* Likewise, we can make the negate of a comparison operation
5890 if the result values are - STORE_FLAG_VALUE and zero. */
5898 mode);
5909 mode);
5913 }
5914 }
5915 }
5917 /* First see if we can apply the inverse distributive law. */
5920 {
5924 }
5926 /* If CODE is an associative operation not otherwise handled, see if we
5927 can associate some operands. This can win if they are constants or
5928 if they are logically related (i.e. (a & b) & a). */
5934 {
5936 {
5940 rtx inner;
5942 /* Make sure we pass the constant operand if any as the second
5943 one if this is a commutative operation. */
5951 /* For commutative operations, try the other pair if that one
5952 didn't simplify. */
5954 {
5959 }
5963 }
5964 }
5966 /* A little bit of algebraic simplification here. */
5968 {
5970 /* Ensure that our address has any ASHIFTs converted to MULT in case
5971 address-recognizing predicates are called later. */
5980 /* See if this can be moved to simplify_subreg. */
5983 /* Don't call gen_lowpart if the inner mode
5984 is VOIDmode and we cannot simplify it, as SUBREG without
5985 inner mode is invalid. */
5992 {
5993 rtx temp;
5999 /* If op is known to have all lower bits zero, the result is zero. */
6013 }
6015 /* Don't change the mode of the MEM if that would change the meaning
6016 of the address. */
6023 /* Note that we cannot do any narrowing for non-constants since
6024 we might have been counting on using the fact that some bits were
6025 zero. We now do this in the SET. */
6032 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
6033 replaced by (lshiftrt X C). This will convert
6034 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
6042 /* If X has only a single bit that might be nonzero, say, bit I, convert
6043 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
6044 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
6045 (sign_extract X 1 Y). But only do this if TEMP isn't a register
6046 or a SUBREG of one since we'd be making the expression more
6047 complex if it was just a register. */
6054 {
6055 rtx temp1 = simplify_shift_const
6061 /* If all we did was surround TEMP with the two shifts, we
6062 haven't improved anything, so don't use it. Otherwise,
6063 we are better off with TEMP1. */
6068 }
6072 /* We can't handle truncation to a partial integer mode here
6073 because we don't know the real bitsize of the partial
6074 integer mode. */
6083 /* We can truncate a constant value and return it. */
6084 {
6085 poly_int64 c;
6088 }
6090 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
6091 whose value is a comparison can be replaced with a subreg if
6092 STORE_FLAG_VALUE permits. */
6101 /* (const (const X)) can become (const X). Do it this way rather than
6102 returning the inner CONST since CONST can be shared with a
6103 REG_EQUAL note. */
6109 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6110 can add in an offset. find_split_point will split this address up
6111 again if it doesn't match. */
6118 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6119 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6120 bit-field and can be replaced by either a sign_extend or a
6121 sign_extract. The `and' may be a zero_extend and the two
6122 <c>, -<c> constants may be reversed. */
6139 return simplify_shift_const
6146 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6147 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6148 the bitsize of the mode - 1. This allows simplification of
6149 "a = (b & 8) == 0;" */
6156 return simplify_shift_const
6160 const1_rtx),
6164 /* If we are adding two things that have no bits in common, convert
6165 the addition into an IOR. This will often be further simplified,
6166 for example in cases like ((a & 1) + (a & 2)), which can
6167 become a & 3. */
6172 {
6173 /* Try to simplify the expression further. */
6177 /* If we could, great. If not, do not go ahead with the IOR
6178 replacement, since PLUS appears in many special purpose
6179 address arithmetic instructions. */
6187 }
6189 /* Canonicalize x + x into x << 1. */
6198 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6199 (and <foo> (const_int pow2-1)) */
6210 /* If we have (mult (plus A B) C), apply the distributive law and then
6211 the inverse distributive law to see if things simplify. This
6212 occurs mostly in addresses, often when unrolling loops. */
6215 {
6219 }
6221 /* Try simplify a*(b/c) as (a*b)/c. */
6224 {
6230 }
6234 /* If this is a divide by a power of two, treat it as a shift if
6235 its first operand is a shift. */
6255 /* If the first operand is a condition code, we can't do anything
6256 with it. */
6260 {
6268 /* Simplify our comparison, if possible. */
6271 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6272 if only the low-order bit is possibly nonzero in X (such as when
6273 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6274 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6275 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6276 (plus X 1).
6278 Remove any ZERO_EXTRACT we made when thinking this was a
6279 comparison. It may now be simpler to use, e.g., an AND. If a
6280 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6281 the call to make_compound_operation in the SET case.
6283 Don't apply these optimizations if the caller would
6284 prefer a comparison rather than a value.
6285 E.g., for the condition in an IF_THEN_ELSE most targets need
6286 an explicit comparison. */
6289 ;
6307 {
6311 int_mode);
6312 }
6320 {
6324 const1_rtx);
6325 }
6334 {
6337 }
6339 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6340 those above. */
6342 ;
6359 {
6363 int_mode);
6364 }
6373 {
6377 int_mode);
6378 }
6380 /* If X is 0/1, (eq X 0) is X-1. */
6387 {
6390 }
6392 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6393 one bit that might be nonzero, we can convert (ne x 0) to
6394 (ashift x c) where C puts the bit in the sign bit. Remove any
6395 AND with STORE_FLAG_VALUE when we are done, since we are only
6396 going to test the sign bit. */
6404 {
6410 else
6412 }
6414 /* If the code changed, return a whole new comparison.
6415 We also need to avoid using SUBST in cases where
6416 simplify_comparison has widened a comparison with a CONST_INT,
6417 since in that case the wider CONST_INT may fail the sanity
6418 checks in do_SUBST. */
6425 /* Otherwise, keep this operation, but maybe change its operands.
6426 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6429 }
6439 /* If we are processing SET_DEST, we are done. */
6457 /* If this is a shift by a constant amount, simplify it. */
6465 (HOST_WIDE_INT_1U
6474 }
6477 }
6478 \f
6479 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6481 static rtx
6483 {
6490 rtx temp;
6493 rtx reversed;
6496 /* Simplify storing of the truth value. */
6501 /* Also when the truth value has to be reversed. */
6507 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6508 in it is being compared against certain values. Get the true and false
6509 comparisons and see if that says anything about the value of each arm. */
6515 {
6516 HOST_WIDE_INT nzb;
6522 /* If FALSE_CODE is EQ, swap the codes and arms. */
6525 {
6528 }
6530 scalar_int_mode from_mode;
6532 {
6533 /* If we are comparing against zero and the expression being
6534 tested has only a single bit that might be nonzero, that is
6535 its value when it is not equal to zero. Similarly if it is
6536 known to be -1 or 0. */
6540 {
6543 }
6548 {
6551 }
6552 }
6554 /* Now simplify an arm if we know the value of the register in the
6555 branch and it is used in the arm. Be careful due to the potential
6556 of locally-shared RTL. */
6573 }
6575 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6576 reversed, do so to avoid needing two sets of patterns for
6577 subtract-and-branch insns. Similarly if we have a constant in the true
6578 arm, the false arm is the same as the first operand of the comparison, or
6579 the false arm is more complicated than the true arm. */
6592 {
6600 /* It is possible that the conditional has been simplified out. */
6603 }
6605 /* If the two arms are identical, we don't need the comparison. */
6610 /* Convert a == b ? b : a to "a". */
6622 /* Look for cases where we have (abs x) or (neg (abs X)). */
6625 && comparison_p
6632 {
6638 return
6641 mode);
6644 }
6646 /* Look for MIN or MAX. */
6649 || (flag_unsafe_math_optimizations
6652 && comparison_p
6657 {
6672 }
6674 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6675 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6676 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6677 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6678 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6679 neither 1 or -1, but it isn't worth checking for. */
6682 && comparison_p
6685 {
6701 /* If an identity-zero op is commutative, check whether there
6702 would be a match if we swapped the operands. */
6723 {
6727 }
6740 {
6744 }
6761 {
6765 }
6778 {
6782 }
6785 {
6795 const_true_rtx));
6803 }
6804 }
6806 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6807 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6808 negation of a single bit, we can convert this operation to a shift. We
6809 can actually do this more generally, but it doesn't seem worth it. */
6821 return
6825 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6826 non-zero bit in A is C1. */
6834 {
6840 }
6843 }
6844 \f
6845 /* Simplify X, a SET expression. Return the new expression. */
6847 static rtx
6849 {
6852 machine_mode mode
6856 scalar_int_mode int_mode;
6858 /* (set (pc) (return)) gets written as (return). */
6862 /* Now that we know for sure which bits of SRC we are using, see if we can
6863 simplify the expression for the object knowing that we only need the
6864 low-order bits. */
6867 {
6870 }
6872 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6873 the comparison result and try to simplify it unless we already have used
6874 undobuf.other_insn. */
6882 {
6891 {
6894 {
6897 }
6898 }
6899 else
6907 {
6911 }
6912 else
6913 {
6918 /* Attempt to simplify CC user. */
6920 {
6924 }
6926 /* Convert X into a no-op move. */
6930 }
6932 /* Simplify our comparison, if possible. */
6935 #ifdef SELECT_CC_MODE
6936 /* If this machine has CC modes other than CCmode, check to see if we
6937 need to use a different CC mode here. */
6946 else
6949 /* If the mode changed, we have to change SET_DEST, the mode in the
6950 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6951 a hard register, just build new versions with the proper mode. If it
6952 is a pseudo, we lose unless it is only time we set the pseudo, in
6953 which case we can safely change its mode. */
6955 {
6957 {
6959 rtx new_dest;
6963 else
6964 {
6967 }
6974 }
6975 }
6978 /* If the code changed, we have to build a new comparison in
6979 undobuf.other_insn. */
6981 {
6990 /* If the only change we made was to change an EQ into an NE or
6991 vice versa, OP0 has only one bit that might be nonzero, and OP1
6992 is zero, check if changing the user of the condition code will
6993 produce a valid insn. If it won't, we can keep the original code
6994 in that insn by surrounding our operation with an XOR. */
7001 {
7006 {
7013 }
7014 }
7015 }
7020 /* Don't generate a compare of a CC with 0, just use that CC. */
7022 {
7025 }
7026 /* Otherwise, if we didn't previously have the same COMPARE we
7027 want, create it from scratch. */
7030 {
7033 }
7034 }
7035 else
7036 {
7037 /* Get SET_SRC in a form where we have placed back any
7038 compound expressions. Then do the checks below. */
7041 }
7043 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
7044 and X being a REG or (subreg (reg)), we may be able to convert this to
7045 (set (subreg:m2 x) (op)).
7047 We can always do this if M1 is narrower than M2 because that means that
7048 we only care about the low bits of the result.
7050 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
7051 perform a narrower operation than requested since the high-order bits will
7052 be undefined. On machine where it is defined, this transformation is safe
7053 as long as M1 and M2 have the same number of words. */
7057 && (known_equal_after_align_up
7060 UNITS_PER_WORD))
7069 {
7072 dest));
7076 }
7078 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
7079 in SRC. */
7083 {
7087 /* Here we make sure that we don't have a sign bit on. */
7090 {
7093 }
7094 }
7096 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7097 would require a paradoxical subreg. Replace the subreg with a
7098 zero_extend to avoid the reload that would otherwise be required.
7099 Don't do this unless we have a scalar integer mode, otherwise the
7100 transformation is incorrect. */
7107 {
7112 }
7114 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7115 are comparing an item known to be 0 or -1 against 0, use a logical
7116 operation instead. Check for one of the arms being an IOR of the other
7117 arm with some value. We compute three terms to be IOR'ed together. In
7118 practice, at most two will be nonzero. Then we do the IOR's. */
7126 && (!HAVE_conditional_move
7131 {
7156 int_mode),
7157 false_rtx);
7163 term3));
7166 }
7168 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7169 whole thing fail. */
7174 else
7175 /* Convert this into a field assignment operation, if possible. */
7177 }
7178 \f
7179 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7180 result. */
7182 static rtx
7184 {
7187 scalar_int_mode mode;
7190 {
7192 /* We can call simplify_and_const_int only if we don't lose
7193 any (sign) bits when converting INTVAL (op1) to
7194 "unsigned HOST_WIDE_INT". */
7199 {
7206 }
7208 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7209 apply the distributive law and then the inverse distributive
7210 law to see if things simplify. */
7212 {
7216 }
7218 {
7222 }
7226 /* If we have (ior (and A B) C), apply the distributive law and then
7227 the inverse distributive law to see if things simplify. */
7230 {
7234 }
7237 {
7241 }
7246 }
7249 }
7250 \f
7251 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7252 operations" because they can be replaced with two more basic operations.
7253 ZERO_EXTEND is also considered "compound" because it can be replaced with
7254 an AND operation, which is simpler, though only one operation.
7256 The function expand_compound_operation is called with an rtx expression
7257 and will convert it to the appropriate shifts and AND operations,
7258 simplifying at each stage.
7260 The function make_compound_operation is called to convert an expression
7261 consisting of shifts and ANDs into the equivalent compound expression.
7262 It is the inverse of this function, loosely speaking. */
7264 static rtx
7266 {
7270 rtx tem;
7271 scalar_int_mode inner_mode;
7274 {
7277 /* FALLTHRU */
7279 /* We can't necessarily use a const_int for a multiword mode;
7280 it depends on implicitly extending the value.
7281 Since we don't know the right way to extend it,
7282 we can't tell whether the implicit way is right.
7284 Even for a mode that is no wider than a const_int,
7285 we can't win, because we need to sign extend one of its bits through
7286 the rest of it, and we don't know which bit. */
7290 /* Reject modes that aren't scalar integers because turning vector
7291 or complex modes into shifts causes problems. */
7295 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7296 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7297 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7298 reloaded. If not for that, MEM's would very rarely be safe.
7300 Reject modes bigger than a word, because we might not be able
7301 to reference a two-register group starting with an arbitrary register
7302 (and currently gen_lowpart might crash for a SUBREG). */
7308 /* If the inner object has VOIDmode (the only way this can happen
7309 is if it is an ASM_OPERANDS), we can't do anything since we don't
7310 know how much masking to do. */
7319 /* fall through */
7322 /* If the operand is a CLOBBER, just return it. */
7330 /* Reject modes that aren't scalar integers because turning vector
7331 or complex modes into shifts causes problems. */
7338 /* This should stay within the object being extracted, fail otherwise. */
7349 }
7351 /* We've rejected non-scalar operations by now. */
7354 /* Convert sign extension to zero extension, if we know that the high
7355 bit is not set, as this is easier to optimize. It will be converted
7356 back to cheaper alternative in make_extraction. */
7362 {
7366 /* Make sure this is a profitable operation. */
7373 else
7375 }
7377 /* We can optimize some special cases of ZERO_EXTEND. */
7379 {
7380 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7381 know that the last value didn't have any inappropriate bits
7382 set. */
7390 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7399 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7400 is a comparison and STORE_FLAG_VALUE permits. This is like
7401 the first case, but it works even when MODE is larger
7402 than HOST_WIDE_INT. */
7410 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7419 }
7421 /* If we reach here, we want to return a pair of shifts. The inner
7422 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7423 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7424 logical depending on the value of UNSIGNEDP.
7426 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7427 converted into an AND of a shift.
7429 We must check for the case where the left shift would have a negative
7430 count. This can happen in a case like (x >> 31) & 255 on machines
7431 that can't shift by a constant. On those machines, we would first
7432 combine the shift with the AND to produce a variable-position
7433 extraction. Then the constant of 31 would be substituted in
7434 to produce such a position. */
7438 {
7446 }
7451 pos),
7453 else
7454 /* Any other cases we can't handle. */
7457 /* If we couldn't do this for some reason, return the original
7458 expression. */
7463 }
7464 \f
7465 /* X is a SET which contains an assignment of one object into
7466 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7467 or certain SUBREGS). If possible, convert it into a series of
7468 logical operations.
7470 We half-heartedly support variable positions, but do not at all
7471 support variable lengths. */
7473 static const_rtx
7475 {
7476 rtx inner;
7480 scalar_int_mode compute_mode;
7482 /* Loop until we find something we can't simplify. */
7484 {
7487 {
7493 MAX_MODE_INT);
7494 }
7497 {
7505 /* A constant position should stay within the width of INNER. */
7510 {
7516 /* If position is ADJUST - X, new position is X. */
7518 else
7522 pos);
7523 }
7524 }
7526 /* If the destination is a subreg that overwrites the whole of the inner
7527 register, we can move the subreg to the source. */
7529 /* We need SUBREGs to compute nonzero_bits properly. */
7530 && nonzero_sign_valid
7532 {
7534 gen_lowpart
7538 }
7539 else
7545 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7547 {
7548 /* Don't do anything for vector or complex integral types. */
7552 /* Try to find an integral mode to pun with. */
7558 }
7560 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7564 /* Don't try to compute in too wide unsupported modes. */
7568 /* Now compute the equivalent expression. Make a copy of INNER
7569 for the SET_DEST in case it is a MEM into which we will substitute;
7570 we don't want shared RTL in that case. */
7572 compute_mode);
7576 compute_mode,
7578 compute_mode),
7579 inner);
7584 mask),
7585 pos);
7590 }
7593 }
7594 \f
7595 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7596 it is an RTX that represents the (variable) starting position; otherwise,
7597 POS is the (constant) starting bit position. Both are counted from the LSB.
7599 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7601 IN_DEST is nonzero if this is a reference in the destination of a SET.
7602 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7603 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7604 be used.
7606 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7607 ZERO_EXTRACT should be built even for bits starting at bit 0.
7609 MODE is the desired mode of the result (if IN_DEST == 0).
7611 The result is an RTX for the extraction or NULL_RTX if the target
7612 can't handle it. */
7614 static rtx
7618 {
7619 /* This mode describes the size of the storage area
7620 to fetch the overall value from. Within that, we
7621 ignore the POS lowest bits, etc. */
7623 machine_mode inner_mode;
7624 scalar_int_mode wanted_inner_mode;
7630 HOST_WIDE_INT orig_pos;
7638 /* If trying or potentionally trying to extract
7639 bits outside of is_mode, don't look through
7640 non-paradoxical SUBREGs. See PR82192. */
7643 {
7644 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7645 consider just the QI as the memory to extract from.
7646 The subreg adds or removes high bits; its mode is
7647 irrelevant to the meaning of this extraction,
7648 since POS and LEN count from the lsb. */
7652 }
7657 {
7658 /* We're extracting the least significant bits of an rtx
7659 (ashift X (const_int C)), where LEN > C. Extract the
7660 least significant (LEN - C) bits of X, giving an rtx
7661 whose mode is MODE, then shift it left C times. */
7667 }
7671 {
7672 /* We're extracting the least significant bits of an rtx
7673 (mult X (const_int 2^C)), where LEN > C. Extract the
7674 least significant (LEN - C) bits of X, giving an rtx
7675 whose mode is MODE, then multiply it by 2^C. */
7678 {
7684 }
7685 }
7687 /* If trying or potentionally trying to extract
7688 bits outside of is_mode, don't look through
7689 TRUNCATE. See PR82192. */
7696 /* See if this can be done without an extraction. We never can if the
7697 width of the field is not the same as that of some integer mode. For
7698 registers, we can only avoid the extraction if the position is at the
7699 low-order bit and this is either not in the destination or we have the
7700 appropriate STRICT_LOW_PART operation available.
7702 For MEM, we can avoid an extract if the field starts on an appropriate
7703 boundary and we can change the mode of the memory reference. */
7705 scalar_int_mode tmode;
7714 && (! in_dest
7718 && (pos
7721 /* We can't do this if we are widening INNER_MODE (it
7722 may not be aligned, for one thing). */
7729 {
7730 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7731 field. If the original and current mode are the same, we need not
7732 adjust the offset. Otherwise, we do if bytes big endian.
7734 If INNER is not a MEM, get a piece consisting of just the field
7735 of interest (in this case POS % BITS_PER_WORD must be 0). */
7738 {
7739 poly_int64 offset;
7741 /* POS counts from lsb, but make OFFSET count in memory order. */
7745 else
7749 }
7751 {
7753 {
7754 /* We can't call gen_lowpart in a DEST since we
7755 always want a SUBREG (see below) and it would sometimes
7756 return a new hard register. */
7758 {
7759 poly_uint64 offset
7762 /* Avoid creating invalid subregs, for example when
7763 simplifying (x>>32)&255. */
7768 }
7769 else
7771 }
7772 else
7774 }
7775 else
7777 len >= HOST_BITS_PER_WIDE_INT
7778 ? HOST_WIDE_INT_M1U
7781 /* If this extraction is going into the destination of a SET,
7782 make a STRICT_LOW_PART unless we made a MEM. */
7797 /* If we know that no extraneous bits are set, and that the high
7798 bit is not set, convert the extraction to the cheaper of
7799 sign and zero extension, that are equivalent in these cases. */
7805 {
7809 /* Prefer ZERO_EXTENSION, since it gives more information to
7810 backends. */
7815 }
7817 /* Otherwise, sign- or zero-extend unless we already are in the
7818 proper mode. */
7822 }
7824 /* Unless this is a COMPARE or we have a funny memory reference,
7825 don't do anything with zero-extending field extracts starting at
7826 the low-order bit since they are simple AND operations. */
7831 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7832 if the position is not a constant and the length is not 1. In all
7833 other cases, we would only be going outside our object in cases when
7834 an original shift would have been undefined. */
7843 /* If INNER is not from memory, we want it to have the mode of a register
7844 extraction pattern's structure operand, or word_mode if there is no
7845 such pattern. The same applies to extraction_mode and pos_mode
7846 and their respective operands.
7848 For memory, assume that the desired extraction_mode and pos_mode
7849 are the same as for a register operation, since at present we don't
7850 have named patterns for aligned memory structures. */
7855 {
7859 }
7861 /* Never narrow an object, since that might not be safe. */
7867 /* Punt if len is too large for extraction_mode. */
7873 else
7874 {
7875 /* Be careful not to go beyond the extracted object and maintain the
7876 natural alignment of the memory. */
7881 }
7886 {
7887 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7888 BITS_BIG_ENDIAN style. If position is constant, compute new
7889 position. Otherwise, build subtraction.
7890 Note that POS is relative to the mode of the original argument.
7891 If it's a MEM we need to recompute POS relative to that.
7892 However, if we're extracting from (or inserting into) a register,
7893 we want to recompute POS relative to wanted_inner_mode. */
7902 else
7903 pos_rtx
7906 pos_rtx);
7907 /* POS may be less than 0 now, but we check for that below.
7908 Note that it can only be less than 0 if !MEM_P (inner). */
7909 }
7911 /* If INNER has a wider mode, and this is a constant extraction, try to
7912 make it smaller and adjust the byte to point to the byte containing
7913 the value. */
7916 && ! pos_rtx
7921 {
7924 /* The computations below will be correct if the machine is big
7925 endian in both bits and bytes or little endian in bits and bytes.
7926 If it is mixed, we must adjust. */
7928 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7929 adjust OFFSET to compensate. */
7934 /* We can now move to the desired byte. */
7945 }
7947 /* If INNER is not memory, get it into the proper mode. If we are changing
7948 its mode, POS must be a constant and smaller than the size of the new
7949 mode. */
7951 {
7952 /* On the LHS, don't create paradoxical subregs implicitely truncating
7953 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7956 wanted_inner_mode))
7968 pos_rtx
7970 ? HOST_WIDE_INT_M1U
7974 }
7976 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7977 have to zero extend. Otherwise, we can just use a SUBREG.
7979 We dealt with constant rtxes earlier, so pos_rtx cannot
7980 have VOIDmode at this point. */
7984 {
7988 /* If we know that no extraneous bits are set, and that the high
7989 bit is not set, convert extraction to cheaper one - either
7990 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7991 cases. */
7999 {
8003 /* Prefer ZERO_EXTENSION, since it gives more information to
8004 backends. */
8008 }
8010 }
8012 /* Make POS_RTX unless we already have it and it is correct. If we don't
8013 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
8014 be a CONST_INT. */
8021 /* Make the required operation. See if we can use existing rtx. */
8028 }
8029 \f
8030 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
8031 can be commuted with any other operations in X. Return X without
8032 that shift if so. */
8034 static rtx
8036 {
8038 rtx tem;
8041 {
8043 /* This is the shift itself. If it is wide enough, we will return
8044 either the value being shifted if the shift count is equal to
8045 COUNT or a shift for the difference. */
8059 /* If we can safely shift this constant and we find the inner shift,
8060 make a new operation. */
8065 {
8069 }
8074 }
8077 }
8078 \f
8079 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
8080 level of the expression and MODE is its mode. IN_CODE is as for
8081 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
8082 that should be used when recursing on operands of *X_PTR.
8084 There are two possible actions:
8086 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
8087 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
8089 - Return a new rtx, which the caller returns directly. */
8091 static rtx
8095 {
8103 rtx tem;
8104 scalar_int_mode inner_mode;
8108 {
8111 }
8113 /* Process depending on the code of this operation. If NEW is set
8114 nonzero, it will be returned. */
8117 {
8119 /* Convert shifts by constants into multiplications if inside
8120 an address. */
8124 {
8130 {
8133 }
8136 }
8145 {
8149 }
8152 {
8156 mode));
8158 }
8159 else
8160 {
8163 }
8173 {
8177 }
8180 {
8184 mode));
8186 }
8187 else
8188 {
8192 }
8195 /* If the second operand is not a constant, we can't do anything
8196 with it. */
8200 /* If the constant is a power of two minus one and the first operand
8201 is a logical right shift, make an extraction. */
8204 {
8208 }
8210 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8217 {
8224 /* If we narrowed the mode when dropping the subreg, then we lose. */
8228 /* If that didn't give anything, see if the AND simplifies on
8229 its own. */
8231 {
8235 }
8236 }
8237 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8243 {
8244 /* Apply the distributive law, and then try to make extractions. */
8251 }
8253 /* If we are have (and (rotate X C) M) and C is larger than the number
8254 of bits in M, this is an extraction. */
8260 {
8266 }
8268 /* On machines without logical shifts, if the operand of the AND is
8269 a logical shift and our mask turns off all the propagated sign
8270 bits, we can replace the logical shift with an arithmetic shift. */
8278 {
8288 next_code),
8290 }
8292 /* If the constant is one less than a power of two, this might be
8293 representable by an extraction even if no shift is present.
8294 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8295 we are in a COMPARE. */
8299 next_code),
8302 /* If we are in a comparison and this is an AND with a power of two,
8303 convert this into the appropriate bit extract. */
8309 next_code),
8312 /* If the one operand is a paradoxical subreg of a register or memory and
8313 the constant (limited to the smaller mode) has only zero bits where
8314 the sub expression has known zero bits, this can be expressed as
8315 a zero_extend. */
8317 {
8318 rtx sub;
8326 {
8330 /* original AND constant with all the known zero bits set */
8333 {
8337 }
8338 }
8339 }
8344 /* If the sign bit is known to be zero, replace this with an
8345 arithmetic shift. */
8350 {
8353 next_code),
8356 }
8358 /* fall through */
8364 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8365 this is a SIGN_EXTRACT. */
8372 {
8379 }
8381 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8382 If so, try to merge the shifts into a SIGN_EXTEND. We could
8383 also do this for some cases of SIGN_EXTRACT, but it doesn't
8384 seem worth the effort; the case checked for occurs on Alpha. */
8395 next_code),
8402 /* Call ourselves recursively on the inner expression. If we are
8403 narrowing the object and it has a different RTL code from
8404 what it originally did, do this SUBREG as a force_to_mode. */
8405 {
8409 /* If the SUBREG is masking of a logical right shift,
8410 make an extraction. */
8417 {
8426 }
8428 /* If in_code is COMPARE, it isn't always safe to pass it through
8429 to the recursive make_compound_operation call. */
8433 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8434 is (const_int 0), rather than
8435 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8436 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8437 for non-equality comparisons against 0 is not equivalent
8438 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8448 simplified
8456 {
8457 rtx newer
8460 /* If we have something other than a SUBREG, we might have
8461 done an expansion, so rerun ourselves. */
8465 /* force_to_mode can expand compounds. If it just re-expanded
8466 the compound, use gen_lowpart to convert to the desired
8467 mode. */
8469 /* Likewise if it re-expanded the compound only partially.
8470 This happens for SUBREG of ZERO_EXTRACT if they extract
8471 the same number of bits. */
8480 }
8484 }
8489 }
8495 }
8497 /* Look at the expression rooted at X. Look for expressions
8498 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8499 Form these expressions.
8501 Return the new rtx, usually just X.
8503 Also, for machines like the VAX that don't have logical shift insns,
8504 try to convert logical to arithmetic shift operations in cases where
8505 they are equivalent. This undoes the canonicalizations to logical
8506 shifts done elsewhere.
8508 We try, as much as possible, to re-use rtl expressions to save memory.
8510 IN_CODE says what kind of expression we are processing. Normally, it is
8511 SET. In a memory address it is MEM. When processing the arguments of
8512 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8513 precisely it is an equality comparison against zero. */
8515 rtx
8517 {
8524 /* Select the code to be used in recursive calls. Once we are inside an
8525 address, we stay there. If we have a comparison, set to COMPARE,
8526 but once inside, go back to our default of SET. */
8533 scalar_int_mode mode;
8535 {
8541 }
8543 /* Now recursively process each operand of this operation. We need to
8544 handle ZERO_EXTEND specially so that we don't lose track of the
8545 inner mode. */
8547 {
8555 }
8560 {
8563 }
8566 {
8569 }
8573 }
8574 \f
8575 /* Given M see if it is a value that would select a field of bits
8576 within an item, but not the entire word. Return -1 if not.
8577 Otherwise, return the starting position of the field, where 0 is the
8578 low-order bit.
8580 *PLEN is set to the length of the field. */
8582 static int
8584 {
8585 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8590 /* Now shift off the low-order zero bits and see if we have a
8591 power of two minus 1. */
8599 }
8600 \f
8601 /* If X refers to a register that equals REG in value, replace these
8602 references with REG. */
8603 static rtx
8605 {
8613 {
8646 /* FALLTHRU */
8650 {
8654 else
8656 }
8658 /* fall through */
8665 {
8668 {
8670 {
8673 }
8675 }
8676 }
8678 {
8681 {
8684 {
8686 {
8689 }
8691 }
8692 }
8693 }
8696 }
8699 }
8701 /* Return X converted to MODE. If the value is already truncated to
8702 MODE we can just return a subreg even though in the general case we
8703 would need an explicit truncation. */
8705 static rtx
8707 {
8712 {
8713 /* Bit-cast X into an integer mode. */
8718 }
8721 }
8723 /* See if X can be simplified knowing that we will only refer to it in
8724 MODE and will only refer to those bits that are nonzero in MASK.
8725 If other bits are being computed or if masking operations are done
8726 that select a superset of the bits in MASK, they can sometimes be
8727 ignored.
8729 Return a possibly simplified expression, but always convert X to
8730 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8732 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8733 are all off in X. This is used when X will be complemented, by either
8734 NOT, NEG, or XOR. */
8736 static rtx
8739 {
8742 machine_mode op_mode;
8745 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8746 code below will do the wrong thing since the mode of such an
8747 expression is VOIDmode.
8749 Also do nothing if X is a CLOBBER; this can happen if X was
8750 the return value from a call to gen_lowpart. */
8754 /* We want to perform the operation in its present mode unless we know
8755 that the operation is valid in MODE, in which case we do the operation
8756 in MODE. */
8761 /* It is not valid to do a right-shift in a narrower mode
8762 than the one it came in with. */
8767 /* Truncate MASK to fit OP_MODE. */
8771 /* Determine what bits of X are guaranteed to be (non)zero. */
8774 /* If none of the bits in X are needed, return a zero. */
8778 /* If X is a CONST_INT, return a new one. Do this here since the
8779 test below will fail. */
8781 {
8784 else
8785 {
8788 }
8789 }
8791 /* If X is narrower than MODE and we want all the bits in X's mode, just
8792 get X in the proper mode. */
8797 /* We can ignore the effect of a SUBREG if it narrows the mode or
8798 if the constant masks to zero all the bits the mode doesn't have. */
8802 || (mask
8810 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8811 integer too. */
8817 }
8819 /* Subroutine of force_to_mode that handles cases in which both X and
8820 the result are scalar integers. MODE is the mode of the result,
8821 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8822 is preferred for simplified versions of X. The other arguments
8823 are as for force_to_mode. */
8825 static rtx
8829 {
8834 poly_int64 const_op0;
8836 /* When we have an arithmetic operation, or a shift whose count we
8837 do not know, we need to assume that all bits up to the highest-order
8838 bit in MASK will be needed. This is how we form such a mask. */
8841 else
8846 {
8848 /* If X is a (clobber (const_int)), return it since we know we are
8849 generating something that won't match. */
8862 /* Similarly for a truncate. */
8866 /* If this is an AND with a constant, convert it into an AND
8867 whose constant is the AND of that constant with MASK. If it
8868 remains an AND of MASK, delete it since it is redundant. */
8871 {
8876 /* If X is still an AND, see if it is an AND with a mask that
8877 is just some low-order bits. If so, and it is MASK, we don't
8878 need it. */
8884 /* If it remains an AND, try making another AND with the bits
8885 in the mode mask that aren't in MASK turned on. If the
8886 constant in the AND is wide enough, this might make a
8887 cheaper constant. */
8892 {
8893 unsigned HOST_WIDE_INT cval
8895 rtx y;
8902 }
8905 }
8910 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8911 low-order bits (as in an alignment operation) and FOO is already
8912 aligned to that boundary, mask C1 to that boundary as well.
8913 This may eliminate that PLUS and, later, the AND. */
8915 {
8919 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8920 number, sign extend it. */
8933 }
8935 /* fall through */
8938 /* Substituting into the operands of a widening MULT is not likely to
8939 create RTL matching a machine insn. */
8949 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8950 most significant bit in MASK since carries from those bits will
8951 affect the bits we are interested in. */
8956 /* If X is (minus C Y) where C's least set bit is larger than any bit
8957 in the mask, then we may replace with (neg Y). */
8960 {
8963 }
8965 /* Similarly, if C contains every bit in the fuller_mask, then we may
8966 replace with (not Y). */
8969 {
8972 }
8979 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8980 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8981 operation which may be a bitfield extraction. Ensure that the
8982 constant we form is not wider than the mode of X. */
8994 {
8997 xmode);
9003 }
9005 binop:
9006 /* For most binary operations, just propagate into the operation and
9007 change the mode if we have an operation of that mode. */
9012 /* If we ended up truncating both operands, truncate the result of the
9013 operation instead. */
9016 {
9019 }
9025 {
9028 }
9032 /* For left shifts, do the same, but just for the first operand.
9033 However, we cannot do anything with shifts where we cannot
9034 guarantee that the counts are smaller than the size of the mode
9035 because such a count will have a different meaning in a
9036 wider mode. */
9046 /* If the shift count is a constant and we can do arithmetic in
9047 the mode of the shift, refine which bits we need. Otherwise, use the
9048 conservative form of the mask. */
9054 else
9062 {
9065 }
9069 /* Here we can only do something if the shift count is a constant,
9070 this shift constant is valid for the host, and we can do arithmetic
9071 in OP_MODE. */
9077 {
9081 /* Select the mask of the bits we need for the shift operand. */
9084 /* We can only change the mode of the shift if we can do arithmetic
9085 in the mode of the shift and INNER_MASK is no wider than the
9086 width of X's mode. */
9093 {
9096 }
9097 }
9099 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9100 shift and AND produces only copies of the sign bit (C2 is one less
9101 than a power of two), we can do this with just a shift. */
9105 /* The shift puts one of the sign bit copies in the least significant
9106 bit. */
9111 /* Number of bits left after the shift must be more than the mask
9112 needs. */
9115 /* Must be more sign bit copies than the mask needs. */
9118 {
9122 }
9126 /* If we are just looking for the sign bit, we don't need this shift at
9127 all, even if it has a variable count. */
9131 /* If this is a shift by a constant, get a mask that contains those bits
9132 that are not copies of the sign bit. We then have two cases: If
9133 MASK only includes those bits, this can be a logical shift, which may
9134 allow simplifications. If MASK is a single-bit field not within
9135 those bits, we are requesting a copy of the sign bit and hence can
9136 shift the sign bit to the appropriate location. */
9140 {
9144 /* If the considered data is wider than HOST_WIDE_INT, we can't
9145 represent a mask for all its bits in a single scalar.
9146 But we only care about the lower bits, so calculate these. */
9149 {
9152 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9153 is the number of bits a full-width mask would have set.
9154 We need only shift if these are fewer than nonzero can
9155 hold. If not, we must keep all bits set in nonzero. */
9160 + HOST_BITS_PER_WIDE_INT
9162 }
9163 else
9164 {
9167 }
9170 {
9175 }
9178 {
9179 x = simplify_shift_const
9185 }
9186 }
9188 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9189 even if the shift count isn't a constant. */
9193 shiftrt:
9195 /* If this is a zero- or sign-extension operation that just affects bits
9196 we don't care about, remove it. Be sure the call above returned
9197 something that is still a shift. */
9207 next_select);
9213 /* If the shift count is constant and we can do computations
9214 in the mode of X, compute where the bits we care about are.
9215 Otherwise, we can't do anything. Don't change the mode of
9216 the shift or propagate MODE into the shift, though. */
9219 {
9228 }
9232 /* If we just want the low-order bit, the NEG isn't needed since it
9233 won't change the low-order bit. */
9237 /* We need any bits less significant than the most significant bit in
9238 MASK since carries from those bits will affect the bits we are
9239 interested in. */
9244 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9245 same as the XOR case above. Ensure that the constant we form is not
9246 wider than the mode of X. */
9254 {
9261 }
9263 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9264 use the full mask inside the NOT. */
9267 unop:
9270 next_select));
9272 {
9275 }
9279 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9280 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9281 which is equal to STORE_FLAG_VALUE. */
9293 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9294 written in a narrower mode. We play it safe and do not do so. */
9310 }
9312 /* Ensure we return a value of the proper mode. */
9314 }
9315 \f
9316 /* Return nonzero if X is an expression that has one of two values depending on
9317 whether some other value is zero or nonzero. In that case, we return the
9318 value that is being tested, *PTRUE is set to the value if the rtx being
9319 returned has a nonzero value, and *PFALSE is set to the other alternative.
9321 If we return zero, we set *PTRUE and *PFALSE to X. */
9323 static rtx
9325 {
9330 scalar_int_mode int_mode;
9332 /* If we are comparing a value against zero, we are done. */
9335 {
9339 }
9341 /* If this is a unary operation whose operand has one of two values, apply
9342 our opcode to compute those values. */
9345 {
9350 }
9352 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9353 make can't possibly match and would suppress other optimizations. */
9355 ;
9357 /* If this is a binary operation, see if either side has only one of two
9358 values. If either one does or if both do and they are conditional on
9359 the same value, compute the new true and false values. */
9361 {
9369 {
9370 /* Try to enable a simplification by undoing work done by
9371 if_then_else_cond if it converted a REG into something more
9372 complex. */
9374 {
9377 }
9378 else
9379 {
9382 }
9383 }
9387 {
9388 /* If if_then_else_cond returned zero, then true/false are the
9389 same rtl. We must copy one of them to prevent invalid rtl
9390 sharing. */
9397 {
9402 }
9403 else
9404 {
9407 }
9410 }
9412 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9413 operands is zero when the other is nonzero, and vice-versa,
9414 and STORE_FLAG_VALUE is 1 or -1. */
9420 {
9438 {
9445 const_true_rtx);
9447 }
9448 }
9450 /* Similarly for MULT, AND and UMIN, except that for these the result
9451 is always zero. */
9455 {
9469 {
9472 }
9473 }
9474 }
9477 {
9478 /* If we have IF_THEN_ELSE already, extract the condition and
9479 canonicalize it if it is NE or EQ. */
9485 {
9488 }
9489 else
9491 }
9493 /* If X is a SUBREG, we can narrow both the true and false values
9494 if the inner expression, if there is a condition. */
9498 {
9504 {
9508 }
9509 }
9511 /* If X is a constant, this isn't special and will cause confusions
9512 if we treat it as such. Likewise if it is equivalent to a constant. */
9515 ;
9517 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9518 will be least confusing to the rest of the compiler. */
9520 {
9523 }
9525 /* If X is known to be either 0 or -1, those are the true and
9526 false values when testing X. */
9531 {
9534 }
9536 /* Likewise for 0 or a single bit. */
9539 {
9542 }
9544 /* Otherwise fail; show no condition with true and false values the same. */
9547 }
9548 \f
9549 /* Return the value of expression X given the fact that condition COND
9550 is known to be true when applied to REG as its first operand and VAL
9551 as its second. X is known to not be shared and so can be modified in
9552 place.
9554 We only handle the simplest cases, and specifically those cases that
9555 arise with IF_THEN_ELSE expressions. */
9557 static rtx
9559 {
9567 /* If either operand of the condition is a floating point value,
9568 then we have to avoid collapsing an EQ comparison. */
9578 /* If X is (abs REG) and we know something about REG's relationship
9579 with zero, we may be able to simplify this. */
9583 {
9592 }
9594 /* The only other cases we handle are MIN, MAX, and comparisons if the
9595 operands are the same as REG and VAL. */
9598 {
9600 {
9603 }
9606 {
9608 {
9616 else
9618 }
9621 {
9624 /* Do not reverse the condition when it is NE or EQ.
9625 This is because we cannot conclude anything about
9626 the value of 'SMAX (x, y)' when x is not equal to y,
9627 but we can when x equals y. */
9633 {
9644 }
9645 }
9646 }
9647 }
9649 {
9654 {
9655 /* We must simplify subreg here, before we lose track of the
9656 original inner_mode. */
9661 else
9663 }
9666 }
9667 /* We don't have to handle SIGN_EXTEND here, because even in the
9668 case of replacing something with a modeless CONST_INT, a
9669 CONST_INT is already (supposed to be) a valid sign extension for
9670 its narrower mode, which implies it's already properly
9671 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9672 story is different. */
9674 {
9679 {
9680 /* We must simplify the zero_extend here, before we lose
9681 track of the original inner_mode. */
9686 else
9688 }
9691 }
9695 {
9702 }
9705 }
9706 \f
9707 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9708 assignment as a field assignment. */
9710 static int
9712 {
9714 {
9722 }
9730 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9731 Note that all SUBREGs of MEM are paradoxical; otherwise they
9732 would have been rewritten. */
9745 /* We used to see if get_last_value of X and Y were the same but that's
9746 not correct. In one direction, we'll cause the assignment to have
9747 the wrong destination and in the case, we'll import a register into this
9748 insn that might have already have been dead. So fail if none of the
9749 above cases are true. */
9751 }
9752 \f
9753 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9754 Return that assignment if so.
9756 We only handle the most common cases. */
9758 static rtx
9760 {
9763 rtx assign;
9765 HOST_WIDE_INT c1;
9766 HOST_WIDE_INT pos;
9768 rtx other;
9770 /* All the rules in this function are specific to scalar integers. */
9771 scalar_int_mode mode;
9775 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9776 a clear of a one-bit field. We will have changed it to
9777 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9778 for a SUBREG. */
9784 {
9790 }
9799 {
9806 }
9808 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9809 one-bit field. */
9813 {
9819 }
9821 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9822 SRC is an AND with all bits of that field set, then we can discard
9823 the AND. */
9828 {
9835 else
9838 /* Complete overlap. We can remove the source AND. */
9842 /* Partial overlap. We can reduce the source AND. */
9844 {
9848 }
9849 }
9851 /* The other case we handle is assignments into a constant-position
9852 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9853 a mask that has all one bits except for a group of zero bits and
9854 OTHER is known to have zeros where C1 has ones, this is such an
9855 assignment. Compute the position and length from C1. Shift OTHER
9856 to the appropriate position, force it to the required mode, and
9857 make the extraction. Check for the AND in both operands. */
9859 /* One or more SUBREGs might obscure the constant-position field
9860 assignment. The first one we are likely to encounter is an outer
9861 narrowing SUBREG, which we can just strip for the purposes of
9862 identifying the constant-field assignment. */
9879 /* The second SUBREG that might get in the way is a paradoxical
9880 SUBREG around the first operand of the AND. We want to
9881 pretend the operand is as wide as the destination here. We
9882 do this by adjusting the MEM to wider mode for the sole
9883 purpose of the call to rtx_equal_for_field_assignment_p. Also
9884 note this trick only works for MEMs. */
9896 /* The second SUBREG that might get in the way is a paradoxical
9897 SUBREG around the first operand of the AND. We want to
9898 pretend the operand is as wide as the destination here. We
9899 do this by adjusting the MEM to wider mode for the sole
9900 purpose of the call to rtx_equal_for_field_assignment_p. Also
9901 note this trick only works for MEMs. */
9909 else
9923 /* The mode to use for the source is the mode of the assignment, or of
9924 what is inside a possible STRICT_LOW_PART. */
9928 /* Shift OTHER right POS places and make it the source, restricting it
9929 to the proper length and mode. */
9933 dest);
9935 len >= HOST_BITS_PER_WIDE_INT
9936 ? HOST_WIDE_INT_M1U
9940 /* If SRC is masked by an AND that does not make a difference in
9941 the value being stored, strip it. */
9952 }
9953 \f
9954 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9955 if so. */
9957 static rtx
9959 {
9963 rtx tem;
9965 /* Distributivity is not true for floating point as it can change the
9966 value. So we don't do it unless -funsafe-math-optimizations. */
9971 /* The outer operation can only be one of the following: */
9979 /* If either operand is a primitive we can't do anything, so get out
9980 fast. */
9990 /* See if the inner and outer operations distribute. */
9992 {
9997 /* These all distribute except over PLUS. */
10008 /* This is also a multiply, so it distributes over everything. */
10011 /* This used to handle SUBREG, but this turned out to be counter-
10012 productive, since (subreg (op ...)) usually is not handled by
10013 insn patterns, and this "optimization" therefore transformed
10014 recognizable patterns into unrecognizable ones. Therefore the
10015 SUBREG case was removed from here.
10017 It is possible that distributing SUBREG over arithmetic operations
10018 leads to an intermediate result than can then be optimized further,
10019 e.g. by moving the outer SUBREG to the other side of a SET as done
10020 in simplify_set. This seems to have been the original intent of
10021 handling SUBREGs here.
10023 However, with current GCC this does not appear to actually happen,
10024 at least on major platforms. If some case is found where removing
10025 the SUBREG case here prevents follow-on optimizations, distributing
10026 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
10030 }
10032 /* Set LHS and RHS to the inner operands (A and B in the example
10033 above) and set OTHER to the common operand (C in the example).
10034 There is only one way to do this unless the inner operation is
10035 commutative. */
10047 else
10050 /* Form the new inner operation, seeing if it simplifies first. */
10053 /* There is one exception to the general way of distributing:
10054 (a | c) ^ (b | c) -> (a ^ b) & ~c */
10056 {
10059 }
10061 /* We may be able to continuing distributing the result, so call
10062 ourselves recursively on the inner operation before forming the
10063 outer operation, which we return. */
10066 }
10068 /* See if X is of the form (* (+ A B) C), and if so convert to
10069 (+ (* A C) (* B C)) and try to simplify.
10071 Most of the time, this results in no change. However, if some of
10072 the operands are the same or inverses of each other, simplifications
10073 will result.
10075 For example, (and (ior A B) (not B)) can occur as the result of
10076 expanding a bit field assignment. When we apply the distributive
10077 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
10078 which then simplifies to (and (A (not B))).
10080 Note that no checks happen on the validity of applying the inverse
10081 distributive law. This is pointless since we can do it in the
10082 few places where this routine is called.
10084 N is the index of the term that is decomposed (the arithmetic operation,
10085 i.e. (+ A B) in the first example above). !N is the index of the term that
10086 is distributed, i.e. of C in the first example above. */
10087 static rtx
10089 {
10090 machine_mode mode;
10094 /* Distributivity is not true for floating point as it can change the
10095 value. So we don't do it unless -funsafe-math-optimizations. */
10112 /* Special case (and (xor B C) (not A)), which is equivalent to
10113 (xor (ior A B) (ior A C)) */
10115 {
10118 }
10121 {
10122 /* Distribute the second term. */
10125 }
10126 else
10127 {
10128 /* Distribute the first term. */
10131 }
10141 }
10142 \f
10143 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10144 in MODE. Return an equivalent form, if different from (and VAROP
10145 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10147 static rtx
10150 {
10153 rtx orig_varop;
10161 /* Simplify VAROP knowing that we will be only looking at some of the
10162 bits in it.
10164 Note by passing in CONSTOP, we guarantee that the bits not set in
10165 CONSTOP are not significant and will never be examined. We must
10166 ensure that is the case by explicitly masking out those bits
10167 before returning. */
10170 /* If VAROP is a CLOBBER, we will fail so return it. */
10174 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10175 to VAROP and return the new constant. */
10179 /* See what bits may be nonzero in VAROP. Unlike the general case of
10180 a call to nonzero_bits, here we don't care about bits outside
10181 MODE. */
10185 /* Turn off all bits in the constant that are known to already be zero.
10186 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10187 which is tested below. */
10191 /* If we don't have any bits left, return zero. */
10195 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10196 a power of two, we can replace this with an ASHIFT. */
10201 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10202 or XOR, then try to apply the distributive law. This may eliminate
10203 operations if either branch can be simplified because of the AND.
10204 It may also make some cases more complex, but those cases probably
10205 won't match a pattern either with or without this. */
10208 {
10210 return
10211 gen_lowpart
10213 apply_distributive_law
10217 constop),
10220 constop))));
10221 }
10223 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10224 the AND and see if one of the operands simplifies to zero. If so, we
10225 may eliminate it. */
10229 {
10238 }
10240 /* Make a SUBREG if necessary. If we can't make it, fail. */
10245 /* If we are only masking insignificant bits, return VAROP. */
10252 /* Otherwise, return an AND. */
10254 }
10257 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10258 in MODE.
10260 Return an equivalent form, if different from X. Otherwise, return X. If
10261 X is zero, we are to always construct the equivalent form. */
10263 static rtx
10266 {
10277 }
10278 \f
10279 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10280 We don't care about bits outside of those defined in MODE.
10281 We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10283 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10284 a shift, AND, or zero_extract, we can do better. */
10286 static rtx
10288 scalar_int_mode mode,
10290 {
10291 rtx tem;
10294 /* If X is a register whose nonzero bits value is current, use it.
10295 Otherwise, if X is a register whose value we can find, use that
10296 value. Otherwise, use the previously-computed global nonzero bits
10297 for this register. */
10312 && !REGNO_REG_SET_P
10315 {
10316 /* Note that, even if the precision of last_set_mode is lower than that
10317 of mode, record_value_for_reg invoked nonzero_bits on the register
10318 with nonzero_bits_mode (because last_set_mode is necessarily integral
10319 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10320 are all valid, hence in mode too since nonzero_bits_mode is defined
10321 to the largest HWI_COMPUTABLE_MODE_P mode. */
10324 }
10328 {
10333 }
10336 {
10340 /* We don't know anything about the upper bits. */
10344 }
10347 }
10349 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10350 end of X that are known to be equal to the sign bit. X will be used
10351 in mode MODE; the returned value will always be between 1 and the
10352 number of bits in MODE. */
10354 static rtx
10356 scalar_int_mode mode,
10358 {
10359 rtx tem;
10372 && !REGNO_REG_SET_P
10375 {
10378 }
10389 }
10390 \f
10391 /* Return the number of "extended" bits there are in X, when interpreted
10392 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10393 unsigned quantities, this is the number of high-order zero bits.
10394 For signed quantities, this is the number of copies of the sign bit
10395 minus 1. In both case, this function returns the number of "spare"
10396 bits. For example, if two quantities for which this function returns
10397 at least 1 are added, the addition is known not to overflow.
10399 This function will always return 0 unless called during combine, which
10400 implies that it must be called from a define_split. */
10402 unsigned int
10404 {
10408 scalar_int_mode int_mode;
10416 }
10418 /* This function is called from `simplify_shift_const' to merge two
10419 outer operations. Specifically, we have already found that we need
10420 to perform operation *POP0 with constant *PCONST0 at the outermost
10421 position. We would now like to also perform OP1 with constant CONST1
10422 (with *POP0 being done last).
10424 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10425 the resulting operation. *PCOMP_P is set to 1 if we would need to
10426 complement the innermost operand, otherwise it is unchanged.
10428 MODE is the mode in which the operation will be done. No bits outside
10429 the width of this mode matter. It is assumed that the width of this mode
10430 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10432 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10433 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10434 result is simply *PCONST0.
10436 If the resulting operation cannot be expressed as one operation, we
10437 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10439 static int
10440 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10441 {
10448 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10452 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10453 if OP0 is SET. */
10462 {
10464 {
10482 }
10483 }
10485 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10489 /* If the two constants aren't the same, we can't do anything. The
10490 remaining six cases can all be done. */
10494 else
10496 {
10499 /* (a & b) | b == b */
10502 /* (a ^ b) | b == a | b */
10503 {;}
10508 /* (a & b) ^ b == (~a) & b */
10511 /* (a | b) ^ b == a & ~b */
10517 /* (a | b) & b == b */
10520 /* (a ^ b) & b) == (~a) & b */
10525 }
10527 /* Check for NO-OP cases. */
10540 /* ??? Slightly redundant with the above mask, but not entirely.
10541 Moving this above means we'd have to sign-extend the mode mask
10542 for the final test. */
10547 }
10548 \f
10549 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10550 the shift in. The original shift operation CODE is performed on OP in
10551 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10552 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10553 result of the shift is subject to operation OUTER_CODE with operand
10554 OUTER_CONST. */
10556 static scalar_int_mode
10560 {
10563 /* In general we can't perform in wider mode for right shift and rotate. */
10565 {
10567 /* We can still widen if the bits brought in from the left are identical
10568 to the sign bit of ORIG_MODE. */
10576 /* Similarly here but with zero bits. */
10581 /* We can also widen if the bits brought in will be masked off. This
10582 operation is performed in ORIG_MODE. */
10584 {
10590 }
10591 /* fall through */
10601 }
10602 }
10604 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10605 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10606 if we cannot simplify it. Otherwise, return a simplified value.
10608 The shift is normally computed in the widest mode we find in VAROP, as
10609 long as it isn't a different number of words than RESULT_MODE. Exceptions
10610 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10612 static rtx
10615 {
10620 machine_mode shift_mode;
10622 /* We form (outer_op (code varop count) (outer_const)). */
10628 /* Make sure and truncate the "natural" shift on the way in. We don't
10629 want to do this inside the loop as it makes it more difficult to
10630 combine shifts. */
10634 /* If we were given an invalid count, don't do anything except exactly
10635 what was requested. */
10642 /* Unless one of the branches of the `if' in this loop does a `continue',
10643 we will `break' the loop after the `if'. */
10646 {
10647 /* If we have an operand of (clobber (const_int 0)), fail. */
10651 /* Convert ROTATERT to ROTATE. */
10653 {
10657 }
10661 {
10662 /* We only change the modes of scalar shifts. */
10668 }
10670 scalar_int_mode shift_unit_mode
10673 /* Handle cases where the count is greater than the size of the mode
10674 minus 1. For ASHIFT, use the size minus one as the count (this can
10675 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10676 take the count modulo the size. For other shifts, the result is
10677 zero.
10679 Since these shifts are being produced by the compiler by combining
10680 multiple operations, each of which are defined, we know what the
10681 result is supposed to be. */
10684 {
10689 else
10690 {
10691 /* We can't simply return zero because there may be an
10692 outer op. */
10696 }
10697 }
10699 /* If we discovered we had to complement VAROP, leave. Making a NOT
10700 here would cause an infinite loop. */
10705 {
10706 /* An arithmetic right shift of a quantity known to be -1 or 0
10707 is a no-op. */
10711 {
10714 }
10716 /* If we are doing an arithmetic right shift and discarding all but
10717 the sign bit copies, this is equivalent to doing a shift by the
10718 bitsize minus one. Convert it into that shift because it will
10719 often allow other simplifications. */
10726 /* We simplify the tests below and elsewhere by converting
10727 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10728 `make_compound_operation' will convert it to an ASHIFTRT for
10729 those machines (such as VAX) that don't have an LSHIFTRT. */
10734 shift_unit_mode)))
10746 }
10749 {
10756 {
10759 }
10763 /* The following rules apply only to scalars. */
10768 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10769 minus the width of a smaller mode, we can do this with a
10770 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10777 {
10786 }
10790 /* The following rules apply only to scalars. */
10796 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10797 the same number of words as what we've seen so far. Then store
10798 the widest mode in MODE. */
10805 {
10810 }
10814 /* Some machines use MULT instead of ASHIFT because MULT
10815 is cheaper. But it is still better on those machines to
10816 merge two shifts into one. */
10819 {
10824 }
10828 /* Similar, for when divides are cheaper. */
10831 {
10836 }
10840 /* If we are extracting just the sign bit of an arithmetic
10841 right shift, that shift is not needed. However, the sign
10842 bit of a wider mode may be different from what would be
10843 interpreted as the sign bit in a narrower mode, so, if
10844 the result is narrower, don't discard the shift. */
10849 {
10852 }
10854 /* fall through */
10859 /* The following rules apply only to scalars. */
10866 /* Here we have two nested shifts. The result is usually the
10867 AND of a new shift with a mask. We compute the result below. */
10873 {
10877 rtx mask_rtx;
10879 /* We have one common special case. We can't do any merging if
10880 the inner code is an ASHIFTRT of a smaller mode. However, if
10881 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10882 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10883 we can convert it to
10884 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10885 This simplifies certain SIGN_EXTEND operations. */
10889 {
10890 /* C3 has the low-order C1 bits zero. */
10902 }
10904 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10905 than C1 high-order bits equal to the sign bit, we can convert
10906 this to either an ASHIFT or an ASHIFTRT depending on the
10907 two counts.
10909 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10915 {
10919 {
10922 }
10925 }
10927 /* There are some cases we can't do. If CODE is ASHIFTRT,
10928 we can only do this if FIRST_CODE is also ASHIFTRT.
10930 We can't do the case when CODE is ROTATE and FIRST_CODE is
10931 ASHIFTRT.
10933 If the mode of this shift is not the mode of the outer shift,
10934 we can't do this if either shift is a right shift or ROTATE.
10936 Finally, we can't do any of these if the mode is too wide
10937 unless the codes are the same.
10939 Handle the case where the shift codes are the same
10940 first. */
10943 {
10952 }
10963 /* To compute the mask to apply after the shift, shift the
10964 nonzero bits of the inner shift the same way the
10965 outer shift will. */
10968 int_result_mode);
10970 mask_rtx
10974 /* Give up if we can't compute an outer operation to use. */
10982 /* If the shifts are in the same direction, we add the
10983 counts. Otherwise, we subtract them. */
10987 else
10990 /* If COUNT is positive, the new shift is usually CODE,
10991 except for the two exceptions below, in which case it is
10992 FIRST_CODE. If the count is negative, FIRST_CODE should
10993 always be used */
11003 }
11005 /* If we have (A << B << C) for any shift, we can convert this to
11006 (A << C << B). This wins if A is a constant. Only try this if
11007 B is not a constant. */
11012 {
11013 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
11014 sure the result will be masked. See PR70222. */
11022 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
11023 up outer sign extension (often left and right shift) is
11024 hardly more efficient than the original. See PR70429.
11025 Similarly punt for rotates with different modes.
11026 See PR97386. */
11034 count_rtx);
11038 }
11042 /* The following rules apply only to scalars. */
11046 /* Make this fit the case below. */
11053 /* The following rules apply only to scalars. */
11059 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
11060 with C the size of VAROP - 1 and the shift is logical if
11061 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11062 we have an (le X 0) operation. If we have an arithmetic shift
11063 and STORE_FLAG_VALUE is 1 or we have a logical shift with
11064 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
11072 {
11075 const0_rtx);
11081 }
11083 /* If we have (shift (logical)), move the logical to the outside
11084 to allow it to possibly combine with another logical and the
11085 shift to combine with another shift. This also canonicalizes to
11086 what a ZERO_EXTRACT looks like. Also, some machines have
11087 (and (shift)) insns. */
11090 /* We can't do this if we have (ashiftrt (xor)) and the
11091 constant has its sign bit set in shift_unit_mode with
11092 shift_unit_mode wider than result_mode. */
11105 {
11108 }
11110 /* If we can't do that, try to simplify the shift in each arm of the
11111 logical expression, make a new logical expression, and apply
11112 the inverse distributive law. This also can't be done for
11113 (ashiftrt (xor)) where we've widened the shift and the constant
11114 changes the sign bit. */
11120 {
11132 }
11136 /* The following rules apply only to scalars. */
11141 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11142 says that the sign bit can be tested, FOO has mode MODE, C is
11143 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11144 that may be nonzero. */
11154 {
11158 }
11162 /* The following rules apply only to scalars. */
11167 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11168 than the number of bits in the mode is equivalent to A. */
11172 {
11176 }
11178 /* NEG commutes with ASHIFT since it is multiplication. Move the
11179 NEG outside to allow shifts to combine. */
11183 {
11186 }
11190 /* The following rules apply only to scalars. */
11195 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11196 is one less than the number of bits in the mode is
11197 equivalent to (xor A 1). */
11204 {
11208 }
11210 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11211 that might be nonzero in BAR are those being shifted out and those
11212 bits are known zero in FOO, we can replace the PLUS with FOO.
11213 Similarly in the other operand order. This code occurs when
11214 we are computing the size of a variable-size array. */
11221 {
11224 }
11232 {
11235 }
11237 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11248 {
11251 }
11253 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11254 signbit', and attempt to change the PLUS to an XOR and move it to
11255 the outer operation as is done above in the AND/IOR/XOR case
11256 leg for shift(logical). See details in logical handling above
11257 for reasoning in doing so. */
11269 {
11272 }
11277 /* The following rules apply only to scalars. */
11282 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11283 with C the size of VAROP - 1 and the shift is logical if
11284 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11285 we have a (gt X 0) operation. If the shift is arithmetic with
11286 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11287 we have a (neg (gt X 0)) operation. */
11296 {
11299 const0_rtx);
11305 }
11309 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11310 if the truncate does not affect the value. */
11317 {
11321 new_count);
11324 new_count_rtx);
11328 }
11333 }
11336 }
11340 {
11341 /* We only change the modes of scalar shifts. */
11346 }
11348 /* We have now finished analyzing the shift. The result should be
11349 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11350 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11351 to the result of the shift. OUTER_CONST is the relevant constant,
11352 but we must turn off all bits turned off in the shift. */
11360 /* Make a SUBREG if necessary. If we can't make it, fail. */
11365 /* If we have an outer operation and we just made a shift, it is
11366 possible that we could have simplified the shift were it not
11367 for the outer operation. So try to do the simplification
11368 recursively. */
11372 else
11379 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11380 turn off all the bits that the shift would have turned off. */
11382 /* We only change the modes of scalar shifts. */
11386 /* Do the remainder of the processing in RESULT_MODE. */
11389 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11390 operation. */
11395 {
11405 {
11406 /* This means that we have determined that the result is
11407 equivalent to a constant. This should be rare. */
11410 }
11413 else
11416 }
11419 }
11421 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11422 The result of the shift is RESULT_MODE. If we cannot simplify it,
11423 return X or, if it is NULL, synthesize the expression with
11424 simplify_gen_binary. Otherwise, return a simplified value.
11426 The shift is normally computed in the widest mode we find in VAROP, as
11427 long as it isn't a different number of words than RESULT_MODE. Exceptions
11428 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11430 static rtx
11433 {
11444 }
11446 \f
11447 /* A subroutine of recog_for_combine. See there for arguments and
11448 return value. */
11450 static int
11452 {
11454 rtx pat_without_clobbers;
11462 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11463 we use to indicate that something didn't match. If we find such a
11464 thing, force rejection. */
11478 {
11481 else
11484 }
11486 /* If it isn't, there is the possibility that we previously had an insn
11487 that clobbered some register as a side effect, but the combined
11488 insn doesn't need to do that. So try once more without the clobbers
11489 unless this represents an ASM insn. */
11493 {
11498 {
11501 pos++;
11502 }
11512 {
11515 else
11518 }
11519 }
11526 /* Recognize all noop sets, these will be killed by followup pass. */
11530 /* If we had any clobbers to add, make a new pattern than contains
11531 them. Then check to make sure that all of them are dead. */
11533 {
11543 else
11550 {
11555 {
11559 }
11560 }
11562 }
11566 {
11574 /* Allow targets to reject combined insn. */
11576 {
11579 dump_file);
11581 /* Callers expect recog_for_combine to strip
11582 clobbers from the pattern on failure. */
11587 }
11592 }
11598 }
11600 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11601 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11602 Return whether anything was so changed. */
11604 static bool
11606 {
11612 {
11624 {
11634 else
11638 {
11644 }
11645 }
11651 {
11656 {
11662 }
11663 }
11668 {
11672 }
11673 else
11679 {
11682 }
11686 }
11693 scalar_int_mode mode;
11699 {
11713 else
11721 }
11724 }
11726 /* Like recog, but we receive the address of a pointer to a new pattern.
11727 We try to match the rtx that the pointer points to.
11728 If that fails, we may try to modify or replace the pattern,
11729 storing the replacement into the same pointer object.
11731 Modifications include deletion or addition of CLOBBERs. If the
11732 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11733 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11734 (and undo if that fails).
11736 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11737 the CLOBBERs are placed.
11739 The value is the final insn code from the pattern ultimately matched,
11740 or -1. */
11742 static int
11744 {
11756 {
11759 {
11763 }
11764 }
11767 {
11772 }
11775 }
11776 \f
11777 /* Like gen_lowpart_general but for use by combine. In combine it
11778 is not possible to create any new pseudoregs. However, it is
11779 safe to create invalid memory addresses, because combine will
11780 try to recognize them and all they will do is make the combine
11781 attempt fail.
11783 If for some reason this cannot do its job, an rtx
11784 (clobber (const_int 0)) is returned.
11785 An insn containing that will not be recognized. */
11787 static rtx
11789 {
11791 rtx result;
11796 /* We can only support MODE being wider than a word if X is a
11797 constant integer or has a mode the same size. */
11803 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11804 won't know what to do. So we will strip off the SUBREG here and
11805 process normally. */
11807 {
11810 /* For use in case we fall down into the address adjustments
11811 further below, we need to adjust the known mode and size of
11812 x; imode and isize, since we just adjusted x. */
11817 }
11825 {
11826 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11827 address. */
11832 /* If we want to refer to something bigger than the original memref,
11833 generate a paradoxical subreg instead. That will force a reload
11834 of the original memref X. */
11840 }
11842 /* If X is a comparison operator, rewrite it in a new mode. This
11843 probably won't match, but may allow further simplifications. */
11849 /* If we couldn't simplify X any other way, just enclose it in a
11850 SUBREG. Normally, this SUBREG won't match, but some patterns may
11851 include an explicit SUBREG or we may simplify it further in combine. */
11852 else
11853 {
11854 rtx res;
11857 {
11862 }
11866 }
11868 fail:
11870 }
11871 \f
11872 /* Try to simplify a comparison between OP0 and a constant OP1,
11873 where CODE is the comparison code that will be tested, into a
11874 (CODE OP0 const0_rtx) form.
11876 The result is a possibly different comparison code to use.
11877 *POP1 may be updated. */
11879 static enum rtx_code
11882 {
11883 scalar_int_mode int_mode;
11886 /* Get the constant we are comparing against and turn off all bits
11887 not on in our mode. */
11891 /* If we are comparing against a constant power of two and the value
11892 being compared can only have that single bit nonzero (e.g., it was
11893 `and'ed with that bit), we can replace this with a comparison
11894 with zero. */
11903 {
11906 }
11908 /* Similarly, if we are comparing a value known to be either -1 or
11909 0 with -1, change it to the opposite comparison against zero. */
11915 {
11918 }
11920 /* Do some canonicalizations based on the comparison code. We prefer
11921 comparisons against zero and then prefer equality comparisons.
11922 If we can reduce the size of a constant, we will do that too. */
11924 {
11926 /* < C is equivalent to <= (C - 1) */
11928 {
11931 /* ... fall through to LE case below. */
11933 }
11934 else
11938 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11940 {
11943 }
11945 /* If we are doing a <= 0 comparison on a value known to have
11946 a zero sign bit, we can replace this with == 0. */
11957 /* >= C is equivalent to > (C - 1). */
11959 {
11962 /* ... fall through to GT below. */
11964 }
11965 else
11969 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11971 {
11974 }
11976 /* If we are doing a > 0 comparison on a value known to have
11977 a zero sign bit, we can replace this with != 0. */
11988 /* < C is equivalent to <= (C - 1). */
11990 {
11993 /* ... fall through ... */
11995 }
11996 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
12001 {
12005 }
12006 else
12010 /* unsigned <= 0 is equivalent to == 0 */
12013 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
12017 == ((HOST_WIDE_INT_1U
12019 {
12022 }
12026 /* >= C is equivalent to > (C - 1). */
12028 {
12031 /* ... fall through ... */
12033 }
12035 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
12040 {
12044 }
12045 else
12049 /* unsigned > 0 is equivalent to != 0 */
12052 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
12056 == (HOST_WIDE_INT_1U
12058 {
12061 }
12066 }
12070 }
12071 \f
12072 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12073 comparison code that will be tested.
12075 The result is a possibly different comparison code to use. *POP0 and
12076 *POP1 may be updated.
12078 It is possible that we might detect that a comparison is either always
12079 true or always false. However, we do not perform general constant
12080 folding in combine, so this knowledge isn't useful. Such tautologies
12081 should have been detected earlier. Hence we ignore all such cases. */
12083 static enum rtx_code
12085 {
12091 opt_scalar_int_mode tmode_iter;
12093 /* Try a few ways of applying the same transformation to both operands. */
12095 {
12096 /* The test below this one won't handle SIGN_EXTENDs on these machines,
12097 so check specially. */
12116 {
12119 }
12121 /* If both operands are the same constant shift, see if we can ignore the
12122 shift. We can if the shift is a rotate or if the bits shifted out of
12123 this shift are known to be zero for both inputs and if the type of
12124 comparison is compatible with the shift. */
12137 {
12150 else
12152 }
12154 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12155 SUBREGs are of the same mode, and, in both cases, the AND would
12156 be redundant if the comparison was done in the narrower mode,
12157 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12158 and the operand's possibly nonzero bits are 0xffffff01; in that case
12159 if we only care about QImode, we don't need the AND). This case
12160 occurs if the output mode of an scc insn is not SImode and
12161 STORE_FLAG_VALUE == 1 (e.g., the 386).
12163 Similarly, check for a case where the AND's are ZERO_EXTEND
12164 operations from some narrower mode even though a SUBREG is not
12165 present. */
12170 {
12186 {
12190 /* The resulting comparison is always unsigned since we masked
12191 off the original sign bit. */
12195 }
12201 {
12207 }
12211 }
12213 /* If both operands are NOT, we can strip off the outer operation
12214 and adjust the comparison code for swapped operands; similarly for
12215 NEG, except that this must be an equality comparison. */
12221 else
12223 }
12225 /* If the first operand is a constant, swap the operands and adjust the
12226 comparison code appropriately, but don't do this if the second operand
12227 is already a constant integer. */
12229 {
12232 }
12234 /* We now enter a loop during which we will try to simplify the comparison.
12235 For the most part, we only are concerned with comparisons with zero,
12236 but some things may really be comparisons with zero but not start
12237 out looking that way. */
12240 {
12242 scalar_int_mode int_mode;
12246 HOST_WIDE_INT const_op;
12248 /* We only want to handle integral modes. This catches VOIDmode,
12249 CCmode, and the floating-point modes. An exception is that we
12250 can handle VOIDmode if OP0 is a COMPARE or a comparison
12251 operation. */
12258 /* Try to simplify the compare to constant, possibly changing the
12259 comparison op, and/or changing op1 to zero. */
12263 /* Compute some predicates to simplify code below. */
12270 /* If this is a sign bit comparison and we can do arithmetic in
12271 MODE, say that we will only be needing the sign bit of OP0. */
12276 HOST_WIDE_INT_1U
12281 {
12282 /* We can't do anything if OP0 is a condition code value, rather
12283 than an actual data value. */
12289 /* Get the two operands being compared. */
12292 else
12295 /* Check for the cases where we simply want the result of the
12296 earlier test or the opposite of that result. */
12300 {
12304 else
12308 {
12313 }
12314 }
12316 }
12322 /* Now try cases based on the opcode of OP0. If none of the cases
12323 does a "continue", we exit this loop immediately after the
12324 switch. */
12329 {
12331 /* If we are extracting a single bit from a variable position in
12332 a constant that has only a single bit set and are comparing it
12333 with zero, we can convert this into an equality comparison
12334 between the position and the location of the single bit. */
12335 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12336 have already reduced the shift count modulo the word size. */
12342 {
12350 /* Result is nonzero iff shift count is equal to I. */
12353 }
12355 /* fall through */
12360 {
12363 }
12367 /* If testing for equality, we can take the NOT of the constant. */
12370 {
12374 }
12376 /* If just looking at the sign bit, reverse the sense of the
12377 comparison. */
12379 {
12383 }
12387 /* If testing for equality, we can take the NEG of the constant. */
12390 {
12394 }
12396 /* The remaining cases only apply to comparisons with zero. */
12400 /* When X is ABS or is known positive,
12401 (neg X) is < 0 if and only if X != 0. */
12409 {
12413 }
12415 /* If we have NEG of something whose two high-order bits are the
12416 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12418 {
12422 }
12426 /* If we are testing equality and our count is a constant, we
12427 can perform the inverse operation on our RHS. */
12431 {
12435 }
12437 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12438 a particular bit. Convert it to an AND of a constant of that
12439 bit. This will be converted into a ZERO_EXTRACT. */
12444 {
12446 (HOST_WIDE_INT_1U
12451 }
12453 /* Fall through. */
12456 /* ABS is ignorable inside an equality comparison with zero. */
12458 {
12461 }
12465 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12466 (compare FOO CONST) if CONST fits in FOO's mode and we
12467 are either testing inequality or have an unsigned
12468 comparison with ZERO_EXTEND or a signed comparison with
12469 SIGN_EXTEND. But don't do it if we don't have a compare
12470 insn of the given mode, since we'd have to revert it
12471 later on, and then we wouldn't know whether to sign- or
12472 zero-extend. */
12474 && ! unsigned_comparison_p
12478 {
12481 }
12485 /* Check for the case where we are comparing A - C1 with C2, that is
12487 (subreg:MODE (plus (A) (-C1))) op (C2)
12489 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12490 comparison in the wider mode. One of the following two conditions
12491 must be true in order for this to be valid:
12493 1. The mode extension results in the same bit pattern being added
12494 on both sides and the comparison is equality or unsigned. As
12495 C2 has been truncated to fit in MODE, the pattern can only be
12496 all 0s or all 1s.
12498 2. The mode extension results in the sign bit being copied on
12499 each side.
12501 The difficulty here is that we have predicates for A but not for
12502 (A - C1) so we need to check that C1 is within proper bounds so
12503 as to perturbate A as little as possible. */
12512 {
12520 /* (A - C1) zero-extends if it is positive and sign-extends
12521 if it is negative, C2 both zero- and sign-extends. */
12525 /* (A - C1) sign-extends if it is positive and 1-extends
12526 if it is negative, C2 both sign- and 1-extends. */
12533 /* (A - C1) always sign-extends, like C2. */
12537 {
12540 }
12541 }
12543 /* If the inner mode is narrower and we are extracting the low part,
12544 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12546 ;
12555 {
12556 /* Remove outer subregs that don't do anything. */
12561 {
12565 }
12567 }
12568 else
12571 /* FALLTHROUGH */
12580 {
12583 }
12587 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12588 this for equality comparisons due to pathological cases involving
12589 overflows. */
12593 {
12597 }
12599 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12602 {
12606 }
12610 /* We used to optimize signed comparisons against zero, but that
12611 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12612 arrive here as equality comparisons, or (GEU, LTU) are
12613 optimized away. No need to special-case them. */
12615 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12616 (eq B (minus A C)), whichever simplifies. We can only do
12617 this for equality comparisons due to pathological cases involving
12618 overflows. */
12622 {
12626 }
12631 {
12635 }
12637 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12638 of bits in X minus 1, is one iff X > 0. */
12643 {
12647 }
12651 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12652 if C is zero or B is a constant. */
12656 {
12660 }
12665 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12666 iff X <= 0. */
12670 {
12674 }
12678 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12679 will be converted to a ZERO_EXTRACT later. */
12683 {
12688 }
12690 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12691 zero and X is a comparison and C1 and C2 describe only bits set
12692 in STORE_FLAG_VALUE, we can compare with X. */
12700 {
12707 {
12710 }
12711 }
12713 /* If we are doing an equality comparison of an AND of a bit equal
12714 to the sign bit, replace this with a LT or GE comparison of
12715 the underlying value. */
12722 {
12726 }
12728 /* If this AND operation is really a ZERO_EXTEND from a narrower
12729 mode, the constant fits within that mode, and this is either an
12730 equality or unsigned comparison, try to do this comparison in
12731 the narrower mode.
12733 Note that in:
12735 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12736 -> (ne:DI (reg:SI 4) (const_int 0))
12738 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12739 known to hold a value of the required mode the
12740 transformation is invalid. */
12748 {
12751 }
12753 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12754 fits in both M1 and M2 and the SUBREG is either paradoxical
12755 or represents the low part, permute the SUBREG and the AND
12756 and try again. */
12759 {
12761 /* Require an integral mode, to avoid creating something like
12762 (AND:SF ...). */
12765 /* It is unsafe to commute the AND into the SUBREG if the
12766 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12767 not defined. As originally written the upper bits
12768 have a defined value due to the AND operation.
12769 However, if we commute the AND inside the SUBREG then
12770 they no longer have defined values and the meaning of
12771 the code has been changed.
12772 Also C1 should not change value in the smaller mode,
12773 see PR67028 (a positive C1 can become negative in the
12774 smaller mode, so that the AND does no longer mask the
12775 upper bits). */
12776 && ((WORD_REGISTER_OPERATIONS
12788 {
12794 }
12795 }
12797 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12801 {
12806 }
12808 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12809 (eq (and (lshiftrt X) 1) 0).
12810 Also handle the case where (not X) is expressed using xor. */
12814 {
12824 == HOST_WIDE_INT_1U
12826 {
12827 op0
12832 }
12833 }
12837 /* If we have (compare (ashift FOO N) (const_int C)) and
12838 the high order N bits of FOO (N+1 if an inequality comparison)
12839 are known to be zero, we can do this by comparing FOO with C
12840 shifted right N bits so long as the low-order N bits of C are
12841 zero. */
12853 {
12854 /* We must perform a logical shift, not an arithmetic one,
12855 as we want the top N bits of C to be zero. */
12862 }
12864 /* If we are doing a sign bit comparison, it means we are testing
12865 a particular bit. Convert it to the appropriate AND. */
12868 {
12870 (HOST_WIDE_INT_1U
12875 }
12877 /* If this an equality comparison with zero and we are shifting
12878 the low bit to the sign bit, we can convert this to an AND of the
12879 low-order bit. */
12883 {
12886 }
12890 /* If this is an equality comparison with zero, we can do this
12891 as a logical shift, which might be much simpler. */
12894 {
12899 }
12901 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12902 do the comparison in a narrower mode. */
12912 {
12915 }
12917 /* Likewise if OP0 is a PLUS of a sign extension with a
12918 constant, which is usually represented with the PLUS
12919 between the shifts. */
12931 {
12939 new_const);
12941 }
12943 /* FALLTHROUGH */
12945 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12946 the low order N bits of FOO are known to be zero, we can do this
12947 by comparing FOO with C shifted left N bits so long as no
12948 overflow occurs. Even if the low order N bits of FOO aren't known
12949 to be zero, if the comparison is >= or < we can use the same
12950 optimization and for > or <= by setting all the low
12951 order N bits in the comparison constant. */
12962 {
12963 unsigned HOST_WIDE_INT low_bits
12965 & ((HOST_WIDE_INT_1U
12968 {
12969 /* If the shift was logical, then we must make the condition
12970 unsigned. */
12979 const_op
12984 }
12985 }
12987 /* If we are using this shift to extract just the sign bit, we
12988 can replace this with an LT or GE comparison. */
12993 {
12997 }
13002 }
13005 }
13007 /* Now make any compound operations involved in this comparison. Then,
13008 check for an outmost SUBREG on OP0 that is not doing anything or is
13009 paradoxical. The latter transformation must only be performed when
13010 it is known that the "extra" bits will be the same in op0 and op1 or
13011 that they don't matter. There are three cases to consider:
13013 1. SUBREG_REG (op0) is a register. In this case the bits are don't
13014 care bits and we can assume they have any convenient value. So
13015 making the transformation is safe.
13017 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
13018 In this case the upper bits of op0 are undefined. We should not make
13019 the simplification in that case as we do not know the contents of
13020 those bits.
13022 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
13023 In that case we know those bits are zeros or ones. We must also be
13024 sure that they are the same as the upper bits of op1.
13026 We can never remove a SUBREG for a non-equality comparison because
13027 the sign bit is in a different place in the underlying object. */
13040 {
13042 {
13043 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
13044 implemented. */
13046 {
13049 }
13050 }
13054 {
13059 }
13060 }
13062 /* We now do the opposite procedure: Some machines don't have compare
13063 insns in all modes. If OP0's mode is an integer mode smaller than a
13064 word and we can't do a compare in that mode, see if there is a larger
13065 mode for which we can do the compare. There are a number of cases in
13066 which we can use the wider mode. */
13072 {
13077 {
13080 /* If this is a test for negative, we can make an explicit
13081 test of the sign bit. Test this first so we can use
13082 a paradoxical subreg to extend OP0. */
13086 {
13087 unsigned HOST_WIDE_INT sign
13094 }
13096 /* If the only nonzero bits in OP0 and OP1 are those in the
13097 narrower mode and this is an equality or unsigned comparison,
13098 we can use the wider mode. Similarly for sign-extended
13099 values, in which case it is true for all comparisons. */
13116 {
13117 /* If OP0 is an AND and we don't have an AND in MODE either,
13118 make a new AND in the proper mode. */
13126 else
13127 {
13129 {
13134 }
13135 else
13136 {
13141 }
13143 }
13144 }
13145 }
13146 }
13148 /* We may have changed the comparison operands. Re-canonicalize. */
13150 {
13153 }
13155 /* If this machine only supports a subset of valid comparisons, see if we
13156 can convert an unsupported one into a supported one. */
13163 }
13164 \f
13165 /* Utility function for record_value_for_reg. Count number of
13166 rtxs in X. */
13167 static int
13169 {
13176 {
13196 }
13207 }
13208 \f
13209 /* Utility function for following routine. Called when X is part of a value
13210 being stored into last_set_value. Sets last_set_table_tick
13211 for each register mentioned. Similar to mention_regs in cse.c */
13213 static void
13215 {
13221 {
13227 {
13230 }
13233 }
13237 {
13238 /* Check for identical subexpressions. If x contains
13239 identical subexpression we only have to traverse one of
13240 them. */
13242 {
13243 /* Note that at this point x1 has already been
13244 processed. */
13248 /* If x0 and x1 are identical then there is no need to
13249 process x0. */
13253 /* If x0 is identical to a subexpression of x1 then while
13254 processing x1, x0 has already been processed. Thus we
13255 are done with x. */
13260 /* If x1 is identical to a subexpression of x0 then we
13261 still have to process the rest of x0. */
13264 {
13267 }
13268 }
13271 }
13275 }
13277 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13278 are saying that the register is clobbered and we no longer know its
13279 value. If INSN is zero, don't update reg_stat[].last_set; this is
13280 only permitted with VALUE also zero and is used to invalidate the
13281 register. */
13283 static void
13285 {
13291 /* If VALUE contains REG and we have a previous value for REG, substitute
13292 the previous value. */
13294 {
13295 rtx tem;
13297 /* Set things up so get_last_value is allowed to see anything set up to
13298 our insn. */
13302 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13303 it isn't going to be useful and will take a lot of time to process,
13304 so just use the CLOBBER. */
13307 {
13313 {
13314 /* If there are two or more occurrences of REG in VALUE,
13315 prevent the value from growing too much. */
13318 }
13321 }
13322 }
13324 /* For each register modified, show we don't know its value, that
13325 we don't know about its bitwise content, that its value has been
13326 updated, and that we don't know the location of the death of the
13327 register. */
13329 {
13341 }
13343 /* Mark registers that are being referenced in this value. */
13347 /* Now update the status of each register being set.
13348 If someone is using this register in this block, set this register
13349 to invalid since we will get confused between the two lives in this
13350 basic block. This makes using this register always invalid. In cse, we
13351 scan the table to invalidate all entries using this register, but this
13352 is too much work for us. */
13355 {
13361 else
13363 }
13365 /* The value being assigned might refer to X (like in "x++;"). In that
13366 case, we must replace it with (clobber (const_int 0)) to prevent
13367 infinite loops. */
13370 {
13374 }
13376 /* For the main register being modified, update the value, the mode, the
13377 nonzero bits, and the number of sign bit copies. */
13382 {
13390 rsp->last_set_sign_bit_copies
13392 }
13393 }
13395 /* Called via note_stores from record_dead_and_set_regs to handle one
13396 SET or CLOBBER in an insn. DATA is the instruction in which the
13397 set is occurring. */
13399 static void
13401 {
13408 {
13412 }
13415 {
13416 /* If we are setting the whole register, we know its value. Otherwise
13417 show that we don't know the value. We can handle a SUBREG if it's
13418 the low part, but we must be careful with paradoxical SUBREGs on
13419 RISC architectures because we cannot strip e.g. an extension around
13420 a load and record the naked load since the RTL middle-end considers
13421 that the upper bits are defined according to LOAD_EXTEND_OP. */
13428 BITS_PER_WORD)
13431 WORD_REGISTER_OPERATIONS
13437 else
13439 }
13441 /* Ignore pushes, they clobber nothing. */
13444 }
13446 /* Update the records of when each REG was most recently set or killed
13447 for the things done by INSN. This is the last thing done in processing
13448 INSN in the combiner loop.
13450 We update reg_stat[], in particular fields last_set, last_set_value,
13451 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13452 last_death, and also the similar information mem_last_set (which insn
13453 most recently modified memory) and last_call_luid (which insn was the
13454 most recent subroutine call). */
13456 static void
13458 {
13459 rtx link;
13463 {
13466 {
13471 {
13476 }
13477 }
13480 }
13483 {
13484 HARD_REG_SET callee_clobbers
13486 hard_reg_set_iterator hrsi;
13488 {
13491 /* ??? We could try to preserve some information from the last
13492 set of register I if the call doesn't actually clobber
13493 (reg:last_set_mode I), which might be true for ABIs with
13494 partial clobbers. However, it would be difficult to
13495 update last_set_nonzero_bits and last_sign_bit_copies
13496 to account for the part of I that actually was clobbered.
13497 It wouldn't help much anyway, since we rarely see this
13498 situation before RA. */
13508 }
13512 /* We can't combine into a call pattern. Remember, though, that
13513 the return value register is set at this LUID. We could
13514 still replace a register with the return value from the
13515 wrong subroutine call! */
13517 }
13518 else
13520 }
13522 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13523 register present in the SUBREG, so for each such SUBREG go back and
13524 adjust nonzero and sign bit information of the registers that are
13525 known to have some zero/sign bits set.
13527 This is needed because when combine blows the SUBREGs away, the
13528 information on zero/sign bits is lost and further combines can be
13529 missed because of that. */
13531 static void
13533 {
13535 rtx set;
13543 {
13552 {
13555 }
13559 {
13562 }
13565 {
13568 }
13569 else
13571 }
13572 }
13574 /* Check if X, a register, is known to contain a value already
13575 truncated to MODE. In this case we can use a subreg to refer to
13576 the truncated value even though in the generic case we would need
13577 an explicit truncation. */
13579 static bool
13581 {
13593 }
13595 /* If X is a hard reg or a subreg record the mode that the register is
13596 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13597 able to turn a truncate into a subreg using this information. Return true
13598 if traversing X is complete. */
13600 static bool
13602 {
13603 machine_mode truncated_mode;
13607 {
13619 }
13620 /* ??? For hard-regs we now record everything. We might be able to
13621 optimize this using last_set_mode. */
13624 else
13631 {
13634 }
13637 }
13639 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13640 the modes they are used in. This can help truning TRUNCATEs into
13641 SUBREGs. */
13643 static void
13645 {
13650 }
13652 /* Scan X for promoted SUBREGs. For each one found,
13653 note what it implies to the registers used in it. */
13655 static void
13657 {
13662 else
13663 {
13669 {
13679 }
13680 }
13681 }
13682 \f
13683 /* Verify that all the registers and memory references mentioned in *LOC are
13684 still valid. *LOC was part of a value set in INSN when label_tick was
13685 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13686 the invalid references with (clobber (const_int 0)) and return 1. This
13687 replacement is useful because we often can get useful information about
13688 the form of a value (e.g., if it was produced by a shift that always
13689 produces -1 or 0) even though we don't know exactly what registers it
13690 was produced from. */
13692 static int
13694 {
13701 {
13707 {
13710 /* If this is a pseudo-register that was only set once and not
13711 live at the beginning of the function, it is always valid. */
13715 && (!REGNO_REG_SET_P
13717 regno)))
13719 {
13723 }
13724 }
13727 }
13728 /* If this is a memory reference, make sure that there were no stores after
13729 it that might have clobbered the value. We don't have alias info, so we
13730 assume any store invalidates it. Moreover, we only have local UIDs, so
13731 we also assume that there were stores in the intervening basic blocks. */
13734 {
13738 }
13741 {
13743 {
13744 /* Check for identical subexpressions. If x contains
13745 identical subexpression we only have to traverse one of
13746 them. */
13748 {
13749 /* Note that at this point x0 has already been checked
13750 and found valid. */
13754 /* If x0 and x1 are identical then x is also valid. */
13758 /* If x1 is identical to a subexpression of x0 then
13759 while checking x0, x1 has already been checked. Thus
13760 it is valid and so as x. */
13765 /* If x0 is identical to a subexpression of x1 then x is
13766 valid iff the rest of x1 is valid. */
13769 return
13773 }
13778 }
13784 }
13786 /* If we haven't found a reason for it to be invalid, it is valid. */
13788 }
13790 /* Get the last value assigned to X, if known. Some registers
13791 in the value may be replaced with (clobber (const_int 0)) if their value
13792 is known longer known reliably. */
13794 static rtx
13796 {
13798 rtx value;
13801 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13802 then convert it to the desired mode. If this is a paradoxical SUBREG,
13803 we cannot predict what values the "extra" bits might have. */
13817 /* If we don't have a value, or if it isn't for this basic block and
13818 it's either a hard register, set more than once, or it's a live
13819 at the beginning of the function, return 0.
13821 Because if it's not live at the beginning of the function then the reg
13822 is always set before being used (is never used without being set).
13823 And, if it's set only once, and it's always set before use, then all
13824 uses must have the same last value, even if it's not from this basic
13825 block. */
13832 || REGNO_REG_SET_P
13836 /* If the value was set in a later insn than the ones we are processing,
13837 we can't use it even if the register was only set once. */
13842 /* If fewer bits were set than what we are asked for now, we cannot use
13843 the value. */
13848 /* If the value has all its registers valid, return it. */
13852 /* Otherwise, make a copy and replace any invalid register with
13853 (clobber (const_int 0)). If that fails for some reason, return 0. */
13860 }
13861 \f
13862 /* Define three variables used for communication between the following
13863 routines. */
13867 rtx reg_dead_reg;
13869 /* Function called via note_stores from reg_dead_at_p.
13871 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13872 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13874 static void
13876 {
13886 }
13888 /* Return nonzero if REG is known to be dead at INSN.
13890 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13891 referencing REG, it is dead. If we hit a SET referencing REG, it is
13892 live. Otherwise, see if it is live or dead at the start of the basic
13893 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13894 must be assumed to be always live. */
13896 static int
13898 {
13899 basic_block block;
13902 /* Set variables for reg_dead_at_p_1. */
13909 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13910 we allow the machine description to decide whether use-and-clobber
13911 patterns are OK. */
13913 {
13917 }
13919 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13920 beginning of basic block. */
13923 {
13925 {
13935 }
13941 }
13943 /* Look at live-in sets for the basic block that we were in. */
13949 }
13950 \f
13951 /* Note hard registers in X that are used. */
13953 static void
13955 {
13961 {
13965 CASE_CONST_ANY:
13970 /* CC0 must die in the insn after it is set, so we don't need to take
13971 special note of it here. */
13976 /* If we are clobbering a MEM, mark any hard registers inside the
13977 address as used. */
13984 /* A hard reg in a wide mode may really be multiple registers.
13985 If so, mark all of them just like the first. */
13987 {
13988 /* None of this applies to the stack, frame or arg pointers. */
13990 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13998 }
14002 {
14003 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
14004 the address. */
14016 }
14021 }
14023 /* Recursively scan the operands of this expression. */
14025 {
14029 {
14033 {
14038 }
14039 }
14040 }
14041 }
14042 \f
14043 /* Remove register number REGNO from the dead registers list of INSN.
14045 Return the note used to record the death, if there was one. */
14047 rtx
14049 {
14056 }
14058 /* For each register (hardware or pseudo) used within expression X, if its
14059 death is in an instruction with luid between FROM_LUID (inclusive) and
14060 TO_INSN (exclusive), put a REG_DEAD note for that register in the
14061 list headed by PNOTES.
14063 That said, don't move registers killed by maybe_kill_insn.
14065 This is done when X is being merged by combination into TO_INSN. These
14066 notes will then be distributed as needed. */
14068 static void
14071 {
14077 {
14081 /* If we do not know where the register died, it may still die between
14082 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14084 {
14089 {
14091 {
14095 }
14098 }
14099 }
14101 /* Don't move the register if it gets killed in between from and to. */
14110 {
14113 /* It is possible for the call above to return 0. This can occur
14114 when last_death points to I2 or I1 that we combined with.
14115 In that case make a new note.
14117 We must also check for the case where X is a hard register
14118 and NOTE is a death note for a range of hard registers
14119 including X. In that case, we must put REG_DEAD notes for
14120 the remaining registers in place of NOTE. */
14124 {
14133 }
14135 /* If we didn't find any note, or if we found a REG_DEAD note that
14136 covers only part of the given reg, and we have a multi-reg hard
14137 register, then to be safe we must check for REG_DEAD notes
14138 for each register other than the first. They could have
14139 their own REG_DEAD notes lying around. */
14146 {
14153 else
14159 }
14162 {
14165 }
14166 else
14168 }
14171 }
14174 {
14179 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14180 that accesses one word of a multi-word item, some
14181 piece of everything register in the expression is used by
14182 this insn, so remove any old death. */
14183 /* ??? So why do we test for equality of the sizes? */
14189 {
14192 }
14194 /* If this is some other SUBREG, we know it replaces the entire
14195 value, so use that as the destination. */
14199 /* If this is a MEM, adjust deaths of anything used in the address.
14200 For a REG (the only other possibility), the entire value is
14201 being replaced so the old value is not used in this insn. */
14207 }
14216 {
14218 {
14223 }
14226 }
14227 }
14228 \f
14229 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14230 pattern of an insn. X must be a REG. */
14232 static int
14234 {
14238 {
14240 rtx target;
14247 else
14264 }
14272 }
14273 \f
14274 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14275 as appropriate. I3 and I2 are the insns resulting from the combination
14276 insns including FROM (I2 may be zero).
14278 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14279 not need REG_DEAD notes because they are being substituted for. This
14280 saves searching in the most common cases.
14282 Each note in the list is either ignored or placed on some insns, depending
14283 on the type of note. */
14285 static void
14288 {
14290 rtx tem_note;
14294 {
14299 {
14302 /* Doesn't matter much where we put this, as long as it's somewhere.
14303 It is preferable to keep these notes on branches, which is most
14304 likely to be i3. */
14311 else
14312 {
14315 }
14319 /* These notes must remain with the call or trapping instruction. */
14324 else
14325 {
14331 /* ??? Otherwise assume we've combined things such that we
14332 can now prove that the instructions can't trap. Drop the
14333 note in this case. */
14334 }
14338 /* ??? How to distribute between i3-i1. Assume i3 contains the
14339 entire adjustment. Assert i3 contains at least some adjust. */
14341 {
14343 /* fixup_args_size_notes looks at REG_NORETURN note,
14344 so ensure the note is placed there first. */
14346 {
14350 {
14356 }
14357 }
14359 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14360 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14363 && !ACCUMULATE_OUTGOING_ARGS
14365 }
14373 /* These notes must remain with the call. It should not be
14374 possible for both I2 and I3 to be a call. */
14377 else
14378 {
14381 }
14385 /* Any clobbers for i3 may still exist, and so we must process
14386 REG_UNUSED notes from that insn.
14388 Any clobbers from i2 or i1 can only exist if they were added by
14389 recog_for_combine. In that case, recog_for_combine created the
14390 necessary REG_UNUSED notes. Trying to keep any original
14391 REG_UNUSED notes from these insns can cause incorrect output
14392 if it is for the same register as the original i3 dest.
14393 In that case, we will notice that the register is set in i3,
14394 and then add a REG_UNUSED note for the destination of i3, which
14395 is wrong. However, it is possible to have REG_UNUSED notes from
14396 i2 or i1 for register which were both used and clobbered, so
14397 we keep notes from i2 or i1 if they will turn into REG_DEAD
14398 notes. */
14400 /* If this register is set or clobbered in I3, put the note there
14401 unless there is one already. */
14403 {
14411 }
14412 /* Otherwise, if this register is used by I3, then this register
14413 now dies here, so we must put a REG_DEAD note here unless there
14414 is one already. */
14420 {
14423 }
14425 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14426 but we can't tell which at this point. We must reset any
14427 expectations we had about the value that was previously
14428 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14429 and, if appropriate, restore its previous value, but we
14430 don't have enough information for that at this point. */
14431 else
14432 {
14435 /* Otherwise, if this register is now referenced in i2
14436 then the register used to be modified in one of the
14437 original insns. If it was i3 (say, in an unused
14438 parallel), it's now completely gone, so the note can
14439 be discarded. But if it was modified in i2, i1 or i0
14440 and we still reference it in i2, then we're
14441 referencing the previous value, and since the
14442 register was modified and REG_UNUSED, we know that
14443 the previous value is now dead. So, if we only
14444 reference the register in i2, we change the note to
14445 REG_DEAD, to reflect the previous value. However, if
14446 we're also setting or clobbering the register as
14447 scratch, we know (because the register was not
14448 referenced in i3) that it's unused, just as it was
14449 unused before, and we place the note in i2. */
14452 {
14461 }
14462 }
14469 /* These notes say something about results of an insn. We can
14470 only support them if they used to be on I3 in which case they
14471 remain on I3. Otherwise they are ignored.
14473 If the note refers to an expression that is not a constant, we
14474 must also ignore the note since we cannot tell whether the
14475 equivalence is still true. It might be possible to do
14476 slightly better than this (we only have a problem if I2DEST
14477 or I1DEST is present in the expression), but it doesn't
14478 seem worth the trouble. */
14486 /* These notes say something about how a register is used. They must
14487 be present on any use of the register in I2 or I3. */
14492 {
14495 else
14497 }
14502 /* This can show up in several ways -- either directly in the
14503 pattern, or hidden off in the constant pool with (or without?)
14504 a REG_EQUAL note. */
14505 /* ??? Ignore the without-reg_equal-note problem for now. */
14517 {
14520 else
14522 }
14524 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14525 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14526 there. */
14531 {
14538 }
14544 {
14552 }
14556 /* This note says something about the value of a register prior
14557 to the execution of an insn. It is too much trouble to see
14558 if the note is still correct in all situations. It is better
14559 to simply delete it. */
14563 /* If we replaced the right hand side of FROM_INSN with a
14564 REG_EQUAL note, the original use of the dying register
14565 will not have been combined into I3 and I2. In such cases,
14566 FROM_INSN is guaranteed to be the first of the combined
14567 instructions, so we simply need to search back before
14568 FROM_INSN for the previous use or set of this register,
14569 then alter the notes there appropriately.
14571 If the register is used as an input in I3, it dies there.
14572 Similarly for I2, if it is nonzero and adjacent to I3.
14574 If the register is not used as an input in either I3 or I2
14575 and it is not one of the registers we were supposed to eliminate,
14576 there are two possibilities. We might have a non-adjacent I2
14577 or we might have somehow eliminated an additional register
14578 from a computation. For example, we might have had A & B where
14579 we discover that B will always be zero. In this case we will
14580 eliminate the reference to A.
14582 In both cases, we must search to see if we can find a previous
14583 use of A and put the death note there. */
14589 else
14590 {
14596 {
14597 /* If the new I2 sets the same register that is marked
14598 dead in the note, we do not in general know where to
14599 put the note. One important case we _can_ handle is
14600 when the note comes from I3. */
14603 else
14605 }
14612 && !(i2mod
14614 i2mod_old_rhs)))
14619 }
14622 {
14626 {
14628 {
14632 }
14634 /* If the register is being set at TEM_INSN, see if that is all
14635 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14636 into a REG_UNUSED note instead. Don't delete sets to
14637 global register vars. */
14641 {
14652 ;
14654 /* Verify that it was the set, and not a clobber that
14655 modified the register.
14657 CC0 targets must be careful to maintain setter/user
14658 pairs. If we cannot delete the setter due to side
14659 effects, mark the user with an UNUSED note instead
14660 of deleting it. */
14664 && (!HAVE_cc0
14668 {
14669 /* Move the notes and links of TEM_INSN elsewhere.
14670 This might delete other dead insns recursively.
14671 First set the pattern to something that won't use
14672 any register. */
14691 /* Delete the setter too. */
14693 {
14706 }
14707 }
14708 else
14709 {
14712 /* If there isn't already a REG_UNUSED note, put one
14713 here. Do not place a REG_DEAD note, even if
14714 the register is also used here; that would not
14715 match the algorithm used in lifetime analysis
14716 and can cause the consistency check in the
14717 scheduler to fail. */
14722 }
14723 }
14727 {
14730 /* If we are doing a 3->2 combination, and we have a
14731 register which formerly died in i3 and was not used
14732 by i2, which now no longer dies in i3 and is used in
14733 i2 but does not die in i2, and place is between i2
14734 and i3, then we may need to move a link from place to
14735 i2. */
14737 && from_insn
14740 {
14744 }
14746 }
14750 }
14752 }
14754 /* If the register is set or already dead at PLACE, we needn't do
14755 anything with this note if it is still a REG_DEAD note.
14756 We check here if it is set at all, not if is it totally replaced,
14757 which is what `dead_or_set_p' checks, so also check for it being
14758 set partially. */
14761 {
14767 {
14768 /* Unless the register previously died in PLACE, clear
14769 last_death. [I no longer understand why this is
14770 being done.] */
14774 }
14775 else
14778 /* If this is a death note for a hard reg that is occupying
14779 multiple registers, ensure that we are still using all
14780 parts of the object. If we find a piece of the object
14781 that is unused, we must arrange for an appropriate REG_DEAD
14782 note to be added for it. However, we can't just emit a USE
14783 and tag the note to it, since the register might actually
14784 be dead; so we recourse, and the recursive call then finds
14785 the previous insn that used this register. */
14788 {
14797 {
14800 }
14803 {
14804 /* Put only REG_DEAD notes for pieces that are
14805 not already dead or set. */
14809 {
14816 {
14818 NULL_RTX);
14822 NULL_RTX);
14823 }
14828 {
14830 {
14834 }
14838 {
14841 }
14842 }
14843 }
14846 }
14847 }
14848 }
14852 /* Any other notes should not be present at this point in the
14853 compilation. */
14855 }
14858 {
14862 /* Set added_notes_insn to the earliest insn we added a note to. */
14866 }
14869 {
14872 /* Set added_notes_insn to the earliest insn we added a note to. */
14876 }
14877 }
14878 }
14879 \f
14880 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14881 I3, I2, and I1 to new locations. This is also called to add a link
14882 pointing at I3 when I3's destination is changed. */
14884 static void
14886 {
14890 {
14897 /* If the insn that this link points to is a NOTE, ignore it. */
14906 {
14909 {
14925 }
14928 }
14929 else
14942 /* A LOG_LINK is defined as being placed on the first insn that uses
14943 a register and points to the insn that sets the register. Start
14944 searching at the next insn after the target of the link and stop
14945 when we reach a set of the register or the end of the basic block.
14947 Note that this correctly handles the link that used to point from
14948 I3 to I2. Also note that not much searching is typically done here
14949 since most links don't point very far away. */
14958 {
14962 }
14965 {
14968 }
14972 /* If we found a place to put the link, place it there unless there
14973 is already a link to the same insn as LINK at that point. */
14976 {
14984 {
14988 /* Set added_links_insn to the earliest insn we added a
14989 link to. */
14993 }
14994 }
14995 }
14996 }
14997 \f
14998 /* Check for any register or memory mentioned in EQUIV that is not
14999 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
15000 of EXPR where some registers may have been replaced by constants. */
15002 static bool
15004 {
15007 {
15012 }
15014 }
15015 \f
15016 DEBUG_FUNCTION void
15018 {
15019 fprintf
15021 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
15023 }
15025 void
15027 {
15028 fprintf
15030 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
15032 }
15033 \f
15034 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
15035 the reg-to-reg copy can usefully combine with later instructions, but we
15036 do not want to combine the hard reg into later instructions, for that
15037 restricts register allocation. */
15038 static void
15040 {
15041 basic_block bb;
15044 {
15048 {
15071 }
15072 }
15073 }
15075 /* Try combining insns through substitution. */
15076 static unsigned int
15078 {
15088 int rebuild_jump_labels_after_combine
15091 /* Combining insns may have turned an indirect jump into a
15092 direct jump. Rebuild the JUMP_LABEL fields of jumping
15093 instructions. */
15095 {
15102 }
15106 }
15111 {
15121 };
15124 {
15128 {}
15130 /* opt_pass methods: */
15133 {
15135 }
15141 rtl_opt_pass *
15143 {
15145 }