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(CPP_SPEC): add %(subtarget_cpp_spec).
[official-gcc.git] / gcc / longlong.h
blobe6071547ad77493b2892312244528ad1e622693f
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 92, 94, 95, 96, 1997 Free Software Foundation, Inc.
3
4 This definition file is free software; you can redistribute it
5 and/or modify it under the terms of the GNU General Public
6 License as published by the Free Software Foundation; either
7 version 2, or (at your option) any later version.
8
9 This definition file is distributed in the hope that it will be
10 useful, but WITHOUT ANY WARRANTY; without even the implied
11 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 See the GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330,
17 Boston, MA 02111-1307, USA. */
18
19 #ifndef SI_TYPE_SIZE
20 #define SI_TYPE_SIZE 32
21 #endif
22
23 #define __BITS4 (SI_TYPE_SIZE / 4)
24 #define __ll_B (1L << (SI_TYPE_SIZE / 2))
25 #define __ll_lowpart(t) ((USItype) (t) % __ll_B)
26 #define __ll_highpart(t) ((USItype) (t) / __ll_B)
27
28 /* Define auxiliary asm macros.
29
30 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand)
31 multiplies two USItype integers MULTIPLER and MULTIPLICAND,
32 and generates a two-part USItype product in HIGH_PROD and
33 LOW_PROD.
34
35 2) __umulsidi3(a,b) multiplies two USItype integers A and B,
36 and returns a UDItype product. This is just a variant of umul_ppmm.
37
38 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
39 denominator) divides a two-word unsigned integer, composed by the
40 integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and
41 places the quotient in QUOTIENT and the remainder in REMAINDER.
42 HIGH_NUMERATOR must be less than DENOMINATOR for correct operation.
43 If, in addition, the most significant bit of DENOMINATOR must be 1,
44 then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1.
45
46 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
47 denominator). Like udiv_qrnnd but the numbers are signed. The
48 quotient is rounded towards 0.
49
50 5) count_leading_zeros(count, x) counts the number of zero-bits from
51 the msb to the first non-zero bit. This is the number of steps X
52 needs to be shifted left to set the msb. Undefined for X == 0.
53
54 6) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
55 high_addend_2, low_addend_2) adds two two-word unsigned integers,
56 composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and
57 LOW_ADDEND_2 respectively. The result is placed in HIGH_SUM and
58 LOW_SUM. Overflow (i.e. carry out) is not stored anywhere, and is
59 lost.
60
61 7) sub_ddmmss(high_difference, low_difference, high_minuend,
62 low_minuend, high_subtrahend, low_subtrahend) subtracts two
63 two-word unsigned integers, composed by HIGH_MINUEND_1 and
64 LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2
65 respectively. The result is placed in HIGH_DIFFERENCE and
66 LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
67 and is lost.
68
69 If any of these macros are left undefined for a particular CPU,
70 C macros are used. */
71
72 /* The CPUs come in alphabetical order below.
73
74 Please add support for more CPUs here, or improve the current support
75 for the CPUs below!
76 (E.g. WE32100, IBM360.) */
77
78 #if defined (__GNUC__) && !defined (NO_ASM)
79
80 /* We sometimes need to clobber "cc" with gcc2, but that would not be
81 understood by gcc1. Use cpp to avoid major code duplication. */
82 #if __GNUC__ < 2
83 #define __CLOBBER_CC
84 #define __AND_CLOBBER_CC
85 #else /* __GNUC__ >= 2 */
86 #define __CLOBBER_CC : "cc"
87 #define __AND_CLOBBER_CC , "cc"
88 #endif /* __GNUC__ < 2 */
89
90 #if defined (__a29k__) || defined (_AM29K)
91 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
92 __asm__ ("add %1,%4,%5
93 addc %0,%2,%3" \
94 : "=r" ((USItype) (sh)), \
95 "=&r" ((USItype) (sl)) \
96 : "%r" ((USItype) (ah)), \
97 "rI" ((USItype) (bh)), \
98 "%r" ((USItype) (al)), \
99 "rI" ((USItype) (bl)))
100 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
101 __asm__ ("sub %1,%4,%5
102 subc %0,%2,%3" \
103 : "=r" ((USItype) (sh)), \
104 "=&r" ((USItype) (sl)) \
105 : "r" ((USItype) (ah)), \
106 "rI" ((USItype) (bh)), \
107 "r" ((USItype) (al)), \
108 "rI" ((USItype) (bl)))
109 #define umul_ppmm(xh, xl, m0, m1) \
110 do { \
111 USItype __m0 = (m0), __m1 = (m1); \
112 __asm__ ("multiplu %0,%1,%2" \
113 : "=r" ((USItype) (xl)) \
114 : "r" (__m0), \
115 "r" (__m1)); \
116 __asm__ ("multmu %0,%1,%2" \
117 : "=r" ((USItype) (xh)) \
118 : "r" (__m0), \
119 "r" (__m1)); \
120 } while (0)
121 #define udiv_qrnnd(q, r, n1, n0, d) \
122 __asm__ ("dividu %0,%3,%4" \
123 : "=r" ((USItype) (q)), \
124 "=q" ((USItype) (r)) \
125 : "1" ((USItype) (n1)), \
126 "r" ((USItype) (n0)), \
127 "r" ((USItype) (d)))
128 #define count_leading_zeros(count, x) \
129 __asm__ ("clz %0,%1" \
130 : "=r" ((USItype) (count)) \
131 : "r" ((USItype) (x)))
132 #endif /* __a29k__ */
133
134 #if defined (__arm__)
135 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
136 __asm__ ("adds %1, %4, %5
137 adc %0, %2, %3" \
138 : "=r" ((USItype) (sh)), \
139 "=&r" ((USItype) (sl)) \
140 : "%r" ((USItype) (ah)), \
141 "rI" ((USItype) (bh)), \
142 "%r" ((USItype) (al)), \
143 "rI" ((USItype) (bl)))
144 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
145 __asm__ ("subs %1, %4, %5
146 sbc %0, %2, %3" \
147 : "=r" ((USItype) (sh)), \
148 "=&r" ((USItype) (sl)) \
149 : "r" ((USItype) (ah)), \
150 "rI" ((USItype) (bh)), \
151 "r" ((USItype) (al)), \
152 "rI" ((USItype) (bl)))
153 #define umul_ppmm(xh, xl, a, b) \
154 {register USItype __t0, __t1, __t2; \
155 __asm__ ("%@ Inlined umul_ppmm
156 mov %2, %5, lsr #16
157 mov %0, %6, lsr #16
158 bic %3, %5, %2, lsl #16
159 bic %4, %6, %0, lsl #16
160 mul %1, %3, %4
161 mul %4, %2, %4
162 mul %3, %0, %3
163 mul %0, %2, %0
164 adds %3, %4, %3
165 addcs %0, %0, #65536
166 adds %1, %1, %3, lsl #16
167 adc %0, %0, %3, lsr #16" \
168 : "=&r" ((USItype) (xh)), \
169 "=r" ((USItype) (xl)), \
170 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
171 : "r" ((USItype) (a)), \
172 "r" ((USItype) (b)));}
173 #define UMUL_TIME 20
174 #define UDIV_TIME 100
175 #endif /* __arm__ */
176
177 #if defined (__clipper__)
178 #define umul_ppmm(w1, w0, u, v) \
179 ({union {UDItype __ll; \
180 struct {USItype __l, __h;} __i; \
181 } __xx; \
182 __asm__ ("mulwux %2,%0" \
183 : "=r" (__xx.__ll) \
184 : "%0" ((USItype) (u)), \
185 "r" ((USItype) (v))); \
186 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
187 #define smul_ppmm(w1, w0, u, v) \
188 ({union {DItype __ll; \
189 struct {SItype __l, __h;} __i; \
190 } __xx; \
191 __asm__ ("mulwx %2,%0" \
192 : "=r" (__xx.__ll) \
193 : "%0" ((SItype) (u)), \
194 "r" ((SItype) (v))); \
195 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
196 #define __umulsidi3(u, v) \
197 ({UDItype __w; \
198 __asm__ ("mulwux %2,%0" \
199 : "=r" (__w) \
200 : "%0" ((USItype) (u)), \
201 "r" ((USItype) (v))); \
202 __w; })
203 #endif /* __clipper__ */
204
205 #if defined (__gmicro__)
206 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
207 __asm__ ("add.w %5,%1
208 addx %3,%0" \
209 : "=g" ((USItype) (sh)), \
210 "=&g" ((USItype) (sl)) \
211 : "%0" ((USItype) (ah)), \
212 "g" ((USItype) (bh)), \
213 "%1" ((USItype) (al)), \
214 "g" ((USItype) (bl)))
215 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
216 __asm__ ("sub.w %5,%1
217 subx %3,%0" \
218 : "=g" ((USItype) (sh)), \
219 "=&g" ((USItype) (sl)) \
220 : "0" ((USItype) (ah)), \
221 "g" ((USItype) (bh)), \
222 "1" ((USItype) (al)), \
223 "g" ((USItype) (bl)))
224 #define umul_ppmm(ph, pl, m0, m1) \
225 __asm__ ("mulx %3,%0,%1" \
226 : "=g" ((USItype) (ph)), \
227 "=r" ((USItype) (pl)) \
228 : "%0" ((USItype) (m0)), \
229 "g" ((USItype) (m1)))
230 #define udiv_qrnnd(q, r, nh, nl, d) \
231 __asm__ ("divx %4,%0,%1" \
232 : "=g" ((USItype) (q)), \
233 "=r" ((USItype) (r)) \
234 : "1" ((USItype) (nh)), \
235 "0" ((USItype) (nl)), \
236 "g" ((USItype) (d)))
237 #define count_leading_zeros(count, x) \
238 __asm__ ("bsch/1 %1,%0" \
239 : "=g" (count) \
240 : "g" ((USItype) (x)), \
241 "0" ((USItype) 0))
242 #endif
243
244 #if defined (__hppa)
245 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
246 __asm__ ("add %4,%5,%1
247 addc %2,%3,%0" \
248 : "=r" ((USItype) (sh)), \
249 "=&r" ((USItype) (sl)) \
250 : "%rM" ((USItype) (ah)), \
251 "rM" ((USItype) (bh)), \
252 "%rM" ((USItype) (al)), \
253 "rM" ((USItype) (bl)))
254 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
255 __asm__ ("sub %4,%5,%1
256 subb %2,%3,%0" \
257 : "=r" ((USItype) (sh)), \
258 "=&r" ((USItype) (sl)) \
259 : "rM" ((USItype) (ah)), \
260 "rM" ((USItype) (bh)), \
261 "rM" ((USItype) (al)), \
262 "rM" ((USItype) (bl)))
263 #if defined (_PA_RISC1_1)
264 #define umul_ppmm(w1, w0, u, v) \
265 do { \
266 union \
267 { \
268 UDItype __f; \
269 struct {USItype __w1, __w0;} __w1w0; \
270 } __t; \
271 __asm__ ("xmpyu %1,%2,%0" \
272 : "=x" (__t.__f) \
273 : "x" ((USItype) (u)), \
274 "x" ((USItype) (v))); \
275 (w1) = __t.__w1w0.__w1; \
276 (w0) = __t.__w1w0.__w0; \
277 } while (0)
278 #define UMUL_TIME 8
279 #else
280 #define UMUL_TIME 30
281 #endif
282 #define UDIV_TIME 40
283 #define count_leading_zeros(count, x) \
284 do { \
285 USItype __tmp; \
286 __asm__ ( \
287 "ldi 1,%0
288 extru,= %1,15,16,%%r0 ; Bits 31..16 zero?
289 extru,tr %1,15,16,%1 ; No. Shift down, skip add.
290 ldo 16(%0),%0 ; Yes. Perform add.
291 extru,= %1,23,8,%%r0 ; Bits 15..8 zero?
292 extru,tr %1,23,8,%1 ; No. Shift down, skip add.
293 ldo 8(%0),%0 ; Yes. Perform add.
294 extru,= %1,27,4,%%r0 ; Bits 7..4 zero?
295 extru,tr %1,27,4,%1 ; No. Shift down, skip add.
296 ldo 4(%0),%0 ; Yes. Perform add.
297 extru,= %1,29,2,%%r0 ; Bits 3..2 zero?
298 extru,tr %1,29,2,%1 ; No. Shift down, skip add.
299 ldo 2(%0),%0 ; Yes. Perform add.
300 extru %1,30,1,%1 ; Extract bit 1.
301 sub %0,%1,%0 ; Subtract it.
302 " : "=r" (count), "=r" (__tmp) : "1" (x)); \
303 } while (0)
304 #endif
305
306 #if defined (__i386__) || defined (__i486__)
307 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
308 __asm__ ("addl %5,%1
309 adcl %3,%0" \
310 : "=r" ((USItype) (sh)), \
311 "=&r" ((USItype) (sl)) \
312 : "%0" ((USItype) (ah)), \
313 "g" ((USItype) (bh)), \
314 "%1" ((USItype) (al)), \
315 "g" ((USItype) (bl)))
316 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
317 __asm__ ("subl %5,%1
318 sbbl %3,%0" \
319 : "=r" ((USItype) (sh)), \
320 "=&r" ((USItype) (sl)) \
321 : "0" ((USItype) (ah)), \
322 "g" ((USItype) (bh)), \
323 "1" ((USItype) (al)), \
324 "g" ((USItype) (bl)))
325 #define umul_ppmm(w1, w0, u, v) \
326 __asm__ ("mull %3" \
327 : "=a" ((USItype) (w0)), \
328 "=d" ((USItype) (w1)) \
329 : "%0" ((USItype) (u)), \
330 "rm" ((USItype) (v)))
331 #define udiv_qrnnd(q, r, n1, n0, d) \
332 __asm__ ("divl %4" \
333 : "=a" ((USItype) (q)), \
334 "=d" ((USItype) (r)) \
335 : "0" ((USItype) (n0)), \
336 "1" ((USItype) (n1)), \
337 "rm" ((USItype) (d)))
338 #define count_leading_zeros(count, x) \
339 do { \
340 USItype __cbtmp; \
341 __asm__ ("bsrl %1,%0" \
342 : "=r" (__cbtmp) : "rm" ((USItype) (x))); \
343 (count) = __cbtmp ^ 31; \
344 } while (0)
345 #define UMUL_TIME 40
346 #define UDIV_TIME 40
347 #endif /* 80x86 */
348
349 #if defined (__i860__)
350 #if 0
351 /* Make sure these patterns really improve the code before
352 switching them on. */
353 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
354 do { \
355 union \
356 { \
357 DItype __ll; \
358 struct {USItype __l, __h;} __i; \
359 } __a, __b, __s; \
360 __a.__i.__l = (al); \
361 __a.__i.__h = (ah); \
362 __b.__i.__l = (bl); \
363 __b.__i.__h = (bh); \
364 __asm__ ("fiadd.dd %1,%2,%0" \
365 : "=f" (__s.__ll) \
366 : "%f" (__a.__ll), "f" (__b.__ll)); \
367 (sh) = __s.__i.__h; \
368 (sl) = __s.__i.__l; \
369 } while (0)
370 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
371 do { \
372 union \
373 { \
374 DItype __ll; \
375 struct {USItype __l, __h;} __i; \
376 } __a, __b, __s; \
377 __a.__i.__l = (al); \
378 __a.__i.__h = (ah); \
379 __b.__i.__l = (bl); \
380 __b.__i.__h = (bh); \
381 __asm__ ("fisub.dd %1,%2,%0" \
382 : "=f" (__s.__ll) \
383 : "%f" (__a.__ll), "f" (__b.__ll)); \
384 (sh) = __s.__i.__h; \
385 (sl) = __s.__i.__l; \
386 } while (0)
387 #endif
388 #endif /* __i860__ */
389
390 #if defined (__i960__)
391 #define umul_ppmm(w1, w0, u, v) \
392 ({union {UDItype __ll; \
393 struct {USItype __l, __h;} __i; \
394 } __xx; \
395 __asm__ ("emul %2,%1,%0" \
396 : "=d" (__xx.__ll) \
397 : "%dI" ((USItype) (u)), \
398 "dI" ((USItype) (v))); \
399 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
400 #define __umulsidi3(u, v) \
401 ({UDItype __w; \
402 __asm__ ("emul %2,%1,%0" \
403 : "=d" (__w) \
404 : "%dI" ((USItype) (u)), \
405 "dI" ((USItype) (v))); \
406 __w; })
407 #endif /* __i960__ */
408
409 #if defined (__M32R__)
410 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
411 /* The cmp clears the condition bit. */ \
412 __asm__ ("cmp %0,%0
413 addx %%5,%1
414 addx %%3,%0" \
415 : "=r" ((USItype) (sh)), \
416 "=&r" ((USItype) (sl)) \
417 : "%0" ((USItype) (ah)), \
418 "r" ((USItype) (bh)), \
419 "%1" ((USItype) (al)), \
420 "r" ((USItype) (bl)) \
421 : "cbit")
422 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
423 /* The cmp clears the condition bit. */ \
424 __asm__ ("cmp %0,%0
425 subx %5,%1
426 subx %3,%0" \
427 : "=r" ((USItype) (sh)), \
428 "=&r" ((USItype) (sl)) \
429 : "0" ((USItype) (ah)), \
430 "r" ((USItype) (bh)), \
431 "1" ((USItype) (al)), \
432 "r" ((USItype) (bl)) \
433 : "cbit")
434 #endif /* __M32R__ */
435
436 #if defined (__mc68000__)
437 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
438 __asm__ ("add%.l %5,%1
439 addx%.l %3,%0" \
440 : "=d" ((USItype) (sh)), \
441 "=&d" ((USItype) (sl)) \
442 : "%0" ((USItype) (ah)), \
443 "d" ((USItype) (bh)), \
444 "%1" ((USItype) (al)), \
445 "g" ((USItype) (bl)))
446 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
447 __asm__ ("sub%.l %5,%1
448 subx%.l %3,%0" \
449 : "=d" ((USItype) (sh)), \
450 "=&d" ((USItype) (sl)) \
451 : "0" ((USItype) (ah)), \
452 "d" ((USItype) (bh)), \
453 "1" ((USItype) (al)), \
454 "g" ((USItype) (bl)))
455
456 /* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */
457 #if defined (__mc68020__) || defined(mc68020) \
458 || defined(__mc68030__) || defined(mc68030) \
459 || defined(__mc68040__) || defined(mc68040) \
460 || defined(__mc68332__) || defined(mc68332) \
461 || defined(__NeXT__)
462 #define umul_ppmm(w1, w0, u, v) \
463 __asm__ ("mulu%.l %3,%1:%0" \
464 : "=d" ((USItype) (w0)), \
465 "=d" ((USItype) (w1)) \
466 : "%0" ((USItype) (u)), \
467 "dmi" ((USItype) (v)))
468 #define UMUL_TIME 45
469 #define udiv_qrnnd(q, r, n1, n0, d) \
470 __asm__ ("divu%.l %4,%1:%0" \
471 : "=d" ((USItype) (q)), \
472 "=d" ((USItype) (r)) \
473 : "0" ((USItype) (n0)), \
474 "1" ((USItype) (n1)), \
475 "dmi" ((USItype) (d)))
476 #define UDIV_TIME 90
477 #define sdiv_qrnnd(q, r, n1, n0, d) \
478 __asm__ ("divs%.l %4,%1:%0" \
479 : "=d" ((USItype) (q)), \
480 "=d" ((USItype) (r)) \
481 : "0" ((USItype) (n0)), \
482 "1" ((USItype) (n1)), \
483 "dmi" ((USItype) (d)))
484
485 #else /* not mc68020 */
486 #if !defined(__mcf5200__)
487 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
488 #define umul_ppmm(xh, xl, a, b) \
489 __asm__ ("| Inlined umul_ppmm
490 move%.l %2,%/d0
491 move%.l %3,%/d1
492 move%.l %/d0,%/d2
493 swap %/d0
494 move%.l %/d1,%/d3
495 swap %/d1
496 move%.w %/d2,%/d4
497 mulu %/d3,%/d4
498 mulu %/d1,%/d2
499 mulu %/d0,%/d3
500 mulu %/d0,%/d1
501 move%.l %/d4,%/d0
502 eor%.w %/d0,%/d0
503 swap %/d0
504 add%.l %/d0,%/d2
505 add%.l %/d3,%/d2
506 jcc 1f
507 add%.l %#65536,%/d1
508 1: swap %/d2
509 moveq %#0,%/d0
510 move%.w %/d2,%/d0
511 move%.w %/d4,%/d2
512 move%.l %/d2,%1
513 add%.l %/d1,%/d0
514 move%.l %/d0,%0" \
515 : "=g" ((USItype) (xh)), \
516 "=g" ((USItype) (xl)) \
517 : "g" ((USItype) (a)), \
518 "g" ((USItype) (b)) \
519 : "d0", "d1", "d2", "d3", "d4")
520 #define UMUL_TIME 100
521 #define UDIV_TIME 400
522 #endif /* not mcf5200 */
523 #endif /* not mc68020 */
524
525 /* The '020, '030, '040 and '060 have bitfield insns. */
526 #if defined (__mc68020__) || defined(mc68020) \
527 || defined(__mc68030__) || defined(mc68030) \
528 || defined(__mc68040__) || defined(mc68040) \
529 || defined(__mc68060__) || defined(mc68060) \
530 || defined(__NeXT__)
531 #define count_leading_zeros(count, x) \
532 __asm__ ("bfffo %1{%b2:%b2},%0" \
533 : "=d" ((USItype) (count)) \
534 : "od" ((USItype) (x)), "n" (0))
535 #endif
536 #endif /* mc68000 */
537
538 #if defined (__m88000__)
539 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
540 __asm__ ("addu.co %1,%r4,%r5
541 addu.ci %0,%r2,%r3" \
542 : "=r" ((USItype) (sh)), \
543 "=&r" ((USItype) (sl)) \
544 : "%rJ" ((USItype) (ah)), \
545 "rJ" ((USItype) (bh)), \
546 "%rJ" ((USItype) (al)), \
547 "rJ" ((USItype) (bl)))
548 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
549 __asm__ ("subu.co %1,%r4,%r5
550 subu.ci %0,%r2,%r3" \
551 : "=r" ((USItype) (sh)), \
552 "=&r" ((USItype) (sl)) \
553 : "rJ" ((USItype) (ah)), \
554 "rJ" ((USItype) (bh)), \
555 "rJ" ((USItype) (al)), \
556 "rJ" ((USItype) (bl)))
557 #define count_leading_zeros(count, x) \
558 do { \
559 USItype __cbtmp; \
560 __asm__ ("ff1 %0,%1" \
561 : "=r" (__cbtmp) \
562 : "r" ((USItype) (x))); \
563 (count) = __cbtmp ^ 31; \
564 } while (0)
565 #if defined (__mc88110__)
566 #define umul_ppmm(wh, wl, u, v) \
567 do { \
568 union {UDItype __ll; \
569 struct {USItype __h, __l;} __i; \
570 } __xx; \
571 __asm__ ("mulu.d %0,%1,%2" \
572 : "=r" (__xx.__ll) \
573 : "r" ((USItype) (u)), \
574 "r" ((USItype) (v))); \
575 (wh) = __xx.__i.__h; \
576 (wl) = __xx.__i.__l; \
577 } while (0)
578 #define udiv_qrnnd(q, r, n1, n0, d) \
579 ({union {UDItype __ll; \
580 struct {USItype __h, __l;} __i; \
581 } __xx; \
582 USItype __q; \
583 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
584 __asm__ ("divu.d %0,%1,%2" \
585 : "=r" (__q) \
586 : "r" (__xx.__ll), \
587 "r" ((USItype) (d))); \
588 (r) = (n0) - __q * (d); (q) = __q; })
589 #define UMUL_TIME 5
590 #define UDIV_TIME 25
591 #else
592 #define UMUL_TIME 17
593 #define UDIV_TIME 150
594 #endif /* __mc88110__ */
595 #endif /* __m88000__ */
596
597 #if defined (__mips__)
598 #define umul_ppmm(w1, w0, u, v) \
599 __asm__ ("multu %2,%3" \
600 : "=l" ((USItype) (w0)), \
601 "=h" ((USItype) (w1)) \
602 : "d" ((USItype) (u)), \
603 "d" ((USItype) (v)))
604 #define UMUL_TIME 10
605 #define UDIV_TIME 100
606 #endif /* __mips__ */
607
608 #if defined (__ns32000__)
609 #define umul_ppmm(w1, w0, u, v) \
610 ({union {UDItype __ll; \
611 struct {USItype __l, __h;} __i; \
612 } __xx; \
613 __asm__ ("meid %2,%0" \
614 : "=g" (__xx.__ll) \
615 : "%0" ((USItype) (u)), \
616 "g" ((USItype) (v))); \
617 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
618 #define __umulsidi3(u, v) \
619 ({UDItype __w; \
620 __asm__ ("meid %2,%0" \
621 : "=g" (__w) \
622 : "%0" ((USItype) (u)), \
623 "g" ((USItype) (v))); \
624 __w; })
625 #define udiv_qrnnd(q, r, n1, n0, d) \
626 ({union {UDItype __ll; \
627 struct {USItype __l, __h;} __i; \
628 } __xx; \
629 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
630 __asm__ ("deid %2,%0" \
631 : "=g" (__xx.__ll) \
632 : "0" (__xx.__ll), \
633 "g" ((USItype) (d))); \
634 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
635 #endif /* __ns32000__ */
636
637 #if (defined (_ARCH_PPC) || defined (_IBMR2)) && W_TYPE_SIZE == 32
638 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
639 do { \
640 if (__builtin_constant_p (bh) && (bh) == 0) \
641 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
642 : "=r" ((USItype) (sh)), \
643 "=&r" ((USItype) (sl)) \
644 : "%r" ((USItype) (ah)), \
645 "%r" ((USItype) (al)), \
646 "rI" ((USItype) (bl))); \
647 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
648 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
649 : "=r" ((USItype) (sh)), \
650 "=&r" ((USItype) (sl)) \
651 : "%r" ((USItype) (ah)), \
652 "%r" ((USItype) (al)), \
653 "rI" ((USItype) (bl))); \
654 else \
655 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
656 : "=r" ((USItype) (sh)), \
657 "=&r" ((USItype) (sl)) \
658 : "%r" ((USItype) (ah)), \
659 "r" ((USItype) (bh)), \
660 "%r" ((USItype) (al)), \
661 "rI" ((USItype) (bl))); \
662 } while (0)
663 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
664 do { \
665 if (__builtin_constant_p (ah) && (ah) == 0) \
666 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
667 : "=r" ((USItype) (sh)), \
668 "=&r" ((USItype) (sl)) \
669 : "r" ((USItype) (bh)), \
670 "rI" ((USItype) (al)), \
671 "r" ((USItype) (bl))); \
672 else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0) \
673 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
674 : "=r" ((USItype) (sh)), \
675 "=&r" ((USItype) (sl)) \
676 : "r" ((USItype) (bh)), \
677 "rI" ((USItype) (al)), \
678 "r" ((USItype) (bl))); \
679 else if (__builtin_constant_p (bh) && (bh) == 0) \
680 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
681 : "=r" ((USItype) (sh)), \
682 "=&r" ((USItype) (sl)) \
683 : "r" ((USItype) (ah)), \
684 "rI" ((USItype) (al)), \
685 "r" ((USItype) (bl))); \
686 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
687 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
688 : "=r" ((USItype) (sh)), \
689 "=&r" ((USItype) (sl)) \
690 : "r" ((USItype) (ah)), \
691 "rI" ((USItype) (al)), \
692 "r" ((USItype) (bl))); \
693 else \
694 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
695 : "=r" ((USItype) (sh)), \
696 "=&r" ((USItype) (sl)) \
697 : "r" ((USItype) (ah)), \
698 "r" ((USItype) (bh)), \
699 "rI" ((USItype) (al)), \
700 "r" ((USItype) (bl))); \
701 } while (0)
702 #define count_leading_zeros(count, x) \
703 __asm__ ("{cntlz|cntlzw} %0,%1" \
704 : "=r" ((USItype) (count)) \
705 : "r" ((USItype) (x)))
706 #if defined (_ARCH_PPC)
707 #define umul_ppmm(ph, pl, m0, m1) \
708 do { \
709 USItype __m0 = (m0), __m1 = (m1); \
710 __asm__ ("mulhwu %0,%1,%2" \
711 : "=r" ((USItype) ph) \
712 : "%r" (__m0), \
713 "r" (__m1)); \
714 (pl) = __m0 * __m1; \
715 } while (0)
716 #define UMUL_TIME 15
717 #define smul_ppmm(ph, pl, m0, m1) \
718 do { \
719 SItype __m0 = (m0), __m1 = (m1); \
720 __asm__ ("mulhw %0,%1,%2" \
721 : "=r" ((SItype) ph) \
722 : "%r" (__m0), \
723 "r" (__m1)); \
724 (pl) = __m0 * __m1; \
725 } while (0)
726 #define SMUL_TIME 14
727 #define UDIV_TIME 120
728 #else
729 #define umul_ppmm(xh, xl, m0, m1) \
730 do { \
731 USItype __m0 = (m0), __m1 = (m1); \
732 __asm__ ("mul %0,%2,%3" \
733 : "=r" ((USItype) (xh)), \
734 "=q" ((USItype) (xl)) \
735 : "r" (__m0), \
736 "r" (__m1)); \
737 (xh) += ((((SItype) __m0 >> 31) & __m1) \
738 + (((SItype) __m1 >> 31) & __m0)); \
739 } while (0)
740 #define UMUL_TIME 8
741 #define smul_ppmm(xh, xl, m0, m1) \
742 __asm__ ("mul %0,%2,%3" \
743 : "=r" ((SItype) (xh)), \
744 "=q" ((SItype) (xl)) \
745 : "r" (m0), \
746 "r" (m1))
747 #define SMUL_TIME 4
748 #define sdiv_qrnnd(q, r, nh, nl, d) \
749 __asm__ ("div %0,%2,%4" \
750 : "=r" ((SItype) (q)), "=q" ((SItype) (r)) \
751 : "r" ((SItype) (nh)), "1" ((SItype) (nl)), "r" ((SItype) (d)))
752 #define UDIV_TIME 100
753 #endif
754 #endif /* Power architecture variants. */
755
756 #if defined (__pyr__)
757 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
758 __asm__ ("addw %5,%1
759 addwc %3,%0" \
760 : "=r" ((USItype) (sh)), \
761 "=&r" ((USItype) (sl)) \
762 : "%0" ((USItype) (ah)), \
763 "g" ((USItype) (bh)), \
764 "%1" ((USItype) (al)), \
765 "g" ((USItype) (bl)))
766 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
767 __asm__ ("subw %5,%1
768 subwb %3,%0" \
769 : "=r" ((USItype) (sh)), \
770 "=&r" ((USItype) (sl)) \
771 : "0" ((USItype) (ah)), \
772 "g" ((USItype) (bh)), \
773 "1" ((USItype) (al)), \
774 "g" ((USItype) (bl)))
775 /* This insn works on Pyramids with AP, XP, or MI CPUs, but not with SP. */
776 #define umul_ppmm(w1, w0, u, v) \
777 ({union {UDItype __ll; \
778 struct {USItype __h, __l;} __i; \
779 } __xx; \
780 __asm__ ("movw %1,%R0
781 uemul %2,%0" \
782 : "=&r" (__xx.__ll) \
783 : "g" ((USItype) (u)), \
784 "g" ((USItype) (v))); \
785 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
786 #endif /* __pyr__ */
787
788 #if defined (__ibm032__) /* RT/ROMP */
789 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
790 __asm__ ("a %1,%5
791 ae %0,%3" \
792 : "=r" ((USItype) (sh)), \
793 "=&r" ((USItype) (sl)) \
794 : "%0" ((USItype) (ah)), \
795 "r" ((USItype) (bh)), \
796 "%1" ((USItype) (al)), \
797 "r" ((USItype) (bl)))
798 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
799 __asm__ ("s %1,%5
800 se %0,%3" \
801 : "=r" ((USItype) (sh)), \
802 "=&r" ((USItype) (sl)) \
803 : "0" ((USItype) (ah)), \
804 "r" ((USItype) (bh)), \
805 "1" ((USItype) (al)), \
806 "r" ((USItype) (bl)))
807 #define umul_ppmm(ph, pl, m0, m1) \
808 do { \
809 USItype __m0 = (m0), __m1 = (m1); \
810 __asm__ ( \
811 "s r2,r2
812 mts r10,%2
813 m r2,%3
814 m r2,%3
815 m r2,%3
816 m r2,%3
817 m r2,%3
818 m r2,%3
819 m r2,%3
820 m r2,%3
821 m r2,%3
822 m r2,%3
823 m r2,%3
824 m r2,%3
825 m r2,%3
826 m r2,%3
827 m r2,%3
828 m r2,%3
829 cas %0,r2,r0
830 mfs r10,%1" \
831 : "=r" ((USItype) (ph)), \
832 "=r" ((USItype) (pl)) \
833 : "%r" (__m0), \
834 "r" (__m1) \
835 : "r2"); \
836 (ph) += ((((SItype) __m0 >> 31) & __m1) \
837 + (((SItype) __m1 >> 31) & __m0)); \
838 } while (0)
839 #define UMUL_TIME 20
840 #define UDIV_TIME 200
841 #define count_leading_zeros(count, x) \
842 do { \
843 if ((x) >= 0x10000) \
844 __asm__ ("clz %0,%1" \
845 : "=r" ((USItype) (count)) \
846 : "r" ((USItype) (x) >> 16)); \
847 else \
848 { \
849 __asm__ ("clz %0,%1" \
850 : "=r" ((USItype) (count)) \
851 : "r" ((USItype) (x))); \
852 (count) += 16; \
853 } \
854 } while (0)
855 #endif
856
857 #if defined (__sparc__)
858 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
859 __asm__ ("addcc %r4,%5,%1
860 addx %r2,%3,%0" \
861 : "=r" ((USItype) (sh)), \
862 "=&r" ((USItype) (sl)) \
863 : "%rJ" ((USItype) (ah)), \
864 "rI" ((USItype) (bh)), \
865 "%rJ" ((USItype) (al)), \
866 "rI" ((USItype) (bl)) \
867 __CLOBBER_CC)
868 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
869 __asm__ ("subcc %r4,%5,%1
870 subx %r2,%3,%0" \
871 : "=r" ((USItype) (sh)), \
872 "=&r" ((USItype) (sl)) \
873 : "rJ" ((USItype) (ah)), \
874 "rI" ((USItype) (bh)), \
875 "rJ" ((USItype) (al)), \
876 "rI" ((USItype) (bl)) \
877 __CLOBBER_CC)
878 #if defined (__sparc_v8__)
879 #define umul_ppmm(w1, w0, u, v) \
880 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
881 : "=r" ((USItype) (w1)), \
882 "=r" ((USItype) (w0)) \
883 : "r" ((USItype) (u)), \
884 "r" ((USItype) (v)))
885 #define udiv_qrnnd(q, r, n1, n0, d) \
886 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
887 : "=&r" ((USItype) (q)), \
888 "=&r" ((USItype) (r)) \
889 : "r" ((USItype) (n1)), \
890 "r" ((USItype) (n0)), \
891 "r" ((USItype) (d)))
892 #else
893 #if defined (__sparclite__)
894 /* This has hardware multiply but not divide. It also has two additional
895 instructions scan (ffs from high bit) and divscc. */
896 #define umul_ppmm(w1, w0, u, v) \
897 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
898 : "=r" ((USItype) (w1)), \
899 "=r" ((USItype) (w0)) \
900 : "r" ((USItype) (u)), \
901 "r" ((USItype) (v)))
902 #define udiv_qrnnd(q, r, n1, n0, d) \
903 __asm__ ("! Inlined udiv_qrnnd
904 wr %%g0,%2,%%y ! Not a delayed write for sparclite
905 tst %%g0
906 divscc %3,%4,%%g1
907 divscc %%g1,%4,%%g1
908 divscc %%g1,%4,%%g1
909 divscc %%g1,%4,%%g1
910 divscc %%g1,%4,%%g1
911 divscc %%g1,%4,%%g1
912 divscc %%g1,%4,%%g1
913 divscc %%g1,%4,%%g1
914 divscc %%g1,%4,%%g1
915 divscc %%g1,%4,%%g1
916 divscc %%g1,%4,%%g1
917 divscc %%g1,%4,%%g1
918 divscc %%g1,%4,%%g1
919 divscc %%g1,%4,%%g1
920 divscc %%g1,%4,%%g1
921 divscc %%g1,%4,%%g1
922 divscc %%g1,%4,%%g1
923 divscc %%g1,%4,%%g1
924 divscc %%g1,%4,%%g1
925 divscc %%g1,%4,%%g1
926 divscc %%g1,%4,%%g1
927 divscc %%g1,%4,%%g1
928 divscc %%g1,%4,%%g1
929 divscc %%g1,%4,%%g1
930 divscc %%g1,%4,%%g1
931 divscc %%g1,%4,%%g1
932 divscc %%g1,%4,%%g1
933 divscc %%g1,%4,%%g1
934 divscc %%g1,%4,%%g1
935 divscc %%g1,%4,%%g1
936 divscc %%g1,%4,%%g1
937 divscc %%g1,%4,%0
938 rd %%y,%1
939 bl,a 1f
940 add %1,%4,%1
941 1: ! End of inline udiv_qrnnd" \
942 : "=r" ((USItype) (q)), \
943 "=r" ((USItype) (r)) \
944 : "r" ((USItype) (n1)), \
945 "r" ((USItype) (n0)), \
946 "rI" ((USItype) (d)) \
947 : "%g1" __AND_CLOBBER_CC)
948 #define UDIV_TIME 37
949 #define count_leading_zeros(count, x) \
950 __asm__ ("scan %1,0,%0" \
951 : "=r" ((USItype) (x)) \
952 : "r" ((USItype) (count)))
953 #else
954 /* SPARC without integer multiplication and divide instructions.
955 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
956 #define umul_ppmm(w1, w0, u, v) \
957 __asm__ ("! Inlined umul_ppmm
958 wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr
959 sra %3,31,%%g2 ! Don't move this insn
960 and %2,%%g2,%%g2 ! Don't move this insn
961 andcc %%g0,0,%%g1 ! Don't move this insn
962 mulscc %%g1,%3,%%g1
963 mulscc %%g1,%3,%%g1
964 mulscc %%g1,%3,%%g1
965 mulscc %%g1,%3,%%g1
966 mulscc %%g1,%3,%%g1
967 mulscc %%g1,%3,%%g1
968 mulscc %%g1,%3,%%g1
969 mulscc %%g1,%3,%%g1
970 mulscc %%g1,%3,%%g1
971 mulscc %%g1,%3,%%g1
972 mulscc %%g1,%3,%%g1
973 mulscc %%g1,%3,%%g1
974 mulscc %%g1,%3,%%g1
975 mulscc %%g1,%3,%%g1
976 mulscc %%g1,%3,%%g1
977 mulscc %%g1,%3,%%g1
978 mulscc %%g1,%3,%%g1
979 mulscc %%g1,%3,%%g1
980 mulscc %%g1,%3,%%g1
981 mulscc %%g1,%3,%%g1
982 mulscc %%g1,%3,%%g1
983 mulscc %%g1,%3,%%g1
984 mulscc %%g1,%3,%%g1
985 mulscc %%g1,%3,%%g1
986 mulscc %%g1,%3,%%g1
987 mulscc %%g1,%3,%%g1
988 mulscc %%g1,%3,%%g1
989 mulscc %%g1,%3,%%g1
990 mulscc %%g1,%3,%%g1
991 mulscc %%g1,%3,%%g1
992 mulscc %%g1,%3,%%g1
993 mulscc %%g1,%3,%%g1
994 mulscc %%g1,0,%%g1
995 add %%g1,%%g2,%0
996 rd %%y,%1" \
997 : "=r" ((USItype) (w1)), \
998 "=r" ((USItype) (w0)) \
999 : "%rI" ((USItype) (u)), \
1000 "r" ((USItype) (v)) \
1001 : "%g1", "%g2" __AND_CLOBBER_CC)
1002 #define UMUL_TIME 39 /* 39 instructions */
1003 /* It's quite necessary to add this much assembler for the sparc.
1004 The default udiv_qrnnd (in C) is more than 10 times slower! */
1005 #define udiv_qrnnd(q, r, n1, n0, d) \
1006 __asm__ ("! Inlined udiv_qrnnd
1007 mov 32,%%g1
1008 subcc %1,%2,%%g0
1009 1: bcs 5f
1010 addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
1011 sub %1,%2,%1 ! this kills msb of n
1012 addx %1,%1,%1 ! so this can't give carry
1013 subcc %%g1,1,%%g1
1014 2: bne 1b
1015 subcc %1,%2,%%g0
1016 bcs 3f
1017 addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
1018 b 3f
1019 sub %1,%2,%1 ! this kills msb of n
1020 4: sub %1,%2,%1
1021 5: addxcc %1,%1,%1
1022 bcc 2b
1023 subcc %%g1,1,%%g1
1024 ! Got carry from n. Subtract next step to cancel this carry.
1025 bne 4b
1026 addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb
1027 sub %1,%2,%1
1028 3: xnor %0,0,%0
1029 ! End of inline udiv_qrnnd" \
1030 : "=&r" ((USItype) (q)), \
1031 "=&r" ((USItype) (r)) \
1032 : "r" ((USItype) (d)), \
1033 "1" ((USItype) (n1)), \
1034 "0" ((USItype) (n0)) : "%g1" __AND_CLOBBER_CC)
1035 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1036 #endif /* __sparclite__ */
1037 #endif /* __sparc_v8__ */
1038 #endif /* __sparc__ */
1039
1040 #if defined (__vax__)
1041 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1042 __asm__ ("addl2 %5,%1
1043 adwc %3,%0" \
1044 : "=g" ((USItype) (sh)), \
1045 "=&g" ((USItype) (sl)) \
1046 : "%0" ((USItype) (ah)), \
1047 "g" ((USItype) (bh)), \
1048 "%1" ((USItype) (al)), \
1049 "g" ((USItype) (bl)))
1050 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1051 __asm__ ("subl2 %5,%1
1052 sbwc %3,%0" \
1053 : "=g" ((USItype) (sh)), \
1054 "=&g" ((USItype) (sl)) \
1055 : "0" ((USItype) (ah)), \
1056 "g" ((USItype) (bh)), \
1057 "1" ((USItype) (al)), \
1058 "g" ((USItype) (bl)))
1059 #define umul_ppmm(xh, xl, m0, m1) \
1060 do { \
1061 union { \
1062 UDItype __ll; \
1063 struct {USItype __l, __h;} __i; \
1064 } __xx; \
1065 USItype __m0 = (m0), __m1 = (m1); \
1066 __asm__ ("emul %1,%2,$0,%0" \
1067 : "=r" (__xx.__ll) \
1068 : "g" (__m0), \
1069 "g" (__m1)); \
1070 (xh) = __xx.__i.__h; \
1071 (xl) = __xx.__i.__l; \
1072 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1073 + (((SItype) __m1 >> 31) & __m0)); \
1074 } while (0)
1075 #define sdiv_qrnnd(q, r, n1, n0, d) \
1076 do { \
1077 union {DItype __ll; \
1078 struct {SItype __l, __h;} __i; \
1079 } __xx; \
1080 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1081 __asm__ ("ediv %3,%2,%0,%1" \
1082 : "=g" (q), "=g" (r) \
1083 : "g" (__xx.__ll), "g" (d)); \
1084 } while (0)
1085 #endif /* __vax__ */
1086
1087 #endif /* __GNUC__ */
1088
1089 /* If this machine has no inline assembler, use C macros. */
1090
1091 #if !defined (add_ssaaaa)
1092 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1093 do { \
1094 USItype __x; \
1095 __x = (al) + (bl); \
1096 (sh) = (ah) + (bh) + (__x < (al)); \
1097 (sl) = __x; \
1098 } while (0)
1099 #endif
1100
1101 #if !defined (sub_ddmmss)
1102 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1103 do { \
1104 USItype __x; \
1105 __x = (al) - (bl); \
1106 (sh) = (ah) - (bh) - (__x > (al)); \
1107 (sl) = __x; \
1108 } while (0)
1109 #endif
1110
1111 #if !defined (umul_ppmm)
1112 #define umul_ppmm(w1, w0, u, v) \
1113 do { \
1114 USItype __x0, __x1, __x2, __x3; \
1115 USItype __ul, __vl, __uh, __vh; \
1116 \
1117 __ul = __ll_lowpart (u); \
1118 __uh = __ll_highpart (u); \
1119 __vl = __ll_lowpart (v); \
1120 __vh = __ll_highpart (v); \
1121 \
1122 __x0 = (USItype) __ul * __vl; \
1123 __x1 = (USItype) __ul * __vh; \
1124 __x2 = (USItype) __uh * __vl; \
1125 __x3 = (USItype) __uh * __vh; \
1126 \
1127 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1128 __x1 += __x2; /* but this indeed can */ \
1129 if (__x1 < __x2) /* did we get it? */ \
1130 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1131 \
1132 (w1) = __x3 + __ll_highpart (__x1); \
1133 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1134 } while (0)
1135 #endif
1136
1137 #if !defined (__umulsidi3)
1138 #define __umulsidi3(u, v) \
1139 ({DIunion __w; \
1140 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1141 __w.ll; })
1142 #endif
1143
1144 /* Define this unconditionally, so it can be used for debugging. */
1145 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1146 do { \
1147 USItype __d1, __d0, __q1, __q0; \
1148 USItype __r1, __r0, __m; \
1149 __d1 = __ll_highpart (d); \
1150 __d0 = __ll_lowpart (d); \
1151 \
1152 __r1 = (n1) % __d1; \
1153 __q1 = (n1) / __d1; \
1154 __m = (USItype) __q1 * __d0; \
1155 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1156 if (__r1 < __m) \
1157 { \
1158 __q1--, __r1 += (d); \
1159 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1160 if (__r1 < __m) \
1161 __q1--, __r1 += (d); \
1162 } \
1163 __r1 -= __m; \
1164 \
1165 __r0 = __r1 % __d1; \
1166 __q0 = __r1 / __d1; \
1167 __m = (USItype) __q0 * __d0; \
1168 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1169 if (__r0 < __m) \
1170 { \
1171 __q0--, __r0 += (d); \
1172 if (__r0 >= (d)) \
1173 if (__r0 < __m) \
1174 __q0--, __r0 += (d); \
1175 } \
1176 __r0 -= __m; \
1177 \
1178 (q) = (USItype) __q1 * __ll_B | __q0; \
1179 (r) = __r0; \
1180 } while (0)
1181
1182 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1183 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1184 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1185 #define udiv_qrnnd(q, r, nh, nl, d) \
1186 do { \
1187 USItype __r; \
1188 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1189 (r) = __r; \
1190 } while (0)
1191 #endif
1192
1193 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1194 #if !defined (udiv_qrnnd)
1195 #define UDIV_NEEDS_NORMALIZATION 1
1196 #define udiv_qrnnd __udiv_qrnnd_c
1197 #endif
1198
1199 #if !defined (count_leading_zeros)
1200 extern const UQItype __clz_tab[];
1201 #define count_leading_zeros(count, x) \
1202 do { \
1203 USItype __xr = (x); \
1204 USItype __a; \
1205 \
1206 if (SI_TYPE_SIZE <= 32) \
1207 { \
1208 __a = __xr < (1<<2*__BITS4) \
1209 ? (__xr < (1<<__BITS4) ? 0 : __BITS4) \
1210 : (__xr < (1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1211 } \
1212 else \
1213 { \
1214 for (__a = SI_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1215 if (((__xr >> __a) & 0xff) != 0) \
1216 break; \
1217 } \
1218 \
1219 (count) = SI_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1220 } while (0)
1221 #endif
1222
1223 #ifndef UDIV_NEEDS_NORMALIZATION
1224 #define UDIV_NEEDS_NORMALIZATION 0
1225 #endif
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