gcc/config/arm/arm-protos.h

   1 /* Prototypes for exported functions defined in arm.c and pe.c
   2    Copyright (C) 1999-2014 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rearnsha@arm.com)
   4    Minor hacks by Nick Clifton (nickc@cygnus.com)
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    GCC is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_ARM_PROTOS_H
  23 #define GCC_ARM_PROTOS_H
  24
  25 extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
  26 extern int use_return_insn (int, rtx);
  27 extern bool use_simple_return_p (void);
  28 extern enum reg_class arm_regno_class (int);
  29 extern void arm_load_pic_register (unsigned long);
  30 extern int arm_volatile_func (void);
  31 extern void arm_expand_prologue (void);
  32 extern void arm_expand_epilogue (bool);
  33 extern void thumb2_expand_return (bool);
  34 extern const char *arm_strip_name_encoding (const char *);
  35 extern void arm_asm_output_labelref (FILE *, const char *);
  36 extern void thumb2_asm_output_opcode (FILE *);
  37 extern unsigned long arm_current_func_type (void);
  38 extern HOST_WIDE_INT arm_compute_initial_elimination_offset (unsigned int,
  39                                                              unsigned int);
  40 extern HOST_WIDE_INT thumb_compute_initial_elimination_offset (unsigned int,
  41                                                                unsigned int);
  42 extern unsigned int arm_dbx_register_number (unsigned int);
  43 extern void arm_output_fn_unwind (FILE *, bool);
  44
  45 extern rtx arm_expand_builtin (tree exp, rtx target, rtx subtarget
  46                                ATTRIBUTE_UNUSED, enum machine_mode mode
  47                                ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED);
  48 extern tree arm_builtin_decl (unsigned code, bool initialize_p
  49                               ATTRIBUTE_UNUSED);
  50 extern void arm_init_builtins (void);
  51 extern void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
  52
  53 #ifdef RTX_CODE
  54 extern bool arm_vector_mode_supported_p (machine_mode);
  55 extern bool arm_small_register_classes_for_mode_p (machine_mode);
  56 extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);
  57 extern bool arm_modes_tieable_p (machine_mode, machine_mode);
  58 extern int const_ok_for_arm (HOST_WIDE_INT);
  59 extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
  60 extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
  61 extern int arm_split_constant (RTX_CODE, machine_mode, rtx,
  62                                HOST_WIDE_INT, rtx, rtx, int);
  63 extern int legitimate_pic_operand_p (rtx);
  64 extern rtx legitimize_pic_address (rtx, machine_mode, rtx);
  65 extern rtx legitimize_tls_address (rtx, rtx);
  66 extern bool arm_legitimate_address_p (machine_mode, rtx, bool);
  67 extern int arm_legitimate_address_outer_p (machine_mode, rtx, RTX_CODE, int);
  68 extern int thumb_legitimate_offset_p (machine_mode, HOST_WIDE_INT);
  69 extern bool arm_legitimize_reload_address (rtx *, machine_mode, int, int,
  70                                            int);
  71 extern rtx thumb_legitimize_reload_address (rtx *, machine_mode, int, int,
  72                                             int);
  73 extern int thumb1_legitimate_address_p (machine_mode, rtx, int);
  74 extern bool ldm_stm_operation_p (rtx, bool, machine_mode mode,
  75                                  bool, bool);
  76 extern int arm_const_double_rtx (rtx);
  77 extern int vfp3_const_double_rtx (rtx);
  78 extern int neon_immediate_valid_for_move (rtx, machine_mode, rtx *, int *);
  79 extern int neon_immediate_valid_for_logic (rtx, machine_mode, int, rtx *,
  80                                            int *);
  81 extern int neon_immediate_valid_for_shift (rtx, machine_mode, rtx *,
  82                                            int *, bool);
  83 extern char *neon_output_logic_immediate (const char *, rtx *,
  84                                           machine_mode, int, int);
  85 extern char *neon_output_shift_immediate (const char *, char, rtx *,
  86                                           machine_mode, int, bool);
  87 extern void neon_pairwise_reduce (rtx, rtx, machine_mode,
  88                                   rtx (*) (rtx, rtx, rtx));
  89 extern rtx neon_make_constant (rtx);
  90 extern tree arm_builtin_vectorized_function (tree, tree, tree);
  91 extern void neon_expand_vector_init (rtx, rtx);
  92 extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
  93 extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
  94 extern HOST_WIDE_INT neon_element_bits (machine_mode);
  95 extern void neon_reinterpret (rtx, rtx);
  96 extern void neon_emit_pair_result_insn (machine_mode,
  97                                         rtx (*) (rtx, rtx, rtx, rtx),
  98                                         rtx, rtx, rtx);
  99 extern void neon_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int);
 100 extern void neon_split_vcombine (rtx op[3]);
 101 extern enum reg_class coproc_secondary_reload_class (machine_mode, rtx,
 102                                                      bool);
 103 extern bool arm_tls_referenced_p (rtx);
 104
 105 extern int arm_coproc_mem_operand (rtx, bool);
 106 extern int neon_vector_mem_operand (rtx, int, bool);
 107 extern int neon_struct_mem_operand (rtx);
 108
 109 extern int tls_mentioned_p (rtx);
 110 extern int symbol_mentioned_p (rtx);
 111 extern int label_mentioned_p (rtx);
 112 extern RTX_CODE minmax_code (rtx);
 113 extern bool arm_sat_operator_match (rtx, rtx, int *, bool *);
 114 extern int adjacent_mem_locations (rtx, rtx);
 115 extern bool gen_ldm_seq (rtx *, int, bool);
 116 extern bool gen_stm_seq (rtx *, int);
 117 extern bool gen_const_stm_seq (rtx *, int);
 118 extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
 119 extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
 120 extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT);
 121 extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool);
 122 extern bool gen_operands_ldrd_strd (rtx *, bool, bool, bool);
 123 extern int arm_gen_movmemqi (rtx *);
 124 extern bool gen_movmem_ldrd_strd (rtx *);
 125 extern machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
 126 extern machine_mode arm_select_dominance_cc_mode (rtx, rtx,
 127                                                        HOST_WIDE_INT);
 128 extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx, rtx);
 129 extern rtx arm_gen_return_addr_mask (void);
 130 extern void arm_reload_in_hi (rtx *);
 131 extern void arm_reload_out_hi (rtx *);
 132 extern int arm_max_const_double_inline_cost (void);
 133 extern int arm_const_double_inline_cost (rtx);
 134 extern bool arm_const_double_by_parts (rtx);
 135 extern bool arm_const_double_by_immediates (rtx);
 136 extern void arm_emit_call_insn (rtx, rtx, bool);
 137 extern const char *output_call (rtx *);
 138 extern const char *output_call_mem (rtx *);
 139 void arm_emit_movpair (rtx, rtx);
 140 extern const char *output_mov_long_double_arm_from_arm (rtx *);
 141 extern const char *output_move_double (rtx *, bool, int *count);
 142 extern const char *output_move_quad (rtx *);
 143 extern int arm_count_output_move_double_insns (rtx *);
 144 extern const char *output_move_vfp (rtx *operands);
 145 extern const char *output_move_neon (rtx *operands);
 146 extern int arm_attr_length_move_neon (rtx_insn *);
 147 extern int arm_address_offset_is_imm (rtx_insn *);
 148 extern const char *output_add_immediate (rtx *);
 149 extern const char *arithmetic_instr (rtx, int);
 150 extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
 151 extern const char *output_return_instruction (rtx, bool, bool, bool);
 152 extern void arm_poke_function_name (FILE *, const char *);
 153 extern void arm_final_prescan_insn (rtx_insn *);
 154 extern int arm_debugger_arg_offset (int, rtx);
 155 extern bool arm_is_long_call_p (tree);
 156 extern int    arm_emit_vector_const (FILE *, rtx);
 157 extern void arm_emit_fp16_const (rtx c);
 158 extern const char * arm_output_load_gr (rtx *);
 159 extern const char *vfp_output_vstmd (rtx *);
 160 extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool);
 161 extern void arm_set_return_address (rtx, rtx);
 162 extern int arm_eliminable_register (rtx);
 163 extern const char *arm_output_shift(rtx *, int);
 164 extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool);
 165 extern const char *arm_output_iwmmxt_tinsr (rtx *);
 166 extern unsigned int arm_sync_loop_insns (rtx , rtx *);
 167 extern int arm_attr_length_push_multi(rtx, rtx);
 168 extern void arm_expand_compare_and_swap (rtx op[]);
 169 extern void arm_split_compare_and_swap (rtx op[]);
 170 extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
 171 extern rtx arm_load_tp (rtx);
 172
 173 #if defined TREE_CODE
 174 extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
 175 extern bool arm_pad_arg_upward (machine_mode, const_tree);
 176 extern bool arm_pad_reg_upward (machine_mode, tree, int);
 177 #endif
 178 extern int arm_apply_result_size (void);
 179
 180 #endif /* RTX_CODE */
 181
 182 /* Thumb functions.  */
 183 extern void arm_init_expanders (void);
 184 extern const char *thumb1_unexpanded_epilogue (void);
 185 extern void thumb1_expand_prologue (void);
 186 extern void thumb1_expand_epilogue (void);
 187 extern const char *thumb1_output_interwork (void);
 188 #ifdef TREE_CODE
 189 extern int is_called_in_ARM_mode (tree);
 190 #endif
 191 extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
 192 #ifdef RTX_CODE
 193 extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
 194 extern void thumb1_final_prescan_insn (rtx_insn *);
 195 extern void thumb2_final_prescan_insn (rtx_insn *);
 196 extern const char *thumb_load_double_from_address (rtx *);
 197 extern const char *thumb_output_move_mem_multiple (int, rtx *);
 198 extern const char *thumb_call_via_reg (rtx);
 199 extern void thumb_expand_movmemqi (rtx *);
 200 extern rtx arm_return_addr (int, rtx);
 201 extern void thumb_reload_out_hi (rtx *);
 202 extern void thumb_reload_in_hi (rtx *);
 203 extern void thumb_set_return_address (rtx, rtx);
 204 extern const char *thumb1_output_casesi (rtx *);
 205 extern const char *thumb2_output_casesi (rtx *);
 206 #endif
 207
 208 /* Defined in pe.c.  */
 209 extern int arm_dllexport_name_p (const char *);
 210 extern int arm_dllimport_name_p (const char *);
 211
 212 #ifdef TREE_CODE
 213 extern void arm_pe_unique_section (tree, int);
 214 extern void arm_pe_encode_section_info (tree, rtx, int);
 215 extern int arm_dllexport_p (tree);
 216 extern int arm_dllimport_p (tree);
 217 extern void arm_mark_dllexport (tree);
 218 extern void arm_mark_dllimport (tree);
 219 #endif
 220
 221 extern void arm_pr_long_calls (struct cpp_reader *);
 222 extern void arm_pr_no_long_calls (struct cpp_reader *);
 223 extern void arm_pr_long_calls_off (struct cpp_reader *);
 224
 225 extern void arm_lang_object_attributes_init(void);
 226
 227 extern const char *arm_mangle_type (const_tree);
 228 extern const char *arm_mangle_builtin_type (const_tree);
 229
 230 extern void arm_order_regs_for_local_alloc (void);
 231
 232 extern int arm_max_conditional_execute ();
 233
 234 /* Vectorizer cost model implementation.  */
 235 struct cpu_vec_costs {
 236   const int scalar_stmt_cost;   /* Cost of any scalar operation, excluding
 237                                    load and store.  */
 238   const int scalar_load_cost;   /* Cost of scalar load.  */
 239   const int scalar_store_cost;  /* Cost of scalar store.  */
 240   const int vec_stmt_cost;      /* Cost of any vector operation, excluding
 241                                    load, store, vector-to-scalar and
 242                                    scalar-to-vector operation.  */
 243   const int vec_to_scalar_cost;    /* Cost of vect-to-scalar operation.  */
 244   const int scalar_to_vec_cost;    /* Cost of scalar-to-vector operation.  */
 245   const int vec_align_load_cost;   /* Cost of aligned vector load.  */
 246   const int vec_unalign_load_cost; /* Cost of unaligned vector load.  */
 247   const int vec_unalign_store_cost; /* Cost of unaligned vector load.  */
 248   const int vec_store_cost;        /* Cost of vector store.  */
 249   const int cond_taken_branch_cost;    /* Cost of taken branch for vectorizer
 250                                           cost model.  */
 251   const int cond_not_taken_branch_cost;/* Cost of not taken branch for
 252                                           vectorizer cost model.  */
 253 };
 254
 255 #ifdef RTX_CODE
 256 /* This needs to be here because we need RTX_CODE and similar.  */
 257
 258 struct cpu_cost_table;
 259
 260 struct tune_params
 261 {
 262   bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
 263   const struct cpu_cost_table *insn_extra_cost;
 264   bool (*sched_adjust_cost) (rtx_insn *, rtx, rtx_insn *, int *);
 265   int constant_limit;
 266   /* Maximum number of instructions to conditionalise.  */
 267   int max_insns_skipped;
 268   int num_prefetch_slots;
 269   int l1_cache_size;
 270   int l1_cache_line_size;
 271   bool prefer_constant_pool;
 272   int (*branch_cost) (bool, bool);
 273   /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM.  */
 274   bool prefer_ldrd_strd;
 275   /* The preference for non short cirtcuit operation when optimizing for
 276      performance. The first element covers Thumb state and the second one
 277      is for ARM state.  */
 278   bool logical_op_non_short_circuit[2];
 279   /* Vectorizer costs.  */
 280   const struct cpu_vec_costs* vec_costs;
 281   /* Prefer Neon for 64-bit bitops.  */
 282   bool prefer_neon_for_64bits;
 283   /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding.  */
 284   bool disparage_flag_setting_t16_encodings;
 285   /* Prefer 32-bit encoding instead of 16-bit encoding where subset of flags
 286      would be set.  */
 287   bool disparage_partial_flag_setting_t16_encodings;
 288   /* Prefer to inline string operations like memset by using Neon.  */
 289   bool string_ops_prefer_neon;
 290   /* Maximum number of instructions to inline calls to memset.  */
 291   int max_insns_inline_memset;
 292 };
 293
 294 extern const struct tune_params *current_tune;
 295 extern int vfp3_const_double_for_fract_bits (rtx);
 296 /* return power of two from operand, otherwise 0.  */
 297 extern int vfp3_const_double_for_bits (rtx);
 298
 299 extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
 300                                            rtx);
 301 extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
 302 #endif /* RTX_CODE */
 303
 304 extern bool arm_gen_setmem (rtx *);
 305 extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
 306 extern bool arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
 307
 308 extern bool arm_autoinc_modes_ok_p (machine_mode, enum arm_auto_incmodes);
 309
 310 extern void arm_emit_eabi_attribute (const char *, int, int);
 311
 312 /* Defined in gcc/common/config/arm-common.c.  */
 313 extern const char *arm_rewrite_selected_cpu (const char *name);
 314
 315 extern bool arm_is_constant_pool_ref (rtx);
 316
 317 /* Flags used to identify the presence of processor capabilities.  */
 318
 319 /* Bit values used to identify processor capabilities.  */
 320 #define FL_CO_PROC    (1 << 0)        /* Has external co-processor bus */
 321 #define FL_ARCH3M     (1 << 1)        /* Extended multiply */
 322 #define FL_MODE26     (1 << 2)        /* 26-bit mode support */
 323 #define FL_MODE32     (1 << 3)        /* 32-bit mode support */
 324 #define FL_ARCH4      (1 << 4)        /* Architecture rel 4 */
 325 #define FL_ARCH5      (1 << 5)        /* Architecture rel 5 */
 326 #define FL_THUMB      (1 << 6)        /* Thumb aware */
 327 #define FL_LDSCHED    (1 << 7)        /* Load scheduling necessary */
 328 #define FL_STRONG     (1 << 8)        /* StrongARM */
 329 #define FL_ARCH5E     (1 << 9)        /* DSP extensions to v5 */
 330 #define FL_XSCALE     (1 << 10)       /* XScale */
 331 /* spare              (1 << 11) */
 332 #define FL_ARCH6      (1 << 12)       /* Architecture rel 6.  Adds
 333                                          media instructions.  */
 334 #define FL_VFPV2      (1 << 13)       /* Vector Floating Point V2.  */
 335 #define FL_WBUF       (1 << 14)       /* Schedule for write buffer ops.
 336                                          Note: ARM6 & 7 derivatives only.  */
 337 #define FL_ARCH6K     (1 << 15)       /* Architecture rel 6 K extensions.  */
 338 #define FL_THUMB2     (1 << 16)       /* Thumb-2.  */
 339 #define FL_NOTM       (1 << 17)       /* Instructions not present in the 'M'
 340                                          profile.  */
 341 #define FL_THUMB_DIV  (1 << 18)       /* Hardware divide (Thumb mode).  */
 342 #define FL_VFPV3      (1 << 19)       /* Vector Floating Point V3.  */
 343 #define FL_NEON       (1 << 20)       /* Neon instructions.  */
 344 #define FL_ARCH7EM    (1 << 21)       /* Instructions present in the ARMv7E-M
 345                                          architecture.  */
 346 #define FL_ARCH7      (1 << 22)       /* Architecture 7.  */
 347 #define FL_ARM_DIV    (1 << 23)       /* Hardware divide (ARM mode).  */
 348 #define FL_ARCH8      (1 << 24)       /* Architecture 8.  */
 349 #define FL_CRC32      (1 << 25)       /* ARMv8 CRC32 instructions.  */
 350
 351 #define FL_SMALLMUL   (1 << 26)       /* Small multiply supported.  */
 352
 353 #define FL_IWMMXT     (1 << 29)       /* XScale v2 or "Intel Wireless MMX technology".  */
 354 #define FL_IWMMXT2    (1 << 30)       /* "Intel Wireless MMX2 technology".  */
 355
 356 /* Flags that only effect tuning, not available instructions.  */
 357 #define FL_TUNE         (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
 358                          | FL_CO_PROC)
 359
 360 #define FL_FOR_ARCH2    FL_NOTM
 361 #define FL_FOR_ARCH3    (FL_FOR_ARCH2 | FL_MODE32)
 362 #define FL_FOR_ARCH3M   (FL_FOR_ARCH3 | FL_ARCH3M)
 363 #define FL_FOR_ARCH4    (FL_FOR_ARCH3M | FL_ARCH4)
 364 #define FL_FOR_ARCH4T   (FL_FOR_ARCH4 | FL_THUMB)
 365 #define FL_FOR_ARCH5    (FL_FOR_ARCH4 | FL_ARCH5)
 366 #define FL_FOR_ARCH5T   (FL_FOR_ARCH5 | FL_THUMB)
 367 #define FL_FOR_ARCH5E   (FL_FOR_ARCH5 | FL_ARCH5E)
 368 #define FL_FOR_ARCH5TE  (FL_FOR_ARCH5E | FL_THUMB)
 369 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
 370 #define FL_FOR_ARCH6    (FL_FOR_ARCH5TE | FL_ARCH6)
 371 #define FL_FOR_ARCH6J   FL_FOR_ARCH6
 372 #define FL_FOR_ARCH6K   (FL_FOR_ARCH6 | FL_ARCH6K)
 373 #define FL_FOR_ARCH6Z   FL_FOR_ARCH6
 374 #define FL_FOR_ARCH6ZK  FL_FOR_ARCH6K
 375 #define FL_FOR_ARCH6T2  (FL_FOR_ARCH6 | FL_THUMB2)
 376 #define FL_FOR_ARCH6M   (FL_FOR_ARCH6 & ~FL_NOTM)
 377 #define FL_FOR_ARCH7    ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
 378 #define FL_FOR_ARCH7A   (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
 379 #define FL_FOR_ARCH7VE  (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
 380 #define FL_FOR_ARCH7R   (FL_FOR_ARCH7A | FL_THUMB_DIV)
 381 #define FL_FOR_ARCH7M   (FL_FOR_ARCH7 | FL_THUMB_DIV)
 382 #define FL_FOR_ARCH7EM  (FL_FOR_ARCH7M | FL_ARCH7EM)
 383 #define FL_FOR_ARCH8A   (FL_FOR_ARCH7VE | FL_ARCH8)
 384
 385 /* The bits in this mask specify which
 386    instructions we are allowed to generate.  */
 387 extern unsigned long insn_flags;
 388
 389 /* The bits in this mask specify which instruction scheduling options should
 390    be used.  */
 391 extern unsigned long tune_flags;
 392
 393 /* Nonzero if this chip supports the ARM Architecture 3M extensions.  */
 394 extern int arm_arch3m;
 395
 396 /* Nonzero if this chip supports the ARM Architecture 4 extensions.  */
 397 extern int arm_arch4;
 398
 399 /* Nonzero if this chip supports the ARM Architecture 4t extensions.  */
 400 extern int arm_arch4t;
 401
 402 /* Nonzero if this chip supports the ARM Architecture 5 extensions.  */
 403 extern int arm_arch5;
 404
 405 /* Nonzero if this chip supports the ARM Architecture 5E extensions.  */
 406 extern int arm_arch5e;
 407
 408 /* Nonzero if this chip supports the ARM Architecture 6 extensions.  */
 409 extern int arm_arch6;
 410
 411 /* Nonzero if this chip supports the ARM 6K extensions.  */
 412 extern int arm_arch6k;
 413
 414 /* Nonzero if instructions present in ARMv6-M can be used.  */
 415 extern int arm_arch6m;
 416
 417 /* Nonzero if this chip supports the ARM 7 extensions.  */
 418 extern int arm_arch7;
 419
 420 /* Nonzero if instructions not present in the 'M' profile can be used.  */
 421 extern int arm_arch_notm;
 422
 423 /* Nonzero if instructions present in ARMv7E-M can be used.  */
 424 extern int arm_arch7em;
 425
 426 /* Nonzero if instructions present in ARMv8 can be used.  */
 427 extern int arm_arch8;
 428
 429 /* Nonzero if this chip can benefit from load scheduling.  */
 430 extern int arm_ld_sched;
 431
 432 /* Nonzero if this chip is a StrongARM.  */
 433 extern int arm_tune_strongarm;
 434
 435 /* Nonzero if this chip supports Intel Wireless MMX technology.  */
 436 extern int arm_arch_iwmmxt;
 437
 438 /* Nonzero if this chip supports Intel Wireless MMX2 technology.  */
 439 extern int arm_arch_iwmmxt2;
 440
 441 /* Nonzero if this chip is an XScale.  */
 442 extern int arm_arch_xscale;
 443
 444 /* Nonzero if tuning for XScale  */
 445 extern int arm_tune_xscale;
 446
 447 /* Nonzero if we want to tune for stores that access the write-buffer.
 448    This typically means an ARM6 or ARM7 with MMU or MPU.  */
 449 extern int arm_tune_wbuf;
 450
 451 /* Nonzero if tuning for Cortex-A9.  */
 452 extern int arm_tune_cortex_a9;
 453
 454 /* Nonzero if generating Thumb instructions.  */
 455 extern int thumb_code;
 456
 457 /* Nonzero if generating Thumb-1 instructions.  */
 458 extern int thumb1_code;
 459
 460 /* Nonzero if we should define __THUMB_INTERWORK__ in the
 461    preprocessor.
 462    XXX This is a bit of a hack, it's intended to help work around
 463    problems in GLD which doesn't understand that armv5t code is
 464    interworking clean.  */
 465 extern int arm_cpp_interwork;
 466
 467 /* Nonzero if chip supports Thumb 2.  */
 468 extern int arm_arch_thumb2;
 469
 470 /* Nonzero if chip supports integer division instruction.  */
 471 extern int arm_arch_arm_hwdiv;
 472 extern int arm_arch_thumb_hwdiv;
 473
 474 /* Nonzero if we should use Neon to handle 64-bits operations rather
 475    than core registers.  */
 476 extern int prefer_neon_for_64bits;
 477
 478
 479
 480 #endif /* ! GCC_ARM_PROTOS_H */