[PR81647][AARCH64] Fix handling of Unordered Comparisons in aarch64-simd.md
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / vect-mull.c
blob62a3552f7b1e87bca3f92b9587455d9371fc4fc5
2 /* { dg-do run } */
3 /* { dg-options "-O3" } */
5 #include "limits.h"
7 extern void abort (void);
9 #define N 16
11 #include "vect-mull.x"
13 #define SET_VEC(size, type, sign) \
14 void set_vector_##sign##size \
15 (pR##sign##INT##size b, \
16 pR##sign##INT##size c) \
17 { \
18 int i; \
19 for (i=0; i<N; i++) \
20 { \
21 b[i] = (type)((INT_MAX >> (32 - size)) - i); \
22 c[i] = (type)((INT_MAX >> (32 - size)) - i * 2); \
23 } \
26 #define CHECK_VEC(size, sign) void check_vector_##sign##size (pR##sign##INT##size a, \
27 pR##sign##INT##size b) \
28 { \
29 int i; \
30 for (i=0; i<N; i++) \
31 if (a[i] != b[i]) \
32 abort (); \
35 SET_VEC (8, signed char, S)
36 SET_VEC (16, signed short, S)
37 SET_VEC (32, signed int, S)
39 SET_VEC (8, unsigned char, U)
40 SET_VEC (16, unsigned short, U)
41 SET_VEC (32, unsigned int, U)
43 DEF_MULL2 (DEF_MULLB)
44 DEF_MULL2 (DEF_MULLH)
45 DEF_MULL2 (DEF_MULLS)
47 CHECK_VEC (8, S)
48 CHECK_VEC (8, U)
49 CHECK_VEC (16, S)
50 CHECK_VEC (16, U)
51 CHECK_VEC (32, S)
52 CHECK_VEC (32, U)
53 CHECK_VEC (64, S)
54 CHECK_VEC (64, U)
56 int main (void)
59 #define DECL_VAR(name) signed char name##_S8[N]; \
60 signed short name##_S16[N]; \
61 signed int name##_S32[N]; \
62 unsigned char name##_U8[N]; \
63 unsigned short name##_U16[N]; \
64 unsigned int name##_U32[N];
66 DECL_VAR (output);
67 signed long long output_S64[N];
68 unsigned long long output_U64[N];
70 DECL_VAR (input1);
71 DECL_VAR (input2);
73 signed short expected_S16[] =
74 { 16129, 15750, 15375, 15004, 14637, 14274, 13915, 13560,
75 13209, 12862, 12519, 12180, 11845, 11514, 11187, 10864 };
77 signed int expected_S32[] =
78 { 1073676289, 1073577990, 1073479695, 1073381404, 1073283117,
79 1073184834, 1073086555, 1072988280, 1072890009, 1072791742,
80 1072693479, 1072595220, 1072496965, 1072398714, 1072300467,
81 1072202224 };
83 signed long long expected_S64[] =
84 { 4611686014132420609LL, 4611686007689969670LL,
85 4611686001247518735LL, 4611685994805067804LL,
86 4611685988362616877LL, 4611685981920165954LL,
87 4611685975477715035LL, 4611685969035264120LL,
88 4611685962592813209LL, 4611685956150362302LL,
89 4611685949707911399LL, 4611685943265460500LL,
90 4611685936823009605LL, 4611685930380558714LL,
91 4611685923938107827LL, 4611685917495656944LL };
93 unsigned short expected_U16[] =
94 { 16129, 15750, 15375, 15004, 14637, 14274, 13915, 13560,
95 13209, 12862, 12519, 12180, 11845, 11514, 11187, 10864 };
97 unsigned int expected_U32[] =
98 { 1073676289, 1073577990, 1073479695, 1073381404, 1073283117,
99 1073184834, 1073086555, 1072988280, 1072890009, 1072791742,
100 1072693479, 1072595220, 1072496965, 1072398714, 1072300467,
101 1072202224 };
103 unsigned long long expected_U64[] =
104 { 4611686014132420609ULL, 4611686007689969670ULL,
105 4611686001247518735ULL, 4611685994805067804ULL,
106 4611685988362616877ULL, 4611685981920165954ULL,
107 4611685975477715035ULL, 4611685969035264120ULL,
108 4611685962592813209ULL, 4611685956150362302ULL,
109 4611685949707911399ULL, 4611685943265460500ULL,
110 4611685936823009605ULL, 4611685930380558714ULL,
111 4611685923938107827ULL, 4611685917495656944ULL };
113 /* Set up input. */
114 set_vector_S8 (input1_S8, input2_S8);
115 set_vector_S16 (input1_S16, input2_S16);
116 set_vector_S32 (input1_S32, input2_S32);
117 set_vector_U8 (input1_U8, input2_U8);
118 set_vector_U16 (input1_U16, input2_U16);
119 set_vector_U32 (input1_U32, input2_U32);
121 /* Calculate actual results. */
122 widen_mult_Sb (output_S16, input1_S8, input2_S8);
123 widen_mult_Sh (output_S32, input1_S16, input2_S16);
124 widen_mult_Ss (output_S64, input1_S32, input2_S32);
125 widen_mult_Ub (output_U16, input1_U8, input2_U8);
126 widen_mult_Uh (output_U32, input1_U16, input2_U16);
127 widen_mult_Us (output_U64, input1_U32, input2_U32);
129 /* Check actual vs. expected. */
130 check_vector_S16 (expected_S16, output_S16);
131 check_vector_S32 (expected_S32, output_S32);
132 check_vector_S64 (expected_S64, output_S64);
133 check_vector_U16 (expected_U16, output_U16);
134 check_vector_U32 (expected_U32, output_U32);
135 check_vector_U64 (expected_U64, output_U64);
137 return 0;