gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-O3 -fno-vect-cost-model" } */
   3
   4 #pragma GCC target "+nosve"
   5
   6 #include "stdint.h"
   7 #include "vect-ld1r.x"
   8
   9 DEF (int8_t)
  10 DEF (int16_t)
  11 DEF (int32_t)
  12 DEF (int64_t)
  13
  14 /* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.8b"} } */
  15 /* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.16b"} } */
  16 /* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4h"} } */
  17 /* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.8h"} } */
  18 /* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */
  19 /* { dg-final { scan-assembler "ldr\\t\x\[0-9\]+"} } */
  20 /* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */