[PR81647][AARCH64] Fix handling of Unordered Comparisons in aarch64-simd.md
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / fcvt_double_long.c
blob5eb36ff6dddbca85ee9c78661319e7f2e6653a02
1 /* { dg-do compile } */
2 /* { dg-options "-O2" } */
4 #define GPF double
5 #define SUFFIX(x) x
6 #define GPI long
8 #include "fcvt.x"
10 /* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
11 /* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
12 /* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
13 /* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
14 /* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
15 /* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
16 /* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
17 /* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */