[PR81647][AARCH64] Fix handling of Unordered Comparisons in aarch64-simd.md
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / ands_2.c
blobb061b1dfc59c1847cb799a1e49f8e5fc53bf2f14
1 /* { dg-do run } */
2 /* { dg-options "-O2 --save-temps -fno-inline" } */
4 extern void abort (void);
6 int
7 ands_si_test1 (int a, int b, int c)
9 int d = a & b;
11 /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
12 /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
13 if (d <= 0)
14 return a + c;
15 else
16 return b + d + c;
19 int
20 ands_si_test2 (int a, int b, int c)
22 int d = a & 0x99999999;
24 /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
25 /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
26 if (d <= 0)
27 return a + c;
28 else
29 return b + d + c;
32 int
33 ands_si_test3 (int a, int b, int c)
35 int d = a & (b << 3);
37 /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
38 /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
39 if (d <= 0)
40 return a + c;
41 else
42 return b + d + c;
45 typedef long long s64;
47 s64
48 ands_di_test1 (s64 a, s64 b, s64 c)
50 s64 d = a & b;
52 /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
53 /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
54 if (d <= 0)
55 return a + c;
56 else
57 return b + d + c;
60 s64
61 ands_di_test2 (s64 a, s64 b, s64 c)
63 s64 d = a & 0xaaaaaaaaaaaaaaaall;
65 /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
66 /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
67 if (d <= 0)
68 return a + c;
69 else
70 return b + d + c;
73 s64
74 ands_di_test3 (s64 a, s64 b, s64 c)
76 s64 d = a & (b << 3);
78 /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
79 /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
80 if (d <= 0)
81 return a + c;
82 else
83 return b + d + c;
86 int
87 main ()
89 int x;
90 s64 y;
92 x = ands_si_test1 (29, 4, 5);
93 if (x != 13)
94 abort ();
96 x = ands_si_test1 (5, 2, 20);
97 if (x != 25)
98 abort ();
100 x = ands_si_test2 (29, 4, 5);
101 if (x != 34)
102 abort ();
104 x = ands_si_test2 (1024, 2, 20);
105 if (x != 1044)
106 abort ();
108 x = ands_si_test3 (35, 4, 5);
109 if (x != 41)
110 abort ();
112 x = ands_si_test3 (5, 2, 20);
113 if (x != 25)
114 abort ();
116 y = ands_di_test1 (0x130000029ll,
117 0x320000004ll,
118 0x505050505ll);
120 if (y != ((0x130000029ll & 0x320000004ll) + 0x320000004ll + 0x505050505ll))
121 abort ();
123 y = ands_di_test1 (0x5000500050005ll,
124 0x2111211121112ll,
125 0x0000000002020ll);
126 if (y != 0x5000500052025ll)
127 abort ();
129 y = ands_di_test2 (0x130000029ll,
130 0x320000004ll,
131 0x505050505ll);
132 if (y != ((0x130000029ll & 0xaaaaaaaaaaaaaaaall) + 0x320000004ll + 0x505050505ll))
133 abort ();
135 y = ands_di_test2 (0x540004100ll,
136 0x320000004ll,
137 0x805050205ll);
138 if (y != (0x540004100ll + 0x805050205ll))
139 abort ();
141 y = ands_di_test3 (0x130000029ll,
142 0x064000008ll,
143 0x505050505ll);
144 if (y != ((0x130000029ll & (0x064000008ll << 3))
145 + 0x064000008ll + 0x505050505ll))
146 abort ();
148 y = ands_di_test3 (0x130002900ll,
149 0x088000008ll,
150 0x505050505ll);
151 if (y != (0x130002900ll + 0x505050505ll))
152 abort ();
154 return 0;