gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
   3
   4 #include "riscv_vector.h"
   5
   6 vint32m1_t
   7 __attribute__((target("arch=+v")))
   8 test_1 (vint32m1_t a, vint32m1_t b, size_t vl)
   9 {
  10   return __riscv_vadd_vv_i32m1 (a, b, vl);
  11 }
  12
  13 void
  14 test_2 ()
  15 {
  16   vint32m1_t a;
  17 }
  18
  19 size_t
  20 test_3 (size_t vl)
  21 {
  22   return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
  23 }