RISC-V: Allow RVV intrinsic when function target("arch=+v")

[official-gcc.git] / gcc / testsuite / gcc.target / riscv / rvv / base / target_attribute_v_with_intrinsic-7.c

/* { dg-do compile } */
/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */

#include "riscv_vector.h"

size_t test_1 (size_t vl)
{
  return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
}