RISC-V: Allow RVV intrinsic when function target("arch=+v")

[official-gcc.git] / gcc / testsuite / gcc.target / riscv / rvv / base / target_attribute_v_with_intrinsic-4.c

/* { dg-do compile } */
/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */

#include "riscv_vector.h"

void
test_1 (vint32m1_t a) /* { dg-error {argument type 'vint32m1_t' requires the V ISA extension} } */
{
  return;
}