gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-march=rv64gc -mabi=lp64d -O3 -Wno-implicit-int" } */
   3
   4 #include "riscv_vector.h"
   5
   6 vint32m1_t
   7 __attribute__((target("arch=+zbb")))
   8 test_1 (vint32m1_t a, vint32m1_t b, size_t vl)
   9 {
  10   return __riscv_vadd_vv_i32m1 (a, b, vl);
  11 }
  12
  13 /* { dg-error "return type 'vint32m1_t' requires the V ISA extension" "" { target { "riscv*-*-*" } } 0 } */