gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-2.c

   1 /* Test that we do not have error when compile */
   2 /* { dg-do compile } */
   3 /* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
   4
   5 #include "riscv_vector.h"
   6
   7 vint32m1_t
   8 __attribute__((target("arch=+v")))
   9 test_1 (vint32m1_t a, vint32m1_t b, size_t vl)
  10 {
  11   return __riscv_vadd_vv_i32m1 (a, b, vl);
  12 }
  13
  14 void
  15 test_2 ()
  16 {
  17   vint32m1_t a;
  18 }