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RISC-V: Allow RVV intrinsic when function target("arch=+v")
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / rvv / base / target_attribute_v_with_intrinsic-1.c
blobdfe8191021e40c3bf1961cd481f285efc45565dc
1 /* Test that we do not have error when compile */
2 /* { dg-do compile } */
3 /* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
4
5 #include "riscv_vector.h"
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