gcc/config/riscv/riscv-c.cc

   1 /* RISC-V-specific code for C family languages.
   2    Copyright (C) 2011-2024 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3, or (at your option)
  10 any later version.
  11
  12 GCC is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING3.  If not see
  19 <http://www.gnu.org/licenses/>.  */
  20
  21 #define IN_TARGET_CODE 1
  22
  23 #define INCLUDE_STRING
  24 #include "config.h"
  25 #include "system.h"
  26 #include "coretypes.h"
  27 #include "tm.h"
  28 #include "c-family/c-common.h"
  29 #include "cpplib.h"
  30 #include "c-family/c-pragma.h"
  31 #include "target.h"
  32 #include "tm_p.h"
  33 #include "riscv-subset.h"
  34
  35 #define builtin_define(TXT) cpp_define (pfile, TXT)
  36
  37 static int
  38 riscv_ext_version_value (unsigned major, unsigned minor)
  39 {
  40   return (major * RISCV_MAJOR_VERSION_BASE)
  41     + (minor * RISCV_MINOR_VERSION_BASE);
  42 }
  43
  44 /* Implement TARGET_CPU_CPP_BUILTINS.  */
  45
  46 void
  47 riscv_cpu_cpp_builtins (cpp_reader *pfile)
  48 {
  49   builtin_define ("__riscv");
  50
  51   if (TARGET_RVC || TARGET_ZCA)
  52     builtin_define ("__riscv_compressed");
  53
  54   if (TARGET_RVE)
  55     builtin_define (TARGET_64BIT ? "__riscv_64e" : "__riscv_32e");
  56
  57   if (TARGET_ATOMIC)
  58     builtin_define ("__riscv_atomic");
  59
  60   if (TARGET_MUL)
  61     builtin_define ("__riscv_mul");
  62   if (TARGET_DIV)
  63     builtin_define ("__riscv_div");
  64   if (TARGET_DIV && TARGET_MUL)
  65     builtin_define ("__riscv_muldiv");
  66
  67   builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8);
  68   if (TARGET_HARD_FLOAT)
  69     builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
  70
  71   if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV)
  72     {
  73       builtin_define ("__riscv_fdiv");
  74       builtin_define ("__riscv_fsqrt");
  75     }
  76
  77   switch (riscv_abi)
  78     {
  79     case ABI_ILP32E:
  80     case ABI_LP64E:
  81       builtin_define ("__riscv_abi_rve");
  82       gcc_fallthrough ();
  83
  84     case ABI_ILP32:
  85     case ABI_LP64:
  86       builtin_define ("__riscv_float_abi_soft");
  87       break;
  88
  89     case ABI_ILP32F:
  90     case ABI_LP64F:
  91       builtin_define ("__riscv_float_abi_single");
  92       break;
  93
  94     case ABI_ILP32D:
  95     case ABI_LP64D:
  96       builtin_define ("__riscv_float_abi_double");
  97       break;
  98     }
  99
 100   switch (riscv_cmodel)
 101     {
 102     case CM_MEDLOW:
 103       builtin_define ("__riscv_cmodel_medlow");
 104       break;
 105
 106     case CM_LARGE:
 107       builtin_define ("__riscv_cmodel_large");
 108       break;
 109
 110     case CM_PIC:
 111     case CM_MEDANY:
 112       builtin_define ("__riscv_cmodel_medany");
 113       break;
 114     }
 115
 116   if (riscv_user_wants_strict_align)
 117     builtin_define_with_int_value ("__riscv_misaligned_avoid", 1);
 118   else if (riscv_slow_unaligned_access_p)
 119     builtin_define_with_int_value ("__riscv_misaligned_slow", 1);
 120   else
 121     builtin_define_with_int_value ("__riscv_misaligned_fast", 1);
 122
 123   if (TARGET_MIN_VLEN != 0)
 124     builtin_define_with_int_value ("__riscv_v_min_vlen", TARGET_MIN_VLEN);
 125
 126   if (TARGET_VECTOR_ELEN_64)
 127     builtin_define_with_int_value ("__riscv_v_elen", 64);
 128   else if (TARGET_VECTOR_ELEN_32)
 129     builtin_define_with_int_value ("__riscv_v_elen", 32);
 130
 131   if (TARGET_VECTOR_ELEN_FP_64)
 132     builtin_define_with_int_value ("__riscv_v_elen_fp", 64);
 133   else if (TARGET_VECTOR_ELEN_FP_32)
 134     builtin_define_with_int_value ("__riscv_v_elen_fp", 32);
 135   else if (TARGET_MIN_VLEN != 0)
 136     builtin_define_with_int_value ("__riscv_v_elen_fp", 0);
 137
 138   if (TARGET_MIN_VLEN)
 139     {
 140       builtin_define ("__riscv_vector");
 141       builtin_define_with_int_value ("__riscv_v_intrinsic",
 142                                      riscv_ext_version_value (0, 12));
 143
 144       if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)
 145         builtin_define_with_int_value ("__riscv_v_fixed_vlen", TARGET_MIN_VLEN);
 146     }
 147
 148   if (TARGET_XTHEADVECTOR)
 149     builtin_define_with_int_value ("__riscv_th_v_intrinsic",
 150                                    riscv_ext_version_value (0, 11));
 151
 152   /* Define architecture extension test macros.  */
 153   builtin_define_with_int_value ("__riscv_arch_test", 1);
 154
 155   const riscv_subset_list *subset_list = riscv_current_subset_list ();
 156   if (!subset_list)
 157     return;
 158
 159   size_t max_ext_len = 0;
 160
 161   /* Figure out the max length of extension name for reserving buffer.   */
 162   for (const riscv_subset_t *subset = subset_list->begin ();
 163        subset != subset_list->end ();
 164        subset = subset->next)
 165     max_ext_len = MAX (max_ext_len, subset->name.length ());
 166
 167   char *buf = (char *)alloca (max_ext_len + 10 /* For __riscv_ and '\0'.  */);
 168
 169   for (const riscv_subset_t *subset = subset_list->begin ();
 170        subset != subset_list->end ();
 171        subset = subset->next)
 172     {
 173       int version_value = riscv_ext_version_value (subset->major_version,
 174                                                    subset->minor_version);
 175       /* Special rule for zicsr and zifencei, it's used for ISA spec 2.2 or
 176          earlier.  */
 177       if ((subset->name == "zicsr" || subset->name == "zifencei")
 178           && version_value == 0)
 179         version_value = riscv_ext_version_value (2, 0);
 180
 181       sprintf (buf, "__riscv_%s", subset->name.c_str ());
 182       builtin_define_with_int_value (buf, version_value);
 183     }
 184 }
 185
 186 /* Implement "#pragma riscv intrinsic".  */
 187
 188 static void
 189 riscv_pragma_intrinsic (cpp_reader *)
 190 {
 191   tree x;
 192
 193   if (pragma_lex (&x) != CPP_STRING)
 194     {
 195       error ("%<#pragma riscv intrinsic%> requires a string parameter");
 196       return;
 197     }
 198
 199   const char *name = TREE_STRING_POINTER (x);
 200
 201   if (strcmp (name, "vector") == 0
 202       || strcmp (name, "xtheadvector") == 0)
 203     {
 204       if (TARGET_VECTOR)
 205         riscv_vector::handle_pragma_vector ();
 206       else /* Indicates riscv_vector.h is included but v is missing in arch  */
 207         {
 208           /* To make the the rvv types and intrinsic API available for the
 209              target("arch=+v") attribute,  we need to temporally enable the
 210              TARGET_VECTOR, and disable it after all initialized.  */
 211           target_flags |= MASK_VECTOR;
 212
 213           riscv_vector::init_builtins ();
 214           riscv_vector::handle_pragma_vector ();
 215
 216           target_flags &= ~MASK_VECTOR;
 217         }
 218     }
 219   else
 220     error ("unknown %<#pragma riscv intrinsic%> option %qs", name);
 221 }
 222
 223 /* Implement TARGET_CHECK_BUILTIN_CALL.  */
 224 static bool
 225 riscv_check_builtin_call (location_t loc, vec<location_t> arg_loc, tree fndecl,
 226                           tree, unsigned int nargs, tree *args)
 227 {
 228   unsigned int code = DECL_MD_FUNCTION_CODE (fndecl);
 229   unsigned int subcode = code >> RISCV_BUILTIN_SHIFT;
 230   switch (code & RISCV_BUILTIN_CLASS)
 231     {
 232     case RISCV_BUILTIN_GENERAL:
 233       return true;
 234
 235     case RISCV_BUILTIN_VECTOR:
 236       return riscv_vector::check_builtin_call (loc, arg_loc, subcode,
 237                                                fndecl, nargs, args);
 238     }
 239   gcc_unreachable ();
 240 }
 241
 242 /* Implement TARGET_RESOLVE_OVERLOADED_BUILTIN.  */
 243 static tree
 244 riscv_resolve_overloaded_builtin (unsigned int uncast_location, tree fndecl,
 245                                   void *uncast_arglist)
 246 {
 247   vec<tree, va_gc> empty = {};
 248   location_t loc = (location_t) uncast_location;
 249   vec<tree, va_gc> *arglist = (vec<tree, va_gc> *) uncast_arglist;
 250   unsigned int code = DECL_MD_FUNCTION_CODE (fndecl);
 251   unsigned int subcode = code >> RISCV_BUILTIN_SHIFT;
 252   tree new_fndecl = NULL_TREE;
 253
 254   if (!arglist)
 255     arglist = &empty;
 256
 257   switch (code & RISCV_BUILTIN_CLASS)
 258     {
 259     case RISCV_BUILTIN_GENERAL:
 260       break;
 261     case RISCV_BUILTIN_VECTOR:
 262       new_fndecl = riscv_vector::resolve_overloaded_builtin (loc, subcode,
 263                                                              fndecl, arglist);
 264       break;
 265     default:
 266       gcc_unreachable ();
 267     }
 268
 269   if (new_fndecl == NULL_TREE)
 270     return new_fndecl;
 271
 272   return build_function_call_vec (loc, vNULL, new_fndecl, arglist, NULL,
 273                                   fndecl);
 274 }
 275
 276 /* Implement REGISTER_TARGET_PRAGMAS.  */
 277
 278 void
 279 riscv_register_pragmas (void)
 280 {
 281   targetm.resolve_overloaded_builtin = riscv_resolve_overloaded_builtin;
 282   targetm.check_builtin_call = riscv_check_builtin_call;
 283   c_register_pragma ("riscv", "intrinsic", riscv_pragma_intrinsic);
 284 }