| blob | 627ef6537ddd49461a32c88b919f136179a723e3 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
123 #ifndef CHECK_STACK_LIMIT
124 #define CHECK_STACK_LIMIT (-1)
125 #endif
127 /* Return index of given mode in mult and division cost tables. */
128 #define MODE_INDEX(mode) \
129 ((mode) == QImode ? 0 \
130 : (mode) == HImode ? 1 \
131 : (mode) == SImode ? 2 \
132 : (mode) == DImode ? 3 \
133 : 4)
135 /* Processor costs (relative to an add) */
136 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
137 #define COSTS_N_BYTES(N) ((N) * 2)
139 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
148 const
171 in QImode, HImode and SImode.
172 Relative to reg-reg move (2). */
176 in SFmode, DFmode and XFmode */
178 in SFmode, DFmode and XFmode */
181 in SImode and DImode */
183 in SImode and DImode */
186 in SImode, DImode and TImode */
188 in SImode, DImode and TImode */
201 ix86_size_memcpy,
202 ix86_size_memset,
214 };
216 /* Processor costs (relative to an add) */
219 DUMMY_STRINGOP_ALGS};
222 DUMMY_STRINGOP_ALGS};
224 static const
247 in QImode, HImode and SImode.
248 Relative to reg-reg move (2). */
252 in SFmode, DFmode and XFmode */
254 in SFmode, DFmode and XFmode */
257 in SImode and DImode */
259 in SImode and DImode */
262 in SImode, DImode and TImode */
264 in SImode, DImode and TImode */
277 i386_memcpy,
278 i386_memset,
290 };
294 DUMMY_STRINGOP_ALGS};
297 DUMMY_STRINGOP_ALGS};
299 static const
322 in QImode, HImode and SImode.
323 Relative to reg-reg move (2). */
327 in SFmode, DFmode and XFmode */
329 in SFmode, DFmode and XFmode */
332 in SImode and DImode */
334 in SImode and DImode */
337 in SImode, DImode and TImode */
339 in SImode, DImode and TImode */
342 shared for code and data, so 4kB is
343 not really precise. */
354 i486_memcpy,
355 i486_memset,
367 };
371 DUMMY_STRINGOP_ALGS};
374 DUMMY_STRINGOP_ALGS};
376 static const
399 in QImode, HImode and SImode.
400 Relative to reg-reg move (2). */
404 in SFmode, DFmode and XFmode */
406 in SFmode, DFmode and XFmode */
409 in SImode and DImode */
411 in SImode and DImode */
414 in SImode, DImode and TImode */
416 in SImode, DImode and TImode */
429 pentium_memcpy,
430 pentium_memset,
442 };
444 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
445 (we ensure the alignment). For small blocks inline loop is still a
446 noticeable win, for bigger blocks either rep movsl or rep movsb is
447 way to go. Rep movsb has apparently more expensive startup time in CPU,
448 but after 4K the difference is down in the noise. */
453 DUMMY_STRINGOP_ALGS};
458 DUMMY_STRINGOP_ALGS};
459 static const
482 in QImode, HImode and SImode.
483 Relative to reg-reg move (2). */
487 in SFmode, DFmode and XFmode */
489 in SFmode, DFmode and XFmode */
492 in SImode and DImode */
494 in SImode and DImode */
497 in SImode, DImode and TImode */
499 in SImode, DImode and TImode */
512 pentiumpro_memcpy,
513 pentiumpro_memset,
525 };
529 DUMMY_STRINGOP_ALGS};
532 DUMMY_STRINGOP_ALGS};
533 static const
556 in QImode, HImode and SImode.
557 Relative to reg-reg move (2). */
561 in SFmode, DFmode and XFmode */
563 in SFmode, DFmode and XFmode */
567 in SImode and DImode */
569 in SImode and DImode */
572 in SImode, DImode and TImode */
574 in SImode, DImode and TImode */
587 geode_memcpy,
588 geode_memset,
600 };
604 DUMMY_STRINGOP_ALGS};
607 DUMMY_STRINGOP_ALGS};
608 static const
631 in QImode, HImode and SImode.
632 Relative to reg-reg move (2). */
636 in SFmode, DFmode and XFmode */
638 in SFmode, DFmode and XFmode */
641 in SImode and DImode */
643 in SImode and DImode */
646 in SImode, DImode and TImode */
648 in SImode, DImode and TImode */
652 have integrated l2 cache, but
653 optimizing for k6 is not important
654 enough to worry about that. */
664 k6_memcpy,
665 k6_memset,
677 };
679 /* For some reason, Athlon deals better with REP prefix (relative to loops)
680 compared to K8. Alignment becomes important after 8 bytes for memcpy and
681 128 bytes for memset. */
684 DUMMY_STRINGOP_ALGS};
687 DUMMY_STRINGOP_ALGS};
688 static const
711 in QImode, HImode and SImode.
712 Relative to reg-reg move (2). */
716 in SFmode, DFmode and XFmode */
718 in SFmode, DFmode and XFmode */
721 in SImode and DImode */
723 in SImode and DImode */
726 in SImode, DImode and TImode */
728 in SImode, DImode and TImode */
741 athlon_memcpy,
742 athlon_memset,
754 };
756 /* K8 has optimized REP instruction for medium sized blocks, but for very
757 small blocks it is better to use loop. For large blocks, libcall can
758 do nontemporary accesses and beat inline considerably. */
769 static const
792 in QImode, HImode and SImode.
793 Relative to reg-reg move (2). */
797 in SFmode, DFmode and XFmode */
799 in SFmode, DFmode and XFmode */
802 in SImode and DImode */
804 in SImode and DImode */
807 in SImode, DImode and TImode */
809 in SImode, DImode and TImode */
814 /* New AMD processors never drop prefetches; if they cannot be performed
815 immediately, they are queued. We set number of simultaneous prefetches
816 to a large constant to reflect this (it probably is not a good idea not
817 to limit number of prefetches at all, as their execution also takes some
818 time). */
828 k8_memcpy,
829 k8_memset,
841 };
843 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
844 very small blocks it is better to use loop. For large blocks, libcall can
845 do nontemporary accesses and beat inline considerably. */
878 in QImode, HImode and SImode.
879 Relative to reg-reg move (2). */
883 in SFmode, DFmode and XFmode */
885 in SFmode, DFmode and XFmode */
888 in SImode and DImode */
890 in SImode and DImode */
893 in SImode, DImode and TImode */
895 in SImode, DImode and TImode */
897 /* On K8:
898 MOVD reg64, xmmreg Double FSTORE 4
899 MOVD reg32, xmmreg Double FSTORE 4
900 On AMDFAM10:
901 MOVD reg64, xmmreg Double FADD 3
902 1/1 1/1
903 MOVD reg32, xmmreg Double FADD 3
904 1/1 1/1 */
908 /* New AMD processors never drop prefetches; if they cannot be performed
909 immediately, they are queued. We set number of simultaneous prefetches
910 to a large constant to reflect this (it probably is not a good idea not
911 to limit number of prefetches at all, as their execution also takes some
912 time). */
922 amdfam10_memcpy,
923 amdfam10_memset,
935 };
937 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
938 very small blocks it is better to use loop. For large blocks, libcall
939 can do nontemporary accesses and beat inline considerably. */
973 in QImode, HImode and SImode.
974 Relative to reg-reg move (2). */
978 in SFmode, DFmode and XFmode */
980 in SFmode, DFmode and XFmode */
983 in SImode and DImode */
985 in SImode and DImode */
988 in SImode, DImode and TImode */
990 in SImode, DImode and TImode */
992 /* On K8:
993 MOVD reg64, xmmreg Double FSTORE 4
994 MOVD reg32, xmmreg Double FSTORE 4
995 On AMDFAM10:
996 MOVD reg64, xmmreg Double FADD 3
997 1/1 1/1
998 MOVD reg32, xmmreg Double FADD 3
999 1/1 1/1 */
1003 /* New AMD processors never drop prefetches; if they cannot be performed
1004 immediately, they are queued. We set number of simultaneous prefetches
1005 to a large constant to reflect this (it probably is not a good idea not
1006 to limit number of prefetches at all, as their execution also takes some
1007 time). */
1017 bdver1_memcpy,
1018 bdver1_memset,
1030 };
1032 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1033 very small blocks it is better to use loop. For large blocks, libcall
1034 can do nontemporary accesses and beat inline considerably. */
1069 in QImode, HImode and SImode.
1070 Relative to reg-reg move (2). */
1074 in SFmode, DFmode and XFmode */
1076 in SFmode, DFmode and XFmode */
1079 in SImode and DImode */
1081 in SImode and DImode */
1084 in SImode, DImode and TImode */
1086 in SImode, DImode and TImode */
1088 /* On K8:
1089 MOVD reg64, xmmreg Double FSTORE 4
1090 MOVD reg32, xmmreg Double FSTORE 4
1091 On AMDFAM10:
1092 MOVD reg64, xmmreg Double FADD 3
1093 1/1 1/1
1094 MOVD reg32, xmmreg Double FADD 3
1095 1/1 1/1 */
1099 /* New AMD processors never drop prefetches; if they cannot be performed
1100 immediately, they are queued. We set number of simultaneous prefetches
1101 to a large constant to reflect this (it probably is not a good idea not
1102 to limit number of prefetches at all, as their execution also takes some
1103 time). */
1113 bdver2_memcpy,
1114 bdver2_memset,
1126 };
1129 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1130 very small blocks it is better to use loop. For large blocks, libcall
1131 can do nontemporary accesses and beat inline considerably. */
1164 in QImode, HImode and SImode.
1165 Relative to reg-reg move (2). */
1169 in SFmode, DFmode and XFmode */
1171 in SFmode, DFmode and XFmode */
1174 in SImode and DImode */
1176 in SImode and DImode */
1179 in SImode, DImode and TImode */
1181 in SImode, DImode and TImode */
1186 /* New AMD processors never drop prefetches; if they cannot be performed
1187 immediately, they are queued. We set number of simultaneous prefetches
1188 to a large constant to reflect this (it probably is not a good idea not
1189 to limit number of prefetches at all, as their execution also takes some
1190 time). */
1200 bdver3_memcpy,
1201 bdver3_memset,
1213 };
1215 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1216 very small blocks it is better to use loop. For large blocks, libcall
1217 can do nontemporary accesses and beat inline considerably. */
1250 in QImode, HImode and SImode.
1251 Relative to reg-reg move (2). */
1255 in SFmode, DFmode and XFmode */
1257 in SFmode, DFmode and XFmode */
1260 in SImode and DImode */
1262 in SImode and DImode */
1265 in SImode, DImode and TImode */
1267 in SImode, DImode and TImode */
1272 /* New AMD processors never drop prefetches; if they cannot be performed
1273 immediately, they are queued. We set number of simultaneous prefetches
1274 to a large constant to reflect this (it probably is not a good idea not
1275 to limit number of prefetches at all, as their execution also takes some
1276 time). */
1286 bdver4_memcpy,
1287 bdver4_memset,
1299 };
1301 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1302 very small blocks it is better to use loop. For large blocks, libcall can
1303 do nontemporary accesses and beat inline considerably. */
1336 in QImode, HImode and SImode.
1337 Relative to reg-reg move (2). */
1341 in SFmode, DFmode and XFmode */
1343 in SFmode, DFmode and XFmode */
1346 in SImode and DImode */
1348 in SImode and DImode */
1351 in SImode, DImode and TImode */
1353 in SImode, DImode and TImode */
1355 /* On K8:
1356 MOVD reg64, xmmreg Double FSTORE 4
1357 MOVD reg32, xmmreg Double FSTORE 4
1358 On AMDFAM10:
1359 MOVD reg64, xmmreg Double FADD 3
1360 1/1 1/1
1361 MOVD reg32, xmmreg Double FADD 3
1362 1/1 1/1 */
1375 btver1_memcpy,
1376 btver1_memset,
1388 };
1422 in QImode, HImode and SImode.
1423 Relative to reg-reg move (2). */
1427 in SFmode, DFmode and XFmode */
1429 in SFmode, DFmode and XFmode */
1432 in SImode and DImode */
1434 in SImode and DImode */
1437 in SImode, DImode and TImode */
1439 in SImode, DImode and TImode */
1441 /* On K8:
1442 MOVD reg64, xmmreg Double FSTORE 4
1443 MOVD reg32, xmmreg Double FSTORE 4
1444 On AMDFAM10:
1445 MOVD reg64, xmmreg Double FADD 3
1446 1/1 1/1
1447 MOVD reg32, xmmreg Double FADD 3
1448 1/1 1/1 */
1460 btver2_memcpy,
1461 btver2_memset,
1473 };
1477 DUMMY_STRINGOP_ALGS};
1481 DUMMY_STRINGOP_ALGS};
1483 static const
1506 in QImode, HImode and SImode.
1507 Relative to reg-reg move (2). */
1511 in SFmode, DFmode and XFmode */
1513 in SFmode, DFmode and XFmode */
1516 in SImode and DImode */
1518 in SImode and DImode */
1521 in SImode, DImode and TImode */
1523 in SImode, DImode and TImode */
1536 pentium4_memcpy,
1537 pentium4_memset,
1549 };
1562 static const
1585 in QImode, HImode and SImode.
1586 Relative to reg-reg move (2). */
1590 in SFmode, DFmode and XFmode */
1592 in SFmode, DFmode and XFmode */
1595 in SImode and DImode */
1597 in SImode and DImode */
1600 in SImode, DImode and TImode */
1602 in SImode, DImode and TImode */
1615 nocona_memcpy,
1616 nocona_memset,
1628 };
1639 static const
1662 in QImode, HImode and SImode.
1663 Relative to reg-reg move (2). */
1667 in SFmode, DFmode and XFmode */
1669 in SFmode, DFmode and XFmode */
1672 in SImode and DImode */
1674 in SImode and DImode */
1677 in SImode, DImode and TImode */
1679 in SImode, DImode and TImode */
1692 atom_memcpy,
1693 atom_memset,
1705 };
1716 static const
1739 in QImode, HImode and SImode.
1740 Relative to reg-reg move (2). */
1744 in SFmode, DFmode and XFmode */
1746 in SFmode, DFmode and XFmode */
1749 in SImode and DImode */
1751 in SImode and DImode */
1754 in SImode, DImode and TImode */
1756 in SImode, DImode and TImode */
1769 slm_memcpy,
1770 slm_memset,
1782 };
1793 static const
1816 in QImode, HImode and SImode.
1817 Relative to reg-reg move (2). */
1821 in SFmode, DFmode and XFmode */
1823 in SFmode, DFmode and XFmode */
1826 in SImode and DImode */
1828 in SImode and DImode */
1831 in SImode, DImode and TImode */
1833 in SImode, DImode and TImode */
1846 intel_memcpy,
1847 intel_memset,
1859 };
1861 /* Generic should produce code tuned for Core-i7 (and newer chips)
1862 and btver1 (and newer chips). */
1874 static const
1877 /* On all chips taken into consideration lea is 2 cycles and more. With
1878 this cost however our current implementation of synth_mult results in
1879 use of unnecessary temporary registers causing regression on several
1880 SPECfp benchmarks. */
1901 in QImode, HImode and SImode.
1902 Relative to reg-reg move (2). */
1906 in SFmode, DFmode and XFmode */
1908 in SFmode, DFmode and XFmode */
1911 in SImode and DImode */
1913 in SImode and DImode */
1916 in SImode, DImode and TImode */
1918 in SImode, DImode and TImode */
1924 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1925 value is increased to perhaps more appropriate value of 5. */
1933 generic_memcpy,
1934 generic_memset,
1946 };
1948 /* core_cost should produce code tuned for Core familly of CPUs. */
1961 static const
1964 /* On all chips taken into consideration lea is 2 cycles and more. With
1965 this cost however our current implementation of synth_mult results in
1966 use of unnecessary temporary registers causing regression on several
1967 SPECfp benchmarks. */
1988 in QImode, HImode and SImode.
1989 Relative to reg-reg move (2). */
1993 in SFmode, DFmode and XFmode */
1995 in SFmode, DFmode and XFmode */
1998 in SImode and DImode */
2000 in SImode and DImode */
2003 in SImode, DImode and TImode */
2005 in SImode, DImode and TImode */
2011 /* FIXME perhaps more appropriate value is 5. */
2019 core_memcpy,
2020 core_memset,
2032 };
2035 /* Set by -mtune. */
2038 /* Set by -mtune or -Os. */
2041 /* Processor feature/optimization bitmasks. */
2042 #define m_386 (1<<PROCESSOR_I386)
2043 #define m_486 (1<<PROCESSOR_I486)
2044 #define m_PENT (1<<PROCESSOR_PENTIUM)
2045 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2046 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2047 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2048 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2049 #define m_CORE2 (1<<PROCESSOR_CORE2)
2050 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2051 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2052 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2053 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2054 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2055 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2056 #define m_KNL (1<<PROCESSOR_KNL)
2057 #define m_INTEL (1<<PROCESSOR_INTEL)
2059 #define m_GEODE (1<<PROCESSOR_GEODE)
2060 #define m_K6 (1<<PROCESSOR_K6)
2061 #define m_K6_GEODE (m_K6 | m_GEODE)
2062 #define m_K8 (1<<PROCESSOR_K8)
2063 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2064 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2065 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2066 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2067 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2068 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2069 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2070 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2071 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2072 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2073 #define m_BTVER (m_BTVER1 | m_BTVER2)
2074 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2076 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2079 #undef DEF_TUNE
2080 #define DEF_TUNE(tune, name, selector) name,
2082 #undef DEF_TUNE
2083 };
2085 /* Feature tests against the various tunings. */
2088 /* Feature tests against the various tunings used to create ix86_tune_features
2089 based on the processor mask. */
2091 #undef DEF_TUNE
2092 #define DEF_TUNE(tune, name, selector) selector,
2094 #undef DEF_TUNE
2095 };
2097 /* Feature tests against the various architecture variations. */
2100 /* Feature tests against the various architecture variations, used to create
2101 ix86_arch_features based on the processor mask. */
2103 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2106 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2109 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2112 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2115 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2117 };
2119 /* In case the average insn count for single function invocation is
2120 lower than this constant, emit fast (but longer) prologue and
2121 epilogue code. */
2122 #define FAST_PROLOGUE_INSN_COUNT 20
2124 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2129 /* Array of the smallest class containing reg number REGNO, indexed by
2130 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2133 {
2134 /* ax, dx, cx, bx */
2136 /* si, di, bp, sp */
2138 /* FP registers */
2141 /* arg pointer */
2142 NON_Q_REGS,
2143 /* flags, fpsr, fpcr, frame */
2145 /* SSE registers */
2148 /* MMX registers */
2151 /* REX registers */
2154 /* SSE REX registers */
2157 /* AVX-512 SSE registers */
2162 /* Mask registers. */
2165 /* MPX bound registers */
2167 };
2169 /* The "default" register map used in 32bit mode. */
2172 {
2184 };
2186 /* The "default" register map used in 64bit mode. */
2189 {
2201 };
2203 /* Define the register numbers to be used in Dwarf debugging information.
2204 The SVR4 reference port C compiler uses the following register numbers
2205 in its Dwarf output code:
2206 0 for %eax (gcc regno = 0)
2207 1 for %ecx (gcc regno = 2)
2208 2 for %edx (gcc regno = 1)
2209 3 for %ebx (gcc regno = 3)
2210 4 for %esp (gcc regno = 7)
2211 5 for %ebp (gcc regno = 6)
2212 6 for %esi (gcc regno = 4)
2213 7 for %edi (gcc regno = 5)
2214 The following three DWARF register numbers are never generated by
2215 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2216 believes these numbers have these meanings.
2217 8 for %eip (no gcc equivalent)
2218 9 for %eflags (gcc regno = 17)
2219 10 for %trapno (no gcc equivalent)
2220 It is not at all clear how we should number the FP stack registers
2221 for the x86 architecture. If the version of SDB on x86/svr4 were
2222 a bit less brain dead with respect to floating-point then we would
2223 have a precedent to follow with respect to DWARF register numbers
2224 for x86 FP registers, but the SDB on x86/svr4 is so completely
2225 broken with respect to FP registers that it is hardly worth thinking
2226 of it as something to strive for compatibility with.
2227 The version of x86/svr4 SDB I have at the moment does (partially)
2228 seem to believe that DWARF register number 11 is associated with
2229 the x86 register %st(0), but that's about all. Higher DWARF
2230 register numbers don't seem to be associated with anything in
2231 particular, and even for DWARF regno 11, SDB only seems to under-
2232 stand that it should say that a variable lives in %st(0) (when
2233 asked via an `=' command) if we said it was in DWARF regno 11,
2234 but SDB still prints garbage when asked for the value of the
2235 variable in question (via a `/' command).
2236 (Also note that the labels SDB prints for various FP stack regs
2237 when doing an `x' command are all wrong.)
2238 Note that these problems generally don't affect the native SVR4
2239 C compiler because it doesn't allow the use of -O with -g and
2240 because when it is *not* optimizing, it allocates a memory
2241 location for each floating-point variable, and the memory
2242 location is what gets described in the DWARF AT_location
2243 attribute for the variable in question.
2244 Regardless of the severe mental illness of the x86/svr4 SDB, we
2245 do something sensible here and we use the following DWARF
2246 register numbers. Note that these are all stack-top-relative
2247 numbers.
2248 11 for %st(0) (gcc regno = 8)
2249 12 for %st(1) (gcc regno = 9)
2250 13 for %st(2) (gcc regno = 10)
2251 14 for %st(3) (gcc regno = 11)
2252 15 for %st(4) (gcc regno = 12)
2253 16 for %st(5) (gcc regno = 13)
2254 17 for %st(6) (gcc regno = 14)
2255 18 for %st(7) (gcc regno = 15)
2256 */
2258 {
2270 };
2272 /* Define parameter passing and return registers. */
2275 {
2277 };
2280 {
2282 };
2285 {
2287 };
2289 /* Additional registers that are clobbered by SYSV calls. */
2292 {
2297 };
2299 /* Define the structure for the machine field in struct function. */
2304 rtx rtl;
2306 };
2308 /* Structure describing stack frame layout.
2309 Stack grows downward:
2311 [arguments]
2312 <- ARG_POINTER
2313 saved pc
2315 saved static chain if ix86_static_chain_on_stack
2317 saved frame pointer if frame_pointer_needed
2318 <- HARD_FRAME_POINTER
2319 [saved regs]
2320 <- regs_save_offset
2321 [padding0]
2323 [saved SSE regs]
2324 <- sse_regs_save_offset
2325 [padding1] |
2326 | <- FRAME_POINTER
2327 [va_arg registers] |
2328 |
2329 [frame] |
2330 |
2331 [padding2] | = to_allocate
2332 <- STACK_POINTER
2333 */
2334 struct ix86_frame
2335 {
2342 /* The offsets relative to ARG_POINTER. */
2343 HOST_WIDE_INT frame_pointer_offset;
2344 HOST_WIDE_INT hard_frame_pointer_offset;
2345 HOST_WIDE_INT stack_pointer_offset;
2346 HOST_WIDE_INT hfp_save_offset;
2347 HOST_WIDE_INT reg_save_offset;
2348 HOST_WIDE_INT sse_reg_save_offset;
2350 /* When save_regs_using_mov is set, emit prologue using
2351 move instead of push instructions. */
2353 };
2355 /* Which cpu are we scheduling for. */
2358 /* Which cpu are we optimizing for. */
2361 /* Which instruction set architecture to use. */
2364 /* True if processor has SSE prefetch instruction. */
2367 /* -mstackrealign option */
2384 /* Preferred alignment for stack boundary in bits. */
2387 /* Alignment for incoming stack boundary in bits specified at
2388 command line. */
2391 /* Default alignment for incoming stack boundary in bits. */
2394 /* Alignment for incoming stack boundary in bits. */
2397 /* Calling abi specific va_list type nodes. */
2401 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2405 /* Fence to use after loop using movnt. */
2406 tree x86_mfence;
2408 /* Register class used for passing given 64bit part of the argument.
2409 These represent classes as documented by the PS ABI, with the exception
2410 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2411 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2413 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2414 whenever possible (upper half does contain padding). */
2415 enum x86_64_reg_class
2416 {
2417 X86_64_NO_CLASS,
2418 X86_64_INTEGER_CLASS,
2419 X86_64_INTEGERSI_CLASS,
2420 X86_64_SSE_CLASS,
2421 X86_64_SSESF_CLASS,
2422 X86_64_SSEDF_CLASS,
2423 X86_64_SSEUP_CLASS,
2424 X86_64_X87_CLASS,
2425 X86_64_X87UP_CLASS,
2426 X86_64_COMPLEX_X87_CLASS,
2427 X86_64_MEMORY_CLASS
2428 };
2430 #define MAX_CLASSES 8
2432 /* Table of constants used by fldpi, fldln2, etc.... */
2436 \f
2441 const_tree);
2453 enum ix86_function_specific_strings
2454 {
2455 IX86_FUNCTION_SPECIFIC_ARCH,
2456 IX86_FUNCTION_SPECIFIC_TUNE,
2457 IX86_FUNCTION_SPECIFIC_MAX
2458 };
2480 \f
2481 #ifndef SUBTARGET32_DEFAULT_CPU
2483 #endif
2485 /* Whether -mtune= or -march= were specified */
2489 /* Vectorization library interface and handlers. */
2495 /* Processor target table, indexed by processor number */
2496 struct ptt
2497 {
2505 };
2507 /* This table must be in sync with enum processor_type in i386.h. */
2509 {
2536 };
2537 \f
2538 static unsigned int
2540 {
2543 /* vzeroupper instructions are inserted immediately after reload to
2544 account for possible spills from 256bit registers. The pass
2545 reuses mode switching infrastructure by re-running mode insertion
2546 pass, so disable entities that have already been processed. */
2552 /* Call optimize_mode_switching. */
2555 }
2560 {
2570 };
2573 {
2577 {}
2579 /* opt_pass methods: */
2581 {
2585 }
2588 {
2590 }
2596 rtl_opt_pass *
2598 {
2600 }
2602 /* Return true if a red-zone is in use. */
2606 {
2608 }
2609 \f
2610 /* Return a string that documents the current -m options. The caller is
2611 responsible for freeing the string. */
2617 {
2618 struct ix86_target_opts
2619 {
2622 };
2624 /* This table is ordered so that options like -msse4.2 that imply
2625 preceding options while match those first. */
2627 {
2680 };
2682 /* Flag options. */
2684 {
2713 };
2730 /* Add -march= option. */
2732 {
2735 }
2737 /* Add -mtune= option. */
2739 {
2742 }
2744 /* Add -m32/-m64/-mx32. */
2746 {
2749 else
2751 isa &= ~ (OPTION_MASK_ISA_64BIT
2752 | OPTION_MASK_ABI_64
2754 }
2755 else
2759 /* Pick out the options in isa options. */
2761 {
2763 {
2766 }
2767 }
2770 {
2773 isa);
2774 }
2776 /* Add flag options. */
2778 {
2780 {
2783 }
2784 }
2787 {
2790 }
2792 /* Add -fpmath= option. */
2794 {
2797 {
2812 }
2813 }
2815 /* Any options? */
2821 /* Size the string. */
2825 {
2830 }
2832 /* Build the string. */
2837 {
2844 {
2846 line_len++;
2849 {
2853 }
2854 }
2858 {
2862 }
2863 }
2869 }
2871 /* Return true, if profiling code should be emitted before
2872 prologue. Otherwise it returns false.
2873 Note: For x86 with "hotfix" it is sorried. */
2874 static bool
2876 {
2878 }
2880 /* Function that is callable from the debugger to print the current
2881 options. */
2882 void ATTRIBUTE_UNUSED
2884 {
2890 {
2893 }
2894 else
2898 }
2901 #define DEF_ENUM
2902 #define DEF_ALG(alg, name) #name,
2904 #undef DEF_ENUM
2905 #undef DEF_ALG
2906 };
2908 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2909 The string is of the following form (or comma separated list of it):
2911 strategy_alg:max_size:[align|noalign]
2913 where the full size range for the strategy is either [0, max_size] or
2914 [min_size, max_size], in which min_size is the max_size + 1 of the
2915 preceding range. The last size range must have max_size == -1.
2917 Examples:
2919 1.
2920 -mmemcpy-strategy=libcall:-1:noalign
2922 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2925 2.
2926 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2928 This is to tell the compiler to use the following strategy for memset
2929 1) when the expected size is between [1, 16], use rep_8byte strategy;
2930 2) when the size is between [17, 2048], use vector_loop;
2931 3) when the size is > 2048, use libcall. */
2933 struct stringop_size_range
2934 {
2936 stringop_alg alg;
2938 };
2940 static void
2942 {
2950 else
2955 do
2956 {
2966 {
2970 }
2973 {
2977 }
2984 {
2986 alg_name,
2989 }
2993 {
2994 /* rep; movq isn't available in 32-bit code. */
2997 alg_name,
3000 }
3008 else
3009 {
3013 }
3014 n++;
3016 }
3020 {
3025 }
3028 {
3032 }
3034 /* Now override the default algs array. */
3036 {
3042 }
3043 }
3045 \f
3046 /* parse -mtune-ctrl= option. When DUMP is true,
3047 print the features that are explicitly set. */
3049 static void
3051 {
3059 do
3060 {
3067 {
3068 curr_feature_string++;
3070 }
3072 {
3074 {
3080 }
3081 }
3086 }
3089 }
3091 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3092 processor type. */
3094 static void
3096 {
3101 {
3104 else
3106 }
3109 {
3114 }
3117 }
3120 /* Default align_* from the processor table. */
3122 static void
3124 {
3126 {
3129 }
3131 {
3134 }
3136 {
3138 }
3139 }
3141 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook. */
3143 static void
3145 {
3147 }
3149 /* Override various settings based on options. If MAIN_ARGS_P, the
3150 options are from the command line, otherwise they are from
3151 attributes. */
3153 static void
3157 {
3165 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3166 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3167 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3168 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3169 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3170 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3171 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3172 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3173 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3174 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3175 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3176 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3177 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3178 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3179 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3180 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3181 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3182 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3183 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3184 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3185 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3186 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3187 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3188 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3189 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3190 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3191 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3192 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3193 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3194 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3195 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3196 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3197 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3198 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3199 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3200 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3201 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3202 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3203 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3204 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3205 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3206 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3207 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3208 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3209 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3210 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3211 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3212 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3213 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3214 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3215 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3216 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3217 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3218 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3219 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3220 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3221 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3223 #define PTA_CORE2 \
3224 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3225 | PTA_CX16 | PTA_FXSR)
3226 #define PTA_NEHALEM \
3227 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3228 #define PTA_WESTMERE \
3229 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3230 #define PTA_SANDYBRIDGE \
3231 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3232 #define PTA_IVYBRIDGE \
3233 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3234 #define PTA_HASWELL \
3235 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3236 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3237 #define PTA_BROADWELL \
3238 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3239 #define PTA_KNL \
3240 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3241 #define PTA_BONNELL \
3242 (PTA_CORE2 | PTA_MOVBE)
3243 #define PTA_SILVERMONT \
3244 (PTA_WESTMERE | PTA_MOVBE)
3246 /* if this reaches 64, need to widen struct pta flags below */
3248 static struct pta
3249 {
3254 }
3256 {
3290 PTA_SANDYBRIDGE},
3292 PTA_SANDYBRIDGE},
3294 PTA_IVYBRIDGE},
3296 PTA_IVYBRIDGE},
3388 PTA_64BIT
3390 };
3392 /* -mrecip options. */
3393 static struct
3394 {
3397 }
3399 {
3406 };
3410 /* Set up prefix/suffix so the error messages refer to either the command
3411 line argument, or the attribute(target). */
3413 {
3417 }
3418 else
3419 {
3423 }
3425 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3426 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3429 #ifdef TARGET_BI_ARCH
3430 else
3431 {
3432 #if TARGET_BI_ARCH == 1
3433 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3434 is on and OPTION_MASK_ABI_X32 is off. We turn off
3435 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3436 -mx32. */
3439 #else
3440 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3441 on and OPTION_MASK_ABI_64 is off. We turn off
3442 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3443 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3447 #endif
3448 }
3449 #endif
3452 {
3453 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3454 OPTION_MASK_ABI_64 for TARGET_X32. */
3457 }
3460 | OPTION_MASK_ABI_X32
3463 {
3464 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3465 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3468 }
3470 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3471 SUBTARGET_OVERRIDE_OPTIONS;
3472 #endif
3474 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3475 SUBSUBTARGET_OVERRIDE_OPTIONS;
3476 #endif
3478 /* -fPIC is the default for x86_64. */
3482 /* Need to check -mtune=generic first. */
3484 {
3485 /* As special support for cross compilers we read -mtune=native
3486 as -mtune=generic. With native compilers we won't see the
3487 -mtune=native, as it was changed by the driver. */
3489 {
3491 }
3496 }
3497 else
3498 {
3502 {
3503 opts->x_ix86_tune_string
3506 }
3508 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3509 or defaulted. We need to use a sensible tune option. */
3511 {
3513 }
3514 }
3518 {
3519 /* rep; movq isn't available in 32-bit code. */
3522 }
3525 opts->x_ix86_arch_string
3528 else
3532 {
3540 }
3541 else
3548 /* For targets using ms ABI enable ms-extensions, if not
3549 explicit turned off. For non-ms ABI we turn off this
3550 option. */
3555 {
3557 {
3601 {
3604 }
3612 }
3613 }
3614 else
3615 {
3616 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3617 use of rip-relative addressing. This eliminates fixups that
3618 would otherwise be needed if this object is to be placed in a
3619 DLL, and is essentially just as efficient as direct addressing. */
3625 else
3627 }
3629 {
3632 }
3640 {
3643 /* Default cpu tuning to the architecture. */
3821 }
3845 {
3849 {
3851 {
3853 {
3861 }
3862 else
3865 }
3866 }
3867 /* Intel CPUs have always interpreted SSE prefetch instructions as
3868 NOPs; so, we can enable SSE prefetch instructions even when
3869 -mtune (rather than -march) points us to a processor that has them.
3870 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3871 higher processors. */
3876 }
3884 #ifndef USE_IX86_FRAME_POINTER
3885 #define USE_IX86_FRAME_POINTER 0
3886 #endif
3888 #ifndef USE_X86_64_FRAME_POINTER
3889 #define USE_X86_64_FRAME_POINTER 0
3890 #endif
3892 /* Set the default values for switches whose default depends on TARGET_64BIT
3893 in case they weren't overwritten by command line options. */
3895 {
3903 opts->x_flag_unwind_tables
3907 }
3908 else
3909 {
3911 opts->x_flag_omit_frame_pointer
3917 }
3920 /* TODO: ix86_cost should be chosen at instruction or function granuality
3921 so for cold code we use size_cost even in !optimize_size compilation. */
3924 else
3927 /* Arrange to set up i386_stack_locals for all functions. */
3930 /* Validate -mregparm= value. */
3932 {
3936 {
3940 }
3941 }
3945 /* Default align_* from the processor table. */
3948 /* Provide default for -mbranch-cost= value. */
3953 {
3954 opts->x_target_flags
3957 /* Enable by default the SSE and MMX builtins. Do allow the user to
3958 explicitly disable any of these. In particular, disabling SSE and
3959 MMX for kernel code is extremely useful. */
3961 opts->x_ix86_isa_flags
3968 }
3969 else
3970 {
3971 opts->x_target_flags
3975 opts->x_ix86_isa_flags
3978 /* i386 ABI does not specify red zone. It still makes sense to use it
3979 when programmer takes care to stack from being destroyed. */
3982 }
3984 /* Keep nonleaf frame pointers. */
3990 /* If we're doing fast math, we don't care about comparison order
3991 wrt NaNs. This lets us use a shorter comparison sequence. */
3995 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3996 since the insns won't need emulation. */
4000 /* Likewise, if the target doesn't have a 387, or we've specified
4001 software floating point, don't use 387 inline intrinsics. */
4005 /* Turn on MMX builtins for -msse. */
4007 opts->x_ix86_isa_flags
4010 /* Enable SSE prefetch. */
4015 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
4018 opts->x_ix86_isa_flags
4021 /* Enable popcnt instruction for -msse4.2 or -mabm. */
4024 opts->x_ix86_isa_flags
4027 /* Enable lzcnt instruction for -mabm. */
4029 opts->x_ix86_isa_flags
4032 /* Validate -mpreferred-stack-boundary= value or default it to
4033 PREFERRED_STACK_BOUNDARY_DEFAULT. */
4036 {
4043 {
4047 else
4050 }
4051 else
4052 ix86_preferred_stack_boundary
4054 }
4056 /* Set the default value for -mstackrealign. */
4062 /* Validate -mincoming-stack-boundary= value or default it to
4063 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4066 {
4073 else
4074 {
4075 ix86_user_incoming_stack_boundary
4077 ix86_incoming_stack_boundary
4079 }
4080 }
4082 #ifndef NO_PROFILE_COUNTERS
4085 #endif
4089 /* Accept -msseregparm only if at least SSE support is enabled. */
4095 {
4097 {
4099 {
4102 }
4105 {
4108 }
4109 }
4110 }
4111 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4112 fpmath=387. The second is however default at many targets since the
4113 extra 80bit precision of temporaries is considered to be part of ABI.
4114 Overwrite the default at least for -ffast-math.
4115 TODO: -mfpmath=both seems to produce same performing code with bit
4116 smaller binaries. It is however not clear if register allocation is
4117 ready for this setting.
4118 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4119 codegen. We may switch to 387 with -ffast-math for size optimized
4120 functions. */
4124 else
4127 /* If the i387 is disabled, then do not return values in it. */
4131 /* Use external vectorized library in vectorizing intrinsics. */
4134 {
4145 }
4151 /* If stack probes are required, the space used for large function
4152 arguments on the stack must also be probed, so enable
4153 -maccumulate-outgoing-args so this happens in the prologue. */
4156 {
4161 }
4163 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4164 {
4170 }
4172 /* When scheduling description is not available, disable scheduler pass
4173 so it won't slow down the compilation and make x87 code slower. */
4194 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4196 && HAVE_prefetch
4202 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4203 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4208 {
4211 {
4213 ix86_gen_tls_local_dynamic_base_64
4215 }
4216 else
4217 {
4219 ix86_gen_tls_local_dynamic_base_64
4221 }
4222 }
4223 else
4227 {
4237 }
4238 else
4239 {
4249 }
4251 #ifdef USE_IX86_CLD
4252 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4255 #endif
4258 {
4263 }
4265 {
4269 }
4271 {
4272 #if defined(PROFILE_BEFORE_PROLOGUE)
4274 #else
4276 #endif
4277 }
4287 /* Enable 128-bit AVX instruction generation
4288 for the auto-vectorizer. */
4294 {
4301 {
4304 {
4306 q++;
4307 }
4308 else
4313 else
4314 {
4317 {
4320 }
4323 {
4327 }
4328 }
4333 else
4335 }
4336 }
4343 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4344 for 64-bit Bionic. */
4349 ? MASK_LONG_DOUBLE_128
4352 /* Only one of them can be active. */
4356 /* Save the initial options in case the user does function specific
4357 options. */
4359 target_option_default_node = target_option_current_node
4362 /* Handle stack protector */
4364 opts->x_ix86_stack_protector_guard
4367 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4369 {
4373 }
4376 {
4380 }
4381 }
4383 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4385 static void
4387 {
4389 struct register_pass_info insert_vzeroupper_info
4392 };
4397 /* This needs to be done at start up. It's convenient to do it here. */
4399 }
4401 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4404 {
4408 }
4410 /* Update register usage after having seen the compiler flags. */
4412 static void
4414 {
4417 /* For 32-bit targets, squash the REX registers. */
4419 {
4426 }
4428 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4436 {
4437 /* Set/reset conditionally defined registers from
4438 CALL_USED_REGISTERS initializer. */
4442 /* Calculate registers of CLOBBERED_REGS register set
4443 as call used registers from GENERAL_REGS register set. */
4447 }
4449 /* If MMX is disabled, squash the registers. */
4455 /* If SSE is disabled, squash the registers. */
4461 /* If the FPU is disabled, squash the registers. */
4467 /* If AVX512F is disabled, squash the registers. */
4469 {
4475 }
4477 /* If MPX is disabled, squash the registers. */
4481 }
4483 \f
4484 /* Save the current options */
4486 static void
4489 {
4525 /* The fields are char but the variables are not; make sure the
4526 values fit in the fields. */
4531 }
4533 /* Restore the current options */
4535 static void
4538 {
4544 /* We don't change -fPIC. */
4582 /* TODO: ix86_cost should be chosen at instruction or function granuality
4583 so for cold code we use size_cost even in !optimize_size compilation. */
4586 else
4589 /* Recreate the arch feature tests if the arch changed */
4591 {
4596 }
4598 /* Recreate the tune optimization tests */
4601 }
4603 /* Adjust target options after streaming them in. This is mainly about
4604 reconciling them with global options. */
4606 static void
4608 {
4609 /* flag_pic is a global option, but ix86_cmodel is target saved option
4610 partly computed from flag_pic. If flag_pic is on, adjust x_ix86_cmodel
4611 for PIC, or error out. */
4614 {
4633 }
4634 else
4636 {
4651 }
4652 }
4654 /* Print the current options */
4656 static void
4659 {
4677 {
4680 }
4681 }
4683 \f
4684 /* Inner function to process the attribute((target(...))), take an argument and
4685 set the current options from the argument. If we have a list, recursively go
4686 over the list. */
4688 static bool
4693 {
4697 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4698 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4699 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4700 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4701 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4703 enum ix86_opt_type
4704 {
4705 ix86_opt_unknown,
4706 ix86_opt_yes,
4707 ix86_opt_no,
4708 ix86_opt_str,
4709 ix86_opt_enum,
4710 ix86_opt_isa
4711 };
4713 static const struct
4714 {
4721 /* isa options */
4774 /* enum options */
4777 /* string options */
4781 /* flag options */
4783 OPT_mcld,
4784 MASK_CLD),
4787 OPT_mfancy_math_387,
4788 MASK_NO_FANCY_MATH_387),
4791 OPT_mieee_fp,
4792 MASK_IEEE_FP),
4795 OPT_minline_all_stringops,
4796 MASK_INLINE_ALL_STRINGOPS),
4799 OPT_minline_stringops_dynamically,
4800 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4803 OPT_mno_align_stringops,
4804 MASK_NO_ALIGN_STRINGOPS),
4807 OPT_mrecip,
4808 MASK_RECIP),
4810 };
4812 /* If this is a list, recurse to get the options. */
4814 {
4821 enum_opts_set))
4825 }
4828 {
4831 }
4833 /* Handle multiple arguments separated by commas. */
4837 {
4851 {
4855 }
4856 else
4857 {
4860 }
4862 /* Recognize no-xxx. */
4864 {
4868 }
4869 else
4872 /* Find the option. */
4876 {
4884 {
4889 }
4890 }
4892 /* Process the option. */
4894 {
4897 }
4900 {
4906 }
4909 {
4915 else
4917 }
4920 {
4922 {
4925 }
4926 else
4928 }
4931 {
4939 global_dc);
4940 else
4941 {
4944 }
4945 }
4947 else
4949 }
4952 }
4954 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4956 tree
4960 {
4975 /* Process each of the options on the chain. */
4980 /* If the changed options are different from the default, rerun
4981 ix86_option_override_internal, and then save the options away.
4982 The string options are are attribute options, and will be undone
4983 when we copy the save structure. */
4989 {
4990 /* If we are using the default tune= or arch=, undo the string assigned,
4991 and use the default. */
5002 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
5007 {
5010 }
5012 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
5015 /* Add any builtin functions with the new isa if any. */
5018 /* Save the current options unless we are validating options for
5019 #pragma. */
5026 /* Free up memory allocated to hold the strings */
5029 }
5032 }
5034 /* Hook to validate attribute((target("string"))). */
5036 static bool
5039 tree args,
5041 {
5046 /* attribute((target("default"))) does nothing, beyond
5047 affecting multi-versioning. */
5056 /* Get the optimization options of the current function. */
5062 /* Init func_options. */
5070 /* Initialize func_options to the default before its target options can
5071 be set. */
5084 {
5089 }
5092 }
5094 \f
5095 /* Hook to determine if one function can safely inline another. */
5097 static bool
5099 {
5104 /* If callee has no option attributes, then it is ok to inline. */
5108 /* If caller has no option attributes, but callee does then it is not ok to
5109 inline. */
5113 else
5114 {
5118 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5119 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5120 function. */
5125 /* See if we have the same non-isa options. */
5129 /* See if arch, tune, etc. are the same. */
5142 else
5144 }
5147 }
5149 \f
5150 /* Remember the last target of ix86_set_current_function. */
5153 /* Set targets globals to the default (or current #pragma GCC target
5154 if active). Invalidate ix86_previous_fndecl cache. */
5156 void
5158 {
5165 else
5168 }
5170 /* Establish appropriate back-end context for processing the function
5171 FNDECL. The argument might be NULL to indicate processing at top
5172 level, outside of any function scope. */
5173 static void
5175 {
5176 /* Only change the context if the function changes. This hook is called
5177 several times in the course of compiling a function, and we don't want to
5178 slow things down too much or call target_reinit when it isn't safe. */
5182 tree old_tree;
5187 else
5191 {
5195 }
5202 {
5208 else
5210 }
5212 }
5214 \f
5215 /* Return true if this goes in large data/bss. */
5217 static bool
5219 {
5223 /* Functions are never large data. */
5227 /* Automatic variables are never large data. */
5232 {
5238 }
5239 else
5240 {
5243 /* If this is an incomplete type with size 0, then we can't put it
5244 in data because it might be too big when completed. Also,
5245 int_size_in_bytes returns -1 if size can vary or is larger than
5246 an integer in which case also it is safer to assume that it goes in
5247 large data. */
5250 }
5253 }
5255 /* Switch to the appropriate section for output of DECL.
5256 DECL is either a `VAR_DECL' node or a constant of some sort.
5257 RELOC indicates whether forming the initial value of DECL requires
5258 link-time relocations. */
5263 {
5265 {
5269 {
5303 /* We don't split these for medium model. Place them into
5304 default sections and hope for best. */
5306 }
5308 {
5309 /* We might get called with string constants, but get_named_section
5310 doesn't like them as they are not DECLs. Also, we need to set
5311 flags in that case. */
5315 }
5316 }
5318 }
5320 /* Select a set of attributes for section NAME based on the properties
5321 of DECL and whether or not RELOC indicates that DECL's initializer
5322 might contain runtime relocations. */
5324 static unsigned int ATTRIBUTE_UNUSED
5326 {
5340 }
5342 /* Build up a unique section name, expressed as a
5343 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5344 RELOC indicates whether the initial value of EXP requires
5345 link-time relocations. */
5347 static void ATTRIBUTE_UNUSED
5349 {
5351 {
5353 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5357 {
5381 /* We don't split these for medium model. Place them into
5382 default sections and hope for best. */
5384 }
5386 {
5393 /* If we're using one_only, then there needs to be a .gnu.linkonce
5394 prefix to the section name. */
5401 }
5402 }
5404 }
5406 #ifdef COMMON_ASM_OP
5407 /* This says how to output assembler code to declare an
5408 uninitialized external linkage data object.
5410 For medium model x86-64 we need to use .largecomm opcode for
5411 large objects. */
5412 void
5416 {
5420 else
5425 }
5426 #endif
5428 /* Utility function for targets to use in implementing
5429 ASM_OUTPUT_ALIGNED_BSS. */
5431 void
5434 {
5438 else
5441 #ifdef ASM_DECLARE_OBJECT_NAME
5444 #else
5445 /* Standard thing is just output label for the object. */
5449 }
5450 \f
5451 /* Decide whether we must probe the stack before any space allocation
5452 on this target. It's essentially TARGET_STACK_PROBE except when
5453 -fstack-check causes the stack to be already probed differently. */
5455 bool
5457 {
5458 /* Do not probe the stack twice if static stack checking is enabled. */
5463 }
5464 \f
5465 /* Decide whether we can make a sibling call to a function. DECL is the
5466 declaration of the function being targeted by the call and EXP is the
5467 CALL_EXPR representing the call. */
5469 static bool
5471 {
5475 /* If we are generating position-independent code, we cannot sibcall
5476 optimize any indirect call, or a direct call to a global function,
5477 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5479 && !TARGET_64BIT
5480 && flag_pic
5484 /* If we need to align the outgoing stack, then sibcalling would
5485 unalign the stack, which may break the called function. */
5491 {
5494 }
5495 else
5496 {
5497 /* We're looking at the CALL_EXPR, we need the type of the function. */
5502 }
5504 /* Check that the return value locations are the same. Like
5505 if we are returning floats on the 80387 register stack, we cannot
5506 make a sibcall from a function that doesn't return a float to a
5507 function that does or, conversely, from a function that does return
5508 a float to a function that doesn't; the necessary stack adjustment
5509 would not be executed. This is also the place we notice
5510 differences in the return value ABI. Note that it is ok for one
5511 of the functions to have void return type as long as the return
5512 value of the other is passed in a register. */
5517 {
5520 }
5522 ;
5527 {
5528 /* The SYSV ABI has more call-clobbered registers;
5529 disallow sibcalls from MS to SYSV. */
5533 }
5534 else
5535 {
5536 /* If this call is indirect, we'll need to be able to use a
5537 call-clobbered register for the address of the target function.
5538 Make sure that all such registers are not used for passing
5539 parameters. Note that DLLIMPORT functions are indirect. */
5542 {
5544 {
5545 /* ??? Need to count the actual number of registers to be used,
5546 not the possible number of registers. Fix later. */
5548 }
5549 }
5550 }
5552 /* Otherwise okay. That also includes certain types of indirect calls. */
5554 }
5556 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5557 and "sseregparm" calling convention attributes;
5558 arguments as in struct attribute_spec.handler. */
5560 static tree
5562 tree args,
5565 {
5570 {
5572 name);
5575 }
5577 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5579 {
5580 tree cst;
5583 {
5585 }
5588 {
5590 }
5594 {
5597 name);
5599 }
5601 {
5605 }
5608 }
5611 {
5612 /* Do not warn when emulating the MS ABI. */
5617 name);
5620 }
5622 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5624 {
5626 {
5628 }
5630 {
5632 }
5634 {
5636 }
5638 {
5640 }
5641 }
5643 /* Can combine stdcall with fastcall (redundant), regparm and
5644 sseregparm. */
5646 {
5648 {
5650 }
5652 {
5654 }
5656 {
5658 }
5659 }
5661 /* Can combine cdecl with regparm and sseregparm. */
5663 {
5665 {
5667 }
5669 {
5671 }
5673 {
5675 }
5676 }
5678 {
5681 name);
5683 {
5685 }
5687 {
5689 }
5691 {
5693 }
5694 }
5696 /* Can combine sseregparm with all attributes. */
5699 }
5701 /* The transactional memory builtins are implicitly regparm or fastcall
5702 depending on the ABI. Override the generic do-nothing attribute that
5703 these builtins were declared with, and replace it with one of the two
5704 attributes that we expect elsewhere. */
5706 static tree
5709 {
5710 tree alt;
5712 /* In no case do we want to add the placeholder attribute. */
5715 /* The 64-bit ABI is unchanged for transactional memory. */
5719 /* ??? Is there a better way to validate 32-bit windows? We have
5720 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5723 else
5724 {
5727 }
5731 }
5733 /* This function determines from TYPE the calling-convention. */
5735 unsigned int
5737 {
5740 tree attrs;
5747 {
5757 /* Regparam isn't allowed for thiscall and fastcall. */
5759 {
5764 }
5768 }
5775 || is_stdarg
5781 }
5783 /* Return 0 if the attributes for two types are incompatible, 1 if they
5784 are compatible, and 2 if they are nearly compatible (which causes a
5785 warning to be generated). */
5787 static int
5789 {
5805 }
5806 \f
5807 /* Return the regparm value for a function with the indicated TYPE and DECL.
5808 DECL may be NULL when calling function indirectly
5809 or considering a libcall. */
5811 static int
5813 {
5814 tree attr;
5825 {
5828 {
5831 }
5832 }
5838 /* Use register calling convention for local functions when possible. */
5841 {
5846 /* Caller and callee must agree on the calling convention, so
5847 checking here just optimize means that with
5848 __attribute__((optimize (...))) caller could use regparm convention
5849 and callee not, or vice versa. Instead look at whether the callee
5850 is optimized or not. */
5853 {
5856 {
5859 /* Make sure no regparm register is taken by a
5860 fixed register variable. */
5862 local_regparm++)
5866 /* We don't want to use regparm(3) for nested functions as
5867 these use a static chain pointer in the third argument. */
5871 /* Save a register for the split stack. */
5875 /* Each fixed register usage increases register pressure,
5876 so less registers should be used for argument passing.
5877 This functionality can be overriden by an explicit
5878 regparm value. */
5881 globals++;
5883 local_regparm
5888 }
5889 }
5890 }
5893 }
5895 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5896 DFmode (2) arguments in SSE registers for a function with the
5897 indicated TYPE and DECL. DECL may be NULL when calling function
5898 indirectly or considering a libcall. Otherwise return 0. */
5900 static int
5902 {
5905 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5906 by the sseregparm attribute. */
5909 {
5911 {
5913 {
5917 else
5920 }
5922 }
5925 }
5934 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5935 (and DFmode for SSE2) arguments in SSE registers. */
5937 /* TARGET_SSE_MATH */
5941 {
5944 {
5945 /* Refuse to produce wrong code when local function with SSE enabled
5946 is called from SSE disabled function.
5947 We may work hard to work out these scenarios but hopefully
5948 it doesnot matter in practice. */
5950 {
5954 }
5957 }
5958 }
5961 }
5963 /* Return true if EAX is live at the start of the function. Used by
5964 ix86_expand_prologue to determine if we need special help before
5965 calling allocate_stack_worker. */
5967 static bool
5969 {
5970 /* Cheat. Don't bother working forward from ix86_function_regparm
5971 to the function type to whether an actual argument is located in
5972 eax. Instead just look at cfg info, which is still close enough
5973 to correct at this point. This gives false positives for broken
5974 functions that might use uninitialized data that happens to be
5975 allocated in eax, but who cares? */
5977 }
5979 static bool
5981 {
5982 tree attr;
5985 {
5991 /* For 32-bit MS-ABI the default is to keep aggregate
5992 return pointer. */
5995 }
5997 }
5999 /* Value is the number of bytes of arguments automatically
6000 popped when returning from a subroutine call.
6001 FUNDECL is the declaration node of the function (as a tree),
6002 FUNTYPE is the data type of the function (as a tree),
6003 or for a library call it is an identifier node for the subroutine name.
6004 SIZE is the number of bytes of arguments passed on the stack.
6006 On the 80386, the RTD insn may be used to pop them if the number
6007 of args is fixed, but if the number is variable then the caller
6008 must pop them all. RTD can't be used for library calls now
6009 because the library is compiled with the Unix compiler.
6010 Use of RTD is a selectable option, since it is incompatible with
6011 standard Unix calling sequences. If the option is not selected,
6012 the caller must always pop the args.
6014 The attribute stdcall is equivalent to RTD on a per module basis. */
6016 static int
6018 {
6021 /* None of the 64-bit ABIs pop arguments. */
6032 /* Lose any fake structure return argument if it is passed on the stack. */
6035 {
6039 }
6042 }
6044 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
6046 static bool
6048 {
6049 /* Check operand constraints in case hard registers were propagated
6050 into insn pattern. This check prevents combine pass from
6051 generating insn patterns with invalid hard register operands.
6052 These invalid insns can eventually confuse reload to error out
6053 with a spill failure. See also PRs 46829 and 46843. */
6055 {
6064 {
6072 /* For pre-AVX disallow unaligned loads/stores where the
6073 instructions don't support it. */
6077 {
6081 }
6083 /* A unary operator may be accepted by the predicate, but it
6084 is irrelevant for matching constraints. */
6089 {
6097 }
6104 /* Operand has no constraints, anything is OK. */
6109 {
6114 && operands_match_p
6118 {
6121 }
6122 }
6126 }
6127 }
6130 }
6131 \f
6132 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6134 static unsigned HOST_WIDE_INT
6136 {
6140 }
6141 \f
6142 /* Argument support functions. */
6144 /* Return true when register may be used to pass function parameters. */
6145 bool
6147 {
6155 {
6159 else
6165 }
6171 /* TODO: The function should depend on current function ABI but
6172 builtins.c would need updating then. Therefore we use the
6173 default ABI. */
6175 /* RAX is used as hidden argument to va_arg functions. */
6181 else
6188 }
6190 /* Return if we do not know how to pass TYPE solely in registers. */
6192 static bool
6194 {
6198 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6199 The layout_type routine is crafty and tries to trick us into passing
6200 currently unsupported vector types on the stack by using TImode. */
6203 }
6205 /* It returns the size, in bytes, of the area reserved for arguments passed
6206 in registers for the function represented by fndecl dependent to the used
6207 abi format. */
6208 int
6210 {
6214 else
6219 }
6221 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6222 call abi used. */
6223 enum calling_abi
6225 {
6227 {
6230 {
6232 {
6234 {
6237 {
6240 }
6241 }
6243 }
6244 }
6248 }
6250 }
6252 /* We add this as a workaround in order to use libc_has_function
6253 hook in i386.md. */
6254 bool
6256 {
6258 }
6260 static bool
6262 {
6264 {
6268 else
6270 }
6272 }
6274 static enum calling_abi
6276 {
6280 }
6282 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6283 call abi used. */
6284 enum calling_abi
6286 {
6290 }
6292 /* Write the extra assembler code needed to declare a function properly. */
6294 void
6296 tree decl)
6297 {
6301 {
6307 }
6309 #ifdef SUBTARGET_ASM_UNWIND_INIT
6311 #endif
6315 /* Output magic byte marker, if hot-patch attribute is set. */
6317 {
6319 {
6320 /* leaq [%rsp + 0], %rsp */
6323 }
6324 else
6325 {
6326 /* movl.s %edi, %edi
6327 push %ebp
6328 movl.s %esp, %ebp */
6331 }
6332 }
6333 }
6335 /* regclass.c */
6338 /* Implementation of call abi switching target hook. Specific to FNDECL
6339 the specific call register sets are set. See also
6340 ix86_conditional_register_usage for more details. */
6341 void
6343 {
6346 else
6348 }
6350 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6351 expensive re-initialization of init_regs each time we switch function context
6352 since this is needed only during RTL expansion. */
6353 static void
6355 {
6359 }
6361 /* Return 1 if pseudo register should be created and used to hold
6362 GOT address for PIC code. */
6363 bool
6365 {
6372 }
6374 /* Initialize large model PIC register. */
6376 static void
6378 {
6380 rtx tmp_reg;
6389 label));
6393 }
6395 /* Create and initialize PIC register if required. */
6396 static void
6398 {
6399 edge entry_edge;
6408 {
6411 else
6413 }
6414 else
6415 {
6416 /* If there is future mcount call in the function it is more profitable
6417 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6426 }
6434 }
6436 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6437 for a call to a function whose data type is FNTYPE.
6438 For a library call, FNTYPE is 0. */
6440 void
6444 tree fndecl,
6446 {
6453 {
6456 {
6460 }
6461 else
6463 }
6464 else
6469 /* Set up the number of registers to use for passing arguments. */
6472 {
6474 ? X86_64_REGPARM_MAX
6476 }
6478 {
6481 {
6483 ? X86_64_SSE_REGPARM_MAX
6485 }
6486 }
6494 /* Because type might mismatch in between caller and callee, we need to
6495 use actual type of function for local calls.
6496 FIXME: cgraph_analyze can be told to actually record if function uses
6497 va_start so for local functions maybe_vaarg can be made aggressive
6498 helping K&R code.
6499 FIXME: once typesytem is fixed, we won't need this code anymore. */
6512 {
6513 /* If there are variable arguments, then we won't pass anything
6514 in registers in 32-bit mode. */
6516 {
6525 }
6527 /* Use ecx and edx registers if function has fastcall attribute,
6528 else look for regparm information. */
6530 {
6533 {
6536 }
6538 {
6541 }
6542 else
6544 }
6546 /* Set up the number of SSE registers used for passing SFmode
6547 and DFmode arguments. Warn for mismatching ABI. */
6549 }
6550 }
6552 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6553 But in the case of vector types, it is some vector mode.
6555 When we have only some of our vector isa extensions enabled, then there
6556 are some modes for which vector_mode_supported_p is false. For these
6557 modes, the generic vector support in gcc will choose some non-vector mode
6558 in order to implement the type. By computing the natural mode, we'll
6559 select the proper ABI location for the operand and not depend on whatever
6560 the middle-end decides to do with these vector types.
6562 The midde-end can't deal with the vector types > 16 bytes. In this
6563 case, we return the original mode and warn ABI change if CUM isn't
6564 NULL.
6566 If INT_RETURN is true, warn ABI change if the vector mode isn't
6567 available for function return value. */
6569 static machine_mode
6572 {
6576 {
6579 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6581 {
6586 else
6589 /* Get the mode which has this inner mode and number of units. */
6593 {
6595 {
6600 {
6604 }
6606 {
6610 }
6613 }
6615 {
6620 {
6624 }
6626 {
6630 }
6633 }
6636 {
6641 {
6645 }
6647 {
6651 }
6652 }
6654 {
6659 {
6663 }
6665 {
6669 }
6670 }
6672 }
6675 }
6676 }
6679 }
6681 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6682 this may not agree with the mode that the type system has chosen for the
6683 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6684 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6686 static rtx
6689 {
6690 rtx tmp;
6694 else
6695 {
6699 }
6702 }
6704 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6705 of this code is to classify each 8bytes of incoming argument by the register
6706 class and assign registers accordingly. */
6708 /* Return the union class of CLASS1 and CLASS2.
6709 See the x86-64 PS ABI for details. */
6711 static enum x86_64_reg_class
6713 {
6714 /* Rule #1: If both classes are equal, this is the resulting class. */
6718 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6719 the other class. */
6725 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6729 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6737 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6738 MEMORY is used. */
6747 /* Rule #6: Otherwise class SSE is used. */
6749 }
6751 /* Classify the argument of type TYPE and mode MODE.
6752 CLASSES will be filled by the register class used to pass each word
6753 of the operand. The number of words is returned. In case the parameter
6754 should be passed in memory, 0 is returned. As a special case for zero
6755 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6757 BIT_OFFSET is used internally for handling records and specifies offset
6758 of the offset in bits modulo 512 to avoid overflow cases.
6760 See the x86-64 PS ABI for details.
6761 */
6763 static int
6766 {
6767 HOST_WIDE_INT bytes =
6769 int words
6772 /* Variable sized entities are always passed/returned in memory. */
6781 {
6783 tree field;
6786 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6793 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6794 signalize memory class, so handle it as special case. */
6796 {
6799 }
6801 /* Classify each field of record and merge classes. */
6803 {
6805 /* And now merge the fields of structure. */
6807 {
6809 {
6815 /* Bitfields are always classified as integer. Handle them
6816 early, since later code would consider them to be
6817 misaligned integers. */
6819 {
6828 }
6829 else
6830 {
6835 /* Flexible array member is ignored. */
6842 {
6846 {
6849 "the ABI of passing struct with"
6850 " a flexible array member has"
6852 }
6854 }
6856 subclasses,
6866 }
6867 }
6868 }
6872 /* Arrays are handled as small records. */
6873 {
6880 /* The partial classes are now full classes. */
6891 }
6894 /* Unions are similar to RECORD_TYPE but offset is always 0.
6895 */
6897 {
6899 {
6907 bit_offset);
6912 }
6913 }
6918 }
6921 {
6922 /* When size > 16 bytes, if the first one isn't
6923 X86_64_SSE_CLASS or any other ones aren't
6924 X86_64_SSEUP_CLASS, everything should be passed in
6925 memory. */
6932 }
6934 /* Final merger cleanup. */
6936 {
6937 /* If one class is MEMORY, everything should be passed in
6938 memory. */
6942 /* The X86_64_SSEUP_CLASS should be always preceded by
6943 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6947 {
6948 /* The first one should never be X86_64_SSEUP_CLASS. */
6951 }
6953 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6954 everything should be passed in memory. */
6957 {
6960 /* The first one should never be X86_64_X87UP_CLASS. */
6963 {
6966 "the ABI of passing union with long double"
6968 }
6970 }
6971 }
6973 }
6975 /* Compute alignment needed. We align all types to natural boundaries with
6976 exception of XFmode that is aligned to 64bits. */
6978 {
6987 /* Misaligned fields are always returned in memory. */
6990 }
6992 /* for V1xx modes, just use the base mode */
6997 /* Classification of atomic types. */
6999 {
7015 {
7018 /* Analyze last 128 bits only. */
7022 {
7025 }
7027 {
7030 }
7032 {
7036 }
7038 {
7041 }
7042 else
7044 }
7051 /* OImode shouldn't be used directly. */
7058 else
7076 else
7077 {
7081 {
7084 "the ABI of passing structure with complex float"
7086 }
7089 }
7098 /* This modes is larger than 16 bytes. */
7156 else
7160 }
7161 }
7163 /* Examine the argument and return set number of register required in each
7164 class. Return true iff parameter should be passed in memory. */
7166 static bool
7169 {
7180 {
7201 }
7204 }
7206 /* Construct container for the argument used by GCC interface. See
7207 FUNCTION_ARG for the detailed description. */
7209 static rtx
7213 {
7214 /* The following variables hold the static issued_error state. */
7219 machine_mode tmpmode;
7228 rtx ret;
7239 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7240 some less clueful developer tries to use floating-point anyway. */
7242 {
7244 {
7246 {
7249 }
7250 }
7252 {
7255 }
7257 }
7259 /* Likewise, error if the ABI requires us to return values in the
7260 x87 registers and the user specified -mno-80387. */
7266 {
7268 {
7271 }
7273 }
7275 /* First construct simple cases. Avoid SCmode, since we want to use
7276 single register to pass this type. */
7279 {
7294 /* Zero sized array, struct or class. */
7298 }
7337 /* Otherwise figure out the entries of the PARALLEL. */
7339 {
7343 {
7348 /* Merge TImodes on aligned occasions here too. */
7350 tmpmode
7354 else
7356 /* We've requested 24 bytes we
7357 don't have mode for. Use DImode. */
7364 intreg++;
7372 sse_regno++;
7380 sse_regno++;
7385 {
7391 {
7393 i++;
7394 }
7395 else
7420 }
7426 sse_regno++;
7430 }
7431 }
7433 /* Empty aligned struct, union or class. */
7441 }
7443 /* Update the data in CUM to advance over an argument of mode MODE
7444 and data type TYPE. (TYPE is null for libcalls where that information
7445 may not be available.)
7447 Return a number of integer regsiters advanced over. */
7449 static int
7452 HOST_WIDE_INT words)
7453 {
7457 {
7464 /* FALLTHRU */
7476 {
7479 }
7483 /* OImode shouldn't be used directly. */
7492 /* FALLTHRU */
7514 {
7519 {
7522 }
7523 }
7533 {
7538 {
7541 }
7542 }
7544 }
7547 }
7549 static int
7552 {
7555 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7562 {
7568 }
7569 else
7570 {
7575 }
7576 }
7578 static int
7580 HOST_WIDE_INT words)
7581 {
7582 /* Otherwise, this should be passed indirect. */
7587 {
7591 }
7593 }
7595 /* Update the data in CUM to advance over an argument of mode MODE and
7596 data type TYPE. (TYPE is null for libcalls where that information
7597 may not be available.) */
7599 static void
7602 {
7609 else
7618 {
7619 /* If we pass bounds in BT then just update remained bounds count. */
7621 {
7624 }
7626 /* Update remained number of bounds to force. */
7633 }
7635 /* The first arg not going to Bounds Tables resets this counter. */
7637 /* For unnamed args we always pass bounds to avoid bounds mess when
7638 passed and received types do not match. If bounds do not follow
7639 unnamed arg, still pretend required number of bounds were passed. */
7641 {
7644 }
7650 else
7653 /* For stdarg we expect bounds to be passed for each value passed
7654 in register. */
7657 /* For pointers passed in memory we expect bounds passed in Bounds
7658 Table. */
7661 }
7663 /* Define where to put the arguments to a function.
7664 Value is zero to push the argument on the stack,
7665 or a hard register in which to store the argument.
7667 MODE is the argument's machine mode.
7668 TYPE is the data type of the argument (as a tree).
7669 This is null for libcalls where that information may
7670 not be available.
7671 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7672 the preceding args and about the function being called.
7673 NAMED is nonzero if this argument is a named parameter
7674 (otherwise it is an extra parameter matching an ellipsis). */
7676 static rtx
7680 {
7681 /* Avoid the AL settings for the Unix64 ABI. */
7686 {
7693 /* FALLTHRU */
7699 {
7702 /* Fastcall allocates the first two DWORD (SImode) or
7703 smaller arguments to ECX and EDX if it isn't an
7704 aggregate type . */
7706 {
7712 /* ECX not EAX is the first allocated register. */
7715 }
7717 }
7726 /* FALLTHRU */
7728 /* In 32bit, we pass TImode in xmm registers. */
7736 {
7740 }
7745 /* OImode and XImode shouldn't be used directly. */
7761 {
7765 }
7775 {
7779 }
7781 }
7784 }
7786 static rtx
7789 {
7790 /* Handle a hidden AL argument containing number of registers
7791 for varargs x86-64 functions. */
7795 ? X86_64_SSE_REGPARM_MAX
7800 {
7816 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7820 }
7826 }
7828 static rtx
7831 HOST_WIDE_INT bytes)
7832 {
7835 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7836 We use value of -2 to specify that current function call is MSABI. */
7840 /* If we've run out of registers, it goes on the stack. */
7846 /* Only floating point modes are passed in anything but integer regs. */
7848 {
7851 else
7852 {
7855 /* Unnamed floating parameters are passed in both the
7856 SSE and integer registers. */
7862 }
7863 }
7864 /* Handle aggregated types passed in register. */
7866 {
7871 }
7874 }
7876 /* Return where to put the arguments to a function.
7877 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7879 MODE is the argument's machine mode. TYPE is the data type of the
7880 argument. It is null for libcalls where that information may not be
7881 available. CUM gives information about the preceding args and about
7882 the function being called. NAMED is nonzero if this argument is a
7883 named parameter (otherwise it is an extra parameter matching an
7884 ellipsis). */
7886 static rtx
7889 {
7893 rtx arg;
7895 /* All pointer bounds argumntas are handled separately here. */
7898 {
7899 /* Return NULL if bounds are forced to go in Bounds Table. */
7902 /* Return the next available bound reg if any. */
7905 /* Return the next special slot number otherwise. */
7906 else
7910 }
7914 else
7918 /* To simplify the code below, represent vector types with a vector mode
7919 even if MMX/SSE are not active. */
7927 else
7931 }
7933 /* A C expression that indicates when an argument must be passed by
7934 reference. If nonzero for an argument, a copy of that argument is
7935 made in memory and a pointer to the argument is passed instead of
7936 the argument itself. The pointer is passed in whatever way is
7937 appropriate for passing a pointer to that type. */
7939 static bool
7942 {
7945 /* Bounds are never passed by reference. */
7950 /* See Windows x64 Software Convention. */
7952 {
7955 {
7956 /* Arrays are passed by reference. */
7961 {
7962 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7963 are passed by reference. */
7965 }
7966 }
7968 /* __m128 is passed by reference. */
7974 }
7975 }
7980 }
7982 /* Return true when TYPE should be 128bit aligned for 32bit argument
7983 passing ABI. XXX: This function is obsolete and is only used for
7984 checking psABI compatibility with previous versions of GCC. */
7986 static bool
7988 {
8000 {
8001 /* Walk the aggregates recursively. */
8003 {
8007 {
8008 tree field;
8010 /* Walk all the structure fields. */
8012 {
8016 }
8018 }
8021 /* Just for use if some languages passes arrays by value. */
8028 }
8029 }
8031 }
8033 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
8034 XXX: This function is obsolete and is only used for checking psABI
8035 compatibility with previous versions of GCC. */
8037 static unsigned int
8040 {
8041 /* In 32bit, only _Decimal128 and __float128 are aligned to their
8042 natural boundaries. */
8044 {
8045 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
8046 make an exception for SSE modes since these require 128bit
8047 alignment.
8049 The handling here differs from field_alignment. ICC aligns MMX
8050 arguments to 4 byte boundaries, while structure fields are aligned
8051 to 8 byte boundaries. */
8053 {
8056 }
8057 else
8058 {
8061 }
8062 }
8066 }
8068 /* Return true when TYPE should be 128bit aligned for 32bit argument
8069 passing ABI. */
8071 static bool
8073 {
8083 {
8084 /* Walk the aggregates recursively. */
8086 {
8090 {
8091 tree field;
8093 /* Walk all the structure fields. */
8095 field;
8097 {
8101 }
8103 }
8106 /* Just for use if some languages passes arrays by value. */
8113 }
8114 }
8115 else
8119 }
8121 /* Gives the alignment boundary, in bits, of an argument with the
8122 specified mode and type. */
8124 static unsigned int
8126 {
8129 {
8130 /* Since the main variant type is used for call, we convert it to
8131 the main variant type. */
8134 }
8135 else
8139 else
8140 {
8145 {
8146 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8148 {
8151 }
8157 }
8160 && !warned
8162 saved_align))
8163 {
8166 "The ABI for passing parameters with %d-byte"
8169 }
8170 }
8173 }
8175 /* Return true if N is a possible register number of function value. */
8177 static bool
8179 {
8181 {
8193 /* Complex values are returned in %st(0)/%st(1) pair. */
8196 /* TODO: The function should depend on current function ABI but
8197 builtins.c would need updating then. Therefore we use the
8198 default ABI. */
8203 /* Complex values are returned in %xmm0/%xmm1 pair. */
8212 }
8215 }
8217 /* Define how to find the value returned by a function.
8218 VALTYPE is the data type of the value (as a tree).
8219 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8220 otherwise, FUNC is 0. */
8222 static rtx
8225 {
8228 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8229 we normally prevent this case when mmx is not available. However
8230 some ABIs may require the result to be returned like DImode. */
8234 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8235 we prevent this case when sse is not available. However some ABIs
8236 may require the result to be returned like integer TImode. */
8241 /* 32-byte vector modes in %ymm0. */
8245 /* 64-byte vector modes in %zmm0. */
8249 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8252 else
8253 /* Most things go in %eax. */
8256 /* Override FP return register with %xmm0 for local functions when
8257 SSE math is enabled or for functions with sseregparm attribute. */
8259 {
8264 }
8266 /* OImode shouldn't be used directly. */
8270 }
8272 static rtx
8274 const_tree valtype)
8275 {
8276 rtx ret;
8278 /* Handle libcalls, which don't provide a type node. */
8280 {
8284 {
8303 }
8306 }
8308 {
8309 /* Pointers are always returned in word_mode. */
8311 }
8317 /* For zero sized structures, construct_container returns NULL, but we
8318 need to keep rest of compiler happy by returning meaningful value. */
8323 }
8325 static rtx
8327 const_tree valtype)
8328 {
8332 {
8334 {
8353 }
8354 }
8356 }
8358 static rtx
8361 {
8376 else
8378 }
8380 static rtx
8382 {
8388 }
8390 /* Return an RTX representing a place where a function returns
8391 or recieves pointer bounds or NULL if no bounds are returned.
8393 VALTYPE is a data type of a value returned by the function.
8395 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8396 or FUNCTION_TYPE of the function.
8398 If OUTGOING is false, return a place in which the caller will
8399 see the return value. Otherwise, return a place where a
8400 function returns a value. */
8402 static rtx
8404 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8406 {
8412 {
8413 bitmap slots;
8415 bitmap_iterator bi;
8423 {
8428 }
8434 }
8435 else
8439 }
8441 /* Pointer function arguments and return values are promoted to
8442 word_mode. */
8444 static machine_mode
8448 {
8450 {
8453 }
8455 for_return);
8456 }
8458 /* Return true if a structure, union or array with MODE containing FIELD
8459 should be accessed using BLKmode. */
8461 static bool
8463 {
8464 /* Union with XFmode must be in BLKmode. */
8468 }
8470 rtx
8472 {
8474 }
8476 /* Return true iff type is returned in memory. */
8478 static bool
8480 {
8481 #ifdef SUBTARGET_RETURN_IN_MEMORY
8483 #else
8485 HOST_WIDE_INT size;
8491 {
8493 {
8496 /* __m128 is returned in xmm0. */
8505 /* Otherwise, the size must be exactly in [1248]. */
8507 }
8508 else
8509 {
8514 }
8515 }
8516 else
8517 {
8527 {
8528 /* User-created vectors small enough to fit in EAX. */
8532 /* Unless ABI prescibes otherwise,
8533 MMX/3dNow values are returned in MM0 if available. */
8538 /* SSE values are returned in XMM0 if available. */
8542 /* AVX values are returned in YMM0 if available. */
8546 /* AVX512F values are returned in ZMM0 if available. */
8549 }
8557 /* OImode shouldn't be used directly. */
8561 }
8562 #endif
8563 }
8565 \f
8566 /* Create the va_list data type. */
8568 /* Returns the calling convention specific va_list date type.
8569 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8571 static tree
8573 {
8576 /* For i386 we use plain pointer to argument area. */
8586 unsigned_type_node);
8589 unsigned_type_node);
8592 ptr_type_node);
8595 ptr_type_node);
8614 /* The correct type is an array type of one element. */
8616 }
8618 /* Setup the builtin va_list data type and for 64-bit the additional
8619 calling convention specific va_list data types. */
8621 static tree
8623 {
8626 /* Initialize abi specific va_list builtin types. */
8628 {
8629 tree t;
8631 {
8636 }
8637 else
8638 {
8643 }
8645 {
8650 }
8651 else
8652 {
8657 }
8658 }
8661 }
8663 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8665 static void
8667 {
8669 alias_set_type set;
8672 /* GPR size of varargs save area. */
8675 else
8678 /* FPR size of varargs save area. We don't need it if we don't pass
8679 anything in SSE registers. */
8682 else
8696 {
8704 }
8707 {
8708 machine_mode smode;
8710 rtx test;
8712 /* Now emit code to save SSE registers. The AX parameter contains number
8713 of SSE parameter registers used to call this function, though all we
8714 actually check here is the zero/non-zero status. */
8719 label));
8721 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8722 we used movdqa (i.e. TImode) instead? Perhaps even better would
8723 be if we could determine the real mode of the data, via a hook
8724 into pass_stdarg. Ignore all that for now. */
8734 {
8743 }
8746 }
8747 }
8749 static void
8751 {
8755 /* Reset to zero, as there might be a sysv vaarg used
8756 before. */
8761 {
8772 }
8773 }
8775 static void
8778 {
8780 CUMULATIVE_ARGS next_cum;
8781 tree fntype;
8783 /* This argument doesn't appear to be used anymore. Which is good,
8784 because the old code here didn't suppress rtl generation. */
8792 /* For varargs, we do not want to skip the dummy va_dcl argument.
8793 For stdargs, we do want to skip the last named argument. */
8801 else
8803 }
8805 static void
8808 tree type,
8811 {
8813 CUMULATIVE_ARGS next_cum;
8814 tree fntype;
8815 rtx save_area;
8820 /* Do nothing if we use plain pointer to argument area. */
8826 /* For varargs, we do not want to skip the dummy va_dcl argument.
8827 For stdargs, we do want to skip the last named argument. */
8841 {
8846 rtx bounds;
8850 else
8851 {
8852 rtx ldx_addr =
8859 }
8865 bnd_reg++;
8866 }
8867 }
8870 /* Checks if TYPE is of kind va_list char *. */
8872 static bool
8874 {
8875 tree canonic;
8877 /* For 32-bit it is always true. */
8883 }
8885 /* Implement va_start. */
8887 static void
8889 {
8893 tree type;
8894 rtx ovf_rtx;
8898 {
8901 /* When we are splitting the stack, we can't refer to the stack
8902 arguments using internal_arg_pointer, because they may be on
8903 the old stack. The split stack prologue will arrange to
8904 leave a pointer to the old stack arguments in a scratch
8905 register, which we here copy to a pseudo-register. The split
8906 stack prologue can't set the pseudo-register directly because
8907 it (the prologue) runs before any registers have been saved. */
8911 {
8912 rtx reg;
8926 }
8927 }
8929 /* Only 64bit target needs something special. */
8931 {
8934 else
8935 {
8945 /* Store zero bounds for va_list. */
8949 next));
8951 }
8953 }
8962 /* The following should be folded into the MEM_REF offset. */
8972 /* Count number of gp and fp argument registers used. */
8978 {
8984 }
8987 {
8993 }
8995 /* Find the overflow area. */
8999 else
9005 /* Store zero bounds for overflow area pointer. */
9014 {
9015 /* Find the register save area.
9016 Prologue of the function save it right above stack frame. */
9022 /* Store zero bounds for save area pointer. */
9029 }
9030 }
9032 /* Implement va_arg. */
9034 static tree
9037 {
9044 rtx container;
9046 tree ptrtype;
9047 machine_mode nat_mode;
9050 /* Only 64bit target needs something special. */
9074 {
9087 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
9089 {
9092 }
9100 }
9102 /* Pull the value out of the saved registers. */
9107 {
9121 /* In case we are passing structure, verify that it is consecutive block
9122 on the register save area. If not we need to do moves. */
9124 {
9125 /* Verify that all registers are strictly consecutive */
9127 {
9131 {
9136 }
9137 }
9138 else
9139 {
9143 {
9148 }
9149 }
9150 }
9152 {
9155 }
9156 else
9157 {
9160 }
9162 /* First ensure that we fit completely in registers. */
9164 {
9171 }
9173 {
9181 }
9183 /* Compute index to start of area used for integer regs. */
9185 {
9186 /* int_addr = gpr + sav; */
9189 }
9191 {
9192 /* sse_addr = fpr + sav; */
9195 }
9197 {
9201 /* addr = &temp; */
9206 {
9210 tree piece_type;
9211 tree addr_type;
9212 tree daddr_type;
9221 {
9226 }
9230 else
9237 {
9240 }
9241 else
9242 {
9245 }
9252 {
9257 }
9258 else
9259 {
9260 tree copy
9265 }
9267 }
9268 }
9271 {
9275 }
9278 {
9282 }
9287 }
9289 /* ... otherwise out of the overflow area. */
9291 /* When we align parameter on stack for caller, if the parameter
9292 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9293 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9294 here with caller. */
9299 /* Care for on-stack alignment if needed. */
9302 else
9303 {
9308 }
9325 }
9326 \f
9327 /* Return true if OPNUM's MEM should be matched
9328 in movabs* patterns. */
9330 bool
9332 {
9344 }
9345 \f
9346 /* Initialize the table of extra 80387 mathematical constants. */
9348 static void
9350 {
9352 {
9358 };
9362 {
9364 /* Ensure each constant is rounded to XFmode precision. */
9367 }
9370 }
9372 /* Return non-zero if the constant is something that
9373 can be loaded with a special instruction. */
9375 int
9377 {
9380 REAL_VALUE_TYPE r;
9392 /* For XFmode constants, try to find a special 80387 instruction when
9393 optimizing for size or on those CPUs that benefit from them. */
9396 {
9405 }
9407 /* Load of the constant -0.0 or -1.0 will be split as
9408 fldz;fchs or fld1;fchs sequence. */
9415 }
9417 /* Return the opcode of the special instruction to be used to load
9418 the constant X. */
9422 {
9424 {
9444 }
9445 }
9447 /* Return the CONST_DOUBLE representing the 80387 constant that is
9448 loaded by the specified special instruction. The argument IDX
9449 matches the return value from standard_80387_constant_p. */
9451 rtx
9453 {
9460 {
9471 }
9474 XFmode);
9475 }
9477 /* Return 1 if X is all 0s and 2 if x is all 1s
9478 in supported SSE/AVX vector mode. */
9480 int
9482 {
9483 machine_mode mode;
9494 {
9515 }
9518 }
9520 /* Return the opcode of the special instruction to be used to load
9521 the constant X. */
9525 {
9527 {
9530 {
9557 }
9567 else
9572 }
9574 }
9576 /* Returns true if OP contains a symbol reference */
9578 bool
9580 {
9589 {
9591 {
9597 }
9601 }
9604 }
9606 /* Return true if it is appropriate to emit `ret' instructions in the
9607 body of a function. Do this only if the epilogue is simple, needing a
9608 couple of insns. Prior to reloading, we can't tell how many registers
9609 must be saved, so return false then. Return false if there is no frame
9610 marker to de-allocate. */
9612 bool
9614 {
9620 /* Don't allow more than 32k pop, since that's all we can do
9621 with one instruction. */
9628 }
9629 \f
9630 /* Value should be nonzero if functions must have frame pointers.
9631 Zero means the frame pointer need not be set up (and parms may
9632 be accessed via the stack pointer) in functions that seem suitable. */
9634 static bool
9636 {
9637 /* If we accessed previous frames, then the generated code expects
9638 to be able to access the saved ebp value in our frame. */
9642 /* Several x86 os'es need a frame pointer for other reasons,
9643 usually pertaining to setjmp. */
9647 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9651 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9652 allocation is 4GB. */
9656 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9657 turns off the frame pointer by default. Turn it back on now if
9658 we've not got a leaf function. */
9668 }
9670 /* Record that the current function accesses previous call frames. */
9672 void
9674 {
9676 }
9677 \f
9678 #ifndef USE_HIDDEN_LINKONCE
9679 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9680 # define USE_HIDDEN_LINKONCE 1
9681 # else
9682 # define USE_HIDDEN_LINKONCE 0
9683 # endif
9684 #endif
9688 /* Fills in the label name that should be used for a pc thunk for
9689 the given register. */
9691 static void
9693 {
9698 else
9700 }
9703 /* This function generates code for -fpic that loads %ebx with
9704 the return address of the caller and then returns. */
9706 static void
9708 {
9713 {
9715 tree decl;
9731 #if TARGET_MACHO
9733 {
9742 }
9743 else
9744 #endif
9746 {
9757 }
9758 else
9759 {
9762 }
9768 /* Make sure unwind info is emitted for the thunk if needed. */
9771 /* Pad stack IP move with 4 instructions (two NOPs count
9772 as one instruction). */
9774 {
9779 }
9790 }
9794 }
9796 /* Emit code for the SET_GOT patterns. */
9800 {
9806 {
9807 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9812 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9813 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9814 an unadorned address. */
9819 }
9824 {
9826 /* We don't need a pic base, we're not producing pic. */
9833 }
9834 else
9835 {
9844 #if TARGET_MACHO
9845 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9846 This is what will be referenced by the Mach-O PIC subsystem. */
9850 /* When we are restoring the pic base at the site of a nonlocal label,
9851 and we decided to emit the pic base above, we will still output a
9852 local label used for calculating the correction offset (even though
9853 the offset will be 0 in that case). */
9857 #endif
9858 }
9864 }
9866 /* Generate an "push" pattern for input ARG. */
9868 static rtx
9870 {
9883 stack_pointer_rtx)),
9884 arg);
9885 }
9887 /* Generate an "pop" pattern for input ARG. */
9889 static rtx
9891 {
9896 arg,
9899 stack_pointer_rtx)));
9900 }
9902 /* Return >= 0 if there is an unused call-clobbered register available
9903 for the entire function. */
9905 static unsigned int
9907 {
9914 {
9916 /* Can't use the same register for both PIC and DRAP. */
9919 else
9924 }
9927 }
9929 /* Return TRUE if we need to save REGNO. */
9931 static bool
9933 {
9936 {
9938 {
9939 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
9940 _mcount in prologue. */
9943 }
9950 }
9953 {
9956 {
9962 }
9963 }
9974 }
9976 /* Return number of saved general prupose registers. */
9978 static int
9980 {
9986 nregs ++;
9988 }
9990 /* Return number of saved SSE registrers. */
9992 static int
9994 {
10002 nregs ++;
10004 }
10006 /* Given FROM and TO register numbers, say whether this elimination is
10007 allowed. If stack alignment is needed, we can only replace argument
10008 pointer with hard frame pointer, or replace frame pointer with stack
10009 pointer. Otherwise, frame pointer elimination is automatically
10010 handled and all other eliminations are valid. */
10012 static bool
10014 {
10020 else
10022 }
10024 /* Return the offset between two registers, one to be eliminated, and the other
10025 its replacement, at the start of a routine. */
10027 HOST_WIDE_INT
10029 {
10038 else
10039 {
10047 }
10048 }
10050 /* In a dynamically-aligned function, we can't know the offset from
10051 stack pointer to frame pointer, so we must ensure that setjmp
10052 eliminates fp against the hard fp (%ebp) rather than trying to
10053 index from %esp up to the top of the frame across a gap that is
10054 of unknown (at compile-time) size. */
10055 static rtx
10057 {
10059 }
10061 /* When using -fsplit-stack, the allocation routines set a field in
10062 the TCB to the bottom of the stack plus this much space, measured
10063 in bytes. */
10065 #define SPLIT_STACK_AVAILABLE 256
10067 /* Fill structure ix86_frame about frame of currently computed function. */
10069 static void
10071 {
10073 HOST_WIDE_INT offset;
10076 HOST_WIDE_INT to_allocate;
10081 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
10082 function prologues and leaf. */
10086 {
10089 }
10090 /* preferred_stack_boundary is never updated for call
10091 expanded from tls descriptor. Update it here. We don't update it in
10092 expand stage because according to the comments before
10093 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
10094 away. */
10097 {
10101 }
10110 /* For SEH we have to limit the amount of code movement into the prologue.
10111 At present we do this via a BLOCKAGE, at which point there's very little
10112 scheduling that can be done, which means that there's very little point
10113 in doing anything except PUSHs. */
10117 /* During reload iteration the amount of registers saved can change.
10118 Recompute the value as needed. Do not recompute when amount of registers
10119 didn't change as reload does multiple calls to the function and does not
10120 expect the decision to change within single iteration. */
10123 {
10129 /* The fast prologue uses move instead of push to save registers. This
10130 is significantly longer, but also executes faster as modern hardware
10131 can execute the moves in parallel, but can't do that for push/pop.
10133 Be careful about choosing what prologue to emit: When function takes
10134 many instructions to execute we may use slow version as well as in
10135 case function is known to be outside hot spot (this is known with
10136 feedback only). Weight the size of function by number of registers
10137 to save as it is cheap to use one or two push instructions but very
10138 slow to use many of them. */
10142 || (flag_branch_probabilities
10145 else
10148 }
10150 frame->save_regs_using_mov
10152 /* If static stack checking is enabled and done with probes,
10153 the registers need to be saved before allocating the frame. */
10156 /* Skip return address. */
10159 /* Skip pushed static chain. */
10163 /* Skip saved base pointer. */
10168 /* The traditional frame pointer location is at the top of the frame. */
10171 /* Register save area */
10175 /* On SEH target, registers are pushed just before the frame pointer
10176 location. */
10180 /* Align and set SSE register save area. */
10182 {
10183 /* The only ABI that has saved SSE registers (Win64) also has a
10184 16-byte aligned default stack, and thus we don't need to be
10185 within the re-aligned local stack frame to save them. */
10189 }
10192 /* The re-aligned stack starts here. Values before this point are not
10193 directly comparable with values below this point. In order to make
10194 sure that no value happens to be the same before and after, force
10195 the alignment computation below to add a non-zero value. */
10199 /* Va-arg area */
10203 /* Align start of frame for local function. */
10212 /* Frame pointer points here. */
10217 /* Add outgoing arguments area. Can be skipped if we eliminated
10218 all the function calls as dead code.
10219 Skipping is however impossible when function calls alloca. Alloca
10220 expander assumes that last crtl->outgoing_args_size
10221 of stack frame are unused. */
10225 {
10228 }
10229 else
10232 /* Align stack boundary. Only needed if we're calling another function
10233 or using alloca. */
10238 /* We've reached end of stack frame. */
10241 /* Size prologue needs to allocate. */
10252 {
10258 }
10259 else
10263 /* The SEH frame pointer location is near the bottom of the frame.
10264 This is enforced by the fact that the difference between the
10265 stack pointer and the frame pointer is limited to 240 bytes in
10266 the unwind data structure. */
10268 {
10269 HOST_WIDE_INT diff;
10271 /* If we can leave the frame pointer where it is, do so. Also, returns
10272 the establisher frame for __builtin_frame_address (0). */
10277 {
10278 /* Ideally we'd determine what portion of the local stack frame
10279 (within the constraint of the lowest 240) is most heavily used.
10280 But without that complication, simply bias the frame pointer
10281 by 128 bytes so as to maximize the amount of the local stack
10282 frame that is addressable with 8-bit offsets. */
10284 }
10285 }
10286 }
10288 /* This is semi-inlined memory_address_length, but simplified
10289 since we know that we're always dealing with reg+offset, and
10290 to avoid having to create and discard all that rtl. */
10294 {
10298 {
10299 /* EBP and R13 cannot be encoded without an offset. */
10301 }
10305 /* ESP and R12 must be encoded with a SIB byte. */
10307 len++;
10310 }
10312 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10313 The valid base registers are taken from CFUN->MACHINE->FS. */
10315 static rtx
10317 {
10323 {
10324 /* Choose the base register most likely to allow the most scheduling
10325 opportunities. Generally FP is valid throughout the function,
10326 while DRAP must be reloaded within the epilogue. But choose either
10327 over the SP due to increased encoding size. */
10330 {
10333 }
10335 {
10338 }
10340 {
10343 }
10344 }
10345 else
10346 {
10347 HOST_WIDE_INT toffset;
10350 /* Choose the base register with the smallest address encoding.
10351 With a tie, choose FP > DRAP > SP. */
10353 {
10357 }
10359 {
10363 {
10367 }
10368 }
10370 {
10374 {
10378 }
10379 }
10380 }
10384 }
10386 /* Emit code to save registers in the prologue. */
10388 static void
10390 {
10396 {
10399 }
10400 }
10402 /* Emit a single register save at CFA - CFA_OFFSET. */
10404 static void
10406 HOST_WIDE_INT cfa_offset)
10407 {
10415 /* For SSE saves, we need to indicate the 128-bit alignment. */
10426 /* When saving registers into a re-aligned local stack frame, avoid
10427 any tricky guessing by dwarf2out. */
10429 {
10433 {
10434 /* A bit of a hack. We force the DRAP register to be saved in
10435 the re-aligned stack frame, which provides us with a copy
10436 of the CFA that will last past the prologue. Install it. */
10442 }
10443 else
10444 {
10445 /* The frame pointer is a stable reference within the
10446 aligned frame. Use it. */
10453 }
10454 }
10456 /* The memory may not be relative to the current CFA register,
10457 which means that we may need to generate a new pattern for
10458 use by the unwind info. */
10460 {
10465 }
10466 }
10468 /* Emit code to save registers using MOV insns.
10469 First register is stored at CFA - CFA_OFFSET. */
10470 static void
10472 {
10477 {
10480 }
10481 }
10483 /* Emit code to save SSE registers using MOV insns.
10484 First register is stored at CFA - CFA_OFFSET. */
10485 static void
10487 {
10492 {
10495 }
10496 }
10500 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10501 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10502 Don't add the note if the previously saved value will be left untouched
10503 within stack red-zone till return, as unwinders can find the same value
10504 in the register and on the stack. */
10506 static void
10508 {
10514 {
10517 }
10518 else
10519 queued_cfa_restores
10521 }
10523 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10525 static void
10527 {
10528 rtx last;
10532 ;
10537 }
10539 /* Expand prologue or epilogue stack adjustment.
10540 The pattern exist to put a dependency on all ebp-based memory accesses.
10541 STYLE should be negative if instructions should be marked as frame related,
10542 zero if %r11 register is live and cannot be freely used and positive
10543 otherwise. */
10545 static void
10548 {
10550 rtx insn;
10557 else
10558 {
10559 rtx tmp;
10560 /* r11 is used by indirect sibcall return as well, set before the
10561 epilogue and used after the epilogue. */
10564 else
10565 {
10569 }
10575 }
10582 {
10583 rtx r;
10593 }
10595 {
10598 {
10602 }
10603 }
10606 {
10611 {
10614 }
10616 {
10619 }
10620 else
10621 {
10622 /* Else there are two possibilities: SP itself, which we set
10623 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10624 taken care of this by hand along the eh_return path. */
10627 }
10631 }
10632 }
10634 /* Find an available register to be used as dynamic realign argument
10635 pointer regsiter. Such a register will be written in prologue and
10636 used in begin of body, so it must not be
10637 1. parameter passing register.
10638 2. GOT pointer.
10639 We reuse static-chain register if it is available. Otherwise, we
10640 use DI for i386 and R13 for x86-64. We chose R13 since it has
10641 shorter encoding.
10643 Return: the regno of chosen register. */
10645 static unsigned int
10647 {
10651 {
10652 /* Use R13 for nested function or function need static chain.
10653 Since function with tail call may use any caller-saved
10654 registers in epilogue, DRAP must not use caller-saved
10655 register in such case. */
10660 }
10661 else
10662 {
10663 /* Use DI for nested function or function need static chain.
10664 Since function with tail call may use any caller-saved
10665 registers in epilogue, DRAP must not use caller-saved
10666 register in such case. */
10670 /* Reuse static chain register if it isn't used for parameter
10671 passing. */
10673 {
10677 }
10679 }
10680 }
10682 /* Return minimum incoming stack alignment. */
10684 static unsigned int
10686 {
10689 /* Prefer the one specified at command line. */
10692 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10693 if -mstackrealign is used, it isn't used for sibcall check and
10694 estimated stack alignment is 128bit. */
10696 && !TARGET_64BIT
10697 && ix86_force_align_arg_pointer
10700 else
10703 /* Incoming stack alignment can be changed on individual functions
10704 via force_align_arg_pointer attribute. We use the smallest
10705 incoming stack boundary. */
10711 /* The incoming stack frame has to be aligned at least at
10712 parm_stack_boundary. */
10716 /* Stack at entrance of main is aligned by runtime. We use the
10717 smallest incoming stack boundary. */
10725 }
10727 /* Update incoming stack boundary and estimated stack alignment. */
10729 static void
10731 {
10732 ix86_incoming_stack_boundary
10735 /* x86_64 vararg needs 16byte stack alignment for register save
10736 area. */
10741 }
10743 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10744 needed or an rtx for DRAP otherwise. */
10746 static rtx
10748 {
10753 {
10754 /* Assign DRAP to vDRAP and returns vDRAP */
10756 rtx drap_vreg;
10757 rtx arg_ptr;
10770 {
10773 }
10775 }
10776 else
10778 }
10780 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10782 static rtx
10784 {
10786 }
10789 rtx reg;
10791 };
10793 /* Return a short-lived scratch register for use on function entry.
10794 In 32-bit mode, it is valid only after the registers are saved
10795 in the prologue. This register must be released by means of
10796 release_scratch_register_on_entry once it is dead. */
10798 static void
10800 {
10806 {
10807 /* We always use R11 in 64-bit mode. */
10809 }
10810 else
10811 {
10813 bool fastcall_p
10815 bool thiscall_p
10819 int drap_regno
10822 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10823 for the static chain register. */
10827 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10828 for the static chain register. */
10833 /* ecx is the static chain register. */
10835 && !static_chain_p
10840 /* esi is the static chain register. */
10846 else
10847 {
10850 }
10851 }
10855 {
10858 }
10859 }
10861 /* Release a scratch register obtained from the preceding function. */
10863 static void
10865 {
10867 {
10871 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10877 }
10878 }
10880 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10882 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10884 static void
10886 {
10887 /* We skip the probe for the first interval + a small dope of 4 words and
10888 probe that many bytes past the specified size to maintain a protection
10889 area at the botton of the stack. */
10893 /* See if we have a constant small number of probes to generate. If so,
10894 that's the easy case. The run-time loop is made up of 11 insns in the
10895 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10896 for n # of intervals. */
10898 {
10902 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10903 values of N from 1 until it exceeds SIZE. If only one probe is
10904 needed, this will not generate any code. Then adjust and probe
10905 to PROBE_INTERVAL + SIZE. */
10907 {
10909 {
10912 }
10913 else
10920 }
10924 else
10932 /* Adjust back to account for the additional first interval. */
10936 }
10938 /* Otherwise, do the same as above, but in a loop. Note that we must be
10939 extra careful with variables wrapping around because we might be at
10940 the very top (or the very bottom) of the address space and we have
10941 to be able to handle this case properly; in particular, we use an
10942 equality test for the loop condition. */
10943 else
10944 {
10945 HOST_WIDE_INT rounded_size;
10951 /* Step 1: round SIZE to the previous multiple of the interval. */
10956 /* Step 2: compute initial and final value of the loop counter. */
10958 /* SP = SP_0 + PROBE_INTERVAL. */
10963 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10967 stack_pointer_rtx)));
10970 /* Step 3: the loop
10972 while (SP != LAST_ADDR)
10973 {
10974 SP = SP + PROBE_INTERVAL
10975 probe at SP
10976 }
10978 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10979 values of N from 1 until it is equal to ROUNDED_SIZE. */
10984 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10985 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10988 {
10993 }
10995 /* Adjust back to account for the additional first interval. */
11001 }
11005 /* Even if the stack pointer isn't the CFA register, we need to correctly
11006 describe the adjustments made to it, in particular differentiate the
11007 frame-related ones from the frame-unrelated ones. */
11009 {
11022 }
11024 /* Make sure nothing is scheduled before we are done. */
11026 }
11028 /* Adjust the stack pointer up to REG while probing it. */
11032 {
11042 /* Jump to END_LAB if SP == LAST_ADDR. */
11050 /* SP = SP + PROBE_INTERVAL. */
11054 /* Probe at SP. */
11065 }
11067 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11068 inclusive. These are offsets from the current stack pointer. */
11070 static void
11072 {
11073 /* See if we have a constant small number of probes to generate. If so,
11074 that's the easy case. The run-time loop is made up of 7 insns in the
11075 generic case while the compile-time loop is made up of n insns for n #
11076 of intervals. */
11078 {
11079 HOST_WIDE_INT i;
11081 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11082 it exceeds SIZE. If only one probe is needed, this will not
11083 generate any code. Then probe at FIRST + SIZE. */
11090 }
11092 /* Otherwise, do the same as above, but in a loop. Note that we must be
11093 extra careful with variables wrapping around because we might be at
11094 the very top (or the very bottom) of the address space and we have
11095 to be able to handle this case properly; in particular, we use an
11096 equality test for the loop condition. */
11097 else
11098 {
11105 /* Step 1: round SIZE to the previous multiple of the interval. */
11110 /* Step 2: compute initial and final value of the loop counter. */
11112 /* TEST_OFFSET = FIRST. */
11115 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
11119 /* Step 3: the loop
11121 while (TEST_ADDR != LAST_ADDR)
11122 {
11123 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11124 probe at TEST_ADDR
11125 }
11127 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11128 until it is equal to ROUNDED_SIZE. */
11133 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11134 that SIZE is equal to ROUNDED_SIZE. */
11139 stack_pointer_rtx,
11144 }
11146 /* Make sure nothing is scheduled before we are done. */
11148 }
11150 /* Probe a range of stack addresses from REG to END, inclusive. These are
11151 offsets from the current stack pointer. */
11155 {
11165 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11173 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11177 /* Probe at TEST_ADDR. */
11190 }
11192 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11193 to be generated in correct form. */
11194 static void
11196 {
11197 /* Check if stack realign is really needed after reload, and
11198 stores result in cfun */
11199 unsigned int incoming_stack_boundary
11208 {
11209 /* After stack_realign_needed is finalized, we can't no longer
11210 change it. */
11213 }
11215 /* If the only reason for frame_pointer_needed is that we conservatively
11216 assumed stack realignment might be needed, but in the end nothing that
11217 needed the stack alignment had been spilled, clear frame_pointer_needed
11218 and say we don't need stack realignment. */
11220 && frame_pointer_needed
11222 && flag_omit_frame_pointer
11224 && !ix86_current_function_calls_tls_descriptor
11233 {
11235 basic_block bb;
11242 HARD_FRAME_POINTER_REGNUM);
11244 {
11249 set_up_by_prologue))
11250 {
11254 }
11255 }
11257 /* If drap has been set, but it actually isn't live at the start
11258 of the function, there is no reason to set it up. */
11260 {
11263 {
11266 }
11267 }
11268 else
11283 }
11287 }
11289 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11291 static void
11293 {
11299 {
11302 {
11308 }
11309 }
11310 }
11312 /* Expand the prologue into a bunch of separate insns. */
11314 void
11316 {
11320 HOST_WIDE_INT allocate;
11326 /* DRAP should not coexist with stack_realign_fp */
11331 /* Initialize CFA state for before the prologue. */
11335 /* Track SP offset to the CFA. We continue tracking this after we've
11336 swapped the CFA register away from SP. In the case of re-alignment
11337 this is fudged; we're interested to offsets within the local frame. */
11344 {
11345 /* We should have already generated an error for any use of
11346 ms_hook on a nested function. */
11349 /* Check if profiling is active and we shall use profiling before
11350 prologue variant. If so sorry. */
11355 /* In ix86_asm_output_function_label we emitted:
11356 8b ff movl.s %edi,%edi
11357 55 push %ebp
11358 8b ec movl.s %esp,%ebp
11360 This matches the hookable function prologue in Win32 API
11361 functions in Microsoft Windows XP Service Pack 2 and newer.
11362 Wine uses this to enable Windows apps to hook the Win32 API
11363 functions provided by Wine.
11365 What that means is that we've already set up the frame pointer. */
11369 {
11372 /* We've decided to use the frame pointer already set up.
11373 Describe this to the unwinder by pretending that both
11374 push and mov insns happen right here.
11376 Putting the unwind info here at the end of the ms_hook
11377 is done so that we can make absolutely certain we get
11378 the required byte sequence at the start of the function,
11379 rather than relying on an assembler that can produce
11380 the exact encoding required.
11382 However it does mean (in the unpatched case) that we have
11383 a 1 insn window where the asynchronous unwind info is
11384 incorrect. However, if we placed the unwind info at
11385 its correct location we would have incorrect unwind info
11386 in the patched case. Which is probably all moot since
11387 I don't expect Wine generates dwarf2 unwind info for the
11388 system libraries that use this feature. */
11394 stack_pointer_rtx);
11402 /* Note that gen_push incremented m->fs.cfa_offset, even
11403 though we didn't emit the push insn here. */
11407 }
11408 else
11409 {
11410 /* The frame pointer is not needed so pop %ebp again.
11411 This leaves us with a pristine state. */
11413 }
11414 }
11416 /* The first insn of a function that accepts its static chain on the
11417 stack is to push the register that would be filled in by a direct
11418 call. This insn will be skipped by the trampoline. */
11420 {
11424 /* We don't want to interpret this push insn as a register save,
11425 only as a stack adjustment. The real copy of the register as
11426 a save will be done later, if needed. */
11431 }
11433 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11434 of DRAP is needed and stack realignment is really needed after reload */
11436 {
11439 /* Only need to push parameter pointer reg if it is caller saved. */
11441 {
11442 /* Push arg pointer reg */
11445 }
11447 /* Grab the argument pointer. */
11454 /* Align the stack. */
11456 stack_pointer_rtx,
11460 /* Replicate the return address on the stack so that return
11461 address can be reached via (argp - 1) slot. This is needed
11462 to implement macro RETURN_ADDR_RTX and intrinsic function
11463 expand_builtin_return_addr etc. */
11469 /* For the purposes of frame and register save area addressing,
11470 we've started over with a new frame. */
11473 }
11479 {
11480 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11481 slower on all targets. Also sdb doesn't like it. */
11485 /* Push registers now, before setting the frame pointer
11486 on SEH target. */
11488 && TARGET_SEH
11490 {
11494 }
11497 {
11505 }
11506 }
11509 {
11510 /* If saving registers via PUSH, do so now. */
11512 {
11516 }
11518 /* When using red zone we may start register saving before allocating
11519 the stack frame saving one cycle of the prologue. However, avoid
11520 doing this if we have to probe the stack; at least on x86_64 the
11521 stack probe can turn into a call that clobbers a red zone location. */
11523 && (! TARGET_STACK_PROBE
11525 {
11528 }
11529 }
11532 {
11536 /* The computation of the size of the re-aligned stack frame means
11537 that we must allocate the size of the register save area before
11538 performing the actual alignment. Otherwise we cannot guarantee
11539 that there's enough storage above the realignment point. */
11546 /* Align the stack. */
11548 stack_pointer_rtx,
11551 /* For the purposes of register save area addressing, the stack
11552 pointer is no longer valid. As for the value of sp_offset,
11553 see ix86_compute_frame_layout, which we need to match in order
11554 to pass verification of stack_pointer_offset at the end. */
11557 }
11562 {
11563 /* We start to count from ARG_POINTER. */
11566 /* If it was realigned, take into account the fake frame. */
11568 {
11575 /* This over-estimates by 1 minimal-stack-alignment-unit but
11576 mitigates that by counting in the new return address slot. */
11577 current_function_dynamic_stack_size
11579 }
11582 }
11584 /* On SEH target with very large frame size, allocate an area to save
11585 SSE registers (as the very large allocation won't be described). */
11589 {
11590 HOST_WIDE_INT sse_size =
11595 /* No need to do stack checking as the area will be immediately
11596 written. */
11603 }
11605 /* The stack has already been decremented by the instruction calling us
11606 so probe if the size is non-negative to preserve the protection area. */
11608 {
11609 /* We expect the registers to be saved when probes are used. */
11613 {
11616 {
11619 }
11620 }
11621 else
11622 {
11629 {
11631 {
11634 }
11635 else
11637 }
11638 else
11639 {
11641 {
11645 }
11646 else
11648 }
11649 }
11650 }
11653 ;
11656 {
11660 }
11661 else
11662 {
11674 {
11677 /* Note that SEH directives need to continue tracking the stack
11678 pointer even after the frame pointer has been set up. */
11680 {
11688 }
11689 }
11692 {
11697 {
11705 }
11706 }
11711 /* Use the fact that AX still contains ALLOCATE. */
11713 ? gen_pro_epilogue_adjust_stack_di_sub
11720 {
11728 }
11731 /* Use stack_pointer_rtx for relative addressing so that code
11732 works for realigned stack, too. */
11734 {
11741 }
11743 {
11748 }
11749 }
11752 /* If we havn't already set up the frame pointer, do so now. */
11754 {
11766 }
11773 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11774 in PROLOGUE. */
11776 {
11782 /* Deleting already emmitted SET_GOT if exist and allocated to
11783 REAL_PIC_OFFSET_TABLE_REGNUM. */
11785 }
11788 {
11789 /* vDRAP is setup but after reload it turns out stack realign
11790 isn't necessary, here we will emit prologue to setup DRAP
11791 without stack realign adjustment */
11794 }
11796 /* Prevent instructions from being scheduled into register save push
11797 sequence when access to the redzone area is done through frame pointer.
11798 The offset between the frame pointer and the stack pointer is calculated
11799 relative to the value of the stack pointer at the end of the function
11800 prologue, and moving instructions that access redzone area via frame
11801 pointer inside push sequence violates this assumption. */
11805 /* Emit cld instruction if stringops are used in the function. */
11809 /* SEH requires that the prologue end within 256 bytes of the start of
11810 the function. Prevent instruction schedules that would extend that.
11811 Further, prevent alloca modifications to the stack pointer from being
11812 combined with prologue modifications. */
11815 }
11817 /* Emit code to restore REG using a POP insn. */
11819 static void
11821 {
11830 {
11831 /* Previously we'd represented the CFA as an expression
11832 like *(%ebp - 8). We've just popped that value from
11833 the stack, which means we need to reset the CFA to
11834 the drap register. This will remain until we restore
11835 the stack pointer. */
11839 /* This means that the DRAP register is valid for addressing too. */
11842 }
11845 {
11852 }
11854 /* When the frame pointer is the CFA, and we pop it, we are
11855 swapping back to the stack pointer as the CFA. This happens
11856 for stack frames that don't allocate other data, so we assume
11857 the stack pointer is now pointing at the return address, i.e.
11858 the function entry state, which makes the offset be 1 word. */
11860 {
11863 {
11871 }
11872 }
11873 }
11875 /* Emit code to restore saved registers using POP insns. */
11877 static void
11879 {
11885 }
11887 /* Emit code and notes for the LEAVE instruction. */
11889 static void
11891 {
11903 {
11911 }
11914 }
11916 /* Emit code to restore saved registers using MOV insns.
11917 First register is restored from CFA - CFA_OFFSET. */
11918 static void
11921 {
11927 {
11929 rtx mem;
11937 {
11938 /* Previously we'd represented the CFA as an expression
11939 like *(%ebp - 8). We've just popped that value from
11940 the stack, which means we need to reset the CFA to
11941 the drap register. This will remain until we restore
11942 the stack pointer. */
11946 /* This means that the DRAP register is valid for addressing. */
11948 }
11949 else
11953 }
11954 }
11956 /* Emit code to restore saved registers using MOV insns.
11957 First register is restored from CFA - CFA_OFFSET. */
11958 static void
11961 {
11966 {
11968 rtx mem;
11978 }
11979 }
11981 /* Restore function stack, frame, and registers. */
11983 void
11985 {
12001 /* The FP must be valid if the frame pointer is present. */
12006 /* We must have *some* valid pointer to the stack frame. */
12009 /* The DRAP is never valid at this point. */
12012 /* See the comment about red zone and frame
12013 pointer usage in ix86_expand_prologue. */
12020 /* Determine the CFA offset of the end of the red-zone. */
12023 {
12024 /* The red-zone begins below the return address. */
12027 /* When the register save area is in the aligned portion of
12028 the stack, determine the maximum runtime displacement that
12029 matches up with the aligned frame. */
12033 }
12035 /* Special care must be taken for the normal return case of a function
12036 using eh_return: the eax and edx registers are marked as saved, but
12037 not restored along this path. Adjust the save location to match. */
12041 /* EH_RETURN requires the use of moves to function properly. */
12044 /* SEH requires the use of pops to identify the epilogue. */
12047 /* If we're only restoring one register and sp is not valid then
12048 using a move instruction to restore the register since it's
12049 less work than reloading sp and popping the register. */
12062 && TARGET_USE_LEAVE
12066 else
12070 {
12071 /* Ensure that the entire register save area is addressable via
12072 the stack pointer, if we will restore via sp. */
12077 {
12081 style,
12083 }
12084 }
12086 /* If there are any SSE registers to restore, then we have to do it
12087 via moves, since there's obviously no pop for SSE regs. */
12093 {
12094 rtx t;
12099 /* eh_return epilogues need %ecx added to the stack pointer. */
12101 {
12105 /* Stack align doesn't work with eh_return. */
12107 /* Neither does regparm nested functions. */
12111 {
12119 /* Note that we use SA as a temporary CFA, as the return
12120 address is at the proper place relative to it. We
12121 pretend this happens at the FP restore insn because
12122 prior to this insn the FP would be stored at the wrong
12123 offset relative to SA, and after this insn we have no
12124 other reasonable register to use for the CFA. We don't
12125 bother resetting the CFA to the SP for the duration of
12126 the return insn. */
12139 }
12140 else
12141 {
12149 {
12153 UNITS_PER_WORD));
12155 }
12156 }
12159 }
12160 }
12161 else
12162 {
12163 /* SEH requires that the function end with (1) a stack adjustment
12164 if necessary, (2) a sequence of pops, and (3) a return or
12165 jump instruction. Prevent insns from the function body from
12166 being scheduled into this sequence. */
12168 {
12169 /* Prevent a catch region from being adjacent to the standard
12170 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12171 several other flags that would be interesting to test are
12172 not yet set up. */
12175 else
12177 }
12179 /* First step is to deallocate the stack frame so that we can
12180 pop the registers. Also do it on SEH target for very large
12181 frame as the emitted instructions aren't allowed by the ABI in
12182 epilogues. */
12184 || (TARGET_SEH
12187 {
12192 }
12194 {
12198 style,
12200 }
12203 }
12205 /* If we used a stack pointer and haven't already got rid of it,
12206 then do so now. */
12208 {
12209 /* If the stack pointer is valid and pointing at the frame
12210 pointer store address, then we only need a pop. */
12213 /* Leave results in shorter dependency chains on CPUs that are
12214 able to grok it fast. */
12219 else
12220 {
12222 hard_frame_pointer_rtx,
12225 }
12226 }
12229 {
12257 }
12259 /* At this point the stack pointer must be valid, and we must have
12260 restored all of the registers. We may not have deallocated the
12261 entire stack frame. We've delayed this until now because it may
12262 be possible to merge the local stack deallocation with the
12263 deallocation forced by ix86_static_chain_on_stack. */
12268 {
12272 }
12273 else
12276 /* Sibcall epilogues don't want a return instruction. */
12278 {
12281 }
12284 {
12287 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12288 address, do explicit add, and jump indirectly to the caller. */
12291 {
12295 /* There is no "pascal" calling convention in any 64bit ABI. */
12312 }
12313 else
12315 }
12316 else
12319 /* Restore the state back to the state from the prologue,
12320 so that it's correct for the next epilogue. */
12322 }
12324 /* Reset from the function's potential modifications. */
12326 static void
12328 {
12332 #if TARGET_MACHO
12333 /* Mach-O doesn't support labels at the end of objects, so if
12334 it looks like we might want one, insert a NOP. */
12335 {
12341 {
12342 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12343 notes only, instead set their CODE_LABEL_NUMBER to -1,
12344 otherwise there would be code generation differences
12345 in between -g and -g0. */
12349 }
12359 }
12360 #endif
12362 }
12364 /* Return a scratch register to use in the split stack prologue. The
12365 split stack prologue is used for -fsplit-stack. It is the first
12366 instructions in the function, even before the regular prologue.
12367 The scratch register can be any caller-saved register which is not
12368 used for parameters or for the static chain. */
12370 static unsigned int
12372 {
12375 else
12376 {
12389 {
12391 {
12395 }
12397 }
12399 {
12403 }
12405 {
12408 else
12409 {
12411 {
12415 }
12417 }
12418 }
12419 else
12420 {
12421 /* FIXME: We could make this work by pushing a register
12422 around the addition and comparison. */
12425 }
12426 }
12427 }
12429 /* A SYMBOL_REF for the function which allocates new stackspace for
12430 -fsplit-stack. */
12434 /* A SYMBOL_REF for the more stack function when using the large
12435 model. */
12439 /* Handle -fsplit-stack. These are the first instructions in the
12440 function, even before the regular prologue. */
12442 void
12444 {
12446 HOST_WIDE_INT allocate;
12452 rtx fn;
12460 /* This is the label we will branch to if we have enough stack
12461 space. We expect the basic block reordering pass to reverse this
12462 branch if optimizing, so that we branch in the unlikely case. */
12465 /* We need to compare the stack pointer minus the frame size with
12466 the stack boundary in the TCB. The stack boundary always gives
12467 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12468 can compare directly. Otherwise we need to do an addition. */
12471 UNSPEC_STACK_CHECK);
12476 else
12477 {
12479 rtx offset;
12481 /* We need a scratch register to hold the stack pointer minus
12482 the required frame size. Since this is the very start of the
12483 function, the scratch register can be any caller-saved
12484 register which is not used for parameters. */
12491 {
12492 /* We don't use ix86_gen_add3 in this case because it will
12493 want to split to lea, but when not optimizing the insn
12494 will not be split after this point. */
12497 offset)));
12498 }
12499 else
12500 {
12503 stack_pointer_rtx));
12504 }
12506 }
12512 /* Mark the jump as very likely to be taken. */
12517 {
12520 }
12523 /* Get more stack space. We pass in the desired stack space and the
12524 size of the arguments to copy to the new stack. In 32-bit mode
12525 we push the parameters; __morestack will return on a new stack
12526 anyhow. In 64-bit mode we pass the parameters in r10 and
12527 r11. */
12532 {
12538 /* If this function uses a static chain, it will be in %r10.
12539 Preserve it across the call to __morestack. */
12541 {
12542 rtx rax;
12547 }
12551 {
12552 HOST_WIDE_INT argval;
12555 /* When using the large model we need to load the address
12556 into a register, and we've run out of registers. So we
12557 switch to a different calling convention, and we call a
12558 different function: __morestack_large. We pass the
12559 argument size in the upper 32 bits of r10 and pass the
12560 frame size in the lower 32 bits. */
12565 {
12566 split_stack_fn_large =
12569 }
12571 {
12573 rtx x;
12582 UNSPEC_GOT);
12588 }
12589 else
12596 }
12597 else
12598 {
12602 }
12605 }
12606 else
12607 {
12610 }
12616 /* In order to make call/return prediction work right, we now need
12617 to execute a return instruction. See
12618 libgcc/config/i386/morestack.S for the details on how this works.
12620 For flow purposes gcc must not see this as a return
12621 instruction--we need control flow to continue at the subsequent
12622 label. Therefore, we use an unspec. */
12626 /* If we are in 64-bit mode and this function uses a static chain,
12627 we saved %r10 in %rax before calling _morestack. */
12632 /* If this function calls va_start, we need to store a pointer to
12633 the arguments on the old stack, because they may not have been
12634 all copied to the new stack. At this point the old stack can be
12635 found at the frame pointer value used by __morestack, because
12636 __morestack has set that up before calling back to us. Here we
12637 store that pointer in a scratch register, and in
12638 ix86_expand_prologue we store the scratch register in a stack
12639 slot. */
12641 {
12643 rtx frame_reg;
12650 /* 64-bit:
12651 fp -> old fp value
12652 return address within this function
12653 return address of caller of this function
12654 stack arguments
12655 So we add three words to get to the stack arguments.
12657 32-bit:
12658 fp -> old fp value
12659 return address within this function
12660 first argument to __morestack
12661 second argument to __morestack
12662 return address of caller of this function
12663 stack arguments
12664 So we add five words to get to the stack arguments.
12665 */
12676 }
12681 /* If this function calls va_start, we now have to set the scratch
12682 register for the case where we do not call __morestack. In this
12683 case we need to set it based on the stack pointer. */
12685 {
12692 }
12693 }
12695 /* We may have to tell the dataflow pass that the split stack prologue
12696 is initializing a scratch register. */
12698 static void
12700 {
12702 {
12705 }
12706 }
12707 \f
12708 /* Extract the parts of an RTL expression that is a valid memory address
12709 for an instruction. Return 0 if the structure of the address is
12710 grossly off. Return -1 if the address contains ASHIFT, so it is not
12711 strictly valid, but still used for computing length of lea instruction. */
12713 int
12715 {
12720 rtx tmp;
12724 /* Allow zero-extended SImode addresses,
12725 they will be emitted with addr32 prefix. */
12727 {
12730 {
12734 }
12737 {
12744 }
12745 }
12747 /* Allow SImode subregs of DImode addresses,
12748 they will be emitted with addr32 prefix. */
12750 {
12753 {
12757 }
12758 }
12763 {
12766 else
12768 }
12770 {
12775 do
12776 {
12781 }
12788 {
12791 {
12816 /* FALLTHRU */
12820 && TARGET_TLS_DIRECT_SEG_REFS
12823 else
12830 /* FALLTHRU */
12837 else
12852 }
12853 }
12854 }
12856 {
12859 }
12861 {
12862 /* We're called for lea too, which implements ashift on occasion. */
12872 }
12873 else
12877 {
12879 ;
12882 ;
12883 else
12885 }
12887 /* Extract the integral value of scale. */
12889 {
12893 }
12898 /* Avoid useless 0 displacement. */
12902 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12907 {
12910 }
12912 /* Special case: %ebp cannot be encoded as a base without a displacement.
12913 Similarly %r13. */
12915 && base_reg
12924 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12925 Avoid this by transforming to [%esi+0].
12926 Reload calls address legitimization without cfun defined, so we need
12927 to test cfun for being non-NULL. */
12933 /* Special case: encode reg+reg instead of reg*2. */
12937 /* Special case: scaling cannot be encoded without base or displacement. */
12948 }
12949 \f
12950 /* Return cost of the memory address x.
12951 For i386, it is better to use a complex address than let gcc copy
12952 the address into a reg and make a new pseudo. But not if the address
12953 requires to two regs - that would mean more pseudos with longer
12954 lifetimes. */
12955 static int
12957 {
12969 /* Attempt to minimize number of registers in the address by increasing
12970 address cost for each used register. We don't increase address cost
12971 for "pic_offset_table_rtx". When a memopt with "pic_offset_table_rtx"
12972 is not invariant itself it most likely means that base or index is not
12973 invariant. Therefore only "pic_offset_table_rtx" could be hoisted out,
12974 which is not profitable for x86. */
12978 || !pic_offset_table_rtx
12981 cost++;
12986 || !pic_offset_table_rtx
12989 cost++;
12991 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12992 since it's predecode logic can't detect the length of instructions
12993 and it degenerates to vector decoded. Increase cost of such
12994 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12995 to split such addresses or even refuse such addresses at all.
12997 Following addressing modes are affected:
12998 [base+scale*index]
12999 [scale*index+disp]
13000 [base+index]
13002 The first and last case may be avoidable by explicitly coding the zero in
13003 memory address, but I don't have AMD-K6 machine handy to check this
13004 theory. */
13013 }
13014 \f
13015 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
13016 this is used for to form addresses to local data when -fPIC is in
13017 use. */
13019 static bool
13021 {
13024 }
13026 /* Determine if a given RTX is a valid constant. We already know this
13027 satisfies CONSTANT_P. */
13029 static bool
13031 {
13032 /* Pointer bounds constants are not valid. */
13037 {
13042 {
13046 }
13051 /* Only some unspecs are valid as "constants". */
13054 {
13070 }
13072 /* We must have drilled down to a symbol. */
13077 /* FALLTHRU */
13080 /* TLS symbols are never valid. */
13084 /* DLLIMPORT symbols are never valid. */
13089 #if TARGET_MACHO
13090 /* mdynamic-no-pic */
13093 #endif
13107 }
13109 /* Otherwise we handle everything else in the move patterns. */
13111 }
13113 /* Determine if it's legal to put X into the constant pool. This
13114 is not possible for the address of thread-local symbols, which
13115 is checked above. */
13117 static bool
13119 {
13120 /* We can always put integral constants and vectors in memory. */
13122 {
13131 }
13133 }
13135 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
13136 otherwise zero. */
13138 static bool
13140 {
13146 }
13149 /* Nonzero if the constant value X is a legitimate general operand
13150 when generating PIC code. It is given that flag_pic is on and
13151 that X satisfies CONSTANT_P. */
13153 bool
13155 {
13156 rtx inner;
13159 {
13166 /* Only some unspecs are valid as "constants". */
13169 {
13182 }
13183 /* FALLTHRU */
13191 }
13192 }
13194 /* Determine if a given CONST RTX is a valid memory displacement
13195 in PIC mode. */
13197 bool
13199 {
13202 /* In 64bit mode we can allow direct addresses of symbols and labels
13203 when they are not dynamic symbols. */
13205 {
13209 {
13233 /* FALLTHRU */
13236 /* TLS references should always be enclosed in UNSPEC.
13237 The dllimported symbol needs always to be resolved. */
13243 {
13251 /* Function-symbols need to be resolved only for
13252 large-model.
13253 For the small-model we don't need to resolve anything
13254 here. */
13259 /* Non-external symbols don't need to be resolved for
13260 large, and medium-model. */
13265 }
13268 || (HAVE_LD_PIE_COPYRELOC
13269 && flag_pie
13278 }
13279 }
13285 {
13286 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13287 of GOT tables. We should not need these anyway. */
13299 }
13303 {
13308 }
13317 {
13321 /* We need to check for both symbols and labels because VxWorks loads
13322 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13323 details. */
13327 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13328 While ABI specify also 32bit relocation but we don't produce it in
13329 small PIC model at all. */
13351 }
13354 }
13356 /* Determine if op is suitable RTX for an address register.
13357 Return naked register if a register or a register subreg is
13358 found, otherwise return NULL_RTX. */
13360 static rtx
13362 {
13365 /* Only SImode or DImode registers can form the address. */
13372 {
13380 /* Don't allow SUBREGs that span more than a word. It can
13381 lead to spill failures when the register is one word out
13382 of a two word structure. */
13386 /* Allow only SUBREGs of non-eliminable hard registers. */
13389 }
13391 /* Op is not a register. */
13393 }
13395 /* Recognizes RTL expressions that are valid memory addresses for an
13396 instruction. The MODE argument is the machine mode for the MEM
13397 expression that wants to use this address.
13399 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13400 convert common non-canonical forms to canonical form so that they will
13401 be recognized. */
13403 static bool
13405 {
13408 HOST_WIDE_INT scale;
13412 /* Decomposition failed. */
13421 /* Validate base register. */
13423 {
13431 /* Base is not valid. */
13433 }
13435 /* Validate index register. */
13437 {
13445 /* Index is not valid. */
13447 }
13449 /* Index and base should have the same mode. */
13454 /* Address override works only on the (%reg) part of %fs:(%reg). */
13460 /* Validate scale factor. */
13462 {
13464 /* Scale without index. */
13468 /* Scale is not a valid multiplier. */
13470 }
13472 /* Validate displacement. */
13474 {
13479 {
13480 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13481 used. While ABI specify also 32bit relocations, we don't produce
13482 them at all and use IP relative instead. */
13489 /* 64bit address unspec. */
13509 /* Invalid address unspec. */
13511 }
13514 && (flag_pic
13515 || (TARGET_MACHO
13516 #if TARGET_MACHO
13517 && MACHOPIC_INDIRECT
13519 #endif
13520 )))
13521 {
13523 is_legitimate_pic:
13525 {
13526 /* foo@dtpoff(%rX) is ok. */
13533 /* Non-constant pic memory reference. */
13535 }
13538 /* Displacement is an invalid pic construct. */
13540 #if TARGET_MACHO
13543 /* displacment must be referenced via non_lazy_pointer */
13545 #endif
13547 /* This code used to verify that a symbolic pic displacement
13548 includes the pic_offset_table_rtx register.
13550 While this is good idea, unfortunately these constructs may
13551 be created by "adds using lea" optimization for incorrect
13552 code like:
13554 int a;
13555 int foo(int i)
13556 {
13557 return *(&a+i);
13558 }
13560 This code is nonsensical, but results in addressing
13561 GOT table with pic_offset_table_rtx base. We can't
13562 just refuse it easily, since it gets matched by
13563 "addsi3" pattern, that later gets split to lea in the
13564 case output register differs from input. While this
13565 can be handled by separate addsi pattern for this case
13566 that never results in lea, this seems to be easier and
13567 correct fix for crash to disable this test. */
13568 }
13575 /* Displacement is not constant. */
13579 /* Displacement is out of range. */
13581 /* In x32 mode, constant addresses are sign extended to 64bit, so
13582 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13587 }
13589 /* Everything looks valid. */
13591 }
13593 /* Determine if a given RTX is a valid constant address. */
13595 bool
13597 {
13599 }
13600 \f
13601 /* Return a unique alias set for the GOT. */
13603 static alias_set_type
13605 {
13610 }
13612 /* Return a legitimate reference for ORIG (an address) using the
13613 register REG. If REG is 0, a new pseudo is generated.
13615 There are two types of references that must be handled:
13617 1. Global data references must load the address from the GOT, via
13618 the PIC reg. An insn is emitted to do this load, and the reg is
13619 returned.
13621 2. Static data references, constant pool addresses, and code labels
13622 compute the address as an offset from the GOT, whose base is in
13623 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13624 differentiate them from global data objects. The returned
13625 address is the PIC reg + an unspec constant.
13627 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13628 reg also appears in the address. */
13630 static rtx
13632 {
13636 #if TARGET_MACHO
13638 {
13641 /* Use the generic Mach-O PIC machinery. */
13643 }
13644 #endif
13647 {
13651 }
13657 {
13658 rtx tmpreg;
13659 /* This symbol may be referenced via a displacement from the PIC
13660 base address (@GOTOFF). */
13665 {
13667 UNSPEC_GOTOFF);
13669 }
13670 else
13675 else
13680 {
13684 }
13685 else
13687 }
13689 {
13690 /* This symbol may be referenced via a displacement from the PIC
13691 base address (@GOTOFF). */
13696 {
13698 UNSPEC_GOTOFF);
13700 }
13701 else
13707 {
13710 }
13711 }
13713 /* We can't use @GOTOFF for text labels on VxWorks;
13714 see gotoff_operand. */
13716 {
13721 /* For x64 PE-COFF there is no GOT table. So we use address
13722 directly. */
13724 {
13732 }
13734 {
13742 /* Use directly gen_movsi, otherwise the address is loaded
13743 into register for CSE. We don't want to CSE this addresses,
13744 instead we CSE addresses from the GOT table, so skip this. */
13747 }
13748 else
13749 {
13750 /* This symbol must be referenced via a load from the
13751 Global Offset Table (@GOT). */
13765 }
13766 }
13767 else
13768 {
13771 {
13773 {
13776 }
13777 else
13779 }
13781 {
13784 /* We must match stuff we generate before. Assume the only
13785 unspecs that can get here are ours. Not that we could do
13786 anything with them anyway.... */
13792 }
13794 {
13797 /* Check first to see if this is a constant offset from a @GOTOFF
13798 symbol reference. */
13801 {
13803 {
13805 UNSPEC_GOTOFF);
13811 {
13814 }
13815 }
13816 else
13817 {
13820 {
13824 }
13825 }
13826 }
13827 else
13828 {
13831 new_rtx
13835 {
13838 {
13841 new_rtx
13843 }
13844 else
13846 }
13847 else
13848 {
13849 /* For %rip addressing, we have to use just disp32, not
13850 base nor index. */
13857 {
13860 }
13862 }
13863 }
13864 }
13865 }
13867 }
13868 \f
13869 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13871 static rtx
13873 {
13877 {
13882 }
13888 }
13890 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13894 static rtx
13896 {
13898 {
13904 }
13907 {
13909 UNSPEC_PLTOFF);
13912 }
13915 }
13917 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13921 rtx
13923 {
13925 {
13926 ix86_tls_module_base_symbol
13931 }
13934 }
13936 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13937 false if we expect this to be used for a memory address and true if
13938 we expect to load the address into a register. */
13940 static rtx
13942 {
13948 /* Fall back to global dynamic model if tool chain cannot support local
13949 dynamic. */
13956 {
13961 {
13964 else
13965 {
13968 }
13969 }
13972 {
13975 else
13985 }
13986 else
13987 {
13991 {
13996 emit_call_insn
14006 }
14007 else
14009 }
14016 {
14019 else
14020 {
14023 }
14024 }
14027 {
14032 else
14038 }
14039 else
14040 {
14044 {
14047 rtx eqv;
14050 emit_call_insn
14055 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
14056 share the LD_BASE result with other LD model accesses. */
14058 UNSPEC_TLS_LD_BASE);
14062 }
14063 else
14065 }
14073 {
14080 }
14085 {
14087 {
14088 /* The Sun linker took the AMD64 TLS spec literally
14089 and can only handle %rax as destination of the
14090 initial executable code sequence. */
14095 }
14097 /* Generate DImode references to avoid %fs:(%reg32)
14098 problems and linker IE->LE relaxation bug. */
14102 }
14104 {
14107 }
14109 {
14113 }
14114 else
14115 {
14118 }
14128 {
14133 }
14134 else
14135 {
14139 }
14149 {
14153 }
14154 else
14155 {
14159 }
14164 }
14167 }
14169 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14170 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14171 unique refptr-DECL symbol corresponding to symbol DECL. */
14174 {
14178 {
14180 }
14182 static void
14184 {
14190 else
14192 }
14193 };
14197 static tree
14199 {
14205 tree to;
14206 rtx rtl;
14233 else
14246 {
14248 #ifdef SUB_TARGET_RECORD_STUB
14250 #endif
14251 }
14260 }
14262 /* Expand SYMBOL into its corresponding far-addresse symbol.
14263 WANT_REG is true if we require the result be a register. */
14265 static rtx
14267 {
14268 tree imp_decl;
14269 rtx x;
14278 }
14280 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14281 true if we require the result be a register. */
14283 static rtx
14285 {
14286 tree imp_decl;
14287 rtx x;
14296 }
14298 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14299 is true if we require the result be a register. */
14301 static rtx
14303 {
14308 {
14315 {
14318 }
14319 }
14335 {
14338 }
14340 }
14342 /* Try machine-dependent ways of modifying an illegitimate address
14343 to be legitimate. If we find one, return the new, valid address.
14344 This macro is used in only one place: `memory_address' in explow.c.
14346 OLDX is the address as it was before break_out_memory_refs was called.
14347 In some cases it is useful to look at this to decide what needs to be done.
14349 It is always safe for this macro to do nothing. It exists to recognize
14350 opportunities to optimize the output.
14352 For the 80386, we handle X+REG by loading X into a register R and
14353 using R+REG. R will go in a general reg and indexing will be used.
14354 However, if REG is a broken-out memory address or multiplication,
14355 nothing needs to be done because REG can certainly go in a general reg.
14357 When -fpic is used, special handling is needed for symbolic references.
14358 See comments by legitimize_pic_address in i386.c for details. */
14360 static rtx
14362 {
14373 {
14377 }
14380 {
14384 }
14389 #if TARGET_MACHO
14392 #endif
14394 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14398 {
14403 }
14406 {
14407 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14412 {
14418 }
14423 {
14429 }
14431 /* Put multiply first if it isn't already. */
14433 {
14436 }
14438 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14439 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14440 created by virtual register instantiation, register elimination, and
14441 similar optimizations. */
14443 {
14449 }
14451 /* Canonicalize
14452 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14453 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14458 {
14459 rtx constant;
14463 {
14466 }
14468 {
14471 }
14472 else
14476 {
14483 }
14484 }
14490 {
14493 }
14496 {
14499 }
14507 {
14510 }
14516 {
14520 {
14523 }
14527 }
14530 {
14534 {
14537 }
14541 }
14542 }
14545 }
14546 \f
14547 /* Print an integer constant expression in assembler syntax. Addition
14548 and subtraction are the only arithmetic that may appear in these
14549 expressions. FILE is the stdio stream to write to, X is the rtx, and
14550 CODE is the operand print code from the output string. */
14552 static void
14554 {
14558 {
14567 else
14568 {
14571 /* Mark the decl as referenced so that cgraph will
14572 output the function. */
14576 #if TARGET_MACHO
14580 #endif
14582 }
14590 /* FALLTHRU */
14601 /* This used to output parentheses around the expression,
14602 but that does not work on the 386 (either ATT or BSD assembler). */
14607 /* We can't handle floating point constants;
14608 TARGET_PRINT_OPERAND must handle them. */
14613 /* Some assemblers need integer constants to appear first. */
14615 {
14619 }
14620 else
14621 {
14626 }
14641 {
14645 }
14650 {
14669 /* FIXME: This might be @TPOFF in Sun ld too. */
14678 else
14688 else
14694 #if TARGET_MACHO
14699 #endif
14703 }
14708 }
14709 }
14711 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14712 We need to emit DTP-relative relocations. */
14714 static void ATTRIBUTE_UNUSED
14716 {
14721 {
14729 }
14730 }
14732 /* Return true if X is a representation of the PIC register. This copes
14733 with calls from ix86_find_base_term, where the register might have
14734 been replaced by a cselib value. */
14736 static bool
14738 {
14745 {
14753 }
14754 else
14756 }
14758 /* Helper function for ix86_delegitimize_address.
14759 Attempt to delegitimize TLS local-exec accesses. */
14761 static rtx
14763 {
14788 {
14793 }
14799 }
14801 /* In the name of slightly smaller debug output, and to cater to
14802 general assembler lossage, recognize PIC+GOTOFF and turn it back
14803 into a direct symbol reference.
14805 On Darwin, this is necessary to avoid a crash, because Darwin
14806 has a different PIC label for each routine but the DWARF debugging
14807 information is not associated with any particular routine, so it's
14808 necessary to remove references to the PIC label from RTL stored by
14809 the DWARF output code. */
14811 static rtx
14813 {
14815 /* addend is NULL or some rtx if x is something+GOTOFF where
14816 something doesn't include the PIC register. */
14818 /* reg_addend is NULL or a multiple of some register. */
14820 /* const_addend is NULL or a const_int. */
14822 /* This is the result, or NULL. */
14831 {
14838 {
14844 }
14851 {
14854 {
14859 }
14861 }
14866 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14867 and -mcmodel=medium -fpic. */
14868 }
14875 /* %ebx + GOT/GOTOFF */
14876 ;
14878 {
14879 /* %ebx + %reg * scale + GOT/GOTOFF */
14885 else
14886 {
14889 }
14890 }
14891 else
14897 {
14900 }
14921 {
14922 /* If the rest of original X doesn't involve the PIC register, add
14923 addend and subtract pic_offset_table_rtx. This can happen e.g.
14924 for code like:
14925 leal (%ebx, %ecx, 4), %ecx
14926 ...
14927 movl foo@GOTOFF(%ecx), %edx
14928 in which case we return (%ecx - %ebx) + foo
14929 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
14930 and reload has completed. */
14934 pic_offset_table_rtx),
14935 result);
14937 {
14941 }
14942 else
14944 }
14946 {
14950 }
14952 }
14954 /* If X is a machine specific address (i.e. a symbol or label being
14955 referenced as a displacement from the GOT implemented using an
14956 UNSPEC), then return the base term. Otherwise return X. */
14958 rtx
14960 {
14961 rtx term;
14964 {
14977 }
14980 }
14981 \f
14982 static void
14985 {
14989 {
14992 }
14997 {
15000 {
15019 }
15023 {
15042 }
15049 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
15050 Those same assemblers have the same but opposite lossage on cmov. */
15053 else
15058 {
15071 }
15078 else
15083 {
15096 }
15103 else
15113 else
15124 }
15126 }
15128 /* Print the name of register X to FILE based on its machine mode and number.
15129 If CODE is 'w', pretend the mode is HImode.
15130 If CODE is 'b', pretend the mode is QImode.
15131 If CODE is 'k', pretend the mode is SImode.
15132 If CODE is 'q', pretend the mode is DImode.
15133 If CODE is 'x', pretend the mode is V4SFmode.
15134 If CODE is 't', pretend the mode is V8SFmode.
15135 If CODE is 'g', pretend the mode is V16SFmode.
15136 If CODE is 'h', pretend the reg is the 'high' byte register.
15137 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15138 If CODE is 'd', duplicate the operand for AVX instruction.
15139 */
15141 void
15143 {
15153 {
15157 }
15160 {
15163 }
15181 else
15195 {
15203 normal:
15219 {
15224 }
15228 }
15232 /* Irritatingly, AMD extended registers use
15233 different naming convention: "r%d[bwd]" */
15235 {
15238 {
15252 /* no suffix */
15257 }
15259 }
15262 {
15265 else
15267 }
15268 }
15270 /* Meaning of CODE:
15271 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15272 C -- print opcode suffix for set/cmov insn.
15273 c -- like C, but print reversed condition
15274 F,f -- likewise, but for floating-point.
15275 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15276 otherwise nothing
15277 R -- print embeded rounding and sae.
15278 r -- print only sae.
15279 z -- print the opcode suffix for the size of the current operand.
15280 Z -- likewise, with special suffixes for x87 instructions.
15281 * -- print a star (in certain assembler syntax)
15282 A -- print an absolute memory reference.
15283 E -- print address with DImode register names if TARGET_64BIT.
15284 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15285 s -- print a shift double count, followed by the assemblers argument
15286 delimiter.
15287 b -- print the QImode name of the register for the indicated operand.
15288 %b0 would print %al if operands[0] is reg 0.
15289 w -- likewise, print the HImode name of the register.
15290 k -- likewise, print the SImode name of the register.
15291 q -- likewise, print the DImode name of the register.
15292 x -- likewise, print the V4SFmode name of the register.
15293 t -- likewise, print the V8SFmode name of the register.
15294 g -- likewise, print the V16SFmode name of the register.
15295 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15296 y -- print "st(0)" instead of "st" as a register.
15297 d -- print duplicated register operand for AVX instruction.
15298 D -- print condition for SSE cmp instruction.
15299 P -- if PIC, print an @PLT suffix.
15300 p -- print raw symbol name.
15301 X -- don't print any sort of PIC '@' suffix for a symbol.
15302 & -- print some in-use local-dynamic symbol name.
15303 H -- print a memory address offset by 8; used for sse high-parts
15304 Y -- print condition for XOP pcom* instruction.
15305 + -- print a branch hint as 'cs' or 'ds' prefix
15306 ; -- print a semicolon (after prefixes due to bug in older gas).
15307 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15308 @ -- print a segment register of thread base pointer load
15309 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15310 ! -- print MPX prefix for jxx/call/ret instructions if required.
15311 */
15313 void
15315 {
15317 {
15319 {
15322 {
15328 /* Intel syntax. For absolute addresses, registers should not
15329 be surrounded by braces. */
15331 {
15336 }
15341 }
15347 /* Wrap address in an UNSPEC to declare special handling. */
15385 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15390 {
15404 output_operand_lossage
15407 }
15410 #endif
15415 {
15416 /* Opcodes don't get size suffixes if using Intel opcodes. */
15421 {
15439 output_operand_lossage
15442 }
15443 }
15446 warning
15448 /* FALLTHRU */
15451 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15456 {
15458 {
15460 #ifdef HAVE_AS_IX86_FILDS
15462 #endif
15470 #ifdef HAVE_AS_IX86_FILDQ
15472 #else
15474 #endif
15479 }
15480 }
15482 {
15483 /* 387 opcodes don't get size suffixes
15484 if the operands are registers. */
15489 {
15505 }
15506 }
15507 else
15508 {
15509 output_operand_lossage
15512 }
15514 output_operand_lossage
15535 {
15538 }
15543 {
15594 }
15598 /* Little bit of braindamage here. The SSE compare instructions
15599 does use completely different names for the comparisons that the
15600 fp conditional moves. */
15602 {
15605 {
15608 }
15614 {
15617 }
15623 {
15626 }
15635 {
15638 }
15644 {
15647 }
15653 {
15656 }
15667 }
15672 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15675 #endif
15680 {
15684 }
15688 file);
15693 {
15697 }
15698 /* It doesn't actually matter what mode we use here, as we're
15699 only going to use this for printing. */
15701 /* Output 'qword ptr' for intel assembler dialect. */
15710 #ifdef HAVE_AS_IX86_HLE
15712 #else
15714 #endif
15716 #ifdef HAVE_AS_IX86_HLE
15718 #else
15720 #endif
15721 /* We do not want to print value of the operand. */
15750 {
15765 }
15778 {
15783 else
15786 }
15789 {
15790 rtx x;
15799 {
15804 {
15806 bool cputaken
15809 /* Emit hints only in the case default branch prediction
15810 heuristics would fail. */
15812 {
15813 /* We use 3e (DS) prefix for taken branches and
15814 2e (CS) prefix for not taken branches. */
15817 else
15819 }
15820 }
15821 }
15823 }
15826 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15828 #endif
15835 /* The kernel uses a different segment register for performance
15836 reasons; a system call would not have to trash the userspace
15837 segment register, which would be expensive. */
15840 else
15860 }
15861 }
15867 {
15868 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15871 {
15874 {
15883 else
15890 }
15892 /* Check for explicit size override (codes 'b', 'w', 'k',
15893 'q' and 'x') */
15907 }
15910 /* Avoid (%rip) for call operands. */
15916 else
15918 }
15921 {
15922 REAL_VALUE_TYPE r;
15930 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15934 else
15936 }
15939 {
15940 REAL_VALUE_TYPE r;
15949 }
15951 /* These float cases don't actually occur as immediate operands. */
15953 {
15958 }
15960 else
15961 {
15962 /* We have patterns that allow zero sets of memory, for instance.
15963 In 64-bit mode, we should probably support all 8-byte vectors,
15964 since we can in fact encode that into an immediate. */
15966 {
15969 }
15972 {
15974 {
15977 }
15980 {
15983 else
15985 }
15986 }
15991 else
15993 }
15994 }
15996 static bool
15998 {
16001 }
16002 \f
16003 /* Print a memory operand whose address is ADDR. */
16005 static void
16007 {
16016 {
16023 }
16025 {
16029 }
16031 {
16035 {
16038 }
16041 }
16043 {
16048 }
16049 else
16060 {
16071 }
16073 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16075 {
16087 }
16089 {
16090 /* Displacement only requires special attention. */
16093 {
16097 }
16100 else
16102 }
16103 else
16104 {
16105 /* Print SImode register names to force addr32 prefix. */
16107 {
16108 #ifdef ENABLE_CHECKING
16111 {
16122 }
16123 #endif
16126 }
16128 && TARGET_X32
16129 && disp
16132 {
16133 /* X32 runs in 64-bit mode, where displacement, DISP, in
16134 address DISP(%r64), is encoded as 32-bit immediate sign-
16135 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16136 address is %r64 + 0xffffffffbffffd00. When %r64 <
16137 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16138 which is invalid for x32. The correct address is %r64
16139 - 0x40000300 == 0xf7ffdd64. To properly encode
16140 -0x40000300(%r64) for x32, we zero-extend negative
16141 displacement by forcing addr32 prefix which truncates
16142 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16143 zero-extend all negative displacements, including -1(%rsp).
16144 However, for small negative displacements, sign-extension
16145 won't cause overflow. We only zero-extend negative
16146 displacements if they < -16*1024*1024, which is also used
16147 to check legitimate address displacements for PIC. */
16149 }
16152 {
16154 {
16159 else
16161 }
16167 {
16172 }
16174 }
16175 else
16176 {
16180 {
16181 /* Pull out the offset of a symbol; print any symbol itself. */
16185 {
16189 }
16197 else
16199 }
16203 {
16206 {
16210 }
16211 }
16214 else
16218 {
16223 }
16225 }
16226 }
16227 }
16229 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16231 static bool
16233 {
16234 rtx op;
16241 {
16244 /* FIXME: This might be @TPOFF in Sun ld. */
16255 else
16267 else
16274 #if TARGET_MACHO
16280 #endif
16283 {
16288 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16290 #else
16292 #endif
16295 }
16300 }
16303 }
16304 \f
16305 /* Split one or more double-mode RTL references into pairs of half-mode
16306 references. The RTL can be REG, offsettable MEM, integer constant, or
16307 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16308 split and "num" is its length. lo_half and hi_half are output arrays
16309 that parallel "operands". */
16311 void
16314 {
16315 machine_mode half_mode;
16319 {
16328 }
16333 {
16336 /* simplify_subreg refuse to split volatile memory addresses,
16337 but we still have to handle it. */
16339 {
16342 }
16343 else
16344 {
16351 }
16352 }
16353 }
16354 \f
16355 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16356 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16357 is the expression of the binary operation. The output may either be
16358 emitted here, or returned to the caller, like all output_* functions.
16360 There is no guarantee that the operands are the same mode, as they
16361 might be within FLOAT or FLOAT_EXTEND expressions. */
16363 #ifndef SYSV386_COMPAT
16364 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16365 wants to fix the assemblers because that causes incompatibility
16366 with gcc. No-one wants to fix gcc because that causes
16367 incompatibility with assemblers... You can use the option of
16368 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16369 #define SYSV386_COMPAT 1
16370 #endif
16374 {
16380 #ifdef ENABLE_CHECKING
16381 /* Even if we do not want to check the inputs, this documents input
16382 constraints. Which helps in understanding the following code. */
16392 else
16394 #endif
16397 {
16402 else
16411 else
16420 else
16429 else
16436 }
16439 {
16441 {
16445 else
16447 }
16448 else
16449 {
16453 else
16455 }
16457 }
16461 {
16467 /* know operands[0] == operands[1]. */
16470 {
16473 }
16476 {
16478 /* How is it that we are storing to a dead operand[2]?
16479 Well, presumably operands[1] is dead too. We can't
16480 store the result to st(0) as st(0) gets popped on this
16481 instruction. Instead store to operands[2] (which I
16482 think has to be st(1)). st(1) will be popped later.
16483 gcc <= 2.8.1 didn't have this check and generated
16484 assembly code that the Unixware assembler rejected. */
16486 else
16489 }
16493 else
16500 {
16503 }
16506 {
16509 }
16512 {
16513 #if SYSV386_COMPAT
16514 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16515 derived assemblers, confusingly reverse the direction of
16516 the operation for fsub{r} and fdiv{r} when the
16517 destination register is not st(0). The Intel assembler
16518 doesn't have this brain damage. Read !SYSV386_COMPAT to
16519 figure out what the hardware really does. */
16522 else
16524 #else
16526 /* As above for fmul/fadd, we can't store to st(0). */
16528 else
16530 #endif
16532 }
16535 {
16536 #if SYSV386_COMPAT
16539 else
16541 #else
16544 else
16546 #endif
16548 }
16551 {
16554 else
16557 }
16559 {
16560 #if SYSV386_COMPAT
16562 #else
16564 #endif
16565 }
16566 else
16567 {
16568 #if SYSV386_COMPAT
16570 #else
16572 #endif
16573 }
16578 }
16582 }
16584 /* Check if a 256bit AVX register is referenced inside of EXP. */
16586 static bool
16588 {
16594 }
16596 /* Return needed mode for entity in optimize_mode_switching pass. */
16598 static int
16600 {
16602 {
16603 rtx link;
16605 /* Needed mode is set to AVX_U128_CLEAN if there are
16606 no 256bit modes used in function arguments. */
16608 link;
16610 {
16612 {
16617 }
16618 }
16621 }
16623 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16624 changes state only when a 256bit register is written to, but we need
16625 to prevent the compiler from moving optimal insertion point above
16626 eventual read from 256bit register. */
16633 }
16635 /* Return mode that i387 must be switched into
16636 prior to the execution of insn. */
16638 static int
16640 {
16643 /* The mode UNINITIALIZED is used to store control word after a
16644 function call or ASM pattern. The mode ANY specify that function
16645 has no requirements on the control word and make no changes in the
16646 bits we are interested in. */
16660 {
16683 }
16686 }
16688 /* Return mode that entity must be switched into
16689 prior to the execution of insn. */
16691 static int
16693 {
16695 {
16705 }
16707 }
16709 /* Check if a 256bit AVX register is referenced in stores. */
16711 static void
16713 {
16715 {
16718 }
16719 }
16721 /* Calculate mode of upper 128bit AVX registers after the insn. */
16723 static int
16725 {
16732 /* We know that state is clean after CALL insn if there are no
16733 256bit registers used in the function return register. */
16735 {
16740 }
16742 /* Otherwise, return current mode. Remember that if insn
16743 references AVX 256bit registers, the mode was already changed
16744 to DIRTY from MODE_NEEDED. */
16746 }
16748 /* Return the mode that an insn results in. */
16750 static int
16752 {
16754 {
16764 }
16765 }
16767 static int
16769 {
16770 tree arg;
16772 /* Entry mode is set to AVX_U128_DIRTY if there are
16773 256bit modes used in function arguments. */
16776 {
16781 }
16784 }
16786 /* Return a mode that ENTITY is assumed to be
16787 switched to at function entry. */
16789 static int
16791 {
16793 {
16803 }
16804 }
16806 static int
16808 {
16811 /* Exit mode is set to AVX_U128_DIRTY if there are
16812 256bit modes used in the function return register. */
16817 }
16819 /* Return a mode that ENTITY is assumed to be
16820 switched to at function exit. */
16822 static int
16824 {
16826 {
16836 }
16837 }
16839 static int
16841 {
16843 }
16845 /* Output code to initialize control word copies used by trunc?f?i and
16846 rounding patterns. CURRENT_MODE is set to current control word,
16847 while NEW_MODE is set to new control word. */
16849 static void
16851 {
16853 rtx new_mode;
16864 {
16866 {
16868 /* round toward zero (truncate) */
16874 /* round down toward -oo */
16881 /* round up toward +oo */
16888 /* mask precision exception for nearbyint() */
16895 }
16896 }
16897 else
16898 {
16900 {
16902 /* round toward zero (truncate) */
16908 /* round down toward -oo */
16914 /* round up toward +oo */
16920 /* mask precision exception for nearbyint() */
16927 }
16928 }
16934 }
16936 /* Emit vzeroupper. */
16938 void
16940 {
16943 /* Cancel automatic vzeroupper insertion if there are
16944 live call-saved SSE registers at the insertion point. */
16956 }
16958 /* Generate one or more insns to set ENTITY to MODE. */
16960 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16961 is the set of hard registers live at the point where the insn(s)
16962 are to be inserted. */
16964 static void
16966 HARD_REG_SET regs_live)
16967 {
16969 {
16984 }
16985 }
16987 /* Output code for INSN to convert a float to a signed int. OPERANDS
16988 are the insn operands. The output may be [HSD]Imode and the input
16989 operand may be [SDX]Fmode. */
16993 {
16998 /* Jump through a hoop or two for DImode, since the hardware has no
16999 non-popping instruction. We used to do this a different way, but
17000 that was somewhat fragile and broke with post-reload splitters. */
17010 else
17011 {
17016 else
17020 }
17023 }
17025 /* Output code for x87 ffreep insn. The OPNO argument, which may only
17026 have the values zero or one, indicates the ffreep insn's operand
17027 from the OPERANDS array. */
17031 {
17033 #ifdef HAVE_AS_IX86_FFREEP
17035 #else
17036 {
17046 }
17047 #endif
17050 }
17053 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17054 should be used. UNORDERED_P is true when fucom should be used. */
17058 {
17064 {
17067 }
17068 else
17069 {
17072 }
17075 {
17079 else
17081 else
17084 else
17086 }
17093 {
17095 {
17098 }
17099 else
17101 }
17104 && stack_top_dies
17107 {
17108 /* If both the top of the 387 stack dies, and the other operand
17109 is also a stack register that dies, then this must be a
17110 `fcompp' float compare */
17113 {
17114 /* There is no double popping fcomi variant. Fortunately,
17115 eflags is immune from the fstp's cc clobbering. */
17118 else
17121 }
17122 else
17123 {
17126 else
17128 }
17129 }
17130 else
17131 {
17132 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17135 {
17143 NULL,
17144 NULL,
17151 NULL,
17152 NULL,
17153 NULL,
17154 NULL
17155 };
17170 }
17171 }
17173 void
17175 {
17178 #ifdef ASM_QUAD
17181 #else
17183 #endif
17186 }
17188 void
17190 {
17193 #ifdef ASM_QUAD
17196 #else
17198 #endif
17199 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17205 #if TARGET_MACHO
17207 {
17211 }
17212 #endif
17213 else
17216 }
17217 \f
17218 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17219 for the target. */
17221 void
17223 {
17224 rtx tmp;
17226 /* We play register width games, which are only valid after reload. */
17229 /* Avoid HImode and its attendant prefix byte. */
17235 {
17238 }
17241 }
17243 /* X is an unchanging MEM. If it is a constant pool reference, return
17244 the constant pool rtx, else NULL. */
17246 rtx
17248 {
17255 }
17257 void
17259 {
17267 {
17268 rtx tmp;
17272 {
17278 }
17281 }
17285 {
17288 rtx tmp;
17293 else
17297 {
17304 }
17305 }
17309 {
17311 {
17312 #if TARGET_MACHO
17313 /* dynamic-no-pic */
17315 {
17322 }
17324 {
17328 }
17331 else
17332 {
17340 }
17341 /* dynamic-no-pic */
17342 #endif
17343 }
17344 else
17345 {
17349 {
17355 }
17356 }
17357 }
17358 else
17359 {
17370 /* Force large constants in 64bit compilation into register
17371 to get them CSEed. */
17382 {
17383 /* If we are loading a floating point constant to a register,
17384 force the value to memory now, since we'll get better code
17385 out the back end. */
17389 {
17394 }
17395 }
17396 }
17399 }
17401 void
17403 {
17410 /* Force constants other than zero into memory. We do not know how
17411 the instructions used to build constants modify the upper 64 bits
17412 of the register, once we have that information we may be able
17413 to handle some of them more efficiently. */
17422 /* We need to check memory alignment for SSE mode since attribute
17423 can make operands unaligned. */
17428 {
17431 /* ix86_expand_vector_move_misalign() does not like constants ... */
17437 /* ... nor both arguments in memory. */
17445 }
17447 /* Make operand1 a register if it isn't already. */
17451 {
17454 }
17457 }
17459 /* Split 32-byte AVX unaligned load and store if needed. */
17461 static void
17463 {
17464 rtx m;
17468 machine_mode mode;
17471 {
17492 }
17495 {
17498 {
17505 }
17506 /* Normal *mov<mode>_internal pattern will handle
17507 unaligned loads just fine if misaligned_operand
17508 is true, and without the UNSPEC it can be combined
17509 with arithmetic instructions. */
17512 else
17514 }
17516 {
17519 {
17524 }
17525 else
17527 }
17528 else
17530 }
17532 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17533 straight to ix86_expand_vector_move. */
17534 /* Code generation for scalar reg-reg moves of single and double precision data:
17535 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17536 movaps reg, reg
17537 else
17538 movss reg, reg
17539 if (x86_sse_partial_reg_dependency == true)
17540 movapd reg, reg
17541 else
17542 movsd reg, reg
17544 Code generation for scalar loads of double precision data:
17545 if (x86_sse_split_regs == true)
17546 movlpd mem, reg (gas syntax)
17547 else
17548 movsd mem, reg
17550 Code generation for unaligned packed loads of single precision data
17551 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17552 if (x86_sse_unaligned_move_optimal)
17553 movups mem, reg
17555 if (x86_sse_partial_reg_dependency == true)
17556 {
17557 xorps reg, reg
17558 movlps mem, reg
17559 movhps mem+8, reg
17560 }
17561 else
17562 {
17563 movlps mem, reg
17564 movhps mem+8, reg
17565 }
17567 Code generation for unaligned packed loads of double precision data
17568 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17569 if (x86_sse_unaligned_move_optimal)
17570 movupd mem, reg
17572 if (x86_sse_split_regs == true)
17573 {
17574 movlpd mem, reg
17575 movhpd mem+8, reg
17576 }
17577 else
17578 {
17579 movsd mem, reg
17580 movhpd mem+8, reg
17581 }
17582 */
17584 void
17586 {
17595 {
17597 {
17601 {
17603 {
17606 }
17607 else
17609 }
17611 /* FALLTHRU */
17615 {
17630 }
17636 else
17644 }
17647 }
17651 {
17653 {
17657 {
17659 {
17662 }
17663 else
17665 }
17667 /* FALLTHRU */
17677 }
17680 }
17683 {
17684 /* Normal *mov<mode>_internal pattern will handle
17685 unaligned loads just fine if misaligned_operand
17686 is true, and without the UNSPEC it can be combined
17687 with arithmetic instructions. */
17693 /* ??? If we have typed data, then it would appear that using
17694 movdqu is the only way to get unaligned data loaded with
17695 integer type. */
17697 {
17699 {
17702 }
17704 /* We will eventually emit movups based on insn attributes. */
17708 }
17710 {
17711 rtx zero;
17714 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17715 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17717 {
17718 /* We will eventually emit movups based on insn attributes. */
17721 }
17723 /* When SSE registers are split into halves, we can avoid
17724 writing to the top half twice. */
17726 {
17729 }
17730 else
17731 {
17732 /* ??? Not sure about the best option for the Intel chips.
17733 The following would seem to satisfy; the register is
17734 entirely cleared, breaking the dependency chain. We
17735 then store to the upper half, with a dependency depth
17736 of one. A rumor has it that Intel recommends two movsd
17737 followed by an unpacklpd, but this is unconfirmed. And
17738 given that the dependency depth of the unpacklpd would
17739 still be one, I'm not sure why this would be better. */
17741 }
17747 }
17748 else
17749 {
17750 rtx t;
17753 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17754 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17756 {
17758 {
17761 }
17768 }
17772 else
17777 else
17786 }
17787 }
17789 {
17791 {
17794 /* We will eventually emit movups based on insn attributes. */
17796 }
17798 {
17800 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17801 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17803 /* We will eventually emit movups based on insn attributes. */
17805 else
17806 {
17811 }
17812 }
17813 else
17814 {
17819 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17820 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17822 {
17825 }
17826 else
17827 {
17832 }
17833 }
17834 }
17835 else
17837 }
17839 /* Helper function of ix86_fixup_binary_operands to canonicalize
17840 operand order. Returns true if the operands should be swapped. */
17842 static bool
17844 rtx operands[])
17845 {
17850 /* If the operation is not commutative, we can't do anything. */
17854 /* Highest priority is that src1 should match dst. */
17860 /* Next highest priority is that immediate constants come second. */
17866 /* Lowest priority is that memory references should come second. */
17873 }
17876 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17877 destination to use for the operation. If different from the true
17878 destination in operands[0], a copy operation will be required. */
17880 rtx
17882 rtx operands[])
17883 {
17888 /* Canonicalize operand order. */
17890 {
17891 /* It is invalid to swap operands of different modes. */
17895 }
17897 /* Both source operands cannot be in memory. */
17899 {
17900 /* Optimization: Only read from memory once. */
17902 {
17905 }
17908 else
17910 }
17912 /* If the destination is memory, and we do not have matching source
17913 operands, do things in registers. */
17917 /* Source 1 cannot be a constant. */
17921 /* Source 1 cannot be a non-matching memory. */
17925 /* Improve address combine. */
17934 }
17936 /* Similarly, but assume that the destination has already been
17937 set up properly. */
17939 void
17942 {
17945 }
17947 /* Attempt to expand a binary operator. Make the expansion closer to the
17948 actual machine, then just general_operand, which will allow 3 separate
17949 memory references (one output, two input) in a single insn. */
17951 void
17953 rtx operands[])
17954 {
17961 /* Emit the instruction. */
17968 {
17969 /* This is going to be an LEA; avoid splitting it later. */
17971 }
17972 else
17973 {
17976 }
17978 /* Fix up the destination if needed. */
17981 }
17983 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17984 the given OPERANDS. */
17986 void
17988 rtx operands[])
17989 {
17992 {
17995 }
17997 {
18000 }
18001 /* Optimize (__m128i) d | (__m128i) e and similar code
18002 when d and e are float vectors into float vector logical
18003 insn. In C/C++ without using intrinsics there is no other way
18004 to express vector logical operation on float vectors than
18005 to cast them temporarily to integer vectors. */
18007 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
18016 {
18017 rtx dst;
18019 {
18028 {
18031 }
18032 else
18033 {
18038 }
18049 }
18050 }
18059 }
18061 /* Return TRUE or FALSE depending on whether the binary operator meets the
18062 appropriate constraints. */
18064 bool
18067 {
18072 /* Both source operands cannot be in memory. */
18076 /* Canonicalize operand order for commutative operators. */
18080 /* If the destination is memory, we must have a matching source operand. */
18084 /* Source 1 cannot be a constant. */
18088 /* Source 1 cannot be a non-matching memory. */
18090 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18098 }
18100 /* Attempt to expand a unary operator. Make the expansion closer to the
18101 actual machine, then just general_operand, which will allow 2 separate
18102 memory references (one output, one input) in a single insn. */
18104 void
18106 rtx operands[])
18107 {
18114 /* If the destination is memory, and we do not have matching source
18115 operands, do things in registers. */
18117 {
18120 else
18122 }
18124 /* When source operand is memory, destination must match. */
18128 /* Emit the instruction. */
18134 else
18135 {
18138 }
18140 /* Fix up the destination if needed. */
18143 }
18145 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18146 divisor are within the range [0-255]. */
18148 void
18151 {
18160 {
18173 }
18180 /* Use 8bit unsigned divimod if dividend and divisor are within
18181 the range [0-255]. */
18190 pc_rtx);
18195 /* Generate original signed/unsigned divimod. */
18200 /* Branch to the end. */
18204 /* Generate 8bit unsigned divide. */
18206 /* Don't use operands[0] for result of 8bit divide since not all
18207 registers support QImode ZERO_EXTRACT. */
18214 {
18217 }
18218 else
18219 {
18222 }
18224 /* Extract remainder from AH. */
18228 else
18229 {
18230 /* Need a new scratch register since the old one has result
18231 of 8bit divide. */
18235 }
18238 /* Zero extend quotient from AL. */
18244 }
18246 #define LEA_MAX_STALL (3)
18247 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18249 /* Increase given DISTANCE in half-cycles according to
18250 dependencies between PREV and NEXT instructions.
18251 Add 1 half-cycle if there is no dependency and
18252 go to next cycle if there is some dependecy. */
18254 static unsigned int
18256 {
18272 }
18274 /* Function checks if instruction INSN defines register number
18275 REGNO1 or REGNO2. */
18277 static bool
18280 {
18281 df_ref def;
18291 }
18293 /* Function checks if instruction INSN uses register number
18294 REGNO as a part of address expression. */
18296 static bool
18298 {
18299 df_ref use;
18306 }
18308 /* Search backward for non-agu definition of register number REGNO1
18309 or register number REGNO2 in basic block starting from instruction
18310 START up to head of basic block or instruction INSN.
18312 Function puts true value into *FOUND var if definition was found
18313 and false otherwise.
18315 Distance in half-cycles between START and found instruction or head
18316 of BB is added to DISTANCE and returned. */
18318 static int
18322 {
18332 {
18334 {
18337 {
18340 {
18343 }
18344 }
18347 }
18352 }
18355 }
18357 /* Search backward for non-agu definition of register number REGNO1
18358 or register number REGNO2 in INSN's basic block until
18359 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18360 2. Reach neighbour BBs boundary, or
18361 3. Reach agu definition.
18362 Returns the distance between the non-agu definition point and INSN.
18363 If no definition point, returns -1. */
18365 static int
18368 {
18379 {
18380 edge e;
18381 edge_iterator ei;
18386 {
18389 }
18395 else
18396 {
18401 {
18402 int bb_dist
18408 {
18415 }
18416 }
18419 }
18420 }
18422 /* get_attr_type may modify recog data. We want to make sure
18423 that recog data is valid for instruction INSN, on which
18424 distance_non_agu_define is called. INSN is unchanged here. */
18431 }
18433 /* Return the distance in half-cycles between INSN and the next
18434 insn that uses register number REGNO in memory address added
18435 to DISTANCE. Return -1 if REGNO0 is set.
18437 Put true value into *FOUND if register usage was found and
18438 false otherwise.
18439 Put true value into *REDEFINED if register redefinition was
18440 found and false otherwise. */
18442 static int
18446 {
18455 {
18458 /* If insn and start belong to the same bb, set prev to insn,
18459 so the call to increase_distance will increase the distance
18460 between insns by 1. */
18462 }
18467 {
18469 {
18472 {
18473 /* Return DISTANCE if OP0 is used in memory
18474 address in NEXT. */
18477 }
18480 {
18481 /* Return -1 if OP0 is set in NEXT. */
18484 }
18487 }
18493 }
18496 }
18498 /* Return the distance between INSN and the next insn that uses
18499 register number REGNO0 in memory address. Return -1 if no such
18500 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18502 static int
18504 {
18516 {
18517 edge e;
18518 edge_iterator ei;
18523 {
18526 }
18532 else
18533 {
18539 {
18540 int bb_dist
18545 {
18552 }
18553 }
18556 }
18557 }
18563 }
18565 /* Define this macro to tune LEA priority vs ADD, it take effect when
18566 there is a dilemma of choicing LEA or ADD
18567 Negative value: ADD is more preferred than LEA
18568 Zero: Netrual
18569 Positive value: LEA is more preferred than ADD*/
18570 #define IX86_LEA_PRIORITY 0
18572 /* Return true if usage of lea INSN has performance advantage
18573 over a sequence of instructions. Instructions sequence has
18574 SPLIT_COST cycles higher latency than lea latency. */
18576 static bool
18579 {
18582 /* For Silvermont if using a 2-source or 3-source LEA for
18583 non-destructive destination purposes, or due to wanting
18584 ability to use SCALE, the use of LEA is justified. */
18586 {
18594 }
18600 {
18601 /* If there is no non AGU operand definition, no AGU
18602 operand usage and split cost is 0 then both lea
18603 and non lea variants have same priority. Currently
18604 we prefer lea for 64 bit code and non lea on 32 bit
18605 code. */
18608 else
18610 }
18612 /* With longer definitions distance lea is more preferable.
18613 Here we change it to take into account splitting cost and
18614 lea priority. */
18617 /* If there is no use in memory addess then we just check
18618 that split cost exceeds AGU stall. */
18622 /* If this insn has both backward non-agu dependence and forward
18623 agu dependence, the one with short distance takes effect. */
18625 }
18627 /* Return true if it is legal to clobber flags by INSN and
18628 false otherwise. */
18630 static bool
18632 {
18634 df_ref use;
18635 bitmap live;
18638 {
18640 {
18647 }
18653 }
18657 }
18659 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18660 move and add to avoid AGU stalls. */
18662 bool
18664 {
18667 /* Check if we need to optimize. */
18671 /* Check it is correct to split here. */
18679 /* We need to split only adds with non destructive
18680 destination operand. */
18683 else
18685 }
18687 /* Return true if we should emit lea instruction instead of mov
18688 instruction. */
18690 bool
18692 {
18695 /* Check if we need to optimize. */
18699 /* Use lea for reg to reg moves only. */
18707 }
18709 /* Return true if we need to split lea into a sequence of
18710 instructions to avoid AGU stalls. */
18712 bool
18714 {
18720 /* Check we need to optimize. */
18724 /* The "at least two components" test below might not catch simple
18725 move or zero extension insns if parts.base is non-NULL and parts.disp
18726 is const0_rtx as the only components in the address, e.g. if the
18727 register is %rbp or %r13. As this test is much cheaper and moves or
18728 zero extensions are the common case, do this check first. */
18734 /* Check if it is OK to split here. */
18741 /* There should be at least two components in the address. */
18746 /* We should not split into add if non legitimate pic
18747 operand is used as displacement. */
18762 /* Compute how many cycles we will add to execution time
18763 if split lea into a sequence of instructions. */
18765 {
18766 /* Have to use mov instruction if non desctructive
18767 destination form is used. */
18771 /* Have to add index to base if both exist. */
18775 /* Have to use shift and adds if scale is 2 or greater. */
18777 {
18782 else
18784 }
18786 /* Have to use add instruction with immediate if
18787 disp is non zero. */
18791 /* Subtract the price of lea. */
18793 }
18797 }
18799 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18800 matches destination. RTX includes clobber of FLAGS_REG. */
18802 static void
18805 {
18812 }
18814 /* Return true if regno1 def is nearest to the insn. */
18816 static bool
18818 {
18825 {
18827 {
18830 }
18836 }
18838 /* None of the regs is defined in the bb. */
18840 }
18842 /* Split lea instructions into a sequence of instructions
18843 which are executed on ALU to avoid AGU stalls.
18844 It is assumed that it is allowed to clobber flags register
18845 at lea position. */
18847 void
18849 {
18865 {
18868 }
18871 {
18874 }
18880 {
18881 /* Case r1 = r1 + ... */
18883 {
18884 /* If we have a case r1 = r1 + C * r2 then we
18885 should use multiplication which is very
18886 expensive. Assume cost model is wrong if we
18887 have such case here. */
18892 }
18893 else
18894 {
18895 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18899 /* Use shift for scaling. */
18908 }
18909 }
18911 {
18914 }
18915 else
18916 {
18918 {
18921 }
18923 {
18926 }
18927 else
18928 {
18933 else
18934 {
18935 rtx tmp1;
18937 /* Find better operand for SET instruction, depending
18938 on which definition is farther from the insn. */
18941 else
18951 }
18954 }
18958 }
18959 }
18961 /* Return true if it is ok to optimize an ADD operation to LEA
18962 operation to avoid flag register consumation. For most processors,
18963 ADD is faster than LEA. For the processors like BONNELL, if the
18964 destination register of LEA holds an actual address which will be
18965 used soon, LEA is better and otherwise ADD is better. */
18967 bool
18969 {
18974 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18982 }
18984 /* Return true if destination reg of SET_BODY is shift count of
18985 USE_BODY. */
18987 static bool
18989 {
18990 rtx set_dest;
18991 rtx shift_rtx;
18994 /* Retrieve destination of SET_BODY. */
18996 {
19005 use_body))
19010 }
19012 /* Retrieve shift count of USE_BODY. */
19014 {
19026 }
19034 {
19037 /* Return true if shift count is dest of SET_BODY. */
19039 {
19040 /* Add check since it can be invoked before register
19041 allocation in pre-reload schedule. */
19047 }
19048 }
19051 }
19053 /* Return true if destination reg of SET_INSN is shift count of
19054 USE_INSN. */
19056 bool
19058 {
19061 }
19063 /* Return TRUE or FALSE depending on whether the unary operator meets the
19064 appropriate constraints. */
19066 bool
19068 machine_mode,
19070 {
19071 /* If one of operands is memory, source and destination must match. */
19077 }
19079 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19080 are ok, keeping in mind the possible movddup alternative. */
19082 bool
19084 {
19090 }
19092 /* Post-reload splitter for converting an SF or DFmode value in an
19093 SSE register into an unsigned SImode. */
19095 void
19097 {
19098 machine_mode vecmode;
19108 /* Load up the value into the low element. We must ensure that the other
19109 elements are valid floats -- zero is the easiest such value. */
19111 {
19114 else
19116 }
19117 else
19118 {
19123 else
19125 }
19145 else
19150 }
19152 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19153 Expects the 64-bit DImode to be supplied in a pair of integral
19154 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19155 -mfpmath=sse, !optimize_size only. */
19157 void
19159 {
19163 rtx x;
19169 {
19172 }
19173 else
19174 {
19178 }
19186 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19189 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19190 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19191 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19192 (0x1.0p84 + double(fp_value_hi_xmm)).
19193 Note these exponents differ by 32. */
19197 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19198 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19207 /* Add the upper and lower DFmode values together. */
19210 else
19211 {
19215 }
19218 }
19220 /* Not used, but eases macroization of patterns. */
19221 void
19223 {
19225 }
19227 /* Convert an unsigned SImode value into a DFmode. Only currently used
19228 for SSE, but applicable anywhere. */
19230 void
19232 {
19233 REAL_VALUE_TYPE TWO31r;
19248 }
19250 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19251 32-bit mode; otherwise we have a direct convert instruction. */
19253 void
19255 {
19256 REAL_VALUE_TYPE TWO32r;
19274 }
19276 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19277 For x86_32, -mfpmath=sse, !optimize_size only. */
19278 void
19280 {
19281 REAL_VALUE_TYPE ONE16r;
19300 }
19302 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19303 a vector of unsigned ints VAL to vector of floats TARGET. */
19305 void
19307 {
19309 REAL_VALUE_TYPE TWO16r;
19316 else
19321 OPTAB_DIRECT);
19332 OPTAB_DIRECT);
19334 OPTAB_DIRECT);
19337 }
19339 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19340 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19341 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19342 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19344 rtx
19346 {
19347 REAL_VALUE_TYPE TWO31r;
19362 {
19368 }
19377 OPTAB_DIRECT);
19378 else
19379 {
19385 OPTAB_DIRECT);
19386 }
19389 }
19391 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19392 then replicate the value for all elements of the vector
19393 register. */
19395 rtx
19397 {
19399 rtvec v;
19400 machine_mode scalar_mode;
19403 {
19436 }
19437 }
19439 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19440 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19441 for an SSE register. If VECT is true, then replicate the mask for
19442 all elements of the vector register. If INVERT is true, then create
19443 a mask excluding the sign bit. */
19445 rtx
19447 {
19449 wide_int w;
19453 {
19484 }
19491 /* Force this value into the low part of a fp vector constant. */
19500 }
19502 /* Generate code for floating point ABS or NEG. */
19504 void
19506 rtx operands[])
19507 {
19518 {
19524 }
19526 /* NEG and ABS performed with SSE use bitwise mask operations.
19527 Create the appropriate mask now. */
19530 else
19540 {
19542 rtvec par;
19547 else
19548 {
19551 }
19553 }
19554 else
19556 }
19558 /* Expand a copysign operation. Special case operand 0 being a constant. */
19560 void
19562 {
19576 else
19580 {
19587 {
19590 else
19591 {
19595 }
19596 }
19606 else
19610 }
19611 else
19612 {
19622 else
19626 }
19627 }
19629 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19630 be a constant, and so has already been expanded into a vector constant. */
19632 void
19634 {
19650 {
19653 }
19654 }
19656 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19657 so we have to do two masks. */
19659 void
19661 {
19676 {
19677 /* Shouldn't happen often (it's useless, obviously), but when it does
19678 we'd generate incorrect code if we continue below. */
19681 }
19684 {
19695 }
19696 else
19697 {
19699 {
19701 }
19703 {
19707 }
19711 {
19714 }
19716 {
19721 }
19723 }
19727 }
19729 /* Return TRUE or FALSE depending on whether the first SET in INSN
19730 has source and destination with matching CC modes, and that the
19731 CC mode is at least as constrained as REQ_MODE. */
19733 bool
19735 {
19736 rtx set;
19737 machine_mode set_mode;
19747 {
19757 /* FALLTHRU */
19761 /* FALLTHRU */
19765 /* FALLTHRU */
19779 }
19782 }
19784 /* Generate insn patterns to do an integer compare of OPERANDS. */
19786 static rtx
19788 {
19789 machine_mode cmpmode;
19795 /* This is very simple, but making the interface the same as in the
19796 FP case makes the rest of the code easier. */
19800 /* Return the test that should be put into the flags user, i.e.
19801 the bcc, scc, or cmov instruction. */
19803 }
19805 /* Figure out whether to use ordered or unordered fp comparisons.
19806 Return the appropriate mode to use. */
19808 machine_mode
19810 {
19811 /* ??? In order to make all comparisons reversible, we do all comparisons
19812 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19813 all forms trapping and nontrapping comparisons, we can make inequality
19814 comparisons trapping again, since it results in better code when using
19815 FCOM based compares. */
19817 }
19819 machine_mode
19821 {
19825 {
19828 }
19831 {
19832 /* Only zero flag is needed. */
19836 /* Codes needing carry flag. */
19839 /* Detect overflow checks. They need just the carry flag. */
19843 else
19848 /* Codes possibly doable only with sign flag when
19849 comparing against zero. */
19854 else
19855 /* For other cases Carry flag is not required. */
19857 /* Codes doable only with sign flag when comparing
19858 against zero, but we miss jump instruction for it
19859 so we need to use relational tests against overflow
19860 that thus needs to be zero. */
19865 else
19867 /* strcmp pattern do (use flags) and combine may ask us for proper
19868 mode. */
19873 }
19874 }
19876 /* Return the fixed registers used for condition codes. */
19878 static bool
19880 {
19884 }
19886 /* If two condition code modes are compatible, return a condition code
19887 mode which is compatible with both. Otherwise, return
19888 VOIDmode. */
19890 static machine_mode
19892 {
19909 {
19923 {
19937 }
19941 /* These are only compatible with themselves, which we already
19942 checked above. */
19944 }
19945 }
19948 /* Return a comparison we can do and that it is equivalent to
19949 swap_condition (code) apart possibly from orderedness.
19950 But, never change orderedness if TARGET_IEEE_FP, returning
19951 UNKNOWN in that case if necessary. */
19953 static enum rtx_code
19955 {
19957 {
19968 }
19969 }
19971 /* Return cost of comparison CODE using the best strategy for performance.
19972 All following functions do use number of instructions as a cost metrics.
19973 In future this should be tweaked to compute bytes for optimize_size and
19974 take into account performance of various instructions on various CPUs. */
19976 static int
19978 {
19981 /* The cost of code using bit-twiddling on %ah. */
19983 {
20006 }
20009 {
20016 }
20017 }
20019 /* Return strategy to use for floating-point. We assume that fcomi is always
20020 preferrable where available, since that is also true when looking at size
20021 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20023 enum ix86_fpcmp_strategy
20025 {
20026 /* Do fcomi/sahf based test when profitable. */
20035 }
20037 /* Swap, force into registers, or otherwise massage the two operands
20038 to a fp comparison. The operands are updated in place; the new
20039 comparison code is returned. */
20041 static enum rtx_code
20043 {
20049 /* All of the unordered compare instructions only work on registers.
20050 The same is true of the fcomi compare instructions. The XFmode
20051 compare instructions require registers except when comparing
20052 against zero or when converting operand 1 from fixed point to
20053 floating point. */
20062 {
20065 }
20066 else
20067 {
20068 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20069 things around if they appear profitable, otherwise force op0
20070 into a register. */
20076 {
20079 {
20082 }
20083 }
20089 {
20094 {
20097 }
20098 else
20100 }
20101 }
20103 /* Try to rearrange the comparison to make it cheaper. */
20107 {
20112 }
20117 }
20119 /* Convert comparison codes we use to represent FP comparison to integer
20120 code that will result in proper branch. Return UNKNOWN if no such code
20121 is available. */
20123 enum rtx_code
20125 {
20127 {
20150 }
20151 }
20153 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20155 static rtx
20157 {
20164 /* Do fcomi/sahf based test when profitable. */
20166 {
20171 tmp);
20179 tmp);
20188 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20195 /* In the unordered case, we have to check C2 for NaN's, which
20196 doesn't happen to work out to anything nice combination-wise.
20197 So do some bit twiddling on the value we've got in AH to come
20198 up with an appropriate set of condition codes. */
20202 {
20206 {
20209 }
20210 else
20211 {
20217 }
20222 {
20227 }
20228 else
20229 {
20232 }
20237 {
20240 }
20241 else
20242 {
20246 }
20251 {
20257 }
20258 else
20259 {
20262 }
20267 {
20272 }
20273 else
20274 {
20277 }
20282 {
20287 }
20288 else
20289 {
20292 }
20306 }
20311 }
20313 /* Return the test that should be put into the flags user, i.e.
20314 the bcc, scc, or cmov instruction. */
20317 const0_rtx);
20318 }
20320 static rtx
20322 {
20323 rtx ret;
20329 {
20332 }
20333 else
20337 }
20339 void
20341 {
20343 rtx tmp;
20346 {
20353 simple:
20357 pc_rtx);
20365 /* Expand DImode branch into multiple compare+branch. */
20366 {
20370 machine_mode submode;
20373 {
20376 }
20383 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20384 avoid two branches. This costs one extra insn, so disable when
20385 optimizing for size. */
20390 {
20408 }
20410 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20411 op1 is a constant and the low word is zero, then we can just
20412 examine the high word. Similarly for low word -1 and
20413 less-or-equal-than or greater-than. */
20417 {
20420 {
20423 }
20427 {
20430 }
20434 }
20436 /* Otherwise, we need two or three jumps. */
20445 {
20459 }
20461 /*
20462 * a < b =>
20463 * if (hi(a) < hi(b)) goto true;
20464 * if (hi(a) > hi(b)) goto false;
20465 * if (lo(a) < lo(b)) goto true;
20466 * false:
20467 */
20479 }
20484 }
20485 }
20487 /* Split branch based on floating point condition. */
20488 void
20491 {
20492 rtx condition;
20493 rtx i;
20496 {
20499 }
20502 tmp);
20510 }
20512 void
20514 {
20515 rtx ret;
20522 }
20524 /* Expand comparison setting or clearing carry flag. Return true when
20525 successful and set pop for the operation. */
20526 static bool
20528 {
20529 machine_mode mode =
20532 /* Do not handle double-mode compares that go through special path. */
20537 {
20538 rtx compare_op;
20543 /* Shortcut: following common codes never translate
20544 into carry flag compares. */
20549 /* These comparisons require zero flag; swap operands so they won't. */
20552 {
20555 }
20557 /* Try to expand the comparison and verify that we end up with
20558 carry flag based comparison. This fails to be true only when
20559 we decide to expand comparison using arithmetic that is not
20560 too common scenario. */
20569 else
20578 }
20584 {
20589 /* Convert a==0 into (unsigned)a<1. */
20598 /* Convert a>b into b<a or a>=b-1. */
20602 {
20604 /* Bail out on overflow. We still can swap operands but that
20605 would force loading of the constant into register. */
20610 }
20611 else
20612 {
20615 }
20618 /* Convert a>=0 into (unsigned)a<0x80000000. */
20636 }
20637 /* Swapping operands may cause constant to appear as first operand. */
20639 {
20643 }
20647 }
20649 bool
20651 {
20654 rtx compare_op;
20676 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20677 HImode insns, we'd be swallowed in word prefix ops. */
20683 {
20687 HOST_WIDE_INT diff;
20690 /* Sign bit compares are better done using shifts than we do by using
20691 sbb. */
20694 {
20695 /* Detect overlap between destination and compare sources. */
20699 {
20700 rtx flags;
20709 {
20711 compare_code
20713 }
20715 /* To simplify rest of code, restrict to the GEU case. */
20717 {
20721 }
20722 else
20723 {
20726 reverse_condition_maybe_unordered
20728 else
20731 }
20740 else
20743 }
20744 else
20745 {
20748 else
20749 {
20752 }
20754 }
20757 {
20758 /*
20759 * cmpl op0,op1
20760 * sbbl dest,dest
20761 * [addl dest, ct]
20762 *
20763 * Size 5 - 8.
20764 */
20769 }
20771 {
20772 /*
20773 * cmpl op0,op1
20774 * sbbl dest,dest
20775 * orl $ct, dest
20776 *
20777 * Size 8.
20778 */
20782 }
20784 {
20785 /*
20786 * cmpl op0,op1
20787 * sbbl dest,dest
20788 * notl dest
20789 * [addl dest, cf]
20790 *
20791 * Size 8 - 11.
20792 */
20798 }
20799 else
20800 {
20801 /*
20802 * cmpl op0,op1
20803 * sbbl dest,dest
20804 * [notl dest]
20805 * andl cf - ct, dest
20806 * [addl dest, ct]
20807 *
20808 * Size 8 - 11.
20809 */
20812 {
20816 }
20826 }
20832 }
20835 {
20840 {
20843 /* We may be reversing unordered compare to normal compare, that
20844 is not valid in general (we may convert non-trapping condition
20845 to trapping one), however on i386 we currently emit all
20846 comparisons unordered. */
20848 }
20849 else
20852 {
20856 }
20857 }
20862 {
20867 {
20872 }
20873 }
20875 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20879 {
20880 /* If lea code below could be used, only optimize
20881 if it results in a 2 insn sequence. */
20887 {
20888 /*
20889 * notl op1 (if necessary)
20890 * sarl $31, op1
20891 * orl cf, op1
20892 */
20894 {
20898 }
20909 }
20910 }
20918 {
20919 /*
20920 * xorl dest,dest
20921 * cmpl op1,op2
20922 * setcc dest
20923 * lea cf(dest*(ct-cf)),dest
20924 *
20925 * Size 14.
20926 *
20927 * This also catches the degenerate setcc-only case.
20928 */
20930 rtx tmp;
20936 /* On x86_64 the lea instruction operates on Pmode, so we need
20937 to get arithmetics done in proper mode to match. */
20940 else
20941 {
20942 rtx out1;
20945 nops++;
20947 {
20949 nops++;
20950 }
20951 }
20953 {
20955 nops++;
20956 }
20958 {
20961 else
20963 }
20968 }
20970 /*
20971 * General case: Jumpful:
20972 * xorl dest,dest cmpl op1, op2
20973 * cmpl op1, op2 movl ct, dest
20974 * setcc dest jcc 1f
20975 * decl dest movl cf, dest
20976 * andl (cf-ct),dest 1:
20977 * addl ct,dest
20978 *
20979 * Size 20. Size 14.
20980 *
20981 * This is reasonably steep, but branch mispredict costs are
20982 * high on modern cpus, so consider failing only if optimizing
20983 * for space.
20984 */
20989 {
20991 {
20996 {
20999 /* We may be reversing unordered compare to normal compare,
21000 that is not valid in general (we may convert non-trapping
21001 condition to trapping one), however on i386 we currently
21002 emit all comparisons unordered. */
21004 }
21005 else
21006 {
21010 }
21013 {
21017 }
21018 }
21021 {
21022 /* notl op1 (if needed)
21023 sarl $31, op1
21024 andl (cf-ct), op1
21025 addl ct, op1
21027 For x < 0 (resp. x <= -1) there will be no notl,
21028 so if possible swap the constants to get rid of the
21029 complement.
21030 True/false will be -1/0 while code below (store flag
21031 followed by decrement) is 0/-1, so the constants need
21032 to be exchanged once more. */
21035 {
21038 }
21039 else
21043 }
21044 else
21045 {
21049 constm1_rtx,
21051 }
21063 }
21064 }
21067 {
21068 /* Try a few things more with specific constants and a variable. */
21070 optab op;
21076 /* If one of the two operands is an interesting constant, load a
21077 constant with the above and mask it in with a logical operation. */
21080 {
21086 else
21088 }
21090 {
21096 else
21098 }
21099 else
21106 /* Recurse to get the constant loaded. */
21110 /* Mask in the interesting variable. */
21112 OPTAB_WIDEN);
21117 }
21119 /*
21120 * For comparison with above,
21121 *
21122 * movl cf,dest
21123 * movl ct,tmp
21124 * cmpl op1,op2
21125 * cmovcc tmp,dest
21126 *
21127 * Size 15.
21128 */
21150 }
21152 /* Swap, force into registers, or otherwise massage the two operands
21153 to an sse comparison with a mask result. Thus we differ a bit from
21154 ix86_prepare_fp_compare_args which expects to produce a flags result.
21156 The DEST operand exists to help determine whether to commute commutative
21157 operators. The POP0/POP1 operands are updated in place. The new
21158 comparison code is returned, or UNKNOWN if not implementable. */
21160 static enum rtx_code
21163 {
21165 {
21168 /* AVX supports all the needed comparisons. */
21171 /* We have no LTGT as an operator. We could implement it with
21172 NE & ORDERED, but this requires an extra temporary. It's
21173 not clear that it's worth it. */
21180 /* These are supported directly. */
21187 /* AVX has 3 operand comparisons, no need to swap anything. */
21190 /* For commutative operators, try to canonicalize the destination
21191 operand to be first in the comparison - this helps reload to
21192 avoid extra moves. */
21195 /* FALLTHRU */
21201 /* These are not supported directly before AVX, and furthermore
21202 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21203 comparison operands to transform into something that is
21204 supported. */
21211 }
21214 }
21216 /* Detect conditional moves that exactly match min/max operational
21217 semantics. Note that this is IEEE safe, as long as we don't
21218 interchange the operands.
21220 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21221 and TRUE if the operation is successful and instructions are emitted. */
21223 static bool
21226 {
21227 machine_mode mode;
21229 rtx tmp;
21232 ;
21235 else
21242 else
21247 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21248 but MODE may be a vector mode and thus not appropriate. */
21250 {
21252 rtvec v;
21257 }
21258 else
21259 {
21262 }
21266 }
21268 /* Expand an sse vector comparison. Return the register with the result. */
21270 static rtx
21273 {
21277 /* In general case result of comparison can differ from operands' type. */
21278 machine_mode cmp_mode;
21280 /* In AVX512F the result of comparison is an integer mask. */
21282 rtx x;
21285 {
21290 }
21291 else
21304 /* Compare patterns for int modes are unspec in AVX512F only. */
21306 {
21310 {
21327 }
21330 {
21333 }
21334 }
21338 {
21341 }
21342 else
21346 }
21348 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21349 operations. This is used for both scalar and vector conditional moves. */
21351 static void
21353 {
21357 /* In AVX512F the result of comparison is an integer mask. */
21365 {
21367 }
21370 {
21374 }
21377 {
21382 }
21385 {
21389 }
21392 {
21400 op_true,
21401 op_false)));
21402 }
21403 else
21404 {
21414 {
21428 {
21435 }
21450 {
21457 }
21481 }
21484 {
21488 }
21489 else
21490 {
21496 else
21508 }
21509 }
21510 }
21512 /* Expand a floating-point conditional move. Return true if successful. */
21514 bool
21516 {
21524 {
21525 machine_mode cmode;
21527 /* Since we've no cmove for sse registers, don't force bad register
21528 allocation just to gain access to it. Deny movcc when the
21529 comparison mode doesn't match the move mode. */
21548 }
21555 /* The floating point conditional move instructions don't directly
21556 support conditions resulting from a signed integer comparison. */
21560 {
21565 }
21572 }
21574 /* Expand a floating-point vector conditional move; a vcond operation
21575 rather than a movcc operation. */
21577 bool
21579 {
21581 rtx cmp;
21586 {
21587 rtx temp;
21589 {
21606 }
21608 OPTAB_DIRECT);
21611 }
21621 }
21623 /* Expand a signed/unsigned integral vector conditional move. */
21625 bool
21627 {
21637 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21638 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21647 {
21651 {
21657 }
21660 {
21666 }
21667 }
21676 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21680 ;
21681 else
21682 {
21683 /* Canonicalize the comparison to EQ, GT, GTU. */
21685 {
21702 /* FALLTHRU */
21712 }
21714 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21716 {
21718 {
21720 /* SSE4.1 supports EQ. */
21727 /* SSE4.2 supports GT/GTU. */
21734 }
21735 }
21737 /* Unsigned parallel compare is not supported by the hardware.
21738 Play some tricks to turn this into a signed comparison
21739 against 0. */
21741 {
21745 {
21752 {
21757 {
21766 }
21767 /* Subtract (-(INT MAX) - 1) from both operands to make
21768 them signed. */
21779 }
21788 /* Perform a parallel unsigned saturating subtraction. */
21801 }
21802 }
21803 }
21805 /* Allow the comparison to be done in one mode, but the movcc to
21806 happen in another mode. */
21808 {
21811 }
21812 else
21813 {
21819 }
21824 }
21826 /* AVX512F does support 64-byte integer vector operations,
21827 thus the longest vector we are faced with is V64QImode. */
21828 #define MAX_VECT_LEN 64
21830 struct expand_vec_perm_d
21831 {
21834 machine_mode vmode;
21838 };
21840 static bool
21843 {
21844 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21845 expander, so args are either in d, or in op0, op1 etc. */
21851 {
21882 {
21885 }
21889 {
21892 }
21896 {
21899 }
21915 {
21918 }
21922 {
21925 }
21929 {
21932 }
21936 }
21941 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21942 expander, so args are either in d, or in op0, op1 etc. */
21944 {
21952 }
21956 }
21958 /* Expand a variable vector permutation. */
21960 void
21962 {
21973 /* Number of elements in the vector. */
21982 {
21984 {
21985 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21986 an constant shuffle operand. With a tiny bit of effort we can
21987 use VPERMD instead. A re-interpretation stall for V4DFmode is
21988 unfortunate but there's no avoiding it.
21989 Similarly for V16HImode we don't have instructions for variable
21990 shuffling, while for V32QImode we can use after preparing suitable
21991 masks vpshufb; vpshufb; vpermq; vpor. */
21994 {
21998 }
21999 else
22000 {
22004 }
22007 /* Replicate the low bits of the V4DImode mask into V8SImode:
22008 mask = { A B C D }
22009 t1 = { A A B B C C D D }. */
22017 else
22020 /* Multiply the shuffle indicies by two. */
22022 OPTAB_DIRECT);
22024 /* Add one to the odd shuffle indicies:
22025 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22027 {
22030 }
22034 OPTAB_DIRECT);
22036 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22041 }
22044 {
22046 /* The VPERMD and VPERMPS instructions already properly ignore
22047 the high bits of the shuffle elements. No need for us to
22048 perform an AND ourselves. */
22050 {
22055 }
22056 else
22057 {
22063 }
22070 else
22071 {
22077 }
22081 /* By combining the two 128-bit input vectors into one 256-bit
22082 input vector, we can use VPERMD and VPERMPS for the full
22083 two-operand shuffle. */
22115 /* From mask create two adjusted masks, which contain the same
22116 bits as mask in the low 7 bits of each vector element.
22117 The first mask will have the most significant bit clear
22118 if it requests element from the same 128-bit lane
22119 and MSB set if it requests element from the other 128-bit lane.
22120 The second mask will have the opposite values of the MSB,
22121 and additionally will have its 128-bit lanes swapped.
22122 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22123 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22124 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22125 stands for other 12 bytes. */
22126 /* The bit whether element is from the same lane or the other
22127 lane is bit 4, so shift it up by 3 to the MSB position. */
22131 /* Clear MSB bits from the mask just in case it had them set. */
22133 /* After this t1 will have MSB set for elements from other lane. */
22135 /* Clear bits other than MSB. */
22137 /* Or in the lower bits from mask into t3. */
22139 /* And invert MSB bits in t1, so MSB is set for elements from the same
22140 lane. */
22142 /* Swap 128-bit lanes in t3. */
22147 /* And or in the lower bits from mask into t1. */
22150 {
22151 /* Each of these shuffles will put 0s in places where
22152 element from the other 128-bit lane is needed, otherwise
22153 will shuffle in the requested value. */
22157 /* For t3 the 128-bit lanes are swapped again. */
22162 /* And oring both together leads to the result. */
22169 }
22172 /* Similarly to the above one_operand_shuffle code,
22173 just for repeated twice for each operand. merge_two:
22174 code will merge the two results together. */
22198 }
22199 }
22202 {
22203 /* The XOP VPPERM insn supports three inputs. By ignoring the
22204 one_operand_shuffle special case, we avoid creating another
22205 set of constant vectors in memory. */
22208 /* mask = mask & {2*w-1, ...} */
22210 }
22211 else
22212 {
22213 /* mask = mask & {w-1, ...} */
22215 }
22223 /* For non-QImode operations, convert the word permutation control
22224 into a byte permutation control. */
22226 {
22231 /* Convert mask to vector of chars. */
22234 /* Replicate each of the input bytes into byte positions:
22235 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22236 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22237 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22244 else
22247 /* Convert it into the byte positions by doing
22248 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22254 }
22256 /* The actual shuffle operations all operate on V16QImode. */
22261 {
22268 }
22270 {
22277 }
22278 else
22279 {
22283 /* Shuffle the two input vectors independently. */
22289 merge_two:
22290 /* Then merge them together. The key is whether any given control
22291 element contained a bit set that indicates the second word. */
22295 {
22296 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22297 more shuffle to convert the V2DI input mask into a V4SI
22298 input mask. At which point the masking that expand_int_vcond
22299 will work as desired. */
22307 }
22329 }
22330 }
22332 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22333 true if we should do zero extension, else sign extension. HIGH_P is
22334 true if we want the N/2 high elements, else the low elements. */
22336 void
22338 {
22340 rtx tmp;
22343 {
22349 {
22353 else
22356 extract
22362 else
22365 extract
22371 else
22374 extract
22380 else
22383 extract
22389 else
22392 extract
22398 else
22401 extract
22407 else
22413 else
22419 else
22424 }
22427 {
22430 }
22432 {
22433 /* Shift higher 8 bytes to lower 8 bytes. */
22438 }
22439 else
22443 }
22444 else
22445 {
22449 {
22453 else
22459 else
22465 else
22470 }
22474 else
22481 }
22482 }
22484 /* Expand conditional increment or decrement using adb/sbb instructions.
22485 The default case using setcc followed by the conditional move can be
22486 done by generic code. */
22487 bool
22489 {
22491 rtx flags;
22493 rtx compare_op;
22496 machine_mode mode;
22511 {
22514 }
22517 {
22521 reverse_condition_maybe_unordered
22523 else
22525 }
22529 /* Construct either adc or sbb insn. */
22531 {
22533 {
22548 }
22549 }
22550 else
22551 {
22553 {
22568 }
22569 }
22573 }
22576 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22577 but works for floating pointer parameters and nonoffsetable memories.
22578 For pushes, it returns just stack offsets; the values will be saved
22579 in the right order. Maximally three parts are generated. */
22581 static int
22583 {
22588 else
22594 /* Optimize constant pool reference to immediates. This is used by fp
22595 moves, that force all constants to memory to allow combining. */
22597 {
22601 }
22604 {
22605 /* The only non-offsetable memories we handle are pushes. */
22614 }
22617 {
22619 /* Caution: if we looked through a constant pool memory above,
22620 the operand may actually have a different mode now. That's
22621 ok, since we want to pun this all the way back to an integer. */
22625 }
22628 {
22631 else
22632 {
22636 {
22640 }
22642 {
22647 }
22649 {
22650 REAL_VALUE_TYPE r;
22655 {
22662 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22663 long double may not be 80-bit. */
22672 }
22675 }
22676 else
22678 }
22679 }
22680 else
22681 {
22685 {
22688 {
22692 }
22694 {
22698 }
22700 {
22701 REAL_VALUE_TYPE r;
22707 /* real_to_target puts 32-bit pieces in each long. */
22709 gen_int_mode
22712 DImode);
22716 else
22718 gen_int_mode
22721 DImode);
22722 }
22723 else
22725 }
22726 }
22729 }
22731 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22732 Return false when normal moves are needed; true when all required
22733 insns have been emitted. Operands 2-4 contain the input values
22734 int the correct order; operands 5-7 contain the output values. */
22736 void
22738 {
22746 /* The DFmode expanders may ask us to move double.
22747 For 64bit target this is single move. By hiding the fact
22748 here we simplify i386.md splitters. */
22750 {
22751 /* Optimize constant pool reference to immediates. This is used by
22752 fp moves, that force all constants to memory to allow combining. */
22759 {
22762 }
22763 else
22768 }
22770 /* The only non-offsettable memory we handle is push. */
22773 else
22780 /* When emitting push, take care for source operands on the stack. */
22783 {
22786 /* Compensate for the stack decrement by 4. */
22791 /* src_base refers to the stack pointer and is
22792 automatically decreased by emitted push. */
22796 }
22798 /* We need to do copy in the right order in case an address register
22799 of the source overlaps the destination. */
22801 {
22802 rtx tmp;
22805 {
22809 collisions++;
22810 }
22812 /* Collision in the middle part can be handled by reordering. */
22814 {
22817 }
22821 {
22823 {
22826 }
22827 else
22828 {
22831 }
22832 }
22834 /* If there are more collisions, we can't handle it by reordering.
22835 Do an lea to the last part and use only one colliding move. */
22837 {
22838 rtx base;
22844 /* Handle the case when the last part isn't valid for lea.
22845 Happens in 64-bit mode storing the 12-byte XFmode. */
22852 {
22855 }
22856 }
22857 }
22860 {
22862 {
22864 {
22869 }
22871 {
22874 }
22875 }
22876 else
22877 {
22878 /* In 64bit mode we don't have 32bit push available. In case this is
22879 register, it is OK - we will just use larger counterpart. We also
22880 retype memory - these comes from attempt to avoid REX prefix on
22881 moving of second half of TFmode value. */
22883 {
22885 {
22896 }
22900 }
22901 }
22905 }
22907 /* Choose correct order to not overwrite the source before it is copied. */
22917 {
22919 {
22922 }
22923 }
22924 else
22925 {
22927 {
22930 }
22931 }
22933 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22935 {
22944 }
22950 }
22952 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22953 left shift by a constant, either using a single shift or
22954 a sequence of add instructions. */
22956 static void
22958 {
22964 {
22968 }
22969 else
22970 {
22973 }
22974 }
22976 void
22978 {
22987 {
22992 {
22998 }
22999 else
23000 {
23008 }
23010 }
23017 {
23018 /* Assuming we've chosen a QImode capable registers, then 1 << N
23019 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23021 {
23037 }
23039 /* Otherwise, we can get the same results by manually performing
23040 a bit extract operation on bit 5/6, and then performing the two
23041 shifts. The two methods of getting 0/1 into low/high are exactly
23042 the same size. Avoiding the shift in the bit extract case helps
23043 pentium4 a bit; no one else seems to care much either way. */
23044 else
23045 {
23046 machine_mode half_mode;
23050 HOST_WIDE_INT bits;
23051 rtx x;
23054 {
23060 }
23061 else
23062 {
23068 }
23072 else
23080 }
23085 }
23088 {
23089 /* For -1 << N, we can avoid the shld instruction, because we
23090 know that we're shifting 0...31/63 ones into a -1. */
23094 else
23096 }
23097 else
23098 {
23106 }
23111 {
23117 }
23118 else
23119 {
23124 }
23125 }
23127 void
23129 {
23139 {
23144 {
23150 }
23152 {
23161 }
23162 else
23163 {
23171 }
23172 }
23173 else
23174 {
23186 {
23194 scratch));
23195 }
23196 else
23197 {
23202 }
23203 }
23204 }
23206 void
23208 {
23218 {
23223 {
23230 }
23231 else
23232 {
23240 }
23241 }
23242 else
23243 {
23255 {
23261 scratch));
23262 }
23263 else
23264 {
23269 }
23270 }
23271 }
23273 /* Predict just emitted jump instruction to be taken with probability PROB. */
23274 static void
23276 {
23280 }
23282 /* Helper function for the string operations below. Dest VARIABLE whether
23283 it is aligned to VALUE bytes. If true, jump to the label. */
23286 {
23291 else
23297 else
23300 }
23302 /* Adjust COUNTER by the VALUE. */
23303 static void
23305 {
23310 }
23312 /* Zero extend possibly SImode EXP to Pmode register. */
23313 rtx
23315 {
23317 }
23319 /* Divide COUNTREG by SCALE. */
23320 static rtx
23322 {
23323 rtx sc;
23335 }
23337 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23338 DImode for constant loop counts. */
23340 static machine_mode
23342 {
23350 }
23352 /* Copy the address to a Pmode register. This is used for x32 to
23353 truncate DImode TLS address to a SImode register. */
23355 static rtx
23357 {
23358 rtx reg;
23360 {
23364 }
23365 else
23366 {
23371 }
23372 }
23374 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23375 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23376 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23377 memory by VALUE (supposed to be in MODE).
23379 The size is rounded down to whole number of chunk size moved at once.
23380 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23383 static void
23388 {
23395 rtx size;
23404 /* Those two should combine. */
23406 {
23410 }
23417 /* This assert could be relaxed - in this case we'll need to compute
23418 smallest power of two, containing in PIECE_SIZE_N and pass it to
23419 offset_address. */
23425 {
23429 /* When unrolling for chips that reorder memory reads and writes,
23430 we can save registers by using single temporary.
23431 Also using 4 temporaries is overkill in 32bit mode. */
23433 {
23435 {
23437 {
23438 destmem =
23440 srcmem =
23442 }
23444 }
23445 }
23446 else
23447 {
23451 {
23454 {
23455 srcmem =
23457 }
23459 }
23461 {
23463 {
23464 destmem =
23466 }
23468 }
23469 }
23470 }
23471 else
23473 {
23475 destmem =
23478 }
23488 {
23494 else
23496 }
23497 else
23505 {
23510 }
23512 }
23514 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23515 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23516 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23517 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23518 ORIG_VALUE is the original value passed to memset to fill the memory with.
23519 Other arguments have same meaning as for previous function. */
23521 static void
23524 rtx count,
23526 {
23527 rtx destexp;
23528 rtx srcexp;
23529 rtx countreg;
23530 HOST_WIDE_INT rounded_count;
23532 /* If possible, it is shorter to use rep movs.
23533 TODO: Maybe it is better to move this logic to decide_alg. */
23544 {
23548 }
23549 else
23552 {
23557 }
23562 {
23565 }
23566 else
23567 {
23571 {
23575 }
23576 else
23579 {
23584 }
23585 else
23586 {
23589 }
23592 }
23593 }
23595 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23596 DESTMEM.
23597 SRC is passed by pointer to be updated on return.
23598 Return value is updated DST. */
23599 static rtx
23601 HOST_WIDE_INT size_to_move)
23602 {
23605 machine_mode move_mode;
23608 /* Find the widest mode in which we could perform moves.
23609 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23610 it until move of such size is supported. */
23615 {
23619 }
23621 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23622 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23624 {
23629 {
23633 }
23634 }
23640 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23644 {
23645 /* We move from memory to memory, so we'll need to do it via
23646 a temporary register. */
23657 piece_size);
23659 piece_size);
23660 }
23662 /* Update DST and SRC rtx. */
23665 }
23667 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23668 static void
23671 {
23674 {
23679 /* For now MAX_SIZE should be a power of 2. This assert could be
23680 relaxed, but it'll require a bit more complicated epilogue
23681 expanding. */
23684 {
23687 }
23689 }
23691 {
23697 }
23699 /* When there are stringops, we can cheaply increase dest and src pointers.
23700 Otherwise we save code size by maintaining offset (zero is readily
23701 available from preceding rep operation) and using x86 addressing modes.
23702 */
23704 {
23706 {
23713 }
23715 {
23722 }
23724 {
23731 }
23732 }
23733 else
23734 {
23736 rtx tmp;
23739 {
23750 }
23752 {
23765 }
23767 {
23776 }
23777 }
23778 }
23780 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23781 with value PROMOTED_VAL.
23782 SRC is passed by pointer to be updated on return.
23783 Return value is updated DST. */
23784 static rtx
23786 HOST_WIDE_INT size_to_move)
23787 {
23790 machine_mode move_mode;
23793 /* Find the widest mode in which we could perform moves.
23794 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23795 it until move of such size is supported. */
23800 {
23803 }
23810 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23814 {
23816 {
23819 piece_size);
23821 }
23829 piece_size);
23830 }
23832 /* Update DST rtx. */
23834 }
23835 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23836 static void
23839 {
23840 count =
23846 }
23848 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23849 static void
23852 {
23853 rtx dest;
23856 {
23861 /* For now MAX_SIZE should be a power of 2. This assert could be
23862 relaxed, but it'll require a bit more complicated epilogue
23863 expanding. */
23866 {
23868 {
23871 else
23873 }
23874 }
23876 }
23878 {
23881 }
23883 {
23886 {
23891 }
23892 else
23893 {
23902 }
23905 }
23907 {
23910 {
23913 }
23914 else
23915 {
23920 }
23923 }
23925 {
23931 }
23933 {
23939 }
23941 {
23947 }
23948 }
23950 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23951 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23952 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23953 ignored.
23954 Return value is updated DESTMEM. */
23955 static rtx
23960 {
23963 {
23965 {
23968 {
23971 else
23973 }
23974 else
23980 }
23981 }
23983 }
23985 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23986 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23987 and jump to DONE_LABEL. */
23988 static void
23994 {
23997 rtx modesize;
24000 /* If we do not have vector value to copy, we must reduce size. */
24002 {
24004 {
24009 }
24010 else
24012 }
24013 else
24014 {
24015 /* Choose appropriate vector mode. */
24021 }
24026 {
24029 else
24030 {
24033 }
24035 }
24041 {
24045 }
24047 {
24050 else
24051 {
24054 }
24056 }
24062 }
24064 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24065 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24066 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24067 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24068 DONE_LABEL is a label after the whole copying sequence. The label is created
24069 on demand if *DONE_LABEL is NULL.
24070 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24071 bounds after the initial copies.
24073 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24074 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24075 we will dispatch to a library call for large blocks.
24077 In pseudocode we do:
24079 if (COUNT < SIZE)
24080 {
24081 Assume that SIZE is 4. Bigger sizes are handled analogously
24082 if (COUNT & 4)
24083 {
24084 copy 4 bytes from SRCPTR to DESTPTR
24085 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24086 goto done_label
24087 }
24088 if (!COUNT)
24089 goto done_label;
24090 copy 1 byte from SRCPTR to DESTPTR
24091 if (COUNT & 2)
24092 {
24093 copy 2 bytes from SRCPTR to DESTPTR
24094 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24095 }
24096 }
24097 else
24098 {
24099 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24100 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24102 OLD_DESPTR = DESTPTR;
24103 Align DESTPTR up to DESIRED_ALIGN
24104 SRCPTR += DESTPTR - OLD_DESTPTR
24105 COUNT -= DEST_PTR - OLD_DESTPTR
24106 if (DYNAMIC_CHECK)
24107 Round COUNT down to multiple of SIZE
24108 << optional caller supplied zero size guard is here >>
24109 << optional caller suppplied dynamic check is here >>
24110 << caller supplied main copy loop is here >>
24111 }
24112 done_label:
24113 */
24114 static void
24117 machine_mode mode,
24127 {
24130 rtx modesize;
24132 rtx mode_value;
24134 /* Chose proper value to copy. */
24137 else
24141 /* See if block is big or small, handle small blocks. */
24143 {
24154 /* Handle sizes > 3. */
24161 /* Nothing to copy? Jump to DONE_LABEL if so */
24165 /* Do a byte copy. */
24169 else
24170 {
24173 }
24175 /* Handle sizes 2 and 3. */
24182 else
24183 {
24188 }
24194 }
24195 else
24199 /* Start memcpy for COUNT >= SIZE. */
24201 {
24204 }
24206 /* Copy first desired_align bytes. */
24212 {
24215 else
24216 {
24219 }
24222 }
24225 /* Copy last SIZE bytes. */
24232 else
24233 {
24239 }
24241 {
24245 else
24246 {
24249 }
24250 }
24252 /* Align destination. */
24254 {
24258 /* Align destptr up, place it to new register. */
24267 /* See how many bytes we skipped. */
24271 /* Adjust srcptr and count. */
24277 /* We copied at most size + prolog_size. */
24280 else
24283 /* Our loops always round down the bock size, but for dispatch to library
24284 we need precise value. */
24288 }
24289 else
24290 {
24292 /* Decrease count, so we won't end up copying last word twice. */
24296 else
24300 }
24301 }
24304 /* This function is like the previous one, except here we know how many bytes
24305 need to be copied. That allows us to update alignment not only of DST, which
24306 is returned, but also of SRC, which is passed as a pointer for that
24307 reason. */
24308 static rtx
24313 {
24321 {
24325 }
24330 {
24332 {
24334 {
24337 else
24339 }
24340 else
24343 }
24344 }
24351 {
24357 {
24360 {
24364 }
24369 }
24373 }
24376 }
24378 /* Return true if ALG can be used in current context.
24379 Assume we expand memset if MEMSET is true. */
24380 static bool
24382 {
24387 /* Algorithms using the rep prefix want at least edi and ecx;
24388 additionally, memset wants eax and memcpy wants esi. Don't
24389 consider such algorithms if the user has appropriated those
24390 registers for their own purposes. */
24397 }
24399 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24400 static enum stringop_alg
24404 {
24415 /* Even if the string operation call is cold, we still might spend a lot
24416 of time processing large blocks. */
24422 else
24428 else
24431 /* See maximal size for user defined algorithm. */
24433 {
24440 }
24442 /* If expected size is not known but max size is small enough
24443 so inline version is a win, set expected size into
24444 the range. */
24449 /* If user specified the algorithm, honnor it if possible. */
24453 /* rep; movq or rep; movl is the smallest variant. */
24455 {
24460 else
24463 }
24464 /* Very tiny blocks are best handled via the loop, REP is expensive to
24465 setup. */
24469 {
24473 {
24474 /* We get here if the algorithms that were not libcall-based
24475 were rep-prefix based and we are unable to use rep prefixes
24476 based on global register usage. Break out of the loop and
24477 use the heuristic below. */
24481 {
24485 {
24488 }
24489 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24490 last non-libcall inline algorithm. */
24492 {
24493 /* When the current size is best to be copied by a libcall,
24494 but we are still forced to inline, run the heuristic below
24495 that will pick code for medium sized blocks. */
24497 {
24500 }
24503 }
24505 {
24508 }
24509 }
24510 }
24511 }
24512 /* When asked to inline the call anyway, try to pick meaningful choice.
24513 We look for maximal size of block that is faster to copy by hand and
24514 take blocks of at most of that size guessing that average size will
24515 be roughly half of the block.
24517 If this turns out to be bad, we might simply specify the preferred
24518 choice in ix86_costs. */
24522 {
24525 /* If there aren't any usable algorithms, then recursing on
24526 smaller sizes isn't going to find anything. Just return the
24527 simple byte-at-a-time copy loop. */
24529 {
24530 /* Pick something reasonable. */
24534 }
24542 else
24545 }
24548 }
24550 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24551 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24552 static int
24556 machine_mode move_mode)
24557 {
24568 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24569 copying whole cacheline at once. */
24582 }
24585 /* Helper function for memcpy. For QImode value 0xXY produce
24586 0xXYXYXYXY of wide specified by MODE. This is essentially
24587 a * 0x10101010, but we can do slightly better than
24588 synth_mult by unwinding the sequence by hand on CPUs with
24589 slow multiply. */
24590 static rtx
24592 {
24594 rtx tmp;
24601 {
24609 }
24618 nops--;
24623 {
24627 OPTAB_DIRECT);
24628 }
24629 else
24630 {
24636 else
24638 else
24639 {
24642 reg =
24644 }
24654 }
24655 }
24657 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24658 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24659 alignment from ALIGN to DESIRED_ALIGN. */
24660 static rtx
24663 {
24664 rtx promoted_val;
24673 else
24677 }
24679 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24680 operations when profitable. The code depends upon architecture, block size
24681 and alignment, but always has one of the following overall structures:
24683 Aligned move sequence:
24685 1) Prologue guard: Conditional that jumps up to epilogues for small
24686 blocks that can be handled by epilogue alone. This is faster
24687 but also needed for correctness, since prologue assume the block
24688 is larger than the desired alignment.
24690 Optional dynamic check for size and libcall for large
24691 blocks is emitted here too, with -minline-stringops-dynamically.
24693 2) Prologue: copy first few bytes in order to get destination
24694 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24695 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24696 copied. We emit either a jump tree on power of two sized
24697 blocks, or a byte loop.
24699 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24700 with specified algorithm.
24702 4) Epilogue: code copying tail of the block that is too small to be
24703 handled by main body (or up to size guarded by prologue guard).
24705 Misaligned move sequence
24707 1) missaligned move prologue/epilogue containing:
24708 a) Prologue handling small memory blocks and jumping to done_label
24709 (skipped if blocks are known to be large enough)
24710 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24711 needed by single possibly misaligned move
24712 (skipped if alignment is not needed)
24713 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24715 2) Zero size guard dispatching to done_label, if needed
24717 3) dispatch to library call, if needed,
24719 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24720 with specified algorithm. */
24721 bool
24727 {
24728 rtx destreg;
24731 rtx tmp;
24747 /* TODO: Once value ranges are available, fill in proper data. */
24755 /* i386 can do misaligned access on reasonably increased cost. */
24759 /* ALIGN is the minimum of destination and source alignment, but we care here
24760 just about destination alignment. */
24766 {
24769 /* When COUNT is 0, there is nothing to do. */
24772 }
24773 else
24774 {
24783 }
24785 /* Make sure we don't need to care about overflow later on. */
24789 /* Step 0: Decide on preferred algorithm, desired alignment and
24790 size of chunks to be copied by main loop. */
24792 issetmem,
24799 /* For now vector-version of memset is generated only for memory zeroing, as
24800 creating of promoted vector value is very cheap in this case. */
24813 {
24832 /* Find the widest supported mode. */
24838 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24839 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24841 {
24846 }
24858 }
24866 /* Step 1: Prologue guard. */
24868 /* Alignment code needs count to be in register. */
24870 {
24873 {
24874 align_bytes
24878 else
24880 }
24883 }
24886 /* Misaligned move sequences handle both prologue and epilogue at once.
24887 Default code generation results in a smaller code for large alignments
24888 and also avoids redundant job when sizes are known precisely. */
24889 misaligned_prologue_used
24890 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24896 /* Do the cheap promotion to allow better CSE across the
24897 main loop and epilogue (ie one load of the big constant in the
24898 front of all code.
24899 For now the misaligned move sequences do not have fast path
24900 without broadcasting. */
24902 {
24904 {
24910 }
24911 else
24912 {
24915 }
24916 }
24917 /* Misaligned move sequences handles both prologues and epilogues at once.
24918 Default code generation results in smaller code for large alignments and
24919 also avoids redundant job when sizes are known precisely. */
24921 {
24922 /* Misaligned move prologue handled small blocks by itself. */
24923 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24928 desired_align < align
24937 {
24938 /* It is possible that we copied enough so the main loop will not
24939 execute. */
24949 else
24951 }
24952 }
24953 /* Ensure that alignment prologue won't copy past end of block. */
24955 {
24957 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24958 Make sure it is power of 2. */
24961 /* To improve performance of small blocks, we jump around the VAL
24962 promoting mode. This mean that if the promoted VAL is not constant,
24963 we might not use it in the epilogue and have to use byte
24964 loop variant. */
24969 {
24970 /* If main algorithm works on QImode, no epilogue is needed.
24971 For small sizes just don't align anything. */
24974 else
24976 }
24979 {
24986 else
24988 }
24989 }
24991 /* Emit code to decide on runtime whether library call or inline should be
24992 used. */
24994 {
24996 {
24998 {
25002 }
25003 }
25004 else
25005 {
25015 else
25019 }
25020 }
25022 /* Step 2: Alignment prologue. */
25023 /* Do the expensive promotion once we branched off the small blocks. */
25029 {
25031 {
25032 /* Except for the first move in prologue, we no longer know
25033 constant offset in aliasing info. It don't seems to worth
25034 the pain to maintain it for the first move, so throw away
25035 the info early. */
25042 issetmem);
25043 /* At most desired_align - align bytes are copied. */
25046 else
25048 }
25049 else
25050 {
25051 /* If we know how many bytes need to be stored before dst is
25052 sufficiently aligned, maintain aliasing info accurately. */
25054 srcreg,
25055 promoted_val,
25056 vec_promoted_val,
25057 desired_align,
25058 align_bytes,
25059 issetmem);
25066 }
25068 && !min_size
25073 {
25074 /* It is possible that we copied enough so the main loop will not
25075 execute. */
25085 else
25087 }
25088 }
25090 {
25097 }
25101 /* Step 3: Main loop. */
25104 {
25127 }
25128 /* Adjust properly the offset of src and dest memory for aliasing. */
25130 {
25136 }
25137 else
25138 {
25142 }
25144 /* Step 4: Epilogue to copy the remaining bytes. */
25145 epilogue:
25147 {
25148 /* When the main loop is done, COUNT_EXP might hold original count,
25149 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25150 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25151 bytes. Compensate if needed. */
25154 {
25155 tmp =
25158 OPTAB_DIRECT);
25161 }
25164 }
25167 {
25170 epilogue_size_needed);
25171 else
25172 {
25176 epilogue_size_needed);
25177 else
25179 epilogue_size_needed);
25180 }
25181 }
25185 }
25188 /* Expand the appropriate insns for doing strlen if not just doing
25189 repnz; scasb
25191 out = result, initialized with the start address
25192 align_rtx = alignment of the address.
25193 scratch = scratch register, initialized with the startaddress when
25194 not aligned, otherwise undefined
25196 This is just the body. It needs the initializations mentioned above and
25197 some address computing at the end. These things are done in i386.md. */
25199 static void
25201 {
25203 rtx tmp;
25208 rtx mem;
25211 rtx cmp;
25217 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25219 /* Is there a known alignment and is it less than 4? */
25221 {
25224 /* Is there a known alignment and is it not 2? */
25226 {
25230 /* Leave just the 3 lower bits. */
25240 }
25241 else
25242 {
25243 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25244 check if is aligned to 4 - byte. */
25251 }
25255 /* Now compare the bytes. */
25257 /* Compare the first n unaligned byte on a byte per byte basis. */
25261 /* Increment the address. */
25264 /* Not needed with an alignment of 2 */
25266 {
25270 end_0_label);
25275 }
25278 end_0_label);
25281 }
25283 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25284 align this loop. It gives only huge programs, but does not help to
25285 speed up. */
25292 /* This formula yields a nonzero result iff one of the bytes is zero.
25293 This saves three branches inside loop and many cycles. */
25301 align_4_label);
25304 {
25310 /* If zero is not in the first two bytes, move two bytes forward. */
25316 reg,
25317 tmpreg)));
25318 /* Emit lea manually to avoid clobbering of flags. */
25326 reg2,
25327 out)));
25328 }
25329 else
25330 {
25332 /* Is zero in the first two bytes? */
25339 pc_rtx);
25343 /* Not in the first two. Move two bytes forward. */
25349 }
25351 /* Avoid branch in fixing the byte. */
25359 }
25361 /* Expand strlen. */
25363 bool
25365 {
25368 /* The generic case of strlen expander is long. Avoid it's
25369 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25372 && !TARGET_INLINE_ALL_STRINGOPS
25382 {
25383 /* Well it seems that some optimizer does not combine a call like
25384 foo(strlen(bar), strlen(bar));
25385 when the move and the subtraction is done here. It does calculate
25386 the length just once when these instructions are done inside of
25387 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25388 often used and I use one fewer register for the lifetime of
25389 output_strlen_unroll() this is better. */
25395 /* strlensi_unroll_1 returns the address of the zero at the end of
25396 the string, like memchr(), so compute the length by subtracting
25397 the start address. */
25399 }
25400 else
25401 {
25402 rtx unspec;
25404 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25417 /* If .md starts supporting :P, this can be done in .md. */
25423 }
25425 }
25427 /* For given symbol (function) construct code to compute address of it's PLT
25428 entry in large x86-64 PIC model. */
25429 static rtx
25431 {
25444 }
25446 rtx
25448 rtx callarg2,
25450 {
25460 {
25461 #if TARGET_MACHO
25464 #endif
25465 }
25466 else
25467 {
25468 /* Static functions and indirect calls don't need the pic register. */
25470 && (!TARGET_64BIT
25475 {
25479 pic_offset_table_rtx);
25480 }
25481 }
25483 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25484 parameters passed in vector registers. */
25489 {
25493 }
25496 && !TARGET_PECOFF
25504 {
25507 }
25512 {
25513 /* We should add bounds as destination register in case
25514 pointer with bounds may be returned. */
25516 {
25520 {
25525 }
25526 else
25527 {
25531 }
25532 }
25535 }
25539 {
25543 }
25547 {
25548 int const cregs_size
25553 {
25558 }
25559 }
25568 }
25570 /* Output the assembly for a call instruction. */
25574 {
25580 {
25583 /* SEH epilogue detection requires the indirect branch case
25584 to include REX.W. */
25587 else
25592 }
25594 /* SEH unwinding can require an extra nop to be emitted in several
25595 circumstances. Determine if we have one of those. */
25597 {
25601 {
25602 /* If we get to another real insn, we don't need the nop. */
25606 /* If we get to the epilogue note, prevent a catch region from
25607 being adjacent to the standard epilogue sequence. If non-
25608 call-exceptions, we'll have done this during epilogue emission. */
25610 && !flag_non_call_exceptions
25612 {
25615 }
25616 }
25618 /* If we didn't find a real insn following the call, prevent the
25619 unwinder from looking into the next function. */
25622 }
25626 else
25635 }
25636 \f
25637 /* Clear stack slot assignments remembered from previous functions.
25638 This is called from INIT_EXPANDERS once before RTL is emitted for each
25639 function. */
25643 {
25651 }
25653 /* Return a MEM corresponding to a stack slot with mode MODE.
25654 Allocate a new slot if necessary.
25656 The RTL for a function can have several slots available: N is
25657 which slot to use. */
25659 rtx
25661 {
25678 }
25680 static void
25682 {
25688 }
25689 \f
25690 /* Check whether x86 address PARTS is a pc-relative address. */
25692 static bool
25694 {
25702 {
25704 {
25721 }
25722 }
25724 }
25726 /* Calculate the length of the memory address in the instruction encoding.
25727 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25728 or other prefixes. We never generate addr32 prefix for LEA insn. */
25730 int
25732 {
25749 /* If this is not LEA instruction, add the length of addr32 prefix. */
25754 len++;
25768 /* Rule of thumb:
25769 - esp as the base always wants an index,
25770 - ebp as the base always wants a displacement,
25771 - r12 as the base always wants an index,
25772 - r13 as the base always wants a displacement. */
25774 /* Register Indirect. */
25776 {
25777 /* esp (for its index) and ebp (for its displacement) need
25778 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25779 code. */
25786 len++;
25787 }
25789 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25790 is not disp32, but disp32(%rip), so for disp32
25791 SIB byte is needed, unless print_operand_address
25792 optimizes it into disp32(%rip) or (%rip) is implied
25793 by UNSPEC. */
25795 {
25798 len++;
25799 }
25800 else
25801 {
25802 /* Find the length of the displacement constant. */
25804 {
25807 else
25809 }
25810 /* ebp always wants a displacement. Similarly r13. */
25812 len++;
25814 /* An index requires the two-byte modrm form.... */
25816 /* ...like esp (or r12), which always wants an index. */
25820 len++;
25821 }
25824 }
25826 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25827 is set, expect that insn have 8bit immediate alternative. */
25828 int
25830 {
25836 {
25841 {
25844 {
25856 }
25858 {
25861 }
25862 }
25864 {
25874 /* Immediates for DImode instructions are encoded
25875 as 32bit sign extended values. */
25881 }
25882 }
25884 }
25886 /* Compute default value for "length_address" attribute. */
25887 int
25889 {
25893 {
25904 }
25909 {
25912 {
25917 constraints++;
25920 ;
25921 /* Skip ignored operands. */
25924 }
25926 }
25928 }
25930 /* Compute default value for "length_vex" attribute. It includes
25931 2 or 3 byte VEX prefix and 1 opcode byte. */
25933 int
25936 {
25939 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25940 byte VEX prefix. */
25944 /* We can always use 2 byte VEX prefix in 32bit. */
25952 {
25953 /* REX.W bit uses 3 byte VEX prefix. */
25957 }
25958 else
25959 {
25960 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25964 }
25967 }
25968 \f
25969 /* Return the maximum number of instructions a cpu can issue. */
25971 static int
25973 {
25975 {
26007 }
26008 }
26010 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
26011 by DEP_INSN and nothing set by DEP_INSN. */
26013 static bool
26015 {
26018 /* Simplify the test for uninteresting insns. */
26026 {
26029 }
26034 {
26037 }
26038 else
26044 /* This test is true if the dependent insn reads the flags but
26045 not any other potentially set register. */
26053 }
26055 /* Return true iff USE_INSN has a memory address with operands set by
26056 SET_INSN. */
26058 bool
26060 {
26065 {
26068 }
26070 }
26072 /* Helper function for exact_store_load_dependency.
26073 Return true if addr is found in insn. */
26074 static bool
26076 {
26083 {
26089 CASE_CONST_ANY:
26098 }
26102 {
26104 {
26114 }
26115 }
26117 }
26119 /* Return true if there exists exact dependency for store & load, i.e.
26120 the same memory address is used in them. */
26121 static bool
26123 {
26137 }
26139 static int
26141 {
26147 /* Anti and output dependencies have zero cost on all CPUs. */
26153 /* If we can't recognize the insns, we can't really do anything. */
26161 {
26163 /* Address Generation Interlock adds a cycle of latency. */
26165 {
26176 }
26180 /* ??? Compares pair with jump/setcc. */
26184 /* Floating point stores require value to be ready one cycle earlier. */
26192 /* INT->FP conversion is expensive. */
26196 /* There is one cycle extra latency between an FP op and a store. */
26206 /* Show ability of reorder buffer to hide latency of load by executing
26207 in parallel with previous instruction in case
26208 previous instruction is not needed to compute the address. */
26211 {
26212 /* Claim moves to take one cycle, as core can issue one load
26213 at time and the next load can start cycle later. */
26218 cost--;
26219 }
26223 /* The esp dependency is resolved before
26224 the instruction is really finished. */
26229 /* INT->FP conversion is expensive. */
26235 /* Show ability of reorder buffer to hide latency of load by executing
26236 in parallel with previous instruction in case
26237 previous instruction is not needed to compute the address. */
26240 {
26241 /* Claim moves to take one cycle, as core can issue one load
26242 at time and the next load can start cycle later. */
26248 else
26250 }
26261 /* Stack engine allows to execute push&pop instructions in parall. */
26265 /* FALLTHRU */
26271 /* Show ability of reorder buffer to hide latency of load by executing
26272 in parallel with previous instruction in case
26273 previous instruction is not needed to compute the address. */
26276 {
26280 /* Because of the difference between the length of integer and
26281 floating unit pipeline preparation stages, the memory operands
26282 for floating point are cheaper.
26284 ??? For Athlon it the difference is most probably 2. */
26287 else
26292 else
26294 }
26301 /* Stack engine allows to execute push&pop instructions in parall. */
26308 /* Show ability of reorder buffer to hide latency of load by executing
26309 in parallel with previous instruction in case
26310 previous instruction is not needed to compute the address. */
26313 {
26316 else
26318 }
26327 /* Increase cost of integer loads. */
26330 {
26333 {
26336 else
26337 {
26338 /* Increase cost of ld/st for short int types only
26339 because of store forwarding issue. */
26343 {
26344 /* Increase cost of store/load insn if exact
26345 dependence exists and it is load insn. */
26350 }
26351 }
26352 }
26353 }
26357 }
26360 }
26362 /* How many alternative schedules to try. This should be as wide as the
26363 scheduling freedom in the DFA, but no wider. Making this value too
26364 large results extra work for the scheduler. */
26366 static int
26368 {
26370 {
26382 /* We use lookahead value 4 for BD both before and after reload
26383 schedules. Plan is to have value 8 included for O3. */
26394 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26395 as many instructions can be executed on a cycle, i.e.,
26396 issue_rate. I wonder why tuning for many CPUs does not do this. */
26399 /* Don't use lookahead for pre-reload schedule to save compile time. */
26404 }
26405 }
26407 /* Return true if target platform supports macro-fusion. */
26409 static bool
26411 {
26413 }
26415 /* Check whether current microarchitecture support macro fusion
26416 for insn pair "CONDGEN + CONDJMP". Refer to
26417 "Intel Architectures Optimization Reference Manual". */
26419 static bool
26421 {
26442 {
26447 {
26451 else
26453 }
26454 }
26461 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26462 supported. */
26469 /* No fusion for RIP-relative address. */
26476 ix86_address parts;
26482 }
26487 /* Check whether conditional jump use Sign or Overflow Flags. */
26495 /* Return true for TYPE_TEST and TYPE_ICMP. */
26500 /* The following is the case that macro-fusion for alu + jmp. */
26504 /* No fusion for alu op with memory destination operand. */
26509 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26510 supported. */
26519 }
26521 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26522 execution. It is applied if
26523 (1) IMUL instruction is on the top of list;
26524 (2) There exists the only producer of independent IMUL instruction in
26525 ready list.
26526 Return index of IMUL producer if it was found and -1 otherwise. */
26527 static int
26529 {
26532 sd_iterator_def sd_it;
26533 dep_t dep;
26540 /* Check that IMUL instruction is on the top of ready list. */
26549 /* Search for producer of independent IMUL instruction. */
26551 {
26555 /* Skip IMUL instruction. */
26565 {
26566 rtx con;
26577 {
26578 sd_iterator_def sd_it1;
26579 dep_t dep1;
26580 /* Check if there is no other dependee for IMUL. */
26583 {
26584 rtx pro;
26590 }
26593 }
26594 }
26597 }
26599 }
26601 /* Try to find the best candidate on the top of ready list if two insns
26602 have the same priority - candidate is best if its dependees were
26603 scheduled earlier. Applied for Silvermont only.
26604 Return true if top 2 insns must be interchanged. */
26605 static bool
26607 {
26610 rtx set;
26611 sd_iterator_def sd_it;
26612 dep_t dep;
26615 #define INSN_TICK(INSN) (HID (INSN)->tick)
26636 {
26639 /* Determine winner more precise. */
26641 {
26642 rtx pro;
26648 }
26650 {
26651 rtx pro;
26657 }
26660 {
26661 /* Determine winner - load must win. */
26667 }
26669 }
26671 #undef INSN_TICK
26672 }
26674 /* Perform possible reodering of ready list for Atom/Silvermont only.
26675 Return issue rate. */
26676 static int
26679 {
26686 /* Set up issue rate. */
26689 /* Do reodering for BONNELL/SILVERMONT only. */
26693 /* Nothing to do if ready list contains only 1 instruction. */
26697 /* Do reodering for post-reload scheduler only. */
26702 {
26707 /* Put IMUL producer (ready[index]) at the top of ready list. */
26713 }
26715 /* Skip selective scheduling since HID is not populated in it. */
26719 {
26723 /* Swap 2 top elements of ready list. */
26727 }
26729 }
26731 static bool
26734 /* Returns true if lhs of insn is HW function argument register and set up
26735 is_spilled to true if it is likely spilled HW register. */
26736 static bool
26738 {
26739 rtx dst;
26743 /* Call instructions are not movable, ignore it. */
26754 {
26755 /* Is it likely spilled HW register? */
26760 }
26762 }
26764 /* Add output dependencies for chain of function adjacent arguments if only
26765 there is a move to likely spilled HW register. Return first argument
26766 if at least one dependence was added or NULL otherwise. */
26769 {
26777 /* Find nearest to call argument passing instruction. */
26779 {
26788 }
26792 {
26799 {
26802 }
26804 {
26805 /* Add output depdendence between two function arguments if chain
26806 of output arguments contains likely spilled HW registers. */
26810 }
26811 else
26813 }
26817 }
26819 /* Add output or anti dependency from insn to first_arg to restrict its code
26820 motion. */
26821 static void
26823 {
26824 rtx set;
26825 rtx tmp;
26827 /* Add anti dependencies for bounds stores. */
26832 {
26835 }
26842 {
26843 /* Add output dependency to the first function argument. */
26846 }
26847 /* Add anti dependency. */
26849 }
26851 /* Avoid cross block motion of function argument through adding dependency
26852 from the first non-jump instruction in bb. */
26853 static void
26855 {
26859 {
26861 {
26864 {
26867 }
26868 }
26872 }
26873 }
26875 /* Hook for pre-reload schedule - avoid motion of function arguments
26876 passed in likely spilled HW registers. */
26877 static void
26879 {
26888 {
26891 {
26892 /* Add dependee for first argument to predecessors if only
26893 region contains more than one block. */
26897 /* Skip trivial regions and region head blocks that can have
26898 predecessors outside of region. */
26900 {
26901 edge e;
26902 edge_iterator ei;
26904 /* Regions are SCCs with the exception of selective
26905 scheduling with pipelining of outer blocks enabled.
26906 So also check that immediate predecessors of a non-head
26907 block are in the same region. */
26909 {
26910 /* Avoid creating of loop-carried dependencies through
26911 using topological ordering in the region. */
26915 }
26916 }
26920 }
26921 }
26924 }
26926 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26927 HW registers to maximum, to schedule them at soon as possible. These are
26928 moves from function argument registers at the top of the function entry
26929 and moves from function return value registers after call. */
26930 static int
26932 {
26933 rtx set;
26943 {
26950 }
26953 }
26955 /* Model decoder of Core 2/i7.
26956 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26957 track the instruction fetch block boundaries and make sure that long
26958 (9+ bytes) instructions are assigned to D0. */
26960 /* Maximum length of an insn that can be handled by
26961 a secondary decoder unit. '8' for Core 2/i7. */
26964 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26965 '16' for Core 2/i7. */
26968 /* Maximum number of instructions decoder can handle per cycle.
26969 '6' for Core 2/i7. */
26973 ix86_first_cycle_multipass_data_t;
26975 const_ix86_first_cycle_multipass_data_t;
26977 /* A variable to store target state across calls to max_issue within
26978 one cycle. */
26982 /* Initialize DATA. */
26983 static void
26985 {
26986 ix86_first_cycle_multipass_data_t data
26993 }
26995 /* Advancing the cycle; reset ifetch block counts. */
26996 static void
26998 {
27005 }
27009 /* Filter out insns from ready_try that the core will not be able to issue
27010 on current cycle due to decoder. */
27011 static void
27012 core2i7_first_cycle_multipass_filter_ready_try
27015 {
27017 {
27028 (!first_cycle_insn_p
27030 /* ... or it would not fit into the ifetch block ... */
27032 /* ... or the decoder is full already ... */
27034 /* ... mask the insn out. */
27035 {
27040 }
27041 }
27042 }
27044 /* Prepare for a new round of multipass lookahead scheduling. */
27045 static void
27049 {
27050 ix86_first_cycle_multipass_data_t data
27052 const_ix86_first_cycle_multipass_data_t prev_data
27055 /* Restore the state from the end of the previous round. */
27059 /* Filter instructions that cannot be issued on current cycle due to
27060 decoder restrictions. */
27062 first_cycle_insn_p);
27063 }
27065 /* INSN is being issued in current solution. Account for its impact on
27066 the decoder model. */
27067 static void
27071 {
27072 ix86_first_cycle_multipass_data_t data
27074 const_ix86_first_cycle_multipass_data_t prev_data
27084 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27086 {
27089 }
27091 {
27095 }
27098 /* Filter out insns from ready_try that the core will not be able to issue
27099 on current cycle due to decoder. */
27102 }
27104 /* Revert the effect on ready_try. */
27105 static void
27109 {
27110 const_ix86_first_cycle_multipass_data_t data
27113 sbitmap_iterator sbi;
27117 {
27119 }
27120 }
27122 /* Save the result of multipass lookahead scheduling for the next round. */
27123 static void
27125 {
27126 const_ix86_first_cycle_multipass_data_t data
27128 ix86_first_cycle_multipass_data_t next_data
27132 {
27135 }
27136 }
27138 /* Deallocate target data. */
27139 static void
27141 {
27142 ix86_first_cycle_multipass_data_t data
27146 {
27150 }
27151 }
27153 /* Prepare for scheduling pass. */
27154 static void
27156 {
27157 /* Install scheduling hooks for current CPU. Some of these hooks are used
27158 in time-critical parts of the scheduler, so we only set them up when
27159 they are actually used. */
27161 {
27166 /* Do not perform multipass scheduling for pre-reload schedule
27167 to save compile time. */
27169 {
27185 /* Set decoder parameters. */
27190 }
27191 /* ... Fall through ... */
27201 }
27202 }
27204 \f
27205 /* Compute the alignment given to a constant that is being placed in memory.
27206 EXP is the constant and ALIGN is the alignment that the object would
27207 ordinarily have.
27208 The value of this function is used instead of that alignment to align
27209 the object. */
27211 int
27213 {
27216 {
27221 }
27227 }
27229 /* Compute the alignment for a static variable.
27230 TYPE is the data type, and ALIGN is the alignment that
27231 the object would ordinarily have. The value of this function is used
27232 instead of that alignment to align the object. */
27234 int
27236 {
27237 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27238 for symbols from other compilation units or symbols that don't need
27239 to bind locally. In order to preserve some ABI compatibility with
27240 those compilers, ensure we don't decrease alignment from what we
27241 used to assume. */
27245 /* A data structure, equal or greater than the size of a cache line
27246 (64 bytes in the Pentium 4 and other recent Intel processors, including
27247 processors based on Intel Core microarchitecture) should be aligned
27248 so that its base address is a multiple of a cache line size. */
27250 int max_align
27257 {
27261 }
27267 {
27274 }
27276 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27277 to 16byte boundary. */
27279 {
27286 }
27292 {
27297 }
27299 {
27306 }
27311 {
27316 }
27319 {
27324 }
27327 }
27329 /* Compute the alignment for a local variable or a stack slot. EXP is
27330 the data type or decl itself, MODE is the widest mode available and
27331 ALIGN is the alignment that the object would ordinarily have. The
27332 value of this macro is used instead of that alignment to align the
27333 object. */
27335 unsigned int
27338 {
27342 {
27345 }
27346 else
27347 {
27350 }
27352 /* Don't do dynamic stack realignment for long long objects with
27353 -mpreferred-stack-boundary=2. */
27362 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27363 register in MODE. We will return the largest alignment of XF
27364 and DF. */
27366 {
27370 }
27372 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27373 to 16byte boundary. Exact wording is:
27375 An array uses the same alignment as its elements, except that a local or
27376 global array variable of length at least 16 bytes or
27377 a C99 variable-length array variable always has alignment of at least 16 bytes.
27379 This was added to allow use of aligned SSE instructions at arrays. This
27380 rule is meant for static storage (where compiler can not do the analysis
27381 by itself). We follow it for automatic variables only when convenient.
27382 We fully control everything in the function compiled and functions from
27383 other unit can not rely on the alignment.
27385 Exclude va_list type. It is the common case of local array where
27386 we can not benefit from the alignment.
27388 TODO: Probably one should optimize for size only when var is not escaping. */
27391 {
27401 }
27403 {
27408 }
27410 {
27416 }
27421 {
27426 }
27429 {
27435 }
27437 }
27439 /* Compute the minimum required alignment for dynamic stack realignment
27440 purposes for a local variable, parameter or a stack slot. EXP is
27441 the data type or decl itself, MODE is its mode and ALIGN is the
27442 alignment that the object would ordinarily have. */
27444 unsigned int
27447 {
27451 {
27454 }
27455 else
27456 {
27459 }
27464 /* Don't do dynamic stack realignment for long long objects with
27465 -mpreferred-stack-boundary=2. */
27472 }
27473 \f
27474 /* Find a location for the static chain incoming to a nested function.
27475 This is a register, unless all free registers are used by arguments. */
27477 static rtx
27479 {
27482 /* While this function won't be called by the middle-end when a static
27483 chain isn't needed, it's also used throughout the backend so it's
27484 easiest to keep this check centralized. */
27489 {
27490 /* We always use R10 in 64-bit mode. */
27492 }
27493 else
27494 {
27498 /* By default in 32-bit mode we use ECX to pass the static chain. */
27502 {
27505 }
27506 else
27507 {
27510 }
27514 {
27515 /* Fastcall functions use ecx/edx for arguments, which leaves
27516 us with EAX for the static chain.
27517 Thiscall functions use ecx for arguments, which also
27518 leaves us with EAX for the static chain. */
27520 }
27522 {
27523 /* Thiscall functions use ecx for arguments, which leaves
27524 us with EAX and EDX for the static chain.
27525 We are using for abi-compatibility EAX. */
27527 }
27529 {
27530 /* For regparm 3, we have no free call-clobbered registers in
27531 which to store the static chain. In order to implement this,
27532 we have the trampoline push the static chain to the stack.
27533 However, we can't push a value below the return address when
27534 we call the nested function directly, so we have to use an
27535 alternate entry point. For this we use ESI, and have the
27536 alternate entry point push ESI, so that things appear the
27537 same once we're executing the nested function. */
27539 {
27545 }
27547 }
27548 }
27551 }
27553 /* Emit RTL insns to initialize the variable parts of a trampoline.
27554 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27555 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27556 to be passed to the target function. */
27558 static void
27560 {
27568 {
27571 /* Load the function address to r11. Try to load address using
27572 the shorter movl instead of movabs. We may want to support
27573 movq for kernel mode, but kernel does not use trampolines at
27574 the moment. FNADDR is a 32bit address and may not be in
27575 DImode when ptr_mode == SImode. Always use movl in this
27576 case. */
27579 {
27588 }
27589 else
27590 {
27597 }
27599 /* Load static chain using movabs to r10. Use the shorter movl
27600 instead of movabs when ptr_mode == SImode. */
27602 {
27605 }
27606 else
27607 {
27610 }
27619 /* Jump to r11; the last (unused) byte is a nop, only there to
27620 pad the write out to a single 32-bit store. */
27624 }
27625 else
27626 {
27629 /* Depending on the static chain location, either load a register
27630 with a constant, or push the constant to the stack. All of the
27631 instructions are the same size. */
27634 {
27636 {
27643 }
27644 }
27645 else
27660 /* Compute offset from the end of the jmp to the target function.
27661 In the case in which the trampoline stores the static chain on
27662 the stack, we need to skip the first insn which pushes the
27663 (call-saved) register static chain; this push is 1 byte. */
27670 }
27674 #ifdef HAVE_ENABLE_EXECUTE_STACK
27675 #ifdef CHECK_EXECUTE_STACK_ENABLED
27677 #endif
27680 #endif
27681 }
27682 \f
27683 /* The following file contains several enumerations and data structures
27684 built from the definitions in i386-builtin-types.def. */
27688 /* Table for the ix86 builtin non-function types. */
27691 /* Retrieve an element from the above table, building some of
27692 the types lazily. */
27694 static tree
27696 {
27708 {
27709 machine_mode mode;
27716 }
27717 else
27718 {
27724 else
27732 }
27736 }
27738 /* Table for the ix86 builtin function types. */
27741 /* Retrieve an element from the above table, building some of
27742 the types lazily. */
27744 static tree
27746 {
27747 tree type;
27756 {
27764 {
27767 }
27770 }
27771 else
27772 {
27778 }
27782 }
27785 /* Codes for all the SSE/MMX builtins. */
27786 enum ix86_builtins
27787 {
27788 IX86_BUILTIN_ADDPS,
27789 IX86_BUILTIN_ADDSS,
27790 IX86_BUILTIN_DIVPS,
27791 IX86_BUILTIN_DIVSS,
27792 IX86_BUILTIN_MULPS,
27793 IX86_BUILTIN_MULSS,
27794 IX86_BUILTIN_SUBPS,
27795 IX86_BUILTIN_SUBSS,
27797 IX86_BUILTIN_CMPEQPS,
27798 IX86_BUILTIN_CMPLTPS,
27799 IX86_BUILTIN_CMPLEPS,
27800 IX86_BUILTIN_CMPGTPS,
27801 IX86_BUILTIN_CMPGEPS,
27802 IX86_BUILTIN_CMPNEQPS,
27803 IX86_BUILTIN_CMPNLTPS,
27804 IX86_BUILTIN_CMPNLEPS,
27805 IX86_BUILTIN_CMPNGTPS,
27806 IX86_BUILTIN_CMPNGEPS,
27807 IX86_BUILTIN_CMPORDPS,
27808 IX86_BUILTIN_CMPUNORDPS,
27809 IX86_BUILTIN_CMPEQSS,
27810 IX86_BUILTIN_CMPLTSS,
27811 IX86_BUILTIN_CMPLESS,
27812 IX86_BUILTIN_CMPNEQSS,
27813 IX86_BUILTIN_CMPNLTSS,
27814 IX86_BUILTIN_CMPNLESS,
27815 IX86_BUILTIN_CMPORDSS,
27816 IX86_BUILTIN_CMPUNORDSS,
27818 IX86_BUILTIN_COMIEQSS,
27819 IX86_BUILTIN_COMILTSS,
27820 IX86_BUILTIN_COMILESS,
27821 IX86_BUILTIN_COMIGTSS,
27822 IX86_BUILTIN_COMIGESS,
27823 IX86_BUILTIN_COMINEQSS,
27824 IX86_BUILTIN_UCOMIEQSS,
27825 IX86_BUILTIN_UCOMILTSS,
27826 IX86_BUILTIN_UCOMILESS,
27827 IX86_BUILTIN_UCOMIGTSS,
27828 IX86_BUILTIN_UCOMIGESS,
27829 IX86_BUILTIN_UCOMINEQSS,
27831 IX86_BUILTIN_CVTPI2PS,
27832 IX86_BUILTIN_CVTPS2PI,
27833 IX86_BUILTIN_CVTSI2SS,
27834 IX86_BUILTIN_CVTSI642SS,
27835 IX86_BUILTIN_CVTSS2SI,
27836 IX86_BUILTIN_CVTSS2SI64,
27837 IX86_BUILTIN_CVTTPS2PI,
27838 IX86_BUILTIN_CVTTSS2SI,
27839 IX86_BUILTIN_CVTTSS2SI64,
27841 IX86_BUILTIN_MAXPS,
27842 IX86_BUILTIN_MAXSS,
27843 IX86_BUILTIN_MINPS,
27844 IX86_BUILTIN_MINSS,
27846 IX86_BUILTIN_LOADUPS,
27847 IX86_BUILTIN_STOREUPS,
27848 IX86_BUILTIN_MOVSS,
27850 IX86_BUILTIN_MOVHLPS,
27851 IX86_BUILTIN_MOVLHPS,
27852 IX86_BUILTIN_LOADHPS,
27853 IX86_BUILTIN_LOADLPS,
27854 IX86_BUILTIN_STOREHPS,
27855 IX86_BUILTIN_STORELPS,
27857 IX86_BUILTIN_MASKMOVQ,
27858 IX86_BUILTIN_MOVMSKPS,
27859 IX86_BUILTIN_PMOVMSKB,
27861 IX86_BUILTIN_MOVNTPS,
27862 IX86_BUILTIN_MOVNTQ,
27864 IX86_BUILTIN_LOADDQU,
27865 IX86_BUILTIN_STOREDQU,
27867 IX86_BUILTIN_PACKSSWB,
27868 IX86_BUILTIN_PACKSSDW,
27869 IX86_BUILTIN_PACKUSWB,
27871 IX86_BUILTIN_PADDB,
27872 IX86_BUILTIN_PADDW,
27873 IX86_BUILTIN_PADDD,
27874 IX86_BUILTIN_PADDQ,
27875 IX86_BUILTIN_PADDSB,
27876 IX86_BUILTIN_PADDSW,
27877 IX86_BUILTIN_PADDUSB,
27878 IX86_BUILTIN_PADDUSW,
27879 IX86_BUILTIN_PSUBB,
27880 IX86_BUILTIN_PSUBW,
27881 IX86_BUILTIN_PSUBD,
27882 IX86_BUILTIN_PSUBQ,
27883 IX86_BUILTIN_PSUBSB,
27884 IX86_BUILTIN_PSUBSW,
27885 IX86_BUILTIN_PSUBUSB,
27886 IX86_BUILTIN_PSUBUSW,
27888 IX86_BUILTIN_PAND,
27889 IX86_BUILTIN_PANDN,
27890 IX86_BUILTIN_POR,
27891 IX86_BUILTIN_PXOR,
27893 IX86_BUILTIN_PAVGB,
27894 IX86_BUILTIN_PAVGW,
27896 IX86_BUILTIN_PCMPEQB,
27897 IX86_BUILTIN_PCMPEQW,
27898 IX86_BUILTIN_PCMPEQD,
27899 IX86_BUILTIN_PCMPGTB,
27900 IX86_BUILTIN_PCMPGTW,
27901 IX86_BUILTIN_PCMPGTD,
27903 IX86_BUILTIN_PMADDWD,
27905 IX86_BUILTIN_PMAXSW,
27906 IX86_BUILTIN_PMAXUB,
27907 IX86_BUILTIN_PMINSW,
27908 IX86_BUILTIN_PMINUB,
27910 IX86_BUILTIN_PMULHUW,
27911 IX86_BUILTIN_PMULHW,
27912 IX86_BUILTIN_PMULLW,
27914 IX86_BUILTIN_PSADBW,
27915 IX86_BUILTIN_PSHUFW,
27917 IX86_BUILTIN_PSLLW,
27918 IX86_BUILTIN_PSLLD,
27919 IX86_BUILTIN_PSLLQ,
27920 IX86_BUILTIN_PSRAW,
27921 IX86_BUILTIN_PSRAD,
27922 IX86_BUILTIN_PSRLW,
27923 IX86_BUILTIN_PSRLD,
27924 IX86_BUILTIN_PSRLQ,
27925 IX86_BUILTIN_PSLLWI,
27926 IX86_BUILTIN_PSLLDI,
27927 IX86_BUILTIN_PSLLQI,
27928 IX86_BUILTIN_PSRAWI,
27929 IX86_BUILTIN_PSRADI,
27930 IX86_BUILTIN_PSRLWI,
27931 IX86_BUILTIN_PSRLDI,
27932 IX86_BUILTIN_PSRLQI,
27934 IX86_BUILTIN_PUNPCKHBW,
27935 IX86_BUILTIN_PUNPCKHWD,
27936 IX86_BUILTIN_PUNPCKHDQ,
27937 IX86_BUILTIN_PUNPCKLBW,
27938 IX86_BUILTIN_PUNPCKLWD,
27939 IX86_BUILTIN_PUNPCKLDQ,
27941 IX86_BUILTIN_SHUFPS,
27943 IX86_BUILTIN_RCPPS,
27944 IX86_BUILTIN_RCPSS,
27945 IX86_BUILTIN_RSQRTPS,
27946 IX86_BUILTIN_RSQRTPS_NR,
27947 IX86_BUILTIN_RSQRTSS,
27948 IX86_BUILTIN_RSQRTF,
27949 IX86_BUILTIN_SQRTPS,
27950 IX86_BUILTIN_SQRTPS_NR,
27951 IX86_BUILTIN_SQRTSS,
27953 IX86_BUILTIN_UNPCKHPS,
27954 IX86_BUILTIN_UNPCKLPS,
27956 IX86_BUILTIN_ANDPS,
27957 IX86_BUILTIN_ANDNPS,
27958 IX86_BUILTIN_ORPS,
27959 IX86_BUILTIN_XORPS,
27961 IX86_BUILTIN_EMMS,
27962 IX86_BUILTIN_LDMXCSR,
27963 IX86_BUILTIN_STMXCSR,
27964 IX86_BUILTIN_SFENCE,
27966 IX86_BUILTIN_FXSAVE,
27967 IX86_BUILTIN_FXRSTOR,
27968 IX86_BUILTIN_FXSAVE64,
27969 IX86_BUILTIN_FXRSTOR64,
27971 IX86_BUILTIN_XSAVE,
27972 IX86_BUILTIN_XRSTOR,
27973 IX86_BUILTIN_XSAVE64,
27974 IX86_BUILTIN_XRSTOR64,
27976 IX86_BUILTIN_XSAVEOPT,
27977 IX86_BUILTIN_XSAVEOPT64,
27979 IX86_BUILTIN_XSAVEC,
27980 IX86_BUILTIN_XSAVEC64,
27982 IX86_BUILTIN_XSAVES,
27983 IX86_BUILTIN_XRSTORS,
27984 IX86_BUILTIN_XSAVES64,
27985 IX86_BUILTIN_XRSTORS64,
27987 /* 3DNow! Original */
27988 IX86_BUILTIN_FEMMS,
27989 IX86_BUILTIN_PAVGUSB,
27990 IX86_BUILTIN_PF2ID,
27991 IX86_BUILTIN_PFACC,
27992 IX86_BUILTIN_PFADD,
27993 IX86_BUILTIN_PFCMPEQ,
27994 IX86_BUILTIN_PFCMPGE,
27995 IX86_BUILTIN_PFCMPGT,
27996 IX86_BUILTIN_PFMAX,
27997 IX86_BUILTIN_PFMIN,
27998 IX86_BUILTIN_PFMUL,
27999 IX86_BUILTIN_PFRCP,
28000 IX86_BUILTIN_PFRCPIT1,
28001 IX86_BUILTIN_PFRCPIT2,
28002 IX86_BUILTIN_PFRSQIT1,
28003 IX86_BUILTIN_PFRSQRT,
28004 IX86_BUILTIN_PFSUB,
28005 IX86_BUILTIN_PFSUBR,
28006 IX86_BUILTIN_PI2FD,
28007 IX86_BUILTIN_PMULHRW,
28009 /* 3DNow! Athlon Extensions */
28010 IX86_BUILTIN_PF2IW,
28011 IX86_BUILTIN_PFNACC,
28012 IX86_BUILTIN_PFPNACC,
28013 IX86_BUILTIN_PI2FW,
28014 IX86_BUILTIN_PSWAPDSI,
28015 IX86_BUILTIN_PSWAPDSF,
28017 /* SSE2 */
28018 IX86_BUILTIN_ADDPD,
28019 IX86_BUILTIN_ADDSD,
28020 IX86_BUILTIN_DIVPD,
28021 IX86_BUILTIN_DIVSD,
28022 IX86_BUILTIN_MULPD,
28023 IX86_BUILTIN_MULSD,
28024 IX86_BUILTIN_SUBPD,
28025 IX86_BUILTIN_SUBSD,
28027 IX86_BUILTIN_CMPEQPD,
28028 IX86_BUILTIN_CMPLTPD,
28029 IX86_BUILTIN_CMPLEPD,
28030 IX86_BUILTIN_CMPGTPD,
28031 IX86_BUILTIN_CMPGEPD,
28032 IX86_BUILTIN_CMPNEQPD,
28033 IX86_BUILTIN_CMPNLTPD,
28034 IX86_BUILTIN_CMPNLEPD,
28035 IX86_BUILTIN_CMPNGTPD,
28036 IX86_BUILTIN_CMPNGEPD,
28037 IX86_BUILTIN_CMPORDPD,
28038 IX86_BUILTIN_CMPUNORDPD,
28039 IX86_BUILTIN_CMPEQSD,
28040 IX86_BUILTIN_CMPLTSD,
28041 IX86_BUILTIN_CMPLESD,
28042 IX86_BUILTIN_CMPNEQSD,
28043 IX86_BUILTIN_CMPNLTSD,
28044 IX86_BUILTIN_CMPNLESD,
28045 IX86_BUILTIN_CMPORDSD,
28046 IX86_BUILTIN_CMPUNORDSD,
28048 IX86_BUILTIN_COMIEQSD,
28049 IX86_BUILTIN_COMILTSD,
28050 IX86_BUILTIN_COMILESD,
28051 IX86_BUILTIN_COMIGTSD,
28052 IX86_BUILTIN_COMIGESD,
28053 IX86_BUILTIN_COMINEQSD,
28054 IX86_BUILTIN_UCOMIEQSD,
28055 IX86_BUILTIN_UCOMILTSD,
28056 IX86_BUILTIN_UCOMILESD,
28057 IX86_BUILTIN_UCOMIGTSD,
28058 IX86_BUILTIN_UCOMIGESD,
28059 IX86_BUILTIN_UCOMINEQSD,
28061 IX86_BUILTIN_MAXPD,
28062 IX86_BUILTIN_MAXSD,
28063 IX86_BUILTIN_MINPD,
28064 IX86_BUILTIN_MINSD,
28066 IX86_BUILTIN_ANDPD,
28067 IX86_BUILTIN_ANDNPD,
28068 IX86_BUILTIN_ORPD,
28069 IX86_BUILTIN_XORPD,
28071 IX86_BUILTIN_SQRTPD,
28072 IX86_BUILTIN_SQRTSD,
28074 IX86_BUILTIN_UNPCKHPD,
28075 IX86_BUILTIN_UNPCKLPD,
28077 IX86_BUILTIN_SHUFPD,
28079 IX86_BUILTIN_LOADUPD,
28080 IX86_BUILTIN_STOREUPD,
28081 IX86_BUILTIN_MOVSD,
28083 IX86_BUILTIN_LOADHPD,
28084 IX86_BUILTIN_LOADLPD,
28086 IX86_BUILTIN_CVTDQ2PD,
28087 IX86_BUILTIN_CVTDQ2PS,
28089 IX86_BUILTIN_CVTPD2DQ,
28090 IX86_BUILTIN_CVTPD2PI,
28091 IX86_BUILTIN_CVTPD2PS,
28092 IX86_BUILTIN_CVTTPD2DQ,
28093 IX86_BUILTIN_CVTTPD2PI,
28095 IX86_BUILTIN_CVTPI2PD,
28096 IX86_BUILTIN_CVTSI2SD,
28097 IX86_BUILTIN_CVTSI642SD,
28099 IX86_BUILTIN_CVTSD2SI,
28100 IX86_BUILTIN_CVTSD2SI64,
28101 IX86_BUILTIN_CVTSD2SS,
28102 IX86_BUILTIN_CVTSS2SD,
28103 IX86_BUILTIN_CVTTSD2SI,
28104 IX86_BUILTIN_CVTTSD2SI64,
28106 IX86_BUILTIN_CVTPS2DQ,
28107 IX86_BUILTIN_CVTPS2PD,
28108 IX86_BUILTIN_CVTTPS2DQ,
28110 IX86_BUILTIN_MOVNTI,
28111 IX86_BUILTIN_MOVNTI64,
28112 IX86_BUILTIN_MOVNTPD,
28113 IX86_BUILTIN_MOVNTDQ,
28115 IX86_BUILTIN_MOVQ128,
28117 /* SSE2 MMX */
28118 IX86_BUILTIN_MASKMOVDQU,
28119 IX86_BUILTIN_MOVMSKPD,
28120 IX86_BUILTIN_PMOVMSKB128,
28122 IX86_BUILTIN_PACKSSWB128,
28123 IX86_BUILTIN_PACKSSDW128,
28124 IX86_BUILTIN_PACKUSWB128,
28126 IX86_BUILTIN_PADDB128,
28127 IX86_BUILTIN_PADDW128,
28128 IX86_BUILTIN_PADDD128,
28129 IX86_BUILTIN_PADDQ128,
28130 IX86_BUILTIN_PADDSB128,
28131 IX86_BUILTIN_PADDSW128,
28132 IX86_BUILTIN_PADDUSB128,
28133 IX86_BUILTIN_PADDUSW128,
28134 IX86_BUILTIN_PSUBB128,
28135 IX86_BUILTIN_PSUBW128,
28136 IX86_BUILTIN_PSUBD128,
28137 IX86_BUILTIN_PSUBQ128,
28138 IX86_BUILTIN_PSUBSB128,
28139 IX86_BUILTIN_PSUBSW128,
28140 IX86_BUILTIN_PSUBUSB128,
28141 IX86_BUILTIN_PSUBUSW128,
28143 IX86_BUILTIN_PAND128,
28144 IX86_BUILTIN_PANDN128,
28145 IX86_BUILTIN_POR128,
28146 IX86_BUILTIN_PXOR128,
28148 IX86_BUILTIN_PAVGB128,
28149 IX86_BUILTIN_PAVGW128,
28151 IX86_BUILTIN_PCMPEQB128,
28152 IX86_BUILTIN_PCMPEQW128,
28153 IX86_BUILTIN_PCMPEQD128,
28154 IX86_BUILTIN_PCMPGTB128,
28155 IX86_BUILTIN_PCMPGTW128,
28156 IX86_BUILTIN_PCMPGTD128,
28158 IX86_BUILTIN_PMADDWD128,
28160 IX86_BUILTIN_PMAXSW128,
28161 IX86_BUILTIN_PMAXUB128,
28162 IX86_BUILTIN_PMINSW128,
28163 IX86_BUILTIN_PMINUB128,
28165 IX86_BUILTIN_PMULUDQ,
28166 IX86_BUILTIN_PMULUDQ128,
28167 IX86_BUILTIN_PMULHUW128,
28168 IX86_BUILTIN_PMULHW128,
28169 IX86_BUILTIN_PMULLW128,
28171 IX86_BUILTIN_PSADBW128,
28172 IX86_BUILTIN_PSHUFHW,
28173 IX86_BUILTIN_PSHUFLW,
28174 IX86_BUILTIN_PSHUFD,
28176 IX86_BUILTIN_PSLLDQI128,
28177 IX86_BUILTIN_PSLLWI128,
28178 IX86_BUILTIN_PSLLDI128,
28179 IX86_BUILTIN_PSLLQI128,
28180 IX86_BUILTIN_PSRAWI128,
28181 IX86_BUILTIN_PSRADI128,
28182 IX86_BUILTIN_PSRLDQI128,
28183 IX86_BUILTIN_PSRLWI128,
28184 IX86_BUILTIN_PSRLDI128,
28185 IX86_BUILTIN_PSRLQI128,
28187 IX86_BUILTIN_PSLLDQ128,
28188 IX86_BUILTIN_PSLLW128,
28189 IX86_BUILTIN_PSLLD128,
28190 IX86_BUILTIN_PSLLQ128,
28191 IX86_BUILTIN_PSRAW128,
28192 IX86_BUILTIN_PSRAD128,
28193 IX86_BUILTIN_PSRLW128,
28194 IX86_BUILTIN_PSRLD128,
28195 IX86_BUILTIN_PSRLQ128,
28197 IX86_BUILTIN_PUNPCKHBW128,
28198 IX86_BUILTIN_PUNPCKHWD128,
28199 IX86_BUILTIN_PUNPCKHDQ128,
28200 IX86_BUILTIN_PUNPCKHQDQ128,
28201 IX86_BUILTIN_PUNPCKLBW128,
28202 IX86_BUILTIN_PUNPCKLWD128,
28203 IX86_BUILTIN_PUNPCKLDQ128,
28204 IX86_BUILTIN_PUNPCKLQDQ128,
28206 IX86_BUILTIN_CLFLUSH,
28207 IX86_BUILTIN_MFENCE,
28208 IX86_BUILTIN_LFENCE,
28209 IX86_BUILTIN_PAUSE,
28211 IX86_BUILTIN_FNSTENV,
28212 IX86_BUILTIN_FLDENV,
28213 IX86_BUILTIN_FNSTSW,
28214 IX86_BUILTIN_FNCLEX,
28216 IX86_BUILTIN_BSRSI,
28217 IX86_BUILTIN_BSRDI,
28218 IX86_BUILTIN_RDPMC,
28219 IX86_BUILTIN_RDTSC,
28220 IX86_BUILTIN_RDTSCP,
28221 IX86_BUILTIN_ROLQI,
28222 IX86_BUILTIN_ROLHI,
28223 IX86_BUILTIN_RORQI,
28224 IX86_BUILTIN_RORHI,
28226 /* SSE3. */
28227 IX86_BUILTIN_ADDSUBPS,
28228 IX86_BUILTIN_HADDPS,
28229 IX86_BUILTIN_HSUBPS,
28230 IX86_BUILTIN_MOVSHDUP,
28231 IX86_BUILTIN_MOVSLDUP,
28232 IX86_BUILTIN_ADDSUBPD,
28233 IX86_BUILTIN_HADDPD,
28234 IX86_BUILTIN_HSUBPD,
28235 IX86_BUILTIN_LDDQU,
28237 IX86_BUILTIN_MONITOR,
28238 IX86_BUILTIN_MWAIT,
28240 /* SSSE3. */
28241 IX86_BUILTIN_PHADDW,
28242 IX86_BUILTIN_PHADDD,
28243 IX86_BUILTIN_PHADDSW,
28244 IX86_BUILTIN_PHSUBW,
28245 IX86_BUILTIN_PHSUBD,
28246 IX86_BUILTIN_PHSUBSW,
28247 IX86_BUILTIN_PMADDUBSW,
28248 IX86_BUILTIN_PMULHRSW,
28249 IX86_BUILTIN_PSHUFB,
28250 IX86_BUILTIN_PSIGNB,
28251 IX86_BUILTIN_PSIGNW,
28252 IX86_BUILTIN_PSIGND,
28253 IX86_BUILTIN_PALIGNR,
28254 IX86_BUILTIN_PABSB,
28255 IX86_BUILTIN_PABSW,
28256 IX86_BUILTIN_PABSD,
28258 IX86_BUILTIN_PHADDW128,
28259 IX86_BUILTIN_PHADDD128,
28260 IX86_BUILTIN_PHADDSW128,
28261 IX86_BUILTIN_PHSUBW128,
28262 IX86_BUILTIN_PHSUBD128,
28263 IX86_BUILTIN_PHSUBSW128,
28264 IX86_BUILTIN_PMADDUBSW128,
28265 IX86_BUILTIN_PMULHRSW128,
28266 IX86_BUILTIN_PSHUFB128,
28267 IX86_BUILTIN_PSIGNB128,
28268 IX86_BUILTIN_PSIGNW128,
28269 IX86_BUILTIN_PSIGND128,
28270 IX86_BUILTIN_PALIGNR128,
28271 IX86_BUILTIN_PABSB128,
28272 IX86_BUILTIN_PABSW128,
28273 IX86_BUILTIN_PABSD128,
28275 /* AMDFAM10 - SSE4A New Instructions. */
28276 IX86_BUILTIN_MOVNTSD,
28277 IX86_BUILTIN_MOVNTSS,
28278 IX86_BUILTIN_EXTRQI,
28279 IX86_BUILTIN_EXTRQ,
28280 IX86_BUILTIN_INSERTQI,
28281 IX86_BUILTIN_INSERTQ,
28283 /* SSE4.1. */
28284 IX86_BUILTIN_BLENDPD,
28285 IX86_BUILTIN_BLENDPS,
28286 IX86_BUILTIN_BLENDVPD,
28287 IX86_BUILTIN_BLENDVPS,
28288 IX86_BUILTIN_PBLENDVB128,
28289 IX86_BUILTIN_PBLENDW128,
28291 IX86_BUILTIN_DPPD,
28292 IX86_BUILTIN_DPPS,
28294 IX86_BUILTIN_INSERTPS128,
28296 IX86_BUILTIN_MOVNTDQA,
28297 IX86_BUILTIN_MPSADBW128,
28298 IX86_BUILTIN_PACKUSDW128,
28299 IX86_BUILTIN_PCMPEQQ,
28300 IX86_BUILTIN_PHMINPOSUW128,
28302 IX86_BUILTIN_PMAXSB128,
28303 IX86_BUILTIN_PMAXSD128,
28304 IX86_BUILTIN_PMAXUD128,
28305 IX86_BUILTIN_PMAXUW128,
28307 IX86_BUILTIN_PMINSB128,
28308 IX86_BUILTIN_PMINSD128,
28309 IX86_BUILTIN_PMINUD128,
28310 IX86_BUILTIN_PMINUW128,
28312 IX86_BUILTIN_PMOVSXBW128,
28313 IX86_BUILTIN_PMOVSXBD128,
28314 IX86_BUILTIN_PMOVSXBQ128,
28315 IX86_BUILTIN_PMOVSXWD128,
28316 IX86_BUILTIN_PMOVSXWQ128,
28317 IX86_BUILTIN_PMOVSXDQ128,
28319 IX86_BUILTIN_PMOVZXBW128,
28320 IX86_BUILTIN_PMOVZXBD128,
28321 IX86_BUILTIN_PMOVZXBQ128,
28322 IX86_BUILTIN_PMOVZXWD128,
28323 IX86_BUILTIN_PMOVZXWQ128,
28324 IX86_BUILTIN_PMOVZXDQ128,
28326 IX86_BUILTIN_PMULDQ128,
28327 IX86_BUILTIN_PMULLD128,
28329 IX86_BUILTIN_ROUNDSD,
28330 IX86_BUILTIN_ROUNDSS,
28332 IX86_BUILTIN_ROUNDPD,
28333 IX86_BUILTIN_ROUNDPS,
28335 IX86_BUILTIN_FLOORPD,
28336 IX86_BUILTIN_CEILPD,
28337 IX86_BUILTIN_TRUNCPD,
28338 IX86_BUILTIN_RINTPD,
28339 IX86_BUILTIN_ROUNDPD_AZ,
28341 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28342 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28343 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28345 IX86_BUILTIN_FLOORPS,
28346 IX86_BUILTIN_CEILPS,
28347 IX86_BUILTIN_TRUNCPS,
28348 IX86_BUILTIN_RINTPS,
28349 IX86_BUILTIN_ROUNDPS_AZ,
28351 IX86_BUILTIN_FLOORPS_SFIX,
28352 IX86_BUILTIN_CEILPS_SFIX,
28353 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28355 IX86_BUILTIN_PTESTZ,
28356 IX86_BUILTIN_PTESTC,
28357 IX86_BUILTIN_PTESTNZC,
28359 IX86_BUILTIN_VEC_INIT_V2SI,
28360 IX86_BUILTIN_VEC_INIT_V4HI,
28361 IX86_BUILTIN_VEC_INIT_V8QI,
28362 IX86_BUILTIN_VEC_EXT_V2DF,
28363 IX86_BUILTIN_VEC_EXT_V2DI,
28364 IX86_BUILTIN_VEC_EXT_V4SF,
28365 IX86_BUILTIN_VEC_EXT_V4SI,
28366 IX86_BUILTIN_VEC_EXT_V8HI,
28367 IX86_BUILTIN_VEC_EXT_V2SI,
28368 IX86_BUILTIN_VEC_EXT_V4HI,
28369 IX86_BUILTIN_VEC_EXT_V16QI,
28370 IX86_BUILTIN_VEC_SET_V2DI,
28371 IX86_BUILTIN_VEC_SET_V4SF,
28372 IX86_BUILTIN_VEC_SET_V4SI,
28373 IX86_BUILTIN_VEC_SET_V8HI,
28374 IX86_BUILTIN_VEC_SET_V4HI,
28375 IX86_BUILTIN_VEC_SET_V16QI,
28377 IX86_BUILTIN_VEC_PACK_SFIX,
28378 IX86_BUILTIN_VEC_PACK_SFIX256,
28380 /* SSE4.2. */
28381 IX86_BUILTIN_CRC32QI,
28382 IX86_BUILTIN_CRC32HI,
28383 IX86_BUILTIN_CRC32SI,
28384 IX86_BUILTIN_CRC32DI,
28386 IX86_BUILTIN_PCMPESTRI128,
28387 IX86_BUILTIN_PCMPESTRM128,
28388 IX86_BUILTIN_PCMPESTRA128,
28389 IX86_BUILTIN_PCMPESTRC128,
28390 IX86_BUILTIN_PCMPESTRO128,
28391 IX86_BUILTIN_PCMPESTRS128,
28392 IX86_BUILTIN_PCMPESTRZ128,
28393 IX86_BUILTIN_PCMPISTRI128,
28394 IX86_BUILTIN_PCMPISTRM128,
28395 IX86_BUILTIN_PCMPISTRA128,
28396 IX86_BUILTIN_PCMPISTRC128,
28397 IX86_BUILTIN_PCMPISTRO128,
28398 IX86_BUILTIN_PCMPISTRS128,
28399 IX86_BUILTIN_PCMPISTRZ128,
28401 IX86_BUILTIN_PCMPGTQ,
28403 /* AES instructions */
28404 IX86_BUILTIN_AESENC128,
28405 IX86_BUILTIN_AESENCLAST128,
28406 IX86_BUILTIN_AESDEC128,
28407 IX86_BUILTIN_AESDECLAST128,
28408 IX86_BUILTIN_AESIMC128,
28409 IX86_BUILTIN_AESKEYGENASSIST128,
28411 /* PCLMUL instruction */
28412 IX86_BUILTIN_PCLMULQDQ128,
28414 /* AVX */
28415 IX86_BUILTIN_ADDPD256,
28416 IX86_BUILTIN_ADDPS256,
28417 IX86_BUILTIN_ADDSUBPD256,
28418 IX86_BUILTIN_ADDSUBPS256,
28419 IX86_BUILTIN_ANDPD256,
28420 IX86_BUILTIN_ANDPS256,
28421 IX86_BUILTIN_ANDNPD256,
28422 IX86_BUILTIN_ANDNPS256,
28423 IX86_BUILTIN_BLENDPD256,
28424 IX86_BUILTIN_BLENDPS256,
28425 IX86_BUILTIN_BLENDVPD256,
28426 IX86_BUILTIN_BLENDVPS256,
28427 IX86_BUILTIN_DIVPD256,
28428 IX86_BUILTIN_DIVPS256,
28429 IX86_BUILTIN_DPPS256,
28430 IX86_BUILTIN_HADDPD256,
28431 IX86_BUILTIN_HADDPS256,
28432 IX86_BUILTIN_HSUBPD256,
28433 IX86_BUILTIN_HSUBPS256,
28434 IX86_BUILTIN_MAXPD256,
28435 IX86_BUILTIN_MAXPS256,
28436 IX86_BUILTIN_MINPD256,
28437 IX86_BUILTIN_MINPS256,
28438 IX86_BUILTIN_MULPD256,
28439 IX86_BUILTIN_MULPS256,
28440 IX86_BUILTIN_ORPD256,
28441 IX86_BUILTIN_ORPS256,
28442 IX86_BUILTIN_SHUFPD256,
28443 IX86_BUILTIN_SHUFPS256,
28444 IX86_BUILTIN_SUBPD256,
28445 IX86_BUILTIN_SUBPS256,
28446 IX86_BUILTIN_XORPD256,
28447 IX86_BUILTIN_XORPS256,
28448 IX86_BUILTIN_CMPSD,
28449 IX86_BUILTIN_CMPSS,
28450 IX86_BUILTIN_CMPPD,
28451 IX86_BUILTIN_CMPPS,
28452 IX86_BUILTIN_CMPPD256,
28453 IX86_BUILTIN_CMPPS256,
28454 IX86_BUILTIN_CVTDQ2PD256,
28455 IX86_BUILTIN_CVTDQ2PS256,
28456 IX86_BUILTIN_CVTPD2PS256,
28457 IX86_BUILTIN_CVTPS2DQ256,
28458 IX86_BUILTIN_CVTPS2PD256,
28459 IX86_BUILTIN_CVTTPD2DQ256,
28460 IX86_BUILTIN_CVTPD2DQ256,
28461 IX86_BUILTIN_CVTTPS2DQ256,
28462 IX86_BUILTIN_EXTRACTF128PD256,
28463 IX86_BUILTIN_EXTRACTF128PS256,
28464 IX86_BUILTIN_EXTRACTF128SI256,
28465 IX86_BUILTIN_VZEROALL,
28466 IX86_BUILTIN_VZEROUPPER,
28467 IX86_BUILTIN_VPERMILVARPD,
28468 IX86_BUILTIN_VPERMILVARPS,
28469 IX86_BUILTIN_VPERMILVARPD256,
28470 IX86_BUILTIN_VPERMILVARPS256,
28471 IX86_BUILTIN_VPERMILPD,
28472 IX86_BUILTIN_VPERMILPS,
28473 IX86_BUILTIN_VPERMILPD256,
28474 IX86_BUILTIN_VPERMILPS256,
28475 IX86_BUILTIN_VPERMIL2PD,
28476 IX86_BUILTIN_VPERMIL2PS,
28477 IX86_BUILTIN_VPERMIL2PD256,
28478 IX86_BUILTIN_VPERMIL2PS256,
28479 IX86_BUILTIN_VPERM2F128PD256,
28480 IX86_BUILTIN_VPERM2F128PS256,
28481 IX86_BUILTIN_VPERM2F128SI256,
28482 IX86_BUILTIN_VBROADCASTSS,
28483 IX86_BUILTIN_VBROADCASTSD256,
28484 IX86_BUILTIN_VBROADCASTSS256,
28485 IX86_BUILTIN_VBROADCASTPD256,
28486 IX86_BUILTIN_VBROADCASTPS256,
28487 IX86_BUILTIN_VINSERTF128PD256,
28488 IX86_BUILTIN_VINSERTF128PS256,
28489 IX86_BUILTIN_VINSERTF128SI256,
28490 IX86_BUILTIN_LOADUPD256,
28491 IX86_BUILTIN_LOADUPS256,
28492 IX86_BUILTIN_STOREUPD256,
28493 IX86_BUILTIN_STOREUPS256,
28494 IX86_BUILTIN_LDDQU256,
28495 IX86_BUILTIN_MOVNTDQ256,
28496 IX86_BUILTIN_MOVNTPD256,
28497 IX86_BUILTIN_MOVNTPS256,
28498 IX86_BUILTIN_LOADDQU256,
28499 IX86_BUILTIN_STOREDQU256,
28500 IX86_BUILTIN_MASKLOADPD,
28501 IX86_BUILTIN_MASKLOADPS,
28502 IX86_BUILTIN_MASKSTOREPD,
28503 IX86_BUILTIN_MASKSTOREPS,
28504 IX86_BUILTIN_MASKLOADPD256,
28505 IX86_BUILTIN_MASKLOADPS256,
28506 IX86_BUILTIN_MASKSTOREPD256,
28507 IX86_BUILTIN_MASKSTOREPS256,
28508 IX86_BUILTIN_MOVSHDUP256,
28509 IX86_BUILTIN_MOVSLDUP256,
28510 IX86_BUILTIN_MOVDDUP256,
28512 IX86_BUILTIN_SQRTPD256,
28513 IX86_BUILTIN_SQRTPS256,
28514 IX86_BUILTIN_SQRTPS_NR256,
28515 IX86_BUILTIN_RSQRTPS256,
28516 IX86_BUILTIN_RSQRTPS_NR256,
28518 IX86_BUILTIN_RCPPS256,
28520 IX86_BUILTIN_ROUNDPD256,
28521 IX86_BUILTIN_ROUNDPS256,
28523 IX86_BUILTIN_FLOORPD256,
28524 IX86_BUILTIN_CEILPD256,
28525 IX86_BUILTIN_TRUNCPD256,
28526 IX86_BUILTIN_RINTPD256,
28527 IX86_BUILTIN_ROUNDPD_AZ256,
28529 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28530 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28531 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28533 IX86_BUILTIN_FLOORPS256,
28534 IX86_BUILTIN_CEILPS256,
28535 IX86_BUILTIN_TRUNCPS256,
28536 IX86_BUILTIN_RINTPS256,
28537 IX86_BUILTIN_ROUNDPS_AZ256,
28539 IX86_BUILTIN_FLOORPS_SFIX256,
28540 IX86_BUILTIN_CEILPS_SFIX256,
28541 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28543 IX86_BUILTIN_UNPCKHPD256,
28544 IX86_BUILTIN_UNPCKLPD256,
28545 IX86_BUILTIN_UNPCKHPS256,
28546 IX86_BUILTIN_UNPCKLPS256,
28548 IX86_BUILTIN_SI256_SI,
28549 IX86_BUILTIN_PS256_PS,
28550 IX86_BUILTIN_PD256_PD,
28551 IX86_BUILTIN_SI_SI256,
28552 IX86_BUILTIN_PS_PS256,
28553 IX86_BUILTIN_PD_PD256,
28555 IX86_BUILTIN_VTESTZPD,
28556 IX86_BUILTIN_VTESTCPD,
28557 IX86_BUILTIN_VTESTNZCPD,
28558 IX86_BUILTIN_VTESTZPS,
28559 IX86_BUILTIN_VTESTCPS,
28560 IX86_BUILTIN_VTESTNZCPS,
28561 IX86_BUILTIN_VTESTZPD256,
28562 IX86_BUILTIN_VTESTCPD256,
28563 IX86_BUILTIN_VTESTNZCPD256,
28564 IX86_BUILTIN_VTESTZPS256,
28565 IX86_BUILTIN_VTESTCPS256,
28566 IX86_BUILTIN_VTESTNZCPS256,
28567 IX86_BUILTIN_PTESTZ256,
28568 IX86_BUILTIN_PTESTC256,
28569 IX86_BUILTIN_PTESTNZC256,
28571 IX86_BUILTIN_MOVMSKPD256,
28572 IX86_BUILTIN_MOVMSKPS256,
28574 /* AVX2 */
28575 IX86_BUILTIN_MPSADBW256,
28576 IX86_BUILTIN_PABSB256,
28577 IX86_BUILTIN_PABSW256,
28578 IX86_BUILTIN_PABSD256,
28579 IX86_BUILTIN_PACKSSDW256,
28580 IX86_BUILTIN_PACKSSWB256,
28581 IX86_BUILTIN_PACKUSDW256,
28582 IX86_BUILTIN_PACKUSWB256,
28583 IX86_BUILTIN_PADDB256,
28584 IX86_BUILTIN_PADDW256,
28585 IX86_BUILTIN_PADDD256,
28586 IX86_BUILTIN_PADDQ256,
28587 IX86_BUILTIN_PADDSB256,
28588 IX86_BUILTIN_PADDSW256,
28589 IX86_BUILTIN_PADDUSB256,
28590 IX86_BUILTIN_PADDUSW256,
28591 IX86_BUILTIN_PALIGNR256,
28592 IX86_BUILTIN_AND256I,
28593 IX86_BUILTIN_ANDNOT256I,
28594 IX86_BUILTIN_PAVGB256,
28595 IX86_BUILTIN_PAVGW256,
28596 IX86_BUILTIN_PBLENDVB256,
28597 IX86_BUILTIN_PBLENDVW256,
28598 IX86_BUILTIN_PCMPEQB256,
28599 IX86_BUILTIN_PCMPEQW256,
28600 IX86_BUILTIN_PCMPEQD256,
28601 IX86_BUILTIN_PCMPEQQ256,
28602 IX86_BUILTIN_PCMPGTB256,
28603 IX86_BUILTIN_PCMPGTW256,
28604 IX86_BUILTIN_PCMPGTD256,
28605 IX86_BUILTIN_PCMPGTQ256,
28606 IX86_BUILTIN_PHADDW256,
28607 IX86_BUILTIN_PHADDD256,
28608 IX86_BUILTIN_PHADDSW256,
28609 IX86_BUILTIN_PHSUBW256,
28610 IX86_BUILTIN_PHSUBD256,
28611 IX86_BUILTIN_PHSUBSW256,
28612 IX86_BUILTIN_PMADDUBSW256,
28613 IX86_BUILTIN_PMADDWD256,
28614 IX86_BUILTIN_PMAXSB256,
28615 IX86_BUILTIN_PMAXSW256,
28616 IX86_BUILTIN_PMAXSD256,
28617 IX86_BUILTIN_PMAXUB256,
28618 IX86_BUILTIN_PMAXUW256,
28619 IX86_BUILTIN_PMAXUD256,
28620 IX86_BUILTIN_PMINSB256,
28621 IX86_BUILTIN_PMINSW256,
28622 IX86_BUILTIN_PMINSD256,
28623 IX86_BUILTIN_PMINUB256,
28624 IX86_BUILTIN_PMINUW256,
28625 IX86_BUILTIN_PMINUD256,
28626 IX86_BUILTIN_PMOVMSKB256,
28627 IX86_BUILTIN_PMOVSXBW256,
28628 IX86_BUILTIN_PMOVSXBD256,
28629 IX86_BUILTIN_PMOVSXBQ256,
28630 IX86_BUILTIN_PMOVSXWD256,
28631 IX86_BUILTIN_PMOVSXWQ256,
28632 IX86_BUILTIN_PMOVSXDQ256,
28633 IX86_BUILTIN_PMOVZXBW256,
28634 IX86_BUILTIN_PMOVZXBD256,
28635 IX86_BUILTIN_PMOVZXBQ256,
28636 IX86_BUILTIN_PMOVZXWD256,
28637 IX86_BUILTIN_PMOVZXWQ256,
28638 IX86_BUILTIN_PMOVZXDQ256,
28639 IX86_BUILTIN_PMULDQ256,
28640 IX86_BUILTIN_PMULHRSW256,
28641 IX86_BUILTIN_PMULHUW256,
28642 IX86_BUILTIN_PMULHW256,
28643 IX86_BUILTIN_PMULLW256,
28644 IX86_BUILTIN_PMULLD256,
28645 IX86_BUILTIN_PMULUDQ256,
28646 IX86_BUILTIN_POR256,
28647 IX86_BUILTIN_PSADBW256,
28648 IX86_BUILTIN_PSHUFB256,
28649 IX86_BUILTIN_PSHUFD256,
28650 IX86_BUILTIN_PSHUFHW256,
28651 IX86_BUILTIN_PSHUFLW256,
28652 IX86_BUILTIN_PSIGNB256,
28653 IX86_BUILTIN_PSIGNW256,
28654 IX86_BUILTIN_PSIGND256,
28655 IX86_BUILTIN_PSLLDQI256,
28656 IX86_BUILTIN_PSLLWI256,
28657 IX86_BUILTIN_PSLLW256,
28658 IX86_BUILTIN_PSLLDI256,
28659 IX86_BUILTIN_PSLLD256,
28660 IX86_BUILTIN_PSLLQI256,
28661 IX86_BUILTIN_PSLLQ256,
28662 IX86_BUILTIN_PSRAWI256,
28663 IX86_BUILTIN_PSRAW256,
28664 IX86_BUILTIN_PSRADI256,
28665 IX86_BUILTIN_PSRAD256,
28666 IX86_BUILTIN_PSRLDQI256,
28667 IX86_BUILTIN_PSRLWI256,
28668 IX86_BUILTIN_PSRLW256,
28669 IX86_BUILTIN_PSRLDI256,
28670 IX86_BUILTIN_PSRLD256,
28671 IX86_BUILTIN_PSRLQI256,
28672 IX86_BUILTIN_PSRLQ256,
28673 IX86_BUILTIN_PSUBB256,
28674 IX86_BUILTIN_PSUBW256,
28675 IX86_BUILTIN_PSUBD256,
28676 IX86_BUILTIN_PSUBQ256,
28677 IX86_BUILTIN_PSUBSB256,
28678 IX86_BUILTIN_PSUBSW256,
28679 IX86_BUILTIN_PSUBUSB256,
28680 IX86_BUILTIN_PSUBUSW256,
28681 IX86_BUILTIN_PUNPCKHBW256,
28682 IX86_BUILTIN_PUNPCKHWD256,
28683 IX86_BUILTIN_PUNPCKHDQ256,
28684 IX86_BUILTIN_PUNPCKHQDQ256,
28685 IX86_BUILTIN_PUNPCKLBW256,
28686 IX86_BUILTIN_PUNPCKLWD256,
28687 IX86_BUILTIN_PUNPCKLDQ256,
28688 IX86_BUILTIN_PUNPCKLQDQ256,
28689 IX86_BUILTIN_PXOR256,
28690 IX86_BUILTIN_MOVNTDQA256,
28691 IX86_BUILTIN_VBROADCASTSS_PS,
28692 IX86_BUILTIN_VBROADCASTSS_PS256,
28693 IX86_BUILTIN_VBROADCASTSD_PD256,
28694 IX86_BUILTIN_VBROADCASTSI256,
28695 IX86_BUILTIN_PBLENDD256,
28696 IX86_BUILTIN_PBLENDD128,
28697 IX86_BUILTIN_PBROADCASTB256,
28698 IX86_BUILTIN_PBROADCASTW256,
28699 IX86_BUILTIN_PBROADCASTD256,
28700 IX86_BUILTIN_PBROADCASTQ256,
28701 IX86_BUILTIN_PBROADCASTB128,
28702 IX86_BUILTIN_PBROADCASTW128,
28703 IX86_BUILTIN_PBROADCASTD128,
28704 IX86_BUILTIN_PBROADCASTQ128,
28705 IX86_BUILTIN_VPERMVARSI256,
28706 IX86_BUILTIN_VPERMDF256,
28707 IX86_BUILTIN_VPERMVARSF256,
28708 IX86_BUILTIN_VPERMDI256,
28709 IX86_BUILTIN_VPERMTI256,
28710 IX86_BUILTIN_VEXTRACT128I256,
28711 IX86_BUILTIN_VINSERT128I256,
28712 IX86_BUILTIN_MASKLOADD,
28713 IX86_BUILTIN_MASKLOADQ,
28714 IX86_BUILTIN_MASKLOADD256,
28715 IX86_BUILTIN_MASKLOADQ256,
28716 IX86_BUILTIN_MASKSTORED,
28717 IX86_BUILTIN_MASKSTOREQ,
28718 IX86_BUILTIN_MASKSTORED256,
28719 IX86_BUILTIN_MASKSTOREQ256,
28720 IX86_BUILTIN_PSLLVV4DI,
28721 IX86_BUILTIN_PSLLVV2DI,
28722 IX86_BUILTIN_PSLLVV8SI,
28723 IX86_BUILTIN_PSLLVV4SI,
28724 IX86_BUILTIN_PSRAVV8SI,
28725 IX86_BUILTIN_PSRAVV4SI,
28726 IX86_BUILTIN_PSRLVV4DI,
28727 IX86_BUILTIN_PSRLVV2DI,
28728 IX86_BUILTIN_PSRLVV8SI,
28729 IX86_BUILTIN_PSRLVV4SI,
28731 IX86_BUILTIN_GATHERSIV2DF,
28732 IX86_BUILTIN_GATHERSIV4DF,
28733 IX86_BUILTIN_GATHERDIV2DF,
28734 IX86_BUILTIN_GATHERDIV4DF,
28735 IX86_BUILTIN_GATHERSIV4SF,
28736 IX86_BUILTIN_GATHERSIV8SF,
28737 IX86_BUILTIN_GATHERDIV4SF,
28738 IX86_BUILTIN_GATHERDIV8SF,
28739 IX86_BUILTIN_GATHERSIV2DI,
28740 IX86_BUILTIN_GATHERSIV4DI,
28741 IX86_BUILTIN_GATHERDIV2DI,
28742 IX86_BUILTIN_GATHERDIV4DI,
28743 IX86_BUILTIN_GATHERSIV4SI,
28744 IX86_BUILTIN_GATHERSIV8SI,
28745 IX86_BUILTIN_GATHERDIV4SI,
28746 IX86_BUILTIN_GATHERDIV8SI,
28748 /* AVX512F */
28749 IX86_BUILTIN_SI512_SI256,
28750 IX86_BUILTIN_PD512_PD256,
28751 IX86_BUILTIN_PS512_PS256,
28752 IX86_BUILTIN_SI512_SI,
28753 IX86_BUILTIN_PD512_PD,
28754 IX86_BUILTIN_PS512_PS,
28755 IX86_BUILTIN_ADDPD512,
28756 IX86_BUILTIN_ADDPS512,
28757 IX86_BUILTIN_ADDSD_ROUND,
28758 IX86_BUILTIN_ADDSS_ROUND,
28759 IX86_BUILTIN_ALIGND512,
28760 IX86_BUILTIN_ALIGNQ512,
28761 IX86_BUILTIN_BLENDMD512,
28762 IX86_BUILTIN_BLENDMPD512,
28763 IX86_BUILTIN_BLENDMPS512,
28764 IX86_BUILTIN_BLENDMQ512,
28765 IX86_BUILTIN_BROADCASTF32X4_512,
28766 IX86_BUILTIN_BROADCASTF64X4_512,
28767 IX86_BUILTIN_BROADCASTI32X4_512,
28768 IX86_BUILTIN_BROADCASTI64X4_512,
28769 IX86_BUILTIN_BROADCASTSD512,
28770 IX86_BUILTIN_BROADCASTSS512,
28771 IX86_BUILTIN_CMPD512,
28772 IX86_BUILTIN_CMPPD512,
28773 IX86_BUILTIN_CMPPS512,
28774 IX86_BUILTIN_CMPQ512,
28775 IX86_BUILTIN_CMPSD_MASK,
28776 IX86_BUILTIN_CMPSS_MASK,
28777 IX86_BUILTIN_COMIDF,
28778 IX86_BUILTIN_COMISF,
28779 IX86_BUILTIN_COMPRESSPD512,
28780 IX86_BUILTIN_COMPRESSPDSTORE512,
28781 IX86_BUILTIN_COMPRESSPS512,
28782 IX86_BUILTIN_COMPRESSPSSTORE512,
28783 IX86_BUILTIN_CVTDQ2PD512,
28784 IX86_BUILTIN_CVTDQ2PS512,
28785 IX86_BUILTIN_CVTPD2DQ512,
28786 IX86_BUILTIN_CVTPD2PS512,
28787 IX86_BUILTIN_CVTPD2UDQ512,
28788 IX86_BUILTIN_CVTPH2PS512,
28789 IX86_BUILTIN_CVTPS2DQ512,
28790 IX86_BUILTIN_CVTPS2PD512,
28791 IX86_BUILTIN_CVTPS2PH512,
28792 IX86_BUILTIN_CVTPS2UDQ512,
28793 IX86_BUILTIN_CVTSD2SS_ROUND,
28794 IX86_BUILTIN_CVTSI2SD64,
28795 IX86_BUILTIN_CVTSI2SS32,
28796 IX86_BUILTIN_CVTSI2SS64,
28797 IX86_BUILTIN_CVTSS2SD_ROUND,
28798 IX86_BUILTIN_CVTTPD2DQ512,
28799 IX86_BUILTIN_CVTTPD2UDQ512,
28800 IX86_BUILTIN_CVTTPS2DQ512,
28801 IX86_BUILTIN_CVTTPS2UDQ512,
28802 IX86_BUILTIN_CVTUDQ2PD512,
28803 IX86_BUILTIN_CVTUDQ2PS512,
28804 IX86_BUILTIN_CVTUSI2SD32,
28805 IX86_BUILTIN_CVTUSI2SD64,
28806 IX86_BUILTIN_CVTUSI2SS32,
28807 IX86_BUILTIN_CVTUSI2SS64,
28808 IX86_BUILTIN_DIVPD512,
28809 IX86_BUILTIN_DIVPS512,
28810 IX86_BUILTIN_DIVSD_ROUND,
28811 IX86_BUILTIN_DIVSS_ROUND,
28812 IX86_BUILTIN_EXPANDPD512,
28813 IX86_BUILTIN_EXPANDPD512Z,
28814 IX86_BUILTIN_EXPANDPDLOAD512,
28815 IX86_BUILTIN_EXPANDPDLOAD512Z,
28816 IX86_BUILTIN_EXPANDPS512,
28817 IX86_BUILTIN_EXPANDPS512Z,
28818 IX86_BUILTIN_EXPANDPSLOAD512,
28819 IX86_BUILTIN_EXPANDPSLOAD512Z,
28820 IX86_BUILTIN_EXTRACTF32X4,
28821 IX86_BUILTIN_EXTRACTF64X4,
28822 IX86_BUILTIN_EXTRACTI32X4,
28823 IX86_BUILTIN_EXTRACTI64X4,
28824 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28825 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28826 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28827 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28828 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28829 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28830 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28831 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28832 IX86_BUILTIN_GETEXPPD512,
28833 IX86_BUILTIN_GETEXPPS512,
28834 IX86_BUILTIN_GETEXPSD128,
28835 IX86_BUILTIN_GETEXPSS128,
28836 IX86_BUILTIN_GETMANTPD512,
28837 IX86_BUILTIN_GETMANTPS512,
28838 IX86_BUILTIN_GETMANTSD128,
28839 IX86_BUILTIN_GETMANTSS128,
28840 IX86_BUILTIN_INSERTF32X4,
28841 IX86_BUILTIN_INSERTF64X4,
28842 IX86_BUILTIN_INSERTI32X4,
28843 IX86_BUILTIN_INSERTI64X4,
28844 IX86_BUILTIN_LOADAPD512,
28845 IX86_BUILTIN_LOADAPS512,
28846 IX86_BUILTIN_LOADDQUDI512,
28847 IX86_BUILTIN_LOADDQUSI512,
28848 IX86_BUILTIN_LOADUPD512,
28849 IX86_BUILTIN_LOADUPS512,
28850 IX86_BUILTIN_MAXPD512,
28851 IX86_BUILTIN_MAXPS512,
28852 IX86_BUILTIN_MAXSD_ROUND,
28853 IX86_BUILTIN_MAXSS_ROUND,
28854 IX86_BUILTIN_MINPD512,
28855 IX86_BUILTIN_MINPS512,
28856 IX86_BUILTIN_MINSD_ROUND,
28857 IX86_BUILTIN_MINSS_ROUND,
28858 IX86_BUILTIN_MOVAPD512,
28859 IX86_BUILTIN_MOVAPS512,
28860 IX86_BUILTIN_MOVDDUP512,
28861 IX86_BUILTIN_MOVDQA32LOAD512,
28862 IX86_BUILTIN_MOVDQA32STORE512,
28863 IX86_BUILTIN_MOVDQA32_512,
28864 IX86_BUILTIN_MOVDQA64LOAD512,
28865 IX86_BUILTIN_MOVDQA64STORE512,
28866 IX86_BUILTIN_MOVDQA64_512,
28867 IX86_BUILTIN_MOVNTDQ512,
28868 IX86_BUILTIN_MOVNTDQA512,
28869 IX86_BUILTIN_MOVNTPD512,
28870 IX86_BUILTIN_MOVNTPS512,
28871 IX86_BUILTIN_MOVSHDUP512,
28872 IX86_BUILTIN_MOVSLDUP512,
28873 IX86_BUILTIN_MULPD512,
28874 IX86_BUILTIN_MULPS512,
28875 IX86_BUILTIN_MULSD_ROUND,
28876 IX86_BUILTIN_MULSS_ROUND,
28877 IX86_BUILTIN_PABSD512,
28878 IX86_BUILTIN_PABSQ512,
28879 IX86_BUILTIN_PADDD512,
28880 IX86_BUILTIN_PADDQ512,
28881 IX86_BUILTIN_PANDD512,
28882 IX86_BUILTIN_PANDND512,
28883 IX86_BUILTIN_PANDNQ512,
28884 IX86_BUILTIN_PANDQ512,
28885 IX86_BUILTIN_PBROADCASTD512,
28886 IX86_BUILTIN_PBROADCASTD512_GPR,
28887 IX86_BUILTIN_PBROADCASTMB512,
28888 IX86_BUILTIN_PBROADCASTMW512,
28889 IX86_BUILTIN_PBROADCASTQ512,
28890 IX86_BUILTIN_PBROADCASTQ512_GPR,
28891 IX86_BUILTIN_PCMPEQD512_MASK,
28892 IX86_BUILTIN_PCMPEQQ512_MASK,
28893 IX86_BUILTIN_PCMPGTD512_MASK,
28894 IX86_BUILTIN_PCMPGTQ512_MASK,
28895 IX86_BUILTIN_PCOMPRESSD512,
28896 IX86_BUILTIN_PCOMPRESSDSTORE512,
28897 IX86_BUILTIN_PCOMPRESSQ512,
28898 IX86_BUILTIN_PCOMPRESSQSTORE512,
28899 IX86_BUILTIN_PEXPANDD512,
28900 IX86_BUILTIN_PEXPANDD512Z,
28901 IX86_BUILTIN_PEXPANDDLOAD512,
28902 IX86_BUILTIN_PEXPANDDLOAD512Z,
28903 IX86_BUILTIN_PEXPANDQ512,
28904 IX86_BUILTIN_PEXPANDQ512Z,
28905 IX86_BUILTIN_PEXPANDQLOAD512,
28906 IX86_BUILTIN_PEXPANDQLOAD512Z,
28907 IX86_BUILTIN_PMAXSD512,
28908 IX86_BUILTIN_PMAXSQ512,
28909 IX86_BUILTIN_PMAXUD512,
28910 IX86_BUILTIN_PMAXUQ512,
28911 IX86_BUILTIN_PMINSD512,
28912 IX86_BUILTIN_PMINSQ512,
28913 IX86_BUILTIN_PMINUD512,
28914 IX86_BUILTIN_PMINUQ512,
28915 IX86_BUILTIN_PMOVDB512,
28916 IX86_BUILTIN_PMOVDB512_MEM,
28917 IX86_BUILTIN_PMOVDW512,
28918 IX86_BUILTIN_PMOVDW512_MEM,
28919 IX86_BUILTIN_PMOVQB512,
28920 IX86_BUILTIN_PMOVQB512_MEM,
28921 IX86_BUILTIN_PMOVQD512,
28922 IX86_BUILTIN_PMOVQD512_MEM,
28923 IX86_BUILTIN_PMOVQW512,
28924 IX86_BUILTIN_PMOVQW512_MEM,
28925 IX86_BUILTIN_PMOVSDB512,
28926 IX86_BUILTIN_PMOVSDB512_MEM,
28927 IX86_BUILTIN_PMOVSDW512,
28928 IX86_BUILTIN_PMOVSDW512_MEM,
28929 IX86_BUILTIN_PMOVSQB512,
28930 IX86_BUILTIN_PMOVSQB512_MEM,
28931 IX86_BUILTIN_PMOVSQD512,
28932 IX86_BUILTIN_PMOVSQD512_MEM,
28933 IX86_BUILTIN_PMOVSQW512,
28934 IX86_BUILTIN_PMOVSQW512_MEM,
28935 IX86_BUILTIN_PMOVSXBD512,
28936 IX86_BUILTIN_PMOVSXBQ512,
28937 IX86_BUILTIN_PMOVSXDQ512,
28938 IX86_BUILTIN_PMOVSXWD512,
28939 IX86_BUILTIN_PMOVSXWQ512,
28940 IX86_BUILTIN_PMOVUSDB512,
28941 IX86_BUILTIN_PMOVUSDB512_MEM,
28942 IX86_BUILTIN_PMOVUSDW512,
28943 IX86_BUILTIN_PMOVUSDW512_MEM,
28944 IX86_BUILTIN_PMOVUSQB512,
28945 IX86_BUILTIN_PMOVUSQB512_MEM,
28946 IX86_BUILTIN_PMOVUSQD512,
28947 IX86_BUILTIN_PMOVUSQD512_MEM,
28948 IX86_BUILTIN_PMOVUSQW512,
28949 IX86_BUILTIN_PMOVUSQW512_MEM,
28950 IX86_BUILTIN_PMOVZXBD512,
28951 IX86_BUILTIN_PMOVZXBQ512,
28952 IX86_BUILTIN_PMOVZXDQ512,
28953 IX86_BUILTIN_PMOVZXWD512,
28954 IX86_BUILTIN_PMOVZXWQ512,
28955 IX86_BUILTIN_PMULDQ512,
28956 IX86_BUILTIN_PMULLD512,
28957 IX86_BUILTIN_PMULUDQ512,
28958 IX86_BUILTIN_PORD512,
28959 IX86_BUILTIN_PORQ512,
28960 IX86_BUILTIN_PROLD512,
28961 IX86_BUILTIN_PROLQ512,
28962 IX86_BUILTIN_PROLVD512,
28963 IX86_BUILTIN_PROLVQ512,
28964 IX86_BUILTIN_PRORD512,
28965 IX86_BUILTIN_PRORQ512,
28966 IX86_BUILTIN_PRORVD512,
28967 IX86_BUILTIN_PRORVQ512,
28968 IX86_BUILTIN_PSHUFD512,
28969 IX86_BUILTIN_PSLLD512,
28970 IX86_BUILTIN_PSLLDI512,
28971 IX86_BUILTIN_PSLLQ512,
28972 IX86_BUILTIN_PSLLQI512,
28973 IX86_BUILTIN_PSLLVV16SI,
28974 IX86_BUILTIN_PSLLVV8DI,
28975 IX86_BUILTIN_PSRAD512,
28976 IX86_BUILTIN_PSRADI512,
28977 IX86_BUILTIN_PSRAQ512,
28978 IX86_BUILTIN_PSRAQI512,
28979 IX86_BUILTIN_PSRAVV16SI,
28980 IX86_BUILTIN_PSRAVV8DI,
28981 IX86_BUILTIN_PSRLD512,
28982 IX86_BUILTIN_PSRLDI512,
28983 IX86_BUILTIN_PSRLQ512,
28984 IX86_BUILTIN_PSRLQI512,
28985 IX86_BUILTIN_PSRLVV16SI,
28986 IX86_BUILTIN_PSRLVV8DI,
28987 IX86_BUILTIN_PSUBD512,
28988 IX86_BUILTIN_PSUBQ512,
28989 IX86_BUILTIN_PTESTMD512,
28990 IX86_BUILTIN_PTESTMQ512,
28991 IX86_BUILTIN_PTESTNMD512,
28992 IX86_BUILTIN_PTESTNMQ512,
28993 IX86_BUILTIN_PUNPCKHDQ512,
28994 IX86_BUILTIN_PUNPCKHQDQ512,
28995 IX86_BUILTIN_PUNPCKLDQ512,
28996 IX86_BUILTIN_PUNPCKLQDQ512,
28997 IX86_BUILTIN_PXORD512,
28998 IX86_BUILTIN_PXORQ512,
28999 IX86_BUILTIN_RCP14PD512,
29000 IX86_BUILTIN_RCP14PS512,
29001 IX86_BUILTIN_RCP14SD,
29002 IX86_BUILTIN_RCP14SS,
29003 IX86_BUILTIN_RNDSCALEPD,
29004 IX86_BUILTIN_RNDSCALEPS,
29005 IX86_BUILTIN_RNDSCALESD,
29006 IX86_BUILTIN_RNDSCALESS,
29007 IX86_BUILTIN_RSQRT14PD512,
29008 IX86_BUILTIN_RSQRT14PS512,
29009 IX86_BUILTIN_RSQRT14SD,
29010 IX86_BUILTIN_RSQRT14SS,
29011 IX86_BUILTIN_SCALEFPD512,
29012 IX86_BUILTIN_SCALEFPS512,
29013 IX86_BUILTIN_SCALEFSD,
29014 IX86_BUILTIN_SCALEFSS,
29015 IX86_BUILTIN_SHUFPD512,
29016 IX86_BUILTIN_SHUFPS512,
29017 IX86_BUILTIN_SHUF_F32x4,
29018 IX86_BUILTIN_SHUF_F64x2,
29019 IX86_BUILTIN_SHUF_I32x4,
29020 IX86_BUILTIN_SHUF_I64x2,
29021 IX86_BUILTIN_SQRTPD512,
29022 IX86_BUILTIN_SQRTPD512_MASK,
29023 IX86_BUILTIN_SQRTPS512_MASK,
29024 IX86_BUILTIN_SQRTPS_NR512,
29025 IX86_BUILTIN_SQRTSD_ROUND,
29026 IX86_BUILTIN_SQRTSS_ROUND,
29027 IX86_BUILTIN_STOREAPD512,
29028 IX86_BUILTIN_STOREAPS512,
29029 IX86_BUILTIN_STOREDQUDI512,
29030 IX86_BUILTIN_STOREDQUSI512,
29031 IX86_BUILTIN_STOREUPD512,
29032 IX86_BUILTIN_STOREUPS512,
29033 IX86_BUILTIN_SUBPD512,
29034 IX86_BUILTIN_SUBPS512,
29035 IX86_BUILTIN_SUBSD_ROUND,
29036 IX86_BUILTIN_SUBSS_ROUND,
29037 IX86_BUILTIN_UCMPD512,
29038 IX86_BUILTIN_UCMPQ512,
29039 IX86_BUILTIN_UNPCKHPD512,
29040 IX86_BUILTIN_UNPCKHPS512,
29041 IX86_BUILTIN_UNPCKLPD512,
29042 IX86_BUILTIN_UNPCKLPS512,
29043 IX86_BUILTIN_VCVTSD2SI32,
29044 IX86_BUILTIN_VCVTSD2SI64,
29045 IX86_BUILTIN_VCVTSD2USI32,
29046 IX86_BUILTIN_VCVTSD2USI64,
29047 IX86_BUILTIN_VCVTSS2SI32,
29048 IX86_BUILTIN_VCVTSS2SI64,
29049 IX86_BUILTIN_VCVTSS2USI32,
29050 IX86_BUILTIN_VCVTSS2USI64,
29051 IX86_BUILTIN_VCVTTSD2SI32,
29052 IX86_BUILTIN_VCVTTSD2SI64,
29053 IX86_BUILTIN_VCVTTSD2USI32,
29054 IX86_BUILTIN_VCVTTSD2USI64,
29055 IX86_BUILTIN_VCVTTSS2SI32,
29056 IX86_BUILTIN_VCVTTSS2SI64,
29057 IX86_BUILTIN_VCVTTSS2USI32,
29058 IX86_BUILTIN_VCVTTSS2USI64,
29059 IX86_BUILTIN_VFMADDPD512_MASK,
29060 IX86_BUILTIN_VFMADDPD512_MASK3,
29061 IX86_BUILTIN_VFMADDPD512_MASKZ,
29062 IX86_BUILTIN_VFMADDPS512_MASK,
29063 IX86_BUILTIN_VFMADDPS512_MASK3,
29064 IX86_BUILTIN_VFMADDPS512_MASKZ,
29065 IX86_BUILTIN_VFMADDSD3_ROUND,
29066 IX86_BUILTIN_VFMADDSS3_ROUND,
29067 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29068 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29069 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29070 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29071 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29072 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29073 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29074 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29075 IX86_BUILTIN_VFMSUBPD512_MASK3,
29076 IX86_BUILTIN_VFMSUBPS512_MASK3,
29077 IX86_BUILTIN_VFMSUBSD3_MASK3,
29078 IX86_BUILTIN_VFMSUBSS3_MASK3,
29079 IX86_BUILTIN_VFNMADDPD512_MASK,
29080 IX86_BUILTIN_VFNMADDPS512_MASK,
29081 IX86_BUILTIN_VFNMSUBPD512_MASK,
29082 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29083 IX86_BUILTIN_VFNMSUBPS512_MASK,
29084 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29085 IX86_BUILTIN_VPCLZCNTD512,
29086 IX86_BUILTIN_VPCLZCNTQ512,
29087 IX86_BUILTIN_VPCONFLICTD512,
29088 IX86_BUILTIN_VPCONFLICTQ512,
29089 IX86_BUILTIN_VPERMDF512,
29090 IX86_BUILTIN_VPERMDI512,
29091 IX86_BUILTIN_VPERMI2VARD512,
29092 IX86_BUILTIN_VPERMI2VARPD512,
29093 IX86_BUILTIN_VPERMI2VARPS512,
29094 IX86_BUILTIN_VPERMI2VARQ512,
29095 IX86_BUILTIN_VPERMILPD512,
29096 IX86_BUILTIN_VPERMILPS512,
29097 IX86_BUILTIN_VPERMILVARPD512,
29098 IX86_BUILTIN_VPERMILVARPS512,
29099 IX86_BUILTIN_VPERMT2VARD512,
29100 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29101 IX86_BUILTIN_VPERMT2VARPD512,
29102 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29103 IX86_BUILTIN_VPERMT2VARPS512,
29104 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29105 IX86_BUILTIN_VPERMT2VARQ512,
29106 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29107 IX86_BUILTIN_VPERMVARDF512,
29108 IX86_BUILTIN_VPERMVARDI512,
29109 IX86_BUILTIN_VPERMVARSF512,
29110 IX86_BUILTIN_VPERMVARSI512,
29111 IX86_BUILTIN_VTERNLOGD512_MASK,
29112 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29113 IX86_BUILTIN_VTERNLOGQ512_MASK,
29114 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29116 /* Mask arithmetic operations */
29117 IX86_BUILTIN_KAND16,
29118 IX86_BUILTIN_KANDN16,
29119 IX86_BUILTIN_KNOT16,
29120 IX86_BUILTIN_KOR16,
29121 IX86_BUILTIN_KORTESTC16,
29122 IX86_BUILTIN_KORTESTZ16,
29123 IX86_BUILTIN_KUNPCKBW,
29124 IX86_BUILTIN_KXNOR16,
29125 IX86_BUILTIN_KXOR16,
29126 IX86_BUILTIN_KMOV16,
29128 /* AVX512VL. */
29129 IX86_BUILTIN_PMOVUSQD256_MEM,
29130 IX86_BUILTIN_PMOVUSQD128_MEM,
29131 IX86_BUILTIN_PMOVSQD256_MEM,
29132 IX86_BUILTIN_PMOVSQD128_MEM,
29133 IX86_BUILTIN_PMOVQD256_MEM,
29134 IX86_BUILTIN_PMOVQD128_MEM,
29135 IX86_BUILTIN_PMOVUSQW256_MEM,
29136 IX86_BUILTIN_PMOVUSQW128_MEM,
29137 IX86_BUILTIN_PMOVSQW256_MEM,
29138 IX86_BUILTIN_PMOVSQW128_MEM,
29139 IX86_BUILTIN_PMOVQW256_MEM,
29140 IX86_BUILTIN_PMOVQW128_MEM,
29141 IX86_BUILTIN_PMOVUSQB256_MEM,
29142 IX86_BUILTIN_PMOVUSQB128_MEM,
29143 IX86_BUILTIN_PMOVSQB256_MEM,
29144 IX86_BUILTIN_PMOVSQB128_MEM,
29145 IX86_BUILTIN_PMOVQB256_MEM,
29146 IX86_BUILTIN_PMOVQB128_MEM,
29147 IX86_BUILTIN_PMOVUSDW256_MEM,
29148 IX86_BUILTIN_PMOVUSDW128_MEM,
29149 IX86_BUILTIN_PMOVSDW256_MEM,
29150 IX86_BUILTIN_PMOVSDW128_MEM,
29151 IX86_BUILTIN_PMOVDW256_MEM,
29152 IX86_BUILTIN_PMOVDW128_MEM,
29153 IX86_BUILTIN_PMOVUSDB256_MEM,
29154 IX86_BUILTIN_PMOVUSDB128_MEM,
29155 IX86_BUILTIN_PMOVSDB256_MEM,
29156 IX86_BUILTIN_PMOVSDB128_MEM,
29157 IX86_BUILTIN_PMOVDB256_MEM,
29158 IX86_BUILTIN_PMOVDB128_MEM,
29159 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29160 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29161 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29162 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29163 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29164 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29165 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29166 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29167 IX86_BUILTIN_LOADAPD256_MASK,
29168 IX86_BUILTIN_LOADAPD128_MASK,
29169 IX86_BUILTIN_LOADAPS256_MASK,
29170 IX86_BUILTIN_LOADAPS128_MASK,
29171 IX86_BUILTIN_STOREAPD256_MASK,
29172 IX86_BUILTIN_STOREAPD128_MASK,
29173 IX86_BUILTIN_STOREAPS256_MASK,
29174 IX86_BUILTIN_STOREAPS128_MASK,
29175 IX86_BUILTIN_LOADUPD256_MASK,
29176 IX86_BUILTIN_LOADUPD128_MASK,
29177 IX86_BUILTIN_LOADUPS256_MASK,
29178 IX86_BUILTIN_LOADUPS128_MASK,
29179 IX86_BUILTIN_STOREUPD256_MASK,
29180 IX86_BUILTIN_STOREUPD128_MASK,
29181 IX86_BUILTIN_STOREUPS256_MASK,
29182 IX86_BUILTIN_STOREUPS128_MASK,
29183 IX86_BUILTIN_LOADDQUDI256_MASK,
29184 IX86_BUILTIN_LOADDQUDI128_MASK,
29185 IX86_BUILTIN_LOADDQUSI256_MASK,
29186 IX86_BUILTIN_LOADDQUSI128_MASK,
29187 IX86_BUILTIN_LOADDQUHI256_MASK,
29188 IX86_BUILTIN_LOADDQUHI128_MASK,
29189 IX86_BUILTIN_LOADDQUQI256_MASK,
29190 IX86_BUILTIN_LOADDQUQI128_MASK,
29191 IX86_BUILTIN_STOREDQUDI256_MASK,
29192 IX86_BUILTIN_STOREDQUDI128_MASK,
29193 IX86_BUILTIN_STOREDQUSI256_MASK,
29194 IX86_BUILTIN_STOREDQUSI128_MASK,
29195 IX86_BUILTIN_STOREDQUHI256_MASK,
29196 IX86_BUILTIN_STOREDQUHI128_MASK,
29197 IX86_BUILTIN_STOREDQUQI256_MASK,
29198 IX86_BUILTIN_STOREDQUQI128_MASK,
29199 IX86_BUILTIN_COMPRESSPDSTORE256,
29200 IX86_BUILTIN_COMPRESSPDSTORE128,
29201 IX86_BUILTIN_COMPRESSPSSTORE256,
29202 IX86_BUILTIN_COMPRESSPSSTORE128,
29203 IX86_BUILTIN_PCOMPRESSQSTORE256,
29204 IX86_BUILTIN_PCOMPRESSQSTORE128,
29205 IX86_BUILTIN_PCOMPRESSDSTORE256,
29206 IX86_BUILTIN_PCOMPRESSDSTORE128,
29207 IX86_BUILTIN_EXPANDPDLOAD256,
29208 IX86_BUILTIN_EXPANDPDLOAD128,
29209 IX86_BUILTIN_EXPANDPSLOAD256,
29210 IX86_BUILTIN_EXPANDPSLOAD128,
29211 IX86_BUILTIN_PEXPANDQLOAD256,
29212 IX86_BUILTIN_PEXPANDQLOAD128,
29213 IX86_BUILTIN_PEXPANDDLOAD256,
29214 IX86_BUILTIN_PEXPANDDLOAD128,
29215 IX86_BUILTIN_EXPANDPDLOAD256Z,
29216 IX86_BUILTIN_EXPANDPDLOAD128Z,
29217 IX86_BUILTIN_EXPANDPSLOAD256Z,
29218 IX86_BUILTIN_EXPANDPSLOAD128Z,
29219 IX86_BUILTIN_PEXPANDQLOAD256Z,
29220 IX86_BUILTIN_PEXPANDQLOAD128Z,
29221 IX86_BUILTIN_PEXPANDDLOAD256Z,
29222 IX86_BUILTIN_PEXPANDDLOAD128Z,
29223 IX86_BUILTIN_PALIGNR256_MASK,
29224 IX86_BUILTIN_PALIGNR128_MASK,
29225 IX86_BUILTIN_MOVDQA64_256_MASK,
29226 IX86_BUILTIN_MOVDQA64_128_MASK,
29227 IX86_BUILTIN_MOVDQA32_256_MASK,
29228 IX86_BUILTIN_MOVDQA32_128_MASK,
29229 IX86_BUILTIN_MOVAPD256_MASK,
29230 IX86_BUILTIN_MOVAPD128_MASK,
29231 IX86_BUILTIN_MOVAPS256_MASK,
29232 IX86_BUILTIN_MOVAPS128_MASK,
29233 IX86_BUILTIN_MOVDQUHI256_MASK,
29234 IX86_BUILTIN_MOVDQUHI128_MASK,
29235 IX86_BUILTIN_MOVDQUQI256_MASK,
29236 IX86_BUILTIN_MOVDQUQI128_MASK,
29237 IX86_BUILTIN_MINPS128_MASK,
29238 IX86_BUILTIN_MAXPS128_MASK,
29239 IX86_BUILTIN_MINPD128_MASK,
29240 IX86_BUILTIN_MAXPD128_MASK,
29241 IX86_BUILTIN_MAXPD256_MASK,
29242 IX86_BUILTIN_MAXPS256_MASK,
29243 IX86_BUILTIN_MINPD256_MASK,
29244 IX86_BUILTIN_MINPS256_MASK,
29245 IX86_BUILTIN_MULPS128_MASK,
29246 IX86_BUILTIN_DIVPS128_MASK,
29247 IX86_BUILTIN_MULPD128_MASK,
29248 IX86_BUILTIN_DIVPD128_MASK,
29249 IX86_BUILTIN_DIVPD256_MASK,
29250 IX86_BUILTIN_DIVPS256_MASK,
29251 IX86_BUILTIN_MULPD256_MASK,
29252 IX86_BUILTIN_MULPS256_MASK,
29253 IX86_BUILTIN_ADDPD128_MASK,
29254 IX86_BUILTIN_ADDPD256_MASK,
29255 IX86_BUILTIN_ADDPS128_MASK,
29256 IX86_BUILTIN_ADDPS256_MASK,
29257 IX86_BUILTIN_SUBPD128_MASK,
29258 IX86_BUILTIN_SUBPD256_MASK,
29259 IX86_BUILTIN_SUBPS128_MASK,
29260 IX86_BUILTIN_SUBPS256_MASK,
29261 IX86_BUILTIN_XORPD256_MASK,
29262 IX86_BUILTIN_XORPD128_MASK,
29263 IX86_BUILTIN_XORPS256_MASK,
29264 IX86_BUILTIN_XORPS128_MASK,
29265 IX86_BUILTIN_ORPD256_MASK,
29266 IX86_BUILTIN_ORPD128_MASK,
29267 IX86_BUILTIN_ORPS256_MASK,
29268 IX86_BUILTIN_ORPS128_MASK,
29269 IX86_BUILTIN_BROADCASTF32x2_256,
29270 IX86_BUILTIN_BROADCASTI32x2_256,
29271 IX86_BUILTIN_BROADCASTI32x2_128,
29272 IX86_BUILTIN_BROADCASTF64X2_256,
29273 IX86_BUILTIN_BROADCASTI64X2_256,
29274 IX86_BUILTIN_BROADCASTF32X4_256,
29275 IX86_BUILTIN_BROADCASTI32X4_256,
29276 IX86_BUILTIN_EXTRACTF32X4_256,
29277 IX86_BUILTIN_EXTRACTI32X4_256,
29278 IX86_BUILTIN_DBPSADBW256,
29279 IX86_BUILTIN_DBPSADBW128,
29280 IX86_BUILTIN_CVTTPD2QQ256,
29281 IX86_BUILTIN_CVTTPD2QQ128,
29282 IX86_BUILTIN_CVTTPD2UQQ256,
29283 IX86_BUILTIN_CVTTPD2UQQ128,
29284 IX86_BUILTIN_CVTPD2QQ256,
29285 IX86_BUILTIN_CVTPD2QQ128,
29286 IX86_BUILTIN_CVTPD2UQQ256,
29287 IX86_BUILTIN_CVTPD2UQQ128,
29288 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29289 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29290 IX86_BUILTIN_CVTTPS2QQ256,
29291 IX86_BUILTIN_CVTTPS2QQ128,
29292 IX86_BUILTIN_CVTTPS2UQQ256,
29293 IX86_BUILTIN_CVTTPS2UQQ128,
29294 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29295 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29296 IX86_BUILTIN_CVTTPS2UDQ256,
29297 IX86_BUILTIN_CVTTPS2UDQ128,
29298 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29299 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29300 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29301 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29302 IX86_BUILTIN_CVTPD2DQ256_MASK,
29303 IX86_BUILTIN_CVTPD2DQ128_MASK,
29304 IX86_BUILTIN_CVTDQ2PD256_MASK,
29305 IX86_BUILTIN_CVTDQ2PD128_MASK,
29306 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29307 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29308 IX86_BUILTIN_CVTDQ2PS256_MASK,
29309 IX86_BUILTIN_CVTDQ2PS128_MASK,
29310 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29311 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29312 IX86_BUILTIN_CVTPS2PD256_MASK,
29313 IX86_BUILTIN_CVTPS2PD128_MASK,
29314 IX86_BUILTIN_PBROADCASTB256_MASK,
29315 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29316 IX86_BUILTIN_PBROADCASTB128_MASK,
29317 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29318 IX86_BUILTIN_PBROADCASTW256_MASK,
29319 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29320 IX86_BUILTIN_PBROADCASTW128_MASK,
29321 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29322 IX86_BUILTIN_PBROADCASTD256_MASK,
29323 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29324 IX86_BUILTIN_PBROADCASTD128_MASK,
29325 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29326 IX86_BUILTIN_PBROADCASTQ256_MASK,
29327 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29328 IX86_BUILTIN_PBROADCASTQ128_MASK,
29329 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29330 IX86_BUILTIN_BROADCASTSS256,
29331 IX86_BUILTIN_BROADCASTSS128,
29332 IX86_BUILTIN_BROADCASTSD256,
29333 IX86_BUILTIN_EXTRACTF64X2_256,
29334 IX86_BUILTIN_EXTRACTI64X2_256,
29335 IX86_BUILTIN_INSERTF32X4_256,
29336 IX86_BUILTIN_INSERTI32X4_256,
29337 IX86_BUILTIN_PMOVSXBW256_MASK,
29338 IX86_BUILTIN_PMOVSXBW128_MASK,
29339 IX86_BUILTIN_PMOVSXBD256_MASK,
29340 IX86_BUILTIN_PMOVSXBD128_MASK,
29341 IX86_BUILTIN_PMOVSXBQ256_MASK,
29342 IX86_BUILTIN_PMOVSXBQ128_MASK,
29343 IX86_BUILTIN_PMOVSXWD256_MASK,
29344 IX86_BUILTIN_PMOVSXWD128_MASK,
29345 IX86_BUILTIN_PMOVSXWQ256_MASK,
29346 IX86_BUILTIN_PMOVSXWQ128_MASK,
29347 IX86_BUILTIN_PMOVSXDQ256_MASK,
29348 IX86_BUILTIN_PMOVSXDQ128_MASK,
29349 IX86_BUILTIN_PMOVZXBW256_MASK,
29350 IX86_BUILTIN_PMOVZXBW128_MASK,
29351 IX86_BUILTIN_PMOVZXBD256_MASK,
29352 IX86_BUILTIN_PMOVZXBD128_MASK,
29353 IX86_BUILTIN_PMOVZXBQ256_MASK,
29354 IX86_BUILTIN_PMOVZXBQ128_MASK,
29355 IX86_BUILTIN_PMOVZXWD256_MASK,
29356 IX86_BUILTIN_PMOVZXWD128_MASK,
29357 IX86_BUILTIN_PMOVZXWQ256_MASK,
29358 IX86_BUILTIN_PMOVZXWQ128_MASK,
29359 IX86_BUILTIN_PMOVZXDQ256_MASK,
29360 IX86_BUILTIN_PMOVZXDQ128_MASK,
29361 IX86_BUILTIN_REDUCEPD256_MASK,
29362 IX86_BUILTIN_REDUCEPD128_MASK,
29363 IX86_BUILTIN_REDUCEPS256_MASK,
29364 IX86_BUILTIN_REDUCEPS128_MASK,
29365 IX86_BUILTIN_REDUCESD_MASK,
29366 IX86_BUILTIN_REDUCESS_MASK,
29367 IX86_BUILTIN_VPERMVARHI256_MASK,
29368 IX86_BUILTIN_VPERMVARHI128_MASK,
29369 IX86_BUILTIN_VPERMT2VARHI256,
29370 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29371 IX86_BUILTIN_VPERMT2VARHI128,
29372 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29373 IX86_BUILTIN_VPERMI2VARHI256,
29374 IX86_BUILTIN_VPERMI2VARHI128,
29375 IX86_BUILTIN_RCP14PD256,
29376 IX86_BUILTIN_RCP14PD128,
29377 IX86_BUILTIN_RCP14PS256,
29378 IX86_BUILTIN_RCP14PS128,
29379 IX86_BUILTIN_RSQRT14PD256_MASK,
29380 IX86_BUILTIN_RSQRT14PD128_MASK,
29381 IX86_BUILTIN_RSQRT14PS256_MASK,
29382 IX86_BUILTIN_RSQRT14PS128_MASK,
29383 IX86_BUILTIN_SQRTPD256_MASK,
29384 IX86_BUILTIN_SQRTPD128_MASK,
29385 IX86_BUILTIN_SQRTPS256_MASK,
29386 IX86_BUILTIN_SQRTPS128_MASK,
29387 IX86_BUILTIN_PADDB128_MASK,
29388 IX86_BUILTIN_PADDW128_MASK,
29389 IX86_BUILTIN_PADDD128_MASK,
29390 IX86_BUILTIN_PADDQ128_MASK,
29391 IX86_BUILTIN_PSUBB128_MASK,
29392 IX86_BUILTIN_PSUBW128_MASK,
29393 IX86_BUILTIN_PSUBD128_MASK,
29394 IX86_BUILTIN_PSUBQ128_MASK,
29395 IX86_BUILTIN_PADDSB128_MASK,
29396 IX86_BUILTIN_PADDSW128_MASK,
29397 IX86_BUILTIN_PSUBSB128_MASK,
29398 IX86_BUILTIN_PSUBSW128_MASK,
29399 IX86_BUILTIN_PADDUSB128_MASK,
29400 IX86_BUILTIN_PADDUSW128_MASK,
29401 IX86_BUILTIN_PSUBUSB128_MASK,
29402 IX86_BUILTIN_PSUBUSW128_MASK,
29403 IX86_BUILTIN_PADDB256_MASK,
29404 IX86_BUILTIN_PADDW256_MASK,
29405 IX86_BUILTIN_PADDD256_MASK,
29406 IX86_BUILTIN_PADDQ256_MASK,
29407 IX86_BUILTIN_PADDSB256_MASK,
29408 IX86_BUILTIN_PADDSW256_MASK,
29409 IX86_BUILTIN_PADDUSB256_MASK,
29410 IX86_BUILTIN_PADDUSW256_MASK,
29411 IX86_BUILTIN_PSUBB256_MASK,
29412 IX86_BUILTIN_PSUBW256_MASK,
29413 IX86_BUILTIN_PSUBD256_MASK,
29414 IX86_BUILTIN_PSUBQ256_MASK,
29415 IX86_BUILTIN_PSUBSB256_MASK,
29416 IX86_BUILTIN_PSUBSW256_MASK,
29417 IX86_BUILTIN_PSUBUSB256_MASK,
29418 IX86_BUILTIN_PSUBUSW256_MASK,
29419 IX86_BUILTIN_SHUF_F64x2_256,
29420 IX86_BUILTIN_SHUF_I64x2_256,
29421 IX86_BUILTIN_SHUF_I32x4_256,
29422 IX86_BUILTIN_SHUF_F32x4_256,
29423 IX86_BUILTIN_PMOVWB128,
29424 IX86_BUILTIN_PMOVWB256,
29425 IX86_BUILTIN_PMOVSWB128,
29426 IX86_BUILTIN_PMOVSWB256,
29427 IX86_BUILTIN_PMOVUSWB128,
29428 IX86_BUILTIN_PMOVUSWB256,
29429 IX86_BUILTIN_PMOVDB128,
29430 IX86_BUILTIN_PMOVDB256,
29431 IX86_BUILTIN_PMOVSDB128,
29432 IX86_BUILTIN_PMOVSDB256,
29433 IX86_BUILTIN_PMOVUSDB128,
29434 IX86_BUILTIN_PMOVUSDB256,
29435 IX86_BUILTIN_PMOVDW128,
29436 IX86_BUILTIN_PMOVDW256,
29437 IX86_BUILTIN_PMOVSDW128,
29438 IX86_BUILTIN_PMOVSDW256,
29439 IX86_BUILTIN_PMOVUSDW128,
29440 IX86_BUILTIN_PMOVUSDW256,
29441 IX86_BUILTIN_PMOVQB128,
29442 IX86_BUILTIN_PMOVQB256,
29443 IX86_BUILTIN_PMOVSQB128,
29444 IX86_BUILTIN_PMOVSQB256,
29445 IX86_BUILTIN_PMOVUSQB128,
29446 IX86_BUILTIN_PMOVUSQB256,
29447 IX86_BUILTIN_PMOVQW128,
29448 IX86_BUILTIN_PMOVQW256,
29449 IX86_BUILTIN_PMOVSQW128,
29450 IX86_BUILTIN_PMOVSQW256,
29451 IX86_BUILTIN_PMOVUSQW128,
29452 IX86_BUILTIN_PMOVUSQW256,
29453 IX86_BUILTIN_PMOVQD128,
29454 IX86_BUILTIN_PMOVQD256,
29455 IX86_BUILTIN_PMOVSQD128,
29456 IX86_BUILTIN_PMOVSQD256,
29457 IX86_BUILTIN_PMOVUSQD128,
29458 IX86_BUILTIN_PMOVUSQD256,
29459 IX86_BUILTIN_RANGEPD256,
29460 IX86_BUILTIN_RANGEPD128,
29461 IX86_BUILTIN_RANGEPS256,
29462 IX86_BUILTIN_RANGEPS128,
29463 IX86_BUILTIN_GETEXPPS256,
29464 IX86_BUILTIN_GETEXPPD256,
29465 IX86_BUILTIN_GETEXPPS128,
29466 IX86_BUILTIN_GETEXPPD128,
29467 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29468 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29469 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29470 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29471 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29472 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29473 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29474 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29475 IX86_BUILTIN_PABSQ256,
29476 IX86_BUILTIN_PABSQ128,
29477 IX86_BUILTIN_PABSD256_MASK,
29478 IX86_BUILTIN_PABSD128_MASK,
29479 IX86_BUILTIN_PMULHRSW256_MASK,
29480 IX86_BUILTIN_PMULHRSW128_MASK,
29481 IX86_BUILTIN_PMULHUW128_MASK,
29482 IX86_BUILTIN_PMULHUW256_MASK,
29483 IX86_BUILTIN_PMULHW256_MASK,
29484 IX86_BUILTIN_PMULHW128_MASK,
29485 IX86_BUILTIN_PMULLW256_MASK,
29486 IX86_BUILTIN_PMULLW128_MASK,
29487 IX86_BUILTIN_PMULLQ256,
29488 IX86_BUILTIN_PMULLQ128,
29489 IX86_BUILTIN_ANDPD256_MASK,
29490 IX86_BUILTIN_ANDPD128_MASK,
29491 IX86_BUILTIN_ANDPS256_MASK,
29492 IX86_BUILTIN_ANDPS128_MASK,
29493 IX86_BUILTIN_ANDNPD256_MASK,
29494 IX86_BUILTIN_ANDNPD128_MASK,
29495 IX86_BUILTIN_ANDNPS256_MASK,
29496 IX86_BUILTIN_ANDNPS128_MASK,
29497 IX86_BUILTIN_PSLLWI128_MASK,
29498 IX86_BUILTIN_PSLLDI128_MASK,
29499 IX86_BUILTIN_PSLLQI128_MASK,
29500 IX86_BUILTIN_PSLLW128_MASK,
29501 IX86_BUILTIN_PSLLD128_MASK,
29502 IX86_BUILTIN_PSLLQ128_MASK,
29503 IX86_BUILTIN_PSLLWI256_MASK ,
29504 IX86_BUILTIN_PSLLW256_MASK,
29505 IX86_BUILTIN_PSLLDI256_MASK,
29506 IX86_BUILTIN_PSLLD256_MASK,
29507 IX86_BUILTIN_PSLLQI256_MASK,
29508 IX86_BUILTIN_PSLLQ256_MASK,
29509 IX86_BUILTIN_PSRADI128_MASK,
29510 IX86_BUILTIN_PSRAD128_MASK,
29511 IX86_BUILTIN_PSRADI256_MASK,
29512 IX86_BUILTIN_PSRAD256_MASK,
29513 IX86_BUILTIN_PSRAQI128_MASK,
29514 IX86_BUILTIN_PSRAQ128_MASK,
29515 IX86_BUILTIN_PSRAQI256_MASK,
29516 IX86_BUILTIN_PSRAQ256_MASK,
29517 IX86_BUILTIN_PANDD256,
29518 IX86_BUILTIN_PANDD128,
29519 IX86_BUILTIN_PSRLDI128_MASK,
29520 IX86_BUILTIN_PSRLD128_MASK,
29521 IX86_BUILTIN_PSRLDI256_MASK,
29522 IX86_BUILTIN_PSRLD256_MASK,
29523 IX86_BUILTIN_PSRLQI128_MASK,
29524 IX86_BUILTIN_PSRLQ128_MASK,
29525 IX86_BUILTIN_PSRLQI256_MASK,
29526 IX86_BUILTIN_PSRLQ256_MASK,
29527 IX86_BUILTIN_PANDQ256,
29528 IX86_BUILTIN_PANDQ128,
29529 IX86_BUILTIN_PANDND256,
29530 IX86_BUILTIN_PANDND128,
29531 IX86_BUILTIN_PANDNQ256,
29532 IX86_BUILTIN_PANDNQ128,
29533 IX86_BUILTIN_PORD256,
29534 IX86_BUILTIN_PORD128,
29535 IX86_BUILTIN_PORQ256,
29536 IX86_BUILTIN_PORQ128,
29537 IX86_BUILTIN_PXORD256,
29538 IX86_BUILTIN_PXORD128,
29539 IX86_BUILTIN_PXORQ256,
29540 IX86_BUILTIN_PXORQ128,
29541 IX86_BUILTIN_PACKSSWB256_MASK,
29542 IX86_BUILTIN_PACKSSWB128_MASK,
29543 IX86_BUILTIN_PACKUSWB256_MASK,
29544 IX86_BUILTIN_PACKUSWB128_MASK,
29545 IX86_BUILTIN_RNDSCALEPS256,
29546 IX86_BUILTIN_RNDSCALEPD256,
29547 IX86_BUILTIN_RNDSCALEPS128,
29548 IX86_BUILTIN_RNDSCALEPD128,
29549 IX86_BUILTIN_VTERNLOGQ256_MASK,
29550 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29551 IX86_BUILTIN_VTERNLOGD256_MASK,
29552 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29553 IX86_BUILTIN_VTERNLOGQ128_MASK,
29554 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29555 IX86_BUILTIN_VTERNLOGD128_MASK,
29556 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29557 IX86_BUILTIN_SCALEFPD256,
29558 IX86_BUILTIN_SCALEFPS256,
29559 IX86_BUILTIN_SCALEFPD128,
29560 IX86_BUILTIN_SCALEFPS128,
29561 IX86_BUILTIN_VFMADDPD256_MASK,
29562 IX86_BUILTIN_VFMADDPD256_MASK3,
29563 IX86_BUILTIN_VFMADDPD256_MASKZ,
29564 IX86_BUILTIN_VFMADDPD128_MASK,
29565 IX86_BUILTIN_VFMADDPD128_MASK3,
29566 IX86_BUILTIN_VFMADDPD128_MASKZ,
29567 IX86_BUILTIN_VFMADDPS256_MASK,
29568 IX86_BUILTIN_VFMADDPS256_MASK3,
29569 IX86_BUILTIN_VFMADDPS256_MASKZ,
29570 IX86_BUILTIN_VFMADDPS128_MASK,
29571 IX86_BUILTIN_VFMADDPS128_MASK3,
29572 IX86_BUILTIN_VFMADDPS128_MASKZ,
29573 IX86_BUILTIN_VFMSUBPD256_MASK3,
29574 IX86_BUILTIN_VFMSUBPD128_MASK3,
29575 IX86_BUILTIN_VFMSUBPS256_MASK3,
29576 IX86_BUILTIN_VFMSUBPS128_MASK3,
29577 IX86_BUILTIN_VFNMADDPD256_MASK,
29578 IX86_BUILTIN_VFNMADDPD128_MASK,
29579 IX86_BUILTIN_VFNMADDPS256_MASK,
29580 IX86_BUILTIN_VFNMADDPS128_MASK,
29581 IX86_BUILTIN_VFNMSUBPD256_MASK,
29582 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29583 IX86_BUILTIN_VFNMSUBPD128_MASK,
29584 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29585 IX86_BUILTIN_VFNMSUBPS256_MASK,
29586 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29587 IX86_BUILTIN_VFNMSUBPS128_MASK,
29588 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29589 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29590 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29591 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29592 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29593 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29594 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29595 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29596 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29597 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29598 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29599 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29600 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29601 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29602 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29603 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29604 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29605 IX86_BUILTIN_INSERTF64X2_256,
29606 IX86_BUILTIN_INSERTI64X2_256,
29607 IX86_BUILTIN_PSRAVV16HI,
29608 IX86_BUILTIN_PSRAVV8HI,
29609 IX86_BUILTIN_PMADDUBSW256_MASK,
29610 IX86_BUILTIN_PMADDUBSW128_MASK,
29611 IX86_BUILTIN_PMADDWD256_MASK,
29612 IX86_BUILTIN_PMADDWD128_MASK,
29613 IX86_BUILTIN_PSRLVV16HI,
29614 IX86_BUILTIN_PSRLVV8HI,
29615 IX86_BUILTIN_CVTPS2DQ256_MASK,
29616 IX86_BUILTIN_CVTPS2DQ128_MASK,
29617 IX86_BUILTIN_CVTPS2UDQ256,
29618 IX86_BUILTIN_CVTPS2UDQ128,
29619 IX86_BUILTIN_CVTPS2QQ256,
29620 IX86_BUILTIN_CVTPS2QQ128,
29621 IX86_BUILTIN_CVTPS2UQQ256,
29622 IX86_BUILTIN_CVTPS2UQQ128,
29623 IX86_BUILTIN_GETMANTPS256,
29624 IX86_BUILTIN_GETMANTPS128,
29625 IX86_BUILTIN_GETMANTPD256,
29626 IX86_BUILTIN_GETMANTPD128,
29627 IX86_BUILTIN_MOVDDUP256_MASK,
29628 IX86_BUILTIN_MOVDDUP128_MASK,
29629 IX86_BUILTIN_MOVSHDUP256_MASK,
29630 IX86_BUILTIN_MOVSHDUP128_MASK,
29631 IX86_BUILTIN_MOVSLDUP256_MASK,
29632 IX86_BUILTIN_MOVSLDUP128_MASK,
29633 IX86_BUILTIN_CVTQQ2PS256,
29634 IX86_BUILTIN_CVTQQ2PS128,
29635 IX86_BUILTIN_CVTUQQ2PS256,
29636 IX86_BUILTIN_CVTUQQ2PS128,
29637 IX86_BUILTIN_CVTQQ2PD256,
29638 IX86_BUILTIN_CVTQQ2PD128,
29639 IX86_BUILTIN_CVTUQQ2PD256,
29640 IX86_BUILTIN_CVTUQQ2PD128,
29641 IX86_BUILTIN_VPERMT2VARQ256,
29642 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29643 IX86_BUILTIN_VPERMT2VARD256,
29644 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29645 IX86_BUILTIN_VPERMI2VARQ256,
29646 IX86_BUILTIN_VPERMI2VARD256,
29647 IX86_BUILTIN_VPERMT2VARPD256,
29648 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29649 IX86_BUILTIN_VPERMT2VARPS256,
29650 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29651 IX86_BUILTIN_VPERMI2VARPD256,
29652 IX86_BUILTIN_VPERMI2VARPS256,
29653 IX86_BUILTIN_VPERMT2VARQ128,
29654 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29655 IX86_BUILTIN_VPERMT2VARD128,
29656 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29657 IX86_BUILTIN_VPERMI2VARQ128,
29658 IX86_BUILTIN_VPERMI2VARD128,
29659 IX86_BUILTIN_VPERMT2VARPD128,
29660 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29661 IX86_BUILTIN_VPERMT2VARPS128,
29662 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29663 IX86_BUILTIN_VPERMI2VARPD128,
29664 IX86_BUILTIN_VPERMI2VARPS128,
29665 IX86_BUILTIN_PSHUFB256_MASK,
29666 IX86_BUILTIN_PSHUFB128_MASK,
29667 IX86_BUILTIN_PSHUFHW256_MASK,
29668 IX86_BUILTIN_PSHUFHW128_MASK,
29669 IX86_BUILTIN_PSHUFLW256_MASK,
29670 IX86_BUILTIN_PSHUFLW128_MASK,
29671 IX86_BUILTIN_PSHUFD256_MASK,
29672 IX86_BUILTIN_PSHUFD128_MASK,
29673 IX86_BUILTIN_SHUFPD256_MASK,
29674 IX86_BUILTIN_SHUFPD128_MASK,
29675 IX86_BUILTIN_SHUFPS256_MASK,
29676 IX86_BUILTIN_SHUFPS128_MASK,
29677 IX86_BUILTIN_PROLVQ256,
29678 IX86_BUILTIN_PROLVQ128,
29679 IX86_BUILTIN_PROLQ256,
29680 IX86_BUILTIN_PROLQ128,
29681 IX86_BUILTIN_PRORVQ256,
29682 IX86_BUILTIN_PRORVQ128,
29683 IX86_BUILTIN_PRORQ256,
29684 IX86_BUILTIN_PRORQ128,
29685 IX86_BUILTIN_PSRAVQ128,
29686 IX86_BUILTIN_PSRAVQ256,
29687 IX86_BUILTIN_PSLLVV4DI_MASK,
29688 IX86_BUILTIN_PSLLVV2DI_MASK,
29689 IX86_BUILTIN_PSLLVV8SI_MASK,
29690 IX86_BUILTIN_PSLLVV4SI_MASK,
29691 IX86_BUILTIN_PSRAVV8SI_MASK,
29692 IX86_BUILTIN_PSRAVV4SI_MASK,
29693 IX86_BUILTIN_PSRLVV4DI_MASK,
29694 IX86_BUILTIN_PSRLVV2DI_MASK,
29695 IX86_BUILTIN_PSRLVV8SI_MASK,
29696 IX86_BUILTIN_PSRLVV4SI_MASK,
29697 IX86_BUILTIN_PSRAWI256_MASK,
29698 IX86_BUILTIN_PSRAW256_MASK,
29699 IX86_BUILTIN_PSRAWI128_MASK,
29700 IX86_BUILTIN_PSRAW128_MASK,
29701 IX86_BUILTIN_PSRLWI256_MASK,
29702 IX86_BUILTIN_PSRLW256_MASK,
29703 IX86_BUILTIN_PSRLWI128_MASK,
29704 IX86_BUILTIN_PSRLW128_MASK,
29705 IX86_BUILTIN_PRORVD256,
29706 IX86_BUILTIN_PROLVD256,
29707 IX86_BUILTIN_PRORD256,
29708 IX86_BUILTIN_PROLD256,
29709 IX86_BUILTIN_PRORVD128,
29710 IX86_BUILTIN_PROLVD128,
29711 IX86_BUILTIN_PRORD128,
29712 IX86_BUILTIN_PROLD128,
29713 IX86_BUILTIN_FPCLASSPD256,
29714 IX86_BUILTIN_FPCLASSPD128,
29715 IX86_BUILTIN_FPCLASSSD,
29716 IX86_BUILTIN_FPCLASSPS256,
29717 IX86_BUILTIN_FPCLASSPS128,
29718 IX86_BUILTIN_FPCLASSSS,
29719 IX86_BUILTIN_CVTB2MASK128,
29720 IX86_BUILTIN_CVTB2MASK256,
29721 IX86_BUILTIN_CVTW2MASK128,
29722 IX86_BUILTIN_CVTW2MASK256,
29723 IX86_BUILTIN_CVTD2MASK128,
29724 IX86_BUILTIN_CVTD2MASK256,
29725 IX86_BUILTIN_CVTQ2MASK128,
29726 IX86_BUILTIN_CVTQ2MASK256,
29727 IX86_BUILTIN_CVTMASK2B128,
29728 IX86_BUILTIN_CVTMASK2B256,
29729 IX86_BUILTIN_CVTMASK2W128,
29730 IX86_BUILTIN_CVTMASK2W256,
29731 IX86_BUILTIN_CVTMASK2D128,
29732 IX86_BUILTIN_CVTMASK2D256,
29733 IX86_BUILTIN_CVTMASK2Q128,
29734 IX86_BUILTIN_CVTMASK2Q256,
29735 IX86_BUILTIN_PCMPEQB128_MASK,
29736 IX86_BUILTIN_PCMPEQB256_MASK,
29737 IX86_BUILTIN_PCMPEQW128_MASK,
29738 IX86_BUILTIN_PCMPEQW256_MASK,
29739 IX86_BUILTIN_PCMPEQD128_MASK,
29740 IX86_BUILTIN_PCMPEQD256_MASK,
29741 IX86_BUILTIN_PCMPEQQ128_MASK,
29742 IX86_BUILTIN_PCMPEQQ256_MASK,
29743 IX86_BUILTIN_PCMPGTB128_MASK,
29744 IX86_BUILTIN_PCMPGTB256_MASK,
29745 IX86_BUILTIN_PCMPGTW128_MASK,
29746 IX86_BUILTIN_PCMPGTW256_MASK,
29747 IX86_BUILTIN_PCMPGTD128_MASK,
29748 IX86_BUILTIN_PCMPGTD256_MASK,
29749 IX86_BUILTIN_PCMPGTQ128_MASK,
29750 IX86_BUILTIN_PCMPGTQ256_MASK,
29751 IX86_BUILTIN_PTESTMB128,
29752 IX86_BUILTIN_PTESTMB256,
29753 IX86_BUILTIN_PTESTMW128,
29754 IX86_BUILTIN_PTESTMW256,
29755 IX86_BUILTIN_PTESTMD128,
29756 IX86_BUILTIN_PTESTMD256,
29757 IX86_BUILTIN_PTESTMQ128,
29758 IX86_BUILTIN_PTESTMQ256,
29759 IX86_BUILTIN_PTESTNMB128,
29760 IX86_BUILTIN_PTESTNMB256,
29761 IX86_BUILTIN_PTESTNMW128,
29762 IX86_BUILTIN_PTESTNMW256,
29763 IX86_BUILTIN_PTESTNMD128,
29764 IX86_BUILTIN_PTESTNMD256,
29765 IX86_BUILTIN_PTESTNMQ128,
29766 IX86_BUILTIN_PTESTNMQ256,
29767 IX86_BUILTIN_PBROADCASTMB128,
29768 IX86_BUILTIN_PBROADCASTMB256,
29769 IX86_BUILTIN_PBROADCASTMW128,
29770 IX86_BUILTIN_PBROADCASTMW256,
29771 IX86_BUILTIN_COMPRESSPD256,
29772 IX86_BUILTIN_COMPRESSPD128,
29773 IX86_BUILTIN_COMPRESSPS256,
29774 IX86_BUILTIN_COMPRESSPS128,
29775 IX86_BUILTIN_PCOMPRESSQ256,
29776 IX86_BUILTIN_PCOMPRESSQ128,
29777 IX86_BUILTIN_PCOMPRESSD256,
29778 IX86_BUILTIN_PCOMPRESSD128,
29779 IX86_BUILTIN_EXPANDPD256,
29780 IX86_BUILTIN_EXPANDPD128,
29781 IX86_BUILTIN_EXPANDPS256,
29782 IX86_BUILTIN_EXPANDPS128,
29783 IX86_BUILTIN_PEXPANDQ256,
29784 IX86_BUILTIN_PEXPANDQ128,
29785 IX86_BUILTIN_PEXPANDD256,
29786 IX86_BUILTIN_PEXPANDD128,
29787 IX86_BUILTIN_EXPANDPD256Z,
29788 IX86_BUILTIN_EXPANDPD128Z,
29789 IX86_BUILTIN_EXPANDPS256Z,
29790 IX86_BUILTIN_EXPANDPS128Z,
29791 IX86_BUILTIN_PEXPANDQ256Z,
29792 IX86_BUILTIN_PEXPANDQ128Z,
29793 IX86_BUILTIN_PEXPANDD256Z,
29794 IX86_BUILTIN_PEXPANDD128Z,
29795 IX86_BUILTIN_PMAXSD256_MASK,
29796 IX86_BUILTIN_PMINSD256_MASK,
29797 IX86_BUILTIN_PMAXUD256_MASK,
29798 IX86_BUILTIN_PMINUD256_MASK,
29799 IX86_BUILTIN_PMAXSD128_MASK,
29800 IX86_BUILTIN_PMINSD128_MASK,
29801 IX86_BUILTIN_PMAXUD128_MASK,
29802 IX86_BUILTIN_PMINUD128_MASK,
29803 IX86_BUILTIN_PMAXSQ256_MASK,
29804 IX86_BUILTIN_PMINSQ256_MASK,
29805 IX86_BUILTIN_PMAXUQ256_MASK,
29806 IX86_BUILTIN_PMINUQ256_MASK,
29807 IX86_BUILTIN_PMAXSQ128_MASK,
29808 IX86_BUILTIN_PMINSQ128_MASK,
29809 IX86_BUILTIN_PMAXUQ128_MASK,
29810 IX86_BUILTIN_PMINUQ128_MASK,
29811 IX86_BUILTIN_PMINSB256_MASK,
29812 IX86_BUILTIN_PMINUB256_MASK,
29813 IX86_BUILTIN_PMAXSB256_MASK,
29814 IX86_BUILTIN_PMAXUB256_MASK,
29815 IX86_BUILTIN_PMINSB128_MASK,
29816 IX86_BUILTIN_PMINUB128_MASK,
29817 IX86_BUILTIN_PMAXSB128_MASK,
29818 IX86_BUILTIN_PMAXUB128_MASK,
29819 IX86_BUILTIN_PMINSW256_MASK,
29820 IX86_BUILTIN_PMINUW256_MASK,
29821 IX86_BUILTIN_PMAXSW256_MASK,
29822 IX86_BUILTIN_PMAXUW256_MASK,
29823 IX86_BUILTIN_PMINSW128_MASK,
29824 IX86_BUILTIN_PMINUW128_MASK,
29825 IX86_BUILTIN_PMAXSW128_MASK,
29826 IX86_BUILTIN_PMAXUW128_MASK,
29827 IX86_BUILTIN_VPCONFLICTQ256,
29828 IX86_BUILTIN_VPCONFLICTD256,
29829 IX86_BUILTIN_VPCLZCNTQ256,
29830 IX86_BUILTIN_VPCLZCNTD256,
29831 IX86_BUILTIN_UNPCKHPD256_MASK,
29832 IX86_BUILTIN_UNPCKHPD128_MASK,
29833 IX86_BUILTIN_UNPCKHPS256_MASK,
29834 IX86_BUILTIN_UNPCKHPS128_MASK,
29835 IX86_BUILTIN_UNPCKLPD256_MASK,
29836 IX86_BUILTIN_UNPCKLPD128_MASK,
29837 IX86_BUILTIN_UNPCKLPS256_MASK,
29838 IX86_BUILTIN_VPCONFLICTQ128,
29839 IX86_BUILTIN_VPCONFLICTD128,
29840 IX86_BUILTIN_VPCLZCNTQ128,
29841 IX86_BUILTIN_VPCLZCNTD128,
29842 IX86_BUILTIN_UNPCKLPS128_MASK,
29843 IX86_BUILTIN_ALIGND256,
29844 IX86_BUILTIN_ALIGNQ256,
29845 IX86_BUILTIN_ALIGND128,
29846 IX86_BUILTIN_ALIGNQ128,
29847 IX86_BUILTIN_CVTPS2PH256_MASK,
29848 IX86_BUILTIN_CVTPS2PH_MASK,
29849 IX86_BUILTIN_CVTPH2PS_MASK,
29850 IX86_BUILTIN_CVTPH2PS256_MASK,
29851 IX86_BUILTIN_PUNPCKHDQ128_MASK,
29852 IX86_BUILTIN_PUNPCKHDQ256_MASK,
29853 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
29854 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
29855 IX86_BUILTIN_PUNPCKLDQ128_MASK,
29856 IX86_BUILTIN_PUNPCKLDQ256_MASK,
29857 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
29858 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
29859 IX86_BUILTIN_PUNPCKHBW128_MASK,
29860 IX86_BUILTIN_PUNPCKHBW256_MASK,
29861 IX86_BUILTIN_PUNPCKHWD128_MASK,
29862 IX86_BUILTIN_PUNPCKHWD256_MASK,
29863 IX86_BUILTIN_PUNPCKLBW128_MASK,
29864 IX86_BUILTIN_PUNPCKLBW256_MASK,
29865 IX86_BUILTIN_PUNPCKLWD128_MASK,
29866 IX86_BUILTIN_PUNPCKLWD256_MASK,
29867 IX86_BUILTIN_PSLLVV16HI,
29868 IX86_BUILTIN_PSLLVV8HI,
29869 IX86_BUILTIN_PACKSSDW256_MASK,
29870 IX86_BUILTIN_PACKSSDW128_MASK,
29871 IX86_BUILTIN_PACKUSDW256_MASK,
29872 IX86_BUILTIN_PACKUSDW128_MASK,
29873 IX86_BUILTIN_PAVGB256_MASK,
29874 IX86_BUILTIN_PAVGW256_MASK,
29875 IX86_BUILTIN_PAVGB128_MASK,
29876 IX86_BUILTIN_PAVGW128_MASK,
29877 IX86_BUILTIN_VPERMVARSF256_MASK,
29878 IX86_BUILTIN_VPERMVARDF256_MASK,
29879 IX86_BUILTIN_VPERMDF256_MASK,
29880 IX86_BUILTIN_PABSB256_MASK,
29881 IX86_BUILTIN_PABSB128_MASK,
29882 IX86_BUILTIN_PABSW256_MASK,
29883 IX86_BUILTIN_PABSW128_MASK,
29884 IX86_BUILTIN_VPERMILVARPD_MASK,
29885 IX86_BUILTIN_VPERMILVARPS_MASK,
29886 IX86_BUILTIN_VPERMILVARPD256_MASK,
29887 IX86_BUILTIN_VPERMILVARPS256_MASK,
29888 IX86_BUILTIN_VPERMILPD_MASK,
29889 IX86_BUILTIN_VPERMILPS_MASK,
29890 IX86_BUILTIN_VPERMILPD256_MASK,
29891 IX86_BUILTIN_VPERMILPS256_MASK,
29892 IX86_BUILTIN_BLENDMQ256,
29893 IX86_BUILTIN_BLENDMD256,
29894 IX86_BUILTIN_BLENDMPD256,
29895 IX86_BUILTIN_BLENDMPS256,
29896 IX86_BUILTIN_BLENDMQ128,
29897 IX86_BUILTIN_BLENDMD128,
29898 IX86_BUILTIN_BLENDMPD128,
29899 IX86_BUILTIN_BLENDMPS128,
29900 IX86_BUILTIN_BLENDMW256,
29901 IX86_BUILTIN_BLENDMB256,
29902 IX86_BUILTIN_BLENDMW128,
29903 IX86_BUILTIN_BLENDMB128,
29904 IX86_BUILTIN_PMULLD256_MASK,
29905 IX86_BUILTIN_PMULLD128_MASK,
29906 IX86_BUILTIN_PMULUDQ256_MASK,
29907 IX86_BUILTIN_PMULDQ256_MASK,
29908 IX86_BUILTIN_PMULDQ128_MASK,
29909 IX86_BUILTIN_PMULUDQ128_MASK,
29910 IX86_BUILTIN_CVTPD2PS256_MASK,
29911 IX86_BUILTIN_CVTPD2PS_MASK,
29912 IX86_BUILTIN_VPERMVARSI256_MASK,
29913 IX86_BUILTIN_VPERMVARDI256_MASK,
29914 IX86_BUILTIN_VPERMDI256_MASK,
29915 IX86_BUILTIN_CMPQ256,
29916 IX86_BUILTIN_CMPD256,
29917 IX86_BUILTIN_UCMPQ256,
29918 IX86_BUILTIN_UCMPD256,
29919 IX86_BUILTIN_CMPB256,
29920 IX86_BUILTIN_CMPW256,
29921 IX86_BUILTIN_UCMPB256,
29922 IX86_BUILTIN_UCMPW256,
29923 IX86_BUILTIN_CMPPD256_MASK,
29924 IX86_BUILTIN_CMPPS256_MASK,
29925 IX86_BUILTIN_CMPQ128,
29926 IX86_BUILTIN_CMPD128,
29927 IX86_BUILTIN_UCMPQ128,
29928 IX86_BUILTIN_UCMPD128,
29929 IX86_BUILTIN_CMPB128,
29930 IX86_BUILTIN_CMPW128,
29931 IX86_BUILTIN_UCMPB128,
29932 IX86_BUILTIN_UCMPW128,
29933 IX86_BUILTIN_CMPPD128_MASK,
29934 IX86_BUILTIN_CMPPS128_MASK,
29936 IX86_BUILTIN_GATHER3SIV8SF,
29937 IX86_BUILTIN_GATHER3SIV4SF,
29938 IX86_BUILTIN_GATHER3SIV4DF,
29939 IX86_BUILTIN_GATHER3SIV2DF,
29940 IX86_BUILTIN_GATHER3DIV8SF,
29941 IX86_BUILTIN_GATHER3DIV4SF,
29942 IX86_BUILTIN_GATHER3DIV4DF,
29943 IX86_BUILTIN_GATHER3DIV2DF,
29944 IX86_BUILTIN_GATHER3SIV8SI,
29945 IX86_BUILTIN_GATHER3SIV4SI,
29946 IX86_BUILTIN_GATHER3SIV4DI,
29947 IX86_BUILTIN_GATHER3SIV2DI,
29948 IX86_BUILTIN_GATHER3DIV8SI,
29949 IX86_BUILTIN_GATHER3DIV4SI,
29950 IX86_BUILTIN_GATHER3DIV4DI,
29951 IX86_BUILTIN_GATHER3DIV2DI,
29952 IX86_BUILTIN_SCATTERSIV8SF,
29953 IX86_BUILTIN_SCATTERSIV4SF,
29954 IX86_BUILTIN_SCATTERSIV4DF,
29955 IX86_BUILTIN_SCATTERSIV2DF,
29956 IX86_BUILTIN_SCATTERDIV8SF,
29957 IX86_BUILTIN_SCATTERDIV4SF,
29958 IX86_BUILTIN_SCATTERDIV4DF,
29959 IX86_BUILTIN_SCATTERDIV2DF,
29960 IX86_BUILTIN_SCATTERSIV8SI,
29961 IX86_BUILTIN_SCATTERSIV4SI,
29962 IX86_BUILTIN_SCATTERSIV4DI,
29963 IX86_BUILTIN_SCATTERSIV2DI,
29964 IX86_BUILTIN_SCATTERDIV8SI,
29965 IX86_BUILTIN_SCATTERDIV4SI,
29966 IX86_BUILTIN_SCATTERDIV4DI,
29967 IX86_BUILTIN_SCATTERDIV2DI,
29969 /* AVX512DQ. */
29970 IX86_BUILTIN_RANGESD128,
29971 IX86_BUILTIN_RANGESS128,
29972 IX86_BUILTIN_KUNPCKWD,
29973 IX86_BUILTIN_KUNPCKDQ,
29974 IX86_BUILTIN_BROADCASTF32x2_512,
29975 IX86_BUILTIN_BROADCASTI32x2_512,
29976 IX86_BUILTIN_BROADCASTF64X2_512,
29977 IX86_BUILTIN_BROADCASTI64X2_512,
29978 IX86_BUILTIN_BROADCASTF32X8_512,
29979 IX86_BUILTIN_BROADCASTI32X8_512,
29980 IX86_BUILTIN_EXTRACTF64X2_512,
29981 IX86_BUILTIN_EXTRACTF32X8,
29982 IX86_BUILTIN_EXTRACTI64X2_512,
29983 IX86_BUILTIN_EXTRACTI32X8,
29984 IX86_BUILTIN_REDUCEPD512_MASK,
29985 IX86_BUILTIN_REDUCEPS512_MASK,
29986 IX86_BUILTIN_PMULLQ512,
29987 IX86_BUILTIN_XORPD512,
29988 IX86_BUILTIN_XORPS512,
29989 IX86_BUILTIN_ORPD512,
29990 IX86_BUILTIN_ORPS512,
29991 IX86_BUILTIN_ANDPD512,
29992 IX86_BUILTIN_ANDPS512,
29993 IX86_BUILTIN_ANDNPD512,
29994 IX86_BUILTIN_ANDNPS512,
29995 IX86_BUILTIN_INSERTF32X8,
29996 IX86_BUILTIN_INSERTI32X8,
29997 IX86_BUILTIN_INSERTF64X2_512,
29998 IX86_BUILTIN_INSERTI64X2_512,
29999 IX86_BUILTIN_FPCLASSPD512,
30000 IX86_BUILTIN_FPCLASSPS512,
30001 IX86_BUILTIN_CVTD2MASK512,
30002 IX86_BUILTIN_CVTQ2MASK512,
30003 IX86_BUILTIN_CVTMASK2D512,
30004 IX86_BUILTIN_CVTMASK2Q512,
30005 IX86_BUILTIN_CVTPD2QQ512,
30006 IX86_BUILTIN_CVTPS2QQ512,
30007 IX86_BUILTIN_CVTPD2UQQ512,
30008 IX86_BUILTIN_CVTPS2UQQ512,
30009 IX86_BUILTIN_CVTQQ2PS512,
30010 IX86_BUILTIN_CVTUQQ2PS512,
30011 IX86_BUILTIN_CVTQQ2PD512,
30012 IX86_BUILTIN_CVTUQQ2PD512,
30013 IX86_BUILTIN_CVTTPS2QQ512,
30014 IX86_BUILTIN_CVTTPS2UQQ512,
30015 IX86_BUILTIN_CVTTPD2QQ512,
30016 IX86_BUILTIN_CVTTPD2UQQ512,
30017 IX86_BUILTIN_RANGEPS512,
30018 IX86_BUILTIN_RANGEPD512,
30020 /* AVX512BW. */
30021 IX86_BUILTIN_PACKUSDW512,
30022 IX86_BUILTIN_PACKSSDW512,
30023 IX86_BUILTIN_LOADDQUHI512_MASK,
30024 IX86_BUILTIN_LOADDQUQI512_MASK,
30025 IX86_BUILTIN_PSLLDQ512,
30026 IX86_BUILTIN_PSRLDQ512,
30027 IX86_BUILTIN_STOREDQUHI512_MASK,
30028 IX86_BUILTIN_STOREDQUQI512_MASK,
30029 IX86_BUILTIN_PALIGNR512,
30030 IX86_BUILTIN_PALIGNR512_MASK,
30031 IX86_BUILTIN_MOVDQUHI512_MASK,
30032 IX86_BUILTIN_MOVDQUQI512_MASK,
30033 IX86_BUILTIN_PSADBW512,
30034 IX86_BUILTIN_DBPSADBW512,
30035 IX86_BUILTIN_PBROADCASTB512,
30036 IX86_BUILTIN_PBROADCASTB512_GPR,
30037 IX86_BUILTIN_PBROADCASTW512,
30038 IX86_BUILTIN_PBROADCASTW512_GPR,
30039 IX86_BUILTIN_PMOVSXBW512_MASK,
30040 IX86_BUILTIN_PMOVZXBW512_MASK,
30041 IX86_BUILTIN_VPERMVARHI512_MASK,
30042 IX86_BUILTIN_VPERMT2VARHI512,
30043 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30044 IX86_BUILTIN_VPERMI2VARHI512,
30045 IX86_BUILTIN_PAVGB512,
30046 IX86_BUILTIN_PAVGW512,
30047 IX86_BUILTIN_PADDB512,
30048 IX86_BUILTIN_PSUBB512,
30049 IX86_BUILTIN_PSUBSB512,
30050 IX86_BUILTIN_PADDSB512,
30051 IX86_BUILTIN_PSUBUSB512,
30052 IX86_BUILTIN_PADDUSB512,
30053 IX86_BUILTIN_PSUBW512,
30054 IX86_BUILTIN_PADDW512,
30055 IX86_BUILTIN_PSUBSW512,
30056 IX86_BUILTIN_PADDSW512,
30057 IX86_BUILTIN_PSUBUSW512,
30058 IX86_BUILTIN_PADDUSW512,
30059 IX86_BUILTIN_PMAXUW512,
30060 IX86_BUILTIN_PMAXSW512,
30061 IX86_BUILTIN_PMINUW512,
30062 IX86_BUILTIN_PMINSW512,
30063 IX86_BUILTIN_PMAXUB512,
30064 IX86_BUILTIN_PMAXSB512,
30065 IX86_BUILTIN_PMINUB512,
30066 IX86_BUILTIN_PMINSB512,
30067 IX86_BUILTIN_PMOVWB512,
30068 IX86_BUILTIN_PMOVSWB512,
30069 IX86_BUILTIN_PMOVUSWB512,
30070 IX86_BUILTIN_PMULHRSW512_MASK,
30071 IX86_BUILTIN_PMULHUW512_MASK,
30072 IX86_BUILTIN_PMULHW512_MASK,
30073 IX86_BUILTIN_PMULLW512_MASK,
30074 IX86_BUILTIN_PSLLWI512_MASK,
30075 IX86_BUILTIN_PSLLW512_MASK,
30076 IX86_BUILTIN_PACKSSWB512,
30077 IX86_BUILTIN_PACKUSWB512,
30078 IX86_BUILTIN_PSRAVV32HI,
30079 IX86_BUILTIN_PMADDUBSW512_MASK,
30080 IX86_BUILTIN_PMADDWD512_MASK,
30081 IX86_BUILTIN_PSRLVV32HI,
30082 IX86_BUILTIN_PUNPCKHBW512,
30083 IX86_BUILTIN_PUNPCKHWD512,
30084 IX86_BUILTIN_PUNPCKLBW512,
30085 IX86_BUILTIN_PUNPCKLWD512,
30086 IX86_BUILTIN_PSHUFB512,
30087 IX86_BUILTIN_PSHUFHW512,
30088 IX86_BUILTIN_PSHUFLW512,
30089 IX86_BUILTIN_PSRAWI512,
30090 IX86_BUILTIN_PSRAW512,
30091 IX86_BUILTIN_PSRLWI512,
30092 IX86_BUILTIN_PSRLW512,
30093 IX86_BUILTIN_CVTB2MASK512,
30094 IX86_BUILTIN_CVTW2MASK512,
30095 IX86_BUILTIN_CVTMASK2B512,
30096 IX86_BUILTIN_CVTMASK2W512,
30097 IX86_BUILTIN_PCMPEQB512_MASK,
30098 IX86_BUILTIN_PCMPEQW512_MASK,
30099 IX86_BUILTIN_PCMPGTB512_MASK,
30100 IX86_BUILTIN_PCMPGTW512_MASK,
30101 IX86_BUILTIN_PTESTMB512,
30102 IX86_BUILTIN_PTESTMW512,
30103 IX86_BUILTIN_PTESTNMB512,
30104 IX86_BUILTIN_PTESTNMW512,
30105 IX86_BUILTIN_PSLLVV32HI,
30106 IX86_BUILTIN_PABSB512,
30107 IX86_BUILTIN_PABSW512,
30108 IX86_BUILTIN_BLENDMW512,
30109 IX86_BUILTIN_BLENDMB512,
30110 IX86_BUILTIN_CMPB512,
30111 IX86_BUILTIN_CMPW512,
30112 IX86_BUILTIN_UCMPB512,
30113 IX86_BUILTIN_UCMPW512,
30115 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30116 where all operands are 32-byte or 64-byte wide respectively. */
30117 IX86_BUILTIN_GATHERALTSIV4DF,
30118 IX86_BUILTIN_GATHERALTDIV8SF,
30119 IX86_BUILTIN_GATHERALTSIV4DI,
30120 IX86_BUILTIN_GATHERALTDIV8SI,
30121 IX86_BUILTIN_GATHER3ALTDIV16SF,
30122 IX86_BUILTIN_GATHER3ALTDIV16SI,
30123 IX86_BUILTIN_GATHER3ALTSIV4DF,
30124 IX86_BUILTIN_GATHER3ALTDIV8SF,
30125 IX86_BUILTIN_GATHER3ALTSIV4DI,
30126 IX86_BUILTIN_GATHER3ALTDIV8SI,
30127 IX86_BUILTIN_GATHER3ALTSIV8DF,
30128 IX86_BUILTIN_GATHER3ALTSIV8DI,
30129 IX86_BUILTIN_GATHER3DIV16SF,
30130 IX86_BUILTIN_GATHER3DIV16SI,
30131 IX86_BUILTIN_GATHER3DIV8DF,
30132 IX86_BUILTIN_GATHER3DIV8DI,
30133 IX86_BUILTIN_GATHER3SIV16SF,
30134 IX86_BUILTIN_GATHER3SIV16SI,
30135 IX86_BUILTIN_GATHER3SIV8DF,
30136 IX86_BUILTIN_GATHER3SIV8DI,
30137 IX86_BUILTIN_SCATTERDIV16SF,
30138 IX86_BUILTIN_SCATTERDIV16SI,
30139 IX86_BUILTIN_SCATTERDIV8DF,
30140 IX86_BUILTIN_SCATTERDIV8DI,
30141 IX86_BUILTIN_SCATTERSIV16SF,
30142 IX86_BUILTIN_SCATTERSIV16SI,
30143 IX86_BUILTIN_SCATTERSIV8DF,
30144 IX86_BUILTIN_SCATTERSIV8DI,
30146 /* AVX512PF */
30147 IX86_BUILTIN_GATHERPFQPD,
30148 IX86_BUILTIN_GATHERPFDPS,
30149 IX86_BUILTIN_GATHERPFDPD,
30150 IX86_BUILTIN_GATHERPFQPS,
30151 IX86_BUILTIN_SCATTERPFDPD,
30152 IX86_BUILTIN_SCATTERPFDPS,
30153 IX86_BUILTIN_SCATTERPFQPD,
30154 IX86_BUILTIN_SCATTERPFQPS,
30156 /* AVX-512ER */
30157 IX86_BUILTIN_EXP2PD_MASK,
30158 IX86_BUILTIN_EXP2PS_MASK,
30159 IX86_BUILTIN_EXP2PS,
30160 IX86_BUILTIN_RCP28PD,
30161 IX86_BUILTIN_RCP28PS,
30162 IX86_BUILTIN_RCP28SD,
30163 IX86_BUILTIN_RCP28SS,
30164 IX86_BUILTIN_RSQRT28PD,
30165 IX86_BUILTIN_RSQRT28PS,
30166 IX86_BUILTIN_RSQRT28SD,
30167 IX86_BUILTIN_RSQRT28SS,
30169 /* AVX-512IFMA */
30170 IX86_BUILTIN_VPMADD52LUQ512,
30171 IX86_BUILTIN_VPMADD52HUQ512,
30172 IX86_BUILTIN_VPMADD52LUQ256,
30173 IX86_BUILTIN_VPMADD52HUQ256,
30174 IX86_BUILTIN_VPMADD52LUQ128,
30175 IX86_BUILTIN_VPMADD52HUQ128,
30176 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30177 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30178 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30179 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30180 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30181 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30183 /* AVX-512VBMI */
30184 IX86_BUILTIN_VPMULTISHIFTQB512,
30185 IX86_BUILTIN_VPMULTISHIFTQB256,
30186 IX86_BUILTIN_VPMULTISHIFTQB128,
30187 IX86_BUILTIN_VPERMVARQI512_MASK,
30188 IX86_BUILTIN_VPERMT2VARQI512,
30189 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30190 IX86_BUILTIN_VPERMI2VARQI512,
30191 IX86_BUILTIN_VPERMVARQI256_MASK,
30192 IX86_BUILTIN_VPERMVARQI128_MASK,
30193 IX86_BUILTIN_VPERMT2VARQI256,
30194 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30195 IX86_BUILTIN_VPERMT2VARQI128,
30196 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30197 IX86_BUILTIN_VPERMI2VARQI256,
30198 IX86_BUILTIN_VPERMI2VARQI128,
30200 /* SHA builtins. */
30201 IX86_BUILTIN_SHA1MSG1,
30202 IX86_BUILTIN_SHA1MSG2,
30203 IX86_BUILTIN_SHA1NEXTE,
30204 IX86_BUILTIN_SHA1RNDS4,
30205 IX86_BUILTIN_SHA256MSG1,
30206 IX86_BUILTIN_SHA256MSG2,
30207 IX86_BUILTIN_SHA256RNDS2,
30209 /* CLWB instructions. */
30210 IX86_BUILTIN_CLWB,
30212 /* PCOMMIT instructions. */
30213 IX86_BUILTIN_PCOMMIT,
30215 /* CLFLUSHOPT instructions. */
30216 IX86_BUILTIN_CLFLUSHOPT,
30218 /* TFmode support builtins. */
30219 IX86_BUILTIN_INFQ,
30220 IX86_BUILTIN_HUGE_VALQ,
30221 IX86_BUILTIN_FABSQ,
30222 IX86_BUILTIN_COPYSIGNQ,
30224 /* Vectorizer support builtins. */
30225 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30226 IX86_BUILTIN_CPYSGNPS,
30227 IX86_BUILTIN_CPYSGNPD,
30228 IX86_BUILTIN_CPYSGNPS256,
30229 IX86_BUILTIN_CPYSGNPS512,
30230 IX86_BUILTIN_CPYSGNPD256,
30231 IX86_BUILTIN_CPYSGNPD512,
30232 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30233 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30236 /* FMA4 instructions. */
30237 IX86_BUILTIN_VFMADDSS,
30238 IX86_BUILTIN_VFMADDSD,
30239 IX86_BUILTIN_VFMADDPS,
30240 IX86_BUILTIN_VFMADDPD,
30241 IX86_BUILTIN_VFMADDPS256,
30242 IX86_BUILTIN_VFMADDPD256,
30243 IX86_BUILTIN_VFMADDSUBPS,
30244 IX86_BUILTIN_VFMADDSUBPD,
30245 IX86_BUILTIN_VFMADDSUBPS256,
30246 IX86_BUILTIN_VFMADDSUBPD256,
30248 /* FMA3 instructions. */
30249 IX86_BUILTIN_VFMADDSS3,
30250 IX86_BUILTIN_VFMADDSD3,
30252 /* XOP instructions. */
30253 IX86_BUILTIN_VPCMOV,
30254 IX86_BUILTIN_VPCMOV_V2DI,
30255 IX86_BUILTIN_VPCMOV_V4SI,
30256 IX86_BUILTIN_VPCMOV_V8HI,
30257 IX86_BUILTIN_VPCMOV_V16QI,
30258 IX86_BUILTIN_VPCMOV_V4SF,
30259 IX86_BUILTIN_VPCMOV_V2DF,
30260 IX86_BUILTIN_VPCMOV256,
30261 IX86_BUILTIN_VPCMOV_V4DI256,
30262 IX86_BUILTIN_VPCMOV_V8SI256,
30263 IX86_BUILTIN_VPCMOV_V16HI256,
30264 IX86_BUILTIN_VPCMOV_V32QI256,
30265 IX86_BUILTIN_VPCMOV_V8SF256,
30266 IX86_BUILTIN_VPCMOV_V4DF256,
30268 IX86_BUILTIN_VPPERM,
30270 IX86_BUILTIN_VPMACSSWW,
30271 IX86_BUILTIN_VPMACSWW,
30272 IX86_BUILTIN_VPMACSSWD,
30273 IX86_BUILTIN_VPMACSWD,
30274 IX86_BUILTIN_VPMACSSDD,
30275 IX86_BUILTIN_VPMACSDD,
30276 IX86_BUILTIN_VPMACSSDQL,
30277 IX86_BUILTIN_VPMACSSDQH,
30278 IX86_BUILTIN_VPMACSDQL,
30279 IX86_BUILTIN_VPMACSDQH,
30280 IX86_BUILTIN_VPMADCSSWD,
30281 IX86_BUILTIN_VPMADCSWD,
30283 IX86_BUILTIN_VPHADDBW,
30284 IX86_BUILTIN_VPHADDBD,
30285 IX86_BUILTIN_VPHADDBQ,
30286 IX86_BUILTIN_VPHADDWD,
30287 IX86_BUILTIN_VPHADDWQ,
30288 IX86_BUILTIN_VPHADDDQ,
30289 IX86_BUILTIN_VPHADDUBW,
30290 IX86_BUILTIN_VPHADDUBD,
30291 IX86_BUILTIN_VPHADDUBQ,
30292 IX86_BUILTIN_VPHADDUWD,
30293 IX86_BUILTIN_VPHADDUWQ,
30294 IX86_BUILTIN_VPHADDUDQ,
30295 IX86_BUILTIN_VPHSUBBW,
30296 IX86_BUILTIN_VPHSUBWD,
30297 IX86_BUILTIN_VPHSUBDQ,
30299 IX86_BUILTIN_VPROTB,
30300 IX86_BUILTIN_VPROTW,
30301 IX86_BUILTIN_VPROTD,
30302 IX86_BUILTIN_VPROTQ,
30303 IX86_BUILTIN_VPROTB_IMM,
30304 IX86_BUILTIN_VPROTW_IMM,
30305 IX86_BUILTIN_VPROTD_IMM,
30306 IX86_BUILTIN_VPROTQ_IMM,
30308 IX86_BUILTIN_VPSHLB,
30309 IX86_BUILTIN_VPSHLW,
30310 IX86_BUILTIN_VPSHLD,
30311 IX86_BUILTIN_VPSHLQ,
30312 IX86_BUILTIN_VPSHAB,
30313 IX86_BUILTIN_VPSHAW,
30314 IX86_BUILTIN_VPSHAD,
30315 IX86_BUILTIN_VPSHAQ,
30317 IX86_BUILTIN_VFRCZSS,
30318 IX86_BUILTIN_VFRCZSD,
30319 IX86_BUILTIN_VFRCZPS,
30320 IX86_BUILTIN_VFRCZPD,
30321 IX86_BUILTIN_VFRCZPS256,
30322 IX86_BUILTIN_VFRCZPD256,
30324 IX86_BUILTIN_VPCOMEQUB,
30325 IX86_BUILTIN_VPCOMNEUB,
30326 IX86_BUILTIN_VPCOMLTUB,
30327 IX86_BUILTIN_VPCOMLEUB,
30328 IX86_BUILTIN_VPCOMGTUB,
30329 IX86_BUILTIN_VPCOMGEUB,
30330 IX86_BUILTIN_VPCOMFALSEUB,
30331 IX86_BUILTIN_VPCOMTRUEUB,
30333 IX86_BUILTIN_VPCOMEQUW,
30334 IX86_BUILTIN_VPCOMNEUW,
30335 IX86_BUILTIN_VPCOMLTUW,
30336 IX86_BUILTIN_VPCOMLEUW,
30337 IX86_BUILTIN_VPCOMGTUW,
30338 IX86_BUILTIN_VPCOMGEUW,
30339 IX86_BUILTIN_VPCOMFALSEUW,
30340 IX86_BUILTIN_VPCOMTRUEUW,
30342 IX86_BUILTIN_VPCOMEQUD,
30343 IX86_BUILTIN_VPCOMNEUD,
30344 IX86_BUILTIN_VPCOMLTUD,
30345 IX86_BUILTIN_VPCOMLEUD,
30346 IX86_BUILTIN_VPCOMGTUD,
30347 IX86_BUILTIN_VPCOMGEUD,
30348 IX86_BUILTIN_VPCOMFALSEUD,
30349 IX86_BUILTIN_VPCOMTRUEUD,
30351 IX86_BUILTIN_VPCOMEQUQ,
30352 IX86_BUILTIN_VPCOMNEUQ,
30353 IX86_BUILTIN_VPCOMLTUQ,
30354 IX86_BUILTIN_VPCOMLEUQ,
30355 IX86_BUILTIN_VPCOMGTUQ,
30356 IX86_BUILTIN_VPCOMGEUQ,
30357 IX86_BUILTIN_VPCOMFALSEUQ,
30358 IX86_BUILTIN_VPCOMTRUEUQ,
30360 IX86_BUILTIN_VPCOMEQB,
30361 IX86_BUILTIN_VPCOMNEB,
30362 IX86_BUILTIN_VPCOMLTB,
30363 IX86_BUILTIN_VPCOMLEB,
30364 IX86_BUILTIN_VPCOMGTB,
30365 IX86_BUILTIN_VPCOMGEB,
30366 IX86_BUILTIN_VPCOMFALSEB,
30367 IX86_BUILTIN_VPCOMTRUEB,
30369 IX86_BUILTIN_VPCOMEQW,
30370 IX86_BUILTIN_VPCOMNEW,
30371 IX86_BUILTIN_VPCOMLTW,
30372 IX86_BUILTIN_VPCOMLEW,
30373 IX86_BUILTIN_VPCOMGTW,
30374 IX86_BUILTIN_VPCOMGEW,
30375 IX86_BUILTIN_VPCOMFALSEW,
30376 IX86_BUILTIN_VPCOMTRUEW,
30378 IX86_BUILTIN_VPCOMEQD,
30379 IX86_BUILTIN_VPCOMNED,
30380 IX86_BUILTIN_VPCOMLTD,
30381 IX86_BUILTIN_VPCOMLED,
30382 IX86_BUILTIN_VPCOMGTD,
30383 IX86_BUILTIN_VPCOMGED,
30384 IX86_BUILTIN_VPCOMFALSED,
30385 IX86_BUILTIN_VPCOMTRUED,
30387 IX86_BUILTIN_VPCOMEQQ,
30388 IX86_BUILTIN_VPCOMNEQ,
30389 IX86_BUILTIN_VPCOMLTQ,
30390 IX86_BUILTIN_VPCOMLEQ,
30391 IX86_BUILTIN_VPCOMGTQ,
30392 IX86_BUILTIN_VPCOMGEQ,
30393 IX86_BUILTIN_VPCOMFALSEQ,
30394 IX86_BUILTIN_VPCOMTRUEQ,
30396 /* LWP instructions. */
30397 IX86_BUILTIN_LLWPCB,
30398 IX86_BUILTIN_SLWPCB,
30399 IX86_BUILTIN_LWPVAL32,
30400 IX86_BUILTIN_LWPVAL64,
30401 IX86_BUILTIN_LWPINS32,
30402 IX86_BUILTIN_LWPINS64,
30404 IX86_BUILTIN_CLZS,
30406 /* RTM */
30407 IX86_BUILTIN_XBEGIN,
30408 IX86_BUILTIN_XEND,
30409 IX86_BUILTIN_XABORT,
30410 IX86_BUILTIN_XTEST,
30412 /* MPX */
30413 IX86_BUILTIN_BNDMK,
30414 IX86_BUILTIN_BNDSTX,
30415 IX86_BUILTIN_BNDLDX,
30416 IX86_BUILTIN_BNDCL,
30417 IX86_BUILTIN_BNDCU,
30418 IX86_BUILTIN_BNDRET,
30419 IX86_BUILTIN_BNDNARROW,
30420 IX86_BUILTIN_BNDINT,
30421 IX86_BUILTIN_SIZEOF,
30422 IX86_BUILTIN_BNDLOWER,
30423 IX86_BUILTIN_BNDUPPER,
30425 /* BMI instructions. */
30426 IX86_BUILTIN_BEXTR32,
30427 IX86_BUILTIN_BEXTR64,
30428 IX86_BUILTIN_CTZS,
30430 /* TBM instructions. */
30431 IX86_BUILTIN_BEXTRI32,
30432 IX86_BUILTIN_BEXTRI64,
30434 /* BMI2 instructions. */
30435 IX86_BUILTIN_BZHI32,
30436 IX86_BUILTIN_BZHI64,
30437 IX86_BUILTIN_PDEP32,
30438 IX86_BUILTIN_PDEP64,
30439 IX86_BUILTIN_PEXT32,
30440 IX86_BUILTIN_PEXT64,
30442 /* ADX instructions. */
30443 IX86_BUILTIN_ADDCARRYX32,
30444 IX86_BUILTIN_ADDCARRYX64,
30446 /* SBB instructions. */
30447 IX86_BUILTIN_SBB32,
30448 IX86_BUILTIN_SBB64,
30450 /* FSGSBASE instructions. */
30451 IX86_BUILTIN_RDFSBASE32,
30452 IX86_BUILTIN_RDFSBASE64,
30453 IX86_BUILTIN_RDGSBASE32,
30454 IX86_BUILTIN_RDGSBASE64,
30455 IX86_BUILTIN_WRFSBASE32,
30456 IX86_BUILTIN_WRFSBASE64,
30457 IX86_BUILTIN_WRGSBASE32,
30458 IX86_BUILTIN_WRGSBASE64,
30460 /* RDRND instructions. */
30461 IX86_BUILTIN_RDRAND16_STEP,
30462 IX86_BUILTIN_RDRAND32_STEP,
30463 IX86_BUILTIN_RDRAND64_STEP,
30465 /* RDSEED instructions. */
30466 IX86_BUILTIN_RDSEED16_STEP,
30467 IX86_BUILTIN_RDSEED32_STEP,
30468 IX86_BUILTIN_RDSEED64_STEP,
30470 /* F16C instructions. */
30471 IX86_BUILTIN_CVTPH2PS,
30472 IX86_BUILTIN_CVTPH2PS256,
30473 IX86_BUILTIN_CVTPS2PH,
30474 IX86_BUILTIN_CVTPS2PH256,
30476 /* CFString built-in for darwin */
30477 IX86_BUILTIN_CFSTRING,
30479 /* Builtins to get CPU type and supported features. */
30480 IX86_BUILTIN_CPU_INIT,
30481 IX86_BUILTIN_CPU_IS,
30482 IX86_BUILTIN_CPU_SUPPORTS,
30484 /* Read/write FLAGS register built-ins. */
30485 IX86_BUILTIN_READ_FLAGS,
30486 IX86_BUILTIN_WRITE_FLAGS,
30488 IX86_BUILTIN_MAX
30489 };
30491 /* Table for the ix86 builtin decls. */
30494 /* Table of all of the builtin functions that are possible with different ISA's
30495 but are waiting to be built until a function is declared to use that
30496 ISA. */
30505 };
30509 /* Bits that can still enable any inclusion of a builtin. */
30512 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30513 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30514 function decl in the ix86_builtins array. Returns the function decl or
30515 NULL_TREE, if the builtin was not added.
30517 If the front end has a special hook for builtin functions, delay adding
30518 builtin functions that aren't in the current ISA until the ISA is changed
30519 with function specific optimization. Doing so, can save about 300K for the
30520 default compiler. When the builtin is expanded, check at that time whether
30521 it is valid.
30523 If the front end doesn't have a special hook, record all builtins, even if
30524 it isn't an instruction set in the current ISA in case the user uses
30525 function specific options for a different ISA, so that we don't get scope
30526 errors if a builtin is added in the middle of a function scope. */
30532 {
30536 {
30545 {
30551 }
30552 else
30553 {
30554 /* Just a MASK where set_and_not_built_p == true can potentially
30555 include a builtin. */
30564 }
30565 }
30568 }
30570 /* Like def_builtin, but also marks the function decl "const". */
30575 {
30579 else
30583 }
30585 /* Add any new builtin functions for a given ISA that may not have been
30586 declared. This saves a bit of space compared to adding all of the
30587 declarations to the tree, even if we didn't use them. */
30589 static void
30591 {
30595 /* Bits in ISA value can be removed from potential isa values. */
30603 {
30606 {
30609 /* Don't define the builtin again. */
30615 NULL_TREE);
30622 NULL_TREE);
30625 }
30626 }
30629 }
30631 /* Bits for builtin_description.flag. */
30633 /* Set when we don't support the comparison natively, and should
30634 swap_comparison in order to support it. */
30635 #define BUILTIN_DESC_SWAP_OPERANDS 1
30637 struct builtin_description
30638 {
30645 };
30648 {
30649 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30650 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30651 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30652 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30653 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30654 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30655 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30656 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30657 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30658 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30659 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30660 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30661 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30662 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30663 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30664 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30665 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30666 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30667 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30668 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30669 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30670 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30671 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30672 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30673 };
30676 {
30677 /* SSE4.2 */
30678 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30679 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30680 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30681 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30682 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30683 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30684 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30685 };
30688 {
30689 /* SSE4.2 */
30690 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30691 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30692 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30693 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30694 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30695 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30696 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30697 };
30699 /* Special builtins with variable number of arguments. */
30701 {
30702 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30703 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30704 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30706 /* 80387 (for use internally for atomic compound assignment). */
30707 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30708 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30709 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30710 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30712 /* MMX */
30713 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30715 /* 3DNow! */
30716 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30718 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30719 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30720 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30721 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30722 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30723 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30724 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30725 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30726 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30728 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30729 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30730 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30731 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30732 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30733 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30734 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30735 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30737 /* SSE */
30738 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30739 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30740 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30742 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30743 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30744 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30745 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30747 /* SSE or 3DNow!A */
30748 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30749 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30751 /* SSE2 */
30752 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30753 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30754 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30755 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30756 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30757 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30758 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30759 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30760 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30761 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30763 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30764 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30766 /* SSE3 */
30767 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30769 /* SSE4.1 */
30770 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30772 /* SSE4A */
30773 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30774 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30776 /* AVX */
30777 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30778 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30780 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30781 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30782 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30783 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30784 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30786 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30787 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30788 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30789 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30790 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30791 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30792 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30794 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30795 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30796 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30798 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
30799 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
30800 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
30801 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
30802 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
30803 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
30804 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
30805 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
30807 /* AVX2 */
30808 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
30809 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
30810 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
30811 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
30812 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
30813 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
30814 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
30815 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
30816 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
30818 /* AVX512F */
30819 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30820 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30821 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30822 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30823 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30824 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30825 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30826 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30827 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30828 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30829 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30830 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30831 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30832 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30833 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30834 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30835 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30836 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30837 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30838 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30839 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
30840 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
30841 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
30842 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
30843 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30844 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30845 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30846 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30847 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30848 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30849 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30850 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30851 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30852 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30853 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30854 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30855 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30856 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30857 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30858 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30859 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30860 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30861 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30862 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30863 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30864 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30865 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30867 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
30868 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
30869 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
30870 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
30871 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
30872 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
30874 /* FSGSBASE */
30875 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30876 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30877 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30878 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30879 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30880 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30881 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30882 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30884 /* RTM */
30885 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30886 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
30887 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
30889 /* AVX512BW */
30890 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
30891 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
30892 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
30893 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
30895 /* AVX512VL */
30896 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
30897 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
30898 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
30899 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
30900 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30901 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30902 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30903 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30904 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30905 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30906 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30907 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30908 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30909 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30910 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30911 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30912 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30913 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30914 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30915 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30916 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30917 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30918 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30919 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30920 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30921 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30922 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30923 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30924 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30925 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30926 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30927 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30928 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30929 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30930 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30931 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30932 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
30933 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
30934 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
30935 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
30936 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30937 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30938 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30939 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30940 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30941 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30942 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30943 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30944 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30945 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30946 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30947 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30948 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30949 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30950 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30951 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30952 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30953 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30954 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30955 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30956 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30957 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30958 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30959 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30960 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30961 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30962 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30963 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30964 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30965 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30966 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30967 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30968 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30969 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30970 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30971 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30972 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30973 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30974 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30975 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30976 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30977 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30978 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30979 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30980 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30981 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30982 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30983 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30984 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30985 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30986 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30987 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30988 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30989 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30991 /* PCOMMIT. */
30992 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
30993 };
30995 /* Builtins with variable number of arguments. */
30997 {
30998 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
30999 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
31000 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
31001 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31002 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31003 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31004 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31006 /* MMX */
31007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31008 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31009 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31010 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31011 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31012 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31014 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31015 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31016 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31017 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31019 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31020 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31021 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31023 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31024 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31026 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31027 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31028 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31029 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31031 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31032 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31033 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31034 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31035 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31036 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31038 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31039 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31040 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31041 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31042 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
31043 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
31045 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31046 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
31047 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31049 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
31051 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31052 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31053 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31054 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31055 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31056 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31058 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31059 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31060 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31061 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31062 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31063 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31065 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31066 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31067 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31068 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31070 /* 3DNow! */
31071 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31072 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31073 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31074 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31076 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31077 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31078 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31079 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31080 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31081 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31082 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31083 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31084 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31085 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31086 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31087 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31088 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31089 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31090 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31092 /* 3DNow!A */
31093 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31094 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31095 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31096 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31097 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31098 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31100 /* SSE */
31101 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31102 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31103 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31104 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31105 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31106 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31107 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31108 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31109 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31110 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31111 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31112 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31114 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31116 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31117 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31118 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31119 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31120 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31121 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31122 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31123 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31125 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31126 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31127 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31128 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31129 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31130 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31131 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31132 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31133 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31134 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31135 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31136 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31137 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31138 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31139 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31140 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31141 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31142 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31143 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31144 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31146 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31147 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31148 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31149 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31151 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31152 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31153 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31154 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31156 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31158 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31159 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31160 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31161 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31162 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31164 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31165 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31166 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31168 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31170 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31171 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31172 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31174 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31175 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31177 /* SSE MMX or 3Dnow!A */
31178 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31179 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31180 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31182 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31183 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31184 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31185 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31187 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31188 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31190 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31192 /* SSE2 */
31193 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31197 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31199 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31201 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31202 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31203 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31204 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31205 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31207 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31209 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31210 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31211 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31212 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31214 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31216 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31218 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31219 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31220 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31221 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31232 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31233 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31234 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31236 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31237 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31238 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31239 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31242 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31243 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31244 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31245 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31246 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31248 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31249 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31250 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31251 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31253 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31254 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31255 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31256 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31258 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31261 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31262 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31264 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31266 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31267 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31268 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31269 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31270 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31271 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31272 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31273 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31275 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31276 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31277 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31278 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31279 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31281 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31282 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31284 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31285 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31287 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31288 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31289 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31290 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31292 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31293 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31295 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31296 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31297 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31298 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31299 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31300 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31302 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31303 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31304 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31307 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31308 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31309 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31310 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31311 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31312 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31313 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31314 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31320 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31324 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31329 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31330 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31333 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31334 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31335 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31336 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31337 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31338 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31339 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31341 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31342 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31343 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31344 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31345 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31346 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31347 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31349 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31350 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31351 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31352 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31355 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31356 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31358 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31360 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31362 /* SSE2 MMX */
31363 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31364 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31366 /* SSE3 */
31367 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31368 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31370 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31371 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31372 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31373 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31374 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31375 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31377 /* SSSE3 */
31378 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31379 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31380 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31381 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31382 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31383 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31385 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31386 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31387 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31388 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31389 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31390 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31391 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31392 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31393 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31394 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31395 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31396 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31397 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31398 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31399 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31400 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31401 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31402 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31403 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31404 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31405 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31406 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31407 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31408 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31410 /* SSSE3. */
31411 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31412 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31414 /* SSE4.1 */
31415 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31416 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31417 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31418 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31419 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31420 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31421 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31422 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31423 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31424 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31426 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31427 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31428 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31429 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31430 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31431 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31432 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31433 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31434 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31435 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31436 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31437 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31438 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31440 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31441 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31442 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31443 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31444 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31445 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31446 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31447 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31448 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31449 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31450 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31451 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31453 /* SSE4.1 */
31454 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31455 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31456 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31457 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31459 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31460 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31461 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31462 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31464 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31465 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31467 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31468 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31470 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31471 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31472 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31473 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31475 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31476 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31478 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31479 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31481 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31482 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31483 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31485 /* SSE4.2 */
31486 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31487 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31488 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31489 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31490 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31492 /* SSE4A */
31493 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31494 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31495 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31496 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31498 /* AES */
31499 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31500 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31502 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31503 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31504 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31505 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31507 /* PCLMUL */
31508 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31510 /* AVX */
31511 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31512 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31513 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31514 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31515 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31516 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31517 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31518 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31519 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31520 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31521 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31522 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31523 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31524 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31525 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31526 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31527 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31528 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31529 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31530 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31531 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31532 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31533 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31534 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31535 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31536 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31538 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31539 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31540 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31541 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31544 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31545 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31546 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31548 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31549 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31550 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31551 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31555 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31559 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31560 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31564 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31566 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31582 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31584 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31586 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31588 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31594 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31598 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31599 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31601 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31602 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31604 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31605 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31606 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31607 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31609 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31610 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31612 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31613 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31615 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31616 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31621 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31623 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31624 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31625 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31628 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31636 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31637 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31638 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31639 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31640 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31641 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31643 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31644 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31646 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31647 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31649 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31651 /* AVX2 */
31652 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31653 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31654 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31655 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31656 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31657 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31658 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31659 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31660 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31661 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31662 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31663 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31664 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31665 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31666 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31669 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31670 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31671 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31672 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31673 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31674 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31675 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31676 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31677 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31678 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31679 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31680 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31681 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31682 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31683 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31684 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31685 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31686 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31687 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31688 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31689 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31690 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31691 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31692 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31693 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31694 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31695 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31696 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31697 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31698 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31699 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31700 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31701 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31702 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31703 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31704 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31705 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31706 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31707 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31708 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31709 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31710 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31711 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31712 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31713 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31714 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31715 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31716 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31717 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31718 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31719 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31720 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31721 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31722 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31723 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31724 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31725 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31726 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31727 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31728 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31729 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31730 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31731 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31732 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31733 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31734 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31735 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31736 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31737 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31738 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31739 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31740 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31741 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31742 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31743 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31744 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31745 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31746 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31747 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31748 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31749 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31750 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31751 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31752 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31753 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31755 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31757 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31759 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31762 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31764 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31766 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31769 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31778 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31780 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31781 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31782 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31783 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31784 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31786 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31787 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31788 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31789 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31790 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31791 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31792 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31793 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31794 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31795 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31796 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31797 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31799 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31801 /* BMI */
31802 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31803 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31804 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31806 /* TBM */
31807 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31808 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31810 /* F16C */
31811 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
31812 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
31813 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
31814 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
31816 /* BMI2 */
31817 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31818 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31819 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31820 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31821 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31822 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31824 /* AVX512F */
31825 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
31826 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
31827 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
31828 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
31829 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
31830 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
31831 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31832 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31833 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31834 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31835 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31836 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31837 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31838 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
31839 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31840 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
31841 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
31842 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31843 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31844 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31845 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31846 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31847 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31848 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
31849 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31850 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
31851 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31852 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31853 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31854 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31855 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
31856 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
31857 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
31858 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
31859 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
31860 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
31861 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
31862 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
31863 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31864 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31865 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31866 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31867 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31868 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31869 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31870 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31871 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31872 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31873 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31874 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31875 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31876 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31877 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31878 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31879 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
31880 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
31881 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
31882 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
31883 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31884 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31885 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31886 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31887 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31888 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31889 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31890 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31891 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31892 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31893 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31894 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31895 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31896 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31897 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31898 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31899 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31900 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31901 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31902 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31903 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31904 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31905 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31906 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31907 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31908 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31909 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31910 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31911 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31912 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31913 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31914 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31915 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31916 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31917 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31918 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31919 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31920 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31921 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31922 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31923 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31924 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31925 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31926 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31927 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31991 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31992 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31993 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31994 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31999 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32001 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32003 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32007 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32010 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32011 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
32023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
32024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
32025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32026 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
32028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32031 /* Mask arithmetic operations */
32032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
32035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
32039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
32043 /* SHA */
32044 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32045 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32046 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32047 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32048 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32049 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32050 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
32052 /* AVX512VL. */
32053 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
32054 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
32055 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32056 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32057 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32058 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32059 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32060 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32061 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32062 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32063 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32064 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32065 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32066 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32067 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32068 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32069 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32070 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32071 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32072 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32073 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32074 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32075 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32076 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32077 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32078 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32079 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32080 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32081 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32082 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32083 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32084 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32085 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32086 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32087 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32088 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32089 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32090 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32091 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32092 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32093 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32094 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32095 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32096 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32097 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32098 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32099 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32100 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32101 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32102 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32103 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32104 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32105 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32106 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
32107 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
32108 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
32109 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
32110 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32111 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32112 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32113 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32114 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32115 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32116 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32117 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32118 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32119 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32120 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32121 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32122 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32123 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32124 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32125 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32126 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32127 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32128 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32129 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32130 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32131 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32132 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32133 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32134 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32135 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32136 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32137 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32138 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32139 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32140 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32141 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32142 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
32143 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
32144 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
32145 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
32146 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32147 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
32148 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
32149 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32150 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32151 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32152 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32153 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32154 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32155 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32156 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32157 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32158 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32159 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32160 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32161 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32162 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32163 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32164 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32165 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32166 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32167 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32168 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32169 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32170 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32171 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32172 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32173 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32174 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32175 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32177 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32178 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32179 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32180 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32181 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32182 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32183 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32184 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32185 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32186 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32189 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32190 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32191 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32192 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32193 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32194 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32195 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32196 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32197 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32198 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32199 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32200 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32201 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32202 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32203 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32204 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32205 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32206 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32207 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32208 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32209 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32210 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32211 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32212 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32213 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32214 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32215 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32216 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32217 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32218 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32219 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32220 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32221 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32222 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32223 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32224 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32225 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32226 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32227 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32228 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32229 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32230 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32231 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32232 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32233 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32234 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32235 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32236 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32237 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32238 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32239 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32240 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32241 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32242 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32243 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32244 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32245 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32246 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32247 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32248 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32249 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32250 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32251 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32252 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32253 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32254 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32255 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32256 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32257 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32258 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32259 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32260 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32261 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32262 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32263 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32264 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32265 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32266 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32267 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32268 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32269 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32270 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32271 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32272 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32273 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32274 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32275 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32276 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32277 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32278 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32279 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32280 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32281 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32282 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32283 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32284 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32285 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32286 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32287 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32288 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32289 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32290 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32291 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32292 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32293 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32294 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32295 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32296 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32297 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32298 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32299 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32300 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32301 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32302 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32303 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32304 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32305 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32306 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32307 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32308 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32309 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32310 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32311 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32312 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32313 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32314 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32315 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32316 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32317 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32318 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32319 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32320 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32321 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32322 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32323 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32324 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32325 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32326 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32327 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32330 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32331 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32333 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32334 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32339 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32340 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32341 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32342 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32343 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32344 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32347 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32348 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32349 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32350 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32351 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32352 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32353 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32354 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32355 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32356 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32357 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32358 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32359 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32360 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32361 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32362 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32363 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32364 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32365 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32366 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32367 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32368 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32369 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32370 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32371 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32372 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32373 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32374 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32377 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32378 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32379 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32380 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32381 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32382 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32383 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32384 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32385 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32386 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32387 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32394 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32395 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32396 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32398 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32399 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32400 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32401 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32402 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32403 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32404 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32405 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32406 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32407 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32408 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32412 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32419 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32420 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32421 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32422 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32423 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32424 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32425 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32426 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32427 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32428 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32429 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32430 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32431 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32432 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32433 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32434 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32435 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32436 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32437 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32438 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32439 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32440 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32441 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32442 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32443 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32444 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32445 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32446 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32447 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32448 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32449 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32450 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32451 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32452 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32453 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32454 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32455 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32456 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32457 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32458 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32459 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32460 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32461 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32463 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32464 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32465 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32466 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32467 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32468 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32469 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32470 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32471 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32472 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32473 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32474 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32475 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32476 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32479 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32480 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32481 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32482 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32483 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32484 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32485 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32486 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32487 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32488 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32489 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32490 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32491 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32492 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32493 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32494 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32495 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32496 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32497 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32498 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32499 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32500 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32501 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32502 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32503 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32504 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32505 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32506 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32507 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32508 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32509 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32510 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32511 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32512 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32514 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32515 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32516 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32517 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32518 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32519 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32520 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32521 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32522 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32523 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32524 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32525 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32526 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32527 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32528 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32529 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32530 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32531 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32532 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32533 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32534 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32535 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32536 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32537 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32539 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32540 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32541 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32542 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32543 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32544 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32545 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32546 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32547 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32548 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32549 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32550 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32551 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32552 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32553 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32554 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32555 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32556 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32557 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32558 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32559 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32560 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32561 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32562 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32563 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32564 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32565 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32566 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32567 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32568 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32570 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32571 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32572 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32573 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32574 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32575 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32576 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32577 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32578 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32579 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32580 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32581 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32582 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32583 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32584 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32585 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32586 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32587 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32588 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32589 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32590 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32591 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32592 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32593 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32594 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32595 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32596 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32597 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32598 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32599 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32600 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32601 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32602 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32603 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32604 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32606 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32607 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32608 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32609 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32610 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32611 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32612 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32613 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32614 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32619 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32620 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32621 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32622 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32623 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32628 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32629 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32630 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32631 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32632 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32633 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32634 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32635 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32636 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32637 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32638 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32639 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32640 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32641 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32642 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32643 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32644 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32645 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32646 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32647 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32648 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32649 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32650 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32651 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32652 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32653 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32654 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32655 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32656 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32657 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32658 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32659 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32660 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32661 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32662 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32663 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32664 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32665 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32666 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32667 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32668 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32669 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32670 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32671 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32672 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32673 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32674 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32675 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32676 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32677 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32678 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32679 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32680 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32681 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32682 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32683 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32684 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32685 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32686 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32687 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32688 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32689 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32690 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32691 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32692 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32693 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32694 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32695 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32696 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32697 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32698 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32699 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32700 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32701 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32702 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32703 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32704 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32705 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32706 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32707 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32708 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32709 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32710 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32711 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32712 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32713 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32714 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32715 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32716 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32717 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32718 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32719 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32720 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32721 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32722 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32723 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32724 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32725 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32726 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32727 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32728 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32729 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32730 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32731 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32732 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32733 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32734 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32735 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32736 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32737 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32738 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32739 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32740 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32741 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32742 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32743 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32744 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32745 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32746 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32747 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32748 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32749 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32750 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32751 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32752 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32753 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32754 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32755 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32756 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32757 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32758 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32759 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32760 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32761 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32762 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32763 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32764 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32766 /* AVX512DQ. */
32767 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32768 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32769 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32770 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32771 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32772 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32773 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32774 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32775 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32776 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32777 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32778 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32779 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32780 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32781 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32782 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32783 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32784 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32785 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32786 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32787 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32788 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32789 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32790 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32791 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32792 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32793 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32794 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32795 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32796 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
32797 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
32799 /* AVX512BW. */
32800 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
32801 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
32802 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32803 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32804 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32805 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32806 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
32807 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
32808 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32809 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32810 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
32811 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
32812 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
32813 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
32814 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
32815 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
32816 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32817 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32818 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32819 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32820 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32821 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32822 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32823 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32824 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32825 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32826 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32827 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32828 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32829 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32830 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32831 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32832 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32833 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32834 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32835 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32836 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32837 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32838 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32839 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32840 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32841 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32842 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32843 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32844 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32845 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32846 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32847 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32848 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32849 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32850 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32851 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32852 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32853 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32854 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32855 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32856 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
32857 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
32858 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32859 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32860 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32861 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32862 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32863 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32864 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32865 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32866 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32867 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32868 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32869 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32870 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
32871 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
32872 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
32873 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
32874 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32875 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32876 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32877 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32878 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32879 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32880 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32881 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32882 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32883 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32884 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32885 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32886 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32887 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32888 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32889 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32890 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32892 /* AVX512IFMA */
32893 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32894 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32895 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32896 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32897 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32898 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32899 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32900 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32901 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32902 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32903 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32904 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32906 /* AVX512VBMI */
32907 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32908 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32909 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32910 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32911 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32912 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32913 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32914 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32915 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32916 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32917 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32918 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32919 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32920 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32921 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32922 };
32924 /* Builtins with rounding support. */
32926 {
32927 /* AVX512F */
32928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
32933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
32934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
32935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
32936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
32937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
32938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
32941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
32943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
32945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
32947 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
32948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
32949 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
32950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
32951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32956 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
32957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
32958 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
32959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32994 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32999 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33001 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33003 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33007 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33008 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33010 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33011 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33012 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33014 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33016 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33018 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33020 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33022 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
33030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
33031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33048 /* AVX512ER */
33049 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33050 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33051 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33052 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33053 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33054 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33055 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33056 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33057 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33058 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33060 /* AVX512DQ. */
33061 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33062 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33063 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33064 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33065 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33066 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33067 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33068 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33069 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33070 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33071 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33072 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33073 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33074 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33075 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33076 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33077 };
33079 /* Bultins for MPX. */
33081 {
33082 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33083 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33084 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33085 };
33087 /* Const builtins for MPX. */
33089 {
33090 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33091 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33092 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33093 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33094 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33095 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33096 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33097 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33098 };
33100 /* FMA4 and XOP. */
33101 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33102 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33103 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33104 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33105 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33106 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33107 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33108 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33109 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33110 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33111 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33112 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33113 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33114 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33115 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33116 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33117 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33118 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33119 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33120 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33121 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33122 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33123 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33124 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33125 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33126 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33127 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33128 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33129 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33130 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33131 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33132 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33133 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33134 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33135 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33136 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33137 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33138 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33139 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33140 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33141 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33142 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33143 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33144 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33145 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33146 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33147 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33148 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33149 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33150 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33151 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33152 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33155 {
33196 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33197 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33198 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33199 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33200 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33201 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33202 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33204 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33205 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33206 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33207 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33208 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33209 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33210 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33212 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33214 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33215 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33216 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33217 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33218 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33219 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33220 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33221 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33222 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33223 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33224 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33225 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33227 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33228 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33229 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33230 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33231 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33232 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33233 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33234 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33235 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33236 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33237 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33238 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33239 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33240 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33241 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33242 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33244 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33245 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33246 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33247 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33248 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33249 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33251 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33252 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33253 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33254 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33255 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33256 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33257 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33258 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33259 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33260 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33261 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33262 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33263 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33264 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33265 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33267 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33268 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33269 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33270 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33271 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33272 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33273 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33275 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33276 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33277 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33278 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33279 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33280 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33281 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33283 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33284 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33285 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33286 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33287 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33288 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33289 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33291 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33292 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33293 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33294 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33295 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33296 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33297 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33299 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33300 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33301 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33302 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33303 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33304 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33305 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33307 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33308 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33309 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33310 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33311 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33312 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33313 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33315 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33316 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33317 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33318 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33319 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33320 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33321 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33323 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33324 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33325 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33326 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33327 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33328 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33329 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33331 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33332 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33333 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33334 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33335 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33336 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33337 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33338 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33340 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33341 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33342 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33343 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33344 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33345 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33346 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33347 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33349 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33350 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33351 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33352 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33354 };
33355 \f
33356 /* TM vector builtins. */
33358 /* Reuse the existing x86-specific `struct builtin_description' cause
33359 we're lazy. Add casts to make them fit. */
33361 {
33362 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33363 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33364 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33365 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33366 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33367 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33368 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33370 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33371 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33372 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33373 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33374 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33375 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33376 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33378 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33379 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33380 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33381 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33382 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33383 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33384 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33386 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33387 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33388 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33389 };
33391 /* TM callbacks. */
33393 /* Return the builtin decl needed to load a vector of TYPE. */
33395 static tree
33397 {
33399 {
33401 {
33408 }
33409 }
33411 }
33413 /* Return the builtin decl needed to store a vector of TYPE. */
33415 static tree
33417 {
33419 {
33421 {
33428 }
33429 }
33431 }
33432 \f
33433 /* Initialize the transactional memory vector load/store builtins. */
33435 static void
33437 {
33441 tree decl;
33448 /* If there are no builtins defined, we must be compiling in a
33449 language without trans-mem support. */
33453 /* Use whatever attributes a normal TM load has. */
33457 /* Use whatever attributes a normal TM store has. */
33461 /* Use whatever attributes a normal TM log has. */
33469 {
33473 {
33481 {
33484 }
33486 {
33489 }
33490 else
33491 {
33494 }
33496 /* The builtin without the prefix for
33497 calling it directly. */
33499 attrs);
33500 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33501 set the TYPE_ATTRIBUTES. */
33505 }
33506 }
33507 }
33509 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33510 in the current target ISA to allow the user to compile particular modules
33511 with different target specific options that differ from the command line
33512 options. */
33513 static void
33515 {
33520 /* Add all special builtins with variable number of operands. */
33524 {
33530 }
33532 /* Add all builtins with variable number of operands. */
33536 {
33542 }
33544 /* Add all builtins with rounding. */
33548 {
33554 }
33556 /* pcmpestr[im] insns. */
33560 {
33563 else
33566 }
33568 /* pcmpistr[im] insns. */
33572 {
33575 else
33578 }
33580 /* comi/ucomi insns. */
33582 {
33585 else
33588 }
33590 /* SSE */
33596 /* SSE or 3DNow!A */
33599 IX86_BUILTIN_MASKMOVQ);
33601 /* SSE2 */
33610 /* SSE3. */
33616 /* AES */
33630 /* PCLMUL */
33634 /* RDRND */
33641 IX86_BUILTIN_RDRAND64_STEP);
33643 /* AVX2 */
33645 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33646 IX86_BUILTIN_GATHERSIV2DF);
33649 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33650 IX86_BUILTIN_GATHERSIV4DF);
33653 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33654 IX86_BUILTIN_GATHERDIV2DF);
33657 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33658 IX86_BUILTIN_GATHERDIV4DF);
33661 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33662 IX86_BUILTIN_GATHERSIV4SF);
33665 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33666 IX86_BUILTIN_GATHERSIV8SF);
33669 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33670 IX86_BUILTIN_GATHERDIV4SF);
33673 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33674 IX86_BUILTIN_GATHERDIV8SF);
33677 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33678 IX86_BUILTIN_GATHERSIV2DI);
33681 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33682 IX86_BUILTIN_GATHERSIV4DI);
33685 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33686 IX86_BUILTIN_GATHERDIV2DI);
33689 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33690 IX86_BUILTIN_GATHERDIV4DI);
33693 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33694 IX86_BUILTIN_GATHERSIV4SI);
33697 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33698 IX86_BUILTIN_GATHERSIV8SI);
33701 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33702 IX86_BUILTIN_GATHERDIV4SI);
33705 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33706 IX86_BUILTIN_GATHERDIV8SI);
33709 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33710 IX86_BUILTIN_GATHERALTSIV4DF);
33713 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33714 IX86_BUILTIN_GATHERALTDIV8SF);
33717 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33718 IX86_BUILTIN_GATHERALTSIV4DI);
33721 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33722 IX86_BUILTIN_GATHERALTDIV8SI);
33724 /* AVX512F */
33726 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33727 IX86_BUILTIN_GATHER3SIV16SF);
33730 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33731 IX86_BUILTIN_GATHER3SIV8DF);
33734 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33735 IX86_BUILTIN_GATHER3DIV16SF);
33738 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33739 IX86_BUILTIN_GATHER3DIV8DF);
33742 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33743 IX86_BUILTIN_GATHER3SIV16SI);
33746 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33747 IX86_BUILTIN_GATHER3SIV8DI);
33750 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33751 IX86_BUILTIN_GATHER3DIV16SI);
33754 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33755 IX86_BUILTIN_GATHER3DIV8DI);
33758 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33759 IX86_BUILTIN_GATHER3ALTSIV8DF);
33762 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33763 IX86_BUILTIN_GATHER3ALTDIV16SF);
33766 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33767 IX86_BUILTIN_GATHER3ALTSIV8DI);
33770 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33771 IX86_BUILTIN_GATHER3ALTDIV16SI);
33774 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33775 IX86_BUILTIN_SCATTERSIV16SF);
33778 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33779 IX86_BUILTIN_SCATTERSIV8DF);
33782 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33783 IX86_BUILTIN_SCATTERDIV16SF);
33786 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33787 IX86_BUILTIN_SCATTERDIV8DF);
33790 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33791 IX86_BUILTIN_SCATTERSIV16SI);
33794 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33795 IX86_BUILTIN_SCATTERSIV8DI);
33798 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
33799 IX86_BUILTIN_SCATTERDIV16SI);
33802 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
33803 IX86_BUILTIN_SCATTERDIV8DI);
33805 /* AVX512VL */
33807 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
33808 IX86_BUILTIN_GATHER3SIV2DF);
33811 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
33812 IX86_BUILTIN_GATHER3SIV4DF);
33815 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
33816 IX86_BUILTIN_GATHER3DIV2DF);
33819 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
33820 IX86_BUILTIN_GATHER3DIV4DF);
33823 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
33824 IX86_BUILTIN_GATHER3SIV4SF);
33827 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
33828 IX86_BUILTIN_GATHER3SIV8SF);
33831 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
33832 IX86_BUILTIN_GATHER3DIV4SF);
33835 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
33836 IX86_BUILTIN_GATHER3DIV8SF);
33839 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
33840 IX86_BUILTIN_GATHER3SIV2DI);
33843 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
33844 IX86_BUILTIN_GATHER3SIV4DI);
33847 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
33848 IX86_BUILTIN_GATHER3DIV2DI);
33851 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
33852 IX86_BUILTIN_GATHER3DIV4DI);
33855 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
33856 IX86_BUILTIN_GATHER3SIV4SI);
33859 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
33860 IX86_BUILTIN_GATHER3SIV8SI);
33863 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
33864 IX86_BUILTIN_GATHER3DIV4SI);
33867 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
33868 IX86_BUILTIN_GATHER3DIV8SI);
33871 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
33872 IX86_BUILTIN_GATHER3ALTSIV4DF);
33875 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
33876 IX86_BUILTIN_GATHER3ALTDIV8SF);
33879 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
33880 IX86_BUILTIN_GATHER3ALTSIV4DI);
33883 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
33884 IX86_BUILTIN_GATHER3ALTDIV8SI);
33887 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
33888 IX86_BUILTIN_SCATTERSIV8SF);
33891 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
33892 IX86_BUILTIN_SCATTERSIV4SF);
33895 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
33896 IX86_BUILTIN_SCATTERSIV4DF);
33899 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
33900 IX86_BUILTIN_SCATTERSIV2DF);
33903 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
33904 IX86_BUILTIN_SCATTERDIV8SF);
33907 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
33908 IX86_BUILTIN_SCATTERDIV4SF);
33911 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
33912 IX86_BUILTIN_SCATTERDIV4DF);
33915 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
33916 IX86_BUILTIN_SCATTERDIV2DF);
33919 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
33920 IX86_BUILTIN_SCATTERSIV8SI);
33923 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
33924 IX86_BUILTIN_SCATTERSIV4SI);
33927 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
33928 IX86_BUILTIN_SCATTERSIV4DI);
33931 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
33932 IX86_BUILTIN_SCATTERSIV2DI);
33935 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
33936 IX86_BUILTIN_SCATTERDIV8SI);
33939 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
33940 IX86_BUILTIN_SCATTERDIV4SI);
33943 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
33944 IX86_BUILTIN_SCATTERDIV4DI);
33947 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
33948 IX86_BUILTIN_SCATTERDIV2DI);
33950 /* AVX512PF */
33952 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33953 IX86_BUILTIN_GATHERPFDPD);
33955 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33956 IX86_BUILTIN_GATHERPFDPS);
33958 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33959 IX86_BUILTIN_GATHERPFQPD);
33961 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33962 IX86_BUILTIN_GATHERPFQPS);
33964 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33965 IX86_BUILTIN_SCATTERPFDPD);
33967 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33968 IX86_BUILTIN_SCATTERPFDPS);
33970 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33971 IX86_BUILTIN_SCATTERPFQPD);
33973 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33974 IX86_BUILTIN_SCATTERPFQPS);
33976 /* SHA */
33992 /* RTM. */
33996 /* MMX access to the vec_init patterns. */
34001 V4HI_FTYPE_HI_HI_HI_HI,
34002 IX86_BUILTIN_VEC_INIT_V4HI);
34005 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
34006 IX86_BUILTIN_VEC_INIT_V8QI);
34008 /* Access to the vec_extract patterns. */
34030 /* Access to the vec_set patterns. */
34051 /* RDSEED */
34060 /* ADCX */
34065 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34066 IX86_BUILTIN_ADDCARRYX64);
34068 /* SBB */
34073 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34074 IX86_BUILTIN_SBB64);
34076 /* Read/write FLAGS. */
34086 /* CLFLUSHOPT. */
34090 /* CLWB. */
34094 /* Add FMA4 multi-arg argument instructions */
34096 {
34102 }
34103 }
34105 static void
34107 {
34110 tree decl;
34116 {
34123 /* With no leaf and nothrow flags for MPX builtins
34124 abnormal edges may follow its call when setjmp
34125 presents in the function. Since we may have a lot
34126 of MPX builtins calls it causes lots of useless
34127 edges and enormous PHI nodes. To avoid this we mark
34128 MPX builtins as leaf and nothrow. */
34130 {
34132 NULL_TREE);
34134 }
34135 else
34136 {
34139 }
34140 }
34145 {
34153 {
34155 NULL_TREE);
34157 }
34158 else
34159 {
34162 }
34163 }
34164 }
34166 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34167 to return a pointer to VERSION_DECL if the outcome of the expression
34168 formed by PREDICATE_CHAIN is true. This function will be called during
34169 version dispatch to decide which function version to execute. It returns
34170 the basic block at the end, to which more conditions can be added. */
34172 static basic_block
34175 {
34176 gimple return_stmt;
34178 gimple convert_stmt;
34179 gimple call_cond_stmt;
34180 gimple if_else_stmt;
34186 gimple_seq gseq;
34203 {
34211 }
34214 {
34229 else
34230 {
34231 gimple assign_stmt;
34232 /* Use MIN_EXPR to check if any integer is zero?.
34233 and_expr_var = min_expr <cond_var, and_expr_var> */
34241 }
34242 }
34245 integer_zero_node,
34275 }
34277 /* This parses the attribute arguments to target in DECL and determines
34278 the right builtin to use to match the platform specification.
34279 It returns the priority value for this version decl. If PREDICATE_LIST
34280 is not NULL, it stores the list of cpu features that need to be checked
34281 before dispatching this function. */
34283 static unsigned int
34285 {
34286 tree attrs;
34288 tree target_node;
34295 /* Priority of i386 features, greater value is higher priority. This is
34296 used to decide the order in which function dispatch must happen. For
34297 instance, a version specialized for SSE4.2 should be checked for dispatch
34298 before a version for SSE3, as SSE4.2 implies SSE3. */
34299 enum feature_priority
34300 {
34302 P_MMX,
34303 P_SSE,
34304 P_SSE2,
34305 P_SSE3,
34306 P_SSSE3,
34307 P_PROC_SSSE3,
34308 P_SSE4_A,
34309 P_PROC_SSE4_A,
34310 P_SSE4_1,
34311 P_SSE4_2,
34312 P_PROC_SSE4_2,
34313 P_POPCNT,
34314 P_AVX,
34315 P_PROC_AVX,
34316 P_BMI,
34317 P_PROC_BMI,
34318 P_FMA4,
34319 P_XOP,
34320 P_PROC_XOP,
34321 P_FMA,
34322 P_PROC_FMA,
34323 P_BMI2,
34324 P_AVX2,
34325 P_PROC_AVX2,
34326 P_AVX512F,
34327 P_PROC_AVX512F
34328 };
34332 /* These are the target attribute strings for which a dispatcher is
34333 available, from fold_builtin_cpu. */
34335 static struct _feature_list
34336 {
34339 }
34341 {
34359 };
34362 static unsigned int NUM_FEATURES
34378 /* Return priority zero for default function. */
34382 /* Handle arch= if specified. For priority, set it to be 1 more than
34383 the best instruction set the processor can handle. For instance, if
34384 there is a version for atom and a version for ssse3 (the highest ISA
34385 priority for atom), the atom version must be checked for dispatch
34386 before the ssse3 version. */
34388 {
34398 {
34400 {
34408 else
34409 /* We translate "arch=corei7" and "arch=nehalem" to
34410 "corei7" so that it will be mapped to M_INTEL_COREI7
34411 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34418 else
34425 else
34469 }
34470 }
34475 {
34479 }
34482 {
34484 /* For a C string literal the length includes the trailing NULL. */
34487 predicate_chain);
34488 }
34489 }
34491 /* Process feature name. */
34498 {
34499 /* Do not process "arch=" */
34501 {
34504 }
34506 {
34508 {
34510 {
34515 predicate_chain);
34516 }
34517 /* Find the maximum priority feature. */
34522 }
34523 }
34525 {
34529 }
34531 }
34535 {
34538 attrs_str);
34540 }
34542 {
34545 }
34548 }
34550 /* This compares the priority of target features in function DECL1
34551 and DECL2. It returns positive value if DECL1 is higher priority,
34552 negative value if DECL2 is higher priority and 0 if they are the
34553 same. */
34555 static int
34557 {
34562 }
34564 /* V1 and V2 point to function versions with different priorities
34565 based on the target ISA. This function compares their priorities. */
34567 static int
34569 {
34571 {
34572 tree version_decl;
34573 tree predicate_chain;
34580 }
34582 /* This function generates the dispatch function for
34583 multi-versioned functions. DISPATCH_DECL is the function which will
34584 contain the dispatch logic. FNDECLS are the function choices for
34585 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34586 in DISPATCH_DECL in which the dispatch code is generated. */
34588 static int
34592 {
34593 tree default_decl;
34594 gimple ifunc_cpu_init_stmt;
34595 gimple_seq gseq;
34597 tree ele;
34603 struct _function_version_info
34604 {
34605 tree version_decl;
34606 tree predicate_chain;
34614 /*fndecls_p is actually a vector. */
34617 /* At least one more version other than the default. */
34624 /* The first version in the vector is the default decl. */
34630 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34631 constructors, so explicity call __builtin_cpu_init here. */
34642 {
34646 /* Get attribute string, parse it and find the right predicate decl.
34647 The predicate function could be a lengthy combination of many
34648 features, like arch-type and various isa-variants. */
34659 actual_versions++;
34660 }
34662 /* Sort the versions according to descending order of dispatch priority. The
34663 priority is based on the ISA. This is not a perfect solution. There
34664 could still be ambiguity. If more than one function version is suitable
34665 to execute, which one should be dispatched? In future, allow the user
34666 to specify a dispatch priority next to the version. */
34676 /* dispatch default version at the end. */
34682 }
34684 /* Comparator function to be used in qsort routine to sort attribute
34685 specification strings to "target". */
34687 static int
34689 {
34693 }
34695 /* ARGLIST is the argument to target attribute. This function tokenizes
34696 the comma separated arguments, sorts them and returns a string which
34697 is a unique identifier for the comma separated arguments. It also
34698 replaces non-identifier characters "=,-" with "_". */
34702 {
34703 tree arg;
34712 {
34717 argnum++;
34720 argnum++;
34721 }
34726 {
34732 }
34734 /* Replace "=,-" with "_". */
34747 {
34749 i++;
34751 }
34758 {
34763 }
34768 }
34770 /* This function changes the assembler name for functions that are
34771 versions. If DECL is a function version and has a "target"
34772 attribute, it appends the attribute string to its assembler name. */
34774 static tree
34776 {
34777 tree version_attr;
34785 "Function versions cannot be marked as gnu_inline,"
34794 /* target attribute string cannot be NULL. */
34798 version_string
34809 /* Allow assembler name to be modified if already set. */
34817 }
34819 /* This function returns true if FN1 and FN2 are versions of the same function,
34820 that is, the target strings of the function decls are different. This assumes
34821 that FN1 and FN2 have the same signature. */
34823 static bool
34825 {
34837 /* At least one function decl should have the target attribute specified. */
34841 /* Diagnose missing target attribute if one of the decls is already
34842 multi-versioned. */
34844 {
34846 {
34848 {
34853 }
34856 fn2);
34859 /* Prevent diagnosing of the same error multiple times. */
34864 }
34866 }
34871 /* The sorted target strings must be different for fn1 and fn2
34872 to be versions. */
34875 else
34882 }
34884 static tree
34886 {
34887 /* For function version, add the target suffix to the assembler name. */
34891 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
34893 #endif
34896 }
34898 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
34899 is true, append the full path name of the source file. */
34903 {
34911 /* Get a unique name that can be used globally without any chances
34912 of collision at link time. */
34922 /* Use '.' to concatenate names as it is demangler friendly. */
34925 suffix);
34926 else
34930 }
34932 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34934 /* Make a dispatcher declaration for the multi-versioned function DECL.
34935 Calls to DECL function will be replaced with calls to the dispatcher
34936 by the front-end. Return the decl created. */
34938 static tree
34940 {
34941 tree func_decl;
34961 /* Mark this func as external, the resolver will flip it again if
34962 it gets generated. */
34964 /* This will be of type IFUNCs have to be externally visible. */
34968 }
34970 #endif
34972 /* Returns true if decl is multi-versioned and DECL is the default function,
34973 that is it is not tagged with target specific optimization. */
34975 static bool
34977 {
34986 }
34988 /* Make a dispatcher declaration for the multi-versioned function DECL.
34989 Calls to DECL function will be replaced with calls to the dispatcher
34990 by the front-end. Returns the decl of the dispatcher function. */
34992 static tree
34994 {
35016 /* Find the default version and make it the first node. */
35018 /* Go to the beginning of the chain. */
35023 {
35028 }
35030 /* If there is no default node, just return NULL. */
35034 /* Make default info the first node. */
35036 {
35043 }
35047 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35049 {
35054 /* Right now, the dispatching is done via ifunc. */
35060 dispatcher_version_info
35065 /* Set the dispatcher for all the versions. */
35068 {
35071 }
35072 }
35073 else
35074 #endif
35075 {
35077 "multiversioning needs ifunc which is not supported "
35079 }
35082 }
35084 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35085 it to CHAIN. */
35087 static tree
35089 {
35090 tree attr_name;
35091 tree attr_arg_name;
35092 tree attr_args;
35093 tree attr;
35100 }
35102 /* Make the resolver function decl to dispatch the versions of
35103 a multi-versioned function, DEFAULT_DECL. Create an
35104 empty basic block in the resolver and store the pointer in
35105 EMPTY_BB. Return the decl of the resolver function. */
35107 static tree
35111 {
35116 /* IFUNC's have to be globally visible. So, if the default_decl is
35117 not, then the name of the IFUNC should be made unique. */
35121 /* Append the filename to the resolver function if the versions are
35122 not externally visible. This is because the resolver function has
35123 to be externally visible for the loader to find it. So, appending
35124 the filename will prevent conflicts with a resolver function from
35125 another module which is based on the same version name. */
35128 /* The resolver function should return a (void *). */
35139 /* IFUNC resolvers have to be externally visible. */
35143 /* Resolver is not external, body is generated. */
35153 {
35154 /* In this case, each translation unit with a call to this
35155 versioned function will put out a resolver. Ensure it
35156 is comdat to keep just one copy. */
35159 }
35160 /* Build result decl and add to function_decl. */
35176 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35180 /* Create the alias for dispatch to resolver here. */
35181 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35185 }
35187 /* Generate the dispatching code body to dispatch multi-versioned function
35188 DECL. The target hook is called to process the "target" attributes and
35189 provide the code to dispatch the right function at run-time. NODE points
35190 to the dispatcher decl whose body will be created. */
35192 static tree
35194 {
35195 tree resolver_decl;
35196 basic_block empty_bb;
35197 tree default_ver_decl;
35213 /* The first version in the chain corresponds to the default version. */
35216 /* node is going to be an alias, so remove the finalized bit. */
35230 {
35232 /* Check for virtual functions here again, as by this time it should
35233 have been determined if this function needs a vtable index or
35234 not. This happens for methods in derived classes that override
35235 virtual methods in base classes but are not explicitly marked as
35236 virtual. */
35241 }
35247 }
35248 /* This builds the processor_model struct type defined in
35249 libgcc/config/i386/cpuinfo.c */
35251 static tree
35253 {
35260 /* The first 3 fields are unsigned int. */
35262 {
35268 }
35270 /* The last field is an array of unsigned integers of size one. */
35281 }
35283 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35285 static tree
35287 {
35288 tree new_decl;
35291 VAR_DECL,
35293 type);
35306 }
35308 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35309 into an integer defined in libgcc/config/i386/cpuinfo.c */
35311 static tree
35313 {
35319 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35320 enum processor_features
35321 {
35323 F_MMX,
35324 F_POPCNT,
35325 F_SSE,
35326 F_SSE2,
35327 F_SSE3,
35328 F_SSSE3,
35329 F_SSE4_1,
35330 F_SSE4_2,
35331 F_AVX,
35332 F_AVX2,
35333 F_SSE4_A,
35334 F_FMA4,
35335 F_XOP,
35336 F_FMA,
35337 F_AVX512F,
35338 F_BMI,
35339 F_BMI2,
35340 F_MAX
35341 };
35343 /* These are the values for vendor types and cpu types and subtypes
35344 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35345 the corresponding start value. */
35346 enum processor_model
35347 {
35349 M_AMD,
35350 M_CPU_TYPE_START,
35351 M_INTEL_BONNELL,
35352 M_INTEL_CORE2,
35353 M_INTEL_COREI7,
35354 M_AMDFAM10H,
35355 M_AMDFAM15H,
35356 M_INTEL_SILVERMONT,
35357 M_INTEL_KNL,
35358 M_AMD_BTVER1,
35359 M_AMD_BTVER2,
35360 M_CPU_SUBTYPE_START,
35361 M_INTEL_COREI7_NEHALEM,
35362 M_INTEL_COREI7_WESTMERE,
35363 M_INTEL_COREI7_SANDYBRIDGE,
35364 M_AMDFAM10H_BARCELONA,
35365 M_AMDFAM10H_SHANGHAI,
35366 M_AMDFAM10H_ISTANBUL,
35367 M_AMDFAM15H_BDVER1,
35368 M_AMDFAM15H_BDVER2,
35369 M_AMDFAM15H_BDVER3,
35370 M_AMDFAM15H_BDVER4,
35371 M_INTEL_COREI7_IVYBRIDGE,
35372 M_INTEL_COREI7_HASWELL,
35373 M_INTEL_COREI7_BROADWELL
35374 };
35376 static struct _arch_names_table
35377 {
35380 }
35382 {
35409 };
35411 static struct _isa_names_table
35412 {
35415 }
35417 {
35436 };
35450 {
35451 /* *args must be a expr that can contain other EXPRS leading to a
35452 STRING_CST. */
35454 {
35457 }
35459 }
35464 {
35465 tree ref;
35466 tree field;
35467 tree final;
35470 unsigned int NUM_ARCH_NAMES
35479 {
35483 }
35488 /* CPU types are stored in the next field. */
35491 {
35494 }
35496 /* CPU subtypes are stored in the next field. */
35498 {
35501 }
35503 /* Get the appropriate field in __cpu_model. */
35507 /* Check the value. */
35511 }
35513 {
35514 tree ref;
35515 tree array_elt;
35516 tree field;
35517 tree final;
35520 unsigned int NUM_ISA_NAMES
35529 {
35533 }
35536 /* Get the last field, which is __cpu_features. */
35540 /* Get the appropriate field: __cpu_model.__cpu_features */
35544 /* Access the 0th element of __cpu_features array. */
35549 /* Return __cpu_model.__cpu_features[0] & field_val */
35553 }
35555 }
35557 static tree
35560 {
35562 {
35567 {
35570 }
35571 }
35573 #ifdef SUBTARGET_FOLD_BUILTIN
35575 #endif
35578 }
35580 /* Make builtins to detect cpu type and features supported. NAME is
35581 the builtin name, CODE is the builtin code, and FTYPE is the function
35582 type of the builtin. */
35584 static void
35587 {
35588 tree decl;
35589 tree type;
35597 }
35599 /* Make builtins to get CPU type and features supported. The created
35600 builtins are :
35602 __builtin_cpu_init (), to detect cpu type and features,
35603 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35604 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35605 */
35607 static void
35609 {
35616 }
35618 /* Internal method for ix86_init_builtins. */
35620 static void
35622 {
35634 sysv_va_ref =
35637 fnvoid_va_end_ms =
35639 fnvoid_va_start_ms =
35641 fnvoid_va_end_sysv =
35643 fnvoid_va_start_sysv =
35645 NULL_TREE);
35646 fnvoid_va_copy_ms =
35648 NULL_TREE);
35649 fnvoid_va_copy_sysv =
35665 }
35667 static void
35669 {
35672 /* The __float80 type. */
35675 {
35676 /* The __float80 type. */
35681 }
35684 /* The __float128 type. */
35690 /* This macro is built by i386-builtin-types.awk. */
35691 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35692 }
35694 static void
35696 {
35697 tree t;
35701 /* Builtins to get CPU type and features. */
35704 /* TFmode support builtins. */
35710 /* We will expand them to normal call if SSE isn't available since
35711 they are used by libgcc. */
35731 #ifdef SUBTARGET_INIT_BUILTINS
35732 SUBTARGET_INIT_BUILTINS;
35733 #endif
35734 }
35736 /* Return the ix86 builtin for CODE. */
35738 static tree
35740 {
35745 }
35747 /* Errors in the source file can cause expand_expr to return const0_rtx
35748 where we expect a vector. To avoid crashing, use one of the vector
35749 clear instructions. */
35750 static rtx
35752 {
35756 }
35758 /* Fixup modeless constants to fit required mode. */
35759 static rtx
35761 {
35765 }
35767 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35769 static rtx
35771 {
35772 rtx pat;
35792 {
35796 }
35810 }
35812 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
35814 static rtx
35818 {
35819 rtx pat;
35827 rtx op;
35828 machine_mode mode;
35834 {
35914 }
35924 {
35931 {
35933 {
35936 {
35954 xop_rotl:
35956 {
35959 gcc_checking_assert
35961 }
35962 else
35963 {
35964 gcc_checking_assert
35975 }
35979 }
35980 }
35981 }
35982 else
35983 {
35984 non_constant:
35988 /* If we aren't optimizing, only allow one memory operand to be
35989 generated. */
35991 num_memory++;
35999 }
36003 }
36006 {
36017 else
36018 {
36024 }
36037 }
36044 }
36046 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
36047 insns with vec_merge. */
36049 static rtx
36051 rtx target)
36052 {
36053 rtx pat;
36080 }
36082 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36084 static rtx
36087 {
36088 rtx pat;
36093 rtx op2;
36104 /* Swap operands if we have a comparison that isn't available in
36105 hardware. */
36127 }
36129 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36131 static rtx
36133 rtx target)
36134 {
36135 rtx pat;
36149 /* Swap operands if we have a comparison that isn't available in
36150 hardware. */
36173 const0_rtx)));
36176 }
36178 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36180 static rtx
36182 rtx target)
36183 {
36184 rtx pat;
36209 }
36211 static rtx
36214 {
36215 rtx pat;
36220 rtx op2;
36247 }
36249 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36251 static rtx
36253 rtx target)
36254 {
36255 rtx pat;
36288 const0_rtx)));
36291 }
36293 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36295 static rtx
36298 {
36299 rtx pat;
36337 {
36340 }
36343 {
36352 }
36354 {
36363 }
36364 else
36365 {
36372 }
36380 {
36385 emit_insn
36389 FLAGS_REG),
36390 const0_rtx)));
36392 }
36393 else
36395 }
36398 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36400 static rtx
36403 {
36404 rtx pat;
36432 {
36435 }
36438 {
36447 }
36449 {
36458 }
36459 else
36460 {
36467 }
36475 {
36480 emit_insn
36484 FLAGS_REG),
36485 const0_rtx)));
36487 }
36488 else
36490 }
36492 /* Subroutine of ix86_expand_builtin to take care of insns with
36493 variable number of operands. */
36495 static rtx
36498 {
36504 struct
36505 {
36506 rtx op;
36507 machine_mode mode;
36518 {
37228 }
37233 {
37236 }
37239 {
37246 }
37247 else
37248 {
37251 }
37254 {
37261 {
37262 /* SIMD shift insns take either an 8-bit immediate or
37263 register as count. But builtin functions take int as
37264 count. If count doesn't match, we put it in register. */
37266 {
37270 }
37271 }
37274 {
37277 {
37386 {
37390 {
37393 }
37399 }
37401 }
37402 }
37403 else
37404 {
37408 /* If we aren't optimizing, only allow one memory operand to
37409 be generated. */
37411 num_memory++;
37416 {
37419 }
37420 else
37421 {
37424 }
37425 }
37429 }
37432 {
37457 }
37464 }
37466 /* Transform pattern of following layout:
37467 (parallel [
37468 set (A B)
37469 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37470 ])
37471 into:
37472 (set (A B))
37474 Or:
37475 (parallel [ A B
37476 ...
37477 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37478 ...
37479 ])
37480 into:
37481 (parallel [ A B ... ]) */
37483 static rtx
37485 {
37492 {
37501 }
37502 else
37503 {
37509 {
37514 }
37516 /* No more than 1 occurence was removed. */
37520 }
37521 }
37523 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37524 with rounding. */
37525 static rtx
37528 {
37545 /* See avxintrin.h for values. */
37547 {
37551 };
37553 {
37558 };
37561 {
37564 }
37566 {
37569 }
37572 {
37575 }
37598 ? CODE_FOR_sse_ucomi_round
37605 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37607 {
37613 }
37614 else
37615 {
37618 }
37624 set_dst,
37625 const0_rtx)));
37628 }
37630 static rtx
37633 {
37634 rtx pat;
37636 struct
37637 {
37638 rtx op;
37639 machine_mode mode;
37648 {
37731 }
37741 {
37748 {
37750 {
37752 {
37768 }
37769 }
37770 }
37772 {
37774 {
37777 }
37779 /* If there is no rounding use normal version of the pattern. */
37782 }
37783 else
37784 {
37791 {
37794 }
37795 else
37796 {
37799 }
37800 }
37804 }
37807 {
37832 }
37842 }
37844 /* Subroutine of ix86_expand_builtin to take care of special insns
37845 with variable number of operands. */
37847 static rtx
37850 {
37851 tree arg;
37855 struct
37856 {
37857 rtx op;
37858 machine_mode mode;
37867 {
37907 {
37915 }
37934 /* Reserve memory operand for target. */
37937 {
37938 /* These builtins and instructions require the memory
37939 to be properly aligned. */
37958 }
37987 {
37988 /* These builtins and instructions require the memory
37989 to be properly aligned. */
38006 }
38007 /* FALLTHRU */
38045 /* Reserve memory operand for target. */
38072 {
38073 /* These builtins and instructions require the memory
38074 to be properly aligned. */
38097 }
38110 }
38115 {
38120 {
38123 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38124 on it. Try to improve it using get_pointer_alignment,
38125 and if the special builtin is one that requires strict
38126 mode alignment, also from it's GET_MODE_ALIGNMENT.
38127 Failure to do so could lead to ix86_legitimate_combined_insn
38128 rejecting all changes to such insns. */
38134 }
38135 else
38138 }
38139 else
38140 {
38147 }
38150 {
38159 {
38161 {
38167 else
38170 }
38171 }
38172 else
38173 {
38175 {
38176 /* This must be the memory operand. */
38179 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38180 on it. Try to improve it using get_pointer_alignment,
38181 and if the special builtin is one that requires strict
38182 mode alignment, also from it's GET_MODE_ALIGNMENT.
38183 Failure to do so could lead to ix86_legitimate_combined_insn
38184 rejecting all changes to such insns. */
38190 }
38191 else
38192 {
38193 /* This must be register. */
38201 else
38202 {
38205 }
38206 }
38207 }
38211 }
38214 {
38229 }
38235 }
38237 /* Return the integer constant in ARG. Constrain it to be in the range
38238 of the subparts of VEC_TYPE; issue an error if not. */
38240 static int
38242 {
38247 {
38250 }
38253 }
38255 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38256 ix86_expand_vector_init. We DO have language-level syntax for this, in
38257 the form of (type){ init-list }. Except that since we can't place emms
38258 instructions from inside the compiler, we can't allow the use of MMX
38259 registers unless the user explicitly asks for it. So we do *not* define
38260 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38261 we have builtins invoked by mmintrin.h that gives us license to emit
38262 these sorts of instructions. */
38264 static rtx
38266 {
38276 {
38279 }
38286 }
38288 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38289 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38290 had a language-level syntax for referencing vector elements. */
38292 static rtx
38294 {
38298 rtx op0;
38318 }
38320 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38321 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38322 a language-level syntax for referencing vector elements. */
38324 static rtx
38326 {
38350 /* OP0 is the source of these builtin functions and shouldn't be
38351 modified. Create a copy, use it and return it as target. */
38357 }
38359 /* Emit conditional move of SRC to DST with condition
38360 OP1 CODE OP2. */
38361 static void
38363 {
38364 rtx t;
38367 {
38372 }
38373 else
38374 {
38380 }
38381 }
38383 /* Choose max of DST and SRC and put it to DST. */
38384 static void
38386 {
38388 }
38390 /* Expand an expression EXP that calls a built-in function,
38391 with result going to TARGET if that's convenient
38392 (and in mode MODE if that's convenient).
38393 SUBTARGET may be used as the target for computing one of EXP's operands.
38394 IGNORE is nonzero if the value is to be ignored. */
38396 static rtx
38399 {
38409 /* For CPU builtins that can be folded, fold first and expand the fold. */
38411 {
38413 {
38414 /* Make it call __cpu_indicator_init in libgcc. */
38420 }
38423 {
38428 }
38429 }
38431 /* Determine whether the builtin function is available under the current ISA.
38432 Originally the builtin was not created if it wasn't applicable to the
38433 current ISA based on the command line switches. With function specific
38434 options, we need to check in the context of the function making the call
38435 whether it is supported. */
38438 {
38444 else
38445 {
38449 }
38451 }
38454 {
38472 /* Builtin arg1 is size of block but instruction op1 should
38473 be (size - 1). */
38564 /* If no bounds were specified for returned value,
38565 then use INIT bounds. It usually happens when
38566 some built-in function is expanded. */
38568 {
38577 }
38583 {
38586 /* Return value and lb. */
38588 /* Bounds. */
38590 /* Size. */
38597 /* Size was passed but we need to use (size - 1) as for bndmk. */
38601 /* Add LB to size and inverse to get UB. */
38611 /* We need to move bounds to memory before any computations. */
38614 else
38615 {
38618 }
38620 /* Generate mem expression to be used for access to LB and UB. */
38626 /* Compute LB. */
38631 /* Compute UB. UB is stored in 1's complement form. Therefore
38632 we also use max here. */
38641 }
38644 {
38662 /* Put first bounds to temporaries. */
38666 {
38670 }
38671 else
38672 {
38676 }
38678 /* Put second bounds to temporaries. */
38682 {
38686 }
38687 else
38688 {
38692 }
38694 /* Compute LB. */
38698 /* Compute UB. UB is stored in 1's complement form. Therefore
38699 we also use max here. */
38706 }
38709 {
38710 tree name;
38711 rtx symbol;
38729 }
38732 {
38743 /* We need to move bounds to memory first. */
38746 else
38747 {
38750 }
38752 /* Generate mem expression to access LB and load it. */
38757 }
38760 {
38771 /* We need to move bounds to memory first. */
38774 else
38775 {
38778 }
38780 /* Generate mem expression to access UB. */
38783 /* We need to inverse all bits of UB. */
38790 }
38795 ? CODE_FOR_mmx_maskmovq
38797 /* Note the arg order is different from the operand order. */
38918 {
38919 REAL_VALUE_TYPE inf;
38920 rtx tmp;
38932 }
38942 {
38948 insn = (TARGET_64BIT
38952 }
38954 {
38955 insn = (TARGET_64BIT
38959 }
38960 else
38961 {
38964 insn = (TARGET_64BIT
38972 {
38975 }
38977 }
38980 {
38981 /* mode is VOIDmode if __builtin_rd* has been called
38982 without lhs. */
38986 }
38989 {
38994 }
39007 {
39028 }
39034 {
39037 }
39063 {
39066 }
39072 {
39076 {
39115 }
39120 }
39121 else
39122 {
39124 {
39145 }
39147 }
39177 ? CODE_FOR_tbm_bextri_si
39180 {
39183 }
39184 else
39185 {
39194 }
39210 rdrand_step:
39217 {
39220 }
39226 /* Emit SImode conditional move. */
39228 {
39231 }
39234 else
39242 const0_rtx);
39261 rdseed_step:
39268 {
39271 }
39277 const0_rtx);
39306 addcarryx:
39314 /* Generate CF from input operand. */
39319 /* Gen ADCX instruction to compute X+Y+CF. */
39334 /* Store the result. */
39337 {
39340 }
39343 /* Return current CF value. */
39385 kortest:
39399 /* Emit kortest. */
39401 /* And use setcc to return result from flags. */
39659 gather_gen:
39660 rtx half;
39673 /* Note the arg order is different from the operand order. */
39684 else
39688 {
39712 else
39719 {
39724 }
39733 else
39740 {
39745 }
39749 }
39751 /* Force memory operand only with base register here. But we
39752 don't want to do it on memory operand for other builtin
39753 functions. */
39766 {
39769 }
39770 else
39771 {
39774 }
39776 {
39779 }
39781 /* Optimize. If mask is known to have all high bits set,
39782 replace op0 with pc_rtx to signal that the instruction
39783 overwrites the whole destination and doesn't use its
39784 previous contents. */
39786 {
39788 {
39791 }
39793 {
39796 {
39800 negative++;
39803 negative++;
39804 }
39807 }
39810 {
39811 /* Recognize also when mask is like:
39812 __v2df src = _mm_setzero_pd ();
39813 __v2df mask = _mm_cmpeq_pd (src, src);
39814 or
39815 __v8sf src = _mm256_setzero_ps ();
39816 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
39817 as that is a cheaper way to load all ones into
39818 a register than having to load a constant from
39819 memory. */
39822 {
39827 {
39834 /* FALLTHRU */
39844 }
39845 }
39846 }
39847 }
39855 {
39881 }
39884 scatter_gen:
39900 /* Force memory operand only with base register here. But we
39901 don't want to do it on memory operand for other builtin
39902 functions. */
39911 {
39914 }
39915 else
39916 {
39919 }
39928 {
39931 }
39940 vec_prefetch_gen:
39960 {
39963 }
39965 {
39968 }
39973 /* Force memory operand only with base register here. But we
39974 don't want to do it on memory operand for other builtin
39975 functions. */
39982 {
39985 }
39988 {
39991 }
40007 {
40010 }
40016 }
40029 {
40033 /* Emit a normal call if SSE isn't available. */
40037 }
40066 }
40068 /* This returns the target-specific builtin with code CODE if
40069 current_function_decl has visibility on this builtin, which is checked
40070 using isa flags. Returns NULL_TREE otherwise. */
40073 {
40077 /* Determine the isa flags of current_function_decl. */
40089 else
40091 }
40093 /* Return function decl for target specific builtin
40094 for given MPX builtin passed i FCODE. */
40095 static tree
40097 {
40099 {
40135 }
40138 }
40140 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40142 Return an address to be used to load/store bounds for pointer
40143 passed in SLOT.
40145 SLOT_NO is an integer constant holding number of a target
40146 dependent special slot to be used in case SLOT is not a memory.
40148 SPECIAL_BASE is a pointer to be used as a base of fake address
40149 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40150 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40152 static rtx
40154 {
40157 /* NULL slot means we pass bounds for pointer not passed to the
40158 function at all. Register slot means we pass pointer in a
40159 register. In both these cases bounds are passed via Bounds
40160 Table. Since we do not have actual pointer stored in memory,
40161 we have to use fake addresses to access Bounds Table. We
40162 start with (special_base - sizeof (void*)) and decrease this
40163 address by pointer size to get addresses for other slots. */
40165 {
40169 }
40170 /* If pointer is passed in a memory then its address is used to
40171 access Bounds Table. */
40173 {
40177 }
40178 else
40182 }
40184 /* Expand pass uses this hook to load bounds for function parameter
40185 PTR passed in SLOT in case its bounds are not passed in a register.
40187 If SLOT is a memory, then bounds are loaded as for regular pointer
40188 loaded from memory. PTR may be NULL in case SLOT is a memory.
40189 In such case value of PTR (if required) may be loaded from SLOT.
40191 If SLOT is NULL or a register then SLOT_NO is an integer constant
40192 holding number of the target dependent special slot which should be
40193 used to obtain bounds.
40195 Return loaded bounds. */
40197 static rtx
40199 {
40201 rtx addr;
40203 /* Get address to be used to access Bounds Table. Special slots start
40204 at the location of return address of the current function. */
40207 /* Load pointer value from a memory if we don't have it. */
40209 {
40212 }
40219 }
40221 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40222 passed in SLOT in case BOUNDS are not passed in a register.
40224 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40225 stored in memory. PTR may be NULL in case SLOT is a memory.
40226 In such case value of PTR (if required) may be loaded from SLOT.
40228 If SLOT is NULL or a register then SLOT_NO is an integer constant
40229 holding number of the target dependent special slot which should be
40230 used to store BOUNDS. */
40232 static void
40234 {
40235 rtx addr;
40237 /* Get address to be used to access Bounds Table. Special slots start
40238 at the location of return address of a called function. */
40241 /* Load pointer value from a memory if we don't have it. */
40243 {
40246 }
40255 }
40257 /* Load and return bounds returned by function in SLOT. */
40259 static rtx
40261 {
40262 rtx res;
40269 }
40271 /* Store BOUNDS returned by function into SLOT. */
40273 static void
40275 {
40278 }
40280 /* Returns a function decl for a vectorized version of the builtin function
40281 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40282 if it is not available. */
40284 static tree
40286 tree type_in)
40287 {
40303 {
40306 {
40313 }
40318 {
40321 }
40326 {
40333 }
40339 /* The round insn does not trap on denormals. */
40344 {
40351 }
40357 /* The round insn does not trap on denormals. */
40362 {
40367 }
40373 /* The round insn does not trap on denormals. */
40378 {
40385 }
40391 /* The round insn does not trap on denormals. */
40396 {
40401 }
40408 {
40413 }
40420 {
40425 }
40431 /* The round insn does not trap on denormals. */
40436 {
40443 }
40449 /* The round insn does not trap on denormals. */
40454 {
40459 }
40464 {
40471 }
40476 {
40483 }
40487 /* The round insn does not trap on denormals. */
40492 {
40497 }
40501 /* The round insn does not trap on denormals. */
40506 {
40511 }
40515 /* The round insn does not trap on denormals. */
40520 {
40525 }
40529 /* The round insn does not trap on denormals. */
40534 {
40539 }
40543 /* The round insn does not trap on denormals. */
40548 {
40553 }
40557 /* The round insn does not trap on denormals. */
40562 {
40567 }
40571 /* The round insn does not trap on denormals. */
40576 {
40581 }
40585 /* The round insn does not trap on denormals. */
40590 {
40595 }
40599 /* The round insn does not trap on denormals. */
40604 {
40609 }
40613 /* The round insn does not trap on denormals. */
40618 {
40623 }
40628 {
40633 }
40638 {
40643 }
40648 }
40650 /* Dispatch to a handler for a vectorization library. */
40653 type_in);
40656 }
40658 /* Handler for an SVML-style interface to
40659 a library with vectorized intrinsics. */
40661 static tree
40663 {
40671 /* The SVML is suitable for unsafe math only. */
40684 {
40731 }
40740 {
40743 }
40744 else
40747 /* Convert to uppercase. */
40752 args;
40754 arity++;
40758 else
40761 /* Build a function declaration for the vectorized function. */
40770 }
40772 /* Handler for an ACML-style interface to
40773 a library with vectorized intrinsics. */
40775 static tree
40777 {
40785 /* The ACML is 64bits only and suitable for unsafe math only as
40786 it does not correctly support parts of IEEE with the required
40787 precision such as denormals. */
40801 {
40831 }
40838 args;
40840 arity++;
40844 else
40847 /* Build a function declaration for the vectorized function. */
40856 }
40858 /* Returns a decl of a function that implements gather load with
40859 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
40860 Return NULL_TREE if it is not available. */
40862 static tree
40865 {
40881 /* v*gather* insn sign extends index to pointer mode. */
40893 {
40897 else
40903 else
40909 else
40915 else
40921 else
40927 else
40933 else
40939 else
40945 else
40951 else
40957 else
40963 else
40968 }
40971 }
40973 /* Returns a code for a target-specific builtin that implements
40974 reciprocal of the function, or NULL_TREE if not available. */
40976 static tree
40978 {
40985 /* Machine dependent builtins. */
40987 {
40988 /* Vectorized version of sqrt to rsqrt conversion. */
40997 }
40998 else
40999 /* Normal builtins. */
41001 {
41002 /* Sqrt to rsqrt conversion. */
41008 }
41009 }
41010 \f
41011 /* Helper for avx_vpermilps256_operand et al. This is also used by
41012 the expansion functions to turn the parallel back into a mask.
41013 The return value is 0 for no match and the imm8+1 for a match. */
41015 int
41017 {
41025 /* Validate that all of the elements are constants, and not totally
41026 out of range. Copy the data into an integral array to make the
41027 subsequent checks easier. */
41029 {
41039 }
41042 {
41044 /* In the 512-bit DFmode case, we can only move elements within
41045 a 128-bit lane. First fill the second part of the mask,
41046 then fallthru. */
41048 {
41052 }
41054 {
41058 }
41059 /* FALLTHRU */
41062 /* In the 256-bit DFmode case, we can only move elements within
41063 a 128-bit lane. */
41065 {
41069 }
41071 {
41075 }
41079 /* In 512 bit SFmode case, permutation in the upper 256 bits
41080 must mirror the permutation in the lower 256-bits. */
41084 /* FALLTHRU */
41087 /* In 256 bit SFmode case, we have full freedom of
41088 movement within the low 128-bit lane, but the high 128-bit
41089 lane must mirror the exact same pattern. */
41094 /* FALLTHRU */
41098 /* In the 128-bit case, we've full freedom in the placement of
41099 the elements from the source operand. */
41106 }
41108 /* Make sure success has a non-zero value by adding one. */
41110 }
41112 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41113 the expansion functions to turn the parallel back into a mask.
41114 The return value is 0 for no match and the imm8+1 for a match. */
41116 int
41118 {
41126 /* Validate that all of the elements are constants, and not totally
41127 out of range. Copy the data into an integral array to make the
41128 subsequent checks easier. */
41130 {
41140 }
41142 /* Validate that the halves of the permute are halves. */
41150 /* Reconstruct the mask. */
41152 {
41158 }
41160 /* Make sure success has a non-zero value by adding one. */
41162 }
41163 \f
41164 /* Return a register priority for hard reg REGNO. */
41165 static int
41167 {
41168 /* ebp and r13 as the base always wants a displacement, r12 as the
41169 base always wants an index. So discourage their usage in an
41170 address. */
41175 /* New x86-64 int registers result in bigger code size. Discourage
41176 them. */
41179 /* New x86-64 SSE registers result in bigger code size. Discourage
41180 them. */
41183 /* Usage of AX register results in smaller code. Prefer it. */
41187 }
41189 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41191 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41192 QImode must go into class Q_REGS.
41193 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41194 movdf to do mem-to-mem moves through integer regs. */
41196 static reg_class_t
41198 {
41201 /* We're only allowed to return a subclass of CLASS. Many of the
41202 following checks fail for NO_REGS, so eliminate that early. */
41206 /* All classes can load zeros. */
41210 /* Force constants into memory if we are loading a (nonzero) constant into
41211 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41212 instructions to load from a constant. */
41219 /* Prefer SSE regs only, if we can use them for math. */
41223 /* Floating-point constants need more complex checks. */
41225 {
41226 /* General regs can load everything. */
41230 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41231 zero above. We only want to wind up preferring 80387 registers if
41232 we plan on doing computation with them. */
41235 {
41236 /* Limit class to non-sse. */
41245 }
41248 }
41250 /* Generally when we see PLUS here, it's the function invariant
41251 (plus soft-fp const_int). Which can only be computed into general
41252 regs. */
41256 /* QImode constants are easy to load, but non-constant QImode data
41257 must go into Q_REGS. */
41259 {
41265 }
41268 }
41270 /* Discourage putting floating-point values in SSE registers unless
41271 SSE math is being used, and likewise for the 387 registers. */
41272 static reg_class_t
41274 {
41277 /* Restrict the output reload class to the register bank that we are doing
41278 math on. If we would like not to return a subset of CLASS, reject this
41279 alternative: if reload cannot do this, it will still use its choice. */
41285 {
41290 else
41292 }
41295 }
41297 static reg_class_t
41300 {
41301 /* Double-word spills from general registers to non-offsettable memory
41302 references (zero-extended addresses) require special handling. */
41308 {
41310 ? CODE_FOR_reload_noff_load
41312 /* Add the cost of moving address to a temporary. */
41316 }
41318 /* QImode spills from non-QI registers require
41319 intermediate register on 32bit targets. */
41325 {
41330 else
41336 /* Return Q_REGS if the operand is in memory. */
41339 }
41341 /* This condition handles corner case where an expression involving
41342 pointers gets vectorized. We're trying to use the address of a
41343 stack slot as a vector initializer.
41345 (set (reg:V2DI 74 [ vect_cst_.2 ])
41346 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41348 Eventually frame gets turned into sp+offset like this:
41350 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41351 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41352 (const_int 392 [0x188]))))
41354 That later gets turned into:
41356 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41357 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41358 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41360 We'll have the following reload recorded:
41362 Reload 0: reload_in (DI) =
41363 (plus:DI (reg/f:DI 7 sp)
41364 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41365 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41366 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41367 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41368 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41369 reload_reg_rtx: (reg:V2DI 22 xmm1)
41371 Which isn't going to work since SSE instructions can't handle scalar
41372 additions. Returning GENERAL_REGS forces the addition into integer
41373 register and reload can handle subsequent reloads without problems. */
41381 }
41383 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41385 static bool
41387 {
41389 {
41405 }
41408 }
41410 /* If we are copying between general and FP registers, we need a memory
41411 location. The same is true for SSE and MMX registers.
41413 To optimize register_move_cost performance, allow inline variant.
41415 The macro can't work reliably when one of the CLASSES is class containing
41416 registers from multiple units (SSE, MMX, integer). We avoid this by never
41417 combining those units in single alternative in the machine description.
41418 Ensure that this constraint holds to avoid unexpected surprises.
41420 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41421 enforce these sanity checks. */
41426 {
41435 {
41438 }
41443 /* Between mask and general, we have moves no larger than word size. */
41448 /* ??? This is a lie. We do have moves between mmx/general, and for
41449 mmx/sse2. But by saying we need secondary memory we discourage the
41450 register allocator from using the mmx registers unless needed. */
41455 {
41456 /* SSE1 doesn't have any direct moves from other classes. */
41460 /* If the target says that inter-unit moves are more expensive
41461 than moving through memory, then don't generate them. */
41466 /* Between SSE and general, we have moves no larger than word size. */
41469 }
41472 }
41474 bool
41477 {
41479 }
41481 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41483 On the 80386, this is the size of MODE in words,
41484 except in the FP regs, where a single reg is always enough. */
41486 static unsigned char
41488 {
41490 {
41495 else
41497 }
41498 else
41499 {
41502 else
41504 }
41505 }
41507 /* Return true if the registers in CLASS cannot represent the change from
41508 modes FROM to TO. */
41510 bool
41513 {
41517 /* x87 registers can't do subreg at all, as all values are reformatted
41518 to extended precision. */
41523 {
41524 /* Vector registers do not support QI or HImode loads. If we don't
41525 disallow a change to these modes, reload will assume it's ok to
41526 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41527 the vec_dupv4hi pattern. */
41530 }
41533 }
41535 /* Return the cost of moving data of mode M between a
41536 register and memory. A value of 2 is the default; this cost is
41537 relative to those in `REGISTER_MOVE_COST'.
41539 This function is used extensively by register_move_cost that is used to
41540 build tables at startup. Make it inline in this case.
41541 When IN is 2, return maximum of in and out move cost.
41543 If moving between registers and memory is more expensive than
41544 between two registers, you should define this macro to express the
41545 relative cost.
41547 Model also increased moving costs of QImode registers in non
41548 Q_REGS classes.
41549 */
41553 {
41556 {
41559 {
41571 }
41575 }
41577 {
41580 {
41592 }
41596 }
41598 {
41601 {
41610 }
41614 }
41616 {
41619 {
41625 else
41630 }
41631 else
41632 {
41637 else
41639 }
41646 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41653 else
41657 }
41658 }
41660 static int
41663 {
41665 }
41668 /* Return the cost of moving data from a register in class CLASS1 to
41669 one in class CLASS2.
41671 It is not required that the cost always equal 2 when FROM is the same as TO;
41672 on some machines it is expensive to move between registers if they are not
41673 general registers. */
41675 static int
41677 reg_class_t class2_i)
41678 {
41682 /* In case we require secondary memory, compute cost of the store followed
41683 by load. In order to avoid bad register allocation choices, we need
41684 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41687 {
41693 /* In case of copying from general_purpose_register we may emit multiple
41694 stores followed by single load causing memory size mismatch stall.
41695 Count this as arbitrarily high cost of 20. */
41700 /* In the case of FP/MMX moves, the registers actually overlap, and we
41701 have to switch modes in order to treat them differently. */
41707 }
41709 /* Moves between SSE/MMX and integer unit are expensive. */
41713 /* ??? By keeping returned value relatively high, we limit the number
41714 of moves between integer and MMX/SSE registers for all targets.
41715 Additionally, high value prevents problem with x86_modes_tieable_p(),
41716 where integer modes in MMX/SSE registers are not tieable
41717 because of missing QImode and HImode moves to, from or between
41718 MMX/SSE registers. */
41728 }
41730 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41731 MODE. */
41733 bool
41735 {
41736 /* Flags and only flags can only hold CCmode values. */
41747 || (TARGET_AVX512BW
41752 {
41753 /* We implement the move patterns for all vector modes into and
41754 out of SSE registers, even when no operation instructions
41755 are available. */
41757 /* For AVX-512 we allow, regardless of regno:
41758 - XI mode
41759 - any of 512-bit wide vector mode
41760 - any scalar mode. */
41767 /* TODO check for QI/HI scalars. */
41768 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
41776 /* xmm16-xmm31 are only available for AVX-512. */
41780 /* OImode and AVX modes are available only when AVX is enabled. */
41787 }
41789 {
41790 /* We implement the move patterns for 3DNOW modes even in MMX mode,
41791 so if the register is available at all, then we can move data of
41792 the given mode into or out of it. */
41795 }
41798 {
41799 /* Take care for QImode values - they can be in non-QI regs,
41800 but then they do cause partial register stalls. */
41805 /* LRA checks if the hard register is OK for the given mode.
41806 QImode values can live in non-QI regs, so we allow all
41807 registers here. */
41811 }
41812 /* We handle both integer and floats in the general purpose registers. */
41819 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
41820 on to use that value in smaller contexts, this can easily force a
41821 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
41822 supporting DImode, allow it. */
41827 }
41829 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
41830 tieable integer mode. */
41832 static bool
41834 {
41836 {
41849 }
41850 }
41852 /* Return true if MODE1 is accessible in a register that can hold MODE2
41853 without copying. That is, all register classes that can hold MODE2
41854 can also hold MODE1. */
41856 bool
41858 {
41866 /* MODE2 being XFmode implies fp stack or general regs, which means we
41867 can tie any smaller floating point modes to it. Note that we do not
41868 tie this with TFmode. */
41872 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
41873 that we can tie it with SFmode. */
41877 /* If MODE2 is only appropriate for an SSE register, then tie with
41878 any other mode acceptable to SSE registers. */
41888 /* If MODE2 is appropriate for an MMX register, then tie
41889 with any other mode acceptable to MMX registers. */
41896 }
41898 /* Return the cost of moving between two registers of mode MODE. */
41900 static int
41902 {
41906 {
41938 }
41940 /* Return the cost of moving between two registers of mode MODE,
41941 assuming that the move will be in pieces of at most UNITS bytes. */
41943 }
41945 /* Compute a (partial) cost for rtx X. Return true if the complete
41946 cost has been computed, and false if subexpressions should be
41947 scanned. In either case, *TOTAL contains the cost result. */
41949 static bool
41952 {
41953 rtx mask;
41960 {
41964 {
41967 }
41979 && !(TARGET_64BIT
41984 else
41994 {
42004 }
42006 {
42009 {
42018 }
42019 }
42020 /* Fall back to (MEM (SYMBOL_REF)), since that's where
42021 it'll probably end up. Add a penalty for size. */
42028 /* The zero extensions is often completely free on x86_64, so make
42029 it as cheap as possible. */
42035 else
42047 {
42050 {
42053 }
42056 {
42059 }
42060 }
42061 /* FALLTHRU */
42068 {
42069 /* ??? Should be SSE vector operation cost. */
42070 /* At least for published AMD latencies, this really is the same
42071 as the latency for a simple fpu operation like fabs. */
42072 /* V*QImode is emulated with 1-11 insns. */
42074 {
42077 {
42078 /* For XOP we use vpshab, which requires a broadcast of the
42079 value to the variable shift insn. For constants this
42080 means a V16Q const in mem; even when we can perform the
42081 shift with one insn set the cost to prefer paddb. */
42083 {
42088 }
42090 }
42094 }
42095 else
42097 }
42099 {
42101 {
42104 else
42106 }
42107 else
42108 {
42111 else
42113 }
42114 }
42115 else
42116 {
42121 {
42122 /* Return the cost after shift-and truncation. */
42125 }
42126 else
42128 }
42132 {
42133 rtx sub;
42138 /* ??? SSE scalar/vector cost should be used here. */
42139 /* ??? Bald assumption that fma has the same cost as fmul. */
42143 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42154 }
42158 {
42159 /* ??? SSE scalar cost should be used here. */
42162 }
42164 {
42167 }
42169 {
42170 /* ??? SSE vector cost should be used here. */
42173 }
42175 {
42176 /* V*QImode is emulated with 7-13 insns. */
42178 {
42185 }
42186 /* V*DImode is emulated with 5-8 insns. */
42188 {
42191 else
42193 }
42194 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42195 insns, including two PMULUDQ. */
42198 else
42201 }
42202 else
42203 {
42208 {
42211 nbits++;
42212 }
42213 else
42214 /* This is arbitrary. */
42217 /* Compute costs correctly for widening multiplication. */
42221 {
42228 {
42232 else
42234 }
42238 }
42246 }
42253 /* ??? SSE cost should be used here. */
42258 /* ??? SSE vector cost should be used here. */
42260 else
42267 {
42272 {
42275 {
42283 }
42284 }
42287 {
42290 {
42296 }
42297 }
42299 {
42307 }
42308 }
42309 /* FALLTHRU */
42313 {
42314 /* ??? SSE cost should be used here. */
42317 }
42319 {
42322 }
42324 {
42325 /* ??? SSE vector cost should be used here. */
42328 }
42329 /* FALLTHRU */
42336 {
42343 }
42344 /* FALLTHRU */
42348 {
42349 /* ??? SSE cost should be used here. */
42352 }
42354 {
42357 }
42359 {
42360 /* ??? SSE vector cost should be used here. */
42363 }
42364 /* FALLTHRU */
42368 {
42369 /* ??? Should be SSE vector operation cost. */
42370 /* At least for published AMD latencies, this really is the same
42371 as the latency for a simple fpu operation like fabs. */
42373 }
42376 else
42385 {
42386 /* This kind of construct is implemented using test[bwl].
42387 Treat it as if we had an AND. */
42392 }
42402 /* ??? SSE cost should be used here. */
42407 /* ??? SSE vector cost should be used here. */
42413 /* ??? SSE cost should be used here. */
42418 /* ??? SSE vector cost should be used here. */
42430 /* ??? Assume all of these vector manipulation patterns are
42431 recognizable. In which case they all pretty much have the
42432 same cost. */
42437 /* This is masked instruction, assume the same cost,
42438 as nonmasked variant. */
42441 else
42447 }
42448 }
42450 #if TARGET_MACHO
42454 /* Given a symbol name and its associated stub, write out the
42455 definition of the stub. */
42457 void
42459 {
42464 /* For 64-bit we shouldn't get here. */
42467 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42484 else
42491 {
42493 }
42495 {
42496 /* PIC stub. */
42497 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42503 }
42504 else
42507 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42508 it needs no stub-binding-helper. */
42515 {
42518 }
42519 else
42524 /* N.B. Keep the correspondence of these
42525 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42526 old-pic/new-pic/non-pic stubs; altering this will break
42527 compatibility with existing dylibs. */
42529 {
42530 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42532 }
42533 else
42534 /* 16-byte -mdynamic-no-pic stub. */
42540 }
42543 /* Order the registers for register allocator. */
42545 void
42547 {
42551 /* First allocate the local general purpose registers. */
42556 /* Global general purpose registers. */
42561 /* x87 registers come first in case we are doing FP math
42562 using them. */
42567 /* SSE registers. */
42573 /* Extended REX SSE registers. */
42577 /* Mask register. */
42581 /* MPX bound registers. */
42585 /* x87 registers. */
42593 /* Initialize the rest of array as we do not allocate some registers
42594 at all. */
42597 }
42599 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42600 in struct attribute_spec handler. */
42601 static tree
42603 tree args,
42606 {
42611 {
42613 name);
42616 }
42618 {
42620 name);
42623 }
42625 {
42626 tree cst;
42630 {
42633 name);
42635 }
42638 {
42641 name);
42643 }
42646 }
42649 }
42651 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42652 struct attribute_spec.handler. */
42653 static tree
42656 {
42661 {
42663 name);
42666 }
42668 /* Can combine regparm with all attributes but fastcall. */
42670 {
42672 {
42674 }
42677 }
42679 {
42681 {
42683 }
42686 }
42689 }
42691 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42692 struct attribute_spec.handler. */
42693 static tree
42696 {
42699 {
42702 }
42703 else
42707 {
42709 name);
42711 }
42717 {
42719 name);
42721 }
42724 }
42726 static tree
42729 {
42731 {
42733 name);
42735 }
42737 }
42739 static bool
42741 {
42745 }
42747 /* Returns an expression indicating where the this parameter is
42748 located on entry to the FUNCTION. */
42750 static rtx
42752 {
42758 {
42763 else
42766 }
42771 {
42778 {
42783 }
42784 else
42785 {
42788 {
42794 }
42795 }
42797 }
42801 }
42803 /* Determine whether x86_output_mi_thunk can succeed. */
42805 static bool
42807 const_tree function)
42808 {
42809 /* 64-bit can handle anything. */
42813 /* For 32-bit, everything's fine if we have one free register. */
42817 /* Need a free register for vcall_offset. */
42821 /* Need a free register for GOT references. */
42825 /* Otherwise ok. */
42827 }
42829 /* Output the assembler code for a thunk function. THUNK_DECL is the
42830 declaration for the thunk function itself, FUNCTION is the decl for
42831 the target function. DELTA is an immediate constant offset to be
42832 added to THIS. If VCALL_OFFSET is nonzero, the word at
42833 *(*this + vcall_offset) should be added to THIS. */
42835 static void
42838 {
42846 else
42847 {
42853 else
42855 }
42859 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
42860 pull it in now and let DELTA benefit. */
42864 {
42865 /* Put the this parameter into %eax. */
42868 }
42869 else
42872 /* Adjust the this parameter by a fixed constant. */
42874 {
42879 {
42881 {
42885 }
42886 }
42889 }
42891 /* Adjust the this parameter by a value stored in the vtable. */
42893 {
42903 /* Adjust the this parameter. */
42907 {
42911 }
42918 vcall_mem));
42919 else
42921 }
42923 /* If necessary, drop THIS back to its stack slot. */
42929 {
42932 ;
42933 else
42934 {
42938 }
42939 }
42940 else
42941 {
42943 ;
42944 #if TARGET_MACHO
42946 {
42949 }
42951 else
42952 {
42960 }
42961 }
42963 /* Our sibling call patterns do not allow memories, because we have no
42964 predicate that can distinguish between frame and non-frame memory.
42965 For our purposes here, we can get away with (ab)using a jump pattern,
42966 because we're going to do no optimization. */
42968 {
42970 {
42976 }
42977 else
42979 }
42980 else
42981 {
42983 {
42984 // CM_LARGE_PIC always uses pseudo PIC register which is
42985 // uninitialized. Since FUNCTION is local and calling it
42986 // doesn't go through PLT, we use scratch register %r11 as
42987 // PIC register and initialize it here.
42992 }
42995 {
43001 }
43007 }
43010 /* Emit just enough of rest_of_compilation to get the insns emitted.
43011 Note that use_thunk calls assemble_start_function et al. */
43017 }
43019 static void
43021 {
43025 #if TARGET_MACHO
43027 #endif
43034 }
43036 int
43038 {
43039 machine_mode mode;
43050 }
43052 /* Print call to TARGET to FILE. */
43054 static void
43056 {
43059 else
43061 }
43063 /* Output assembler code to FILE to increment profiler label # LABELNO
43064 for profiling a function entry. */
43065 void
43067 {
43071 {
43072 #ifndef NO_PROFILE_COUNTERS
43074 #endif
43078 else
43080 }
43082 {
43083 #ifndef NO_PROFILE_COUNTERS
43086 #endif
43088 }
43089 else
43090 {
43091 #ifndef NO_PROFILE_COUNTERS
43094 #endif
43096 }
43099 {
43103 }
43104 }
43106 /* We don't have exact information about the insn sizes, but we may assume
43107 quite safely that we are informed about all 1 byte insns and memory
43108 address sizes. This is enough to eliminate unnecessary padding in
43109 99% of cases. */
43111 static int
43113 {
43119 /* Discard alignments we've emit and jump instructions. */
43124 /* Important case - calls are always 5 bytes.
43125 It is common to have many calls in the row. */
43134 /* For normal instructions we rely on get_attr_length being exact,
43135 with a few exceptions. */
43137 {
43141 {
43151 /* Otherwise trust get_attr_length. */
43153 }
43158 }
43161 else
43163 }
43165 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43167 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43168 window. */
43170 static void
43172 {
43177 /* Look for all minimal intervals of instructions containing 4 jumps.
43178 The intervals are bounded by START and INSN. NBYTES is the total
43179 size of instructions in the interval including INSN and not including
43180 START. When the NBYTES is smaller than 16 bytes, it is possible
43181 that the end of START and INSN ends up in the same 16byte page.
43183 The smallest offset in the page INSN can start is the case where START
43184 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43185 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43187 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43188 have to, control transfer to label(s) can be performed through other
43189 means, and also we estimate minimum length of all asm stmts as 0. */
43191 {
43195 {
43201 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43202 already in the current 16 byte page, because otherwise
43203 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43204 bytes to reach 16 byte boundary. */
43212 {
43214 {
43219 else
43222 }
43223 }
43225 }
43234 njumps++;
43235 else
43239 {
43244 else
43247 }
43254 {
43261 }
43262 }
43263 }
43264 #endif
43266 /* AMD Athlon works faster
43267 when RET is not destination of conditional jump or directly preceded
43268 by other jump instruction. We avoid the penalty by inserting NOP just
43269 before the RET instructions in such cases. */
43270 static void
43272 {
43273 edge e;
43274 edge_iterator ei;
43277 {
43290 {
43291 edge e;
43292 edge_iterator ei;
43297 {
43300 }
43301 }
43303 {
43309 /* Empty functions get branch mispredict even when
43310 the jump destination is not visible to us. */
43313 }
43315 {
43318 }
43319 }
43320 }
43322 /* Count the minimum number of instructions in BB. Return 4 if the
43323 number of instructions >= 4. */
43325 static int
43327 {
43331 /* Count number of instructions in this block. Return 4 if the number
43332 of instructions >= 4. */
43334 {
43335 /* Only happen in exit blocks. */
43343 {
43344 insn_count++;
43347 }
43348 }
43351 }
43354 /* Count the minimum number of instructions in code path in BB.
43355 Return 4 if the number of instructions >= 4. */
43357 static int
43359 {
43360 edge e;
43361 edge_iterator ei;
43364 /* Only bother counting instructions along paths with no
43365 more than 2 basic blocks between entry and exit. Given
43366 that BB has an edge to exit, determine if a predecessor
43367 of BB has an edge from entry. If so, compute the number
43368 of instructions in the predecessor block. If there
43369 happen to be multiple such blocks, compute the minimum. */
43372 {
43373 edge prev_e;
43374 edge_iterator prev_ei;
43377 {
43380 }
43382 {
43384 {
43389 }
43390 }
43391 }
43397 }
43399 /* Pad short function to 4 instructions. */
43401 static void
43403 {
43404 edge e;
43405 edge_iterator ei;
43408 {
43411 {
43414 /* Pad short function. */
43416 {
43419 /* Find epilogue. */
43428 /* Two NOPs count as one instruction. */
43431 }
43432 }
43433 }
43434 }
43436 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43437 the epilogue, the Windows system unwinder will apply epilogue logic and
43438 produce incorrect offsets. This can be avoided by adding a nop between
43439 the last insn that can throw and the first insn of the epilogue. */
43441 static void
43443 {
43444 edge e;
43445 edge_iterator ei;
43448 {
43451 /* Find the beginning of the epilogue. */
43458 /* We only care about preceding insns that can throw. */
43463 /* Do not separate calls from their debug information. */
43469 else
43473 }
43474 }
43476 /* Implement machine specific optimizations. We implement padding of returns
43477 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43478 static void
43480 {
43481 /* We are freeing block_for_insn in the toplev to keep compatibility
43482 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43489 {
43494 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43497 #endif
43498 }
43499 }
43501 /* Return nonzero when QImode register that must be represented via REX prefix
43502 is used. */
43503 bool
43505 {
43513 }
43515 /* Return true when INSN mentions register that must be encoded using REX
43516 prefix. */
43517 bool
43519 {
43522 {
43527 }
43529 }
43531 /* If profitable, negate (without causing overflow) integer constant
43532 of mode MODE at location LOC. Return true in this case. */
43533 bool
43535 {
43536 HOST_WIDE_INT val;
43542 {
43544 /* DImode x86_64 constants must fit in 32 bits. */
43557 }
43559 /* Avoid overflows. */
43565 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43566 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43569 {
43572 }
43575 }
43577 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43578 optabs would emit if we didn't have TFmode patterns. */
43580 void
43582 {
43617 }
43618 \f
43624 /* Get a vector mode of the same size as the original but with elements
43625 twice as wide. This is only guaranteed to apply to integral vectors. */
43629 {
43630 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43635 }
43637 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43638 fill target with val via vec_duplicate. */
43640 static bool
43642 {
43645 rtx dup;
43647 /* First attempt to recognize VAL as-is. */
43651 {
43653 /* If that fails, force VAL into a register. */
43664 }
43666 }
43668 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43669 with all elements equal to VAR. Return true if successful. */
43671 static bool
43674 {
43678 {
43683 /* FALLTHRU */
43703 {
43704 rtx x;
43711 }
43724 {
43728 permute:
43736 /* Extend to SImode using a paradoxical SUBREG. */
43740 /* Insert the SImode value as low element of a V4SImode vector. */
43749 }
43760 widen:
43761 /* Replicate the value once into the next wider mode and recurse. */
43762 {
43764 rtx x;
43781 }
43787 else
43788 {
43797 }
43804 else
43805 {
43814 }
43819 }
43820 }
43822 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43823 whose ONE_VAR element is VAR, and other elements are zero. Return true
43824 if successful. */
43826 static bool
43829 {
43830 machine_mode vsimode;
43831 rtx new_target;
43836 {
43838 /* For SSE4.1, we normally use vector set. But if the second
43839 element is zero and inter-unit moves are OK, we use movq
43840 instead. */
43842 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
43864 /* Use ix86_expand_vector_set in 64bit mode only. */
43869 }
43872 {
43877 }
43880 {
43885 /* FALLTHRU */
43900 else
43907 {
43908 /* We need to shuffle the value to the correct position, so
43909 create a new pseudo to store the intermediate result. */
43911 /* With SSE2, we can use the integer shuffle insns. */
43913 {
43915 const1_rtx,
43922 }
43924 /* Otherwise convert the intermediate result to V4SFmode and
43925 use the SSE1 shuffle instructions. */
43927 {
43930 }
43931 else
43935 const1_rtx,
43944 }
43959 widen:
43963 /* Zero extend the variable element to SImode and recurse. */
43976 }
43977 }
43979 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43980 consisting of the values in VALS. It is known that all elements
43981 except ONE_VAR are constants. Return true if successful. */
43983 static bool
43986 {
43988 machine_mode wmode;
43996 {
44001 /* For the two element vectors, it's just as easy to use
44002 the general case. */
44006 /* Use ix86_expand_vector_set in 64bit mode only. */
44028 widen:
44029 /* There's no way to set one QImode entry easily. Combine
44030 the variable value with its adjacent constant value, and
44031 promote to an HImode set. */
44034 {
44039 }
44040 else
44041 {
44044 }
44058 }
44063 }
44065 /* A subroutine of ix86_expand_vector_init_general. Use vector
44066 concatenate to handle the most general case: all values variable,
44067 and none identical. */
44069 static void
44072 {
44075 rtvec v;
44079 {
44082 {
44127 }
44140 {
44155 }
44160 {
44179 }
44184 {
44197 }
44200 half:
44201 /* FIXME: We process inputs backward to help RA. PR 36222. */
44205 {
44210 }
44214 {
44218 {
44222 }
44225 {
44229 }
44232 }
44234 {
44237 {
44241 }
44244 }
44245 else
44251 }
44252 }
44254 /* A subroutine of ix86_expand_vector_init_general. Use vector
44255 interleave to handle the most general case: all values variable,
44256 and none identical. */
44258 static void
44261 {
44270 {
44291 }
44294 {
44295 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44299 /* Insert the SImode value as low element of V4SImode vector. */
44303 op0),
44305 const1_rtx);
44308 /* Cast the V4SImode vector back to a vector in orignal mode. */
44312 /* Load even elements into the second position. */
44316 const1_rtx));
44318 /* Cast vector to FIRST_IMODE vector. */
44321 }
44323 /* Interleave low FIRST_IMODE vectors. */
44325 {
44329 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44332 }
44334 /* Interleave low SECOND_IMODE vectors. */
44336 {
44339 {
44344 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44345 vector. */
44348 }
44351 /* FALLTHRU */
44358 /* Cast the SECOND_IMODE vector back to a vector on original
44359 mode. */
44366 }
44367 }
44369 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44370 all values variable, and none identical. */
44372 static void
44375 {
44382 {
44387 /* FALLTHRU */
44415 half:
44439 quarter:
44468 /* FALLTHRU */
44474 /* Don't use ix86_expand_vector_init_interleave if we can't
44475 move from GPR to SSE register directly. */
44491 }
44493 {
44495 machine_mode inner_mode;
44505 {
44509 {
44515 else
44516 {
44521 }
44522 }
44525 }
44530 {
44536 }
44538 {
44544 }
44545 else
44547 }
44548 }
44550 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44551 instructions unless MMX_OK is true. */
44553 void
44555 {
44562 rtx x;
44565 {
44575 }
44577 /* Constants are best loaded from the constant pool. */
44579 {
44582 }
44584 /* If all values are identical, broadcast the value. */
44590 /* Values where only one field is non-constant are best loaded from
44591 the pool and overwritten via move later. */
44593 {
44597 one_var))
44602 }
44605 }
44607 void
44609 {
44612 machine_mode half_mode;
44614 rtx tmp;
44616 = {
44623 };
44625 = {
44632 };
44636 {
44640 {
44645 else
44649 }
44661 else
44667 {
44670 /* For the two element vectors, we implement a VEC_CONCAT with
44671 the extraction of the other element. */
44678 else
44683 }
44692 {
44698 /* tmp = target = A B C D */
44700 /* target = A A B B */
44702 /* target = X A B B */
44704 /* target = A X C D */
44711 /* tmp = target = A B C D */
44713 /* tmp = X B C D */
44715 /* target = A B X D */
44722 /* tmp = target = A B C D */
44724 /* tmp = X B C D */
44726 /* target = A B X D */
44734 }
44742 /* Element 0 handled by vec_merge below. */
44744 {
44747 }
44750 {
44751 /* With SSE2, use integer shuffles to swap element 0 and ELT,
44752 store into element 0, then shuffle them back. */
44769 }
44770 else
44771 {
44772 /* For SSE1, we have to reuse the V4SF code. */
44776 }
44829 half:
44830 /* Compute offset. */
44836 /* Extract the half. */
44840 /* Put val in tmp at elt. */
44843 /* Put it back. */
44849 {
44856 }
44857 else
44861 {
44868 }
44869 else
44873 {
44880 }
44881 else
44885 {
44892 }
44893 else
44897 {
44904 }
44905 else
44909 {
44916 }
44917 else
44922 }
44925 {
44929 }
44930 else
44931 {
44940 }
44941 }
44943 void
44945 {
44949 rtx tmp;
44952 {
44957 /* FALLTHRU */
44970 {
44990 }
45002 {
45004 {
45024 }
45028 }
45029 else
45030 {
45031 /* For SSE1, we have to reuse the V4SF code. */
45035 }
45051 {
45055 else
45059 }
45064 {
45068 else
45072 }
45077 {
45081 else
45085 }
45090 {
45094 else
45098 }
45103 {
45107 else
45111 }
45116 {
45120 else
45124 }
45129 {
45133 else
45137 }
45142 {
45146 else
45150 }
45157 else
45166 else
45175 else
45184 else
45190 /* ??? Could extract the appropriate HImode element and shift. */
45193 }
45196 {
45200 /* Let the rtl optimizers know about the zero extension performed. */
45202 {
45205 }
45208 }
45209 else
45210 {
45217 }
45218 }
45220 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45221 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45222 The upper bits of DEST are undefined, though they shouldn't cause
45223 exceptions (some bits from src or all zeros are ok). */
45225 static void
45227 {
45230 {
45234 else
45252 else
45259 else
45267 {
45272 const1_rtx);
45273 }
45274 else
45275 {
45279 }
45301 else
45323 }
45327 }
45329 /* Expand a vector reduction. FN is the binary pattern to reduce;
45330 DEST is the destination; IN is the input vector. */
45332 void
45334 {
45339 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45343 {
45346 }
45351 {
45356 else
45360 }
45361 }
45362 \f
45363 /* Target hook for scalar_mode_supported_p. */
45364 static bool
45366 {
45371 else
45373 }
45375 /* Implements target hook vector_mode_supported_p. */
45376 static bool
45378 {
45392 }
45394 /* Implement target hook libgcc_floating_mode_supported_p. */
45395 static bool
45397 {
45399 {
45406 #ifdef IX86_NO_LIBGCC_TFMODE
45408 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45410 #else
45412 #endif
45416 }
45417 }
45419 /* Target hook for c_mode_for_suffix. */
45420 static machine_mode
45422 {
45429 }
45431 /* Worker function for TARGET_MD_ASM_CLOBBERS.
45433 We do this in the new i386 backend to maintain source compatibility
45434 with the old cc0-based compiler. */
45436 static tree
45438 {
45440 clobbers);
45442 clobbers);
45444 }
45446 /* Implements target vector targetm.asm.encode_section_info. */
45448 static void ATTRIBUTE_UNUSED
45450 {
45455 }
45457 /* Worker function for REVERSE_CONDITION. */
45459 enum rtx_code
45461 {
45465 }
45467 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45468 to OPERANDS[0]. */
45472 {
45474 {
45477 {
45481 }
45485 }
45487 {
45491 else
45492 {
45493 /* There is no non-popping store to memory for XFmode.
45494 So if we need one, follow the store with a load. */
45497 else
45499 }
45500 }
45501 else
45503 }
45505 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45506 FP status register is set. */
45508 void
45510 {
45512 rtx temp;
45517 {
45522 }
45523 else
45524 {
45529 }
45533 pc_rtx);
45538 }
45540 /* Output code to perform a log1p XFmode calculation. */
45543 {
45549 rtx test;
45555 XFmode));
45569 }
45571 /* Emit code for round calculation. */
45573 {
45580 rtx insn;
45585 {
45597 }
45600 {
45621 }
45629 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
45631 /* scratch = fxam(op1) */
45634 UNSPEC_FXAM)));
45635 /* e1 = fabs(op1) */
45638 /* e2 = e1 + 0.5 */
45643 /* res = floor(e2) */
45645 {
45650 }
45651 else
45655 {
45658 {
45665 UNSPEC_TRUNC_NOOP)));
45666 }
45682 }
45684 /* flags = signbit(a) */
45687 /* if (flags) then res = -res */
45691 pc_rtx);
45702 }
45704 /* Output code to perform a Newton-Rhapson approximation of a single precision
45705 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
45708 {
45716 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
45720 /* x0 = rcp(b) estimate */
45724 UNSPEC_RCP14)));
45725 else
45728 UNSPEC_RCP)));
45730 /* e0 = x0 * b */
45734 /* e0 = x0 * e0 */
45738 /* e1 = x0 + x0 */
45742 /* x1 = e1 - e0 */
45746 /* res = a * x1 */
45749 }
45751 /* Output code to perform a Newton-Rhapson approximation of a
45752 single precision floating point [reciprocal] square root. */
45756 {
45758 REAL_VALUE_TYPE r;
45775 {
45778 /* There is no 512-bit rsqrt. There is however rsqrt14. */
45781 }
45783 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
45784 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
45788 /* x0 = rsqrt(a) estimate */
45791 unspec)));
45793 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
45795 {
45803 /* Handle masked compare. */
45805 {
45807 /* Imm value 0x4 corresponds to not-equal comparison. */
45810 }
45811 else
45812 {
45818 }
45819 }
45821 /* e0 = x0 * a */
45824 /* e1 = e0 * x0 */
45828 /* e2 = e1 - 3. */
45835 /* e3 = -.5 * x0 */
45838 else
45839 /* e3 = -.5 * e0 */
45842 /* ret = e2 * e3 */
45845 }
45847 #ifdef TARGET_SOLARIS
45848 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
45850 static void
45852 tree decl)
45853 {
45854 /* With Binutils 2.15, the "@unwind" marker must be specified on
45855 every occurrence of the ".eh_frame" section, not just the first
45856 one. */
45859 {
45863 }
45865 #ifndef USE_GAS
45867 {
45870 }
45871 #endif
45874 }
45877 /* Return the mangling of TYPE if it is an extended fundamental type. */
45881 {
45889 {
45891 /* __float128 is "g". */
45894 /* "long double" or __float80 is "e". */
45898 }
45899 }
45901 /* For 32-bit code we can save PIC register setup by using
45902 __stack_chk_fail_local hidden function instead of calling
45903 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
45904 register, so it is better to call __stack_chk_fail directly. */
45906 static tree ATTRIBUTE_UNUSED
45908 {
45909 return TARGET_64BIT
45912 }
45914 /* Select a format to encode pointers in exception handling data. CODE
45915 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
45916 true if the symbol may be affected by dynamic relocations.
45918 ??? All x86 object file formats are capable of representing this.
45919 After all, the relocation needed is the same as for the call insn.
45920 Whether or not a particular assembler allows us to enter such, I
45921 guess we'll have to see. */
45922 int
45924 {
45926 {
45933 }
45938 }
45939 \f
45940 /* Expand copysign from SIGN to the positive value ABS_VALUE
45941 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
45942 the sign-bit. */
45943 static void
45945 {
45949 {
45950 machine_mode vmode;
45956 else
45961 {
45962 /* We need to generate a scalar mode mask in this case. */
45967 }
45968 }
45969 else
45975 }
45977 /* Expand fabs (OP0) and return a new rtx that holds the result. The
45978 mask for masking out the sign-bit is stored in *SMASK, if that is
45979 non-null. */
45980 static rtx
45982 {
45991 else
45995 {
45996 /* We need to generate a scalar mode mask in this case. */
46001 }
46009 }
46011 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
46012 swapping the operands if SWAP_OPERANDS is true. The expanded
46013 code is a forward jump to a newly created label in case the
46014 comparison is true. The generated label rtx is returned. */
46018 {
46021 rtx tmp;
46037 }
46039 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
46040 using comparison code CODE. Operands are swapped for the comparison if
46041 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
46042 static rtx
46045 {
46058 }
46060 /* Generate and return a rtx of mode MODE for 2**n where n is the number
46061 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
46062 static rtx
46064 {
46065 REAL_VALUE_TYPE TWO52r;
46066 rtx TWO52;
46073 }
46075 /* Expand SSE sequence for computing lround from OP1 storing
46076 into OP0. */
46077 void
46079 {
46080 /* C code for the stuff we're doing below:
46081 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46082 return (long)tmp;
46083 */
46087 rtx adj;
46089 /* load nextafter (0.5, 0.0) */
46094 /* adj = copysign (0.5, op1) */
46098 /* adj = op1 + adj */
46101 /* op0 = (imode)adj */
46103 }
46105 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46106 into OPERAND0. */
46107 void
46109 {
46110 /* C code for the stuff we're doing below (for do_floor):
46111 xi = (long)op1;
46112 xi -= (double)xi > op1 ? 1 : 0;
46113 return xi;
46114 */
46120 /* reg = (long)op1 */
46124 /* freg = (double)reg */
46128 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46139 }
46141 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46142 result in OPERAND0. */
46143 void
46145 {
46146 /* C code for the stuff we're doing below:
46147 xa = fabs (operand1);
46148 if (!isless (xa, 2**52))
46149 return operand1;
46150 xa = xa + 2**52 - 2**52;
46151 return copysign (xa, operand1);
46152 */
46160 /* xa = abs (operand1) */
46163 /* if (!isless (xa, TWO52)) goto label; */
46176 }
46178 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46179 into OPERAND0. */
46180 void
46182 {
46183 /* C code for the stuff we expand below.
46184 double xa = fabs (x), x2;
46185 if (!isless (xa, TWO52))
46186 return x;
46187 xa = xa + TWO52 - TWO52;
46188 x2 = copysign (xa, x);
46189 Compensate. Floor:
46190 if (x2 > x)
46191 x2 -= 1;
46192 Compensate. Ceil:
46193 if (x2 < x)
46194 x2 -= -1;
46195 return x2;
46196 */
46203 /* Temporary for holding the result, initialized to the input
46204 operand to ease control flow. */
46208 /* xa = abs (operand1) */
46211 /* if (!isless (xa, TWO52)) goto label; */
46214 /* xa = xa + TWO52 - TWO52; */
46218 /* xa = copysign (xa, operand1) */
46221 /* generate 1.0 or -1.0 */
46226 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46230 /* We always need to subtract here to preserve signed zero. */
46239 }
46241 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46242 into OPERAND0. */
46243 void
46245 {
46246 /* C code for the stuff we expand below.
46247 double xa = fabs (x), x2;
46248 if (!isless (xa, TWO52))
46249 return x;
46250 x2 = (double)(long)x;
46251 Compensate. Floor:
46252 if (x2 > x)
46253 x2 -= 1;
46254 Compensate. Ceil:
46255 if (x2 < x)
46256 x2 += 1;
46257 if (HONOR_SIGNED_ZEROS (mode))
46258 return copysign (x2, x);
46259 return x2;
46260 */
46267 /* Temporary for holding the result, initialized to the input
46268 operand to ease control flow. */
46272 /* xa = abs (operand1) */
46275 /* if (!isless (xa, TWO52)) goto label; */
46278 /* xa = (double)(long)x */
46283 /* generate 1.0 */
46286 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46301 }
46303 /* Expand SSE sequence for computing round from OPERAND1 storing
46304 into OPERAND0. Sequence that works without relying on DImode truncation
46305 via cvttsd2siq that is only available on 64bit targets. */
46306 void
46308 {
46309 /* C code for the stuff we expand below.
46310 double xa = fabs (x), xa2, x2;
46311 if (!isless (xa, TWO52))
46312 return x;
46313 Using the absolute value and copying back sign makes
46314 -0.0 -> -0.0 correct.
46315 xa2 = xa + TWO52 - TWO52;
46316 Compensate.
46317 dxa = xa2 - xa;
46318 if (dxa <= -0.5)
46319 xa2 += 1;
46320 else if (dxa > 0.5)
46321 xa2 -= 1;
46322 x2 = copysign (xa2, x);
46323 return x2;
46324 */
46331 /* Temporary for holding the result, initialized to the input
46332 operand to ease control flow. */
46336 /* xa = abs (operand1) */
46339 /* if (!isless (xa, TWO52)) goto label; */
46342 /* xa2 = xa + TWO52 - TWO52; */
46346 /* dxa = xa2 - xa; */
46349 /* generate 0.5, 1.0 and -0.5 */
46355 /* Compensate. */
46357 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46362 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46368 /* res = copysign (xa2, operand1) */
46375 }
46377 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46378 into OPERAND0. */
46379 void
46381 {
46382 /* C code for SSE variant we expand below.
46383 double xa = fabs (x), x2;
46384 if (!isless (xa, TWO52))
46385 return x;
46386 x2 = (double)(long)x;
46387 if (HONOR_SIGNED_ZEROS (mode))
46388 return copysign (x2, x);
46389 return x2;
46390 */
46397 /* Temporary for holding the result, initialized to the input
46398 operand to ease control flow. */
46402 /* xa = abs (operand1) */
46405 /* if (!isless (xa, TWO52)) goto label; */
46408 /* x = (double)(long)x */
46420 }
46422 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46423 into OPERAND0. */
46424 void
46426 {
46431 /* C code for SSE variant we expand below.
46432 double xa = fabs (x), x2;
46433 if (!isless (xa, TWO52))
46434 return x;
46435 xa2 = xa + TWO52 - TWO52;
46436 Compensate:
46437 if (xa2 > xa)
46438 xa2 -= 1.0;
46439 x2 = copysign (xa2, x);
46440 return x2;
46441 */
46445 /* Temporary for holding the result, initialized to the input
46446 operand to ease control flow. */
46450 /* xa = abs (operand1) */
46453 /* if (!isless (xa, TWO52)) goto label; */
46456 /* res = xa + TWO52 - TWO52; */
46461 /* generate 1.0 */
46464 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46472 /* res = copysign (res, operand1) */
46479 }
46481 /* Expand SSE sequence for computing round from OPERAND1 storing
46482 into OPERAND0. */
46483 void
46485 {
46486 /* C code for the stuff we're doing below:
46487 double xa = fabs (x);
46488 if (!isless (xa, TWO52))
46489 return x;
46490 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46491 return copysign (xa, x);
46492 */
46499 /* Temporary for holding the result, initialized to the input
46500 operand to ease control flow. */
46508 /* load nextafter (0.5, 0.0) */
46513 /* xa = xa + 0.5 */
46517 /* xa = (double)(int64_t)xa */
46522 /* res = copysign (xa, operand1) */
46529 }
46531 /* Expand SSE sequence for computing round
46532 from OP1 storing into OP0 using sse4 round insn. */
46533 void
46535 {
46544 {
46555 }
46557 /* round (a) = trunc (a + copysign (0.5, a)) */
46559 /* load nextafter (0.5, 0.0) */
46565 /* e1 = copysign (0.5, op1) */
46569 /* e2 = op1 + e1 */
46572 /* res = trunc (e2) */
46577 }
46578 \f
46580 /* Table of valid machine attributes. */
46582 {
46583 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46584 affects_type_identity } */
46585 /* Stdcall attribute says callee is responsible for popping arguments
46586 if they are not variable. */
46589 /* Fastcall attribute says callee is responsible for popping arguments
46590 if they are not variable. */
46593 /* Thiscall attribute says callee is responsible for popping arguments
46594 if they are not variable. */
46597 /* Cdecl attribute says the callee is a normal C declaration */
46600 /* Regparm attribute specifies how many integer arguments are to be
46601 passed in registers. */
46604 /* Sseregparm attribute says we are using x86_64 calling conventions
46605 for FP arguments. */
46608 /* The transactional memory builtins are implicitly regparm or fastcall
46609 depending on the ABI. Override the generic do-nothing attribute that
46610 these builtins were declared with. */
46613 /* force_align_arg_pointer says this function realigns the stack at entry. */
46616 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46621 #endif
46626 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46627 SUBTARGET_ATTRIBUTE_TABLE,
46628 #endif
46629 /* ms_abi and sysv_abi calling convention function attributes. */
46636 /* End element. */
46638 };
46640 /* Implement targetm.vectorize.builtin_vectorization_cost. */
46641 static int
46644 {
46648 {
46693 }
46694 }
46696 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
46697 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
46698 insn every time. */
46702 /* Initialize vselect_insn. */
46704 static void
46706 {
46708 rtx x;
46719 }
46721 /* Construct (set target (vec_select op0 (parallel perm))) and
46722 return true if that's a valid instruction in the active ISA. */
46724 static bool
46727 {
46753 }
46755 /* Similar, but generate a vec_concat from op0 and op1 as well. */
46757 static bool
46761 {
46762 machine_mode v2mode;
46763 rtx x;
46778 }
46780 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46781 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
46783 static bool
46785 {
46795 ;
46797 ;
46799 ;
46801 ;
46802 else
46805 /* This is a blend, not a permute. Elements must stay in their
46806 respective lanes. */
46808 {
46812 }
46817 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
46818 decision should be extracted elsewhere, so that we only try that
46819 sequence once all budget==3 options have been tried. */
46826 {
46856 /* See if bytes move in pairs so we can use pblendw with
46857 an immediate argument, rather than pblendvb with a vector
46858 argument. */
46861 {
46862 use_pblendvb:
46866 finish_pblendvb:
46872 else
46877 }
46882 /* FALLTHRU */
46884 do_subreg:
46891 /* See if bytes move in pairs. If not, vpblendvb must be used. */
46895 /* See if bytes move in quadruplets. If yes, vpblendd
46896 with immediate can be used. */
46901 {
46902 /* See if bytes move the same in both lanes. If yes,
46903 vpblendw with immediate can be used. */
46908 /* Use vpblendw. */
46913 }
46915 /* Use vpblendd. */
46922 /* See if words move in pairs. If yes, vpblendd can be used. */
46927 {
46928 /* See if words move the same in both lanes. If not,
46929 vpblendvb must be used. */
46932 {
46933 /* Use vpblendvb. */
46943 }
46945 /* Use vpblendw. */
46949 }
46951 /* Use vpblendd. */
46958 /* Use vpblendd. */
46966 }
46968 /* This matches five different patterns with the different modes. */
46976 }
46978 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46979 in terms of the variable form of vpermilps.
46981 Note that we will have already failed the immediate input vpermilps,
46982 which requires that the high and low part shuffle be identical; the
46983 variable form doesn't require that. */
46985 static bool
46987 {
46994 /* We can only permute within the 128-bit lane. */
46996 {
47000 }
47006 {
47009 /* Within each 128-bit lane, the elements of op0 are numbered
47010 from 0 and the elements of op1 are numbered from 4. */
47017 }
47024 }
47026 /* Return true if permutation D can be performed as VMODE permutation
47027 instead. */
47029 static bool
47031 {
47046 else
47052 }
47054 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47055 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
47057 static bool
47059 {
47068 {
47070 {
47073 {
47077 /* Use vperm2i128 insn. The pattern uses
47078 V4DImode instead of V2TImode. */
47091 }
47093 }
47094 }
47095 else
47096 {
47098 {
47101 }
47103 {
47107 /* V4DImode should be already handled through
47108 expand_vselect by vpermq instruction. */
47115 {
47116 /* First see if vpermq can be used for
47117 V8SImode/V16HImode/V32QImode. */
47119 {
47127 {
47131 }
47133 }
47135 /* Next see if vpermd can be used. */
47138 }
47139 /* Or if vpermps can be used. */
47144 {
47145 /* vpshufb only works intra lanes, it is not
47146 possible to shuffle bytes in between the lanes. */
47150 }
47151 }
47153 {
47157 /* If vpermq didn't work, vpshufb won't work either. */
47165 {
47166 /* First see if vpermq can be used for
47167 V16SImode/V32HImode/V64QImode. */
47169 {
47177 {
47181 }
47183 }
47185 /* Next see if vpermd can be used. */
47188 }
47189 /* Or if vpermps can be used. */
47193 {
47194 /* vpshufb only works intra lanes, it is not
47195 possible to shuffle bytes in between the lanes. */
47199 }
47200 }
47201 else
47203 }
47214 else
47215 {
47223 else
47227 {
47231 }
47232 }
47243 {
47258 else
47260 }
47261 else
47262 {
47265 }
47270 }
47272 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47273 in a single instruction. */
47275 static bool
47277 {
47281 /* Check plain VEC_SELECT first, because AVX has instructions that could
47282 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47283 input where SEL+CONCAT may not. */
47285 {
47291 {
47297 }
47300 {
47304 }
47306 {
47307 /* Use vpbroadcast{b,w,d}. */
47310 {
47353 /* For other modes prefer other shuffles this function creates. */
47355 }
47357 {
47361 }
47362 }
47367 /* There are plenty of patterns in sse.md that are written for
47368 SEL+CONCAT and are not replicated for a single op. Perhaps
47369 that should be changed, to avoid the nastiness here. */
47371 /* Recognize interleave style patterns, which means incrementing
47372 every other permutation operand. */
47374 {
47377 }
47382 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47384 {
47386 {
47391 }
47396 }
47397 }
47399 /* Finally, try the fully general two operand permute. */
47404 /* Recognize interleave style patterns with reversed operands. */
47406 {
47408 {
47412 else
47415 }
47420 }
47422 /* Try the SSE4.1 blend variable merge instructions. */
47426 /* Try one of the AVX vpermil variable permutations. */
47430 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47431 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47435 /* Try the AVX2 vpalignr instruction. */
47439 /* Try the AVX512F vpermi2 instructions. */
47444 }
47446 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47447 in terms of a pair of pshuflw + pshufhw instructions. */
47449 static bool
47451 {
47459 /* The two permutations only operate in 64-bit lanes. */
47470 /* Emit the pshuflw. */
47477 /* Emit the pshufhw. */
47485 }
47487 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47488 the permutation using the SSSE3 palignr instruction. This succeeds
47489 when all of the elements in PERM fit within one vector and we merely
47490 need to shift them down so that a single vector permutation has a
47491 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47492 the vpalignr instruction itself can perform the requested permutation. */
47494 static bool
47496 {
47503 /* Even with AVX, palignr only operates on 128-bit vectors,
47504 in AVX2 palignr operates on both 128-bit lanes. */
47514 {
47518 {
47521 }
47530 }
47533 {
47542 }
47544 /* Given that we have SSSE3, we know we'll be able to implement the
47545 single operand permutation after the palignr with pshufb for
47546 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47547 first. */
47553 {
47558 }
47562 {
47568 else
47573 }
47579 /* For AVX2, test whether we can permute the result in one instruction. */
47581 {
47586 }
47590 {
47594 }
47595 else
47596 {
47601 shift));
47602 }
47606 /* Test for the degenerate case where the alignment by itself
47607 produces the desired permutation. */
47609 {
47612 }
47618 }
47620 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
47621 the permutation using the SSE4_1 pblendv instruction. Potentially
47622 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
47624 static bool
47626 {
47632 /* Use the same checks as in expand_vec_perm_blend. */
47636 ;
47638 ;
47640 ;
47641 else
47644 /* Figure out where permutation elements stay not in their
47645 respective lanes. */
47647 {
47651 }
47652 /* We can pblend the part where elements stay not in their
47653 respective lanes only when these elements are all in one
47654 half of a permutation.
47655 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
47656 lanes, but both 8 and 9 >= 8
47657 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
47658 respective lanes and 8 >= 8, but 2 not. */
47664 /* First we apply one operand permutation to the part where
47665 elements stay not in their respective lanes. */
47669 else
47681 else
47686 /* Next we put permuted elements into their positions. */
47690 else
47700 }
47704 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47705 a two vector permutation into a single vector permutation by using
47706 an interleave operation to merge the vectors. */
47708 static bool
47710 {
47719 {
47722 }
47724 {
47727 /* For 32-byte modes allow even d->one_operand_p.
47728 The lack of cross-lane shuffling in some instructions
47729 might prevent a single insn shuffle. */
47732 /* If expand_vec_perm_interleave3 can expand this into
47733 a 3 insn sequence, give up and let it be expanded as
47734 3 insn sequence. While that is one insn longer,
47735 it doesn't need a memory operand and in the common
47736 case that both interleave low and high permutations
47737 with the same operands are adjacent needs 4 insns
47738 for both after CSE. */
47741 }
47742 else
47745 /* Examine from whence the elements come. */
47754 {
47757 /* Split the two input vectors into 4 halves. */
47763 /* If the elements from the low halves use interleave low, and similarly
47764 for interleave high. If the elements are from mis-matched halves, we
47765 can use shufps for V4SF/V4SI or do a DImode shuffle. */
47767 {
47768 /* punpckl* */
47770 {
47775 }
47778 }
47780 {
47781 /* punpckh* */
47783 {
47788 }
47791 }
47793 {
47794 /* shufps */
47796 {
47801 }
47803 {
47804 /* shufpd */
47809 }
47810 }
47812 {
47813 /* shufps */
47815 {
47820 }
47822 {
47823 /* shufpd */
47828 }
47829 }
47830 else
47832 }
47833 else
47834 {
47839 /* Split the two input vectors into 8 quarters. */
47845 {
47848 }
47851 {
47855 }
47857 {
47860 }
47863 {
47865 {
47866 /* Attempt to increase the likelihood that dfinal
47867 shuffle will be intra-lane. */
47871 }
47873 /* vperm2f128 or vperm2i128. */
47875 {
47880 }
47885 {
47889 {
47892 }
47893 }
47894 }
47899 {
47900 /* vpunpckl* */
47902 {
47911 }
47912 }
47915 {
47916 /* vpunpckh* */
47918 {
47927 }
47928 }
47929 else
47931 }
47933 /* Use the remapping array set up above to move the elements from their
47934 swizzled locations into their final destinations. */
47937 {
47940 /* If same_halves is true, both halves of the remapped vector are the
47941 same. Avoid cross-lane accesses if possible. */
47943 {
47946 }
47947 else
47949 }
47951 {
47954 }
47958 /* Test if the final remap can be done with a single insn. For V4SFmode or
47959 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
47972 {
47975 }
47982 }
47984 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47985 a single vector cross-lane permutation into vpermq followed
47986 by any of the single insn permutations. */
47988 static bool
47990 {
48004 {
48007 }
48010 {
48015 }
48028 {
48035 }
48042 {
48047 ;
48050 else
48052 }
48061 }
48063 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
48064 a vector permutation using two instructions, vperm2f128 resp.
48065 vperm2i128 followed by any single in-lane permutation. */
48067 static bool
48069 {
48083 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48084 immediate. For perm < 16 the second permutation uses
48085 d->op0 as first operand, for perm >= 16 it uses d->op1
48086 as first operand. The second operand is the result of
48087 vperm2[fi]128. */
48089 {
48090 /* Ignore permutations which do not move anything cross-lane. */
48092 {
48093 /* The second shuffle for e.g. V4DFmode has
48094 0123 and ABCD operands.
48095 Ignore AB23, as 23 is already in the second lane
48096 of the first operand. */
48098 /* And 01CD, as 01 is in the first lane of the first
48099 operand. */
48101 /* And 4567, as then the vperm2[fi]128 doesn't change
48102 anything on the original 4567 second operand. */
48104 }
48105 else
48106 {
48107 /* The second shuffle for e.g. V4DFmode has
48108 4567 and ABCD operands.
48109 Ignore AB67, as 67 is already in the second lane
48110 of the first operand. */
48112 /* And 45CD, as 45 is in the first lane of the first
48113 operand. */
48115 /* And 0123, as then the vperm2[fi]128 doesn't change
48116 anything on the original 0123 first operand. */
48118 }
48121 {
48127 else
48129 }
48132 {
48136 }
48137 else
48141 {
48145 /* Found a usable second shuffle. dfirst will be
48146 vperm2f128 on d->op0 and d->op1. */
48158 /* And dsecond is some single insn shuffle, taking
48159 d->op0 and result of vperm2f128 (if perm < 16) or
48160 d->op1 and result of vperm2f128 (otherwise). */
48169 }
48171 /* For one operand, the only useful vperm2f128 permutation is 0x01
48172 aka lanes swap. */
48175 }
48178 }
48180 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48181 a two vector permutation using 2 intra-lane interleave insns
48182 and cross-lane shuffle for 32-byte vectors. */
48184 static bool
48186 {
48193 ;
48195 ;
48196 else
48211 {
48215 else
48221 else
48227 else
48233 else
48239 else
48245 else
48250 }
48254 }
48256 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48257 a single vector permutation using a single intra-lane vector
48258 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48259 the non-swapped and swapped vectors together. */
48261 static bool
48263 {
48271 || TARGET_AVX2
48280 {
48287 }
48322 }
48324 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48325 permutation using two vperm2f128, followed by a vshufpd insn blending
48326 the two vectors together. */
48328 static bool
48330 {
48373 }
48375 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48376 permutation with two pshufb insns and an ior. We should have already
48377 failed all two instruction sequences. */
48379 static bool
48381 {
48395 /* Generate two permutation masks. If the required element is within
48396 the given vector it is shuffled into the proper lane. If the required
48397 element is in the other vector, force a zero into the lane by setting
48398 bit 7 in the permutation mask. */
48401 {
48408 {
48411 }
48412 }
48436 }
48438 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48439 with two vpshufb insns, vpermq and vpor. We should have already failed
48440 all two or three instruction sequences. */
48442 static bool
48444 {
48459 /* Generate two permutation masks. If the required element is within
48460 the same lane, it is shuffled in. If the required element from the
48461 other lane, force a zero by setting bit 7 in the permutation mask.
48462 In the other mask the mask has non-negative elements if element
48463 is requested from the other lane, but also moved to the other lane,
48464 so that the result of vpshufb can have the two V2TImode halves
48465 swapped. */
48468 {
48473 {
48476 }
48477 }
48486 /* Swap the 128-byte lanes of h into hp. */
48490 const1_rtx));
48507 }
48509 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48510 and extract-odd permutations of two V32QImode and V16QImode operand
48511 with two vpshufb insns, vpor and vpermq. We should have already
48512 failed all two or three instruction sequences. */
48514 static bool
48516 {
48535 /* Generate two permutation masks. In the first permutation mask
48536 the first quarter will contain indexes for the first half
48537 of the op0, the second quarter will contain bit 7 set, third quarter
48538 will contain indexes for the second half of the op0 and the
48539 last quarter bit 7 set. In the second permutation mask
48540 the first quarter will contain bit 7 set, the second quarter
48541 indexes for the first half of the op1, the third quarter bit 7 set
48542 and last quarter indexes for the second half of the op1.
48543 I.e. the first mask e.g. for V32QImode extract even will be:
48544 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48545 (all values masked with 0xf except for -128) and second mask
48546 for extract even will be
48547 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48550 {
48556 {
48559 }
48560 }
48579 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48587 }
48589 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48590 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
48591 with two "and" and "pack" or two "shift" and "pack" insns. We should
48592 have already failed all two instruction sequences. */
48594 static bool
48596 {
48600 machine_mode half_mode;
48609 {
48611 /* Required for "pack". */
48622 /* No check as all instructions are SSE2. */
48653 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
48654 general shuffles. */
48656 }
48658 /* Check that permutation is even or odd. */
48673 {
48680 }
48681 else
48682 {
48689 }
48690 /* In AVX2 for 256 bit case we need to permute pack result. */
48692 {
48698 const0_rtx,
48699 const2_rtx,
48700 const1_rtx,
48703 }
48704 else
48708 }
48710 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
48711 and extract-odd permutations. */
48713 static bool
48715 {
48719 {
48726 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48730 /* Now an unpck[lh]pd will produce the result required. */
48733 else
48739 {
48748 /* Shuffle within the 128-bit lanes to produce:
48749 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
48753 /* Shuffle the lanes around to produce:
48754 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
48758 /* Shuffle within the 128-bit lanes to produce:
48759 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
48762 /* Shuffle within the 128-bit lanes to produce:
48763 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
48766 /* Shuffle the lanes around to produce:
48767 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
48770 }
48777 /* These are always directly implementable by expand_vec_perm_1. */
48785 else
48786 {
48789 /* We need 2*log2(N)-1 operations to achieve odd/even
48790 with interleave. */
48799 else
48802 }
48814 {
48819 else
48824 {
48829 }
48831 }
48839 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48843 /* Now an vpunpck[lh]qdq will produce the result required. */
48846 else
48853 {
48858 else
48863 {
48868 }
48870 }
48881 /* Shuffle the lanes around into
48882 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
48890 /* Swap the 2nd and 3rd position in each lane into
48891 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
48897 /* Now an vpunpck[lh]qdq will produce
48898 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
48902 else
48911 }
48914 }
48916 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48917 extract-even and extract-odd permutations. */
48919 static bool
48921 {
48933 }
48935 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
48936 permutations. We assume that expand_vec_perm_1 has already failed. */
48938 static bool
48940 {
48948 {
48951 /* These are special-cased in sse.md so that we can optionally
48952 use the vbroadcast instruction. They expand to two insns
48953 if the input happens to be in a register. */
48960 /* These are always implementable using standard shuffle patterns. */
48965 /* These can be implemented via interleave. We save one insn by
48966 stopping once we have promoted to V4SImode and then use pshufd. */
48969 do
48970 {
48971 rtx dest;
48977 {
48981 }
48988 }
49004 /* For AVX2 broadcasts of the first element vpbroadcast* or
49005 vpermq should be used by expand_vec_perm_1. */
49011 }
49012 }
49014 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49015 broadcast permutations. */
49017 static bool
49019 {
49031 }
49033 /* Implement arbitrary permutations of two V64QImode operands
49034 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
49035 static bool
49037 {
49047 machine_mode vmode;
49053 {
49060 }
49062 /* Prepare permutations such that the first one takes care of
49063 putting the even bytes into the right positions or one higher
49064 positions (ds[0]) and the second one takes care of
49065 putting the odd bytes into the right positions or one below
49066 (ds[1]). */
49069 {
49072 {
49075 }
49076 else
49077 {
49080 }
49081 }
49103 }
49105 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49106 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49107 all the shorter instruction sequences. */
49109 static bool
49111 {
49127 /* Generate 4 permutation masks. If the required element is within
49128 the same lane, it is shuffled in. If the required element from the
49129 other lane, force a zero by setting bit 7 in the permutation mask.
49130 In the other mask the mask has non-negative elements if element
49131 is requested from the other lane, but also moved to the other lane,
49132 so that the result of vpshufb can have the two V2TImode halves
49133 swapped. */
49136 {
49141 }
49147 {
49155 }
49158 {
49160 {
49163 }
49170 }
49172 /* Swap the 128-byte lanes of h[X]. */
49174 {
49180 const1_rtx));
49182 }
49185 {
49187 {
49190 }
49196 }
49199 {
49201 {
49205 }
49208 }
49218 }
49220 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49221 With all of the interface bits taken care of, perform the expansion
49222 in D and return true on success. */
49224 static bool
49226 {
49227 /* Try a single instruction expansion. */
49231 /* Try sequences of two instructions. */
49254 /* Try sequences of three instructions. */
49271 /* Try sequences of four instructions. */
49282 /* ??? Look for narrow permutations whose element orderings would
49283 allow the promotion to a wider mode. */
49285 /* ??? Look for sequences of interleave or a wider permute that place
49286 the data into the correct lanes for a half-vector shuffle like
49287 pshuf[lh]w or vpermilps. */
49289 /* ??? Look for sequences of interleave that produce the desired results.
49290 The combinatorics of punpck[lh] get pretty ugly... */
49295 /* Even longer sequences. */
49300 }
49302 /* If a permutation only uses one operand, make it clear. Returns true
49303 if the permutation references both operands. */
49305 static bool
49307 {
49315 {
49321 {
49324 }
49325 /* The elements of PERM do not suggest that only the first operand
49326 is used, but both operands are identical. Allow easier matching
49327 of the permutation by folding the permutation into the single
49328 input vector. */
49329 /* FALLTHRU */
49340 }
49343 }
49345 bool
49347 {
49352 rtx sel;
49369 {
49374 }
49381 /* If the selector says both arguments are needed, but the operands are the
49382 same, the above tried to expand with one_operand_p and flattened selector.
49383 If that didn't work, retry without one_operand_p; we succeeded with that
49384 during testing. */
49386 {
49390 }
49393 }
49395 /* Implement targetm.vectorize.vec_perm_const_ok. */
49397 static bool
49400 {
49409 /* Given sufficient ISA support we can just return true here
49410 for selected vector modes. */
49412 {
49418 /* All implementable with a single vpermi2 insn. */
49423 /* All implementable with a single vpermi2 insn. */
49428 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49436 /* All implementable with a single vpermi2 insn. */
49441 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49446 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49453 /* All implementable with a single vpperm insn. */
49456 /* All implementable with 2 pshufb + 1 ior. */
49462 /* All implementable with shufpd or unpck[lh]pd. */
49466 }
49468 /* Extract the values from the vector CST into the permutation
49469 array in D. */
49472 {
49476 }
49478 /* For all elements from second vector, fold the elements to first. */
49483 /* Check whether the mask can be applied to the vector type. */
49486 /* Implementable with shufps or pshufd. */
49490 /* Otherwise we have to go through the motions and see if we can
49491 figure out how to generate the requested permutation. */
49502 }
49504 void
49506 {
49521 /* We'll either be able to implement the permutation directly... */
49525 /* ... or we use the special-case patterns. */
49527 }
49529 static void
49531 {
49546 {
49549 }
49551 /* Note that for AVX this isn't one instruction. */
49554 }
49557 /* Expand a vector operation CODE for a V*QImode in terms of the
49558 same operation on V*HImode. */
49560 void
49562 {
49564 machine_mode himode;
49574 {
49592 }
49596 {
49598 /* Unpack data such that we've got a source byte in each low byte of
49599 each word. We don't care what goes into the high byte of each word.
49600 Rather than trying to get zero in there, most convenient is to let
49601 it be a copy of the low byte. */
49606 /* FALLTHRU */
49618 /* FALLTHRU */
49628 }
49630 /* Perform the operation. */
49637 /* Merge the data back into the right place. */
49647 {
49648 /* For SSE2, we used an full interleave, so the desired
49649 results are in the even elements. */
49652 }
49653 else
49654 {
49655 /* For AVX, the interleave used above was not cross-lane. So the
49656 extraction is evens but with the second and third quarter swapped.
49657 Happily, that is even one insn shorter than even extraction. */
49660 }
49667 }
49669 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
49670 if op is CONST_VECTOR with all odd elements equal to their
49671 preceding element. */
49673 static bool
49675 {
49685 }
49687 void
49690 {
49693 rtx x;
49701 /* We only play even/odd games with vectors of SImode. */
49704 /* If we're looking for the odd results, shift those members down to
49705 the even slots. For some cpus this is faster than a PSHUFD. */
49707 {
49708 /* For XOP use vpmacsdqh, but only for smult, as it is only
49709 signed. */
49711 {
49715 }
49726 }
49729 {
49732 else
49734 }
49736 {
49739 else
49741 }
49746 else
49747 {
49750 /* The easiest way to implement this without PMULDQ is to go through
49751 the motions as if we are performing a full 64-bit multiply. With
49752 the exception that we need to do less shuffling of the elements. */
49754 /* Compute the sign-extension, aka highparts, of the two operands. */
49760 /* Multiply LO(A) * HI(B), and vice-versa. */
49766 /* Multiply LO(A) * LO(B). */
49770 /* Combine and shift the highparts into place. */
49775 /* Combine high and low parts. */
49778 }
49780 }
49782 void
49785 {
49791 {
49796 {
49797 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
49798 shuffle the elements once so that all elements are in the right
49799 place for immediate use: { A C B D }. */
49804 }
49805 else
49806 {
49807 /* Put the elements into place for the multiply. */
49811 }
49816 /* Shuffle the elements between the lanes. After this we
49817 have { A B E F | C D G H } for each operand. */
49827 /* Shuffle the elements within the lanes. After this we
49828 have { A A B B | C C D D } or { E E F F | G G H H }. */
49869 }
49870 }
49872 void
49874 {
49884 /* Move the results in element 2 down to element 1; we don't care
49885 what goes in elements 2 and 3. Then we can merge the parts
49886 back together with an interleave.
49888 Note that two other sequences were tried:
49889 (1) Use interleaves at the start instead of psrldq, which allows
49890 us to use a single shufps to merge things back at the end.
49891 (2) Use shufps here to combine the two vectors, then pshufd to
49892 put the elements in the correct order.
49893 In both cases the cost of the reformatting stall was too high
49894 and the overall sequence slower. */
49905 }
49907 void
49909 {
49920 {
49921 /* op1: A,B,C,D, op2: E,F,G,H */
49930 /* t1: B,A,D,C */
49937 /* t2: (B*E),(A*F),(D*G),(C*H) */
49940 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
49943 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
49946 /* Multiply lower parts and add all */
49953 }
49954 else
49955 {
49956 machine_mode nmode;
49960 {
49963 }
49965 {
49968 }
49970 {
49973 }
49974 else
49978 /* Multiply low parts. */
49982 /* Shift input vectors right 32 bits so we can multiply high parts. */
49987 /* Multiply high parts by low parts. */
49993 /* Combine and shift the highparts back. */
49997 /* Combine high and low parts. */
49999 }
50003 }
50005 /* Return 1 if control tansfer instruction INSN
50006 should be encoded with bnd prefix.
50007 If insn is NULL then return 1 when control
50008 transfer instructions should be prefixed with
50009 bnd by default for current function. */
50011 bool
50013 {
50014 /* For call insns check special flag. */
50016 {
50020 }
50022 /* All other insns are prefixed only if function is instrumented. */
50024 }
50026 /* Calculate integer abs() using only SSE2 instructions. */
50028 void
50030 {
50035 {
50036 /* For 32-bit signed integer X, the best way to calculate the absolute
50037 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
50049 /* For 16-bit signed integer X, the best way to calculate the absolute
50050 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
50058 /* For 8-bit signed integer X, the best way to calculate the absolute
50059 value of X is min ((unsigned char) X, (unsigned char) (-X)),
50060 as SSE2 provides the PMINUB insn. */
50070 }
50074 }
50076 /* Expand an insert into a vector register through pinsr insn.
50077 Return true if successful. */
50079 bool
50081 {
50089 {
50092 }
50098 {
50103 {
50110 {
50142 }
50156 }
50160 }
50161 }
50162 \f
50163 /* This function returns the calling abi specific va_list type node.
50164 It returns the FNDECL specific va_list type. */
50166 static tree
50168 {
50175 else
50177 }
50179 /* Returns the canonical va_list type specified by TYPE. If there
50180 is no valid TYPE provided, it return NULL_TREE. */
50182 static tree
50184 {
50187 /* Resolve references and pointers to va_list type. */
50196 {
50201 {
50202 /* If va_list is an array type, the argument may have decayed
50203 to a pointer type, e.g. by being passed to another function.
50204 In that case, unwrap both types so that we can compare the
50205 underlying records. */
50208 {
50211 }
50212 }
50219 {
50220 /* If va_list is an array type, the argument may have decayed
50221 to a pointer type, e.g. by being passed to another function.
50222 In that case, unwrap both types so that we can compare the
50223 underlying records. */
50226 {
50229 }
50230 }
50237 {
50238 /* If va_list is an array type, the argument may have decayed
50239 to a pointer type, e.g. by being passed to another function.
50240 In that case, unwrap both types so that we can compare the
50241 underlying records. */
50244 {
50247 }
50248 }
50252 }
50254 }
50256 /* Iterate through the target-specific builtin types for va_list.
50257 IDX denotes the iterator, *PTREE is set to the result type of
50258 the va_list builtin, and *PNAME to its internal type.
50259 Returns zero if there is no element for this index, otherwise
50260 IDX should be increased upon the next call.
50261 Note, do not iterate a base builtin's name like __builtin_va_list.
50262 Used from c_common_nodes_and_builtins. */
50264 static int
50266 {
50268 {
50270 {
50283 }
50284 }
50287 }
50289 #undef TARGET_SCHED_DISPATCH
50290 #define TARGET_SCHED_DISPATCH has_dispatch
50291 #undef TARGET_SCHED_DISPATCH_DO
50292 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50293 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50294 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50295 #undef TARGET_SCHED_REORDER
50296 #define TARGET_SCHED_REORDER ix86_sched_reorder
50297 #undef TARGET_SCHED_ADJUST_PRIORITY
50298 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50299 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50300 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50301 ix86_dependencies_evaluation_hook
50303 /* The size of the dispatch window is the total number of bytes of
50304 object code allowed in a window. */
50305 #define DISPATCH_WINDOW_SIZE 16
50307 /* Number of dispatch windows considered for scheduling. */
50308 #define MAX_DISPATCH_WINDOWS 3
50310 /* Maximum number of instructions in a window. */
50311 #define MAX_INSN 4
50313 /* Maximum number of immediate operands in a window. */
50314 #define MAX_IMM 4
50316 /* Maximum number of immediate bits allowed in a window. */
50317 #define MAX_IMM_SIZE 128
50319 /* Maximum number of 32 bit immediates allowed in a window. */
50320 #define MAX_IMM_32 4
50322 /* Maximum number of 64 bit immediates allowed in a window. */
50323 #define MAX_IMM_64 2
50325 /* Maximum total of loads or prefetches allowed in a window. */
50326 #define MAX_LOAD 2
50328 /* Maximum total of stores allowed in a window. */
50329 #define MAX_STORE 1
50331 #undef BIG
50332 #define BIG 100
50335 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50338 disp_load,
50339 disp_store,
50340 disp_load_store,
50341 disp_prefetch,
50342 disp_imm,
50343 disp_imm_32,
50344 disp_imm_64,
50345 disp_branch,
50346 disp_cmp,
50347 disp_jcc,
50348 disp_last
50349 };
50351 /* Number of allowable groups in a dispatch window. It is an array
50352 indexed by dispatch_group enum. 100 is used as a big number,
50353 because the number of these kind of operations does not have any
50354 effect in dispatch window, but we need them for other reasons in
50355 the table. */
50358 };
50364 };
50366 /* Instruction path. */
50372 last_path
50373 };
50375 /* sched_insn_info defines a window to the instructions scheduled in
50376 the basic block. It contains a pointer to the insn_info table and
50377 the instruction scheduled.
50379 Windows are allocated for each basic block and are linked
50380 together. */
50382 rtx insn;
50389 /* Linked list of dispatch windows. This is a two way list of
50390 dispatch windows of a basic block. It contains information about
50391 the number of uops in the window and the total number of
50392 instructions and of bytes in the object code for this dispatch
50393 window. */
50411 /* Immediate valuse used in an insn. */
50413 {
50422 /* Get dispatch group of insn. */
50424 static enum dispatch_group
50426 {
50442 }
50444 /* Return true if insn is a compare instruction. */
50446 static bool
50448 {
50456 }
50458 /* Return true if a dispatch violation encountered. */
50460 static bool
50462 {
50466 }
50468 /* Return true if insn is a branch instruction. */
50470 static bool
50472 {
50474 }
50476 /* Return true if insn is a prefetch instruction. */
50478 static bool
50480 {
50482 }
50484 /* This function initializes a dispatch window and the list container holding a
50485 pointer to the window. */
50487 static void
50489 {
50495 else
50513 {
50519 }
50521 }
50523 /* This function allocates and initializes a dispatch window and the
50524 list container holding a pointer to the window. */
50528 {
50533 }
50535 /* This routine initializes the dispatch scheduling information. It
50536 initiates building dispatch scheduler tables and constructs the
50537 first dispatch window. */
50539 static void
50541 {
50542 /* Allocate a dispatch list and a window. */
50547 }
50549 /* This function returns true if a branch is detected. End of a basic block
50550 does not have to be a branch, but here we assume only branches end a
50551 window. */
50553 static bool
50555 {
50557 }
50559 /* This function is called when the end of a window processing is reached. */
50561 static void
50563 {
50566 {
50571 }
50573 }
50575 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50576 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50577 for 48 bytes of instructions. Note that these windows are not dispatch
50578 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50582 {
50584 {
50589 }
50595 }
50597 /* Compute number of immediate operands of an instruction. */
50599 static void
50601 {
50608 {
50615 else
50627 {
50630 }
50635 }
50636 }
50638 /* Return total size of immediate operands of an instruction along with number
50639 of corresponding immediate-operands. It initializes its parameters to zero
50640 befor calling FIND_CONSTANT.
50641 INSN is the input instruction. IMM is the total of immediates.
50642 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
50643 bit immediates. */
50645 static int
50647 {
50655 }
50657 /* This function indicates if an operand of an instruction is an
50658 immediate. */
50660 static bool
50662 {
50671 }
50673 /* Return single or double path for instructions. */
50675 static enum insn_path
50677 {
50687 }
50689 /* Return insn dispatch group. */
50691 static enum dispatch_group
50693 {
50711 }
50713 /* Count number of GROUP restricted instructions in a dispatch
50714 window WINDOW_LIST. */
50716 static int
50718 {
50729 {
50748 }
50761 }
50763 /* This function returns true if insn satisfies dispatch rules on the
50764 last window scheduled. */
50766 static bool
50768 {
50776 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
50777 instructions should be given the lowest priority in the
50778 scheduling process in Haifa scheduler to make sure they will be
50779 scheduled in the same dispatch window as the reference to them. */
50783 /* Check nonrestricted. */
50787 /* Get last dispatch window. */
50792 {
50797 /* Window 1 is full. Go for next window. */
50799 }
50806 /* See if it fits in the first window. */
50808 {
50809 /* The first widow should have only single and double path
50810 uops. */
50816 }
50818 }
50820 /* Add an instruction INSN with NUM_UOPS micro-operations to the
50821 dispatch window WINDOW_LIST. */
50823 static void
50825 {
50843 /* Initialize window with new instruction. */
50864 {
50867 }
50868 }
50870 /* Adds a scheduled instruction, INSN, to the current dispatch window.
50871 If the total bytes of instructions or the number of instructions in
50872 the window exceed allowable, it allocates a new window. */
50874 static void
50876 {
50899 /* Get the last dispatch window. */
50907 else
50910 /* If current window is full, get a new window.
50911 Window number zero is full, if MAX_INSN uops are scheduled in it.
50912 Window number one is full, if window zero's bytes plus window
50913 one's bytes is 32, or if the bytes of the new instruction added
50914 to the total makes it greater than 48, or it has already MAX_INSN
50915 instructions in it. */
50924 {
50927 }
50930 {
50934 {
50937 }
50938 }
50940 {
50945 {
50948 }
50951 }
50952 else
50956 {
50957 /* End of basic block is reached do end-basic-block process. */
50960 }
50961 }
50963 /* Print the dispatch window, WINDOW_NUM, to FILE. */
50965 DEBUG_FUNCTION static void
50967 {
50973 else
50987 {
50990 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
50996 }
50997 }
50999 /* Print to stdout a dispatch window. */
51001 DEBUG_FUNCTION void
51003 {
51005 }
51007 /* Print INSN dispatch information to FILE. */
51009 DEBUG_FUNCTION static void
51011 {
51034 }
51036 /* Print to STDERR the status of the ready list with respect to
51037 dispatch windows. */
51039 DEBUG_FUNCTION void
51041 {
51049 }
51051 /* This routine is the driver of the dispatch scheduler. */
51053 static void
51055 {
51060 }
51062 /* Return TRUE if Dispatch Scheduling is supported. */
51064 static bool
51066 {
51070 {
51086 }
51089 }
51091 /* Implementation of reassociation_width target hook used by
51092 reassoc phase to identify parallelism level in reassociated
51093 tree. Statements tree_code is passed in OPC. Arguments type
51094 is passed in MODE.
51096 Currently parallel reassociation is enabled for Atom
51097 processors only and we set reassociation width to be 2
51098 because Atom may issue up to 2 instructions per cycle.
51100 Return value should be fixed if parallel reassociation is
51101 enabled for other processors. */
51103 static int
51105 {
51106 /* Vector part. */
51108 {
51111 else
51113 }
51115 /* Scalar part. */
51120 else
51122 }
51124 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51125 place emms and femms instructions. */
51127 static machine_mode
51129 {
51134 {
51153 else
51165 /* FALLTHRU */
51169 }
51170 }
51172 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51173 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51174 256bit and 128bit vectors. */
51176 static unsigned int
51178 {
51181 }
51183 \f
51185 /* Return class of registers which could be used for pseudo of MODE
51186 and of class RCLASS for spilling instead of memory. Return NO_REGS
51187 if it is not possible or non-profitable. */
51188 static reg_class_t
51190 {
51196 }
51198 /* Implement targetm.vectorize.init_cost. */
51202 {
51206 }
51208 /* Implement targetm.vectorize.add_stmt_cost. */
51210 static unsigned
51214 {
51221 /* Statements in an inner loop relative to the loop being
51222 vectorized are weighted more heavily. The value here is
51223 arbitrary and could potentially be improved with analysis. */
51229 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51230 for Silvermont as it has out of order integer pipeline and can execute
51231 2 scalar instruction per tick, but has in order SIMD pipeline. */
51234 {
51238 }
51243 }
51245 /* Implement targetm.vectorize.finish_cost. */
51247 static void
51250 {
51255 }
51257 /* Implement targetm.vectorize.destroy_cost_data. */
51259 static void
51261 {
51263 }
51265 /* Validate target specific memory model bits in VAL. */
51267 static unsigned HOST_WIDE_INT
51269 {
51276 {
51280 }
51283 {
51287 }
51289 {
51293 }
51295 }
51297 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51298 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51299 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51300 or number of vecsize_mangle variants that should be emitted. */
51302 static int
51306 {
51313 {
51317 }
51322 {
51329 /* case SCmode: */
51330 /* case DCmode: */
51336 }
51338 tree t;
51342 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51344 {
51351 /* case SCmode: */
51352 /* case DCmode: */
51358 }
51361 {
51362 /* Parse here processor clause. If not present, default to 'b'. */
51364 }
51366 {
51367 /* If the function isn't exported, we can pick up just one ISA
51368 for the clones. */
51373 else
51376 }
51377 else
51378 {
51381 }
51383 {
51396 }
51398 {
51401 else
51406 }
51408 }
51410 /* Add target attribute to SIMD clone NODE if needed. */
51412 static void
51414 {
51418 {
51433 }
51443 }
51445 /* If SIMD clone NODE can't be used in a vectorized loop
51446 in current function, return -1, otherwise return a badness of using it
51447 (0 if it is most desirable from vecsize_mangle point of view, 1
51448 slightly less desirable, etc.). */
51450 static int
51452 {
51454 {
51472 }
51473 }
51475 /* This function adjusts the unroll factor based on
51476 the hardware capabilities. For ex, bdver3 has
51477 a loop buffer which makes unrolling of smaller
51478 loops less important. This function decides the
51479 unroll factor using number of memory references
51480 (value 32 is used) as a heuristic. */
51482 static unsigned
51484 {
51493 /* Count the number of memory references within the loop body.
51494 This value determines the unrolling factor for bdver3 and bdver4
51495 architectures. */
51504 {
51509 else
51511 }
51518 }
51521 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51523 static bool
51525 {
51526 /* For x87 floating point with standard excess precision handling,
51527 there is no adddf3 pattern (since x87 floating point only has
51528 XFmode operations) so the default hook implementation gets this
51529 wrong. */
51531 }
51533 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51535 static void
51537 {
51542 {
51557 hold_fnclex);
51570 }
51572 {
51581 mxcsr_orig_var,
51591 ldmxcsr_hold_call);
51594 else
51599 ldmxcsr_clear_call);
51600 else
51604 stxmcsr_update_call);
51606 {
51612 exceptions_assign);
51613 }
51614 else
51619 ldmxcsr_update_call);
51620 }
51621 tree atomic_feraiseexcept
51626 atomic_feraiseexcept_call);
51627 }
51629 /* Return mode to be used for bounds or VOIDmode
51630 if bounds are not supported. */
51632 static enum machine_mode
51634 {
51635 /* Do not support pointer checker if MPX
51636 is not enabled. */
51638 {
51643 }
51646 }
51648 /* Return constant used to statically initialize constant bounds.
51650 This function is used to create special bound values. For now
51651 only INIT bounds and NONE bounds are expected. More special
51652 values may be added later. */
51654 static tree
51656 {
51662 /* This function is supposed to be used to create INIT and
51663 NONE bounds only. */
51668 }
51670 /* Generate a list of statements STMTS to initialize pointer bounds
51671 variable VAR with bounds LB and UB. Return the number of generated
51672 statements. */
51674 static int
51676 {
51694 }
51696 #if !TARGET_MACHO && !TARGET_DLLIMPORT_DECL_ATTRIBUTES
51697 /* For i386, common symbol is local only for non-PIE binaries. For
51698 x86-64, common symbol is local only for non-PIE binaries or linker
51699 supports copy reloc in PIE binaries. */
51701 static bool
51703 {
51705 (!flag_pic
51706 || (TARGET_64BIT
51708 }
51709 #endif
51711 /* If MEM is in the form of [base+offset], extract the two parts
51712 of address and set to BASE and OFFSET, otherwise return false. */
51714 static bool
51716 {
51717 rtx addr;
51727 {
51731 }
51737 {
51741 }
51744 }
51746 /* Given OPERANDS of consecutive load/store, check if we can merge
51747 them into move multiple. LOAD is true if they are load instructions.
51748 MODE is the mode of memory operands. */
51750 bool
51753 {
51758 {
51763 }
51764 else
51765 {
51770 }
51777 /* Check if the addresses are in the form of [base+offset]. */
51783 /* Check if the bases are the same. */
51790 /* Check if mem_1 is adjacent to mem_2 and mem_1 has lower address. */
51795 }
51797 /* Initialize the GCC target structure. */
51798 #undef TARGET_RETURN_IN_MEMORY
51799 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
51801 #undef TARGET_LEGITIMIZE_ADDRESS
51802 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
51804 #undef TARGET_ATTRIBUTE_TABLE
51805 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
51806 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
51807 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
51808 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51809 # undef TARGET_MERGE_DECL_ATTRIBUTES
51810 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
51811 #endif
51813 #undef TARGET_COMP_TYPE_ATTRIBUTES
51814 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
51816 #undef TARGET_INIT_BUILTINS
51817 #define TARGET_INIT_BUILTINS ix86_init_builtins
51818 #undef TARGET_BUILTIN_DECL
51819 #define TARGET_BUILTIN_DECL ix86_builtin_decl
51820 #undef TARGET_EXPAND_BUILTIN
51821 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
51823 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
51824 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
51825 ix86_builtin_vectorized_function
51827 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
51828 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
51830 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
51831 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
51833 #undef TARGET_VECTORIZE_BUILTIN_GATHER
51834 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
51836 #undef TARGET_BUILTIN_RECIPROCAL
51837 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
51839 #undef TARGET_ASM_FUNCTION_EPILOGUE
51840 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
51842 #undef TARGET_ENCODE_SECTION_INFO
51843 #ifndef SUBTARGET_ENCODE_SECTION_INFO
51844 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
51845 #else
51846 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
51847 #endif
51849 #undef TARGET_ASM_OPEN_PAREN
51851 #undef TARGET_ASM_CLOSE_PAREN
51854 #undef TARGET_ASM_BYTE_OP
51855 #define TARGET_ASM_BYTE_OP ASM_BYTE
51857 #undef TARGET_ASM_ALIGNED_HI_OP
51858 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
51859 #undef TARGET_ASM_ALIGNED_SI_OP
51860 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
51861 #ifdef ASM_QUAD
51862 #undef TARGET_ASM_ALIGNED_DI_OP
51863 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
51864 #endif
51866 #undef TARGET_PROFILE_BEFORE_PROLOGUE
51867 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
51869 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
51870 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
51872 #undef TARGET_ASM_UNALIGNED_HI_OP
51873 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
51874 #undef TARGET_ASM_UNALIGNED_SI_OP
51875 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
51876 #undef TARGET_ASM_UNALIGNED_DI_OP
51877 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
51879 #undef TARGET_PRINT_OPERAND
51880 #define TARGET_PRINT_OPERAND ix86_print_operand
51881 #undef TARGET_PRINT_OPERAND_ADDRESS
51882 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
51883 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
51884 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
51885 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
51886 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
51888 #undef TARGET_SCHED_INIT_GLOBAL
51889 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
51890 #undef TARGET_SCHED_ADJUST_COST
51891 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
51892 #undef TARGET_SCHED_ISSUE_RATE
51893 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
51894 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
51895 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
51896 ia32_multipass_dfa_lookahead
51897 #undef TARGET_SCHED_MACRO_FUSION_P
51898 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
51899 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
51900 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
51902 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
51903 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
51905 #undef TARGET_MEMMODEL_CHECK
51906 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
51908 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
51909 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
51911 #ifdef HAVE_AS_TLS
51912 #undef TARGET_HAVE_TLS
51913 #define TARGET_HAVE_TLS true
51914 #endif
51915 #undef TARGET_CANNOT_FORCE_CONST_MEM
51916 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
51917 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
51918 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
51920 #undef TARGET_DELEGITIMIZE_ADDRESS
51921 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
51923 #undef TARGET_MS_BITFIELD_LAYOUT_P
51924 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
51926 #if TARGET_MACHO
51927 #undef TARGET_BINDS_LOCAL_P
51928 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
51929 #else
51930 #undef TARGET_BINDS_LOCAL_P
51931 #define TARGET_BINDS_LOCAL_P ix86_binds_local_p
51932 #endif
51933 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51934 #undef TARGET_BINDS_LOCAL_P
51935 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
51936 #endif
51938 #undef TARGET_ASM_OUTPUT_MI_THUNK
51939 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
51940 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
51941 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
51943 #undef TARGET_ASM_FILE_START
51944 #define TARGET_ASM_FILE_START x86_file_start
51946 #undef TARGET_OPTION_OVERRIDE
51947 #define TARGET_OPTION_OVERRIDE ix86_option_override
51949 #undef TARGET_REGISTER_MOVE_COST
51950 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
51951 #undef TARGET_MEMORY_MOVE_COST
51952 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
51953 #undef TARGET_RTX_COSTS
51954 #define TARGET_RTX_COSTS ix86_rtx_costs
51955 #undef TARGET_ADDRESS_COST
51956 #define TARGET_ADDRESS_COST ix86_address_cost
51958 #undef TARGET_FIXED_CONDITION_CODE_REGS
51959 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
51960 #undef TARGET_CC_MODES_COMPATIBLE
51961 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
51963 #undef TARGET_MACHINE_DEPENDENT_REORG
51964 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
51966 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
51967 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
51969 #undef TARGET_BUILD_BUILTIN_VA_LIST
51970 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
51972 #undef TARGET_FOLD_BUILTIN
51973 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
51975 #undef TARGET_COMPARE_VERSION_PRIORITY
51976 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
51978 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
51979 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
51980 ix86_generate_version_dispatcher_body
51982 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
51983 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
51984 ix86_get_function_versions_dispatcher
51986 #undef TARGET_ENUM_VA_LIST_P
51987 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
51989 #undef TARGET_FN_ABI_VA_LIST
51990 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
51992 #undef TARGET_CANONICAL_VA_LIST_TYPE
51993 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
51995 #undef TARGET_EXPAND_BUILTIN_VA_START
51996 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
51998 #undef TARGET_MD_ASM_CLOBBERS
51999 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
52001 #undef TARGET_PROMOTE_PROTOTYPES
52002 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
52003 #undef TARGET_SETUP_INCOMING_VARARGS
52004 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
52005 #undef TARGET_MUST_PASS_IN_STACK
52006 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
52007 #undef TARGET_FUNCTION_ARG_ADVANCE
52008 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
52009 #undef TARGET_FUNCTION_ARG
52010 #define TARGET_FUNCTION_ARG ix86_function_arg
52011 #undef TARGET_INIT_PIC_REG
52012 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
52013 #undef TARGET_USE_PSEUDO_PIC_REG
52014 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
52015 #undef TARGET_FUNCTION_ARG_BOUNDARY
52016 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
52017 #undef TARGET_PASS_BY_REFERENCE
52018 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
52019 #undef TARGET_INTERNAL_ARG_POINTER
52020 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
52021 #undef TARGET_UPDATE_STACK_BOUNDARY
52022 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
52023 #undef TARGET_GET_DRAP_RTX
52024 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
52025 #undef TARGET_STRICT_ARGUMENT_NAMING
52026 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
52027 #undef TARGET_STATIC_CHAIN
52028 #define TARGET_STATIC_CHAIN ix86_static_chain
52029 #undef TARGET_TRAMPOLINE_INIT
52030 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
52031 #undef TARGET_RETURN_POPS_ARGS
52032 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
52034 #undef TARGET_LEGITIMATE_COMBINED_INSN
52035 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
52037 #undef TARGET_ASAN_SHADOW_OFFSET
52038 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
52040 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
52041 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
52043 #undef TARGET_SCALAR_MODE_SUPPORTED_P
52044 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
52046 #undef TARGET_VECTOR_MODE_SUPPORTED_P
52047 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
52049 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
52050 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
52051 ix86_libgcc_floating_mode_supported_p
52053 #undef TARGET_C_MODE_FOR_SUFFIX
52054 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
52056 #ifdef HAVE_AS_TLS
52057 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
52058 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
52059 #endif
52061 #ifdef SUBTARGET_INSERT_ATTRIBUTES
52062 #undef TARGET_INSERT_ATTRIBUTES
52063 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
52064 #endif
52066 #undef TARGET_MANGLE_TYPE
52067 #define TARGET_MANGLE_TYPE ix86_mangle_type
52069 #if !TARGET_MACHO
52070 #undef TARGET_STACK_PROTECT_FAIL
52071 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
52072 #endif
52074 #undef TARGET_FUNCTION_VALUE
52075 #define TARGET_FUNCTION_VALUE ix86_function_value
52077 #undef TARGET_FUNCTION_VALUE_REGNO_P
52078 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
52080 #undef TARGET_PROMOTE_FUNCTION_MODE
52081 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
52083 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
52084 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ix86_override_options_after_change
52086 #undef TARGET_MEMBER_TYPE_FORCES_BLK
52087 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
52089 #undef TARGET_INSTANTIATE_DECLS
52090 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
52092 #undef TARGET_SECONDARY_RELOAD
52093 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
52095 #undef TARGET_CLASS_MAX_NREGS
52096 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
52098 #undef TARGET_PREFERRED_RELOAD_CLASS
52099 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
52100 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
52101 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
52102 #undef TARGET_CLASS_LIKELY_SPILLED_P
52103 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
52105 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
52106 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
52107 ix86_builtin_vectorization_cost
52108 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
52109 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
52110 ix86_vectorize_vec_perm_const_ok
52111 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
52112 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
52113 ix86_preferred_simd_mode
52114 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
52115 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
52116 ix86_autovectorize_vector_sizes
52117 #undef TARGET_VECTORIZE_INIT_COST
52118 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
52119 #undef TARGET_VECTORIZE_ADD_STMT_COST
52120 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
52121 #undef TARGET_VECTORIZE_FINISH_COST
52122 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
52123 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
52124 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
52126 #undef TARGET_SET_CURRENT_FUNCTION
52127 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
52129 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
52130 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
52132 #undef TARGET_OPTION_SAVE
52133 #define TARGET_OPTION_SAVE ix86_function_specific_save
52135 #undef TARGET_OPTION_RESTORE
52136 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
52138 #undef TARGET_OPTION_POST_STREAM_IN
52139 #define TARGET_OPTION_POST_STREAM_IN ix86_function_specific_post_stream_in
52141 #undef TARGET_OPTION_PRINT
52142 #define TARGET_OPTION_PRINT ix86_function_specific_print
52144 #undef TARGET_OPTION_FUNCTION_VERSIONS
52145 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
52147 #undef TARGET_CAN_INLINE_P
52148 #define TARGET_CAN_INLINE_P ix86_can_inline_p
52150 #undef TARGET_EXPAND_TO_RTL_HOOK
52151 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
52153 #undef TARGET_LEGITIMATE_ADDRESS_P
52154 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
52156 #undef TARGET_LRA_P
52157 #define TARGET_LRA_P hook_bool_void_true
52159 #undef TARGET_REGISTER_PRIORITY
52160 #define TARGET_REGISTER_PRIORITY ix86_register_priority
52162 #undef TARGET_REGISTER_USAGE_LEVELING_P
52163 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
52165 #undef TARGET_LEGITIMATE_CONSTANT_P
52166 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
52168 #undef TARGET_FRAME_POINTER_REQUIRED
52169 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
52171 #undef TARGET_CAN_ELIMINATE
52172 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
52174 #undef TARGET_EXTRA_LIVE_ON_ENTRY
52175 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
52177 #undef TARGET_ASM_CODE_END
52178 #define TARGET_ASM_CODE_END ix86_code_end
52180 #undef TARGET_CONDITIONAL_REGISTER_USAGE
52181 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
52183 #if TARGET_MACHO
52184 #undef TARGET_INIT_LIBFUNCS
52185 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
52186 #endif
52188 #undef TARGET_LOOP_UNROLL_ADJUST
52189 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52191 #undef TARGET_SPILL_CLASS
52192 #define TARGET_SPILL_CLASS ix86_spill_class
52194 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52195 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52196 ix86_simd_clone_compute_vecsize_and_simdlen
52198 #undef TARGET_SIMD_CLONE_ADJUST
52199 #define TARGET_SIMD_CLONE_ADJUST \
52200 ix86_simd_clone_adjust
52202 #undef TARGET_SIMD_CLONE_USABLE
52203 #define TARGET_SIMD_CLONE_USABLE \
52204 ix86_simd_clone_usable
52206 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52207 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52208 ix86_float_exceptions_rounding_supported_p
52210 #undef TARGET_MODE_EMIT
52211 #define TARGET_MODE_EMIT ix86_emit_mode_set
52213 #undef TARGET_MODE_NEEDED
52214 #define TARGET_MODE_NEEDED ix86_mode_needed
52216 #undef TARGET_MODE_AFTER
52217 #define TARGET_MODE_AFTER ix86_mode_after
52219 #undef TARGET_MODE_ENTRY
52220 #define TARGET_MODE_ENTRY ix86_mode_entry
52222 #undef TARGET_MODE_EXIT
52223 #define TARGET_MODE_EXIT ix86_mode_exit
52225 #undef TARGET_MODE_PRIORITY
52226 #define TARGET_MODE_PRIORITY ix86_mode_priority
52228 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52229 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52231 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52232 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52234 #undef TARGET_STORE_BOUNDS_FOR_ARG
52235 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52237 #undef TARGET_LOAD_RETURNED_BOUNDS
52238 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52240 #undef TARGET_STORE_RETURNED_BOUNDS
52241 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52243 #undef TARGET_CHKP_BOUND_MODE
52244 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52246 #undef TARGET_BUILTIN_CHKP_FUNCTION
52247 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52249 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52250 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52252 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52253 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52255 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52256 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52258 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52259 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52261 #undef TARGET_OFFLOAD_OPTIONS
52262 #define TARGET_OFFLOAD_OPTIONS \
52263 ix86_offload_options
52265 #undef TARGET_ABSOLUTE_BIGGEST_ALIGNMENT
52266 #define TARGET_ABSOLUTE_BIGGEST_ALIGNMENT 512
52269 \f