| blob | fa9dd7420b7cb25fb45e32f18334074e92117d38 |
1 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
3 PR tree-optimization/113205
4 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
5 the proposed layout if it does not allow a source partition with
6 layout 2 to keep that layout.
8 2024-02-24 Jakub Jelinek <jakub@redhat.com>
10 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
11 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
12 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
13 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
14 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
15 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
16 macros.
17 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
18 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
19 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
20 HOST_WIDE_INT_UC macros.
21 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
22 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
23 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
24 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
25 macros.
26 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
27 * config/i386/constraints.md (define_constraint "L"): Use
28 HOST_WIDE_INT_C macro.
29 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
30 macro.
31 (movl + movb peephole2): Likewise.
32 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
33 (const_32bit_mask): Likewise.
35 2024-02-24 Jakub Jelinek <jakub@redhat.com>
37 PR middle-end/114073
38 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
39 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
40 types like vector or complex types.
41 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
42 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
43 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
45 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
47 PR target/114028
48 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
49 Return false if inner mode is already Pmode.
50 (rvv_builder::is_all_same_sequence): New function.
51 (expand_vec_init): Emit broadcast if sequence is all same.
53 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
55 PR target/113613
56 * config/aarch64/aarch64-early-ra.cc
57 (early_ra::m_current_region): New member variable.
58 (early_ra::m_fpr_recency): Likewise.
59 (early_ra::start_new_region): Bump m_current_region.
60 (early_ra::allocate_colors): Prefer less recently used registers
61 in the event of a tie. Add a comment to explain why we prefer(ed)
62 higher-numbered registers.
63 (early_ra::find_oldest_color): Prefer less recently used registers
64 here too.
65 (early_ra::finalize_allocation): Update recency information for
66 allocated registers.
67 (early_ra::process_blocks): Initialize m_current_region and
68 m_fpr_recency.
70 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
72 PR target/113295
73 * config/aarch64/aarch64-early-ra.cc
74 (early_ra::test_strictness): New enum.
75 (early_ra::is_chain_candidate): Add a strictness parameter to
76 control whether only correctness matters, or whether both correctness
77 and heuristics should be used. Handle multiple levels of equivalence.
78 (early_ra::find_related_start): Update call accordingly.
79 (early_ra::strided_polarity_pref): Likewise.
80 (early_ra::form_chains): Likewise.
81 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
82 correctness mode rather than trying to inline the test.
84 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
86 PR target/113295
87 * config/aarch64/aarch64-early-ra.cc
88 (early_ra::find_related_start): Account for definitions by shared
89 registers when testing for a single register definition.
90 (early_ra::accumulate_defs): New function.
91 (early_ra::record_copy): If A shares B's register, fold A's
92 definition information into B's. Fold A's use information into B's.
94 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
96 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
97 if R_X86_64_CODE_6_GOTTPOFF is supported.
98 * config.in: Regenerated.
99 * configure: Likewise.
100 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
101 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
103 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
105 PR target/108120
106 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
107 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
109 2024-02-23 Jakub Jelinek <jakub@redhat.com>
111 PR rtl-optimization/114054
112 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
113 temp variable instead of target parameter for result.
115 2024-02-23 Jakub Jelinek <jakub@redhat.com>
117 PR tree-optimization/114040
118 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
119 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
120 probability from likely to unlikely. When handling the true true
121 store, first cast to limb_access_type and then to l's type.
123 2024-02-23 Richard Biener <rguenther@suse.de>
125 PR target/90785
126 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
128 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
130 PR other/109668
131 * config/riscv/arch-canonicalize: Move to python3
132 * config/riscv/multilib-generator: Likewise
134 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
136 * doc/invoke.texi: Document -mcpu.
138 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
140 * configure: Regenerate.
141 * configure.ac: Add parameter "--fatal-warnings" to assemble
142 when checking whether the assemble support conditional branch
143 relaxation.
145 2024-02-22 Jakub Jelinek <jakub@redhat.com>
147 PR c/114007
148 * doc/extend.texi: (__extension__): Remove comments about scope
149 tokens vs. two colons.
151 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
153 PR tree-optimization/109804
154 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
155 DEMANGLE_COMPONENT_UNNAMED_TYPE.
157 2024-02-22 Richard Biener <rguenther@suse.de>
159 PR tree-optimization/114048
160 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
161 can also produce -1 off.
163 2024-02-22 Richard Biener <rguenther@suse.de>
165 PR tree-optimization/114027
166 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
167 condition reduction classification only for single-element
168 chains.
170 2024-02-22 Jakub Jelinek <jakub@redhat.com>
172 PR ipa/111960
173 * profile-count.h (profile_count::dump): Remove overload with
174 char * first argument.
175 * profile-count.cc (profile_count::dump): Change overload with char *
176 first argument which uses sprintf into the overfload with FILE *
177 first argument and use fprintf instead. Remove overload which wrapped
178 it.
180 2024-02-22 Jakub Jelinek <jakub@redhat.com>
182 PR tree-optimization/113993
183 * tree-call-cdce.cc (get_no_error_domain): Handle
184 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
185 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
186 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
187 the as the F128 suffixed cases, otherwise as non-suffixed ones.
188 Handle BUILT_IN_{EXP,POW}10L for
189 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
190 as (-inf, 4932).
192 2024-02-22 Jakub Jelinek <jakub@redhat.com>
194 PR tree-optimization/114038
195 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
196 loop exit condition if end is divisible by limb_prec.
198 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
200 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
201 problem of mabi=, mno-flush-func, mexplicit-relocs;
202 add missing leading - of mbranch-cost option.
203 * config/mips/mips.opt.urls: Regenerate.
205 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
207 PR target/109987
208 * config/rs6000/constraints.md (we): Update internal doc without
209 referring to option -mpower9-vector.
210 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
211 special handlings.
212 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
213 OTHER_P8_VECTOR_MASKS): Merge to ...
214 (OTHER_VSX_VECTOR_MASKS): ... here.
215 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
216 some error message handlings and explicit option mask adjustments on
217 explicit option power{8,9}-vector conflicting with other options.
218 (rs6000_print_isa_options): Update comments.
219 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
220 related array items and handlings.
221 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
222 special handlings.
223 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
224 WarnRemoved.
225 * doc/extend.texi: Remove documentation referring to option
226 -mpower8-vector.
227 * doc/invoke.texi: Remove documentation for option
228 -mpower{8,9}-vector and adjust some documentation referring to them.
229 * doc/md.texi: Update documentation for constraint we.
230 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
232 2024-02-22 Pan Li <pan2.li@intel.com>
234 PR target/114017
235 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
236 the version to 0.12.
238 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
240 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
242 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
243 Robin Dapp <rdapp.gcc@gmail.com>
245 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
246 (generic_ooo_vec_load): Ditto
247 (generic_ooo_vec_store): Ditto
248 (generic_ooo_vec_loadstore_seg): Ditto
249 (generic_ooo_vec_alu): Ditto
250 (generic_ooo_vec_fcmp): Ditto
251 (generic_ooo_vec_imul): Ditto
252 (generic_ooo_vec_fadd): Ditto
253 (generic_ooo_vec_fmul): Ditto
254 (generic_ooo_crypto): Ditto
255 (generic_ooo_perm): Ditto
256 (generic_ooo_vec_reduction): Ditto
257 (generic_ooo_vec_ordered_reduction): Ditto
258 (generic_ooo_vec_idiv): Ditto
259 (generic_ooo_vec_float_divsqrt): Ditto
260 (generic_ooo_vec_mask): Ditto
261 (generic_ooo_vec_vesetvl): Ditto
262 (generic_ooo_vec_setrm): Ditto
263 (generic_ooo_vec_readlen): Ditto
264 * config/riscv/riscv.md: Include generic-vector-ooo
265 * config/riscv/generic-vector-ooo.md: New file. To here
267 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
269 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
270 (generic_ooo_branch): Ditto
271 * config/riscv/generic.md (generic_sfb_alu): Ditto
272 (generic_fmul_half): Ditto
273 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
274 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
275 (sifive_7_popcount): Ditto
276 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
277 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
278 * config/riscv/vector.md: Change rdfrm to fmove
279 * config/riscv/zc.md: Change pushpop to load/store
281 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
283 * doc/invoke.texi (Warning Options): Fix typos.
285 2024-02-21 David Faust <david.faust@oracle.com>
287 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
288 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
289 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
291 2024-02-21 Martin Jambor <mjambor@suse.cz>
293 PR ipa/113476
294 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
295 initializers in the contructor.
296 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
297 * ipa-cp.h: New file.
298 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
299 (ipcp_value_source): Move to ipa-cp.h.
300 (ipcp_value_base): Likewise.
301 (ipcp_value): Likewise.
302 (ipcp_lattice): Likewise.
303 (ipcp_agg_lattice): Likewise.
304 (ipcp_bits_lattice): Likewise.
305 (ipcp_vr_lattice): Likewise.
306 (ipcp_param_lattices): Likewise.
307 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
308 (ipa_value_from_jfunc): Adjust a check for empty lattices.
309 (ipa_context_from_jfunc): Likewise.
310 (ipa_agg_value_from_jfunc): Likewise.
311 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
312 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
313 just in contiguous memory.
314 (ipcp_store_vr_results): Adjust a check for empty lattices.
315 * auto-profile.cc: Include sreal.h and ipa-cp.h.
316 * cgraph.cc: Likewise.
317 * cgraphclones.cc: Likewise.
318 * cgraphunit.cc: Likewise.
319 * config/aarch64/aarch64.cc: Likewise.
320 * config/i386/i386-builtins.cc: Likewise.
321 * config/i386/i386-expand.cc: Likewise.
322 * config/i386/i386-features.cc: Likewise.
323 * config/i386/i386-options.cc: Likewise.
324 * config/i386/i386.cc: Likewise.
325 * config/rs6000/rs6000.cc: Likewise.
326 * config/s390/s390.cc: Likewise.
327 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
328 files to be included in gtype-desc.cc.
329 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
330 * ipa-devirt.cc: Likewise.
331 * ipa-fnsummary.cc: Likewise.
332 * ipa-icf.cc: Likewise.
333 * ipa-inline-analysis.cc: Likewise.
334 * ipa-inline-transform.cc: Likewise.
335 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
336 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
337 * ipa-param-manipulation.cc: Likewise.
338 * ipa-predicate.cc: Likewise.
339 * ipa-profile.cc: Likewise.
340 * ipa-prop.cc: Likewise.
341 (ipa_node_params_t::duplicate): Assert new lattices remain empty
342 instead of setting them to NULL.
343 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
344 * ipa-split.cc: Likewise.
345 * ipa-sra.cc: Likewise.
346 * ipa-strub.cc: Likewise.
347 * ipa-utils.cc: Likewise.
348 * ipa.cc: Likewise.
349 * toplev.cc: Likewise.
350 * tree-ssa-ccp.cc: Likewise.
351 * tree-ssa-sccvn.cc: Likewise.
352 * tree-vrp.cc: Likewise.
354 2024-02-21 Tamar Christina <tamar.christina@arm.com>
356 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
357 Armv8.7-a.
359 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
361 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
362 Use aarch64_gen_compare_zero_and_branch rather than emitting
363 a CBZ directly.
365 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
367 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
368 Remove duplicated call.
370 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
372 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
373 Check that each individual piece of state is shared in the same
374 way, rather than using an aggregate check for PSTATE.ZA.
376 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
378 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
379 In the code that commits a lazy save, only zero ZA if the function
380 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
382 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
384 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
385 directly inserting the associated sequence
386 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
387 ...here instead.
389 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
391 PR target/113995
392 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
393 fold the SVE allocation into the initial allocation if the
394 initial allocation includes a VG save.
396 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
398 PR target/113220
399 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
400 contain jumps even if called after initial RTL expansion.
401 * mode-switching.cc: Include cfgbuild.h.
402 (optimize_mode_switching): Allow the sequence returned by the
403 emit hook to contain internal jumps. Record which blocks
404 contain such jumps and split the blocks at the end.
405 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
406 non-debug insns when scanning the sequence.
408 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
410 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
411 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
413 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
415 * doc/invoke.texi (-mmcu): Add information about MCU specs.
417 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
419 * doc/invoke.texi (-minrt): Clarify that main
420 must take no arguments.
422 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
424 * config/avr/builtins.def: Use function prototypes of given size
425 and signedness.
426 * config/avr/avr.cc (avr_init_builtins): Adjust types required
427 by builtins.def.
428 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
430 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
432 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
433 instead of @table.
435 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
437 * config/bpf/bpf.opt: Add help information for -mcpu.
439 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
441 PR target/113805
442 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
443 New pass.
444 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
445 Declare.
446 * config/aarch64/aarch64.md (is_call): New attribute.
447 (*and<mode>3nr_compare0): Rename to...
448 (@aarch64_and<mode>3nr_compare0): ...this.
449 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
450 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
451 * config/aarch64/aarch64-speculation.cc: Update file comment to
452 describe the new late pass.
453 (aarch64_do_track_speculation): Handle is_call insns like other calls.
454 (pass_track_speculation): Add an is_late member variable.
455 (pass_track_speculation::gate): Run the late pass for streaming-
456 compatible functions and the early pass for other functions.
457 (make_pass_track_speculation): Update accordingly.
458 (make_pass_late_track_speculation): New function.
459 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
460 function.
461 (aarch64_guard_switch_pstate_sm): Use it.
463 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
465 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
466 Register these builtins with a pointer to uint64_t rather than unsigned
467 DI mode.
469 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
471 PR target/113615
472 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
473 Conditionalize on '!TARGET_RDNA2_PLUS'.
474 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
475 (gcn_expand_reduc_scalar):
476 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
478 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
480 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
481 '__gfx90a__' target CPU definition. Add some safeguards for the future.
483 2024-02-19 Richard Biener <rguenther@suse.de>
485 PR rtl-optimization/54052
486 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
487 local defs by LR_OUT.
489 2024-02-19 Jakub Jelinek <jakub@redhat.com>
491 PR tree-optimization/113967
492 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
493 in condition that @rpos is multiple of vector element size.
495 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
497 PR target/113696
498 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
499 Suppress vsetvl fusion.
501 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
503 PR target/113912
504 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
505 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
506 (ix86_emit_save_regs): Don't generate push2 if
507 ix86_can_use_push2pop2 return false.
508 (ix86_expand_epilogue): Don't generate pop2 if
509 ix86_can_use_push2pop2 return false.
511 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
513 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
514 Note on complete device support.
516 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
518 * doc/extend.texi (AVR Function Attributes): Fuse description
519 of "signal" and "interrupt" attribute. Link pseudo instruction.
521 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
523 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
524 symbol type conversions.
525 (__cacop_d): Likewise.
526 (__cpucfg): Likewise.
527 (__asrtle_d): Likewise.
528 (__asrtgt_d): Likewise.
529 (__lddir_d): Likewise.
530 (__ldpte_d): Likewise.
531 (__crc_w_b_w): Likewise.
532 (__crc_w_h_w): Likewise.
533 (__crc_w_w_w): Likewise.
534 (__crc_w_d_w): Likewise.
535 (__crcc_w_b_w): Likewise.
536 (__crcc_w_h_w): Likewise.
537 (__crcc_w_w_w): Likewise.
538 (__crcc_w_d_w): Likewise.
539 (__csrrd_w): Likewise.
540 (__csrwr_w): Likewise.
541 (__csrxchg_w): Likewise.
542 (__csrrd_d): Likewise.
543 (__csrwr_d): Likewise.
544 (__csrxchg_d): Likewise.
545 (__iocsrrd_b): Likewise.
546 (__iocsrrd_h): Likewise.
547 (__iocsrrd_w): Likewise.
548 (__iocsrrd_d): Likewise.
549 (__iocsrwr_b): Likewise.
550 (__iocsrwr_h): Likewise.
551 (__iocsrwr_w): Likewise.
552 (__iocsrwr_d): Likewise.
553 (__frecipe_s): Likewise.
554 (__frecipe_d): Likewise.
555 (__frsqrte_s): Likewise.
556 (__frsqrte_d): Likewise.
558 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
560 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
561 function return value type to unsigned short.
563 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
565 * doc/sourcebuild.texi: add scan-assembler-bound
567 2024-02-16 Jason Merrill <jason@redhat.com>
569 * gdbhooks.py: Fix regex syntax.
571 2024-02-16 Richard Biener <rguenther@suse.de>
573 PR tree-optimization/113895
574 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
575 consistency checking when there are out-of-bound array
576 accesses. Allow -1 off when from an array reference with
577 constant index.
579 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
581 PR target/106543
582 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
583 pattern.
585 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
587 * doc/sourcebuild.texi (Effective-Target Keywords, Other
588 attribugs): Document linker_plugin.
589 (Require Support): Document dg-require-linker-plugin.
591 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
593 PR target/109349
594 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
595 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
596 (RISCV_MINOR_VERSION_BASE): Ditto.
597 (RISCV_REVISION_VERSION_BASE): Ditto.
598 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
599 rather than magic number.
600 * config/riscv/riscv.h (riscv_arch_help): New.
601 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
602 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
603 --print-supported-extensions.
604 * config/riscv/riscv.opt (march=help): New.
605 (print-supported-extensions): New.
606 (-print-supported-extensions): New.
607 * doc/invoke.texi (RISC-V Options): Document -march=help.
609 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
611 PR target/113780
612 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
613 for indirect calls with 4 or more arguments in pac-enabled functions.
615 2024-02-15 David Faust <david.faust@oracle.com>
617 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
618 use ldxb instead of ldxh.
620 2024-02-15 Jakub Jelinek <jakub@redhat.com>
622 PR middle-end/113921
623 * cfgrtl.h (prepend_insn_to_edge): New declaration.
624 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
625 comment.
626 (prepend_insn_to_edge): New function.
627 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
628 insert_insn_on_edge.
630 2024-02-15 Richard Biener <rguenther@suse.de>
632 PR tree-optimization/111156
633 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
634 at the pattern stmt if any.
636 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
638 PR target/113927
639 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
640 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
641 * config/avr/avr.cc (avr_adiw_reg_p): New function.
642 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
643 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
644 * config/avr/avr.md: Same.
645 (attr "isa") <tiny, no_tiny>: Remove.
646 <adiw, no_adiw>: Add.
647 (define_insn, define_insn_and_split): When an alternative has
648 constraint "w", then set attribute "isa" to "adiw".
649 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
650 Built-in define __AVR_HAVE_ADIW__.
651 * doc/invoke.texi (AVR Options): Document it.
653 2024-02-15 Andrew Stubbs <ams@baylibre.com>
655 * config/gcn/gcn-valu.md
656 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
657 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
658 details are supported on RDNA devices.
660 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
662 PR middle-end/113508
663 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
664 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
665 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
666 Add sentence about what the mode m is.
668 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
670 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
671 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
672 var.
674 2024-02-15 Richard Biener <rguenther@suse.de>
676 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
677 stmts.
679 2024-02-15 Jakub Jelinek <jakub@redhat.com>
681 PR tree-optimization/113567
682 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
683 _BitInt multiplication, division or modulo with
684 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
685 force the affected inputs into a new SSA_NAME.
687 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
689 PR target/113871
690 * config/i386/mmx.md (V248FI): New mode iterator.
691 (V24FI_32): DItto.
692 (vec_shl_<V248FI:mode>): New expander.
693 (vec_shl_<V24FI_32:mode>): Ditto.
694 (vec_shr_<V248FI:mode>): Ditto.
695 (vec_shr_<V24FI_32:mode>): Ditto.
696 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
697 (vec_shr_<V248FI:mode>): Ditto.
699 2024-02-14 Jan Hubicka <jh@suse.cz>
701 PR tree-optimization/111054
702 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
704 2024-02-14 Tamar Christina <tamar.christina@arm.com>
706 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
708 2024-02-14 Richard Biener <rguenther@suse.de>
710 PR tree-optimization/113910
711 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
712 the hashval_t hash.
714 2024-02-14 Jakub Jelinek <jakub@redhat.com>
716 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
717 (pp_integer_with_precision): For unsigned ptrdiff_t printing
718 with u, o or x print ptrdiff_t argument converted to
719 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
721 2024-02-14 Richard Biener <rguenther@suse.de>
723 PR middle-end/113576
724 * expr.cc (do_store_flag): For vector bool compares of vectors
725 with padding zero that.
726 * dojump.cc (do_compare_and_jump): Likewise.
728 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
730 * doc/install.texi (Prerequisites): Update gettext link.
732 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
734 PR target/113876
735 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
736 Return false if the incoming stack isn't 16-byte aligned.
738 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
740 PR middle-end/113904
741 * omp-general.cc (struct omp_ts_info): Update for splitting of
742 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
743 * omp-selectors.h (enum omp_tp_type): Replace
744 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
746 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
748 PR target/113742
749 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
750 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
752 2024-02-13 Richard Biener <rguenther@suse.de>
754 PR tree-optimization/113895
755 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
756 offset to discover constant array indices in bits, handle
757 COMPONENT_REF to bitfields.
759 2024-02-13 Richard Biener <rguenther@suse.de>
761 PR tree-optimization/113831
762 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
763 typo in comment.
765 2024-02-13 Richard Biener <rguenther@suse.de>
767 PR tree-optimization/113902
768 * tree-vect-loop.cc (move_early_exit_stmts): Track
769 last_seen_vuse for VUSE updating.
771 2024-02-13 Tamar Christina <tamar.christina@arm.com>
773 PR tree-optimization/113734
774 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
775 an early break loop as partial.
777 2024-02-13 Richard Biener <rguenther@suse.de>
779 PR tree-optimization/113898
780 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
781 missing accumulated off adjustment.
783 2024-02-13 Jakub Jelinek <jakub@redhat.com>
785 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
786 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
787 it against UINT_MAX and ULONG_MAX.
789 2024-02-13 David Malcolm <dmalcolm@redhat.com>
791 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
792 to...
793 (emit_diagnostic_valist_meta): ...this.
794 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
795 (emit_diagnostic_valist_meta): ...this.
797 2024-02-12 Jakub Jelinek <jakub@redhat.com>
799 PR tree-optimization/113849
800 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
801 fast path for widening casts where !m_upwards_2limb and lhs_type
802 has precision which is a multiple of limb_prec.
804 2024-02-12 Jakub Jelinek <jakub@redhat.com>
806 PR c++/113674
807 * attribs.cc (extract_attribute_substring): Remove.
808 (lookup_scoped_attribute_spec): Don't call it.
810 2024-02-12 Jakub Jelinek <jakub@redhat.com>
812 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
813 and cast to fmt_size_t instead of %lu and cast to unsigned long.
815 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
817 * Makefile.in: Add no-info dependency.
818 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
819 available.
820 * configure: Regenerate.
822 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
824 PR target/113855
825 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
826 available to all sub-targets.
827 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
828 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
830 2024-02-12 Richard Biener <rguenther@suse.de>
832 PR tree-optimization/113831
833 PR tree-optimization/108355
834 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
835 we see variable array indices and get_ref_base_and_extent
836 can resolve those to constants fix up the ops to constants
837 as well.
838 (ao_ref_init_from_vn_reference): Use 'off' member for
839 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
840 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
842 2024-02-12 Pan Li <pan2.li@intel.com>
844 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
845 Replace args to arguments for misspelled term.
847 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
849 PR target/112944
850 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
851 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
852 when not linked with -mrodata-in-ram.
854 2024-02-12 Richard Biener <rguenther@suse.de>
856 PR tree-optimization/113863
857 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
858 Record crossed virtual PHIs.
859 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
860 virtual PHIs.
862 2024-02-10 Marek Polacek <polacek@redhat.com>
864 DR 2237
865 PR c++/107126
866 PR c++/97202
867 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
869 2024-02-10 Jakub Jelinek <jakub@redhat.com>
871 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
872 computation of idx for i == 4 of bitint_prec_huge.
874 2024-02-10 Jakub Jelinek <jakub@redhat.com>
876 PR middle-end/110754
877 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
878 decls create PARM_DECL with pointer to original type, set
879 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
880 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
881 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
882 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
883 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
884 of the var as argument.
886 2024-02-10 Jakub Jelinek <jakub@redhat.com>
888 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
889 size_t and precision 4 for ptrdiff_t. Formatting fix.
890 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
891 Formatting fixes.
892 (test_pp_format): Test t and z modifiers.
893 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
895 2024-02-10 Jakub Jelinek <jakub@redhat.com>
897 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
898 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
899 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
900 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
901 and casts to fmt_size_t instead of "%ld" and casts to long.
902 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
903 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
904 instead of "%lu" and casts to unsigned long.
905 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
906 unsigned long.
907 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
908 and casts to fmt_size_t instead of "%ld" and casts to long.
909 * cfgexpand.cc (dump_stack_var_partition): Use
910 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
911 and casts to unsigned long.
912 * gengtype.cc (adjust_field_rtx_def): Likewise.
913 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
914 and casts to fmt_size_t instead of "%ld" and casts to long.
915 * postreload-gcse.cc (dump_hash_table): Likewise.
916 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
917 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
918 (ggc_internal_alloc, ggc_free): Likewise.
919 * genpreds.cc (write_lookup_constraint_1): Likewise.
920 (write_insn_constraint_len): Likewise.
921 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
922 and casts to fmt_size_t instead of "%ld" and casts to long.
923 * varasm.cc (output_constant_pool_contents): Use
924 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
925 * var-tracking.cc (dump_var): Likewise.
927 2024-02-09 Jakub Jelinek <jakub@redhat.com>
929 PR tree-optimization/113783
930 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
931 through VIEW_CONVERT_EXPR for final cast checks. Handle
932 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
933 INTEGER_TYPEs.
934 (gimple_lower_bitint): Don't merge mergeable operations or other
935 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
936 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
937 mode is BLKmode.
939 2024-02-09 Jakub Jelinek <jakub@redhat.com>
941 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
942 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
943 HOST_SIZE_T_PRINT_HEX_PURE): Define.
944 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
945 fixes.
947 2024-02-09 Jakub Jelinek <jakub@redhat.com>
949 PR middle-end/113415
950 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
951 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
952 of hand written loop with emit_insn of copy_insn and emit original
953 after_rtl_seq on the last edge.
955 2024-02-09 Jakub Jelinek <jakub@redhat.com>
957 PR tree-optimization/113818
958 * gimple-lower-bitint.cc (add_eh_edge): New function.
959 (bitint_large_huge::handle_load,
960 bitint_large_huge::lower_mergeable_stmt,
961 bitint_large_huge::lower_muldiv_stmt): Use it.
963 2024-02-09 Jakub Jelinek <jakub@redhat.com>
965 PR tree-optimization/113774
966 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
967 emit any comparison if m_first and low + 1 is equal to
968 m_upwards_2limb, simplify condition for that. If not
969 single_comparison, not m_first and we can prove that the idx <= low
970 comparison will be always true, emit instead of idx <= low
971 comparison low <= low such that cfg cleanup will optimize it at
972 the end of the pass.
974 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
976 PR tree-optimization/113735
977 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
978 limit_check().
980 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
982 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
983 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
985 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
987 PR target/113711
988 PR target/113733
989 * config/i386/constraints.md: List all constraints with j prefix.
990 (j>): Change auto-dec to auto-inc in documentation.
991 (je): Changed to a memory constraint with APX NDD TLS operand
992 check.
993 (jM): New memory constraint for APX NDD instructions.
994 (jO): Likewise.
995 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
996 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
997 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
998 (*add<mode>_1[SWI48]): Use je and jM.
999 (addsi_1_zext): Use jM.
1000 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
1001 (*sub<mode>_1[SWI]): Use jM.
1002 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
1003 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
1004 (*and<dwi>3_doubleword): Likewise.
1005 (*anddi_1): Use jM.
1006 (*andsi_1_zext): Likewise.
1007 (*and<mode>_1[SWI24]): Likewise.
1008 (*<code><dwi>3_doubleword[any_or]): Use rjO
1009 (*code<mode>_1[any_or SWI248]): Use jM.
1010 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
1011 * config/i386/predicates.md (apx_ndd_memory_operand): New.
1012 (apx_ndd_add_memory_operand): Likewise.
1014 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1016 PR target/113824
1017 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
1018 * doc/avr-mmcu.texi: Rebuild.
1020 2024-02-08 Tamar Christina <tamar.christina@arm.com>
1022 PR tree-optimization/113808
1023 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
1024 value cross iterations.
1026 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1028 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
1029 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
1031 2024-02-08 Richard Biener <rguenther@suse.de>
1033 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1034 Revert last change to dr_may_alias_p.
1036 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1038 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
1039 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
1040 Remove spec asm_misc.
1041 * config/avr/specs.h: Same.
1043 2024-02-08 Pan Li <pan2.li@intel.com>
1045 PR target/113766
1046 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
1047 sure the c.arg_num is >= 2 before checking.
1048 (struct build_frm_base): Ditto.
1049 (struct narrow_alu_def): Ditto.
1051 2024-02-07 Richard Biener <rguenther@suse.de>
1053 PR tree-optimization/113796
1054 * tree-if-conv.cc (combine_blocks): Wipe range-info before
1055 replacing PHIs and inserting predicates.
1057 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
1058 Uros Bizjak <ubizjak@gmail.com>
1060 PR target/113690
1061 * config/i386/i386-features.cc (timode_convert_cst): New helper
1062 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
1063 CONST_VECTOR.
1064 (timode_scalar_chain::convert_op): Use timode_convert_cst.
1065 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
1066 Use timode_convert_cst.
1068 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
1070 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
1071 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
1072 (AARCH64_FL_DEBUGv8p9): Likewise.
1073 (AARCH64_FL_FGT2): Likewise.Likewise.
1074 (AARCH64_FL_ITE): Likewise.
1075 (AARCH64_FL_PFAR): Likewise.
1076 (AARCH64_FL_PMUv3_ICNTR): Likewise.
1077 (AARCH64_FL_PMUv3_SS): Likewise.
1078 (AARCH64_FL_PMUv3p9): Likewise.
1079 (AARCH64_FL_RASv2): Likewise.
1080 (AARCH64_FL_S1PIE): Likewise.
1081 (AARCH64_FL_S1POE): Likewise.
1082 (AARCH64_FL_S2PIE): Likewise.
1083 (AARCH64_FL_S2POE): Likewise.
1084 (AARCH64_FL_SCTLR2): Likewise.
1085 (AARCH64_FL_SEBEP): Likewise.
1086 (AARCH64_FL_SPE_FDS): Likewise.
1087 (AARCH64_FL_TCR2): Likewise.
1089 2024-02-07 Richard Biener <rguenther@suse.de>
1091 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1092 Only check whether reads are in-bound in places that are not safe.
1093 Fix dependence check. Add missing newline. Clarify comments.
1095 2024-02-07 Tamar Christina <tamar.christina@arm.com>
1097 PR tree-optimization/113750
1098 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
1099 for single predecessor when doing early break vect.
1100 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
1101 after labels.
1103 2024-02-07 Tamar Christina <tamar.christina@arm.com>
1105 PR tree-optimization/113731
1106 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
1107 method.
1108 * gimple-iterator.h (gsi_move_before): Default new param to
1109 GSI_SAME_STMT.
1110 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
1111 GSI_NEW_STMT.
1113 2024-02-07 Jakub Jelinek <jakub@redhat.com>
1115 PR tree-optimization/113756
1116 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
1117 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
1118 of lh_bits value and mask.
1120 2024-02-07 Jakub Jelinek <jakub@redhat.com>
1122 PR tree-optimization/113753
1123 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
1124 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
1125 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
1126 so that they start with r[half_blocks_needed] lowest bit. Fix up
1127 computation of top mask for SIGNED.
1129 2024-02-07 Pan Li <pan2.li@intel.com>
1131 PR target/113766
1132 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
1133 the signature of func.
1134 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
1135 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
1136 overloaded func with empty args error.
1138 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
1140 PR target/113689
1141 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
1142 R10_REG after sorry.
1144 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
1146 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
1147 Move before new caller, and add ".default" suffix.
1148 (get_suffixed_assembler_name): New.
1149 (make_resolver_func): Use get_suffixed_assembler_name.
1150 (aarch64_generate_version_dispatcher_body): Redo name mangling.
1152 2024-02-06 Jakub Jelinek <jakub@redhat.com>
1154 PR target/113763
1155 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
1156 element from std::pair<unsigned int, char> to an unnamed struct.
1157 Adjust uses of tile range variable.
1159 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1161 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
1162 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
1164 2024-02-06 Jakub Jelinek <jakub@redhat.com>
1166 PR sanitizer/110676
1167 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
1168 reset maxlen to sizetype maximum.
1170 2024-02-06 Jakub Jelinek <jakub@redhat.com>
1172 PR tree-optimization/113736
1173 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
1174 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
1176 2024-02-06 Jakub Jelinek <jakub@redhat.com>
1178 PR tree-optimization/113759
1179 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
1180 or from_unsignedN differs from properties of typeN, update typeN
1181 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
1182 uselessly convertible to typeN, convert it using fold_convert or
1183 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
1184 (convert_plusminus_to_widen): Likewise.
1186 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
1188 PR target/112577
1189 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
1190 vector structure modes correctly.
1192 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
1194 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
1195 warning.
1197 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
1199 PR target/113689
1200 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
1201 (x86_function_profiler): Call x86_64_select_profile_regnum to
1202 get a scratch register for large model profiling.
1204 2024-02-05 Richard Ball <richard.ball@arm.com>
1206 * config/arm/arm.cc (arm_output_mi_thunk): Emit
1207 insn for bti_c when bti is enabled.
1209 2024-02-05 Xi Ruoyao <xry111@xry111.site>
1211 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
1212 neg.
1214 2024-02-05 Xi Ruoyao <xry111@xry111.site>
1216 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
1217 (neg<mode>2): Change the mode iterator from MSA to IMSA because
1218 in FP arithmetic we cannot use (0 - x) for -x.
1219 (neg<mode>2): New define_insn to implement FP vector negation,
1220 using a bnegi instruction to negate the sign bit.
1222 2024-02-05 Richard Biener <rguenther@suse.de>
1224 PR tree-optimization/113707
1225 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
1226 checking the avail set treat out-of-region defines as
1227 available.
1229 2024-02-05 Richard Biener <rguenther@suse.de>
1231 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
1232 the default mode when building a pointer.
1234 2024-02-05 Jakub Jelinek <jakub@redhat.com>
1236 PR tree-optimization/113737
1237 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
1238 has just a single label, remove it and make single successor edge
1239 EDGE_FALLTHRU.
1241 2024-02-05 Jakub Jelinek <jakub@redhat.com>
1243 PR target/113059
1244 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
1245 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
1246 df_analyze call.
1248 2024-02-05 Richard Biener <rguenther@suse.de>
1250 PR target/113255
1251 * config/i386/i386-expand.cc
1252 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
1253 Use a new pseudo for the skipped number of bytes.
1255 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
1257 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
1258 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
1259 sifive-p670.
1261 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
1263 * config/riscv/riscv.md: Include sifive-p400.md.
1264 * config/riscv/sifive-p400.md: New file.
1265 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
1266 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
1267 Add sifive_p400.
1268 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
1269 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
1270 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
1272 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
1274 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
1275 Add missing ":SI" to the match_operator.
1277 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
1279 * config/xtensa/xtensa.md (SHI): New mode iterator.
1280 (2 split patterns related to constsynth):
1281 Change to also accept HImode operands.
1283 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
1285 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
1286 similarly.
1288 2024-02-04 Xi Ruoyao <xry111@xry111.site>
1290 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
1291 incorrect expand.
1292 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
1293 (elmsgnbit): Likewise.
1294 (neg<mode:FVEC>2): New define_insn.
1295 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
1296 are now instantiated in simd.md.
1298 2024-02-04 Xi Ruoyao <xry111@xry111.site>
1300 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
1301 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
1302 MAX_MACHINE_MODE.
1304 2024-02-04 Li Wei <liwei@loongson.cn>
1306 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
1307 (loongarch_expand_vselect_vconcat): Ditto.
1308 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
1309 all 128-bit constant permutation situations.
1310 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
1311 (loongarch_is_imm_set_shuffle): Renamed function name.
1312 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
1313 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
1314 extract-even and extract-odd permutations.
1315 (loongarch_is_odd_extraction): Delete.
1316 (loongarch_is_even_extraction): Ditto.
1317 (loongarch_expand_vec_perm_const): Adjust.
1319 2024-02-03 Jakub Jelinek <jakub@redhat.com>
1321 PR middle-end/113722
1322 * wide-int.cc (wi::bswap_large): Rename third argument from
1323 len to xlen and adjust use in safe_uhwi. Add len variable, set
1324 it to BLOCKS_NEEDED (precision) and use it for clearing of val
1325 and as canonize argument. Clear val using memset instead of
1326 a loop.
1328 2024-02-03 Jakub Jelinek <jakub@redhat.com>
1330 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
1331 mmi.preferred_base + mmi.size - sizeof (void *).
1333 2024-02-03 Xi Ruoyao <xry111@xry111.site>
1335 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
1336 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
1337 the ODR-violating locale declaration.
1339 2024-02-02 Tamar Christina <tamar.christina@arm.com>
1341 PR tree-optimization/113588
1342 PR tree-optimization/113467
1343 * tree-vect-data-refs.cc
1344 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
1345 (vect_analyze_early_break_dependences): Update comments.
1347 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
1349 PR target/59778
1350 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
1351 and PA_BUILTIN_SET_FPSR builtins.
1352 * (pa_builtins_icode): Declare.
1353 * (def_builtin, pa_fpu_init_builtins): New.
1354 * (pa_init_builtins): Initialize FPU builtins.
1355 * (pa_builtin_decl, pa_expand_builtin_1): New.
1356 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
1357 PA_BUILTIN_SET_FPSR builtins.
1358 * (pa_atomic_assign_expand_fenv): New.
1359 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
1360 UNSPECV constants.
1361 (get_fpsr, put_fpsr): New expanders.
1362 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
1363 insn patterns.
1365 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1367 PR target/113697
1368 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
1370 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
1372 * doc/extend.texi (Common Type Attributes): Fix typo in
1373 description of hardbool.
1375 2024-02-02 Jakub Jelinek <jakub@redhat.com>
1377 PR tree-optimization/113692
1378 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
1379 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
1380 final_cast_p.
1382 2024-02-02 Jakub Jelinek <jakub@redhat.com>
1384 PR middle-end/113699
1385 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
1386 uninitialized large/huge _BitInt SSA_NAME inputs.
1388 2024-02-02 Jakub Jelinek <jakub@redhat.com>
1390 PR middle-end/113705
1391 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
1392 around wi::to_wide in order to compare value in prec precision.
1394 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
1396 Revert:
1397 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1399 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
1401 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1403 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
1405 2024-02-02 Pan Li <pan2.li@intel.com>
1407 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
1408 (riscv_pass_by_reference): Ditto.
1409 (riscv_fntype_abi): Ditto.
1411 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1413 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
1414 (pre_vsetvl::cleaup): Remove vsetvl_pre.
1415 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
1417 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
1419 * config/loongarch/larchintrin.h
1420 (__frecipe_s): Update function return type.
1421 (__frecipe_d): Ditto.
1422 (__frsqrte_s): Ditto.
1423 (__frsqrte_d): Ditto.
1425 2024-02-02 Li Wei <liwei@loongson.cn>
1427 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
1428 (loongarch_vector_costs::add_stmt_cost): Adjust.
1430 2024-02-02 Xi Ruoyao <xry111@xry111.site>
1432 * config/loongarch/loongarch.md (unspec): Add
1433 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
1434 (la_pcrel64_two_parts): New define_insn.
1435 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
1436 typo in the comment.
1437 (loongarch_call_tls_get_addr): If -mcmodel=extreme
1438 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
1439 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
1440 note to allow CSE addressing __tls_get_addr.
1441 (loongarch_legitimize_tls_address): If -mcmodel=extreme
1442 -mexplicit-relocs={always,auto}, address TLS IE symbols with
1443 la_pcrel64_two_parts.
1444 (loongarch_split_symbol): If -mcmodel=extreme
1445 -mexplicit-relocs={always,auto}, address symbols with
1446 la_pcrel64_two_parts.
1447 (loongarch_output_mi_thunk): Clean up unreachable code. If
1448 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
1449 thunks with la_pcrel64_two_parts.
1451 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1453 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
1454 Add support for call36.
1456 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1458 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
1459 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
1460 the macro instruction loading symbol address is not applicable.
1461 (loongarch_call_tls_get_addr): Adjust code.
1462 (loongarch_legitimize_tls_address): Likewise.
1464 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1466 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
1467 Add function declaration.
1468 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
1469 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
1470 is not allowed
1471 (loongarch_load_tls): Added macro support in extreme mode.
1472 (loongarch_call_tls_get_addr): Likewise.
1473 (loongarch_legitimize_tls_address): Likewise.
1474 (loongarch_force_address): Likewise.
1475 (loongarch_legitimize_move): Likewise.
1476 (loongarch_output_mi_thunk): Likewise.
1477 (loongarch_option_override_internal): Remove the code that detects
1478 explicit relocs status.
1479 (loongarch_handle_model_attribute): Likewise.
1480 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
1481 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
1482 (symbolic_off64_or_reg_operand): Likewise.
1484 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1486 * config/loongarch/loongarch.cc (loongarch_load_tls):
1487 Load all types of tls symbols through one function.
1488 (loongarch_got_load_tls_gd): Delete.
1489 (loongarch_got_load_tls_ld): Delete.
1490 (loongarch_got_load_tls_ie): Delete.
1491 (loongarch_got_load_tls_le): Delete.
1492 (loongarch_call_tls_get_addr): Modify the called function name.
1493 (loongarch_legitimize_tls_address): Likewise.
1494 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
1495 (@load_tls<mode>): New template.
1496 (@got_load_tls_ld<mode>): Delete.
1497 (@got_load_tls_le<mode>): Delete.
1498 (@got_load_tls_ie<mode>): Delete.
1500 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1502 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
1503 (loongarch_legitimize_address): Add logical transformation code.
1505 2024-02-01 Marek Polacek <polacek@redhat.com>
1507 * doc/invoke.texi: Update -Wdangling-reference documentation.
1509 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
1511 PR target/113701
1512 * config/i386/i386.md (*cmp<dwi>_doubleword):
1513 Do not force SUBREG pieces to pseudos.
1515 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
1517 * config/pa/pa.md (atomic_storedi_1): Fix bug in
1518 alternative 1.
1520 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
1522 * config/avr/avr.cc: Tabify.
1524 2024-02-01 Richard Ball <richard.ball@arm.com>
1526 PR tree-optimization/111268
1527 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
1528 Add variable-length check for vector input arguments
1529 to a function.
1531 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
1533 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
1534 hard-code number of SGPR/VGPR/AVGPR registers.
1535 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
1536 SGPR/VGPR/AVGPR registers.
1538 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
1540 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
1541 attribute, and include sifive-p600.md.
1542 * config/riscv/generic-ooo.md: Update type attribute.
1543 * config/riscv/generic.md: Update type attribute.
1544 * config/riscv/sifive-7.md: Update type attribute.
1545 * config/riscv/sifive-p600.md: New file.
1546 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
1547 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
1548 Add sifive_p600.
1549 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
1550 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
1551 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
1553 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
1555 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
1556 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
1557 * config/riscv/riscv.opt: New macro for 7 new unprivileged
1558 extensions.
1559 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
1560 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
1562 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1564 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
1565 -static-libasan. Add missing whitespace.
1567 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
1569 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
1570 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
1571 Don't 'define_constants'.
1573 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
1575 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
1577 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
1579 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
1580 [TARGET_RDNA3]: Adjust.
1582 2024-02-01 Richard Biener <rguenther@suse.de>
1584 PR tree-optimization/113693
1585 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
1586 data when available.
1588 2024-02-01 Jakub Jelinek <jakub@redhat.com>
1589 Jason Merrill <jason@redhat.com>
1591 PR c++/113531
1592 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
1593 on variables which were promoted to TREE_STATIC.
1595 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
1596 Richard Biener <rguenther@suse.de>
1598 PR target/113560
1599 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
1600 information via tree_non_zero_bits to check if this operand
1601 is suitably extended for a widening (or highpart) multiplication.
1602 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
1603 isn't already of the claimed type.
1605 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1607 Revert:
1608 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1610 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1611 (generic_ooo_branch): ditto
1612 * config/riscv/generic.md (generic_sfb_alu): ditto
1613 (generic_fmul_half): ditto
1614 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1615 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
1616 (sifive_7_popcount): ditto
1617 * config/riscv/vector.md: change rdfrm to fmove
1618 * config/riscv/zc.md: change pushpop to load/store
1620 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1622 Revert:
1623 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1624 Robin Dapp <rdapp.gcc@gmail.com>
1626 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1627 (generic_ooo_vec_load): ditto
1628 (generic_ooo_vec_store): ditto
1629 (generic_ooo_vec_loadstore_seg): ditto
1630 (generic_ooo_vec_alu): ditto
1631 (generic_ooo_vec_fcmp): ditto
1632 (generic_ooo_vec_imul): ditto
1633 (generic_ooo_vec_fadd): ditto
1634 (generic_ooo_vec_fmul): ditto
1635 (generic_ooo_crypto): ditto
1636 (generic_ooo_perm): ditto
1637 (generic_ooo_vec_reduction): ditto
1638 (generic_ooo_vec_ordered_reduction): ditto
1639 (generic_ooo_vec_idiv): ditto
1640 (generic_ooo_vec_float_divsqrt): ditto
1641 (generic_ooo_vec_mask): ditto
1642 (generic_ooo_vec_vesetvl): ditto
1643 (generic_ooo_vec_setrm): ditto
1644 (generic_ooo_vec_readlen): ditto
1645 * config/riscv/riscv.md: include generic-vector-ooo
1646 * config/riscv/generic-vector-ooo.md: New file. to here
1648 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1650 Revert:
1651 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1653 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
1655 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1657 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
1659 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1660 Robin Dapp <rdapp.gcc@gmail.com>
1662 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1663 (generic_ooo_vec_load): ditto
1664 (generic_ooo_vec_store): ditto
1665 (generic_ooo_vec_loadstore_seg): ditto
1666 (generic_ooo_vec_alu): ditto
1667 (generic_ooo_vec_fcmp): ditto
1668 (generic_ooo_vec_imul): ditto
1669 (generic_ooo_vec_fadd): ditto
1670 (generic_ooo_vec_fmul): ditto
1671 (generic_ooo_crypto): ditto
1672 (generic_ooo_perm): ditto
1673 (generic_ooo_vec_reduction): ditto
1674 (generic_ooo_vec_ordered_reduction): ditto
1675 (generic_ooo_vec_idiv): ditto
1676 (generic_ooo_vec_float_divsqrt): ditto
1677 (generic_ooo_vec_mask): ditto
1678 (generic_ooo_vec_vesetvl): ditto
1679 (generic_ooo_vec_setrm): ditto
1680 (generic_ooo_vec_readlen): ditto
1681 * config/riscv/riscv.md: include generic-vector-ooo
1682 * config/riscv/generic-vector-ooo.md: New file. to here
1684 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1686 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1687 (generic_ooo_branch): ditto
1688 * config/riscv/generic.md (generic_sfb_alu): ditto
1689 (generic_fmul_half): ditto
1690 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1691 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
1692 (sifive_7_popcount): ditto
1693 * config/riscv/vector.md: change rdfrm to fmove
1694 * config/riscv/zc.md: change pushpop to load/store
1696 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
1698 PR target/113657
1699 * config/aarch64/aarch64-simd.md (split for movv8di):
1700 For strict aligned mode, use DImode instead of TImode.
1702 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
1704 PR middle-end/113607
1705 * match.pd: Make sure else values match when folding a
1706 vec_cond into a conditional operation.
1708 2024-01-31 Marek Polacek <polacek@redhat.com>
1710 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
1712 2024-01-31 Tamar Christina <tamar.christina@arm.com>
1713 Matthew Malcomson <matthew.malcomson@arm.com>
1715 PR sanitizer/112644
1716 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
1717 memcmp.
1718 * builtins.cc (expand_builtin): Include HWASAN when checking for
1719 builtin inlining.
1721 2024-01-31 Richard Biener <rguenther@suse.de>
1723 PR middle-end/110176
1724 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
1725 to match INTEGER_CST only without outstanding conversion.
1727 2024-01-31 Alex Coplan <alex.coplan@arm.com>
1729 PR target/111677
1730 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
1731 V16QImode for the full 16-byte FPR saves in the vector PCS case.
1733 2024-01-31 Richard Biener <rguenther@suse.de>
1735 PR tree-optimization/111444
1736 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
1737 vn_reference_lookup_2 when optimistically skipping may-defs.
1739 2024-01-31 Richard Biener <rguenther@suse.de>
1741 PR tree-optimization/113630
1742 * tree-ssa-pre.cc (compute_avail): Avoid registering a
1743 reference with a representation with not matching base
1744 access size.
1746 2024-01-31 Jakub Jelinek <jakub@redhat.com>
1748 PR rtl-optimization/113656
1749 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
1750 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
1752 2024-01-31 Jakub Jelinek <jakub@redhat.com>
1754 PR debug/113637
1755 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
1756 with BLKmode are larger than DWARF2_ADDR_SIZE.
1758 2024-01-31 Jakub Jelinek <jakub@redhat.com>
1760 PR tree-optimization/113639
1761 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
1762 For VIEW_CONVERT_EXPR set rhs1 to its operand.
1764 2024-01-31 Richard Biener <rguenther@suse.de>
1766 PR tree-optimization/113670
1767 * tree-vect-data-refs.cc (vect_check_gather_scatter):
1768 Make sure we can take the address of the reference base.
1770 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
1772 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
1773 ATA5835, ATtiny64AUTO, ATA5700M322.
1774 * doc/avr-mmcu.texi: Rebuild.
1776 2024-01-31 Alexandre Oliva <oliva@adacore.com>
1778 PR debug/113394
1779 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
1780 caller.
1782 2024-01-31 Alexandre Oliva <oliva@adacore.com>
1784 PR middle-end/112917
1785 PR middle-end/113100
1786 * builtins.cc (expand_builtin_stack_address): Use
1787 STACK_ADDRESS_OFFSET.
1788 * doc/extend.texi (__builtin_stack_address): Adjust.
1789 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
1790 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
1791 * doc/tm.texi: Rebuilt.
1793 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1795 PR target/113495
1796 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
1797 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
1798 (pre_vsetvl::compute_transparent): New function.
1799 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
1801 2024-01-30 Fangrui Song <maskray@google.com>
1803 PR target/105576
1804 * config/i386/constraints.md: Define constraint "Ws".
1805 * doc/md.texi: Document it.
1807 2024-01-30 Marek Polacek <polacek@redhat.com>
1809 PR c++/110358
1810 PR c++/109640
1811 * doc/invoke.texi: Update -Wdangling-reference description.
1813 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
1815 * config/xtensa/constraints.md (R, T, U):
1816 Change define_constraint to define_memory_constraint.
1817 * config/xtensa/predicates.md (move_operand): Don't check that a
1818 constant pool operand size is a multiple of UNITS_PER_WORD.
1819 * config/xtensa/xtensa.cc
1820 (xtensa_lra_p, TARGET_LRA_P): Remove.
1821 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
1822 clause as it can no longer be true.
1823 (fixup_subreg_mem): Drop function.
1824 (xtensa_output_integer_literal_parts): Consider 16-bit wide
1825 constants.
1826 (xtensa_legitimate_constant_p): Add short-circuit path for
1827 integer load instructions. Don't check that mode size is
1828 at least UNITS_PER_WORD.
1829 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
1830 rather reload_in_progress and reload_completed.
1831 (doloop_end): Drop operand 2.
1832 (movhi_internal): Add alternative loading constant from a
1833 literal pool.
1834 (define_split for DI register_operand): Don't limit to
1835 !TARGET_AUTO_LITPOOLS.
1836 * config/xtensa/xtensa.opt (mlra): Change to no effect.
1838 2024-01-30 Pan Li <pan2.li@intel.com>
1840 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
1841 calculate the gpr count required by vls mode.
1842 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
1843 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
1844 for vls mode.
1845 (riscv_get_arg_info): Add vls mode handling.
1846 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
1848 2024-01-30 Richard Biener <rguenther@suse.de>
1850 PR tree-optimization/113659
1851 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1852 Handle main exit without virtual use.
1854 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
1856 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
1858 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
1860 PR libgcc/113403
1861 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
1862 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
1863 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
1864 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
1865 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
1866 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
1868 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
1870 PR target/113623
1871 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
1872 Mark all registers that occur in addresses as needing a GPR.
1874 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
1876 PR target/113636
1877 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
1878 the containing insn as an extra parameter. Reset debug instructions
1879 if they reference a register that is no longer used by real insns.
1880 (early_ra::apply_allocation): Update calls accordingly.
1882 2024-01-30 Jakub Jelinek <jakub@redhat.com>
1884 PR tree-optimization/113603
1885 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
1886 count_nonzero_bytes call refetch si using get_strinfo in case it
1887 has been unshared in the meantime.
1889 2024-01-30 Jakub Jelinek <jakub@redhat.com>
1891 PR middle-end/101195
1892 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
1893 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
1895 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
1897 * config/riscv/thead.cc (th_print_operand_address): Change %ld
1898 to %lld.
1900 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
1901 Manolis Tsamis <manolis.tsamis@vrull.eu>
1902 Philipp Tomsich <philipp.tomsich@vrull.eu>
1904 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
1905 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
1906 Likewise.
1907 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
1908 Call on framework moved later.
1910 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
1912 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
1913 instruction in naked function epilogues.
1915 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
1917 PR target/113655
1918 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
1919 gcc_cv_as_mips_explicit_relocs.
1920 * configure: Regnerated.
1922 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
1924 PR target/108933
1925 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
1926 Correct generated RTL.
1927 (arm_rev16si2_alt1): Correctly handle conditional execution.
1928 (arm_rev16si2_alt2): Likewise.
1930 2024-01-29 Richard Biener <rguenther@suse.de>
1932 PR middle-end/113622
1933 * expr.cc (expand_assignment): Spill hard registers if
1934 we index them with a variable offset.
1936 2024-01-29 Richard Biener <rguenther@suse.de>
1938 PR middle-end/113622
1939 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
1940 Also allow DECL_HARD_REGISTER variables.
1942 2024-01-29 Alex Coplan <alex.coplan@arm.com>
1944 PR target/113616
1945 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
1946 Use iterate_safely when iterating over debug uses.
1947 (fixup_debug_uses): Likewise.
1948 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
1949 over nondebug insns instead of manually maintaining the next insn.
1950 * iterator-utils.h (class safe_iterator): New.
1951 (iterate_safely): New.
1953 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
1955 PR target/38534
1956 * config/i386/i386-options.cc (ix86_set_func_type): Save
1957 callee-saved registers in noreturn functions for -O0/-Og.
1959 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
1961 PR target/113615
1962 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
1963 define for !TARGET_RDNA2_PLUS.
1965 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
1967 PR target/113281
1968 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
1969 workaround for right shifts.
1970 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
1971 (vect_determine_precisions_from_range): Be more selective about
1972 which codes can be narrowed based on their input and output ranges.
1973 For shifts, require at least one more bit of precision than the
1974 maximum shift amount.
1976 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
1978 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
1980 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
1982 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
1983 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
1984 LLVM 13.0.1+.
1986 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
1988 PR other/111966
1989 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
1990 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
1991 (SET_SRAM_ECC_UNSET): ... this.
1992 (copy_early_debug_info): Remove gfx900 special case, now handled as
1993 part of the generic handling.
1994 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
1996 2024-01-29 Jakub Jelinek <jakub@redhat.com>
1998 PR tree-optimization/110603
1999 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
2000 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
2001 overwritten anyway). Avoid creating invalid range with minlen
2002 larger than maxlen. Formatting fix.
2004 2024-01-29 Richard Biener <rguenther@suse.de>
2006 PR debug/103047
2007 * tree-inline.cc (initialize_inlined_parameters): Reverse
2008 the decl chain of inlined parameters.
2010 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
2012 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
2013 alignment of CFString constants by setting DECL_USER_ALIGN.
2015 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
2016 Jakub Jelinek <jakub@redhat.com>
2018 PR libgcc/113402
2019 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
2020 and BUILT_IN_GCC_NESTED_PTR_DELETED.
2021 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
2022 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
2023 rename the library fallbacks to __gcc_nested_func_ptr_created and
2024 __gcc_nested_func_ptr_deleted.
2025 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
2026 and __gcc_nested_func_ptr_deleted.
2027 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
2028 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
2029 * tree.cc (build_common_builtin_nodes): Build the
2030 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
2031 builtins only for non-explicit.
2033 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
2035 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
2037 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
2039 PR target/38534
2040 * config/i386/i386-options.cc (ix86_set_func_type): Don't
2041 save and restore callee saved registers for a noreturn function
2042 with nothrow or compiled with -fno-exceptions.
2044 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
2046 PR target/103503
2047 PR target/113312
2048 * config/i386/i386-expand.cc (ix86_expand_call): Replace
2049 no_caller_saved_registers check with call_saved_registers check.
2050 Clobber all registers that are not used by the callee with
2051 no_callee_saved_registers attribute.
2052 * config/i386/i386-options.cc (ix86_set_func_type): Set
2053 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
2054 noreturn function. Disallow no_callee_saved_registers with
2055 interrupt or no_caller_saved_registers attributes together.
2056 (ix86_set_current_function): Replace no_caller_saved_registers
2057 check with call_saved_registers check.
2058 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
2059 (ix86_handle_call_saved_registers_attribute): This.
2060 (ix86_gnu_attributes): Add
2061 ix86_handle_call_saved_registers_attribute.
2062 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
2063 no_caller_saved_registers check with call_saved_registers check.
2064 (ix86_function_ok_for_sibcall): Don't allow callee with
2065 no_callee_saved_registers attribute when the calling function
2066 has callee-saved registers.
2067 (ix86_comp_type_attributes): Also check
2068 no_callee_saved_registers.
2069 (ix86_epilogue_uses): Replace no_caller_saved_registers check
2070 with call_saved_registers check.
2071 (ix86_hard_regno_scratch_ok): Likewise.
2072 (ix86_save_reg): Replace no_caller_saved_registers check with
2073 call_saved_registers check. Don't save any registers for
2074 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
2075 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
2076 no_callee_saved_registers attribute is called.
2077 (find_drap_reg): Replace no_caller_saved_registers check with
2078 call_saved_registers check.
2079 * config/i386/i386.h (call_saved_registers_type): New enum.
2080 (machine_function): Replace no_caller_saved_registers with
2081 call_saved_registers.
2082 * doc/extend.texi: Document no_callee_saved_registers attribute.
2084 2024-01-27 Jakub Jelinek <jakub@redhat.com>
2086 PR tree-optimization/113614
2087 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
2088 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
2089 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
2091 2024-01-27 Jakub Jelinek <jakub@redhat.com>
2093 PR tree-optimization/113568
2094 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
2095 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
2096 in the widening extension checks.
2098 2024-01-27 Jakub Jelinek <jakub@redhat.com>
2100 * gimple-lower-bitint.cc (gimple_lower_bitint): For
2101 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
2103 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
2105 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
2106 the warning for an attribute-always_inline without inline declaration.
2108 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
2110 PR other/113575
2111 * genopinit.cc (main): Split init_all_optabs into functions
2112 of 1000 patterns each.
2114 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
2116 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
2117 TM_MULTILIB_CONFIG.
2118 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
2119 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
2120 -march/-mtune.
2122 2024-01-26 Andrew Stubbs <ams@baylibre.com>
2124 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
2125 * config/gcn/gcn-valu.md (all_convert): New iterator.
2126 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
2127 define_expand, and rename the old one to ...
2128 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
2129 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
2130 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
2131 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
2132 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
2133 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
2134 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
2135 (<u>mulqihi3_scalar): Likewise.
2137 2024-01-26 Richard Biener <rguenther@suse.de>
2139 PR tree-optimization/113602
2140 * tree-data-ref.cc (dr_analyze_innermost): Fail when
2141 the base object isn't addressable.
2143 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
2145 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
2146 "--amdhsa-code-object-version=" argument.
2147 (ASM_SPEC): Use it; replace previous version of it.
2149 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2151 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
2152 (pre_vsetvl::emit_vsetvl): Ditto.
2154 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
2156 * config/loongarch/lasx.md (vec_extract<mode>_0):
2157 New define_insn_and_split patten.
2159 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
2161 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
2163 2024-01-26 Li Wei <liwei@loongson.cn>
2165 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
2167 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2169 PR target/113469
2170 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
2172 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
2174 PR target/100212
2175 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
2176 undefined shift after the call to exact_log2.
2178 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
2180 PR target/100204
2181 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
2182 before taking the negative of it.
2184 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
2186 PR target/113526
2187 * lra-constraints.cc (curr_insn_transform): Change class even for
2188 spilled pseudo successfully matched with with NO_REGS.
2190 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
2192 PR target/113601
2193 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
2195 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
2197 PR target/112987
2198 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
2199 (aarch64_expand_epilogue): Use the new function.
2200 (aarch64_split_compare_and_swap): Likewise.
2201 (aarch64_split_atomic_op): Likewise.
2203 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
2205 PR middle-end/112971
2206 * fold-const.cc (simplify_const_binop): New function for binop
2207 simplification of two constant vectors when element-wise
2208 handling is not necessary.
2209 (const_binop): Call new function.
2211 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
2213 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
2214 * config/riscv/constraints.md: Likewise.
2215 * config/riscv/corev.def: Likewise.
2216 * config/riscv/corev.md: Likewise.
2217 * config/riscv/predicates.md: Likewise.
2218 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
2219 * config/riscv/riscv-ftypes.def: Likewise.
2220 * config/riscv/riscv.opt: Likewise.
2221 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
2222 * doc/extend.texi: Add XCVbitmanip builtin documentation.
2223 * doc/sourcebuild.texi: Likewise.
2225 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
2227 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
2229 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
2231 PR target/113538
2232 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
2233 (riscv_fntype_abi): Ditto.
2234 * config/riscv/riscv.opt: Ditto.
2236 2024-01-25 Jakub Jelinek <jakub@redhat.com>
2238 PR middle-end/113574
2239 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
2240 count against TYPE_PRECISION rather than TYPE_SIZE.
2242 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
2244 PR target/113572
2245 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
2246 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
2248 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
2250 PR target/113550
2251 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
2252 whether each split instruction is a load that clobbers the source
2253 address. Emit that instruction last if so.
2255 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
2257 PR target/113485
2258 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
2259 pattern.
2260 (<optab><Vnarrowq><mode>2): Use it instead of generating a
2261 paradoxical subreg for the input.
2263 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2265 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
2266 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
2267 predecessors dump information.
2269 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2271 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
2272 redundant full available computation.
2273 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
2275 2024-01-25 Jakub Jelinek <jakub@redhat.com>
2277 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
2278 * doc/rtl.texi (CONST_VECTOR): Likewise.
2280 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2282 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
2283 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
2284 (pass_vsetvl::execute): Ditto.
2285 * config/riscv/riscv.opt: Ditto.
2287 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
2289 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
2290 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
2292 2024-01-25 Richard Biener <rguenther@suse.de>
2294 PR tree-optimization/113576
2295 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
2296 exits with may_be_zero niters when its the last one.
2298 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
2300 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
2301 For symbols of type tls, non-zero Offset is not generated.
2303 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
2305 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
2306 P9 with m32 and mpowerpc64.
2308 2024-01-25 liuhongt <hongtao.liu@intel.com>
2310 * config/i386/i386-options.cc (ix86_option_override_internal):
2311 Enable -mlam=u57 by default when compiled with
2312 -fsanitize=hwaddress.
2314 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
2316 * common/config/riscv/riscv-common.cc (riscv_implied_info):
2317 Remove {"ztso", "a"}.
2319 2024-01-24 Martin Jambor <mjambor@suse.cz>
2321 PR ipa/108007
2322 PR ipa/112616
2323 * cgraph.h (cgraph_edge): Add a parameter to
2324 redirect_call_stmt_to_callee.
2325 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
2326 parameter to modify_call.
2327 (ipa_release_ssas_in_hash): Declare.
2328 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
2329 parameter killed_ssas, pass it to padjs->modify_call.
2330 * ipa-param-manipulation.cc (purge_all_uses): New function.
2331 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
2332 Instead of substituting uses, invoke purge_all_uses. If
2333 hash of killed SSAs has not been provided, create a temporary one
2334 and release SSAs that have been added to it.
2335 (compare_ssa_versions): New function.
2336 (ipa_release_ssas_in_hash): Likewise.
2337 * tree-inline.cc (redirect_all_calls): Create
2338 id->killed_new_ssa_names earlier, pass it to edge redirection,
2339 adjust a comment.
2340 (copy_body): Release SSAs in id->killed_new_ssa_names.
2342 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
2344 PR target/113486
2345 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
2346 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
2348 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
2350 PR target/113095
2351 * config/riscv/sfb.md: New splitters to rewrite single bit
2352 sign extension as the condition to SFB instructions.
2354 2024-01-24 Jan Hubicka <jh@suse.cz>
2356 PR middle-end/88345
2357 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
2358 (fmin-function-alignment): New parameter.
2359 * doc/invoke.texi: (-fmin-function-alignment): Document.
2360 (-falign-functions,-falign-loops,-falign-labels): Mention that
2361 aglinments are ignored in cold code.
2362 * varasm.cc (assemble_start_function): Handle min-function-alignment.
2364 2024-01-24 Tamar Christina <tamar.christina@arm.com>
2366 PR target/109636
2367 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
2368 mulv2di3): Remove.
2369 * config/aarch64/iterators.md (VQDIV): Remove.
2370 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
2371 SVE_I_SIMD_DI): New.
2372 (VPRED, sve_lane_con): Add V4SI and V2DI.
2373 * config/aarch64/aarch64-sve.md (<optab><mode>3,
2374 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
2375 (mul<mode>3): New, split from <optab><mode>3.
2376 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
2377 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
2378 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
2379 SVE_FULL_HSDI_SIMD_DI.
2381 2024-01-24 Tamar Christina <tamar.christina@arm.com>
2383 PR tree-optimization/113552
2384 * config/aarch64/aarch64.cc
2385 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
2387 2024-01-24 Martin Jambor <mjambor@suse.cz>
2389 PR ipa/113490
2390 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
2391 count is equal or greater than the limit. Use the limit from the
2392 callee.
2394 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
2396 * configure.ac: Detect the explicit relocs support for
2397 mips, and define C macro MIPS_EXPLICIT_RELOCS.
2398 * config.in: Regenerated.
2399 * configure: Regenerated.
2400 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
2401 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
2402 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
2403 !TARGET_EXPLICIT_RELOCS instead of just set it.
2404 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
2405 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
2406 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
2407 and define -m(no-)explicit-relocs as aliases.
2409 2024-01-24 Alex Coplan <alex.coplan@arm.com>
2411 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
2412 to 1.
2413 (-mlate-ldp-fusion): Likewise.
2415 2024-01-24 Tamar Christina <tamar.christina@arm.com>
2417 * tree-vect-loop.cc (vect_get_vect_def,
2418 vect_create_epilog_for_reduction): Rename main_exit_p to
2419 last_val_reduc_p.
2421 2024-01-24 Tamar Christina <tamar.christina@arm.com>
2423 PR tree-optimization/113364
2424 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
2425 early exits then we must reduce from the first offset for all of them.
2427 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2429 PR target/113495
2430 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
2431 (get_regno): Ditto.
2432 (get_bb_index): Ditto.
2433 (pre_vsetvl::compute_avl_def_data): Ditto.
2434 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
2435 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
2437 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
2438 Richard Sandiford <richard.sandiford@arm.com>
2440 PR target/100942
2441 * ccmp.cc (ccmp_candidate_p): Add outer argument.
2442 Allow if the outer is true and the lhs is used more
2443 than once.
2444 (expand_ccmp_expr): Update call to ccmp_candidate_p.
2445 * expr.h (expand_expr_real_gassign): Declare.
2446 * expr.cc (expand_expr_real_gassign): New function, split out from...
2447 (expand_expr_real_1): ...here.
2448 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
2450 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2452 PR target/113089
2453 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
2454 (fixup_debug_use): New.
2455 (fixup_debug_uses_trailing_add): New.
2456 (fixup_debug_uses): New. Use it ...
2457 (ldp_bb_info::fuse_pair): ... here.
2458 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
2459 fix up debug uses of the base register that are affected by
2460 folding in the trailing add insn.
2462 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2464 PR target/113089
2465 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
2466 Update trailing nondebug uses of the base register in the case
2467 of cancelling writeback.
2469 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2471 PR target/113089
2472 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
2473 (debug_insn_use_iterator): New.
2474 (set_info::first_debug_insn_use): New.
2475 (set_info::debug_insn_uses): New.
2476 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
2477 (set_info::first_debug_insn_use): New.
2478 (set_info::debug_insn_uses): New.
2480 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2482 PR target/113356
2483 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
2484 Don't record hazards against the opposite insn in the pair.
2486 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2488 PR target/113070
2489 * config/aarch64/aarch64-ldp-fusion.cc
2490 (struct stp_change_builder): New.
2491 (decide_stp_strategy): Reanme to ...
2492 (try_repurpose_store): ... this.
2493 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
2494 construct stp changes. Fix up uses when inserting new stp insns.
2496 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2498 PR target/113070
2499 * rtl-ssa.h: Include hash-set.h.
2500 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
2501 new_sets parameter and use it to keep track of new user-created sets.
2502 (function_info::apply_changes_to_insn): Also call add_def on new sets.
2503 (function_info::change_insns): Add hash_set to keep track of new
2504 user-created defs. Plumb it through.
2505 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
2506 apply_changes_to_insn.
2508 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2510 PR target/113070
2511 * rtl-ssa/accesses.cc (function_info::create_use): New.
2512 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
2513 Ensure new uses end up referring to permanent defs.
2514 * rtl-ssa/functions.h (function_info::create_use): Declare.
2516 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2518 PR target/113070
2519 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
2520 to finalize_new_accesses from the backwards placement loop, run it
2521 forwards in a separate loop.
2523 2024-01-23 Richard Biener <rguenther@suse.de>
2525 PR tree-optimization/113552
2526 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
2527 floor_log2 instead of exact_log2 on the number of calls.
2529 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
2530 Jakub Jelinek <jakub@redhat.com>
2532 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
2533 decl.
2535 2024-01-23 Richard Biener <rguenther@suse.de>
2537 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2538 Separate single and multi-exit case when creating PHIs between
2539 the main and epilogue.
2541 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
2543 PR target/112989
2544 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
2545 MODE_single variants of functions that don't take tuple arguments.
2547 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2549 PR target/113114
2550 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
2551 Don't assert recog success, just punt if the writeback pair
2552 isn't recognized.
2554 2024-01-23 Jakub Jelinek <jakub@redhat.com>
2556 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
2557 ATTRIBUTE_UNUSED to decl.
2559 2024-01-23 Richard Biener <rguenther@suse.de>
2561 PR debug/107058
2562 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
2563 handle unexpected but bogus DIE contexts when not checking
2564 enabled.
2566 2024-01-23 Jakub Jelinek <jakub@redhat.com>
2568 PR tree-optimization/113462
2569 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
2570 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
2571 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
2572 sizes between 129 and 8192 bytes.
2574 2024-01-23 Xi Ruoyao <xry111@xry111.site>
2576 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
2577 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
2578 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
2579 (loongarch_call_tls_get_addr): Do not split symbols of
2580 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
2581 EXPLICIT_RELOCS_AUTO.
2583 2024-01-23 Richard Biener <rguenther@suse.de>
2585 * alias.cc (known_base_value_p): Remove.
2586 (find_base_value): Remove PLUS/MINUS handling
2587 when both operands are not CONST_INT_P.
2589 2024-01-23 Richard Biener <rguenther@suse.de>
2591 PR rtl-optimization/113255
2592 * alias.cc (find_base_term): Remove PLUS/MINUS handling
2593 when both operands are not CONST_INT_P.
2595 2024-01-23 Richard Biener <rguenther@suse.de>
2597 PR debug/112718
2598 * dwarf2out.cc (dwarf2out_finish): Reset all type units
2599 for the fat part of an LTO compile.
2601 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
2603 * doc/sourcebuild.texi: Add attributes for keywords.
2605 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
2607 PR c++/90463
2608 * doc/invoke.texi (Warning Options): Correct lists of options
2609 enabled by -Wall and -Wextra by checking against common.opt
2610 and c-family/c.opt.
2612 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
2614 PR target/113030
2615 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
2616 instead of cpu_optaliases.
2617 (check_arch): Use arch_opt_alias instead of arch_optaliases.
2619 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2621 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
2622 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
2623 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
2625 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2627 PR target/109092
2628 * config/riscv/riscv.md: Use reg instead of subreg.
2630 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
2632 PR other/111966
2633 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
2634 to match the compiler default.
2635 (simple_object_copy_lto_debug_sections): Never unlink the outfile
2636 on error as the caller does so.
2637 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
2638 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
2640 2024-01-22 Richard Biener <rguenther@suse.de>
2642 PR tree-optimization/113373
2643 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2644 Create LC PHIs in the exit blocks where necessary.
2645 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
2646 to handle missing LC PHIs.
2647 (find_connected_edge): Remove.
2648 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
2650 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2652 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
2654 2024-01-22 xuli <xuli1@eswincomputing.com>
2656 PR target/113420
2657 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
2658 (registered_function::overloaded_hash):refactor.
2659 (resolve_overloaded_builtin):avoid internal ICE.
2661 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
2663 PR target/82420
2664 PR target/111279
2665 * calls.cc (emit_library_call_value_1): Pass valid TYPE
2666 to emit_push_insn.
2667 * expr.cc (emit_push_insn): Likewise.
2669 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
2671 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
2672 correcction version of last change.
2674 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
2676 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
2677 fix bugs in signature.
2679 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
2680 Richard Biener <rguenther@suse.de>
2682 PR rtl-optimization/111267
2683 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
2684 profitable_p method to likely_profitable_p.
2685 (try_fwprop_subst_node): Update call to likely_profitable_p.
2686 Only bail-out early when !prop.likely_profitable_p for instructions
2687 that are not single sets. When comparing costs, bail-out if the
2688 cost is unchanged and !prop.likely_profitable_p.
2690 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
2692 PR c++/90464
2693 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
2694 isn't enabled by -Wunused unless -Wextra is provided, and that
2695 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
2696 -Wunused doesn't enable -Wunused-* options documented as behaving
2697 otherwise, and list them explicitly.
2699 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
2701 PR c/109708
2702 * doc/invoke.texi (Warning Options): Fix broken example and
2703 clean up/reorganize the others. Also describe what the short-form
2704 options mean.
2706 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
2708 PR c/102998
2709 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
2710 (Warning Options): Correct/edit discussion of -Warray-parameter
2711 to make the first example less confusing, and fill in missing info.
2713 2024-01-20 Jakub Jelinek <jakub@redhat.com>
2715 PR tree-optimization/113462
2716 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
2717 Handle rhs1 INTEGER_CST like SSA_NAME.
2719 2024-01-20 Jakub Jelinek <jakub@redhat.com>
2721 PR tree-optimization/113491
2722 * tree-switch-conversion.cc (switch_conversion::build_constructors):
2723 If elt.index has precision higher than sizetype, fold_convert it to
2724 sizetype.
2725 (switch_conversion::array_value_type): Return type if type is
2726 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
2727 (switch_conversion::build_arrays): Use unsigned_type_for rather than
2728 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
2729 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
2730 higher than sizetype, use sizetype as tidx type and fold_convert the
2731 subtraction to sizetype.
2733 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2735 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
2736 (riscv_vector_mode_supported_any_target_p): Ditto.
2738 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
2740 PR target/110934
2741 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
2742 (TARGET_ZERO_CALL_USED_REGS): Define.
2744 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
2746 PR target/108640
2747 * config/m68k/m68k.cc (output_andsi3): Use QImode for
2748 address adjusted for 1-byte RMW access.
2749 (output_iorsi3): Likewise.
2750 (output_xorsi3): Likewise.
2752 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
2754 * doc/invoke.texi (RISC-V Options): Add list of supported
2755 extensions.
2757 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2759 PR target/113495
2760 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
2761 (RVV_VUNDEF): Ditto.
2762 * config/riscv/riscv-vsetvl.cc: Add timevar.
2764 2024-01-19 Richard Biener <rguenther@suse.de>
2766 PR debug/113488
2767 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
2768 an early DIE but there should be, do not pretend there is.
2770 2024-01-19 Richard Biener <rguenther@suse.de>
2772 PR tree-optimization/113494
2773 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2774 Handle endless loop on exit. Handle re-allocated PHI.
2776 2024-01-19 Jakub Jelinek <jakub@redhat.com>
2778 PR tree-optimization/113464
2779 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
2780 optimize loads into GIMPLE_ASM stmts.
2782 2024-01-19 Jakub Jelinek <jakub@redhat.com>
2784 PR tree-optimization/113463
2785 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
2786 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
2787 lhs.
2789 2024-01-19 Jakub Jelinek <jakub@redhat.com>
2791 PR tree-optimization/113459
2792 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
2793 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
2794 of SCALAR_INT_TYPE_MODE if type has BLKmode.
2795 (vn_reference_lookup_3): Likewise. Formatting fix.
2797 2024-01-19 Jakub Jelinek <jakub@redhat.com>
2798 Richard Biener <rguenther@suse.de>
2800 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
2801 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
2802 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
2803 but adjust_address also for BLKmode mode and MEM op0.
2805 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
2807 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
2808 extensions.
2810 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
2812 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
2814 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
2816 * common/config/riscv/riscv-common.cc
2817 (riscv_subset_list::parse_std_ext): Remove.
2818 (riscv_subset_list::parse_multiletter_ext): Remove.
2819 * config/riscv/riscv-subset.h
2820 (riscv_subset_list::parse_std_ext): Remove.
2821 (riscv_subset_list::parse_multiletter_ext): Remove.
2823 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
2825 * common/config/riscv/riscv-common.cc
2826 (riscv_subset_list::parse_single_std_ext): New parameter.
2827 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
2828 (riscv_subset_list::parse_single_ext): Ditto.
2829 (riscv_subset_list::parse): Relax the order for the input of ISA
2830 string.
2831 * config/riscv/riscv-subset.h
2832 (riscv_subset_list::parse_single_std_ext): New parameter.
2833 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
2834 (riscv_subset_list::parse_single_ext): Ditto.
2836 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
2838 * common/config/riscv/riscv-common.cc
2839 (riscv_subset_list::parse_base_ext): New.
2840 (riscv_subset_list::parse): Extract part of logic into
2841 riscv_subset_list::parse_base_ext.
2842 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
2843 New.
2845 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
2847 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
2848 sorry message.
2850 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
2852 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
2853 UNSPEC_CLMUL_VC.
2855 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
2857 PR c/110029
2858 * doc/extend.texi (Common Variable Attributes): Explain what
2859 happens when multiple variables with cleanups are in the same scope.
2861 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
2863 PR ipa/108470
2864 * doc/extend.texi (Common Function Attributes): Document that
2865 noinline also disables some interprocedural optimizations and
2866 improve flow to the part about using inline asm instead to
2867 disable calls from being optimized away completely. Remove the
2868 sentence that says noipa is mainly for internal compiler testing.
2870 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
2872 PR tree-optimization/69807
2873 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
2875 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
2877 PR target/108521
2878 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
2879 from x86 Windows Options.
2881 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
2883 PR c/107942
2884 * doc/extend.texi (C Extensions): Add new section to menu.
2885 (Function Attributes): Move dangling index entries to....
2886 (Const and Volatile Functions): New section.
2888 2024-01-18 David Malcolm <dmalcolm@redhat.com>
2890 PR middle-end/112684
2891 * toplev.cc (toplev::main): Don't ICE in
2892 -fdiagnostics-generate-patch when exiting after options,
2893 since no edit context will have been created.
2895 2024-01-18 Richard Biener <rguenther@suse.de>
2897 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
2898 operands vector.
2900 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
2902 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
2903 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
2905 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
2906 Jin Ma <jinma@linux.alibaba.com>
2907 Xianmiao Qu <cooper.qu@linux.alibaba.com>
2908 Christoph Müllner <christoph.muellner@vrull.eu>
2910 * config/riscv/thead.cc
2911 (th_asm_output_opcode): Rewrite some instructions.
2913 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
2914 Jin Ma <jinma@linux.alibaba.com>
2915 Xianmiao Qu <cooper.qu@linux.alibaba.com>
2916 Christoph Müllner <christoph.muellner@vrull.eu>
2918 * config/riscv/riscv.md (none,thv,rvv): New attribute.
2919 (no,yes): Add an attribute to disable alternative
2920 for xtheadvector or RVV1.0.
2921 * config/riscv/vector.md:
2922 Disable alternatives that destination register overlaps
2923 source register group for xtheadvector.
2925 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
2926 Jin Ma <jinma@linux.alibaba.com>
2927 Xianmiao Qu <cooper.qu@linux.alibaba.com>
2928 Christoph Müllner <christoph.muellner@vrull.eu>
2930 * config/riscv/riscv-vector-builtins-bases.cc
2931 (class th_loadstore_width): Define new builtin bases.
2932 (class th_extract): Define new builtin bases.
2933 (BASE): Define new builtin bases.
2934 * config/riscv/riscv-vector-builtins-bases.h:
2935 Define new builtin class.
2936 * config/riscv/riscv-vector-builtins-shapes.cc
2937 (struct th_loadstore_width_def): Define new builtin shapes.
2938 (struct th_indexed_loadstore_width_def):
2939 Define new builtin shapes.
2940 (struct th_extract_def): Define new builtin shapes.
2941 (SHAPE): Define new builtin shapes.
2942 * config/riscv/riscv-vector-builtins-shapes.h:
2943 Define new builtin shapes.
2944 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
2945 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
2946 * config/riscv/riscv-vector-builtins.h
2947 (enum required_ext): Add new XTheadVector member.
2948 (struct function_group_info): Likewise.
2949 * config/riscv/t-riscv:
2950 Add thead-vector-builtins-functions.def
2951 * config/riscv/thead-vector.md
2952 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
2953 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
2954 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
2955 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
2956 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
2957 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
2958 (@pred_th_extract<mode>): Likewise.
2959 (*pred_th_extract<mode>): Likewise.
2960 * config/riscv/thead-vector-builtins-functions.def: New file.
2962 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
2963 Jin Ma <jinma@linux.alibaba.com>
2964 Xianmiao Qu <cooper.qu@linux.alibaba.com>
2965 Christoph Müllner <christoph.muellner@vrull.eu>
2967 * config.gcc: Add files for XTheadVector intrinsics.
2968 * config/riscv/autovec.md: Guard XTheadVector.
2969 * config/riscv/predicates.md: Disable immediate vl
2970 for XTheadVector.
2971 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
2972 Add pragma for XTheadVector.
2973 * config/riscv/riscv-string.cc (riscv_expand_block_move):
2974 Guard XTheadVector.
2975 * config/riscv/riscv-v.cc (vls_mode_valid_p):
2976 Avoid autovec.
2977 * config/riscv/riscv-vector-builtins-bases.cc:
2978 Do not normalize vsetvl instructions for XTheadVector.
2979 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
2980 New check type function.
2981 (build_one): Adjust for XTheadVector.
2982 * config/riscv/riscv-vector-switch.def (ENTRY):
2983 Disable fractional mode for the XTheadVector extension.
2984 (TUPLE_ENTRY): Likewise.
2985 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
2986 Guard XTheadVector.
2987 (riscv_preferred_simd_mode): Likewsie.
2988 (riscv_autovectorize_vector_modes): Likewise.
2989 (riscv_vector_mode_supported_any_target_p): Likewise.
2990 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
2991 * config/riscv/thead.cc (th_asm_output_opcode):
2992 Rewrite vsetvl instructions.
2993 * config/riscv/vector.md:
2994 Include thead-vector.md and change fractional LMUL
2995 into 1 for vbool.
2996 * config/riscv/riscv_th_vector.h: New file.
2997 * config/riscv/thead-vector.md: New file.
2999 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3000 Jin Ma <jinma@linux.alibaba.com>
3001 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3002 Christoph Müllner <christoph.muellner@vrull.eu>
3004 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
3005 Add new function to add assembler insn code prefix/suffix.
3006 (th_asm_output_opcode):
3007 Add Thead function to add assembler insn code prefix/suffix.
3008 * config/riscv/riscv.cc (riscv_asm_output_opcode):
3009 Implement function to add assembler insn code prefix/suffix.
3010 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
3011 Add new function to add assembler insn code prefix/suffix.
3012 * config/riscv/thead.cc (th_asm_output_opcode):
3013 Implement Thead function to add assembler insn code
3014 prefix/suffix.
3016 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3017 Jin Ma <jinma@linux.alibaba.com>
3018 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3019 Christoph Müllner <christoph.muellner@vrull.eu>
3021 * common/config/riscv/riscv-common.cc
3022 (riscv_subset_list::parse): Add new vendor extension.
3023 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
3024 Add test marco.
3025 * config/riscv/riscv.opt: Add new mask.
3027 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3029 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
3030 to be conditional on macosx-version-min.
3032 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3034 * config/darwin.cc (darwin_objc1_section): Use the correct
3035 meta-data version for constant strings.
3036 (machopic_select_section): Assert if we fail to handle CFString
3037 sections as Obejctive-C meta-data or drectly.
3039 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3041 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
3042 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
3043 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
3044 versions when the object format is Mach-O.
3046 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3048 PR target/105522
3049 * config/darwin.cc (machopic_select_section): Handle C and C++
3050 CFStrings.
3051 (darwin_rename_builtins): Move this out of the CFString code.
3052 (darwin_libc_has_function): Likewise.
3053 (darwin_build_constant_cfstring): Create an anonymous var to
3054 hold each CFString.
3055 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
3056 CFstrings.
3058 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
3060 PR bootstrap/113445
3061 * haifa-sched.cc (dep_list_size): Make global.
3062 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
3063 * sched-int.h (dep_list_size): Declare.
3065 2024-01-18 Martin Jambor <mjambor@suse.cz>
3067 PR tree-optimization/110422
3068 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
3069 gotos.
3071 2024-01-18 Richard Biener <rguenther@suse.de>
3073 PR tree-optimization/113475
3074 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
3075 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
3076 (phi_analyzer::~phi_analyzer): Deallocate and free collected
3077 phi_grous.
3078 (phi_analyzer::process_phi): Record allocated phi_groups.
3080 2024-01-18 Richard Biener <rguenther@suse.de>
3082 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
3083 storage for gvec_oprnds elements.
3085 2024-01-18 Richard Biener <rguenther@suse.de>
3087 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
3088 prefer all later exits we can handle.
3089 (vect_analyze_loop_form): Free the allocated loop body.
3090 Adjust comments.
3092 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3094 * config/avr/avr-log.cc: Tabify.
3096 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3098 * config/riscv/autovec.md: Support vi variant.
3100 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3102 * config/avr/avr-devices.cc: Tabify.
3104 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3106 * config/avr/avr-c.cc: Tabify.
3108 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3110 * config/avr/driver-avr.cc: Tabify.
3112 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3114 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
3116 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3118 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
3120 2024-01-18 Jakub Jelinek <jakub@redhat.com>
3122 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
3123 minline-strcmp, minline-strncmp, minline-strlen,
3124 -param=riscv-vector-abi): Remove Bool keywords.
3126 2024-01-18 Jakub Jelinek <jakub@redhat.com>
3128 PR target/113122
3129 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
3130 support. Add missing space after , in emitted assembly in some
3131 cases. Formatting fixes.
3133 2024-01-18 Xi Ruoyao <xry111@xry111.site>
3135 * config/loongarch/loongarch.md (movsi_internal): Remove
3136 constraint z.
3138 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3140 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
3141 in the diagnostic, and capitalize the device name.
3142 (print_mcu): Generate specs such that:
3143 <*check_rodata_in_ram>: New.
3144 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
3145 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
3146 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
3148 2024-01-18 Jakub Jelinek <jakub@redhat.com>
3150 PR other/113399
3151 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
3152 Common and Optimization.
3154 2024-01-18 Richard Biener <rguenther@suse.de>
3156 PR tree-optimization/113431
3157 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
3158 When there is an invariant load we might not preserve
3159 scalar order.
3161 2024-01-18 Richard Biener <rguenther@suse.de>
3163 PR tree-optimization/113374
3164 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
3165 * tree-vect-loop.cc (move_early_exit_stmts): Update
3166 virtual LC PHIs.
3167 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3168 Refactor. Preserve virtual LC PHIs on all exits.
3170 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
3172 * config/loongarch/loongarch.cc (loongarch_split_symbol):
3173 Assign the '/u' attribute to the mem.
3175 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3177 PR middle-end/110847
3178 * doc/invoke.texi (Option Summary): Document negative forms of
3179 -Wtsan and -Wxor-used-as-pow.
3180 (Warning Options): Likewise.
3182 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3184 PR target/113429
3185 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
3187 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3189 * doc/extend.texi (Common Function Attributes): Re-alphabetize
3190 the table.
3191 (Common Variable Attributes): Likewise.
3192 (Common Type Attributes): Likewise.
3194 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
3196 PR middle-end/111659
3197 * doc/extend.texi (Common Variable Attributes): Fix long lines
3198 in documentation of strict_flex_array + other minor copy-editing.
3199 Add a cross-reference to -Wstrict-flex-arrays.
3200 * doc/invoke.texi (Option Summary): Fix whitespace in tables
3201 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
3202 (C Dialect Options): Combine the docs for the two
3203 -fstrict-flex-arrays forms into a single entry. Note this option
3204 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
3205 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
3206 Minor copy-editing. Add cross references to the strict_flex_array
3207 attribute and -fstrict-flex-arrays option. Add note that this
3208 option depends on -ftree-vrp.
3210 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
3212 PR target/113221
3213 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
3214 only allow REG operands instead of allowing all.
3216 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
3218 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
3219 Remove redundant checks in else condition for readablity.
3220 (earliest_fuse_vsetvl_info) Print iteration count in debug
3221 prints.
3222 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
3223 dump details in certain cases.
3225 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
3227 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
3228 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
3229 * config/riscv/riscv-vsetvl.cc
3230 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
3231 (pass_vsetvl::execute): Use vsetvl_strategy.
3233 2024-01-17 Jan Hubicka <jh@suse.cz>
3235 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
3236 accidental hack reseting offset.
3238 2024-01-17 Jan Hubicka <jh@suse.cz>
3240 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
3241 handling of X86_TUNE_AVOID_512FMA_CHAINS.
3243 2024-01-17 Jan Hubicka <jh@suse.cz>
3244 Jakub Jelinek <jakub@redhat.com>
3246 PR tree-optimization/110852
3247 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
3248 binary operations
3249 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
3250 PRED_COMBINED_VALUE_PREDICTIONS_PHI
3251 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
3252 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
3254 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3256 PR tree-optimization/113421
3257 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
3258 comment.
3259 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
3260 formatting. Start at vop rather than cvop even if stmt is a store
3261 and needs_operand_addr.
3263 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3265 PR middle-end/113410
3266 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
3267 If access_nelts is integral with larger precision than sizetype,
3268 fold_convert it to sizetype.
3270 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3272 PR tree-optimization/113408
3273 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
3274 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
3275 to handle_cast.
3277 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3279 PR middle-end/113406
3280 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
3281 regardless of whether is_gimple_reg_type (restype) or not.
3283 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3285 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
3286 funcions -> functions, and use were instead of was.
3287 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
3288 and guaranteee -> guarantee.
3289 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
3291 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3293 PR middle-end/113409
3294 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
3295 INTEGER_TYPE.
3296 (omp_extract_for_data): Use build_bitint_type rather than
3297 build_nonstandard_integer_type if either iter_type or loop->v type
3298 is BITINT_TYPE.
3299 * omp-expand.cc (expand_omp_for_generic,
3300 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
3301 BITINT_TYPE like INTEGER_TYPE.
3303 2024-01-17 Richard Biener <rguenther@suse.de>
3305 PR tree-optimization/113371
3306 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
3307 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
3308 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
3309 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
3311 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
3313 PR rtl-optimization/96388
3314 PR rtl-optimization/111554
3315 * sched-deps.cc (find_inc): Avoid exponential behavior.
3317 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
3319 PR c/111693
3320 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
3321 from C++ Language Options to Warning Options. Add entry for
3322 -Wuse-after-free.
3323 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
3324 from here....
3325 (Warning Options): ...to here. Minor copy-editing to fix typo
3326 and grammar.
3328 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
3330 * config/mips/mips.cc (mips_compute_frame_info): If another
3331 register is used as global_pointer, mark $GP live false.
3333 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
3335 PR target/112973
3336 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
3337 give the section a light copy-editing pass.
3339 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
3341 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
3342 * config/aarch64/aarch64-tune.md: Regenerated.
3343 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
3345 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
3347 PR target/112573
3348 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
3349 badly formed CONST expressions.
3351 2024-01-16 Daniel Cederman <cederman@gaisler.com>
3353 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
3355 2024-01-16 Daniel Cederman <cederman@gaisler.com>
3357 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
3358 * config/sparc/sync.md (membar_storeload): Turn into named insn
3359 and add GR712RC errata workaround.
3360 (membar_v8): Add GR712RC errata workaround.
3362 2024-01-16 Andreas Larsson <andreas@gaisler.com>
3364 * config/sparc/sync.md (*membar_storeload_leon3): Remove
3365 (*membar_storeload): Enable for LEON
3367 2024-01-16 Jakub Jelinek <jakub@redhat.com>
3369 PR tree-optimization/113372
3370 PR middle-end/90348
3371 PR middle-end/110115
3372 PR middle-end/111422
3373 * cfgexpand.cc (add_scope_conflicts_2): New function.
3374 (add_scope_conflicts_1): Use it.
3376 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
3378 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
3379 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
3380 * doc/avr-mmcu.texi: Regenerate.
3382 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
3384 PR tree-optimization/113091
3385 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
3386 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
3387 scalar use with new function.
3388 (vect_bb_slp_mark_live_stmts): New function as entry to existing
3389 overriden functions with same name.
3390 (vect_slp_analyze_operations): Call new entry function to mark
3391 live statements.
3393 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3395 PR target/113404
3396 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
3397 for RVV in big-endian mode.
3399 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
3401 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
3402 (riscv_pass_in_vector_p): Delete.
3403 (riscv_init_cumulative_args): Delete the checking.
3404 (riscv_get_arg_info): Delete the checking.
3405 (riscv_function_value): Delete the checking.
3406 * config/riscv/riscv.h: Delete the member for checking.
3408 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
3410 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
3412 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
3414 * config.gcc: Include riscv_bitmanip.h.
3415 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
3416 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
3417 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
3418 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
3419 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
3420 * config/riscv/riscv-ftypes.def (2): New ftypes.
3421 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
3422 (RISCV_BUILTIN_NO_PREFIX): Likewise.
3423 * config/riscv/riscv_bitmanip.h: New file.
3425 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
3427 * config.gcc: Include riscv_crypto.h.
3428 * config/riscv/riscv_crypto.h: New file.
3430 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
3432 PR middle-end/113354
3433 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
3434 in the insn if the corresponding operand does not require hard
3435 register anymore.
3437 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
3439 PR target/107201
3440 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
3441 * config/avr/driver-avr.cc (avr_no_devlib): New function.
3442 (avr_devicespecs_file): Use it to remove -nodevicelib from the
3443 options for cores only.
3444 * config/avr/avr-arch.h (avr_get_parch): New prototype.
3445 * config/avr/avr-devices.cc (avr_get_parch): New function.
3447 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3449 PR target/113247
3450 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
3451 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
3452 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
3454 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3456 PR target/113281
3457 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
3458 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
3459 * config/riscv/riscv-vector-costs.h: New function.
3461 2024-01-15 Richard Biener <rguenther@suse.de>
3463 PR tree-optimization/113385
3464 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3465 First redirect, then split the exit edge.
3467 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3469 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
3470 Remove m_num_vector_iterations.
3471 * config/riscv/riscv-vector-costs.h: Ditto.
3473 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
3475 PR target/113156
3476 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
3477 (-mbranch-cost): Set "Optimization" flag.
3479 2024-01-15 Jakub Jelinek <jakub@redhat.com>
3481 PR tree-optimization/113370
3482 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
3483 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
3484 set it to just prec % limb_prec.
3486 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3488 PR target/113393
3489 * config/riscv/vector.md: Fix ternary attributes.
3491 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
3493 PR target/112944
3494 * configure.ac [target=avr]: Check availability of emulations
3495 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
3496 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
3497 * configure: Regenerate.
3498 * config.in: Regenerate.
3499 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
3500 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
3501 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
3502 * config/avr/avr-arch.h (enum avr_device_specific_features):
3503 Add AVR_ISA_FLMAP.
3504 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
3505 AVR_ISA_FLMAP.
3506 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
3507 (avr_set_core_architecture): Set avr_arch_index.
3508 (have_avrxmega2_flmap, have_avrxmega4_flmap)
3509 (have_avrxmega3_rodata_in_flash): Set new static const bool according
3510 to configure results.
3511 (avr_rodata_in_flash_p): New function using them.
3512 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
3513 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
3514 (avr_asm_named_section): Track avr_has_rodata_p.
3515 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
3516 and not avr_rodata_in_flash_p ().
3517 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
3518 (LINK_SPEC): Add %(link_rodata_in_ram).
3519 (LINK_ARCH_SPEC): Remove.
3520 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
3521 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
3522 const bool according to configure results.
3523 (diagnose_mrodata_in_ram): New function.
3524 (print_mcu): Generate specs with the following changes:
3525 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
3526 need to extend avr/specs.h each time we add a new bell or whistle.
3527 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
3528 -m[no-]rodata-in-ram.
3529 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
3530 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
3531 <*cpp>: Add %(cpp_rodata_in_ram).
3532 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
3533 requested.
3534 <*self_spec>: Add -mflmap or %<mflmap as needed.
3536 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
3538 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
3539 not the GPR iterator. Adjust pattern name and mode attribute
3540 accordingly.
3542 2024-01-13 Jakub Jelinek <jakub@redhat.com>
3544 PR tree-optimization/113361
3545 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
3546 Fix up determination of the type for > limb_prec constants.
3548 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
3550 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
3551 Add web-link to the avr-gcc wiki.
3553 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
3555 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
3556 documentation for a version without argument, which is not supported.
3558 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3560 * config/arm/arm_neon.h
3561 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
3562 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
3563 (vld1_f16_x4, vld1_f32_x4): New.
3564 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
3565 (vld1_bf16_x4): New.
3566 (vld1q_types_x4): Updated to use vld1q_x4
3567 from arm_neon_builtins.def
3568 * config/arm/arm_neon_builtins.def
3569 (vld1_x4): Updated entries.
3570 (vld1q_x4): New entries, but comes from the old vld1_x4
3571 * config/arm/neon.md
3572 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
3574 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3576 * config/arm/arm_neon.h
3577 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
3578 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
3579 (vld1_f16_x3, vld1_f32_x3): New.
3580 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
3581 (vld1_bf16_x3): New.
3582 (vld1q_types_x3): Updated to use vld1q_x3 from
3583 arm_neon_builtins.def
3584 * config/arm/arm_neon_builtins.def
3585 (vld1_x3): Updated entries.
3586 (vld1q_x3): New entries, but comes from the old vld1_x2
3587 * config/arm/neon.md
3588 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
3590 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3592 * config/arm/arm_neon.h
3593 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
3594 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
3595 (vld1_f16_x2, vld1_f32_x2): New.
3596 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
3597 (vld1_bf16_x2): New.
3598 (vld1q_types_x2): Updated to use vld1q_x2 from
3599 arm_neon_builtins.def
3600 * config/arm/arm_neon_builtins.def
3601 (vld1_x2): Updated entries.
3602 (vld1q_x2): New entries, but comes from the old vld1_x2
3603 * config/arm/neon.md
3604 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
3605 neon_vld1_x2<mode>.
3607 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3609 * config/arm/arm_neon.h
3610 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
3611 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
3612 (vst1q_f16_x4, vst1q_f32_x4): New.
3613 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
3614 (vst1q_bf16_x4): New.
3615 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
3616 * config/arm/neon.md
3617 (neon_vst1q_x4<mode>): New.
3618 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
3619 * config/arm/unspecs.md
3620 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
3622 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3624 * config/arm/arm_neon.h
3625 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
3626 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
3627 (vst1q_f16_x3, vst1q_f32_x3): New.
3628 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
3629 (vst1q_bf16_x3): New.
3630 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
3631 * config/arm/neon.md
3632 (neon_vst1q_x3<mode>): New.
3633 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
3634 * config/arm/unspecs.md
3635 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
3637 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3639 * config/arm/arm_neon.h
3640 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
3641 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
3642 (vst1q_f16_x2, vst1q_f32_x2): New.
3643 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
3644 (vst1q_bf16_x2): New.
3645 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
3646 * config/arm/neon.md
3647 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
3648 neon_vst1_x2<mode>.
3649 * config/arm/iterators.md
3650 (VMEMX2): New mode iterator.
3651 (VMEMX2_q): New mode attribute.
3653 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3655 * config/arm/arm_neon.h
3656 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
3657 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
3658 (vst1_f16_x4, vst1_f32_x4): New.
3659 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
3660 (vst1_bf16_x4): New.
3661 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
3662 * config/arm/neon.md (vst1_x4<mode>): New.
3664 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3666 * config/arm/arm_neon.h
3667 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
3668 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
3669 (vst1_f16_x3, vst1_f32_x3): New.
3670 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
3671 (vst1_bf16_x3): New.
3672 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
3673 * config/arm/neon.md (vst1_x3<mode>): New.
3675 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3677 * config/arm/arm_neon.h
3678 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
3679 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
3680 (vst1_f16_x2, vst1_f32_x2): New.
3681 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
3682 (vst1_bf16_x2): New.
3683 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
3684 * config/arm/neon.md (vst1_x2<mode>): New.
3686 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3688 * config/arm/arm_neon.h
3689 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
3690 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
3691 (vld1q_f16_x4, vld1q_f32_x4): New.
3692 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
3693 (vld1q_bf16_x4): New.
3694 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
3695 * config/arm/neon.md
3696 (neon_vld1_x4<mode>): New.
3697 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
3698 * config/arm/unspecs.md
3699 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
3701 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3703 * config/arm/arm_neon.h
3704 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
3705 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
3706 (vld1q_f16_x3, vld1q_f32_x3): New.
3707 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
3708 (vld1q_bf16_x3): New.
3709 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
3710 * config/arm/neon.md
3711 (neon_vld1_x3<mode>): New.
3712 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
3713 * config/arm/unspecs.md
3714 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
3716 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3718 * config/arm/arm_neon.h
3719 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
3720 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
3721 (vld1q_f16_x2, vld1q_f32_x2): New.
3722 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
3723 (vld1q_bf16_x2): New.
3724 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
3725 * config/arm/neon.md (vld1_x2<mode>): New.
3727 2024-01-12 Tamar Christina <tamar.christina@arm.com>
3729 PR tree-optimization/113287
3730 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
3732 2024-01-12 Tamar Christina <tamar.christina@arm.com>
3734 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
3735 * tree-vect-loop.cc (vect_transform_loop): Likewise.
3737 2024-01-12 Tamar Christina <tamar.christina@arm.com>
3739 PR tree-optimization/113178
3740 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
3741 alternate exits.
3743 2024-01-12 Tamar Christina <tamar.christina@arm.com>
3745 PR tree-optimization/113237
3746 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
3747 existing LCSSA variable for exit when all exits are early break.
3749 2024-01-12 Tamar Christina <tamar.christina@arm.com>
3751 PR tree-optimization/113137
3752 PR tree-optimization/113136
3753 PR tree-optimization/113172
3754 PR tree-optimization/113178
3755 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3756 Maintain PHIs on inverted loops.
3757 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
3758 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
3759 latch.
3760 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
3762 2024-01-12 Tamar Christina <tamar.christina@arm.com>
3764 PR tree-optimization/113135
3765 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
3766 dependency analysis.
3768 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
3770 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
3771 diagnostics class member name for abort of error.
3773 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
3775 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
3776 format string to %s argument.
3778 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
3779 Jakub Jelinek <jakub@redhat.com>
3781 PR middle-end/113182
3782 * varasm.cc (process_pending_assemble_externals,
3783 assemble_external_libcall): Use targetm.strip_name_encoding
3784 before calling get_identifier.
3786 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
3788 PR target/113196
3789 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
3790 New member variable.
3791 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
3792 Declare.
3793 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
3794 * config/aarch64/aarch64-simd.md
3795 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
3796 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
3797 zip2 for zero-extends to...
3798 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
3799 instruction. Fix big-endian handling.
3800 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
3801 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
3802 zip1 for zero-extends to...
3803 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
3804 Fix big-endian handling.
3805 (*aarch64_zip1_uxtl): New pattern.
3806 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
3807 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
3808 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
3809 (aarch64_gen_shareable_zero): Use it.
3810 (aarch64_split_simd_shift_p): New function.
3812 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
3814 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
3815 (function_beg_insn): New macro.
3816 * function.cc (expand_function_start): Initialize function_beg_insn.
3818 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
3820 PR target/112989
3821 * config/aarch64/aarch64-sve-builtins.h
3822 (function_builder::m_overload_names): Replace with...
3823 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
3824 new global.
3825 (add_overloaded_function): Update accordingly, using get_identifier
3826 to get a GGC-friendly record of the name.
3828 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
3830 PR target/112989
3831 * config/aarch64/aarch64-sve-builtins.def: Don't include
3832 aarch64-sve-builtins-sme.def.
3833 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
3834 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
3835 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
3836 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
3837 requires AARCH64_FL_SME2.
3838 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
3839 AARCH64_FL_SME adjustment here.
3840 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
3841 include SME intrinsics.
3842 (sme_function_groups): New array.
3843 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
3844 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
3846 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3848 PR target/113281
3849 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
3850 (struct cpu_vector_cost): Add regmove struct.
3851 (get_vector_costs): Export as global.
3852 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
3853 (costs::add_stmt_cost): Ditto.
3854 * config/riscv/riscv.cc (get_common_costs): Export global function.
3856 2024-01-12 Jakub Jelinek <jakub@redhat.com>
3858 PR tree-optimization/113334
3859 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
3860 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
3861 to determine if number should be extended by all ones rather than zero
3862 extended.
3864 2024-01-12 Jakub Jelinek <jakub@redhat.com>
3866 PR tree-optimization/113330
3867 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
3868 too large size.
3870 2024-01-12 Jakub Jelinek <jakub@redhat.com>
3872 PR tree-optimization/113323
3873 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
3874 check for lhs being large/huge _BitInt not in m_names.
3876 2024-01-12 Jakub Jelinek <jakub@redhat.com>
3878 PR tree-optimization/113316
3879 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
3880 uninitialized large/huge _BitInt arguments to calls.
3882 2024-01-12 Jakub Jelinek <jakub@redhat.com>
3884 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
3885 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
3886 CEIL (TYPE_PRECISION (t), limb_prec).
3887 (bitint_large_huge::handle_cast): Likewise.
3889 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
3891 PR sanitizer/113284
3892 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
3893 Use assemble_function_label_final () for Power ELF V1 ABI.
3894 * output.h (assemble_function_label_final): New function.
3895 * varasm.cc (assemble_function_label_raw): Use
3896 assemble_function_label_final ().
3897 (assemble_function_label_final): New function.
3899 2024-01-12 Richard Biener <rguenther@suse.de>
3901 PR middle-end/113344
3902 * match.pd ((double)float CMP (double)float -> float CMP float):
3903 Perform result type check only for vectors.
3904 * fold-const.cc (fold_binary_loc): Likewise.
3906 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
3908 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
3909 (usdot_prod<mode>): Ditto.
3910 (sdot_prod<mode>): Ditto.
3911 (udot_prod<mode>): Ditto.
3913 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
3915 PR target/113288
3916 * config/i386/i386-c.cc (ix86_target_macros_internal):
3917 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
3919 2024-01-12 Richard Biener <rguenther@suse.de>
3921 PR target/112280
3922 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
3923 Do not generate code when d.testing_p.
3925 2024-01-12 liuhongt <hongtao.liu@intel.com>
3927 PR target/113039
3928 * doc/invoke.texi (fcf-protection=): Update documents.
3930 2024-01-12 Pan Li <pan2.li@intel.com>
3932 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
3933 comments of predicate func riscv_v_ext_mode_p.
3935 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
3937 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
3938 Modify ABI-name length of vfloat16m8_t
3940 2024-01-12 Li Wei <liwei@loongson.cn>
3942 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
3943 Adjust.
3945 2024-01-12 Li Wei <liwei@loongson.cn>
3947 * config/loongarch/loongarch.md (add<mode>3): Removed.
3948 (*addsi3): New.
3949 (addsi3): Ditto.
3950 (adddi3): Ditto.
3951 (*addsi3_extended): Removed.
3952 (addsi3_extended): New.
3954 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
3956 * config/riscv/thead.md: Add limits for splits.
3958 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
3960 PR middle-end/113322
3961 * expr.cc (do_store_flag): Don't try single bit tests with
3962 comparison on vector types.
3964 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
3966 PR tree-optimization/113301
3967 * match.pd (`1/x`): Delay signed case until late.
3969 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
3971 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
3972 and -msp8 to...
3973 (AVR Internal Options): ...this new @subsubsection.
3975 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
3977 PR rtl-optimization/112918
3978 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
3979 (in_class_p): Restrict condition for narrowing class in case of
3980 allow_all_reload_class_changes_p.
3981 (process_alt_operands): Try to match operand without and with
3982 narrowing reg class. Discourage narrowing the class. Finish insn
3983 matching only if there is no class narrowing.
3984 (curr_insn_transform): Pass true to in_class_p for reg operand win.
3986 2024-01-11 Richard Biener <rguenther@suse.de>
3988 PR tree-optimization/112505
3989 * tree-vect-loop.cc (vectorizable_induction): Reject
3990 bit-precision induction.
3992 2024-01-11 Richard Biener <rguenther@suse.de>
3994 PR tree-optimization/113126
3995 * match.pd ((double)float CMP (double)float -> float CMP float):
3996 Make sure the boolean type is the same.
3997 * fold-const.cc (fold_binary_loc): Likewise.
3999 2024-01-11 Richard Biener <rguenther@suse.de>
4001 PR tree-optimization/112636
4002 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
4003 estimate_numbers_of_iterations before querying
4004 get_max_loop_iterations_int.
4005 (pass_ch::execute): Initialize SCEV and loops appropriately.
4007 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
4009 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
4010 Reduced Tiny.
4011 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
4012 * doc/extend.texi (AVR Variable Attributes): Improve documentation
4013 of io, io_low and address attributes.
4014 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
4015 * doc/avr-mmcu.texi: Rebuild.
4017 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
4019 PR target/113233
4020 * config/loongarch/genopts/loongarch.opt.in: Mark options with
4021 the "Save" property.
4022 * config/loongarch/loongarch.opt: Same.
4023 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
4024 according to la_target.
4025 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
4026 RESTORE} for the la_target structure; Rename option conditions
4027 to have the same "la_" prefix.
4028 * config/loongarch/loongarch.h: Same.
4030 2024-01-11 Pan Li <pan2.li@intel.com>
4032 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
4033 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
4035 2024-01-11 Alex Coplan <alex.coplan@arm.com>
4037 PR target/113077
4038 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
4039 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
4040 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
4041 synthesize these if needed. Update caller ...
4042 (ldp_bb_info::fuse_pair): ... here.
4043 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
4044 and either insn is frame-related.
4045 (find_trailing_add): Punt on frame-related insns.
4046 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
4047 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
4049 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
4051 * config/mips/mips.cc (mips_start_function_definition):
4052 Add ATTRIBUTE_UNUSED.
4054 2024-01-11 Richard Biener <rguenther@suse.de>
4056 PR middle-end/112740
4057 * expr.cc (store_constructor): Check the integer vector
4058 mask has a single bit per element before using sign-extension
4059 to expand an uniform vector.
4061 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4063 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
4064 preempt VLS on unknown NITERS loop.
4066 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
4068 * doc/invoke.texi: Add -mevex512.
4070 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
4072 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
4073 (*nor<mode>3): Likewise.
4074 (nor<mode>3): Likewise.
4075 (*negsi2_extended): New template.
4076 (*<optab>si3_internal): Likewise.
4077 (*one_cmplsi2_internal): Likewise.
4078 (*norsi3_internal): Likewise.
4079 (*<optab>nsi_internal): Likewise.
4080 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
4081 modified bit operation to make the optimization work.
4083 2024-01-11 liuhongt <hongtao.liu@intel.com>
4085 PR target/104401
4086 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
4088 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4090 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
4091 (get_vector_costs): Ditto.
4092 (riscv_builtin_vectorization_cost): Ditto.
4094 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4096 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
4098 2024-01-10 Antoni Boucher <bouanto@zoho.com>
4100 PR jit/111396
4101 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
4102 ipa_free_size_summary.
4103 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
4104 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
4105 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
4106 * ipa-prop.h (ipa_prop_cc_finalize): New function.
4107 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
4108 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
4109 ipa_sra_cc_finalize): New functions.
4110 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
4111 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
4112 ipa_sra_cc_finalize
4113 Include ipa-utils.h.
4115 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
4117 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
4118 (th_int_get_save_adjustment): Likewise.
4119 (th_int_adjust_cfi_prologue): Likewise.
4120 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
4121 (TH_INT_INTERRUPT): New macro.
4122 (riscv_expand_prologue): Add the processing of XTheadInt.
4123 (riscv_expand_epilogue): Likewise.
4124 * config/riscv/riscv.h (BITSET_P): Moved to here.
4125 * config/riscv/riscv.md: New unspec.
4126 * config/riscv/thead.cc (th_int_get_mask): New function.
4127 (th_int_get_save_adjustment): Likewise.
4128 (th_int_adjust_cfi_prologue): Likewise.
4129 * config/riscv/thead.md (th_int_push): New pattern.
4130 (th_int_pop): new pattern.
4132 2024-01-10 Tamar Christina <tamar.christina@arm.com>
4134 PR tree-optimization/112468
4135 * doc/sourcebuild.texi: Document ifn_copysign.
4136 * match.pd: Only apply transformation if target supports the IFN.
4138 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
4140 PR tree-optimization/112581
4141 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
4142 mark_ssa_maybe_undefs.
4143 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
4144 variables can not be reassociated.
4145 (init_range_entry): Check for uninitialized variables too.
4146 (init_reassoc): Call mark_ssa_maybe_undefs.
4148 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
4150 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
4151 Also handle sign extension.
4153 2024-01-10 Alex Coplan <alex.coplan@arm.com>
4155 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
4156 to 0.
4157 (-mlate-ldp-fusion): Likewise.
4159 2024-01-10 Tamar Christina <tamar.christina@arm.com>
4161 PR tree-optimization/113287
4162 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
4163 instead of using BRANCH_EDGE to determine true edge.
4165 2024-01-10 Richard Biener <rguenther@suse.de>
4167 PR tree-optimization/113078
4168 * tree-vect-loop.cc (check_reduction_path): Canonicalize
4169 .COND_SUB to .COND_ADD.
4171 2024-01-10 David Malcolm <dmalcolm@redhat.com>
4173 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
4174 Handle prefix mappings before calling find_opt.
4175 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
4176 "-fno-"-prefixed command-line option.
4177 * opts-common.cc (get_option_prefix_remapping): New.
4178 * opts.h (get_option_prefix_remapping): New decl.
4180 2024-01-10 David Malcolm <dmalcolm@redhat.com>
4182 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
4183 m_urlifier to pp_output_formatted_text.
4184 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
4185 (obstack_append_string): New overload, taking a length.
4186 (urlify_quoted_string): Pass in an obstack ptr, rather than using
4187 that of the pp's buffer. Generalize to handle trailing text in
4188 the buffer beyond the run of quoted text.
4189 (class quoting_info): New.
4190 (on_begin_quote): New.
4191 (on_end_quote): New.
4192 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
4193 it to calls to on_begin_quote and on_end_quote.
4194 (struct auto_obstack): New.
4195 (quoting_info::handle_phase_3): New.
4196 (pp_output_formatted_text): Add urlifier param. Use it if there
4197 is deferred urlification. Delete m_quotes.
4198 (selftest::pp_printf_with_urlifier): Pass urlifier to
4199 pp_output_formatted_text.
4200 (selftest::test_urlification): Update results for the existing
4201 case of quoted text stradding chunks; add more such test cases.
4202 * pretty-print.h (class quoting_info): New forward decl.
4203 (chunk_info::m_quotes): New field.
4204 (pp_output_formatted_text): Add optional urlifier param.
4206 2024-01-10 David Malcolm <dmalcolm@redhat.com>
4208 * pretty-print.cc (selftest::test_pp_format): Add selftest
4209 coverage for numbered args.
4211 2024-01-10 Tamar Christina <tamar.christina@arm.com>
4213 PR tree-optimization/113144
4214 PR tree-optimization/113145
4215 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4216 Update all BB that the original exits dominated.
4218 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
4220 * dwarf2out.cc (modified_type_die): Extend the support of reverse
4221 storage order to enumeration types if -gstrict-dwarf is not passed.
4222 (gen_enumeration_type_die): Add REVERSE parameter and generate the
4223 DIE immediately after the existing one if it is true.
4224 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
4225 call to gen_enumeration_type_die.
4226 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
4227 first recursive call as well as the call to gen_tagged_type_die.
4228 (gen_type_die): Add REVERSE parameter and pass it in the call to
4229 gen_type_die_with_usage.
4231 2024-01-10 Jakub Jelinek <jakub@redhat.com>
4233 PR tree-optimization/113120
4234 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
4235 with root->size TYPE_PRECISION don't build anything new.
4236 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
4237 rather than build_nonstandard_integer_type.
4239 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
4241 * config/i386/i386.opt: Adjust document.
4242 * doc/invoke.texi: Add description for
4243 -mapx-inline-asm-use-gpr32.
4245 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4247 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
4248 (avg<v_double_trunc>3_floor): New pattern.
4249 (<u>avg<v_double_trunc>3_ceil): Remove.
4250 (avg<v_double_trunc>3_ceil): New pattern.
4251 (uavg<mode>3_floor): Ditto.
4252 (uavg<mode>3_ceil): Ditto.
4253 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
4254 (enum insn_type): Ditto.
4255 * config/riscv/riscv-v.cc: Ditto.
4256 * config/riscv/vector-iterators.md (ashiftrt): Remove.
4257 (ASHIFTRT): Ditto.
4258 * config/riscv/vector.md: Add VLS modes.
4260 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
4262 PR target/111480
4263 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
4264 (vczlsbb_char): New int attribute.
4265 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
4266 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
4267 (*vctzlsbb_zext_<mode>): Rename to ...
4268 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
4269 cover vclzlsbb.
4271 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
4273 PR target/112606
4274 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
4275 of the last argument from altivec_register_operand to any_operand. If
4276 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
4277 otherwise if it doesn't satisfy altivec_register_operand, force it to
4278 REG using copy_to_mode_reg.
4280 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
4282 PR middle-end/113100
4283 * builtins.cc (expand_builtin_stack_address): Guard stack point
4284 adjustment with SPARC_STACK_BOUNDARY_HACK.
4286 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
4288 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
4289 argument string definitions.
4290 * config/loongarch/loongarch-str.h: Same.
4291 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
4292 as aliases to -mexplicit-relocs={always,none}
4293 * config/loongarch/loongarch.opt: Regenerate.
4294 * config/loongarch/loongarch.cc: Same.
4296 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
4298 * config/loongarch/loongarch-def.h: Define constants with
4299 enums instead of Macros.
4301 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
4303 * config/loongarch/genopts/loongarch-strings: Rename.
4304 * config/loongarch/genopts/loongarch.opt.in: Same.
4305 * config/loongarch/loongarch-cpu.cc: Same.
4306 * config/loongarch/loongarch-def.cc: Same.
4307 * config/loongarch/loongarch-def.h: Same.
4308 * config/loongarch/loongarch-opts.cc: Same.
4309 * config/loongarch/loongarch-opts.h: Same.
4310 * config/loongarch/loongarch-str.h: Same.
4311 * config/loongarch/loongarch.opt: Same.
4313 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
4315 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
4316 variable with the common la_ prefix.
4317 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
4318 flags as saved using TargetVariable.
4319 * config/loongarch/loongarch.opt: Same.
4320 * config/loongarch/loongarch-def.h: Define evolution_set to
4321 mark changes to the -march default.
4322 * config/loongarch/loongarch-driver.cc: Same.
4323 * config/loongarch/loongarch-opts.cc: Same.
4324 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
4325 conditions around the la_target structure.
4326 * config/loongarch/loongarch.cc: Same.
4327 * config/loongarch/loongarch.md: Same.
4328 * config/loongarch/loongarch-builtins.cc: Same.
4329 * config/loongarch/loongarch-c.cc: Same.
4330 * config/loongarch/lasx.md: Same.
4331 * config/loongarch/lsx.md: Same.
4332 * config/loongarch/sync.md: Same.
4334 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
4336 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
4337 no less.
4339 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
4341 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
4343 2024-01-09 Tamar Christina <tamar.christina@arm.com>
4345 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
4346 restart_loop.
4347 (vectorizable_live_operation): Likewise.
4349 2024-01-09 Tamar Christina <tamar.christina@arm.com>
4351 PR tree-optimization/113199
4352 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
4353 BIT_FIELD_REF.
4355 2024-01-09 Jakub Jelinek <jakub@redhat.com>
4357 PR target/113270
4358 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
4359 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
4360 GTY(()) declaration before the definition, drop GTY(()) drom the
4361 definition.
4363 2024-01-09 Richard Biener <rguenther@suse.de>
4365 PR tree-optimization/113026
4366 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
4367 redundant and wrong niter bound setting. Move niter
4368 bound adjustment down.
4370 2024-01-09 Tamar Christina <tamar.christina@arm.com>
4372 PR middle-end/113163
4373 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
4374 Reject non-linear inductions that aren't supported.
4376 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
4378 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
4379 left shift implementation strategies.
4380 (arc_shift_info): Type for each entry of the shift strategy table.
4381 (arc_shift_context_idx): Return a integer value for each code
4382 generation context, used as an index
4383 (arc_ashl_alg): Table indexed by context and shifted bit count.
4384 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
4385 left shift implementation.
4386 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
4387 provide accurate costs, when optimizing for speed or size.
4389 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4391 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
4393 2024-01-09 Julian Brown <julian@codesourcery.com>
4395 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
4396 processed out before gimplification.
4397 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
4398 * tree.def (OMP_ARRAY_SECTION): New tree code.
4400 2024-01-09 Jakub Jelinek <jakub@redhat.com>
4402 PR tree-optimization/113210
4403 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
4404 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
4405 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
4406 minus 1.
4408 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
4410 PR rtl-optimization/113140
4411 * reorg.cc (fill_slots_from_thread): If we are to branch after the
4412 last instruction of the function, create an end label.
4414 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
4415 Hongtao Liu <hongtao.liu@intel.com>
4417 PR target/112992
4418 * config/i386/i386-expand.cc
4419 (ix86_convert_const_wide_int_to_broadcast): Allow call to
4420 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
4421 (ix86_broadcast_from_constant): Revert recent change; Return a
4422 suitable MEMREF independently of mode/target combinations.
4423 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
4424 to decide whether expansion is possible/preferrable. Only try
4425 forcing DImode constants to memory (and trying again) if calling
4426 ix86_expand_vector_init_duplicate fails with an DImode immediate
4427 constant.
4428 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
4429 V4SImode for suitable immediate constants.
4430 <case E_V4DImode>: Try using V8SImode for suitable constants.
4431 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
4432 <case E_V2HImode>: Likewise.
4433 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
4434 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
4435 <label widen>: Handle CONT_INTs via simplify_binary_operation.
4436 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
4437 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
4438 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
4439 (ix86_expand_vector_init): Move try using a broadcast for all_same
4440 with ix86_expand_vector_init_duplicate before using constant pool.
4442 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
4444 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
4446 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
4448 * config/arm/arm-cpus.in (cortex-m52): New cpu.
4449 * config/arm/arm-tables.opt: Regenerate.
4450 * config/arm/arm-tune.md: Regenerate.
4452 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
4454 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
4455 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
4456 (@vec_concatz<mode>): New insn pattern.
4457 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
4458 Handle VALS containing two vectors.
4460 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4462 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
4463 (vundefined): Ditto.
4465 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
4467 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
4468 Add new function_base for crypto vector.
4469 (class bitmanip): Ditto.
4470 (class b_reverse):Ditto.
4471 (class vwsll): Ditto.
4472 (class clmul): Ditto.
4473 (class vg_nhab): Ditto.
4474 (class crypto_vv):Ditto.
4475 (class crypto_vi):Ditto.
4476 (class vaeskf2_vsm3c):Ditto.
4477 (class vsm3me): Ditto.
4478 (BASE): Add BASE declaration for crypto vector.
4479 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
4480 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
4481 Add crypto vector intrinsic definition.
4482 (vbrev): Ditto.
4483 (vclz): Ditto.
4484 (vctz): Ditto.
4485 (vwsll): Ditto.
4486 (vandn): Ditto.
4487 (vbrev8): Ditto.
4488 (vrev8): Ditto.
4489 (vrol): Ditto.
4490 (vror): Ditto.
4491 (vclmul): Ditto.
4492 (vclmulh): Ditto.
4493 (vghsh): Ditto.
4494 (vgmul): Ditto.
4495 (vaesef): Ditto.
4496 (vaesem): Ditto.
4497 (vaesdf): Ditto.
4498 (vaesdm): Ditto.
4499 (vaesz): Ditto.
4500 (vaeskf1): Ditto.
4501 (vaeskf2): Ditto.
4502 (vsha2ms): Ditto.
4503 (vsha2ch): Ditto.
4504 (vsha2cl): Ditto.
4505 (vsm4k): Ditto.
4506 (vsm4r): Ditto.
4507 (vsm3me): Ditto.
4508 (vsm3c): Ditto.
4509 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
4510 Add new function_shape for crypto vector.
4511 (struct crypto_vi_def): Ditto.
4512 (struct crypto_vv_no_op_type_def): Ditto.
4513 (SHAPE): Add SHAPE declaration of crypto vector.
4514 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
4515 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
4516 Add new data type for crypto vector.
4517 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4518 (vuint32mf2_t): Ditto.
4519 (vuint32m1_t): Ditto.
4520 (vuint32m2_t): Ditto.
4521 (vuint32m4_t): Ditto.
4522 (vuint32m8_t): Ditto.
4523 (vuint64m1_t): Ditto.
4524 (vuint64m2_t): Ditto.
4525 (vuint64m4_t): Ditto.
4526 (vuint64m8_t): Ditto.
4527 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
4528 Add new data struct for crypto vector.
4529 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4530 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
4531 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
4533 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
4535 PR sanitizer/113251
4536 * varasm.cc (assemble_function_label_raw): Do not call
4537 asan_function_start () without the current function.
4539 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
4541 PR target/113225
4542 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
4543 extern and kernel_helper attributed function decls.
4545 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
4547 * btfout.cc (output_btf_strs): Changed.
4549 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
4551 * config/gcn/mkoffload.cc (main): Handle gfx1100
4552 when setting the default XNACK.
4554 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
4556 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
4557 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
4558 (ASM_SPEC): Handle gfx1100.
4559 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
4560 (enum gcn_isa): Add ISA_RDNA3.
4561 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
4562 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
4563 * config/gcn/gcn.cc (gcn_option_override,
4564 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
4565 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
4566 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
4567 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
4568 with gfx1100.
4569 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
4570 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
4571 __gfx1100__.
4572 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
4573 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
4574 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
4575 (isa_has_combined_avgprs, main): Handle gfx1100.
4576 * config/gcn/t-omp-device (isa): Add gfx1100.
4578 2024-01-08 Richard Biener <rguenther@suse.de>
4580 * doc/invoke.texi (-mmovbe): Clarify.
4582 2024-01-08 Richard Biener <rguenther@suse.de>
4584 PR tree-optimization/113026
4585 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
4586 Avoid an epilog in more cases.
4587 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
4588 epilogues niter upper bounds and estimates.
4590 2024-01-08 Jakub Jelinek <jakub@redhat.com>
4592 PR tree-optimization/113228
4593 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
4595 2024-01-08 Jakub Jelinek <jakub@redhat.com>
4597 PR tree-optimization/113120
4598 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
4599 large _BitInt zero INTEGER_CST PHI argument.
4601 2024-01-08 Jakub Jelinek <jakub@redhat.com>
4603 PR tree-optimization/113119
4604 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
4605 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
4606 is before REALPART_EXPR.
4608 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
4610 PR target/112952
4611 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
4612 range when diagnosing attribute "io" and "io_low" are out of range.
4613 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
4614 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
4615 in contexts other than static storage.
4616 (avr_asm_output_aligned_decl_common): Move output of decls with
4617 attribute "address", "io", and "io_low" to...
4618 (avr_output_addr_attrib): ...this new function.
4619 (avr_asm_asm_output_aligned_bss): Remove output for decls with
4620 attribute "address", "io", and "io_low".
4621 (avr_encode_section_info): Rectify handling of decls with attribute
4622 "address", "io", and "io_low".
4624 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
4626 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
4627 (elf_flags): Remove XNACK from the default value.
4628 (main): Set a default XNACK according to the arch.
4630 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
4632 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
4633 (process_asm): Don't count avgprs.
4635 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
4637 * config/i386/i386.opt: Add supported sub-features.
4638 * doc/extend.texi: Add description for target attribute.
4640 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
4642 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
4644 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
4645 Uros Bizjak <ubizjak@gmail.com>
4647 PR target/113231
4648 * config/i386/i386-features.cc (compute_convert_gain): Include
4649 the overhead of explicit load and store (movd) instructions when
4650 converting non-store scalar operations with memory destinations.
4651 Various indentation whitespace fixes.
4653 2024-01-07 Tamar Christina <tamar.christina@arm.com>
4655 * config/arm/neon.md (cbranch<mode>4): New.
4657 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4659 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
4661 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
4663 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
4665 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4667 PR target/113248
4668 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
4669 Update the MAX_SEW.
4671 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4673 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
4674 (variable_vectorized_p): Teach loop invariant.
4675 (has_unexpected_spills_p): Ditto.
4677 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4679 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
4680 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
4681 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
4683 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
4685 PR target/113104
4686 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
4687 (aarch64-vect-compare-costs): ...this.
4688 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
4689 Replace with...
4690 (-param=aarch64-vect-compare-costs=): ...this new param.
4691 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
4692 Don't disable it when vectorizing for Advanced SIMD only.
4693 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
4694 whenever aarch64_vect_compare_costs is true.
4696 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
4698 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
4699 Modify the method of determining the memory offset of [x]vld/[x]vst.
4700 (lasx_mxst_<lasxfmt_f>): Likewise.
4701 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
4702 (loongarch_address_insns): Likewise.
4703 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
4704 (lsx_st_<lsxfmt_f>): Likewise.
4705 * config/loongarch/predicates.md (aq10b_operand): Likewise.
4706 (aq10h_operand): Likewise.
4707 (aq10w_operand): Likewise.
4708 (aq10d_operand): Likewise.
4710 2024-01-05 Alex Coplan <alex.coplan@arm.com>
4712 PR target/113217
4713 * config/aarch64/aarch64-ldp-fusion.cc
4714 (ldp_bb_info::try_fuse_pair): If the second access can throw,
4715 narrow the move range to exactly that insn.
4717 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
4719 * asan.cc (asan_function_start): Drop switch_to_section ().
4720 (asan_emit_stack_protection): Set .LASANPC alignment.
4721 * config/i386/i386.cc: Use assemble_function_label_raw ()
4722 instead of ASM_OUTPUT_LABEL ().
4723 * config/s390/s390.cc (s390_asm_output_function_label):
4724 Likewise.
4725 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
4726 * final.cc (final_start_function_1): Drop
4727 asan_function_start ().
4728 * output.h (assemble_function_label_raw): New function.
4729 * varasm.cc (assemble_function_label_raw): Likewise.
4731 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
4733 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
4734 Use ASM_OUTPUT_FUNCTION_LABEL ().
4735 * config/alpha/alpha.cc (alpha_start_function): Likewise.
4736 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
4737 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
4738 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
4739 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
4740 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
4741 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
4742 * config/ia64/ia64.cc (ia64_start_function): Likewise.
4743 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
4744 Likewise.
4745 * config/microblaze/microblaze.cc (microblaze_function_prologue):
4746 Likewise.
4747 * config/mips/mips.cc (mips_start_unique_function): Return the
4748 tree.
4749 (mips_start_function_definition): Use
4750 ASM_OUTPUT_FUNCTION_LABEL ().
4751 (mips_finish_stub): Pass the tree to
4752 mips_start_function_definition ().
4753 (mips16_build_function_stub): Likewise.
4754 (mips16_build_call_stub): Likewise.
4755 (mips_output_function_prologue): Likewise.
4756 * config/pa/pa.cc (pa_output_function_label): Use
4757 ASM_OUTPUT_FUNCTION_LABEL ().
4758 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
4759 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
4760 Likewise.
4761 (rs6000_xcoff_declare_function_name): Likewise.
4763 2024-01-05 Jakub Jelinek <jakub@redhat.com>
4765 PR tree-optimization/113201
4766 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
4767 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
4769 2024-01-05 Jakub Jelinek <jakub@redhat.com>
4771 PR tree-optimization/90693
4772 * tree-ssa-math-opts.cc (match_single_bit_test): If
4773 tree_expr_nonzero_p (arg), remember it in the second argument to
4774 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
4775 arg ^ (arg - 1) > arg - 1.
4776 * internal-fn.cc (expand_POPCOUNT): If second argument to
4777 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
4778 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
4780 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
4782 * config/riscv/riscv-v.cc (expand_load_store):
4783 Remove `value`.
4784 (expand_cond_len_op): Ditto.
4785 (expand_gather_scatter): Ditto.
4786 (expand_lanes_load_store): Ditto.
4787 (expand_fold_extract_last): Ditto.
4789 2024-01-05 Pan Li <pan2.li@intel.com>
4791 Revert:
4792 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
4794 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
4795 Add new function_base for crypto vector.
4796 (class bitmanip): Ditto.
4797 (class b_reverse):Ditto.
4798 (class vwsll): Ditto.
4799 (class clmul): Ditto.
4800 (class vg_nhab): Ditto.
4801 (class crypto_vv):Ditto.
4802 (class crypto_vi):Ditto.
4803 (class vaeskf2_vsm3c):Ditto.
4804 (class vsm3me): Ditto.
4805 (BASE): Add BASE declaration for crypto vector.
4806 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
4807 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
4808 Add crypto vector intrinsic definition.
4809 (vbrev): Ditto.
4810 (vclz): Ditto.
4811 (vctz): Ditto.
4812 (vwsll): Ditto.
4813 (vandn): Ditto.
4814 (vbrev8): Ditto.
4815 (vrev8): Ditto.
4816 (vrol): Ditto.
4817 (vror): Ditto.
4818 (vclmul): Ditto.
4819 (vclmulh): Ditto.
4820 (vghsh): Ditto.
4821 (vgmul): Ditto.
4822 (vaesef): Ditto.
4823 (vaesem): Ditto.
4824 (vaesdf): Ditto.
4825 (vaesdm): Ditto.
4826 (vaesz): Ditto.
4827 (vaeskf1): Ditto.
4828 (vaeskf2): Ditto.
4829 (vsha2ms): Ditto.
4830 (vsha2ch): Ditto.
4831 (vsha2cl): Ditto.
4832 (vsm4k): Ditto.
4833 (vsm4r): Ditto.
4834 (vsm3me): Ditto.
4835 (vsm3c): Ditto.
4836 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
4837 Add new function_shape for crypto vector.
4838 (struct crypto_vi_def): Ditto.
4839 (struct crypto_vv_no_op_type_def): Ditto.
4840 (SHAPE): Add SHAPE declaration of crypto vector.
4841 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
4842 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
4843 Add new data type for crypto vector.
4844 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4845 (vuint32mf2_t): Ditto.
4846 (vuint32m1_t): Ditto.
4847 (vuint32m2_t): Ditto.
4848 (vuint32m4_t): Ditto.
4849 (vuint32m8_t): Ditto.
4850 (vuint64m1_t): Ditto.
4851 (vuint64m2_t): Ditto.
4852 (vuint64m4_t): Ditto.
4853 (vuint64m8_t): Ditto.
4854 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
4855 Add new data struct for crypto vector.
4856 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4857 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
4858 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
4860 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
4862 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
4863 Add new function_base for crypto vector.
4864 (class bitmanip): Ditto.
4865 (class b_reverse):Ditto.
4866 (class vwsll): Ditto.
4867 (class clmul): Ditto.
4868 (class vg_nhab): Ditto.
4869 (class crypto_vv):Ditto.
4870 (class crypto_vi):Ditto.
4871 (class vaeskf2_vsm3c):Ditto.
4872 (class vsm3me): Ditto.
4873 (BASE): Add BASE declaration for crypto vector.
4874 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
4875 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
4876 Add crypto vector intrinsic definition.
4877 (vbrev): Ditto.
4878 (vclz): Ditto.
4879 (vctz): Ditto.
4880 (vwsll): Ditto.
4881 (vandn): Ditto.
4882 (vbrev8): Ditto.
4883 (vrev8): Ditto.
4884 (vrol): Ditto.
4885 (vror): Ditto.
4886 (vclmul): Ditto.
4887 (vclmulh): Ditto.
4888 (vghsh): Ditto.
4889 (vgmul): Ditto.
4890 (vaesef): Ditto.
4891 (vaesem): Ditto.
4892 (vaesdf): Ditto.
4893 (vaesdm): Ditto.
4894 (vaesz): Ditto.
4895 (vaeskf1): Ditto.
4896 (vaeskf2): Ditto.
4897 (vsha2ms): Ditto.
4898 (vsha2ch): Ditto.
4899 (vsha2cl): Ditto.
4900 (vsm4k): Ditto.
4901 (vsm4r): Ditto.
4902 (vsm3me): Ditto.
4903 (vsm3c): Ditto.
4904 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
4905 Add new function_shape for crypto vector.
4906 (struct crypto_vi_def): Ditto.
4907 (struct crypto_vv_no_op_type_def): Ditto.
4908 (SHAPE): Add SHAPE declaration of crypto vector.
4909 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
4910 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
4911 Add new data type for crypto vector.
4912 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4913 (vuint32mf2_t): Ditto.
4914 (vuint32m1_t): Ditto.
4915 (vuint32m2_t): Ditto.
4916 (vuint32m4_t): Ditto.
4917 (vuint32m8_t): Ditto.
4918 (vuint64m1_t): Ditto.
4919 (vuint64m2_t): Ditto.
4920 (vuint64m4_t): Ditto.
4921 (vuint64m8_t): Ditto.
4922 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
4923 Add new data struct for crypto vector.
4924 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4925 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
4926 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
4928 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4930 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
4932 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
4934 PR tree-optimization/113186
4935 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
4936 Match `^` with the `==` for 1bit integral types.
4937 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
4938 integral types.
4940 2024-01-04 David Malcolm <dmalcolm@redhat.com>
4942 * toplev.cc (general_init): Pass lang_mask to urlifier.
4944 2024-01-04 David Malcolm <dmalcolm@redhat.com>
4946 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
4947 param.
4948 (diagnostic_context::make_option_url): Update for lang_mask param.
4949 * gcc-urlifier.cc: Include "opts.h" and "options.h".
4950 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
4951 (gcc_urlifier::m_lang_mask): New field.
4952 (doc_urls): Make static.
4953 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
4954 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
4955 Look for an option by name before trying a binary search in
4956 doc_urls.
4957 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
4958 (gcc_urlifier::get_url_suffix_for_option): New.
4959 (make_gcc_urlifier): Add lang_mask param.
4960 (selftest::gcc_urlifier_cc_tests): Update for above changes.
4961 Verify that a URL is found for "-fpack-struct".
4962 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
4963 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
4964 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
4965 to make_gcc_urlifier.
4966 * opts-diagnostic.h (get_option_url): Add lang_mask param.
4967 * opts.cc (get_option_html_page): Remove special-casing for
4968 analyzer and LTO.
4969 (get_option_url_suffix): New.
4970 (get_option_url): Reimplement.
4971 (selftest::test_get_option_html_page): Rename to...
4972 (selftest::test_get_option_url_suffix): ...this and update for
4973 above changes.
4974 (selftest::opts_cc_tests): Update for renaming.
4975 * opts.h: Include "rich-location.h".
4976 (get_option_url_suffix): New decl.
4978 2024-01-04 David Malcolm <dmalcolm@redhat.com>
4980 * Makefile.in (ALL_OPT_URL_FILES): New.
4981 (GCC_OBJS): Add options-urls.o.
4982 (OBJS): Likewise.
4983 (OBJS-libcommon): Likewise.
4984 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
4985 inputs to opt-gather.awk.
4986 (options-urls.cc): New Makefile target.
4987 * opt-functions.awk (url_suffix): New function.
4988 (lang_url_suffix): New function.
4989 * options-urls-cc-gen.awk: New file.
4990 * opts.h (get_opt_url_suffix): New decl.
4992 2024-01-04 David Malcolm <dmalcolm@redhat.com>
4994 * params.opt.urls: New file, autogenerated by
4995 regenerate-opt-urls.py.
4997 2024-01-04 David Malcolm <dmalcolm@redhat.com>
4999 * common.opt.urls: New file, autogenerated by
5000 regenerate-opt-urls.py.
5001 * config/aarch64/aarch64.opt.urls: Likewise.
5002 * config/alpha/alpha.opt.urls: Likewise.
5003 * config/alpha/elf.opt.urls: Likewise.
5004 * config/arc/arc-tables.opt.urls: Likewise.
5005 * config/arc/arc.opt.urls: Likewise.
5006 * config/arm/arm-tables.opt.urls: Likewise.
5007 * config/arm/arm.opt.urls: Likewise.
5008 * config/arm/vxworks.opt.urls: Likewise.
5009 * config/avr/avr.opt.urls: Likewise.
5010 * config/bpf/bpf.opt.urls: Likewise.
5011 * config/c6x/c6x-tables.opt.urls: Likewise.
5012 * config/c6x/c6x.opt.urls: Likewise.
5013 * config/cris/cris.opt.urls: Likewise.
5014 * config/cris/elf.opt.urls: Likewise.
5015 * config/csky/csky.opt.urls: Likewise.
5016 * config/csky/csky_tables.opt.urls: Likewise.
5017 * config/darwin.opt.urls: Likewise.
5018 * config/dragonfly.opt.urls: Likewise.
5019 * config/epiphany/epiphany.opt.urls: Likewise.
5020 * config/fr30/fr30.opt.urls: Likewise.
5021 * config/freebsd.opt.urls: Likewise.
5022 * config/frv/frv.opt.urls: Likewise.
5023 * config/ft32/ft32.opt.urls: Likewise.
5024 * config/fused-madd.opt.urls: Likewise.
5025 * config/g.opt.urls: Likewise.
5026 * config/gcn/gcn.opt.urls: Likewise.
5027 * config/gnu-user.opt.urls: Likewise.
5028 * config/h8300/h8300.opt.urls: Likewise.
5029 * config/hpux11.opt.urls: Likewise.
5030 * config/i386/cygming.opt.urls: Likewise.
5031 * config/i386/cygwin.opt.urls: Likewise.
5032 * config/i386/djgpp.opt.urls: Likewise.
5033 * config/i386/i386.opt.urls: Likewise.
5034 * config/i386/mingw-w64.opt.urls: Likewise.
5035 * config/i386/mingw.opt.urls: Likewise.
5036 * config/i386/nto.opt.urls: Likewise.
5037 * config/ia64/ia64.opt.urls: Likewise.
5038 * config/ia64/ilp32.opt.urls: Likewise.
5039 * config/ia64/vms.opt.urls: Likewise.
5040 * config/iq2000/iq2000.opt.urls: Likewise.
5041 * config/linux-android.opt.urls: Likewise.
5042 * config/linux.opt.urls: Likewise.
5043 * config/lm32/lm32.opt.urls: Likewise.
5044 * config/loongarch/loongarch.opt.urls: Likewise.
5045 * config/lynx.opt.urls: Likewise.
5046 * config/m32c/m32c.opt.urls: Likewise.
5047 * config/m32r/m32r.opt.urls: Likewise.
5048 * config/m68k/ieee.opt.urls: Likewise.
5049 * config/m68k/m68k-tables.opt.urls: Likewise.
5050 * config/m68k/m68k.opt.urls: Likewise.
5051 * config/m68k/uclinux.opt.urls: Likewise.
5052 * config/mcore/mcore.opt.urls: Likewise.
5053 * config/microblaze/microblaze.opt.urls: Likewise.
5054 * config/mips/mips-tables.opt.urls: Likewise.
5055 * config/mips/mips.opt.urls: Likewise.
5056 * config/mips/sde.opt.urls: Likewise.
5057 * config/mmix/mmix.opt.urls: Likewise.
5058 * config/mn10300/mn10300.opt.urls: Likewise.
5059 * config/moxie/moxie.opt.urls: Likewise.
5060 * config/msp430/msp430.opt.urls: Likewise.
5061 * config/nds32/nds32-elf.opt.urls: Likewise.
5062 * config/nds32/nds32-linux.opt.urls: Likewise.
5063 * config/nds32/nds32.opt.urls: Likewise.
5064 * config/netbsd-elf.opt.urls: Likewise.
5065 * config/netbsd.opt.urls: Likewise.
5066 * config/nios2/elf.opt.urls: Likewise.
5067 * config/nios2/nios2.opt.urls: Likewise.
5068 * config/nvptx/nvptx-gen.opt.urls: Likewise.
5069 * config/nvptx/nvptx.opt.urls: Likewise.
5070 * config/openbsd.opt.urls: Likewise.
5071 * config/or1k/elf.opt.urls: Likewise.
5072 * config/or1k/or1k.opt.urls: Likewise.
5073 * config/pa/pa-hpux.opt.urls: Likewise.
5074 * config/pa/pa-hpux1010.opt.urls: Likewise.
5075 * config/pa/pa-hpux1111.opt.urls: Likewise.
5076 * config/pa/pa-hpux1131.opt.urls: Likewise.
5077 * config/pa/pa.opt.urls: Likewise.
5078 * config/pa/pa64-hpux.opt.urls: Likewise.
5079 * config/pdp11/pdp11.opt.urls: Likewise.
5080 * config/pru/pru.opt.urls: Likewise.
5081 * config/riscv/riscv.opt.urls: Likewise.
5082 * config/rl78/rl78.opt.urls: Likewise.
5083 * config/rpath.opt.urls: Likewise.
5084 * config/rs6000/476.opt.urls: Likewise.
5085 * config/rs6000/aix64.opt.urls: Likewise.
5086 * config/rs6000/darwin.opt.urls: Likewise.
5087 * config/rs6000/linux64.opt.urls: Likewise.
5088 * config/rs6000/rs6000-tables.opt.urls: Likewise.
5089 * config/rs6000/rs6000.opt.urls: Likewise.
5090 * config/rs6000/sysv4.opt.urls: Likewise.
5091 * config/rtems.opt.urls: Likewise.
5092 * config/rx/elf.opt.urls: Likewise.
5093 * config/rx/rx.opt.urls: Likewise.
5094 * config/s390/s390.opt.urls: Likewise.
5095 * config/s390/tpf.opt.urls: Likewise.
5096 * config/sh/sh.opt.urls: Likewise.
5097 * config/sh/superh.opt.urls: Likewise.
5098 * config/sol2.opt.urls: Likewise.
5099 * config/sparc/long-double-switch.opt.urls: Likewise.
5100 * config/sparc/sparc.opt.urls: Likewise.
5101 * config/stormy16/stormy16.opt.urls: Likewise.
5102 * config/v850/v850.opt.urls: Likewise.
5103 * config/vax/elf.opt.urls: Likewise.
5104 * config/vax/vax.opt.urls: Likewise.
5105 * config/visium/visium.opt.urls: Likewise.
5106 * config/vms/vms.opt.urls: Likewise.
5107 * config/vxworks-smp.opt.urls: Likewise.
5108 * config/vxworks.opt.urls: Likewise.
5109 * config/xtensa/elf.opt.urls: Likewise.
5110 * config/xtensa/uclinux.opt.urls: Likewise.
5111 * config/xtensa/xtensa.opt.urls: Likewise.
5112 * config/bfin/bfin.opt.urls: New file.
5114 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5116 * Makefile.in (OPT_URLS_HTML_DEPS): New.
5117 (regenerate-opt-urls): New target.
5118 (regenerate-opt-urls-unit-test): New target.
5119 * doc/options.texi (Option properties): Add UrlSuffix and
5120 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
5121 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
5122 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
5123 and Makefile.in's OPT_URLS_HTML_DEPS.
5124 (Anatomy of a Target Back End): Add
5125 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
5126 * regenerate-opt-urls.py: New file.
5128 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5130 * diagnostic-format-sarif.cc
5131 (sarif_builder::make_logical_location_object): Convert to...
5132 (make_sarif_logical_location_object): ...this.
5133 (sarif_builder::set_any_logical_locs_arr): Update for above
5134 change.
5135 (sarif_builder::make_thread_flow_location_object): Call
5136 maybe_add_sarif_properties on each diagnostic_event.
5137 * diagnostic-format-sarif.h (class logical_location): New forward
5138 decl.
5139 (make_sarif_logical_location_object): New decl.
5140 * diagnostic-path.h (class sarif_object): New forward decl.
5141 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
5143 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
5144 Patrick Lin <patrick@andestech.com>
5145 Rufus Chen <rufus@andestech.com>
5146 Monk Chiang <monk.chiang@sifive.com>
5148 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
5149 with Nan-boxing value.
5150 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
5152 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
5153 Jeff Law <jlaw@ventanamicro.com>
5155 PR rtl-optimization/104914
5156 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
5157 a sign or zero extension is only required if the modified field
5158 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
5159 targets, don't refer to the temporarily incorrectly extended value
5160 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
5162 2024-01-04 Pan Li <pan2.li@intel.com>
5164 Revert:
5165 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5167 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
5169 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5171 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
5173 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
5175 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
5176 offset of fcsr.
5178 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5180 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
5181 (compute_nregs_for_mode): Refine LMUL.
5182 (max_number_of_live_regs): Ditto.
5183 (compute_estimated_lmul): Ditto.
5184 (has_unexpected_spills_p): Ditto.
5186 2024-01-04 Li Wei <liwei@loongson.cn>
5188 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
5189 Remove useless forward declaration.
5190 (loongarch_is_even_extraction): Remove useless forward declaration.
5191 (loongarch_try_expand_lsx_vshuf_const): Removed.
5192 (loongarch_expand_vec_perm_const_1): Merged.
5193 (loongarch_is_double_duplicate): Removed.
5194 (loongarch_is_center_extraction): Ditto.
5195 (loongarch_is_reversing_permutation): Ditto.
5196 (loongarch_is_di_misalign_extract): Ditto.
5197 (loongarch_is_si_misalign_extract): Ditto.
5198 (loongarch_is_lasx_lowpart_extract): Ditto.
5199 (loongarch_is_op_reverse_perm): Ditto.
5200 (loongarch_is_single_op_perm): Ditto.
5201 (loongarch_is_divisible_perm): Ditto.
5202 (loongarch_is_triple_stride_extract): Ditto.
5203 (loongarch_expand_vec_perm_const_2): Merged.
5204 (loongarch_expand_vec_perm_const): New.
5205 (loongarch_vectorize_vec_perm_const): Adjust.
5207 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
5209 * omp-general.cc: Fix comment typos and misplaced/confusing
5210 comments. Delete redundant include of omp-general.h.
5212 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
5214 PR rtl-optimization/104914
5215 * config/mips/mips.md (insqisi_extended): New patterns.
5216 (inshisi_extended): Ditto.
5218 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
5220 * config/mips/mips.cc (mips_insn_cost): New function.
5222 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
5224 * config/mips/mips.md (perf_ratio): New attribute.
5226 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5228 PR target/113206
5229 PR target/113209
5230 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
5231 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
5232 blocks belong to infinite loop.
5233 (pre_vsetvl::emit_vsetvl): Remove fake edges.
5234 * config/riscv/t-riscv: Add a new include file.
5236 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5238 * config/riscv/vector.md: Fix indent.
5240 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
5242 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
5243 OMP_CLAUSE__SIMDUID_.
5244 * tree.cc (omp_clause_num_ops): Update position of entry for
5245 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
5246 (omp_clause_code_name): Likewise.
5248 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
5250 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
5251 printing of FUNC_MAP/IND_FUNC_MAP labels.
5253 2024-01-03 Jakub Jelinek <jakub@redhat.com>
5255 * gcc.cc (process_command): Update copyright notice dates.
5256 * gcov-dump.cc (print_version): Ditto.
5257 * gcov.cc (print_version): Ditto.
5258 * gcov-tool.cc (print_version): Ditto.
5259 * gengtype.cc (create_file): Ditto.
5260 * doc/cpp.texi: Bump @copying's copyright year.
5261 * doc/cppinternals.texi: Ditto.
5262 * doc/gcc.texi: Ditto.
5263 * doc/gccint.texi: Ditto.
5264 * doc/gcov.texi: Ditto.
5265 * doc/install.texi: Ditto.
5266 * doc/invoke.texi: Ditto.
5268 2024-01-03 Xi Ruoyao <xry111@xry111.site>
5270 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
5271 (fmin<mode>3): Likewise.
5272 (reduc_fmax_scal_<mode>3): New define_expand.
5273 (reduc_fmin_scal_<mode>3): Likewise.
5275 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5277 PR target/113112
5278 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
5279 (max_number_of_live_regs): Ditto.
5280 (has_unexpected_spills_p): Ditto.
5282 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5283 Jin Ma <jinma@linux.alibaba.com>
5284 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5285 Christoph Müllner <christoph.muellner@vrull.eu>
5287 * config/riscv/vector.md:
5288 Use vector_length_operand for vsetvl patterns.
5290 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5292 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
5293 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
5295 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
5297 * config/aarch64/aarch64-tuning-flags.def
5298 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
5299 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
5300 * config/aarch64/aarch64.cc
5301 (aarch64_override_options_internal): Set
5302 param_fully_pipelined_fma according to tuning option.
5303 * config/aarch64/tuning_models/ampere1.h: Add
5304 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
5305 * config/aarch64/tuning_models/ampere1a.h: Likewise.
5306 * config/aarch64/tuning_models/ampere1b.h: Likewise.
5308 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
5310 * config/riscv/vector-crypto.md: Modify copyright year.
5312 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5314 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
5316 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
5318 * config.in: Regenerate.
5319 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
5320 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
5321 Added TLS Le Relax support.
5322 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
5323 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
5324 * configure: Regenerate.
5325 * configure.ac: Check if binutils supports TLS le relax.
5327 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
5329 * config/riscv/iterators.md: Add rotate insn name.
5330 * config/riscv/riscv.md: Add new insns name for crypto vector.
5331 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
5332 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
5333 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
5335 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5337 PR target/113112
5338 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
5339 pointer type liveness count.
5340 \f
5341 Copyright (C) 2024 Free Software Foundation, Inc.
5343 Copying and distribution of this file, with or without modification,
5344 are permitted in any medium without royalty provided the copyright
5345 notice and this notice are preserved.