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* config/sh/sh.h: Delete dead GO_IF_LEGITIMATE_INDEX macro.
[official-gcc.git] / gcc / config / sh / sh.h
blob7a8b23eac16570bfb0635840a94e7d84fba7de1e
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com).
6 Improved by Jim Wilson (wilson@cygnus.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #include "config/vxworks-dummy.h"
28
29 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
30 include it here, because bconfig.h is also included by gencodes.c . */
31 /* ??? No longer true. */
32 extern int code_for_indirect_jump_scratch;
33
34 #define TARGET_CPU_CPP_BUILTINS() \
35 do { \
36 builtin_define ("__sh__"); \
37 builtin_assert ("cpu=sh"); \
38 builtin_assert ("machine=sh"); \
39 switch ((int) sh_cpu) \
40 { \
41 case PROCESSOR_SH1: \
42 builtin_define ("__sh1__"); \
43 break; \
44 case PROCESSOR_SH2: \
45 builtin_define ("__sh2__"); \
46 break; \
47 case PROCESSOR_SH2E: \
48 builtin_define ("__SH2E__"); \
49 break; \
50 case PROCESSOR_SH2A: \
51 builtin_define ("__SH2A__"); \
52 builtin_define (TARGET_SH2A_DOUBLE \
53 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
54 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
55 : "__SH2A_NOFPU__"); \
56 break; \
57 case PROCESSOR_SH3: \
58 builtin_define ("__sh3__"); \
59 builtin_define ("__SH3__"); \
60 if (TARGET_HARD_SH4) \
61 builtin_define ("__SH4_NOFPU__"); \
62 break; \
63 case PROCESSOR_SH3E: \
64 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
65 break; \
66 case PROCESSOR_SH4: \
67 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
68 break; \
69 case PROCESSOR_SH4A: \
70 builtin_define ("__SH4A__"); \
71 builtin_define (TARGET_SH4 \
72 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
73 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
74 : "__SH4_NOFPU__"); \
75 break; \
76 case PROCESSOR_SH5: \
77 { \
78 builtin_define_with_value ("__SH5__", \
79 TARGET_SHMEDIA64 ? "64" : "32", 0); \
80 builtin_define_with_value ("__SHMEDIA__", \
81 TARGET_SHMEDIA ? "1" : "0", 0); \
82 if (! TARGET_FPU_DOUBLE) \
83 builtin_define ("__SH4_NOFPU__"); \
84 } \
85 } \
86 if (TARGET_FPU_ANY) \
87 builtin_define ("__SH_FPU_ANY__"); \
88 if (TARGET_FPU_DOUBLE) \
89 builtin_define ("__SH_FPU_DOUBLE__"); \
90 if (TARGET_HITACHI) \
91 builtin_define ("__HITACHI__"); \
92 if (TARGET_FMOVD) \
93 builtin_define ("__FMOVD_ENABLED__"); \
94 builtin_define (TARGET_LITTLE_ENDIAN \
95 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
96 } while (0)
97
98 /* Value should be nonzero if functions must have frame pointers.
99 Zero means the frame pointer need not be set up (and parms may be accessed
100 via the stack pointer) in functions that seem suitable. */
101
102 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
103 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
104 #endif
105
106 \f
107 /* Nonzero if this is an ELF target - compile time only */
108 #define TARGET_ELF 0
109
110 /* Nonzero if we should generate code using type 2E insns. */
111 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
112
113 /* Nonzero if we should generate code using type 2A insns. */
114 #define TARGET_SH2A TARGET_HARD_SH2A
115 /* Nonzero if we should generate code using type 2A SF insns. */
116 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
117 /* Nonzero if we should generate code using type 2A DF insns. */
118 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
119
120 /* Nonzero if we should generate code using type 3E insns. */
121 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
122
123 /* Nonzero if the cache line size is 32. */
124 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
125
126 /* Nonzero if we schedule for a superscalar implementation. */
127 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
128
129 /* Nonzero if the target has separate instruction and data caches. */
130 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
131
132 /* Nonzero if a double-precision FPU is available. */
133 #define TARGET_FPU_DOUBLE \
134 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
135
136 /* Nonzero if an FPU is available. */
137 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
138
139 /* Nonzero if we should generate code using type 4 insns. */
140 #undef TARGET_SH4
141 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
142
143 /* Nonzero if we're generating code for the common subset of
144 instructions present on both SH4a and SH4al-dsp. */
145 #define TARGET_SH4A_ARCH TARGET_SH4A
146
147 /* Nonzero if we're generating code for SH4a, unless the use of the
148 FPU is disabled (which makes it compatible with SH4al-dsp). */
149 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
150
151 /* Nonzero if we should generate code using the SHcompact instruction
152 set and 32-bit ABI. */
153 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
154
155 /* Nonzero if we should generate code using the SHmedia instruction
156 set and ABI. */
157 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
158
159 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
160 ABI. */
161 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
162
163 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
164 ABI. */
165 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
166
167 /* Nonzero if we should generate code using SHmedia FPU instructions. */
168 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
169
170 /* This is not used by the SH2E calling convention */
171 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
172 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
173 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
174
175 #ifndef TARGET_CPU_DEFAULT
176 #define TARGET_CPU_DEFAULT SELECT_SH1
177 #define SUPPORT_SH1 1
178 #define SUPPORT_SH2E 1
179 #define SUPPORT_SH4 1
180 #define SUPPORT_SH4_SINGLE 1
181 #define SUPPORT_SH2A 1
182 #define SUPPORT_SH2A_SINGLE 1
183 #endif
184
185 #define TARGET_DIVIDE_INV \
186 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
187 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
188 || sh_div_strategy == SH_DIV_INV_CALL \
189 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
190 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
191 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
192 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
193 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
194 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
195 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
196 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
197 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
198 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
199 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
200 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
201
202 #define SELECT_SH1 (MASK_SH1)
203 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
204 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
205 | MASK_FPU_SINGLE)
206 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
207 | MASK_HARD_SH2A_DOUBLE \
208 | MASK_SH2 | MASK_SH1)
209 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
210 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
211 | MASK_SH1 | MASK_FPU_SINGLE)
212 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
213 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
214 | MASK_SH2 | MASK_SH1)
215 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
216 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
217 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
218 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
219 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
220 | SELECT_SH3)
221 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
222 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
223 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
224 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
225 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
226 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
227 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
228 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
229 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
230 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
231 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
232
233 #if SUPPORT_SH1
234 #define SUPPORT_SH2 1
235 #endif
236 #if SUPPORT_SH2
237 #define SUPPORT_SH3 1
238 #define SUPPORT_SH2A_NOFPU 1
239 #endif
240 #if SUPPORT_SH3
241 #define SUPPORT_SH4_NOFPU 1
242 #endif
243 #if SUPPORT_SH4_NOFPU
244 #define SUPPORT_SH4A_NOFPU 1
245 #define SUPPORT_SH4AL 1
246 #endif
247
248 #if SUPPORT_SH2E
249 #define SUPPORT_SH3E 1
250 #define SUPPORT_SH2A_SINGLE_ONLY 1
251 #endif
252 #if SUPPORT_SH3E
253 #define SUPPORT_SH4_SINGLE_ONLY 1
254 #endif
255 #if SUPPORT_SH4_SINGLE_ONLY
256 #define SUPPORT_SH4A_SINGLE_ONLY 1
257 #endif
258
259 #if SUPPORT_SH4
260 #define SUPPORT_SH4A 1
261 #endif
262
263 #if SUPPORT_SH4_SINGLE
264 #define SUPPORT_SH4A_SINGLE 1
265 #endif
266
267 #if SUPPORT_SH5_COMPAT
268 #define SUPPORT_SH5_32MEDIA 1
269 #endif
270
271 #if SUPPORT_SH5_COMPACT_NOFPU
272 #define SUPPORT_SH5_32MEDIA_NOFPU 1
273 #endif
274
275 #define SUPPORT_ANY_SH5_32MEDIA \
276 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
277 #define SUPPORT_ANY_SH5_64MEDIA \
278 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
279 #define SUPPORT_ANY_SH5 \
280 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
281
282 /* Reset all target-selection flags. */
283 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
284 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
285 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
286
287 /* This defaults us to big-endian. */
288 #ifndef TARGET_ENDIAN_DEFAULT
289 #define TARGET_ENDIAN_DEFAULT 0
290 #endif
291
292 #ifndef TARGET_OPT_DEFAULT
293 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
294 #endif
295
296 #define TARGET_DEFAULT \
297 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
298
299 #ifndef SH_MULTILIB_CPU_DEFAULT
300 #define SH_MULTILIB_CPU_DEFAULT "m1"
301 #endif
302
303 #if TARGET_ENDIAN_DEFAULT
304 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
305 #else
306 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
307 #endif
308
309 #define CPP_SPEC " %(subtarget_cpp_spec) "
310
311 #ifndef SUBTARGET_CPP_SPEC
312 #define SUBTARGET_CPP_SPEC ""
313 #endif
314
315 #ifndef SUBTARGET_EXTRA_SPECS
316 #define SUBTARGET_EXTRA_SPECS
317 #endif
318
319 #define EXTRA_SPECS \
320 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
321 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
322 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
323 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
324 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
325 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
326 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
327 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
328 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
329 SUBTARGET_EXTRA_SPECS
330
331 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
332 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
333 #else
334 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
335 #endif
336
337 #define SH_ASM_SPEC \
338 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
339 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
340 %{m2a:--isa=sh2a} \
341 %{m2a-single:--isa=sh2a} \
342 %{m2a-single-only:--isa=sh2a} \
343 %{m2a-nofpu:--isa=sh2a-nofpu} \
344 %{m5-compact*:--isa=SHcompact} \
345 %{m5-32media*:--isa=SHmedia --abi=32} \
346 %{m5-64media*:--isa=SHmedia --abi=64} \
347 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
348
349 #define ASM_SPEC SH_ASM_SPEC
350
351 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
352 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
353 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
354 #else
355 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
356 #endif
357 #endif
358
359 #if STRICT_NOFPU == 1
360 /* Strict nofpu means that the compiler should tell the assembler
361 to reject FPU instructions. E.g. from ASM inserts. */
362 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
363 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
364 #else
365 /* If there were an -isa option for sh5-nofpu then it would also go here. */
366 #define SUBTARGET_ASM_ISA_SPEC \
367 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
368 #endif
369 #else /* ! STRICT_NOFPU */
370 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
371 #endif
372
373 #ifndef SUBTARGET_ASM_SPEC
374 #define SUBTARGET_ASM_SPEC ""
375 #endif
376
377 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
378 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
379 #else
380 #define LINK_EMUL_PREFIX "sh%{ml:l}"
381 #endif
382
383 #if TARGET_CPU_DEFAULT & MASK_SH5
384 #if TARGET_CPU_DEFAULT & MASK_SH_E
385 #define LINK_DEFAULT_CPU_EMUL "32"
386 #if TARGET_CPU_DEFAULT & MASK_SH1
387 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
388 #else
389 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
390 #endif /* MASK_SH1 */
391 #else /* !MASK_SH_E */
392 #define LINK_DEFAULT_CPU_EMUL "64"
393 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
394 #endif /* MASK_SH_E */
395 #define ASM_ISA_DEFAULT_SPEC \
396 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
397 #else /* !MASK_SH5 */
398 #define LINK_DEFAULT_CPU_EMUL ""
399 #define ASM_ISA_DEFAULT_SPEC ""
400 #endif /* MASK_SH5 */
401
402 #define SUBTARGET_LINK_EMUL_SUFFIX ""
403 #define SUBTARGET_LINK_SPEC ""
404
405 /* Go via SH_LINK_SPEC to avoid code replication. */
406 #define LINK_SPEC SH_LINK_SPEC
407
408 #define SH_LINK_SPEC "\
409 -m %(link_emul_prefix)\
410 %{m5-compact*|m5-32media*:32}\
411 %{m5-64media*:64}\
412 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
413 %(subtarget_link_emul_suffix) \
414 %{mrelax:-relax} %(subtarget_link_spec)"
415
416 #ifndef SH_DIV_STR_FOR_SIZE
417 #define SH_DIV_STR_FOR_SIZE "call"
418 #endif
419
420 /* SH2A does not support little-endian. Catch such combinations
421 taking into account the default configuration. */
422 #if TARGET_ENDIAN_DEFAULT == MASK_BIG_ENDIAN
423 #define IS_LITTLE_ENDIAN_OPTION "%{ml:"
424 #else
425 #define IS_LITTLE_ENDIAN_OPTION "%{!mb:"
426 #endif
427
428 #if TARGET_CPU_DEFAULT & MASK_HARD_SH2A
429 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
430 "%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:{!m5*:%eSH2a does not support little-endian}}}}}}"
431 #else
432 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
433 "%{m2a*:%eSH2a does not support little-endian}}"
434 #endif
435
436 #define DRIVER_SELF_SPECS UNSUPPORTED_SH2A
437
438 #define ASSEMBLER_DIALECT assembler_dialect
439
440 extern int assembler_dialect;
441
442 enum sh_divide_strategy_e {
443 /* SH5 strategies. */
444 SH_DIV_CALL,
445 SH_DIV_CALL2,
446 SH_DIV_FP, /* We could do this also for SH4. */
447 SH_DIV_INV,
448 SH_DIV_INV_MINLAT,
449 SH_DIV_INV20U,
450 SH_DIV_INV20L,
451 SH_DIV_INV_CALL,
452 SH_DIV_INV_CALL2,
453 SH_DIV_INV_FP,
454 /* SH1 .. SH4 strategies. Because of the small number of registers
455 available, the compiler uses knowledge of the actual set of registers
456 being clobbered by the different functions called. */
457 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
458 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
459 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
460 SH_DIV_INTRINSIC
461 };
462
463 extern enum sh_divide_strategy_e sh_div_strategy;
464
465 #ifndef SH_DIV_STRATEGY_DEFAULT
466 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
467 #endif
468
469 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
470
471 \f
472 /* Target machine storage layout. */
473
474 /* Define this if most significant bit is lowest numbered
475 in instructions that operate on numbered bit-fields. */
476
477 #define BITS_BIG_ENDIAN 0
478
479 /* Define this if most significant byte of a word is the lowest numbered. */
480 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
481
482 /* Define this if most significant word of a multiword number is the lowest
483 numbered. */
484 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
485
486 #define MAX_BITS_PER_WORD 64
487
488 /* Width in bits of an `int'. We want just 32-bits, even if words are
489 longer. */
490 #define INT_TYPE_SIZE 32
491
492 /* Width in bits of a `long'. */
493 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
494
495 /* Width in bits of a `long long'. */
496 #define LONG_LONG_TYPE_SIZE 64
497
498 /* Width in bits of a `long double'. */
499 #define LONG_DOUBLE_TYPE_SIZE 64
500
501 /* Width of a word, in units (bytes). */
502 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
503 #define MIN_UNITS_PER_WORD 4
504
505 /* Scaling factor for Dwarf data offsets for CFI information.
506 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
507 SHmedia; however, since we do partial register saves for the registers
508 visible to SHcompact, and for target registers for SHMEDIA32, we have
509 to allow saves that are only 4-byte aligned. */
510 #define DWARF_CIE_DATA_ALIGNMENT -4
511
512 /* Width in bits of a pointer.
513 See also the macro `Pmode' defined below. */
514 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
515
516 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
517 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
518
519 /* Boundary (in *bits*) on which stack pointer should be aligned. */
520 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
521
522 /* The log (base 2) of the cache line size, in bytes. Processors prior to
523 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
524 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
525 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
526
527 /* ABI given & required minimum allocation boundary (in *bits*) for the
528 code of a function. */
529 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
530
531 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
532 the vbit must go into the delta field of
533 pointers-to-member-functions. */
534 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
535 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
536
537 /* Alignment of field after `int : 0' in a structure. */
538 #define EMPTY_FIELD_BOUNDARY 32
539
540 /* No data type wants to be aligned rounder than this. */
541 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
542
543 /* The best alignment to use in cases where we have a choice. */
544 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
545
546 /* Make strings word-aligned so strcpy from constants will be faster. */
547 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
548 ((TREE_CODE (EXP) == STRING_CST \
549 && (ALIGN) < FASTEST_ALIGNMENT) \
550 ? FASTEST_ALIGNMENT : (ALIGN))
551
552 /* get_mode_alignment assumes complex values are always held in multiple
553 registers, but that is not the case on the SH; CQImode and CHImode are
554 held in a single integer register. SH5 also holds CSImode and SCmode
555 values in integer registers. This is relevant for argument passing on
556 SHcompact as we use a stack temp in order to pass CSImode by reference. */
557 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
558 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
559 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
560 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
561 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
562
563 /* Make arrays of chars word-aligned for the same reasons. */
564 #define DATA_ALIGNMENT(TYPE, ALIGN) \
565 (TREE_CODE (TYPE) == ARRAY_TYPE \
566 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
567 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
568
569 /* Number of bits which any structure or union's size must be a
570 multiple of. Each structure or union's size is rounded up to a
571 multiple of this. */
572 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
573
574 /* Set this nonzero if move instructions will actually fail to work
575 when given unaligned data. */
576 #define STRICT_ALIGNMENT 1
577
578 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
579 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
580 barrier_align (LABEL_AFTER_BARRIER)
581
582 #define LOOP_ALIGN(A_LABEL) \
583 ((! optimize || TARGET_HARD_SH4 || optimize_size) \
584 ? 0 : sh_loop_align (A_LABEL))
585
586 #define LABEL_ALIGN(A_LABEL) \
587 ( \
588 (PREV_INSN (A_LABEL) \
589 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
590 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
591 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
592 /* explicit alignment insn in constant tables. */ \
593 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
594 : 0)
595
596 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
597 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
598
599 /* The base two logarithm of the known minimum alignment of an insn length. */
600 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
601 (NONJUMP_INSN_P (A_INSN) \
602 ? 1 << TARGET_SHMEDIA \
603 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
604 ? 1 << TARGET_SHMEDIA \
605 : CACHE_LOG)
606 \f
607 /* Standard register usage. */
608
609 /* Register allocation for the Renesas calling convention:
610
611 r0 arg return
612 r1..r3 scratch
613 r4..r7 args in
614 r8..r13 call saved
615 r14 frame pointer/call saved
616 r15 stack pointer
617 ap arg pointer (doesn't really exist, always eliminated)
618 pr subroutine return address
619 t t bit
620 mach multiply/accumulate result, high part
621 macl multiply/accumulate result, low part.
622 fpul fp/int communication register
623 rap return address pointer register
624 fr0 fp arg return
625 fr1..fr3 scratch floating point registers
626 fr4..fr11 fp args in
627 fr12..fr15 call saved floating point registers */
628
629 #define MAX_REGISTER_NAME_LENGTH 5
630 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
631
632 #define SH_REGISTER_NAMES_INITIALIZER \
633 { \
634 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
635 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
636 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
637 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
638 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
639 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
640 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
641 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
642 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
643 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
644 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
645 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
646 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
647 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
648 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
649 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
650 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
651 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
652 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
653 "rap", "sfp" \
654 }
655
656 #define REGNAMES_ARR_INDEX_1(index) \
657 (sh_register_names[index])
658 #define REGNAMES_ARR_INDEX_2(index) \
659 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
660 #define REGNAMES_ARR_INDEX_4(index) \
661 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
662 #define REGNAMES_ARR_INDEX_8(index) \
663 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
664 #define REGNAMES_ARR_INDEX_16(index) \
665 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
666 #define REGNAMES_ARR_INDEX_32(index) \
667 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
668 #define REGNAMES_ARR_INDEX_64(index) \
669 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
670
671 #define REGISTER_NAMES \
672 { \
673 REGNAMES_ARR_INDEX_64 (0), \
674 REGNAMES_ARR_INDEX_64 (64), \
675 REGNAMES_ARR_INDEX_8 (128), \
676 REGNAMES_ARR_INDEX_8 (136), \
677 REGNAMES_ARR_INDEX_8 (144), \
678 REGNAMES_ARR_INDEX_2 (152) \
679 }
680
681 #define ADDREGNAMES_SIZE 32
682 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
683 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
684 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
685
686 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
687 { \
688 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
689 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
690 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
691 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
692 }
693
694 #define ADDREGNAMES_REGNO(index) \
695 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
696 : (-1))
697
698 #define ADDREGNAMES_ARR_INDEX_1(index) \
699 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
700 #define ADDREGNAMES_ARR_INDEX_2(index) \
701 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
702 #define ADDREGNAMES_ARR_INDEX_4(index) \
703 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
704 #define ADDREGNAMES_ARR_INDEX_8(index) \
705 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
706 #define ADDREGNAMES_ARR_INDEX_16(index) \
707 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
708 #define ADDREGNAMES_ARR_INDEX_32(index) \
709 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
710
711 #define ADDITIONAL_REGISTER_NAMES \
712 { \
713 ADDREGNAMES_ARR_INDEX_32 (0) \
714 }
715
716 /* Number of actual hardware registers.
717 The hardware registers are assigned numbers for the compiler
718 from 0 to just below FIRST_PSEUDO_REGISTER.
719 All registers that the compiler knows about must be given numbers,
720 even those that are not normally considered general registers. */
721
722 /* There are many other relevant definitions in sh.md's md_constants. */
723
724 #define FIRST_GENERAL_REG R0_REG
725 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
726 #define FIRST_FP_REG DR0_REG
727 #define LAST_FP_REG (FIRST_FP_REG + \
728 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
729 #define FIRST_XD_REG XD0_REG
730 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
731 #define FIRST_TARGET_REG TR0_REG
732 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
733
734 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
735
736 #define FIRST_BANKED_REG R0_REG
737 #define LAST_BANKED_REG R7_REG
738
739 #define BANKED_REGISTER_P(REGNO) \
740 IN_RANGE ((REGNO), \
741 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
742 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
743
744 #define GENERAL_REGISTER_P(REGNO) \
745 IN_RANGE ((REGNO), \
746 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
747 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
748
749 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
750 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
751 || ((REGNO) == FRAME_POINTER_REGNUM))
752
753 #define FP_REGISTER_P(REGNO) \
754 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
755
756 #define XD_REGISTER_P(REGNO) \
757 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
758
759 #define FP_OR_XD_REGISTER_P(REGNO) \
760 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
761
762 #define FP_ANY_REGISTER_P(REGNO) \
763 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
764
765 #define SPECIAL_REGISTER_P(REGNO) \
766 ((REGNO) == GBR_REG || (REGNO) == T_REG \
767 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
768
769 #define TARGET_REGISTER_P(REGNO) \
770 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
771
772 #define SHMEDIA_REGISTER_P(REGNO) \
773 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
774 || TARGET_REGISTER_P (REGNO))
775
776 /* This is to be used in TARGET_CONDITIONAL_REGISTER_USAGE, to mark
777 registers that should be fixed. */
778 #define VALID_REGISTER_P(REGNO) \
779 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
780 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
781 || (REGNO) == FRAME_POINTER_REGNUM \
782 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
783 || (TARGET_SH2E && (REGNO) == FPUL_REG))
784
785 /* The mode that should be generally used to store a register by
786 itself in the stack, or to load it back. */
787 #define REGISTER_NATURAL_MODE(REGNO) \
788 (FP_REGISTER_P (REGNO) ? SFmode \
789 : XD_REGISTER_P (REGNO) ? DFmode \
790 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
791 ? DImode \
792 : SImode)
793
794 #define FIRST_PSEUDO_REGISTER 154
795
796 /* Don't count soft frame pointer. */
797 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
798
799 /* 1 for registers that have pervasive standard uses
800 and are not available for the register allocator.
801
802 Mach register is fixed 'cause it's only 10 bits wide for SH1.
803 It is 32 bits wide for SH2. */
804
805 #define FIXED_REGISTERS \
806 { \
807 /* Regular registers. */ \
808 0, 0, 0, 0, 0, 0, 0, 0, \
809 0, 0, 0, 0, 0, 0, 0, 1, \
810 /* r16 is reserved, r18 is the former pr. */ \
811 1, 0, 0, 0, 0, 0, 0, 0, \
812 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
813 /* r26 is a global variable data pointer; r27 is for constants. */ \
814 1, 1, 1, 1, 0, 0, 0, 0, \
815 0, 0, 0, 0, 0, 0, 0, 0, \
816 0, 0, 0, 0, 0, 0, 0, 0, \
817 0, 0, 0, 0, 0, 0, 0, 0, \
818 0, 0, 0, 0, 0, 0, 0, 1, \
819 /* FP registers. */ \
820 0, 0, 0, 0, 0, 0, 0, 0, \
821 0, 0, 0, 0, 0, 0, 0, 0, \
822 0, 0, 0, 0, 0, 0, 0, 0, \
823 0, 0, 0, 0, 0, 0, 0, 0, \
824 0, 0, 0, 0, 0, 0, 0, 0, \
825 0, 0, 0, 0, 0, 0, 0, 0, \
826 0, 0, 0, 0, 0, 0, 0, 0, \
827 0, 0, 0, 0, 0, 0, 0, 0, \
828 /* Branch target registers. */ \
829 0, 0, 0, 0, 0, 0, 0, 0, \
830 /* XD registers. */ \
831 0, 0, 0, 0, 0, 0, 0, 0, \
832 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
833 1, 1, 1, 1, 1, 1, 0, 1, \
834 /*"rap", "sfp" */ \
835 1, 1, \
836 }
837
838 /* 1 for registers not available across function calls.
839 These must include the FIXED_REGISTERS and also any
840 registers that can be used without being saved.
841 The latter must include the registers where values are returned
842 and the register where structure-value addresses are passed.
843 Aside from that, you can include as many other registers as you like. */
844
845 #define CALL_USED_REGISTERS \
846 { \
847 /* Regular registers. */ \
848 1, 1, 1, 1, 1, 1, 1, 1, \
849 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
850 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
851 across SH5 function calls. */ \
852 0, 0, 0, 0, 0, 0, 0, 1, \
853 1, 1, 1, 1, 1, 1, 1, 1, \
854 1, 1, 1, 1, 0, 0, 0, 0, \
855 0, 0, 0, 0, 1, 1, 1, 1, \
856 1, 1, 1, 1, 0, 0, 0, 0, \
857 0, 0, 0, 0, 0, 0, 0, 0, \
858 0, 0, 0, 0, 1, 1, 1, 1, \
859 /* FP registers. */ \
860 1, 1, 1, 1, 1, 1, 1, 1, \
861 1, 1, 1, 1, 0, 0, 0, 0, \
862 1, 1, 1, 1, 1, 1, 1, 1, \
863 1, 1, 1, 1, 1, 1, 1, 1, \
864 1, 1, 1, 1, 0, 0, 0, 0, \
865 0, 0, 0, 0, 0, 0, 0, 0, \
866 0, 0, 0, 0, 0, 0, 0, 0, \
867 0, 0, 0, 0, 0, 0, 0, 0, \
868 /* Branch target registers. */ \
869 1, 1, 1, 1, 1, 0, 0, 0, \
870 /* XD registers. */ \
871 1, 1, 1, 1, 1, 1, 0, 0, \
872 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
873 1, 1, 1, 1, 1, 1, 1, 1, \
874 /*"rap", "sfp" */ \
875 1, 1, \
876 }
877
878 /* TARGET_CONDITIONAL_REGISTER_USAGE might want to make a register
879 call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */
880 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
881
882 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
883 across SHcompact function calls. We can't tell whether a called
884 function is SHmedia or SHcompact, so we assume it may be when
885 compiling SHmedia code with the 32-bit ABI, since that's the only
886 ABI that can be linked with SHcompact code. */
887 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
888 (TARGET_SHMEDIA32 \
889 && GET_MODE_SIZE (MODE) > 4 \
890 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
891 && (REGNO) <= FIRST_GENERAL_REG + 15) \
892 || TARGET_REGISTER_P (REGNO) \
893 || (REGNO) == PR_MEDIA_REG))
894
895 /* Return number of consecutive hard regs needed starting at reg REGNO
896 to hold something of mode MODE.
897 This is ordinarily the length in words of a value of mode MODE
898 but can be less for certain modes in special long registers.
899
900 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
901
902 #define HARD_REGNO_NREGS(REGNO, MODE) \
903 (XD_REGISTER_P (REGNO) \
904 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
905 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
906 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
907 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
908
909 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
910
911 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
912 sh_hard_regno_mode_ok ((REGNO), (MODE))
913
914 /* Value is 1 if it is a good idea to tie two pseudo registers
915 when one has mode MODE1 and one has mode MODE2.
916 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
917 for any hard reg, then this must be 0 for correct output.
918 That's the case for xd registers: we don't hold SFmode values in
919 them, so we can't tie an SFmode pseudos with one in another
920 floating-point mode. */
921
922 #define MODES_TIEABLE_P(MODE1, MODE2) \
923 ((MODE1) == (MODE2) \
924 || (TARGET_SHMEDIA \
925 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
926 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
927 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
928 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
929 && (GET_MODE_SIZE (MODE2) <= 4)) \
930 : ((MODE1) != SFmode && (MODE2) != SFmode))))
931
932 /* A C expression that is nonzero if hard register NEW_REG can be
933 considered for use as a rename register for OLD_REG register */
934
935 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
936 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
937
938 /* Specify the registers used for certain standard purposes.
939 The values of these macros are register numbers. */
940
941 /* Define this if the program counter is overloaded on a register. */
942 /* #define PC_REGNUM 15*/
943
944 /* Register to use for pushing function arguments. */
945 #define STACK_POINTER_REGNUM SP_REG
946
947 /* Base register for access to local variables of the function. */
948 #define HARD_FRAME_POINTER_REGNUM FP_REG
949
950 /* Base register for access to local variables of the function. */
951 #define FRAME_POINTER_REGNUM 153
952
953 /* Fake register that holds the address on the stack of the
954 current function's return address. */
955 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
956
957 /* Register to hold the addressing base for position independent
958 code access to data items. */
959 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
960
961 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
962
963 /* Definitions for register eliminations.
964
965 We have three registers that can be eliminated on the SH. First, the
966 frame pointer register can often be eliminated in favor of the stack
967 pointer register. Secondly, the argument pointer register can always be
968 eliminated; it is replaced with either the stack or frame pointer.
969 Third, there is the return address pointer, which can also be replaced
970 with either the stack or the frame pointer. */
971
972 /* This is an array of structures. Each structure initializes one pair
973 of eliminable registers. The "from" register number is given first,
974 followed by "to". Eliminations of the same "from" register are listed
975 in order of preference. */
976
977 /* If you add any registers here that are not actually hard registers,
978 and that have any alternative of elimination that doesn't always
979 apply, you need to amend calc_live_regs to exclude it, because
980 reload spills all eliminable registers where it sees an
981 can_eliminate == 0 entry, thus making them 'live' .
982 If you add any hard registers that can be eliminated in different
983 ways, you have to patch reload to spill them only when all alternatives
984 of elimination fail. */
985
986 #define ELIMINABLE_REGS \
987 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
988 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
989 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
990 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
991 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
992 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
993 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
994
995 /* Define the offset between two registers, one to be eliminated, and the other
996 its replacement, at the start of a routine. */
997
998 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
999 OFFSET = initial_elimination_offset ((FROM), (TO))
1000
1001 /* Base register for access to arguments of the function. */
1002 #define ARG_POINTER_REGNUM AP_REG
1003
1004 /* Register in which the static-chain is passed to a function. */
1005 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1006
1007 /* Don't default to pcc-struct-return, because we have already specified
1008 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1009 target hook. */
1010
1011 #define DEFAULT_PCC_STRUCT_RETURN 0
1012
1013 #define SHMEDIA_REGS_STACK_ADJUST() \
1014 (TARGET_SHCOMPACT && crtl->saves_all_registers \
1015 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1016 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1017 : 0)
1018
1019 \f
1020 /* Define the classes of registers for register constraints in the
1021 machine description. Also define ranges of constants.
1022
1023 One of the classes must always be named ALL_REGS and include all hard regs.
1024 If there is more than one class, another class must be named NO_REGS
1025 and contain no registers.
1026
1027 The name GENERAL_REGS must be the name of a class (or an alias for
1028 another name such as ALL_REGS). This is the class of registers
1029 that is allowed by "g" or "r" in a register constraint.
1030 Also, registers outside this class are allocated only when
1031 instructions express preferences for them.
1032
1033 The classes must be numbered in nondecreasing order; that is,
1034 a larger-numbered class must never be contained completely
1035 in a smaller-numbered class.
1036
1037 For any two classes, it is very desirable that there be another
1038 class that represents their union. */
1039
1040 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1041 be used as the destination of some of the arithmetic ops. There are
1042 also some special purpose registers; the T bit register, the
1043 Procedure Return Register and the Multiply Accumulate Registers. */
1044 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1045 reg_class_subunion. We don't want to have an actual union class
1046 of these, because it would only be used when both classes are calculated
1047 to give the same cost, but there is only one FPUL register.
1048 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1049 applying to the actual instruction alternative considered. E.g., the
1050 y/r alternative of movsi_ie is considered to have no more cost that
1051 the r/r alternative, which is patently untrue. */
1052
1053 enum reg_class
1054 {
1055 NO_REGS,
1056 R0_REGS,
1057 PR_REGS,
1058 T_REGS,
1059 MAC_REGS,
1060 FPUL_REGS,
1061 SIBCALL_REGS,
1062 NON_SP_REGS,
1063 GENERAL_REGS,
1064 FP0_REGS,
1065 FP_REGS,
1066 DF_HI_REGS,
1067 DF_REGS,
1068 FPSCR_REGS,
1069 GENERAL_FP_REGS,
1070 GENERAL_DF_REGS,
1071 TARGET_REGS,
1072 ALL_REGS,
1073 LIM_REG_CLASSES
1074 };
1075
1076 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1077
1078 /* Give names of register classes as strings for dump file. */
1079 #define REG_CLASS_NAMES \
1080 { \
1081 "NO_REGS", \
1082 "R0_REGS", \
1083 "PR_REGS", \
1084 "T_REGS", \
1085 "MAC_REGS", \
1086 "FPUL_REGS", \
1087 "SIBCALL_REGS", \
1088 "NON_SP_REGS", \
1089 "GENERAL_REGS", \
1090 "FP0_REGS", \
1091 "FP_REGS", \
1092 "DF_HI_REGS", \
1093 "DF_REGS", \
1094 "FPSCR_REGS", \
1095 "GENERAL_FP_REGS", \
1096 "GENERAL_DF_REGS", \
1097 "TARGET_REGS", \
1098 "ALL_REGS", \
1099 }
1100
1101 /* Define which registers fit in which classes.
1102 This is an initializer for a vector of HARD_REG_SET
1103 of length N_REG_CLASSES. */
1104
1105 #define REG_CLASS_CONTENTS \
1106 { \
1107 /* NO_REGS: */ \
1108 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1109 /* R0_REGS: */ \
1110 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1111 /* PR_REGS: */ \
1112 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1113 /* T_REGS: */ \
1114 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1115 /* MAC_REGS: */ \
1116 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1117 /* FPUL_REGS: */ \
1118 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1119 /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1120 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1121 /* NON_SP_REGS: */ \
1122 { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1123 /* GENERAL_REGS: */ \
1124 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1125 /* FP0_REGS: */ \
1126 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1127 /* FP_REGS: */ \
1128 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1129 /* DF_HI_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1130 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1131 /* DF_REGS: */ \
1132 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1133 /* FPSCR_REGS: */ \
1134 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1135 /* GENERAL_FP_REGS: */ \
1136 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1137 /* GENERAL_DF_REGS: */ \
1138 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1139 /* TARGET_REGS: */ \
1140 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1141 /* ALL_REGS: */ \
1142 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1143 }
1144
1145 /* The same information, inverted:
1146 Return the class number of the smallest class containing
1147 reg number REGNO. This could be a conditional expression
1148 or could index an array. */
1149
1150 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1151 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1152
1153 /* When this hook returns true for MODE, the compiler allows
1154 registers explicitly used in the rtl to be used as spill registers
1155 but prevents the compiler from extending the lifetime of these
1156 registers. */
1157 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1158 sh_small_register_classes_for_mode_p
1159
1160 /* The order in which register should be allocated. */
1161 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1162 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1163 spilled or used otherwise, we better have the FP_REGS allocated first. */
1164 #define REG_ALLOC_ORDER \
1165 {/* Caller-saved FPRs */ \
1166 65, 66, 67, 68, 69, 70, 71, 64, \
1167 72, 73, 74, 75, 80, 81, 82, 83, \
1168 84, 85, 86, 87, 88, 89, 90, 91, \
1169 92, 93, 94, 95, 96, 97, 98, 99, \
1170 /* Callee-saved FPRs */ \
1171 76, 77, 78, 79,100,101,102,103, \
1172 104,105,106,107,108,109,110,111, \
1173 112,113,114,115,116,117,118,119, \
1174 120,121,122,123,124,125,126,127, \
1175 136,137,138,139,140,141,142,143, \
1176 /* FPSCR */ 151, \
1177 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1178 1, 2, 3, 7, 6, 5, 4, 0, \
1179 8, 9, 17, 19, 20, 21, 22, 23, \
1180 36, 37, 38, 39, 40, 41, 42, 43, \
1181 60, 61, 62, \
1182 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1183 10, 11, 12, 13, 14, 18, \
1184 /* SH5 callee-saved GPRs */ \
1185 28, 29, 30, 31, 32, 33, 34, 35, \
1186 44, 45, 46, 47, 48, 49, 50, 51, \
1187 52, 53, 54, 55, 56, 57, 58, 59, \
1188 /* FPUL */ 150, \
1189 /* SH5 branch target registers */ \
1190 128,129,130,131,132,133,134,135, \
1191 /* Fixed registers */ \
1192 15, 16, 24, 25, 26, 27, 63,144, \
1193 145,146,147,148,149,152,153 }
1194
1195 /* The class value for index registers, and the one for base regs. */
1196 #define INDEX_REG_CLASS \
1197 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1198 #define BASE_REG_CLASS GENERAL_REGS
1199 \f
1200 /* Defines for sh.md and constraints.md. */
1201
1202 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1203 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1204 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1205 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1206 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1207 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1208 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1209 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1210
1211 #define CONST_OK_FOR_J16(VALUE) \
1212 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1213 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1214
1215 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1216 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1217
1218 #define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\
1219 (((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX))
1220
1221 #if 0
1222 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1223 ((((REGCLASS_HAS_FP_REG (CLASS) \
1224 && (REG_P (X) \
1225 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1226 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1227 && TARGET_FMOVD)))) \
1228 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1229 && REG_P (X) \
1230 && FP_REGISTER_P (REGNO (X)))) \
1231 && ! TARGET_SHMEDIA \
1232 && ((MODE) == SFmode || (MODE) == SImode)) \
1233 ? FPUL_REGS \
1234 : (((CLASS) == FPUL_REGS \
1235 || (REGCLASS_HAS_FP_REG (CLASS) \
1236 && ! TARGET_SHMEDIA && MODE == SImode)) \
1237 && (MEM_P (X) \
1238 || (REG_P (X) \
1239 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1240 || REGNO (X) == T_REG \
1241 || system_reg_operand (X, VOIDmode))))) \
1242 ? GENERAL_REGS \
1243 : (((CLASS) == TARGET_REGS \
1244 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1245 && !satisfies_constraint_Csy (X) \
1246 && (!REG_P (X) || ! GENERAL_REGISTER_P (REGNO (X)))) \
1247 ? GENERAL_REGS \
1248 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1249 && REG_P (X) && ! GENERAL_REGISTER_P (REGNO (X)) \
1250 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1251 ? GENERAL_REGS \
1252 : ((CLASS) != GENERAL_REGS && REG_P (X) \
1253 && TARGET_REGISTER_P (REGNO (X))) \
1254 ? GENERAL_REGS : (ELSE))
1255
1256 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1257 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1258
1259 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1260 ((REGCLASS_HAS_FP_REG (CLASS) \
1261 && ! TARGET_SHMEDIA \
1262 && immediate_operand ((X), (MODE)) \
1263 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1264 && (MODE) == SFmode && fldi_ok ())) \
1265 ? R0_REGS \
1266 : ((CLASS) == FPUL_REGS \
1267 && ((REG_P (X) \
1268 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1269 || REGNO (X) == T_REG)) \
1270 || GET_CODE (X) == PLUS)) \
1271 ? GENERAL_REGS \
1272 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1273 ? (satisfies_constraint_I08 (X) \
1274 ? GENERAL_REGS \
1275 : R0_REGS) \
1276 : ((CLASS) == FPSCR_REGS \
1277 && ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1278 || (MEM_P (X) && GET_CODE (XEXP ((X), 0)) == PLUS))) \
1279 ? GENERAL_REGS \
1280 : (REGCLASS_HAS_FP_REG (CLASS) \
1281 && TARGET_SHMEDIA \
1282 && immediate_operand ((X), (MODE)) \
1283 && (X) != CONST0_RTX (GET_MODE (X)) \
1284 && GET_MODE (X) != V4SFmode) \
1285 ? GENERAL_REGS \
1286 : (((MODE) == QImode || (MODE) == HImode) \
1287 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1288 ? GENERAL_REGS \
1289 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1290 && (GET_CODE (X) == LABEL_REF || PIC_ADDR_P (X))) \
1291 ? TARGET_REGS \
1292 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1293 #endif
1294
1295 /* Return the maximum number of consecutive registers
1296 needed to represent mode MODE in a register of class CLASS.
1297
1298 If TARGET_SHMEDIA, we need two FP registers per word.
1299 Otherwise we will need at most one register per word. */
1300 #define CLASS_MAX_NREGS(CLASS, MODE) \
1301 (TARGET_SHMEDIA \
1302 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1303 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1304 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1305
1306 /* If defined, gives a class of registers that cannot be used as the
1307 operand of a SUBREG that changes the mode of the object illegally. */
1308 /* ??? We need to renumber the internal numbers for the frnn registers
1309 when in little endian in order to allow mode size changes. */
1310
1311 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1312 sh_cannot_change_mode_class (FROM, TO, CLASS)
1313 \f
1314 /* Stack layout; function entry, exit and calling. */
1315
1316 /* Define the number of registers that can hold parameters.
1317 These macros are used only in other macro definitions below. */
1318
1319 #define NPARM_REGS(MODE) \
1320 (TARGET_FPU_ANY && (MODE) == SFmode \
1321 ? (TARGET_SH5 ? 12 : 8) \
1322 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1323 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1324 ? (TARGET_SH5 ? 12 : 8) \
1325 : (TARGET_SH5 ? 8 : 4))
1326
1327 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1328 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1329
1330 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1331 #define FIRST_FP_RET_REG FIRST_FP_REG
1332
1333 /* Define this if pushing a word on the stack
1334 makes the stack pointer a smaller address. */
1335 #define STACK_GROWS_DOWNWARD
1336
1337 /* Define this macro to nonzero if the addresses of local variable slots
1338 are at negative offsets from the frame pointer. */
1339 #define FRAME_GROWS_DOWNWARD 1
1340
1341 /* Offset from the frame pointer to the first local variable slot to
1342 be allocated. */
1343 #define STARTING_FRAME_OFFSET 0
1344
1345 /* If we generate an insn to push BYTES bytes,
1346 this says how many the stack pointer really advances by. */
1347 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1348 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1349 do correct alignment. */
1350 #if 0
1351 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1352 #endif
1353
1354 /* Offset of first parameter from the argument pointer register value. */
1355 #define FIRST_PARM_OFFSET(FNDECL) 0
1356
1357 /* Value is the number of bytes of arguments automatically popped when
1358 calling a subroutine.
1359 CUM is the accumulated argument list.
1360
1361 On SHcompact, the call trampoline pops arguments off the stack. */
1362 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1363
1364 /* Some subroutine macros specific to this machine. */
1365
1366 #define BASE_RETURN_VALUE_REG(MODE) \
1367 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1368 ? FIRST_FP_RET_REG \
1369 : TARGET_FPU_ANY && (MODE) == SCmode \
1370 ? FIRST_FP_RET_REG \
1371 : (TARGET_FPU_DOUBLE \
1372 && ((MODE) == DFmode || (MODE) == SFmode \
1373 || (MODE) == DCmode || (MODE) == SCmode )) \
1374 ? FIRST_FP_RET_REG \
1375 : FIRST_RET_REG)
1376
1377 #define BASE_ARG_REG(MODE) \
1378 ((TARGET_SH2E && ((MODE) == SFmode)) \
1379 ? FIRST_FP_PARM_REG \
1380 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1381 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1382 ? FIRST_FP_PARM_REG \
1383 : FIRST_PARM_REG)
1384
1385 /* 1 if N is a possible register number for function argument passing. */
1386 /* ??? There are some callers that pass REGNO as int, and others that pass
1387 it as unsigned. We get warnings unless we do casts everywhere. */
1388 #define FUNCTION_ARG_REGNO_P(REGNO) \
1389 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1390 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1391 || (TARGET_FPU_ANY \
1392 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1393 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1394 + NPARM_REGS (SFmode))))
1395 \f
1396 /* Define a data type for recording info about an argument list
1397 during the scan of that argument list. This data type should
1398 hold all necessary information about the function itself
1399 and about the args processed so far, enough to enable macros
1400 such as FUNCTION_ARG to determine where the next arg should go.
1401
1402 On SH, this is a single integer, which is a number of words
1403 of arguments scanned so far (including the invisible argument,
1404 if any, which holds the structure-value-address).
1405 Thus NARGREGS or more means all following args should go on the stack. */
1406
1407 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1408 struct sh_args {
1409 int arg_count[2];
1410 int force_mem;
1411 /* Nonzero if a prototype is available for the function. */
1412 int prototype_p;
1413 /* The number of an odd floating-point register, that should be used
1414 for the next argument of type float. */
1415 int free_single_fp_reg;
1416 /* Whether we're processing an outgoing function call. */
1417 int outgoing;
1418 /* The number of general-purpose registers that should have been
1419 used to pass partial arguments, that are passed totally on the
1420 stack. On SHcompact, a call trampoline will pop them off the
1421 stack before calling the actual function, and, if the called
1422 function is implemented in SHcompact mode, the incoming arguments
1423 decoder will push such arguments back onto the stack. For
1424 incoming arguments, STACK_REGS also takes into account other
1425 arguments passed by reference, that the decoder will also push
1426 onto the stack. */
1427 int stack_regs;
1428 /* The number of general-purpose registers that should have been
1429 used to pass arguments, if the arguments didn't have to be passed
1430 by reference. */
1431 int byref_regs;
1432 /* Set as by shcompact_byref if the current argument is to be passed
1433 by reference. */
1434 int byref;
1435
1436 /* call_cookie is a bitmask used by call expanders, as well as
1437 function prologue and epilogues, to allow SHcompact to comply
1438 with the SH5 32-bit ABI, that requires 64-bit registers to be
1439 used even though only the lower 32-bit half is visible in
1440 SHcompact mode. The strategy is to call SHmedia trampolines.
1441
1442 The alternatives for each of the argument-passing registers are
1443 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1444 contents from the address in it; (d) add 8 to it, storing the
1445 result in the next register, then (c); (e) copy it from some
1446 floating-point register,
1447
1448 Regarding copies from floating-point registers, r2 may only be
1449 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1450 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1451 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1452 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1453 dr10.
1454
1455 The bit mask is structured as follows:
1456
1457 - 1 bit to tell whether to set up a return trampoline.
1458
1459 - 3 bits to count the number consecutive registers to pop off the
1460 stack.
1461
1462 - 4 bits for each of r9, r8, r7 and r6.
1463
1464 - 3 bits for each of r5, r4, r3 and r2.
1465
1466 - 3 bits set to 0 (the most significant ones)
1467
1468 3 2 1 0
1469 1098 7654 3210 9876 5432 1098 7654 3210
1470 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1471 2223 3344 4555 6666 7777 8888 9999 SSS-
1472
1473 - If F is set, the register must be copied from an FP register,
1474 whose number is encoded in the remaining bits.
1475
1476 - Else, if L is set, the register must be loaded from the address
1477 contained in it. If the P bit is *not* set, the address of the
1478 following dword should be computed first, and stored in the
1479 following register.
1480
1481 - Else, if P is set, the register alone should be popped off the
1482 stack.
1483
1484 - After all this processing, the number of registers represented
1485 in SSS will be popped off the stack. This is an optimization
1486 for pushing/popping consecutive registers, typically used for
1487 varargs and large arguments partially passed in registers.
1488
1489 - If T is set, a return trampoline will be set up for 64-bit
1490 return values to be split into 2 32-bit registers. */
1491 long call_cookie;
1492
1493 /* This is set to nonzero when the call in question must use the Renesas ABI,
1494 even without the -mrenesas option. */
1495 int renesas_abi;
1496 };
1497
1498 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1499 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1500 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1501 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1502 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1503 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1504 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1505 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1506 #define CALL_COOKIE_INT_REG(REG, VAL) \
1507 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1508 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1509 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1510
1511 #define CUMULATIVE_ARGS struct sh_args
1512
1513 #define GET_SH_ARG_CLASS(MODE) \
1514 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1515 ? SH_ARG_FLOAT \
1516 /* There's no mention of complex float types in the SH5 ABI, so we
1517 should presumably handle them as aggregate types. */ \
1518 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1519 ? SH_ARG_INT \
1520 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1521 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1522 ? SH_ARG_FLOAT : SH_ARG_INT)
1523
1524 #define ROUND_ADVANCE(SIZE) \
1525 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1526
1527 /* Round a register number up to a proper boundary for an arg of mode
1528 MODE.
1529
1530 The SH doesn't care about double alignment, so we only
1531 round doubles to even regs when asked to explicitly. */
1532
1533 #define ROUND_REG(CUM, MODE) \
1534 (((TARGET_ALIGN_DOUBLE \
1535 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1536 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1537 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1538 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1539 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1540 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1541
1542 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1543 for a call to a function whose data type is FNTYPE.
1544 For a library call, FNTYPE is 0.
1545
1546 On SH, the offset always starts at 0: the first parm reg is always
1547 the same reg for a given argument class.
1548
1549 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1550
1551 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1552 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1553
1554 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1555 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1556
1557 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1558 This macro is only used in this file. */
1559
1560 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1561 (((TYPE) == 0 \
1562 || (! TREE_ADDRESSABLE ((TYPE)) \
1563 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1564 || ! (AGGREGATE_TYPE_P (TYPE) \
1565 || (!TARGET_FPU_ANY \
1566 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1567 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1568 && ! (CUM).force_mem \
1569 && (TARGET_SH2E \
1570 ? ((MODE) == BLKmode \
1571 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1572 + int_size_in_bytes (TYPE)) \
1573 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1574 : ((ROUND_REG((CUM), (MODE)) \
1575 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1576 <= NPARM_REGS (MODE))) \
1577 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1578
1579 /* By accident we got stuck with passing SCmode on SH4 little endian
1580 in two registers that are nominally successive - which is different from
1581 two single SFmode values, where we take endianness translation into
1582 account. That does not work at all if an odd number of registers is
1583 already in use, so that got fixed, but library functions are still more
1584 likely to use complex numbers without mixing them with SFmode arguments
1585 (which in C would have to be structures), so for the sake of ABI
1586 compatibility the way SCmode values are passed when an even number of
1587 FP registers is in use remains different from a pair of SFmode values for
1588 now.
1589 I.e.:
1590 foo (double); a: fr5,fr4
1591 foo (float a, float b); a: fr5 b: fr4
1592 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1593 this should be the other way round...
1594 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1595 #define FUNCTION_ARG_SCmode_WART 1
1596
1597 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1598 register in SHcompact mode, it must be padded in the most
1599 significant end. This means that passing it by reference wouldn't
1600 pad properly on a big-endian machine. In this particular case, we
1601 pass this argument on the stack, in a way that the call trampoline
1602 will load its value into the appropriate register. */
1603 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1604 ((MODE) == BLKmode \
1605 && TARGET_SHCOMPACT \
1606 && ! TARGET_LITTLE_ENDIAN \
1607 && int_size_in_bytes (TYPE) > 4 \
1608 && int_size_in_bytes (TYPE) < 8)
1609
1610 /* Minimum alignment for an argument to be passed by callee-copy
1611 reference. We need such arguments to be aligned to 8 byte
1612 boundaries, because they'll be loaded using quad loads. */
1613 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1614
1615 /* The SH5 ABI requires floating-point arguments to be passed to
1616 functions without a prototype in both an FP register and a regular
1617 register or the stack. When passing the argument in both FP and
1618 general-purpose registers, list the FP register first. */
1619 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1620 (gen_rtx_PARALLEL \
1621 ((MODE), \
1622 gen_rtvec (2, \
1623 gen_rtx_EXPR_LIST \
1624 (VOIDmode, \
1625 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1626 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1627 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1628 : NULL_RTX), \
1629 const0_rtx), \
1630 gen_rtx_EXPR_LIST \
1631 (VOIDmode, \
1632 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1633 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1634 + (CUM).arg_count[(int) SH_ARG_INT]) \
1635 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1636 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1637 const0_rtx))))
1638
1639 /* The SH5 ABI requires regular registers or stack slots to be
1640 reserved for floating-point arguments. Registers are taken care of
1641 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1642 Unfortunately, there's no way to just reserve a stack slot, so
1643 we'll end up needlessly storing a copy of the argument in the
1644 stack. For incoming arguments, however, the PARALLEL will be
1645 optimized to the register-only form, and the value in the stack
1646 slot won't be used at all. */
1647 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1648 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1649 ? gen_rtx_REG ((MODE), (REG)) \
1650 : gen_rtx_PARALLEL ((MODE), \
1651 gen_rtvec (2, \
1652 gen_rtx_EXPR_LIST \
1653 (VOIDmode, NULL_RTX, \
1654 const0_rtx), \
1655 gen_rtx_EXPR_LIST \
1656 (VOIDmode, gen_rtx_REG ((MODE), \
1657 (REG)), \
1658 const0_rtx))))
1659
1660 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1661 (TARGET_SH5 \
1662 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
1663 || (MODE) == DCmode) \
1664 && ((CUM).arg_count[(int) SH_ARG_INT] \
1665 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1666 : GET_MODE_SIZE (MODE)) \
1667 + 7) / 8) > NPARM_REGS (SImode))
1668
1669 /* Perform any needed actions needed for a function that is receiving a
1670 variable number of arguments. */
1671
1672 /* Call the function profiler with a given profile label.
1673 We use two .aligns, so as to make sure that both the .long is aligned
1674 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1675 from the trapa instruction. */
1676
1677 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1678 { \
1679 if (TARGET_SHMEDIA) \
1680 { \
1681 fprintf((STREAM), "\tmovi\t33,r0\n"); \
1682 fprintf((STREAM), "\ttrapa\tr0\n"); \
1683 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1684 } \
1685 else \
1686 { \
1687 fprintf((STREAM), "\t.align\t2\n"); \
1688 fprintf((STREAM), "\ttrapa\t#33\n"); \
1689 fprintf((STREAM), "\t.align\t2\n"); \
1690 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1691 } \
1692 }
1693
1694 /* Define this macro if the code for function profiling should come
1695 before the function prologue. Normally, the profiling code comes
1696 after. */
1697
1698 #define PROFILE_BEFORE_PROLOGUE
1699
1700 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1701 the stack pointer does not matter. The value is tested only in
1702 functions that have frame pointers.
1703 No definition is equivalent to always zero. */
1704
1705 #define EXIT_IGNORE_STACK 1
1706
1707 /*
1708 On the SH, the trampoline looks like
1709 2 0002 D202 mov.l l2,r2
1710 1 0000 D301 mov.l l1,r3
1711 3 0004 422B jmp @r2
1712 4 0006 0009 nop
1713 5 0008 00000000 l1: .long area
1714 6 000c 00000000 l2: .long function */
1715
1716 /* Length in units of the trampoline for entering a nested function. */
1717 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
1718
1719 /* Alignment required for a trampoline in bits . */
1720 #define TRAMPOLINE_ALIGNMENT \
1721 ((CACHE_LOG < 3 || (optimize_size && ! TARGET_HARVARD)) ? 32 \
1722 : TARGET_SHMEDIA ? 256 : 64)
1723
1724 /* A C expression whose value is RTL representing the value of the return
1725 address for the frame COUNT steps up from the current frame.
1726 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1727 can ignore COUNT. */
1728
1729 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1730 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
1731
1732 /* A C expression whose value is RTL representing the location of the
1733 incoming return address at the beginning of any function, before the
1734 prologue. This RTL is either a REG, indicating that the return
1735 value is saved in REG, or a MEM representing a location in
1736 the stack. */
1737 #define INCOMING_RETURN_ADDR_RTX \
1738 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
1739 \f
1740 /* Addressing modes, and classification of registers for them. */
1741 #define HAVE_POST_INCREMENT TARGET_SH1
1742 #define HAVE_PRE_DECREMENT TARGET_SH1
1743
1744 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1745 ? 0 : TARGET_SH1)
1746 #define USE_LOAD_PRE_DECREMENT(mode) 0
1747 #define USE_STORE_POST_INCREMENT(mode) 0
1748 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1749 ? 0 : TARGET_SH1)
1750
1751 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
1752 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
1753 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1754
1755 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
1756 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
1757 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1758
1759 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
1760
1761 /* Macros to check register numbers against specific register classes. */
1762
1763 /* These assume that REGNO is a hard or pseudo reg number.
1764 They give nonzero only if REGNO is a hard reg of the suitable class
1765 or a pseudo reg currently allocated to a suitable hard reg.
1766 Since they use reg_renumber, they are safe only once reg_renumber
1767 has been allocated, which happens in local-alloc.c. */
1768
1769 #define REGNO_OK_FOR_BASE_P(REGNO) \
1770 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1771 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1772 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1773 (TARGET_SHMEDIA \
1774 ? (GENERAL_REGISTER_P (REGNO) \
1775 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
1776 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1777
1778 /* Maximum number of registers that can appear in a valid memory
1779 address. */
1780
1781 #define MAX_REGS_PER_ADDRESS 2
1782
1783 /* Recognize any constant value that is a valid address. */
1784
1785 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1786
1787 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1788 and check its validity for a certain class.
1789 The suitable hard regs are always accepted and all pseudo regs
1790 are also accepted if STRICT is not set. */
1791
1792 /* Nonzero if X is a reg that can be used as a base reg. */
1793 #define REG_OK_FOR_BASE_P(X, STRICT) \
1794 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1795 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1796
1797 /* Nonzero if X is a reg that can be used as an index. */
1798 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1799 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1800 : REGNO (X) == R0_REG) \
1801 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1802
1803 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1804 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1805 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1806 : REGNO (X) == R0_REG && OFFSET == 0) \
1807 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1808
1809 /* Macros for extra constraints. */
1810
1811 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1812 ((GET_CODE ((OP)) == LABEL_REF) \
1813 || (GET_CODE ((OP)) == CONST \
1814 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1815 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1816 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1817
1818 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1819 (CONSTANT_P (OP) \
1820 && !CONST_INT_P (OP) \
1821 && GET_CODE (OP) != CONST_DOUBLE \
1822 && (!flag_pic \
1823 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1824 && !PIC_ADDR_P (OP) \
1825 && GET_CODE (OP) != LABEL_REF)))
1826
1827 /* Check whether OP is a datalabel unspec. */
1828 #define DATALABEL_REF_NO_CONST_P(OP) \
1829 (GET_CODE (OP) == UNSPEC \
1830 && XINT ((OP), 1) == UNSPEC_DATALABEL \
1831 && XVECLEN ((OP), 0) == 1 \
1832 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
1833
1834 #define GOT_ENTRY_P(OP) \
1835 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1836 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1837
1838 #define GOTPLT_ENTRY_P(OP) \
1839 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1840 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1841
1842 #define UNSPEC_GOTOFF_P(OP) \
1843 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1844
1845 #define GOTOFF_P(OP) \
1846 (GET_CODE (OP) == CONST \
1847 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1848 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1849 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1850 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1851
1852 #define PIC_ADDR_P(OP) \
1853 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1854 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1855
1856 #define PCREL_SYMOFF_P(OP) \
1857 (GET_CODE (OP) == CONST \
1858 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1859 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
1860
1861 #define NON_PIC_REFERENCE_P(OP) \
1862 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
1863 || (GET_CODE (OP) == CONST \
1864 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
1865 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
1866 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
1867 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
1868 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
1869 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1870 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
1871 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1872
1873 #define PIC_REFERENCE_P(OP) \
1874 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
1875 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
1876
1877 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
1878 (flag_pic \
1879 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
1880 || PCREL_SYMOFF_P (OP)) \
1881 : NON_PIC_REFERENCE_P (OP))
1882 \f
1883 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
1884 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
1885 || (GET_CODE (X) == SUBREG \
1886 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1887 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1888 && REG_P (SUBREG_REG (X)) \
1889 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
1890
1891 /* Since this must be r0, which is a single register class, we must check
1892 SUBREGs more carefully, to be sure that we don't accept one that extends
1893 outside the class. */
1894 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
1895 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
1896 || (GET_CODE (X) == SUBREG \
1897 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1898 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1899 && REG_P (SUBREG_REG (X)) \
1900 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
1901
1902 #ifdef REG_OK_STRICT
1903 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
1904 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
1905 #else
1906 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
1907 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
1908 #endif
1909
1910 #define ALLOW_INDEXED_ADDRESS \
1911 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
1912 \f
1913 /* A C compound statement that attempts to replace X, which is an address
1914 that needs reloading, with a valid memory address for an operand of
1915 mode MODE. WIN is a C statement label elsewhere in the code. */
1916
1917 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1918 do { \
1919 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
1920 goto WIN; \
1921 } while (0)
1922 \f
1923 /* Specify the machine mode that this machine uses
1924 for the index in the tablejump instruction. */
1925 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
1926
1927 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1928 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1929 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1930 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1931 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1932 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1933 : SImode)
1934
1935 /* Define as C expression which evaluates to nonzero if the tablejump
1936 instruction expects the table to contain offsets from the address of the
1937 table.
1938 Do not define this if the table should contain absolute addresses. */
1939 #define CASE_VECTOR_PC_RELATIVE 1
1940
1941 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
1942 #define FLOAT_TYPE_SIZE 32
1943
1944 /* Since the SH2e has only `float' support, it is desirable to make all
1945 floating point types equivalent to `float'. */
1946 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
1947
1948 /* 'char' is signed by default. */
1949 #define DEFAULT_SIGNED_CHAR 1
1950
1951 /* The type of size_t unsigned int. */
1952 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
1953
1954 #undef PTRDIFF_TYPE
1955 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
1956
1957 #define WCHAR_TYPE "short unsigned int"
1958 #define WCHAR_TYPE_SIZE 16
1959
1960 #define SH_ELF_WCHAR_TYPE "long int"
1961
1962 /* Max number of bytes we can move from memory to memory
1963 in one reasonably fast instruction. */
1964 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
1965
1966 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
1967 MOVE_MAX is not a compile-time constant. */
1968 #define MAX_MOVE_MAX 8
1969
1970 /* Max number of bytes we want move_by_pieces to be able to copy
1971 efficiently. */
1972 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
1973
1974 /* Define if operations between registers always perform the operation
1975 on the full register even if a narrower mode is specified. */
1976 #define WORD_REGISTER_OPERATIONS
1977
1978 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1979 will either zero-extend or sign-extend. The value of this macro should
1980 be the code that says which one of the two operations is implicitly
1981 done, UNKNOWN if none. */
1982 /* For SHmedia, we can truncate to QImode easier using zero extension. */
1983 /* FP registers can load SImode values, but don't implicitly sign-extend
1984 them to DImode. */
1985 #define LOAD_EXTEND_OP(MODE) \
1986 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
1987 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
1988
1989 /* Define if loading short immediate values into registers sign extends. */
1990 #define SHORT_IMMEDIATES_SIGN_EXTEND
1991
1992 /* Nonzero if access to memory by bytes is no faster than for words. */
1993 #define SLOW_BYTE_ACCESS 1
1994
1995 /* Immediate shift counts are truncated by the output routines (or was it
1996 the assembler?). Shift counts in a register are truncated by SH. Note
1997 that the native compiler puts too large (> 32) immediate shift counts
1998 into a register and shifts by the register, letting the SH decide what
1999 to do instead of doing that itself. */
2000 /* ??? The library routines in lib1funcs.S truncate the shift count.
2001 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2002 expects - the sign bit is significant - so it appears that we need to
2003 leave this zero for correct SH3 code. */
2004 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2005
2006 /* All integers have the same format so truncation is easy. */
2007 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2008 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2009 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2010
2011 /* Define this if addresses of constant functions
2012 shouldn't be put through pseudo regs where they can be cse'd.
2013 Desirable on machines where ordinary constants are expensive
2014 but a CALL with constant address is cheap. */
2015 /*#define NO_FUNCTION_CSE 1*/
2016
2017 /* The machine modes of pointers and functions. */
2018 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2019 #define FUNCTION_MODE Pmode
2020
2021 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2022 are actually function calls with some special constraints on arguments
2023 and register usage.
2024
2025 These macros tell reorg that the references to arguments and
2026 register clobbers for insns of type sfunc do not appear to happen
2027 until after the millicode call. This allows reorg to put insns
2028 which set the argument registers into the delay slot of the millicode
2029 call -- thus they act more like traditional CALL_INSNs.
2030
2031 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2032 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2033 in particular. */
2034
2035 #define INSN_SETS_ARE_DELAYED(X) \
2036 ((NONJUMP_INSN_P (X) \
2037 && GET_CODE (PATTERN (X)) != SEQUENCE \
2038 && GET_CODE (PATTERN (X)) != USE \
2039 && GET_CODE (PATTERN (X)) != CLOBBER \
2040 && get_attr_is_sfunc (X)))
2041
2042 #define INSN_REFERENCES_ARE_DELAYED(X) \
2043 ((NONJUMP_INSN_P (X) \
2044 && GET_CODE (PATTERN (X)) != SEQUENCE \
2045 && GET_CODE (PATTERN (X)) != USE \
2046 && GET_CODE (PATTERN (X)) != CLOBBER \
2047 && get_attr_is_sfunc (X)))
2048
2049 \f
2050 /* Position Independent Code. */
2051
2052 /* We can't directly access anything that contains a symbol,
2053 nor can we indirect via the constant pool. */
2054 #define LEGITIMATE_PIC_OPERAND_P(X) \
2055 ((! nonpic_symbol_mentioned_p (X) \
2056 && (GET_CODE (X) != SYMBOL_REF \
2057 || ! CONSTANT_POOL_ADDRESS_P (X) \
2058 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2059 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2060
2061 #define SYMBOLIC_CONST_P(X) \
2062 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2063 && nonpic_symbol_mentioned_p (X))
2064 \f
2065 /* Compute extra cost of moving data between one register class
2066 and another. */
2067
2068 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2069 uses this information. Hence, the general register <-> floating point
2070 register information here is not used for SFmode. */
2071
2072 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2073 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \
2074 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2075
2076 #define REGCLASS_HAS_FP_REG(CLASS) \
2077 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2078 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2079
2080 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2081 would be so that people with slow memory systems could generate
2082 different code that does fewer memory accesses. */
2083
2084 /* A C expression for the cost of a branch instruction. A value of 1
2085 is the default; other values are interpreted relative to that. */
2086 #define BRANCH_COST(speed_p, predictable_p) sh_branch_cost
2087 \f
2088 /* Assembler output control. */
2089
2090 /* A C string constant describing how to begin a comment in the target
2091 assembler language. The compiler assumes that the comment will end at
2092 the end of the line. */
2093 #define ASM_COMMENT_START "!"
2094
2095 #define ASM_APP_ON ""
2096 #define ASM_APP_OFF ""
2097 #define FILE_ASM_OP "\t.file\n"
2098 #define SET_ASM_OP "\t.set\t"
2099
2100 /* How to change between sections. */
2101
2102 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2103 #define DATA_SECTION_ASM_OP "\t.data"
2104
2105 #if defined CRT_BEGIN || defined CRT_END
2106 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2107 # undef TEXT_SECTION_ASM_OP
2108 # if __SHMEDIA__ == 1 && __SH5__ == 32
2109 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2110 # else
2111 # define TEXT_SECTION_ASM_OP "\t.text"
2112 # endif
2113 #endif
2114
2115 #ifndef BSS_SECTION_ASM_OP
2116 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2117 #endif
2118
2119 #ifndef ASM_OUTPUT_ALIGNED_BSS
2120 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2121 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2122 #endif
2123
2124 /* Define this so that jump tables go in same section as the current function,
2125 which could be text or it could be a user defined section. */
2126 #define JUMP_TABLES_IN_TEXT_SECTION 1
2127
2128 #undef DO_GLOBAL_CTORS_BODY
2129 #define DO_GLOBAL_CTORS_BODY \
2130 { \
2131 typedef void (*pfunc) (void); \
2132 extern pfunc __ctors[]; \
2133 extern pfunc __ctors_end[]; \
2134 pfunc *p; \
2135 for (p = __ctors_end; p > __ctors; ) \
2136 { \
2137 (*--p)(); \
2138 } \
2139 }
2140
2141 #undef DO_GLOBAL_DTORS_BODY
2142 #define DO_GLOBAL_DTORS_BODY \
2143 { \
2144 typedef void (*pfunc) (void); \
2145 extern pfunc __dtors[]; \
2146 extern pfunc __dtors_end[]; \
2147 pfunc *p; \
2148 for (p = __dtors; p < __dtors_end; p++) \
2149 { \
2150 (*p)(); \
2151 } \
2152 }
2153
2154 #define ASM_OUTPUT_REG_PUSH(file, v) \
2155 { \
2156 if (TARGET_SHMEDIA) \
2157 { \
2158 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2159 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2160 } \
2161 else \
2162 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2163 }
2164
2165 #define ASM_OUTPUT_REG_POP(file, v) \
2166 { \
2167 if (TARGET_SHMEDIA) \
2168 { \
2169 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2170 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2171 } \
2172 else \
2173 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2174 }
2175
2176 /* DBX register number for a given compiler register number. */
2177 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2178 to match gdb. */
2179 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2180 register exists, so we should return -1 for invalid register numbers. */
2181 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2182
2183 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2184 used to use the encodings 245..260, but that doesn't make sense:
2185 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2186 the FP registers stay the same when switching between compact and media
2187 mode. Hence, we also need to use the same dwarf frame columns.
2188 Likewise, we need to support unwind information for SHmedia registers
2189 even in compact code. */
2190 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2191 (IN_RANGE ((REGNO), \
2192 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2193 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2194 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2195 : ((int) (REGNO) >= FIRST_FP_REG \
2196 && ((int) (REGNO) \
2197 <= (FIRST_FP_REG + \
2198 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2199 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2200 + (TARGET_SH5 ? 77 : 25)) \
2201 : XD_REGISTER_P (REGNO) \
2202 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2203 : TARGET_REGISTER_P (REGNO) \
2204 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2205 : (REGNO) == PR_REG \
2206 ? (TARGET_SH5 ? 18 : 17) \
2207 : (REGNO) == PR_MEDIA_REG \
2208 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2209 : (REGNO) == GBR_REG \
2210 ? (TARGET_SH5 ? 238 : 18) \
2211 : (REGNO) == MACH_REG \
2212 ? (TARGET_SH5 ? 239 : 20) \
2213 : (REGNO) == MACL_REG \
2214 ? (TARGET_SH5 ? 240 : 21) \
2215 : (REGNO) == T_REG \
2216 ? (TARGET_SH5 ? 242 : 22) \
2217 : (REGNO) == FPUL_REG \
2218 ? (TARGET_SH5 ? 244 : 23) \
2219 : (REGNO) == FPSCR_REG \
2220 ? (TARGET_SH5 ? 243 : 24) \
2221 : (unsigned) -1)
2222
2223 /* This is how to output a reference to a symbol_ref. On SH5,
2224 references to non-code symbols must be preceded by `datalabel'. */
2225 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2226 do \
2227 { \
2228 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2229 fputs ("datalabel ", (FILE)); \
2230 assemble_name ((FILE), XSTR ((SYM), 0)); \
2231 } \
2232 while (0)
2233
2234 /* This is how to output an assembler line
2235 that says to advance the location counter
2236 to a multiple of 2**LOG bytes. */
2237
2238 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2239 if ((LOG) != 0) \
2240 fprintf ((FILE), "\t.align %d\n", (LOG))
2241
2242 /* Globalizing directive for a label. */
2243 #define GLOBAL_ASM_OP "\t.global\t"
2244
2245 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2246
2247 /* Output a relative address table. */
2248
2249 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2250 switch (GET_MODE (BODY)) \
2251 { \
2252 case SImode: \
2253 if (TARGET_SH5) \
2254 { \
2255 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2256 (VALUE), (REL)); \
2257 break; \
2258 } \
2259 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2260 break; \
2261 case HImode: \
2262 if (TARGET_SH5) \
2263 { \
2264 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2265 (VALUE), (REL)); \
2266 break; \
2267 } \
2268 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2269 break; \
2270 case QImode: \
2271 if (TARGET_SH5) \
2272 { \
2273 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2274 (VALUE), (REL)); \
2275 break; \
2276 } \
2277 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2278 break; \
2279 default: \
2280 break; \
2281 }
2282
2283 /* Output an absolute table element. */
2284
2285 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2286 if (! optimize || TARGET_BIGTABLE) \
2287 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2288 else \
2289 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2290
2291 \f
2292 /* A C statement to be executed just prior to the output of
2293 assembler code for INSN, to modify the extracted operands so
2294 they will be output differently.
2295
2296 Here the argument OPVEC is the vector containing the operands
2297 extracted from INSN, and NOPERANDS is the number of elements of
2298 the vector which contain meaningful data for this insn.
2299 The contents of this vector are what will be used to convert the insn
2300 template into assembler code, so you can change the assembler output
2301 by changing the contents of the vector. */
2302
2303 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2304 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2305
2306 \f
2307 extern rtx sh_compare_op0;
2308 extern rtx sh_compare_op1;
2309
2310 /* Which processor to schedule for. The elements of the enumeration must
2311 match exactly the cpu attribute in the sh.md file. */
2312
2313 enum processor_type {
2314 PROCESSOR_SH1,
2315 PROCESSOR_SH2,
2316 PROCESSOR_SH2E,
2317 PROCESSOR_SH2A,
2318 PROCESSOR_SH3,
2319 PROCESSOR_SH3E,
2320 PROCESSOR_SH4,
2321 PROCESSOR_SH4A,
2322 PROCESSOR_SH5
2323 };
2324
2325 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2326 extern enum processor_type sh_cpu;
2327
2328 enum mdep_reorg_phase_e
2329 {
2330 SH_BEFORE_MDEP_REORG,
2331 SH_INSERT_USES_LABELS,
2332 SH_SHORTEN_BRANCHES0,
2333 SH_FIXUP_PCLOAD,
2334 SH_SHORTEN_BRANCHES1,
2335 SH_AFTER_MDEP_REORG
2336 };
2337
2338 extern enum mdep_reorg_phase_e mdep_reorg_phase;
2339
2340 /* Handle Renesas compiler's pragmas. */
2341 #define REGISTER_TARGET_PRAGMAS() do { \
2342 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
2343 c_register_pragma (0, "trapa", sh_pr_trapa); \
2344 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
2345 } while (0)
2346
2347 extern tree sh_deferred_function_attributes;
2348 extern tree *sh_deferred_function_attributes_tail;
2349
2350 /* Set when processing a function with interrupt attribute. */
2351
2352 extern int current_function_interrupt;
2353
2354 \f
2355 /* Instructions with unfilled delay slots take up an
2356 extra two bytes for the nop in the delay slot.
2357 sh-dsp parallel processing insns are four bytes long. */
2358
2359 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2360 (LENGTH) += sh_insn_length_adjustment (X);
2361 \f
2362 /* Define this macro if it is advisable to hold scalars in registers
2363 in a wider mode than that declared by the program. In such cases,
2364 the value is constrained to be within the bounds of the declared
2365 type, but kept valid in the wider mode. The signedness of the
2366 extension may differ from that of the type.
2367
2368 Leaving the unsignedp unchanged gives better code than always setting it
2369 to 0. This is despite the fact that we have only signed char and short
2370 load instructions. */
2371 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2372 if (GET_MODE_CLASS (MODE) == MODE_INT \
2373 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
2374 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
2375 (MODE) = (TARGET_SH1 ? SImode \
2376 : TARGET_SHMEDIA32 ? SImode : DImode);
2377
2378 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
2379
2380 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
2381
2382 /* Better to allocate once the maximum space for outgoing args in the
2383 prologue rather than duplicate around each call. */
2384 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
2385
2386 #define SH_DYNAMIC_SHIFT_COST \
2387 (TARGET_HARD_SH4 ? 1 \
2388 : (TARGET_SH3 || TARGET_SH2A) ? (optimize_size ? 1 : 2) : 20)
2389
2390
2391 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2392
2393 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
2394
2395 #define ACTUAL_NORMAL_MODE(ENTITY) \
2396 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2397
2398 #define NORMAL_MODE(ENTITY) \
2399 (sh_cfun_interrupt_handler_p () \
2400 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
2401 : ACTUAL_NORMAL_MODE (ENTITY))
2402
2403 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
2404
2405 #define MODE_EXIT(ENTITY) \
2406 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
2407
2408 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
2409 && (REGNO) == FPSCR_REG)
2410
2411 #define MODE_NEEDED(ENTITY, INSN) \
2412 (recog_memoized (INSN) >= 0 \
2413 ? get_attr_fp_mode (INSN) \
2414 : FP_MODE_NONE)
2415
2416 #define MODE_AFTER(MODE, INSN) \
2417 (TARGET_HITACHI \
2418 && recog_memoized (INSN) >= 0 \
2419 && get_attr_fp_set (INSN) != FP_SET_NONE \
2420 ? (int) get_attr_fp_set (INSN) \
2421 : (MODE))
2422
2423 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2424 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2425
2426 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2427 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2428
2429 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
2430 sh_can_redirect_branch ((INSN), (SEQ))
2431
2432 #define DWARF_FRAME_RETURN_COLUMN \
2433 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
2434
2435 #define EH_RETURN_DATA_REGNO(N) \
2436 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
2437
2438 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
2439 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
2440
2441 /* We have to distinguish between code and data, so that we apply
2442 datalabel where and only where appropriate. Use sdataN for data. */
2443 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2444 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
2445 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
2446 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
2447
2448 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2449 indirect are handled automatically. */
2450 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2451 do { \
2452 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
2453 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
2454 { \
2455 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
2456 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
2457 if (0) goto DONE; \
2458 } \
2459 } while (0)
2460
2461 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
2462 /* SH constant pool breaks the devices in crtstuff.c to control section
2463 in where code resides. We have to write it as asm code. */
2464 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2465 asm (SECTION_OP "\n\
2466 mov.l 1f,r1\n\
2467 mova 2f,r0\n\
2468 braf r1\n\
2469 lds r0,pr\n\
2470 0: .p2align 2\n\
2471 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
2472 2:\n" TEXT_SECTION_ASM_OP);
2473 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
2474
2475 /* FIXME: middle-end support for highpart optimizations is missing. */
2476 #define high_life_started reload_in_progress
2477
2478 #endif /* ! GCC_SH_H */
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