| blob | 60a724595817a246a8f84514939cf81408481a7e |
1 /* Definitions of target machine for GNU compiler, for the HP Spectrum.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
5 and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
6 Software Science at the University of Utah.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
26 {
30 CMP_MAX /* max comparison type */
31 };
33 /* For long call handling. */
36 /* Which processor to schedule for. */
38 enum processor_type
39 {
40 PROCESSOR_700,
41 PROCESSOR_7100,
42 PROCESSOR_7100LC,
43 PROCESSOR_7200,
44 PROCESSOR_7300,
45 PROCESSOR_8000
46 };
48 /* For -mschedule= option. */
51 /* For -munix= option. */
54 #define pa_cpu_attr ((enum attr_cpu)pa_cpu)
56 /* Print subsidiary information on the compiler version in use. */
60 #define TARGET_PA_10 (!TARGET_PA_11 && !TARGET_PA_20)
62 /* Generate code for the HPPA 2.0 architecture in 64bit mode. */
63 #ifndef TARGET_64BIT
64 #define TARGET_64BIT 0
65 #endif
67 /* Generate code for ELF32 ABI. */
68 #ifndef TARGET_ELF32
69 #define TARGET_ELF32 0
70 #endif
72 /* Generate code for SOM 32bit ABI. */
73 #ifndef TARGET_SOM
74 #define TARGET_SOM 0
75 #endif
77 /* HP-UX UNIX features. */
78 #ifndef TARGET_HPUX
79 #define TARGET_HPUX 0
80 #endif
82 /* HP-UX 10.10 UNIX 95 features. */
83 #ifndef TARGET_HPUX_10_10
84 #define TARGET_HPUX_10_10 0
85 #endif
87 /* HP-UX 11.* features (11.00, 11.11, 11.23, etc.) */
88 #ifndef TARGET_HPUX_11
89 #define TARGET_HPUX_11 0
90 #endif
92 /* HP-UX 11i multibyte and UNIX 98 extensions. */
93 #ifndef TARGET_HPUX_11_11
94 #define TARGET_HPUX_11_11 0
95 #endif
97 /* The following three defines are potential target switches. The current
98 defines are optimal given the current capabilities of GAS and GNU ld. */
100 /* Define to a C expression evaluating to true to use long absolute calls.
101 Currently, only the HP assembler and SOM linker support long absolute
102 calls. They are used only in non-pic code. */
103 #define TARGET_LONG_ABS_CALL (TARGET_SOM && !TARGET_GAS)
105 /* Define to a C expression evaluating to true to use long pic symbol
106 difference calls. This is a call variant similar to the long pic
107 pc-relative call. Long pic symbol difference calls are only used with
108 the HP SOM linker. Currently, only the HP assembler supports these
109 calls. GAS doesn't allow an arbitrary difference of two symbols. */
110 #define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS)
112 /* Define to a C expression evaluating to true to use long pic
113 pc-relative calls. Long pic pc-relative calls are only used with
114 GAS. Currently, they are usable for calls within a module but
115 not for external calls. */
116 #define TARGET_LONG_PIC_PCREL_CALL 0
118 /* Define to a C expression evaluating to true to use SOM secondary
119 definition symbols for weak support. Linker support for secondary
120 definition symbols is buggy prior to HP-UX 11.X. */
121 #define TARGET_SOM_SDEF 0
123 /* Define to a C expression evaluating to true to save the entry value
124 of SP in the current frame marker. This is normally unnecessary.
125 However, the HP-UX unwind library looks at the SAVE_SP callinfo flag.
126 HP compilers don't use this flag but it is supported by the assembler.
127 We set this flag to indicate that register %r3 has been saved at the
128 start of the frame. Thus, when the HP unwind library is used, we
129 need to generate additional code to save SP into the frame marker. */
130 #define TARGET_HPUX_UNWIND_LIBRARY 0
132 #ifndef TARGET_DEFAULT
133 #define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY | MASK_BIG_SWITCH)
134 #endif
136 #ifndef TARGET_CPU_DEFAULT
137 #define TARGET_CPU_DEFAULT 0
138 #endif
140 #ifndef TARGET_SCHED_DEFAULT
141 #define TARGET_SCHED_DEFAULT PROCESSOR_8000
142 #endif
144 /* Support for a compile-time default CPU, et cetera. The rules are:
145 --with-schedule is ignored if -mschedule is specified.
146 --with-arch is ignored if -march is specified. */
147 #define OPTION_DEFAULT_SPECS \
151 /* Specify the dialect of assembler to use. New mnemonics is dialect one
152 and the old mnemonics are dialect zero. */
153 #define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
155 #define OVERRIDE_OPTIONS override_options ()
157 /* Override some settings from dbxelf.h. */
159 /* We do not have to be compatible with dbx, so we enable gdb extensions
160 by default. */
161 #define DEFAULT_GDB_EXTENSIONS 1
163 /* This used to be zero (no max length), but big enums and such can
164 cause huge strings which killed gas.
166 We also have to avoid lossage in dbxout.c -- it does not compute the
167 string size accurately, so we are real conservative here. */
168 #undef DBX_CONTIN_LENGTH
169 #define DBX_CONTIN_LENGTH 3000
171 /* GDB always assumes the current function's frame begins at the value
172 of the stack pointer upon entry to the current function. Accessing
173 local variables and parameters passed on the stack is done using the
174 base of the frame + an offset provided by GCC.
176 For functions which have frame pointers this method works fine;
177 the (frame pointer) == (stack pointer at function entry) and GCC provides
178 an offset relative to the frame pointer.
180 This loses for functions without a frame pointer; GCC provides an offset
181 which is relative to the stack pointer after adjusting for the function's
182 frame size. GDB would prefer the offset to be relative to the value of
183 the stack pointer at the function's entry. Yuk! */
184 #define DEBUGGER_AUTO_OFFSET(X) \
185 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
186 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
188 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
189 ((GET_CODE (X) == PLUS ? OFFSET : 0) \
190 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
192 #define TARGET_CPU_CPP_BUILTINS() \
193 do { \
198 if (TARGET_PA_20) \
200 else if (TARGET_PA_11) \
202 else \
204 } while (0)
206 /* An old set of OS defines for various BSD-like systems. */
207 #define TARGET_OS_CPP_BUILTINS() \
208 do \
209 { \
214 if (!c_dialect_cxx () && !flag_iso) \
220 } \
221 while (0)
227 /* We don't want -lg. */
228 #ifndef LIB_SPEC
230 #endif
232 /* This macro defines command-line switches that modify the default
233 target name.
235 The definition is be an initializer for an array of structures. Each
236 array element has have three elements: the switch name, one of the
237 enumeration codes ADD or DELETE to indicate whether the string should be
238 inserted or deleted, and the string to be inserted or deleted. */
241 /* Make gcc agree with <machine/ansi.h> */
246 #define WCHAR_TYPE_SIZE 32
248 /* Show we can debug even without a frame pointer. */
249 #define CAN_DEBUG_WITHOUT_FP
250 \f
251 /* target machine storage layout */
253 {
254 /* Flag indicating that a .NSUBSPA directive has been output for
255 this function. */
259 /* Define this macro if it is advisable to hold scalars in registers
260 in a wider mode than that declared by the program. In such cases,
261 the value is constrained to be within the bounds of the declared
262 type, but kept valid in the wider mode. The signedness of the
263 extension may differ from that of the type. */
265 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
266 if (GET_MODE_CLASS (MODE) == MODE_INT \
267 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
268 (MODE) = word_mode;
270 /* Define this if most significant bit is lowest numbered
271 in instructions that operate on numbered bit-fields. */
272 #define BITS_BIG_ENDIAN 1
274 /* Define this if most significant byte of a word is the lowest numbered. */
275 /* That is true on the HP-PA. */
276 #define BYTES_BIG_ENDIAN 1
278 /* Define this if most significant word of a multiword number is lowest
279 numbered. */
280 #define WORDS_BIG_ENDIAN 1
282 #define MAX_BITS_PER_WORD 64
284 /* Width of a word, in units (bytes). */
285 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
287 /* Minimum number of units in a word. If this is undefined, the default
288 is UNITS_PER_WORD. Otherwise, it is the constant value that is the
289 smallest value that UNITS_PER_WORD can have at run-time.
291 FIXME: This needs to be 4 when TARGET_64BIT is true to suppress the
292 building of various TImode routines in libgcc. The HP runtime
293 specification doesn't provide the alignment requirements and calling
294 conventions for TImode variables. */
295 #define MIN_UNITS_PER_WORD 4
297 /* The widest floating point format supported by the hardware. Note that
298 setting this influences some Ada floating point type sizes, currently
299 required for GNAT to operate properly. */
300 #define WIDEST_HARDWARE_FP_SIZE 64
302 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
303 #define PARM_BOUNDARY BITS_PER_WORD
305 /* Largest alignment required for any stack parameter, in bits.
306 Don't define this if it is equal to PARM_BOUNDARY */
307 #define MAX_PARM_BOUNDARY BIGGEST_ALIGNMENT
309 /* Boundary (in *bits*) on which stack pointer is always aligned;
310 certain optimizations in combine depend on this.
312 The HP-UX runtime documents mandate 64-byte and 16-byte alignment for
313 the stack on the 32 and 64-bit ports, respectively. However, we
314 are only guaranteed that the stack is aligned to BIGGEST_ALIGNMENT
315 in main. Thus, we treat the former as the preferred alignment. */
316 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
317 #define PREFERRED_STACK_BOUNDARY (TARGET_64BIT ? 128 : 512)
319 /* Allocation boundary (in *bits*) for the code of a function. */
320 #define FUNCTION_BOUNDARY BITS_PER_WORD
322 /* Alignment of field after `int : 0' in a structure. */
323 #define EMPTY_FIELD_BOUNDARY 32
325 /* Every structure's size must be a multiple of this. */
326 #define STRUCTURE_SIZE_BOUNDARY 8
328 /* A bit-field declared as `int' forces `int' alignment for the struct. */
329 #define PCC_BITFIELD_TYPE_MATTERS 1
331 /* No data type wants to be aligned rounder than this. */
332 #define BIGGEST_ALIGNMENT (2 * BITS_PER_WORD)
334 /* Get around hp-ux assembler bug, and make strcpy of constants fast. */
335 #define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
336 ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
338 /* Make arrays of chars word-aligned for the same reasons. */
339 #define DATA_ALIGNMENT(TYPE, ALIGN) \
340 (TREE_CODE (TYPE) == ARRAY_TYPE \
341 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
342 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
344 /* Set this nonzero if move instructions will actually fail to work
345 when given unaligned data. */
346 #define STRICT_ALIGNMENT 1
348 /* Value is 1 if it is a good idea to tie two pseudo registers
349 when one has mode MODE1 and one has mode MODE2.
350 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
351 for any hard reg, then this must be 0 for correct output. */
352 #define MODES_TIEABLE_P(MODE1, MODE2) \
353 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
355 /* Specify the registers used for certain standard purposes.
356 The values of these macros are register numbers. */
358 /* The HP-PA pc isn't overloaded on a register that the compiler knows about. */
359 /* #define PC_REGNUM */
361 /* Register to use for pushing function arguments. */
362 #define STACK_POINTER_REGNUM 30
364 /* Base register for access to local variables of the function. */
365 #define FRAME_POINTER_REGNUM 3
367 /* Value should be nonzero if functions must have frame pointers. */
368 #define FRAME_POINTER_REQUIRED \
369 (current_function_calls_alloca)
371 /* Don't allow hard registers to be renamed into r2 unless r2
372 is already live or already being saved (due to eh). */
374 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
375 ((NEW_REG) != 2 || regs_ever_live[2] || current_function_calls_eh_return)
377 /* C statement to store the difference between the frame pointer
378 and the stack pointer values immediately after the function prologue.
380 Note, we always pretend that this is a leaf function because if
381 it's not, there's no point in trying to eliminate the
382 frame pointer. If it is a leaf function, we guessed right! */
383 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
384 do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0)
386 /* Base register for access to arguments of the function. */
387 #define ARG_POINTER_REGNUM (TARGET_64BIT ? 29 : 3)
389 /* Register in which static-chain is passed to a function. */
390 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? 31 : 29)
392 /* Register used to address the offset table for position-independent
393 data references. */
394 #define PIC_OFFSET_TABLE_REGNUM \
395 (flag_pic ? (TARGET_64BIT ? 27 : 19) : INVALID_REGNUM)
397 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
399 /* Function to return the rtx used to save the pic offset table register
400 across function calls. */
403 #define DEFAULT_PCC_STRUCT_RETURN 0
405 /* Register in which address to store a structure value
406 is passed to a function. */
407 #define PA_STRUCT_VALUE_REGNUM 28
409 /* Describe how we implement __builtin_eh_return. */
410 #define EH_RETURN_DATA_REGNO(N) \
411 ((N) < 3 ? (N) + 20 : (N) == 3 ? 31 : INVALID_REGNUM)
412 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29)
413 #define EH_RETURN_HANDLER_RTX \
414 gen_rtx_MEM (word_mode, \
415 gen_rtx_PLUS (word_mode, frame_pointer_rtx, \
416 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20)))
418 /* Offset from the frame pointer register value to the top of stack. */
419 #define FRAME_POINTER_CFA_OFFSET(FNDECL) 0
421 /* A C expression whose value is RTL representing the location of the
422 incoming return address at the beginning of any function, before the
423 prologue. You only need to define this macro if you want to support
424 call frame debugging information like that provided by DWARF 2. */
425 #define INCOMING_RETURN_ADDR_RTX (gen_rtx_REG (word_mode, 2))
426 #define DWARF_FRAME_RETURN_COLUMN (DWARF_FRAME_REGNUM (2))
428 /* A C expression whose value is an integer giving a DWARF 2 column
429 number that may be used as an alternate return column. This should
430 be defined only if DWARF_FRAME_RETURN_COLUMN is set to a general
431 register, but an alternate column needs to be used for signal frames.
433 Column 0 is not used but unfortunately its register size is set to
434 4 bytes (sizeof CCmode) so it can't be used on 64-bit targets. */
435 #define DWARF_ALT_FRAME_RETURN_COLUMN FIRST_PSEUDO_REGISTER
437 /* This macro chooses the encoding of pointers embedded in the exception
438 handling sections. If at all possible, this should be defined such
439 that the exception handling section will not require dynamic relocations,
440 and so may be read-only.
442 Because the HP assembler auto aligns, it is necessary to use
443 DW_EH_PE_aligned. It's not possible to make the data read-only
444 on the HP-UX SOM port since the linker requires fixups for label
445 differences in different sections to be word aligned. However,
446 the SOM linker can do unaligned fixups for absolute pointers.
447 We also need aligned pointers for global and function pointers.
449 Although the HP-UX 64-bit ELF linker can handle unaligned pc-relative
450 fixups, the runtime doesn't have a consistent relationship between
451 text and data for dynamically loaded objects. Thus, it's not possible
452 to use pc-relative encoding for pointers on this target. It may be
453 possible to use segment relative encodings but GAS doesn't currently
454 have a mechanism to generate these encodings. For other targets, we
455 use pc-relative encoding for pointers. If the pointer might require
456 dynamic relocation, we make it indirect. */
457 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
458 (TARGET_GAS && !TARGET_HPUX \
459 ? (DW_EH_PE_pcrel \
460 | ((GLOBAL) || (CODE) == 2 ? DW_EH_PE_indirect : 0) \
461 | (TARGET_64BIT ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)) \
462 : (!TARGET_GAS || (GLOBAL) || (CODE) == 2 \
463 ? DW_EH_PE_aligned : DW_EH_PE_absptr))
465 /* Handle special EH pointer encodings. Absolute, pc-relative, and
466 indirect are handled automatically. We output pc-relative, and
467 indirect pc-relative ourself since we need some special magic to
468 generate pc-relative relocations, and to handle indirect function
469 pointers. */
470 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
471 do { \
472 if (((ENCODING) & 0x70) == DW_EH_PE_pcrel) \
473 { \
474 fputs (integer_asm_op (SIZE, FALSE), FILE); \
475 if ((ENCODING) & DW_EH_PE_indirect) \
476 output_addr_const (FILE, get_deferred_plabel (ADDR)); \
477 else \
478 assemble_name (FILE, XSTR ((ADDR), 0)); \
480 goto DONE; \
481 } \
482 } while (0)
483 \f
484 /* The letters I, J, K, L and M in a register constraint string
485 can be used to stand for particular ranges of immediate operands.
486 This macro defines what the ranges are.
487 C is the letter, and VALUE is a constant value.
488 Return 1 if VALUE is in the range specified by C.
490 `I' is used for the 11-bit constants.
491 `J' is used for the 14-bit constants.
492 `K' is used for values that can be moved with a zdepi insn.
493 `L' is used for the 5-bit constants.
494 `M' is used for 0.
495 `N' is used for values with the least significant 11 bits equal to zero
496 and when sign extended from 32 to 64 bits the
497 value does not change.
498 `O' is used for numbers n such that n+1 is a power of 2.
499 */
501 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
508 || (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) \
509 == (HOST_WIDE_INT) -1 << 31)) \
512 : 0)
514 /* Similar, but for floating or large integer constants, and defining letters
515 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
517 For PA, `G' is the floating-point constant zero. `H' is undefined. */
519 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
521 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
522 : 0)
524 /* The class value for index registers, and the one for base regs. */
525 #define INDEX_REG_CLASS GENERAL_REGS
526 #define BASE_REG_CLASS GENERAL_REGS
528 #define FP_REG_CLASS_P(CLASS) \
529 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
531 /* True if register is floating-point. */
532 #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
534 /* Given an rtx X being reloaded into a reg required to be
535 in class CLASS, return the class of reg to actually use.
536 In general this is just CLASS; but on some machines
537 in some cases it is preferable to use a more restrictive class. */
538 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
540 #define MAYBE_FP_REG_CLASS_P(CLASS) \
541 reg_classes_intersect_p ((CLASS), FP_REGS)
543 /* On the PA it is not possible to directly move data between
544 GENERAL_REGS and FP_REGS. On the 32-bit port, we use the
545 location at SP-16. We don't expose this location in the RTL to
546 avoid scheduling related problems. For example, the store and
547 load could be separated by a call to a pure or const function
548 which has no frame and uses SP-16. */
549 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
550 (TARGET_64BIT \
551 && (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \
552 || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1)))
554 \f
555 /* Stack layout; function entry, exit and calling. */
557 /* Define this if pushing a word on the stack
558 makes the stack pointer a smaller address. */
559 /* #define STACK_GROWS_DOWNWARD */
561 /* Believe it or not. */
562 #define ARGS_GROW_DOWNWARD
564 /* Define this to nonzero if the nominal address of the stack frame
565 is at the high-address end of the local variables;
566 that is, each additional local variable allocated
567 goes at a more negative offset in the frame. */
568 #define FRAME_GROWS_DOWNWARD 0
570 /* Offset within stack frame to start allocating local variables at.
571 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
572 first local allocated. Otherwise, it is the offset to the BEGINNING
573 of the first local allocated.
575 On the 32-bit ports, we reserve one slot for the previous frame
576 pointer and one fill slot. The fill slot is for compatibility
577 with HP compiled programs. On the 64-bit ports, we reserve one
578 slot for the previous frame pointer. */
579 #define STARTING_FRAME_OFFSET 8
581 /* Define STACK_ALIGNMENT_NEEDED to zero to disable final alignment
582 of the stack. The default is to align it to STACK_BOUNDARY. */
583 #define STACK_ALIGNMENT_NEEDED 0
585 /* If we generate an insn to push BYTES bytes,
586 this says how many the stack pointer really advances by.
587 On the HP-PA, don't define this because there are no push insns. */
588 /* #define PUSH_ROUNDING(BYTES) */
590 /* Offset of first parameter from the argument pointer register value.
591 This value will be negated because the arguments grow down.
592 Also note that on STACK_GROWS_UPWARD machines (such as this one)
593 this is the distance from the frame pointer to the end of the first
594 argument, not it's beginning. To get the real offset of the first
595 argument, the size of the argument must be added. */
597 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_64BIT ? -64 : -32)
599 /* When a parameter is passed in a register, stack space is still
600 allocated for it. */
601 #define REG_PARM_STACK_SPACE(DECL) (TARGET_64BIT ? 64 : 16)
603 /* Define this if the above stack space is to be considered part of the
604 space allocated by the caller. */
605 #define OUTGOING_REG_PARM_STACK_SPACE
607 /* Keep the stack pointer constant throughout the function.
608 This is both an optimization and a necessity: longjmp
609 doesn't behave itself when the stack pointer moves within
610 the function! */
611 #define ACCUMULATE_OUTGOING_ARGS 1
613 /* The weird HPPA calling conventions require a minimum of 48 bytes on
614 the stack: 16 bytes for register saves, and 32 bytes for magic.
615 This is the difference between the logical top of stack and the
616 actual sp.
618 On the 64-bit port, the HP C compiler allocates a 48-byte frame
619 marker, although the runtime documentation only describes a 16
620 byte marker. For compatibility, we allocate 48 bytes. */
621 #define STACK_POINTER_OFFSET \
622 (TARGET_64BIT ? -(current_function_outgoing_args_size + 48): -32)
624 #define STACK_DYNAMIC_OFFSET(FNDECL) \
625 (TARGET_64BIT \
626 ? (STACK_POINTER_OFFSET) \
627 : ((STACK_POINTER_OFFSET) - current_function_outgoing_args_size))
629 /* Value is 1 if returning from a function call automatically
630 pops the arguments described by the number-of-args field in the call.
631 FUNDECL is the declaration node of the function (as a tree),
632 FUNTYPE is the data type of the function (as a tree),
633 or for a library call it is an identifier node for the subroutine name. */
635 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
637 /* Define how to find the value returned by a function.
638 VALTYPE is the data type of the value (as a tree).
639 If the precise function being called is known, FUNC is its FUNCTION_DECL;
640 otherwise, FUNC is 0. */
642 #define FUNCTION_VALUE(VALTYPE, FUNC) function_value (VALTYPE, FUNC)
644 /* Define how to find the value returned by a library function
645 assuming the value has mode MODE. */
647 #define LIBCALL_VALUE(MODE) \
648 gen_rtx_REG (MODE, \
649 (! TARGET_SOFT_FLOAT \
650 && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
652 /* 1 if N is a possible register number for a function value
653 as seen by the caller. */
655 #define FUNCTION_VALUE_REGNO_P(N) \
656 ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32))
658 \f
659 /* Define a data type for recording info about an argument list
660 during the scan of that argument list. This data type should
661 hold all necessary information about the function itself
662 and about the args processed so far, enough to enable macros
663 such as FUNCTION_ARG to determine where the next arg should go.
665 On the HP-PA, the WORDS field holds the number of words
666 of arguments scanned so far (including the invisible argument,
667 if any, which holds the structure-value-address). Thus, 4 or
668 more means all following args should go on the stack.
670 The INCOMING field tracks whether this is an "incoming" or
671 "outgoing" argument.
673 The INDIRECT field indicates whether this is is an indirect
674 call or not.
676 The NARGS_PROTOTYPE field indicates that an argument does not
677 have a prototype when it less than or equal to 0. */
681 #define CUMULATIVE_ARGS struct hppa_args
683 /* Initialize a variable CUM of type CUMULATIVE_ARGS
684 for a call to a function whose data type is FNTYPE.
685 For a library call, FNTYPE is 0. */
687 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
688 (CUM).words = 0, \
689 (CUM).incoming = 0, \
690 (CUM).indirect = (FNTYPE) && !(FNDECL), \
691 (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \
692 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \
693 + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
694 || pa_return_in_memory (TREE_TYPE (FNTYPE), 0))) \
695 : 0)
699 /* Similar, but when scanning the definition of a procedure. We always
700 set NARGS_PROTOTYPE large so we never return a PARALLEL. */
702 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
703 (CUM).words = 0, \
704 (CUM).incoming = 1, \
705 (CUM).indirect = 0, \
706 (CUM).nargs_prototype = 1000
708 /* Figure out the size in words of the function argument. The size
709 returned by this macro should always be greater than zero because
710 we pass variable and zero sized objects by reference. */
712 #define FUNCTION_ARG_SIZE(MODE, TYPE) \
713 ((((MODE) != BLKmode \
714 ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
715 : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
717 /* Update the data in CUM to advance over an argument
718 of mode MODE and data type TYPE.
719 (TYPE is null for libcalls where that information may not be available.) */
721 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
722 { (CUM).nargs_prototype--; \
723 (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE) \
724 + (((CUM).words & 01) && (TYPE) != 0 \
725 && FUNCTION_ARG_SIZE(MODE, TYPE) > 1); \
726 }
728 /* Determine where to put an argument to a function.
729 Value is zero to push the argument on the stack,
730 or a hard register in which to store the argument.
732 MODE is the argument's machine mode.
733 TYPE is the data type of the argument (as a tree).
734 This is null for libcalls where that information may
735 not be available.
736 CUM is a variable of type CUMULATIVE_ARGS which gives info about
737 the preceding args and about the function being called.
738 NAMED is nonzero if this argument is a named parameter
739 (otherwise it is an extra parameter matching an ellipsis).
741 On the HP-PA the first four words of args are normally in registers
742 and the rest are pushed. But any arg that won't entirely fit in regs
743 is pushed.
745 Arguments passed in registers are either 1 or 2 words long.
747 The caller must make a distinction between calls to explicitly named
748 functions and calls through pointers to functions -- the conventions
749 are different! Calls through pointers to functions only use general
750 registers for the first four argument words.
752 Of course all this is different for the portable runtime model
753 HP wants everyone to use for ELF. Ugh. Here's a quick description
754 of how it's supposed to work.
756 1) callee side remains unchanged. It expects integer args to be
757 in the integer registers, float args in the float registers and
758 unnamed args in integer registers.
760 2) caller side now depends on if the function being called has
761 a prototype in scope (rather than if it's being called indirectly).
763 2a) If there is a prototype in scope, then arguments are passed
764 according to their type (ints in integer registers, floats in float
765 registers, unnamed args in integer registers.
767 2b) If there is no prototype in scope, then floating point arguments
768 are passed in both integer and float registers. egad.
770 FYI: The portable parameter passing conventions are almost exactly like
771 the standard parameter passing conventions on the RS6000. That's why
772 you'll see lots of similar code in rs6000.h. */
774 /* If defined, a C expression which determines whether, and in which
775 direction, to pad out an argument with extra space. */
776 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
778 /* Specify padding for the last element of a block move between registers
779 and memory.
781 The 64-bit runtime specifies that objects need to be left justified
782 (i.e., the normal justification for a big endian target). The 32-bit
783 runtime specifies right justification for objects smaller than 64 bits.
784 We use a DImode register in the parallel for 5 to 7 byte structures
785 so that there is only one element. This allows the object to be
786 correctly padded. */
787 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
788 function_arg_padding ((MODE), (TYPE))
790 /* Do not expect to understand this without reading it several times. I'm
791 tempted to try and simply it, but I worry about breaking something. */
793 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
794 function_arg (&CUM, MODE, TYPE, NAMED)
796 /* If defined, a C expression that gives the alignment boundary, in
797 bits, of an argument with the specified mode and type. If it is
798 not defined, `PARM_BOUNDARY' is used for all arguments. */
800 /* Arguments larger than one word are double word aligned. */
802 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
803 (((TYPE) \
804 ? (integer_zerop (TYPE_SIZE (TYPE)) \
805 || !TREE_CONSTANT (TYPE_SIZE (TYPE)) \
806 || int_size_in_bytes (TYPE) <= UNITS_PER_WORD) \
807 : GET_MODE_SIZE(MODE) <= UNITS_PER_WORD) \
808 ? PARM_BOUNDARY : MAX_PARM_BOUNDARY)
810 \f
815 /* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
816 as assembly via FUNCTION_PROFILER. Just output a local label.
817 We can't use the function label because the GAS SOM target can't
818 handle the difference of a global symbol and a local symbol. */
820 #ifndef FUNC_BEGIN_PROLOG_LABEL
822 #endif
824 #define FUNCTION_PROFILER(FILE, LABEL) \
825 (*targetm.asm_out.internal_label) (FILE, FUNC_BEGIN_PROLOG_LABEL, LABEL)
827 #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no)
830 /* The profile counter if emitted must come before the prologue. */
831 #define PROFILE_BEFORE_PROLOGUE 1
833 /* We never want final.c to emit profile counters. When profile
834 counters are required, we have to defer emitting them to the end
835 of the current file. */
836 #define NO_PROFILE_COUNTERS 1
838 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
839 the stack pointer does not matter. The value is tested only in
840 functions that have frame pointers.
841 No definition is equivalent to always zero. */
845 #define EXIT_IGNORE_STACK \
846 (get_frame_size () != 0 \
847 || current_function_calls_alloca || current_function_outgoing_args_size)
849 /* Output assembler code for a block containing the constant parts
850 of a trampoline, leaving space for the variable parts.\
852 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
853 and then branches to the specified routine.
855 This code template is copied from text segment to stack location
856 and then patched with INITIALIZE_TRAMPOLINE to contain
857 valid values, and then entered as a subroutine.
859 It is best to keep this as small as possible to avoid having to
860 flush multiple lines in the cache. */
862 #define TRAMPOLINE_TEMPLATE(FILE) \
863 { \
864 if (!TARGET_64BIT) \
865 { \
868 if (ASSEMBLER_DIALECT == 0) \
870 else \
874 if (TARGET_PA_20) \
875 { \
880 } \
881 else \
882 { \
887 } \
892 } \
893 else \
894 { \
907 } \
908 }
910 /* Length in units of the trampoline for entering a nested function. */
912 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)
914 /* Length in units of the trampoline instruction code. */
916 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
918 /* Minimum length of a cache line. A length of 16 will work on all
919 PA-RISC processors. All PA 1.1 processors have a cache line of
920 32 bytes. Most but not all PA 2.0 processors have a cache line
921 of 64 bytes. As cache flushes are expensive and we don't support
922 PA 1.0, we use a minimum length of 32. */
924 #define MIN_CACHELINE_SIZE 32
926 /* Emit RTL insns to initialize the variable parts of a trampoline.
927 FNADDR is an RTX for the address of the function's pure code.
928 CXT is an RTX for the static chain value for the function.
930 Move the function address to the trampoline template at offset 36.
931 Move the static chain value to trampoline template at offset 40.
932 Move the trampoline address to trampoline template at offset 44.
933 Move r19 to trampoline template at offset 48. The latter two
934 words create a plabel for the indirect call to the trampoline.
936 A similar sequence is used for the 64-bit port but the plabel is
937 at the beginning of the trampoline.
939 Finally, the cache entries for the trampoline code are flushed.
940 This is necessary to ensure that the trampoline instruction sequence
941 is written to memory prior to any attempts at prefetching the code
942 sequence. */
944 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
945 { \
946 rtx start_addr = gen_reg_rtx (Pmode); \
947 rtx end_addr = gen_reg_rtx (Pmode); \
948 rtx line_length = gen_reg_rtx (Pmode); \
949 rtx tmp; \
950 \
951 if (!TARGET_64BIT) \
952 { \
953 tmp = memory_address (Pmode, plus_constant ((TRAMP), 36)); \
954 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
955 tmp = memory_address (Pmode, plus_constant ((TRAMP), 40)); \
956 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
957 \
959 tmp = memory_address (Pmode, plus_constant ((TRAMP), 44)); \
960 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (TRAMP)); \
961 tmp = memory_address (Pmode, plus_constant ((TRAMP), 48)); \
962 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
963 gen_rtx_REG (Pmode, 19)); \
964 \
965 /* fdc and fic only use registers for the address to flush, \
966 they do not accept integer displacements. We align the \
967 start and end addresses to the beginning of their respective \
969 tmp = force_reg (Pmode, (TRAMP)); \
970 emit_insn (gen_andsi3 (start_addr, tmp, \
971 GEN_INT (-MIN_CACHELINE_SIZE))); \
972 tmp = force_reg (Pmode, \
973 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
974 emit_insn (gen_andsi3 (end_addr, tmp, \
975 GEN_INT (-MIN_CACHELINE_SIZE))); \
976 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
977 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
978 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
979 gen_reg_rtx (Pmode), \
980 gen_reg_rtx (Pmode))); \
981 } \
982 else \
983 { \
984 tmp = memory_address (Pmode, plus_constant ((TRAMP), 56)); \
985 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
986 tmp = memory_address (Pmode, plus_constant ((TRAMP), 64)); \
987 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
988 \
990 tmp = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
991 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
992 force_reg (Pmode, plus_constant ((TRAMP), 32))); \
993 tmp = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
994 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
995 gen_rtx_REG (Pmode, 27)); \
996 \
997 /* fdc and fic only use registers for the address to flush, \
998 they do not accept integer displacements. We align the \
999 start and end addresses to the beginning of their respective \
1001 tmp = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
1002 emit_insn (gen_anddi3 (start_addr, tmp, \
1003 GEN_INT (-MIN_CACHELINE_SIZE))); \
1004 tmp = force_reg (Pmode, \
1005 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
1006 emit_insn (gen_anddi3 (end_addr, tmp, \
1007 GEN_INT (-MIN_CACHELINE_SIZE))); \
1008 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
1009 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
1010 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
1011 gen_reg_rtx (Pmode), \
1012 gen_reg_rtx (Pmode))); \
1013 } \
1014 }
1016 /* Perform any machine-specific adjustment in the address of the trampoline.
1017 ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
1018 Adjust the trampoline address to point to the plabel at offset 44. */
1020 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
1021 if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))
1023 /* Implement `va_start' for varargs and stdarg. */
1025 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1026 hppa_va_start (valist, nextarg)
1027 \f
1028 /* Addressing modes, and classification of registers for them.
1030 Using autoincrement addressing modes on PA8000 class machines is
1031 not profitable. */
1033 #define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
1034 #define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)
1036 #define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
1037 #define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)
1039 /* Macros to check register numbers against specific register classes. */
1041 /* The following macros assume that X is a hard or pseudo reg number.
1042 They give nonzero only if X is a hard reg of the suitable class
1043 or a pseudo reg currently allocated to a suitable hard reg.
1044 Since they use reg_renumber, they are safe only once reg_renumber
1045 has been allocated, which happens in local-alloc.c. */
1047 #define REGNO_OK_FOR_INDEX_P(X) \
1048 ((X) && ((X) < 32 \
1049 || (X >= FIRST_PSEUDO_REGISTER \
1050 && reg_renumber \
1051 && (unsigned) reg_renumber[X] < 32)))
1052 #define REGNO_OK_FOR_BASE_P(X) \
1053 ((X) && ((X) < 32 \
1054 || (X >= FIRST_PSEUDO_REGISTER \
1055 && reg_renumber \
1056 && (unsigned) reg_renumber[X] < 32)))
1057 #define REGNO_OK_FOR_FP_P(X) \
1058 (FP_REGNO_P (X) \
1059 || (X >= FIRST_PSEUDO_REGISTER \
1060 && reg_renumber \
1061 && FP_REGNO_P (reg_renumber[X])))
1063 /* Now macros that check whether X is a register and also,
1064 strictly, whether it is in a specified class.
1066 These macros are specific to the HP-PA, and may be used only
1067 in code for printing assembler insns and in conditions for
1068 define_optimization. */
1070 /* 1 if X is an fp register. */
1072 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1073 \f
1074 /* Maximum number of registers that can appear in a valid memory address. */
1076 #define MAX_REGS_PER_ADDRESS 2
1078 /* Non-TLS symbolic references. */
1079 #define PA_SYMBOL_REF_TLS_P(RTX) \
1080 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
1082 /* Recognize any constant value that is a valid address except
1083 for symbolic addresses. We get better CSE by rejecting them
1084 here and allowing hppa_legitimize_address to break them up. We
1085 use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */
1087 #define CONSTANT_ADDRESS_P(X) \
1088 ((GET_CODE (X) == LABEL_REF \
1089 || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \
1090 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1091 || GET_CODE (X) == HIGH) \
1092 && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
1094 /* A C expression that is nonzero if we are using the new HP assembler. */
1096 #ifndef NEW_HP_ASSEMBLER
1097 #define NEW_HP_ASSEMBLER 0
1098 #endif
1100 /* The macros below define the immediate range for CONST_INTS on
1101 the 64-bit port. Constants in this range can be loaded in three
1102 instructions using a ldil/ldo/depdi sequence. Constants outside
1103 this range are forced to the constant pool prior to reload. */
1105 #define MAX_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) 32 << 31)
1106 #define MIN_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) -32 << 31)
1107 #define LEGITIMATE_64BIT_CONST_INT_P(X) \
1108 ((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT)
1110 /* A C expression that is nonzero if X is a legitimate constant for an
1111 immediate operand.
1113 We include all constant integers and constant doubles, but not
1114 floating-point, except for floating-point zero. We reject LABEL_REFs
1115 if we're not using gas or the new HP assembler.
1117 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
1118 that need more than three instructions to load prior to reload. This
1119 limit is somewhat arbitrary. It takes three instructions to load a
1120 CONST_INT from memory but two are memory accesses. It may be better
1121 to increase the allowed range for CONST_INTS. We may also be able
1122 to handle CONST_DOUBLES. */
1124 #define LEGITIMATE_CONSTANT_P(X) \
1125 ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1126 || (X) == CONST0_RTX (GET_MODE (X))) \
1127 && (NEW_HP_ASSEMBLER \
1128 || TARGET_GAS \
1129 || GET_CODE (X) != LABEL_REF) \
1130 && (!TARGET_64BIT \
1131 || GET_CODE (X) != CONST_DOUBLE) \
1132 && (!TARGET_64BIT \
1133 || HOST_BITS_PER_WIDE_INT <= 32 \
1134 || GET_CODE (X) != CONST_INT \
1135 || reload_in_progress \
1136 || reload_completed \
1137 || LEGITIMATE_64BIT_CONST_INT_P (INTVAL (X)) \
1138 || cint_ok_for_move (INTVAL (X))) \
1139 && !function_label_operand (X, VOIDmode))
1141 /* Target flags set on a symbol_ref. */
1143 /* Set by ASM_OUTPUT_SYMBOL_REF when a symbol_ref is output. */
1144 #define SYMBOL_FLAG_REFERENCED (1 << SYMBOL_FLAG_MACH_DEP_SHIFT)
1145 #define SYMBOL_REF_REFERENCED_P(RTX) \
1146 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_REFERENCED) != 0)
1148 /* Subroutines for EXTRA_CONSTRAINT.
1150 Return 1 iff OP is a pseudo which did not get a hard register and
1151 we are running the reload pass. */
1152 #define IS_RELOADING_PSEUDO_P(OP) \
1153 ((reload_in_progress \
1154 && GET_CODE (OP) == REG \
1155 && REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1156 && reg_renumber [REGNO (OP)] < 0))
1158 /* Return 1 iff OP is a scaled or unscaled index address. */
1159 #define IS_INDEX_ADDR_P(OP) \
1160 (GET_CODE (OP) == PLUS \
1161 && GET_MODE (OP) == Pmode \
1162 && (GET_CODE (XEXP (OP, 0)) == MULT \
1163 || GET_CODE (XEXP (OP, 1)) == MULT \
1164 || (REG_P (XEXP (OP, 0)) \
1165 && REG_P (XEXP (OP, 1)))))
1167 /* Return 1 iff OP is a LO_SUM DLT address. */
1168 #define IS_LO_SUM_DLT_ADDR_P(OP) \
1169 (GET_CODE (OP) == LO_SUM \
1170 && GET_MODE (OP) == Pmode \
1171 && REG_P (XEXP (OP, 0)) \
1172 && REG_OK_FOR_BASE_P (XEXP (OP, 0)) \
1173 && GET_CODE (XEXP (OP, 1)) == UNSPEC)
1175 /* Optional extra constraints for this machine. Borrowed from sparc.h.
1177 `A' is a LO_SUM DLT memory operand.
1179 `Q' is any memory operand that isn't a symbolic, indexed or lo_sum
1180 memory operand. Note that an unassigned pseudo register is such a
1181 memory operand. Needed because reload will generate these things
1182 and then not re-recognize the insn, causing constrain_operands to
1183 fail.
1185 `R' is a scaled/unscaled indexed memory operand.
1187 `S' is the constant 31.
1189 `T' is for floating-point loads and stores.
1191 `U' is the constant 63.
1193 `W' is a register indirect memory operand. We could allow short
1194 displacements but GO_IF_LEGITIMATE_ADDRESS can't tell when a
1195 long displacement is valid. This is only used for prefetch
1196 instructions with the `sl' completer. */
1198 #define EXTRA_CONSTRAINT(OP, C) \
1200 (IS_RELOADING_PSEUDO_P (OP) \
1201 || (GET_CODE (OP) == MEM \
1202 && (reload_in_progress \
1203 || memory_address_p (GET_MODE (OP), XEXP (OP, 0))) \
1204 && !symbolic_memory_operand (OP, VOIDmode) \
1205 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1206 && !IS_INDEX_ADDR_P (XEXP (OP, 0)))) \
1208 (GET_CODE (OP) == MEM \
1209 && REG_P (XEXP (OP, 0)) \
1210 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1212 (GET_CODE (OP) == MEM \
1213 && IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))) \
1215 (GET_CODE (OP) == MEM \
1216 && IS_INDEX_ADDR_P (XEXP (OP, 0))) \
1218 (GET_CODE (OP) == MEM \
1219 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1220 && !IS_INDEX_ADDR_P (XEXP (OP, 0)) \
1221 /* Floating-point loads and stores are used to load \
1222 integer values as well as floating-point values. \
1223 They don't have the same set of REG+D address modes \
1224 as integer loads and stores. PA 1.x supports only \
1225 short displacements. PA 2.0 supports long displacements \
1226 but the base register needs to be aligned. \
1227 \
1228 The checks in GO_IF_LEGITIMATE_ADDRESS for SFmode and \
1229 DFmode test the validity of an address for use in a \
1230 floating point load or store. So, we use SFmode/DFmode \
1231 to see if the address is valid for a floating-point \
1233 && memory_address_p ((GET_MODE_SIZE (GET_MODE (OP)) == 4 \
1234 ? SFmode \
1235 : DFmode), \
1236 XEXP (OP, 0))) \
1238 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) \
1240 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0)))))))
1243 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1244 and check its validity for a certain class.
1245 We have two alternate definitions for each of them.
1246 The usual definition accepts all pseudo regs; the other rejects
1247 them unless they have been allocated suitable hard regs.
1248 The symbol REG_OK_STRICT causes the latter definition to be used.
1250 Most source files want to accept pseudo regs in the hope that
1251 they will get allocated to the class that the insn wants them to be in.
1252 Source files for reload pass need to be strict.
1253 After reload, it makes no difference, since pseudo regs have
1254 been eliminated by then. */
1256 #ifndef REG_OK_STRICT
1258 /* Nonzero if X is a hard reg that can be used as an index
1259 or if it is a pseudo reg. */
1260 #define REG_OK_FOR_INDEX_P(X) \
1261 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1262 /* Nonzero if X is a hard reg that can be used as a base reg
1263 or if it is a pseudo reg. */
1264 #define REG_OK_FOR_BASE_P(X) \
1265 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1267 #else
1269 /* Nonzero if X is a hard reg that can be used as an index. */
1270 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1271 /* Nonzero if X is a hard reg that can be used as a base reg. */
1272 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1274 #endif
1275 \f
1276 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1277 valid memory address for an instruction. The MODE argument is the
1278 machine mode for the MEM expression that wants to use this address.
1280 On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
1281 REG+REG, and REG+(REG*SCALE). The indexed address forms are only
1282 available with floating point loads and stores, and integer loads.
1283 We get better code by allowing indexed addresses in the initial
1284 RTL generation.
1286 The acceptance of indexed addresses as legitimate implies that we
1287 must provide patterns for doing indexed integer stores, or the move
1288 expanders must force the address of an indexed store to a register.
1289 We have adopted the latter approach.
1291 Another function of GO_IF_LEGITIMATE_ADDRESS is to ensure that
1292 the base register is a valid pointer for indexed instructions.
1293 On targets that have non-equivalent space registers, we have to
1294 know at the time of assembler output which register in a REG+REG
1295 pair is the base register. The REG_POINTER flag is sometimes lost
1296 in reload and the following passes, so it can't be relied on during
1297 code generation. Thus, we either have to canonicalize the order
1298 of the registers in REG+REG indexed addresses, or treat REG+REG
1299 addresses separately and provide patterns for both permutations.
1301 The latter approach requires several hundred additional lines of
1302 code in pa.md. The downside to canonicalizing is that a PLUS
1303 in the wrong order can't combine to form to make a scaled indexed
1304 memory operand. As we won't need to canonicalize the operands if
1305 the REG_POINTER lossage can be fixed, it seems better canonicalize.
1307 We initially break out scaled indexed addresses in canonical order
1308 in emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
1309 scaled indexed addresses during RTL generation. However, fold_rtx
1310 has its own opinion on how the operands of a PLUS should be ordered.
1311 If one of the operands is equivalent to a constant, it will make
1312 that operand the second operand. As the base register is likely to
1313 be equivalent to a SYMBOL_REF, we have made it the second operand.
1315 GO_IF_LEGITIMATE_ADDRESS accepts REG+REG as legitimate when the
1316 operands are in the order INDEX+BASE on targets with non-equivalent
1317 space registers, and in any order on targets with equivalent space
1318 registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing.
1320 We treat a SYMBOL_REF as legitimate if it is part of the current
1321 function's constant-pool, because such addresses can actually be
1322 output as REG+SMALLINT.
1324 Note we only allow 5-bit immediates for access to a constant address;
1325 doing so avoids losing for loading/storing a FP register at an address
1326 which will not fit in 5 bits. */
1328 #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
1329 #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
1331 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
1332 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
1334 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
1335 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
1337 #define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000)
1338 #define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))
1340 #if HOST_BITS_PER_WIDE_INT > 32
1341 #define VAL_32_BITS_P(X) \
1342 ((unsigned HOST_WIDE_INT)(X) + ((unsigned HOST_WIDE_INT) 1 << 31) \
1343 < (unsigned HOST_WIDE_INT) 2 << 31)
1344 #else
1345 #define VAL_32_BITS_P(X) 1
1346 #endif
1347 #define INT_32_BITS(X) VAL_32_BITS_P (INTVAL (X))
1349 /* These are the modes that we allow for scaled indexing. */
1350 #define MODE_OK_FOR_SCALED_INDEXING_P(MODE) \
1351 ((TARGET_64BIT && (MODE) == DImode) \
1352 || (MODE) == SImode \
1353 || (MODE) == HImode \
1354 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1356 /* These are the modes that we allow for unscaled indexing. */
1357 #define MODE_OK_FOR_UNSCALED_INDEXING_P(MODE) \
1358 ((TARGET_64BIT && (MODE) == DImode) \
1359 || (MODE) == SImode \
1360 || (MODE) == HImode \
1361 || (MODE) == QImode \
1362 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1364 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1365 { \
1366 if ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1367 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC \
1368 || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC) \
1369 && REG_P (XEXP (X, 0)) \
1370 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) \
1371 goto ADDR; \
1372 else if (GET_CODE (X) == PLUS) \
1373 { \
1374 rtx base = 0, index = 0; \
1375 if (REG_P (XEXP (X, 1)) \
1376 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1377 base = XEXP (X, 1), index = XEXP (X, 0); \
1378 else if (REG_P (XEXP (X, 0)) \
1379 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1380 base = XEXP (X, 0), index = XEXP (X, 1); \
1381 if (base \
1382 && GET_CODE (index) == CONST_INT \
1383 && ((INT_14_BITS (index) \
1384 && (((MODE) != DImode \
1385 && (MODE) != SFmode \
1386 && (MODE) != DFmode) \
1387 /* The base register for DImode loads and stores \
1388 with long displacements must be aligned because \
1389 the lower three bits in the displacement are \
1391 || ((MODE) == DImode \
1392 && (!TARGET_64BIT \
1393 || (INTVAL (index) % 8) == 0)) \
1394 /* Similarly, the base register for SFmode/DFmode \
1395 loads and stores with long displacements must \
1396 be aligned. \
1397 \
1398 FIXME: the ELF32 linker clobbers the LSB of \
1399 the FP register number in PA 2.0 floating-point \
1400 insns with long displacements. This is because \
1401 R_PARISC_DPREL14WR and other relocations like \
1402 it are not supported. For now, we reject long \
1404 || (((MODE) == SFmode || (MODE) == DFmode) \
1405 && (TARGET_SOFT_FLOAT \
1406 || (TARGET_PA_20 \
1407 && !TARGET_ELF32 \
1408 && (INTVAL (index) \
1409 % GET_MODE_SIZE (MODE)) == 0))))) \
1410 || INT_5_BITS (index))) \
1411 goto ADDR; \
1412 if (!TARGET_DISABLE_INDEXING \
1413 /* Only accept the "canonical" INDEX+BASE operand order \
1415 && (TARGET_NO_SPACE_REGS \
1416 ? (base && REG_P (index)) \
1417 : (base == XEXP (X, 1) && REG_P (index) \
1418 && (reload_completed \
1419 || (reload_in_progress && HARD_REGISTER_P (base)) \
1420 || REG_POINTER (base)) \
1421 && (reload_completed \
1422 || (reload_in_progress && HARD_REGISTER_P (index)) \
1423 || !REG_POINTER (index)))) \
1424 && MODE_OK_FOR_UNSCALED_INDEXING_P (MODE) \
1425 && REG_OK_FOR_INDEX_P (index) \
1426 && borx_reg_operand (base, Pmode) \
1427 && borx_reg_operand (index, Pmode)) \
1428 goto ADDR; \
1429 if (!TARGET_DISABLE_INDEXING \
1430 && base \
1431 && GET_CODE (index) == MULT \
1432 && MODE_OK_FOR_SCALED_INDEXING_P (MODE) \
1433 && REG_P (XEXP (index, 0)) \
1434 && GET_MODE (XEXP (index, 0)) == Pmode \
1435 && REG_OK_FOR_INDEX_P (XEXP (index, 0)) \
1436 && GET_CODE (XEXP (index, 1)) == CONST_INT \
1437 && INTVAL (XEXP (index, 1)) \
1438 == (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
1439 && borx_reg_operand (base, Pmode)) \
1440 goto ADDR; \
1441 } \
1442 else if (GET_CODE (X) == LO_SUM \
1443 && GET_CODE (XEXP (X, 0)) == REG \
1444 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1445 && CONSTANT_P (XEXP (X, 1)) \
1446 && (TARGET_SOFT_FLOAT \
1448 || (TARGET_PA_20 \
1449 && !TARGET_ELF32 \
1450 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1451 || ((MODE) != SFmode \
1452 && (MODE) != DFmode))) \
1453 goto ADDR; \
1454 else if (GET_CODE (X) == LO_SUM \
1455 && GET_CODE (XEXP (X, 0)) == SUBREG \
1456 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG \
1457 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0))) \
1458 && CONSTANT_P (XEXP (X, 1)) \
1459 && (TARGET_SOFT_FLOAT \
1461 || (TARGET_PA_20 \
1462 && !TARGET_ELF32 \
1463 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1464 || ((MODE) != SFmode \
1465 && (MODE) != DFmode))) \
1466 goto ADDR; \
1467 else if (GET_CODE (X) == LABEL_REF \
1468 || (GET_CODE (X) == CONST_INT \
1469 && INT_5_BITS (X))) \
1470 goto ADDR; \
1472 else if (GET_CODE (X) == LO_SUM \
1473 && GET_CODE (XEXP (X, 0)) == REG \
1474 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1475 && GET_CODE (XEXP (X, 1)) == UNSPEC \
1476 && (TARGET_SOFT_FLOAT \
1477 || (TARGET_PA_20 && !TARGET_ELF32) \
1478 || ((MODE) != SFmode \
1479 && (MODE) != DFmode))) \
1480 goto ADDR; \
1481 }
1483 /* Look for machine dependent ways to make the invalid address AD a
1484 valid address.
1486 For the PA, transform:
1488 memory(X + <large int>)
1490 into:
1492 if (<large int> & mask) >= 16
1493 Y = (<large int> & ~mask) + mask + 1 Round up.
1494 else
1495 Y = (<large int> & ~mask) Round down.
1496 Z = X + Y
1497 memory (Z + (<large int> - Y));
1499 This makes reload inheritance and reload_cse work better since Z
1500 can be reused.
1502 There may be more opportunities to improve code with this hook. */
1503 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
1504 do { \
1505 long offset, newoffset, mask; \
1506 rtx new, temp = NULL_RTX; \
1507 \
1508 mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1509 ? (TARGET_PA_20 && !TARGET_ELF32 ? 0x3fff : 0x1f) : 0x3fff); \
1510 \
1511 if (optimize && GET_CODE (AD) == PLUS) \
1512 temp = simplify_binary_operation (PLUS, Pmode, \
1513 XEXP (AD, 0), XEXP (AD, 1)); \
1514 \
1515 new = temp ? temp : AD; \
1516 \
1517 if (optimize \
1518 && GET_CODE (new) == PLUS \
1519 && GET_CODE (XEXP (new, 0)) == REG \
1520 && GET_CODE (XEXP (new, 1)) == CONST_INT) \
1521 { \
1522 offset = INTVAL (XEXP ((new), 1)); \
1523 \
1525 if ((offset & mask) >= ((mask + 1) / 2)) \
1526 newoffset = (offset & ~mask) + mask + 1; \
1527 else \
1528 newoffset = offset & ~mask; \
1529 \
1531 if (!VAL_5_BITS_P (newoffset) \
1532 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1533 newoffset &= ~(GET_MODE_SIZE (MODE) -1); \
1534 \
1535 if (newoffset != 0 && VAL_14_BITS_P (newoffset)) \
1536 { \
1537 temp = gen_rtx_PLUS (Pmode, XEXP (new, 0), \
1538 GEN_INT (newoffset)); \
1539 AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
1540 push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0, \
1541 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, \
1542 (OPNUM), (TYPE)); \
1543 goto WIN; \
1544 } \
1545 } \
1546 } while (0)
1550 \f
1551 /* Try machine-dependent ways of modifying an illegitimate address
1552 to be legitimate. If we find one, return the new, valid address.
1553 This macro is used in only one place: `memory_address' in explow.c.
1555 OLDX is the address as it was before break_out_memory_refs was called.
1556 In some cases it is useful to look at this to decide what needs to be done.
1558 MODE and WIN are passed so that this macro can use
1559 GO_IF_LEGITIMATE_ADDRESS.
1561 It is always safe for this macro to do nothing. It exists to recognize
1562 opportunities to optimize the output. */
1564 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1565 { rtx orig_x = (X); \
1566 (X) = hppa_legitimize_address (X, OLDX, MODE); \
1567 if ((X) != orig_x && memory_address_p (MODE, X)) \
1568 goto WIN; }
1570 /* Go to LABEL if ADDR (a legitimate address expression)
1571 has an effect that depends on the machine mode it is used for. */
1573 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1574 \f
1575 #define TARGET_ASM_SELECT_SECTION pa_select_section
1577 /* Return a nonzero value if DECL has a section attribute. */
1578 #define IN_NAMED_SECTION_P(DECL) \
1579 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
1580 && DECL_SECTION_NAME (DECL) != NULL_TREE)
1582 /* Define this macro if references to a symbol must be treated
1583 differently depending on something about the variable or
1584 function named by the symbol (such as what section it is in).
1586 The macro definition, if any, is executed immediately after the
1587 rtl for DECL or other node is created.
1588 The value of the rtl will be a `mem' whose address is a
1589 `symbol_ref'.
1591 The usual thing for this macro to do is to a flag in the
1592 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1593 name string in the `symbol_ref' (if one bit is not enough
1594 information).
1596 On the HP-PA we use this to indicate if a symbol is in text or
1597 data space. Also, function labels need special treatment. */
1599 #define TEXT_SPACE_P(DECL)\
1600 (TREE_CODE (DECL) == FUNCTION_DECL \
1601 || (TREE_CODE (DECL) == VAR_DECL \
1602 && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
1603 && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
1604 && !flag_pic) \
1605 || CONSTANT_CLASS_P (DECL))
1609 /* Specify the machine mode that this machine uses for the index in the
1610 tablejump instruction. For small tables, an element consists of a
1611 ia-relative branch and its delay slot. When -mbig-switch is specified,
1612 we use a 32-bit absolute address for non-pic code, and a 32-bit offset
1613 for both 32 and 64-bit pic code. */
1614 #define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode)
1616 /* Jump tables must be 32-bit aligned, no matter the size of the element. */
1617 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
1619 /* Define this as 1 if `char' should by default be signed; else as 0. */
1620 #define DEFAULT_SIGNED_CHAR 1
1622 /* Max number of bytes we can move from memory to memory
1623 in one reasonably fast instruction. */
1624 #define MOVE_MAX 8
1626 /* Higher than the default as we prefer to use simple move insns
1627 (better scheduling and delay slot filling) and because our
1628 built-in block move is really a 2X unrolled loop.
1630 Believe it or not, this has to be big enough to allow for copying all
1631 arguments passed in registers to avoid infinite recursion during argument
1632 setup for a function call. Why? Consider how we copy the stack slots
1633 reserved for parameters when they may be trashed by a call. */
1634 #define MOVE_RATIO (TARGET_64BIT ? 8 : 4)
1636 /* Define if operations between registers always perform the operation
1637 on the full register even if a narrower mode is specified. */
1638 #define WORD_REGISTER_OPERATIONS
1640 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1641 will either zero-extend or sign-extend. The value of this macro should
1642 be the code that says which one of the two operations is implicitly
1643 done, UNKNOWN if none. */
1644 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1646 /* Nonzero if access to memory by bytes is slow and undesirable. */
1647 #define SLOW_BYTE_ACCESS 1
1649 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1650 is done just by pretending it is already truncated. */
1651 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1653 /* Specify the machine mode that pointers have.
1654 After generation of rtl, the compiler makes no further distinction
1655 between pointers and any other objects of this machine mode. */
1656 #define Pmode word_mode
1658 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1659 return the mode to be used for the comparison. For floating-point, CCFPmode
1660 should be used. CC_NOOVmode should be used when the first operand is a
1661 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1662 needed. */
1663 #define SELECT_CC_MODE(OP,X,Y) \
1664 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode) \
1666 /* A function address in a call instruction
1667 is a byte address (for indexing purposes)
1668 so give the MEM rtx a byte's mode. */
1669 #define FUNCTION_MODE SImode
1671 /* Define this if addresses of constant functions
1672 shouldn't be put through pseudo regs where they can be cse'd.
1673 Desirable on machines where ordinary constants are expensive
1674 but a CALL with constant address is cheap. */
1675 #define NO_FUNCTION_CSE
1677 /* Define this to be nonzero if shift instructions ignore all but the low-order
1678 few bits. */
1679 #define SHIFT_COUNT_TRUNCATED 1
1681 /* Compute extra cost of moving data between one register class
1682 and another.
1684 Make moves from SAR so expensive they should never happen. We used to
1685 have 0xffff here, but that generates overflow in rare cases.
1687 Copies involving a FP register and a non-FP register are relatively
1688 expensive because they must go through memory.
1690 Other copies are reasonably cheap. */
1691 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1692 (CLASS1 == SHIFT_REGS ? 0x100 \
1693 : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16 \
1694 : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16 \
1695 : 2)
1697 /* Adjust the cost of branches. */
1698 #define BRANCH_COST (pa_cpu == PROCESSOR_8000 ? 2 : 1)
1700 /* Handling the special cases is going to get too complicated for a macro,
1701 just call `pa_adjust_insn_length' to do the real work. */
1702 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1703 LENGTH += pa_adjust_insn_length (INSN, LENGTH);
1705 /* Millicode insns are actually function calls with some special
1706 constraints on arguments and register usage.
1708 Millicode calls always expect their arguments in the integer argument
1709 registers, and always return their result in %r29 (ret1). They
1710 are expected to clobber their arguments, %r1, %r29, and the return
1711 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
1713 This macro tells reorg that the references to arguments and
1714 millicode calls do not appear to happen until after the millicode call.
1715 This allows reorg to put insns which set the argument registers into the
1716 delay slot of the millicode call -- thus they act more like traditional
1717 CALL_INSNs.
1719 Note we cannot consider side effects of the insn to be delayed because
1720 the branch and link insn will clobber the return pointer. If we happened
1721 to use the return pointer in the delay slot of the call, then we lose.
1723 get_attr_type will try to recognize the given insn, so make sure to
1724 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1725 in particular. */
1726 #define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X))
1728 \f
1729 /* Control the assembler format that we output. */
1731 /* A C string constant describing how to begin a comment in the target
1732 assembler language. The compiler assumes that the comment will end at
1733 the end of the line. */
1737 /* Output to assembler file text saying following lines
1738 may contain character constants, extra white space, comments, etc. */
1742 /* Output to assembler file text saying following lines
1743 no longer contain unusual constructs. */
1747 /* This is how to output the definition of a user-level label named NAME,
1748 such as the label on a static function or variable NAME. */
1750 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1751 do { \
1752 assemble_name ((FILE), (NAME)); \
1753 if (TARGET_GAS) \
1755 else \
1757 } while (0)
1759 /* This is how to output a reference to a user-level label named NAME.
1760 `assemble_name' uses this. */
1762 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1763 do { \
1764 const char *xname = (NAME); \
1765 if (FUNCTION_NAME_P (NAME)) \
1766 xname += 1; \
1768 xname += 1; \
1769 else \
1770 fputs (user_label_prefix, FILE); \
1771 fputs (xname, FILE); \
1772 } while (0)
1774 /* This how we output the symbol_ref X. */
1776 #define ASM_OUTPUT_SYMBOL_REF(FILE,X) \
1777 do { \
1778 SYMBOL_REF_FLAGS (X) |= SYMBOL_FLAG_REFERENCED; \
1779 assemble_name (FILE, XSTR (X, 0)); \
1780 } while (0)
1782 /* This is how to store into the string LABEL
1783 the symbol_ref name of an internal numbered label where
1784 PREFIX is the class of label and NUM is the number within the class.
1785 This is suitable for output with `assemble_name'. */
1787 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1790 /* Output the definition of a compiler-generated label named NAME. */
1792 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,NAME) \
1793 do { \
1794 assemble_name_raw ((FILE), (NAME)); \
1795 if (TARGET_GAS) \
1797 else \
1799 } while (0)
1801 #define TARGET_ASM_GLOBALIZE_LABEL pa_globalize_label
1803 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1804 output_ascii ((FILE), (P), (SIZE))
1806 /* Jump tables are always placed in the text section. Technically, it
1807 is possible to put them in the readonly data section when -mbig-switch
1808 is specified. This has the benefit of getting the table out of .text
1809 and reducing branch lengths as a result. The downside is that an
1810 additional insn (addil) is needed to access the table when generating
1811 PIC code. The address difference table also has to use 32-bit
1812 pc-relative relocations. Currently, GAS does not support these
1813 relocations, although it is easily modified to do this operation.
1814 The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0"
1815 when using ELF GAS. A simple difference can be used when using
1816 SOM GAS or the HP assembler. The final downside is GDB complains
1817 about the nesting of the label for the table when debugging. */
1819 #define JUMP_TABLES_IN_TEXT_SECTION 1
1821 /* This is how to output an element of a case-vector that is absolute. */
1823 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1824 if (TARGET_BIG_SWITCH) \
1826 else \
1829 /* This is how to output an element of a case-vector that is relative.
1830 Since we always place jump tables in the text section, the difference
1831 is absolute and requires no relocation. */
1833 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1834 if (TARGET_BIG_SWITCH) \
1836 else \
1839 /* This is how to output an assembler line that says to advance the
1840 location counter to a multiple of 2**LOG bytes. */
1842 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1845 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1847 (unsigned HOST_WIDE_INT)(SIZE))
1849 /* This says how to output an assembler line to define an uninitialized
1850 global variable with size SIZE (in bytes) and alignment ALIGN (in bits).
1851 This macro exists to properly support languages like C++ which do not
1852 have common data. */
1854 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1855 pa_asm_output_aligned_bss (FILE, NAME, SIZE, ALIGN)
1857 /* This says how to output an assembler line to define a global common symbol
1858 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1860 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1861 pa_asm_output_aligned_common (FILE, NAME, SIZE, ALIGN)
1863 /* This says how to output an assembler line to define a local common symbol
1864 with size SIZE (in bytes) and alignment ALIGN (in bits). This macro
1865 controls how the assembler definitions of uninitialized static variables
1866 are output. */
1868 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1869 pa_asm_output_aligned_local (FILE, NAME, SIZE, ALIGN)
1874 /* All HP assemblers use "!" to separate logical lines. */
1877 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1880 /* Print operand X (an rtx) in assembler syntax to file FILE.
1881 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1882 For `%' followed by punctuation, CODE is the punctuation and X is null.
1884 On the HP-PA, the CODE can be `r', meaning this is a register-only operand
1885 and an immediate zero should be represented as `r0'.
1887 Several % codes are defined:
1888 O an operation
1889 C compare conditions
1890 N extract conditions
1891 M modifier to handle preincrement addressing for memory refs.
1892 F modifier to handle preincrement addressing for fp memory refs */
1894 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1896 \f
1897 /* Print a memory address as an operand to reference that memory location. */
1899 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1900 { rtx addr = ADDR; \
1901 switch (GET_CODE (addr)) \
1902 { \
1903 case REG: \
1905 break; \
1906 case PLUS: \
1907 gcc_assert (GET_CODE (XEXP (addr, 1)) == CONST_INT); \
1909 reg_names [REGNO (XEXP (addr, 0))]); \
1910 break; \
1911 case LO_SUM: \
1912 if (!symbolic_operand (XEXP (addr, 1), VOIDmode)) \
1914 else if (flag_pic == 0) \
1916 else \
1918 output_global_address (FILE, XEXP (addr, 1), 0); \
1920 output_operand (XEXP (addr, 0), 0); \
1922 break; \
1923 case CONST_INT: \
1925 break; \
1926 default: \
1927 output_addr_const (FILE, addr); \
1928 }}
1930 \f
1931 /* Find the return address associated with the frame given by
1932 FRAMEADDR. */
1933 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
1934 (return_addr_rtx (COUNT, FRAMEADDR))
1936 /* Used to mask out junk bits from the return address, such as
1937 processor state, interrupt status, condition codes and the like. */
1938 #define MASK_RETURN_ADDR \
1939 /* The privilege level is in the two low order bits, mask em out \
1941 (GEN_INT (-4))
1943 /* The number of Pmode words for the setjmp buffer. */
1944 #define JMP_BUF_SIZE 50
1946 /* We need a libcall to canonicalize function pointers on TARGET_ELF32. */
1947 #define CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL \
1948 "__canonicalize_funcptr_for_compare"
1950 #ifdef HAVE_AS_TLS
1951 #undef TARGET_HAVE_TLS
1952 #define TARGET_HAVE_TLS true
1953 #endif