1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
51 /* 1 if the caller has placed an "unimp" insn immediately after the call.
52 This is used in v8 code when calling a function that returns a structure.
53 v9 doesn't have this. Be careful to have this test be the same as that
56 #define SKIP_CALLERS_UNIMP_P \
57 (!TARGET_ARCH64 && current_function_returns_struct \
58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
62 /* Global variables for machine-dependent things. */
64 /* Size of frame. Need to know this to emit return insns from leaf procedures.
65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
66 reload pass. This is important as the value is later used in insn
67 scheduling (to see what can go in a delay slot).
68 APPARENT_FSIZE is the size of the stack less the register save area and less
69 the outgoing argument area. It is used when saving call preserved regs. */
70 static HOST_WIDE_INT apparent_fsize
;
71 static HOST_WIDE_INT actual_fsize
;
73 /* Number of live general or floating point registers needed to be
74 saved (as 4-byte quantities). */
75 static int num_gfregs
;
77 /* Save the operands last given to a compare for use when we
78 generate a scc or bcc insn. */
79 rtx sparc_compare_op0
, sparc_compare_op1
;
81 /* Coordinate with the md file wrt special insns created by
82 sparc_function_epilogue. */
83 bool sparc_emitting_epilogue
;
85 /* Vector to say how input registers are mapped to output registers.
86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
87 eliminate it. You must use -fomit-frame-pointer to get that. */
88 char leaf_reg_remap
[] =
89 { 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
102 96, 97, 98, 99, 100};
104 /* Vector, indexed by hard register number, which contains 1
105 for a register that is allowable in a candidate for leaf
106 function treatment. */
107 char sparc_leaf_regs
[] =
108 { 1, 1, 1, 1, 1, 1, 1, 1,
109 0, 0, 0, 0, 0, 0, 1, 0,
110 0, 0, 0, 0, 0, 0, 0, 0,
111 1, 1, 1, 1, 1, 1, 0, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
122 struct machine_function
GTY(())
124 /* Some local-dynamic TLS symbol name. */
125 const char *some_ld_name
;
128 /* Name of where we pretend to think the frame pointer points.
129 Normally, this is "%fp", but if we are in a leaf procedure,
130 this is "%sp+something". We record "something" separately as it may be
131 too big for reg+constant addressing. */
133 static const char *frame_base_name
;
134 static HOST_WIDE_INT frame_base_offset
;
136 static void sparc_init_modes (void);
137 static int save_regs (FILE *, int, int, const char *, int, int, HOST_WIDE_INT
);
138 static int restore_regs (FILE *, int, int, const char *, int, int);
139 static void build_big_number (FILE *, HOST_WIDE_INT
, const char *);
140 static void scan_record_type (tree
, int *, int *, int *);
141 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
142 tree
, int, int, int *, int *);
144 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
145 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
147 static void sparc_output_addr_vec (rtx
);
148 static void sparc_output_addr_diff_vec (rtx
);
149 static void sparc_output_deferred_case_vectors (void);
150 static int check_return_regs (rtx
);
151 static rtx
sparc_builtin_saveregs (void);
152 static int epilogue_renumber (rtx
*, int);
153 static bool sparc_assemble_integer (rtx
, unsigned int, int);
154 static int set_extends (rtx
);
155 static void output_restore_regs (FILE *, int);
156 static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT
);
157 static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT
);
158 static void sparc_function_epilogue (FILE *, HOST_WIDE_INT
, int);
159 static void sparc_function_prologue (FILE *, HOST_WIDE_INT
, int);
160 #ifdef OBJECT_FORMAT_ELF
161 static void sparc_elf_asm_named_section (const char *, unsigned int);
163 static void sparc_aout_select_section (tree
, int, unsigned HOST_WIDE_INT
)
165 static void sparc_aout_select_rtx_section (enum machine_mode
, rtx
,
166 unsigned HOST_WIDE_INT
)
169 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
170 static int sparc_issue_rate (void);
171 static void sparc_sched_init (FILE *, int, int);
172 static int sparc_use_dfa_pipeline_interface (void);
173 static int sparc_use_sched_lookahead (void);
175 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
176 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
177 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
178 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
179 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
181 static bool sparc_function_ok_for_sibcall (tree
, tree
);
182 static void sparc_init_libfuncs (void);
183 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
184 HOST_WIDE_INT
, tree
);
185 static struct machine_function
* sparc_init_machine_status (void);
186 static bool sparc_cannot_force_const_mem (rtx
);
187 static rtx
sparc_tls_get_addr (void);
188 static rtx
sparc_tls_got (void);
189 static const char *get_some_local_dynamic_name (void);
190 static int get_some_local_dynamic_name_1 (rtx
*, void *);
191 static bool sparc_rtx_costs (rtx
, int, int, int *);
192 static bool sparc_promote_prototypes (tree
);
193 static rtx
sparc_struct_value_rtx (tree
, int);
194 static bool sparc_return_in_memory (tree
, tree
);
195 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS
*);
197 /* Option handling. */
199 /* Code model option as passed by user. */
200 const char *sparc_cmodel_string
;
202 enum cmodel sparc_cmodel
;
204 char sparc_hard_reg_printed
[8];
206 struct sparc_cpu_select sparc_select
[] =
208 /* switch name, tune arch */
209 { (char *)0, "default", 1, 1 },
210 { (char *)0, "-mcpu=", 1, 1 },
211 { (char *)0, "-mtune=", 1, 0 },
215 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
216 enum processor_type sparc_cpu
;
218 /* Initialize the GCC target structure. */
220 /* The sparc default is to use .half rather than .short for aligned
221 HI objects. Use .word instead of .long on non-ELF systems. */
222 #undef TARGET_ASM_ALIGNED_HI_OP
223 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
224 #ifndef OBJECT_FORMAT_ELF
225 #undef TARGET_ASM_ALIGNED_SI_OP
226 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
229 #undef TARGET_ASM_UNALIGNED_HI_OP
230 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
231 #undef TARGET_ASM_UNALIGNED_SI_OP
232 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
233 #undef TARGET_ASM_UNALIGNED_DI_OP
234 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
236 /* The target hook has to handle DI-mode values. */
237 #undef TARGET_ASM_INTEGER
238 #define TARGET_ASM_INTEGER sparc_assemble_integer
240 #undef TARGET_ASM_FUNCTION_PROLOGUE
241 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
242 #undef TARGET_ASM_FUNCTION_EPILOGUE
243 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
245 #undef TARGET_SCHED_ADJUST_COST
246 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
247 #undef TARGET_SCHED_ISSUE_RATE
248 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
249 #undef TARGET_SCHED_INIT
250 #define TARGET_SCHED_INIT sparc_sched_init
251 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
252 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
253 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
254 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
256 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
257 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
259 #undef TARGET_INIT_LIBFUNCS
260 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
263 #undef TARGET_HAVE_TLS
264 #define TARGET_HAVE_TLS true
266 #undef TARGET_CANNOT_FORCE_CONST_MEM
267 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
269 #undef TARGET_ASM_OUTPUT_MI_THUNK
270 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
271 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
272 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
274 #undef TARGET_RTX_COSTS
275 #define TARGET_RTX_COSTS sparc_rtx_costs
276 #undef TARGET_ADDRESS_COST
277 #define TARGET_ADDRESS_COST hook_int_rtx_0
279 /* Return TRUE if the promotion described by PROMOTE_MODE should also be done
280 for outgoing function arguments.
281 This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
282 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
284 #undef TARGET_PROMOTE_FUNCTION_ARGS
285 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
287 /* Return TRUE if the promotion described by PROMOTE_MODE should also be done
288 for the return value of functions. If this macro is defined, FUNCTION_VALUE
289 must perform the same promotions done by PROMOTE_MODE.
290 This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
291 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
293 #undef TARGET_PROMOTE_FUNCTION_RETURN
294 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
296 #undef TARGET_PROMOTE_PROTOTYPES
297 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
299 #undef TARGET_STRUCT_VALUE_RTX
300 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
301 #undef TARGET_RETURN_IN_MEMORY
302 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
304 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
305 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
306 #undef TARGET_STRICT_ARGUMENT_NAMING
307 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
309 struct gcc_target targetm
= TARGET_INITIALIZER
;
311 /* Validate and override various options, and do some machine dependent
315 sparc_override_options (void)
317 static struct code_model
{
318 const char *const name
;
320 } const cmodels
[] = {
322 { "medlow", CM_MEDLOW
},
323 { "medmid", CM_MEDMID
},
324 { "medany", CM_MEDANY
},
325 { "embmedany", CM_EMBMEDANY
},
328 const struct code_model
*cmodel
;
329 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
330 static struct cpu_default
{
332 const char *const name
;
333 } const cpu_default
[] = {
334 /* There must be one entry here for each TARGET_CPU value. */
335 { TARGET_CPU_sparc
, "cypress" },
336 { TARGET_CPU_sparclet
, "tsc701" },
337 { TARGET_CPU_sparclite
, "f930" },
338 { TARGET_CPU_v8
, "v8" },
339 { TARGET_CPU_hypersparc
, "hypersparc" },
340 { TARGET_CPU_sparclite86x
, "sparclite86x" },
341 { TARGET_CPU_supersparc
, "supersparc" },
342 { TARGET_CPU_v9
, "v9" },
343 { TARGET_CPU_ultrasparc
, "ultrasparc" },
344 { TARGET_CPU_ultrasparc3
, "ultrasparc3" },
347 const struct cpu_default
*def
;
348 /* Table of values for -m{cpu,tune}=. */
349 static struct cpu_table
{
350 const char *const name
;
351 const enum processor_type processor
;
354 } const cpu_table
[] = {
355 { "v7", PROCESSOR_V7
, MASK_ISA
, 0 },
356 { "cypress", PROCESSOR_CYPRESS
, MASK_ISA
, 0 },
357 { "v8", PROCESSOR_V8
, MASK_ISA
, MASK_V8
},
358 /* TI TMS390Z55 supersparc */
359 { "supersparc", PROCESSOR_SUPERSPARC
, MASK_ISA
, MASK_V8
},
360 { "sparclite", PROCESSOR_SPARCLITE
, MASK_ISA
, MASK_SPARCLITE
},
361 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
362 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
363 { "f930", PROCESSOR_F930
, MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
364 { "f934", PROCESSOR_F934
, MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
365 { "hypersparc", PROCESSOR_HYPERSPARC
, MASK_ISA
, MASK_V8
|MASK_FPU
},
366 { "sparclite86x", PROCESSOR_SPARCLITE86X
, MASK_ISA
|MASK_FPU
,
368 { "sparclet", PROCESSOR_SPARCLET
, MASK_ISA
, MASK_SPARCLET
},
370 { "tsc701", PROCESSOR_TSC701
, MASK_ISA
, MASK_SPARCLET
},
371 { "v9", PROCESSOR_V9
, MASK_ISA
, MASK_V9
},
372 /* TI ultrasparc I, II, IIi */
373 { "ultrasparc", PROCESSOR_ULTRASPARC
, MASK_ISA
, MASK_V9
374 /* Although insns using %y are deprecated, it is a clear win on current
376 |MASK_DEPRECATED_V8_INSNS
},
377 /* TI ultrasparc III */
378 /* ??? Check if %y issue still holds true in ultra3. */
379 { "ultrasparc3", PROCESSOR_ULTRASPARC3
, MASK_ISA
, MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
382 const struct cpu_table
*cpu
;
383 const struct sparc_cpu_select
*sel
;
386 #ifndef SPARC_BI_ARCH
387 /* Check for unsupported architecture size. */
388 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
389 error ("%s is not supported by this configuration",
390 DEFAULT_ARCH32_P
? "-m64" : "-m32");
393 /* We force all 64bit archs to use 128 bit long double */
394 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
396 error ("-mlong-double-64 not allowed with -m64");
397 target_flags
|= MASK_LONG_DOUBLE_128
;
400 /* Code model selection. */
401 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
405 sparc_cmodel
= CM_32
;
408 if (sparc_cmodel_string
!= NULL
)
412 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
413 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
415 if (cmodel
->name
== NULL
)
416 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
418 sparc_cmodel
= cmodel
->value
;
421 error ("-mcmodel= is not supported on 32 bit systems");
424 fpu
= TARGET_FPU
; /* save current -mfpu status */
426 /* Set the default CPU. */
427 for (def
= &cpu_default
[0]; def
->name
; ++def
)
428 if (def
->cpu
== TARGET_CPU_DEFAULT
)
432 sparc_select
[0].string
= def
->name
;
434 for (sel
= &sparc_select
[0]; sel
->name
; ++sel
)
438 for (cpu
= &cpu_table
[0]; cpu
->name
; ++cpu
)
439 if (! strcmp (sel
->string
, cpu
->name
))
442 sparc_cpu
= cpu
->processor
;
446 target_flags
&= ~cpu
->disable
;
447 target_flags
|= cpu
->enable
;
453 error ("bad value (%s) for %s switch", sel
->string
, sel
->name
);
457 /* If -mfpu or -mno-fpu was explicitly used, don't override with
458 the processor default. Clear MASK_FPU_SET to avoid confusing
459 the reverse mapping from switch values to names. */
462 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
463 target_flags
&= ~MASK_FPU_SET
;
466 /* Don't allow -mvis if FPU is disabled. */
468 target_flags
&= ~MASK_VIS
;
470 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
472 -m64 also implies v9. */
473 if (TARGET_VIS
|| TARGET_ARCH64
)
475 target_flags
|= MASK_V9
;
476 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
479 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
480 if (TARGET_V9
&& TARGET_ARCH32
)
481 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
483 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
484 if (! TARGET_V9
|| TARGET_ARCH64
)
485 target_flags
&= ~MASK_V8PLUS
;
487 /* Don't use stack biasing in 32 bit mode. */
489 target_flags
&= ~MASK_STACK_BIAS
;
491 /* Supply a default value for align_functions. */
492 if (align_functions
== 0
493 && (sparc_cpu
== PROCESSOR_ULTRASPARC
494 || sparc_cpu
== PROCESSOR_ULTRASPARC3
))
495 align_functions
= 32;
497 /* Validate PCC_STRUCT_RETURN. */
498 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
499 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
501 /* Only use .uaxword when compiling for a 64-bit target. */
503 targetm
.asm_out
.unaligned_op
.di
= NULL
;
505 /* Do various machine dependent initializations. */
508 /* Set up function hooks. */
509 init_machine_status
= sparc_init_machine_status
;
512 /* Miscellaneous utilities. */
514 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
515 or branch on register contents instructions. */
518 v9_regcmp_p (enum rtx_code code
)
520 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
521 || code
== LE
|| code
== GT
);
525 /* Operand constraints. */
527 /* Return nonzero only if OP is a register of mode MODE,
531 reg_or_0_operand (rtx op
, enum machine_mode mode
)
533 if (register_operand (op
, mode
))
535 if (op
== const0_rtx
)
537 if (GET_MODE (op
) == VOIDmode
&& GET_CODE (op
) == CONST_DOUBLE
538 && CONST_DOUBLE_HIGH (op
) == 0
539 && CONST_DOUBLE_LOW (op
) == 0)
541 if (fp_zero_operand (op
, mode
))
546 /* Return nonzero only if OP is const1_rtx. */
549 const1_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
551 return op
== const1_rtx
;
554 /* Nonzero if OP is a floating point value with value 0.0. */
557 fp_zero_operand (rtx op
, enum machine_mode mode
)
559 if (GET_MODE_CLASS (GET_MODE (op
)) != MODE_FLOAT
)
561 return op
== CONST0_RTX (mode
);
564 /* Nonzero if OP is a register operand in floating point register. */
567 fp_register_operand (rtx op
, enum machine_mode mode
)
569 if (! register_operand (op
, mode
))
571 if (GET_CODE (op
) == SUBREG
)
572 op
= SUBREG_REG (op
);
573 return GET_CODE (op
) == REG
&& SPARC_FP_REG_P (REGNO (op
));
576 /* Nonzero if OP is a floating point constant which can
577 be loaded into an integer register using a single
578 sethi instruction. */
583 if (GET_CODE (op
) == CONST_DOUBLE
)
588 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
589 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
590 ! REAL_VALUE_MINUS_ZERO (r
))
592 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
593 if (SPARC_SETHI_P (i
))
600 /* Nonzero if OP is a floating point constant which can
601 be loaded into an integer register using a single
607 if (GET_CODE (op
) == CONST_DOUBLE
)
612 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
613 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
614 ! REAL_VALUE_MINUS_ZERO (r
))
616 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
617 if (SPARC_SIMM13_P (i
))
624 /* Nonzero if OP is a floating point constant which can
625 be loaded into an integer register using a high/losum
626 instruction sequence. */
629 fp_high_losum_p (rtx op
)
631 /* The constraints calling this should only be in
632 SFmode move insns, so any constant which cannot
633 be moved using a single insn will do. */
634 if (GET_CODE (op
) == CONST_DOUBLE
)
639 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
640 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
641 ! REAL_VALUE_MINUS_ZERO (r
))
643 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
644 if (! SPARC_SETHI_P (i
)
645 && ! SPARC_SIMM13_P (i
))
652 /* Nonzero if OP is an integer register. */
655 intreg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
657 return (register_operand (op
, SImode
)
658 || (TARGET_ARCH64
&& register_operand (op
, DImode
)));
661 /* Nonzero if OP is a floating point condition code register. */
664 fcc_reg_operand (rtx op
, enum machine_mode mode
)
666 /* This can happen when recog is called from combine. Op may be a MEM.
667 Fail instead of calling abort in this case. */
668 if (GET_CODE (op
) != REG
)
671 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
674 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
677 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
678 if (reg_renumber
== 0)
679 return REGNO (op
) >= FIRST_PSEUDO_REGISTER
;
680 return REGNO_OK_FOR_CCFP_P (REGNO (op
));
682 return (unsigned) REGNO (op
) - SPARC_FIRST_V9_FCC_REG
< 4;
686 /* Nonzero if OP is a floating point condition code fcc0 register. */
689 fcc0_reg_operand (rtx op
, enum machine_mode mode
)
691 /* This can happen when recog is called from combine. Op may be a MEM.
692 Fail instead of calling abort in this case. */
693 if (GET_CODE (op
) != REG
)
696 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
699 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
702 return REGNO (op
) == SPARC_FCC_REG
;
705 /* Nonzero if OP is an integer or floating point condition code register. */
708 icc_or_fcc_reg_operand (rtx op
, enum machine_mode mode
)
710 if (GET_CODE (op
) == REG
&& REGNO (op
) == SPARC_ICC_REG
)
712 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
715 && GET_MODE (op
) != CCmode
&& GET_MODE (op
) != CCXmode
)
720 return fcc_reg_operand (op
, mode
);
723 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
725 restore_operand (rtx op
, enum machine_mode mode
)
727 return (GET_CODE (op
) == REG
&& GET_MODE (op
) == mode
728 && (REGNO (op
) < 8 || (REGNO (op
) >= 24 && REGNO (op
) < 32)));
731 /* Call insn on SPARC can take a PC-relative constant address, or any regular
735 call_operand (rtx op
, enum machine_mode mode
)
737 if (GET_CODE (op
) != MEM
)
740 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
744 call_operand_address (rtx op
, enum machine_mode mode
)
746 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
749 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
750 otherwise return 0. */
753 tls_symbolic_operand (rtx op
)
755 if (GET_CODE (op
) != SYMBOL_REF
)
757 return SYMBOL_REF_TLS_MODEL (op
);
761 tgd_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
763 return tls_symbolic_operand (op
) == TLS_MODEL_GLOBAL_DYNAMIC
;
767 tld_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
769 return tls_symbolic_operand (op
) == TLS_MODEL_LOCAL_DYNAMIC
;
773 tie_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
775 return tls_symbolic_operand (op
) == TLS_MODEL_INITIAL_EXEC
;
779 tle_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
781 return tls_symbolic_operand (op
) == TLS_MODEL_LOCAL_EXEC
;
784 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
785 reference and a constant. */
788 symbolic_operand (register rtx op
, enum machine_mode mode
)
790 enum machine_mode omode
= GET_MODE (op
);
792 if (omode
!= mode
&& omode
!= VOIDmode
&& mode
!= VOIDmode
)
795 switch (GET_CODE (op
))
798 return !SYMBOL_REF_TLS_MODEL (op
);
805 return (((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
806 && !SYMBOL_REF_TLS_MODEL (XEXP (op
, 0)))
807 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
808 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
815 /* Return truth value of statement that OP is a symbolic memory
816 operand of mode MODE. */
819 symbolic_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
821 if (GET_CODE (op
) == SUBREG
)
822 op
= SUBREG_REG (op
);
823 if (GET_CODE (op
) != MEM
)
826 return ((GET_CODE (op
) == SYMBOL_REF
&& !SYMBOL_REF_TLS_MODEL (op
))
827 || GET_CODE (op
) == CONST
|| GET_CODE (op
) == HIGH
828 || GET_CODE (op
) == LABEL_REF
);
831 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
834 label_ref_operand (rtx op
, enum machine_mode mode
)
836 if (GET_CODE (op
) != LABEL_REF
)
838 if (GET_MODE (op
) != mode
)
843 /* Return 1 if the operand is an argument used in generating pic references
844 in either the medium/low or medium/anywhere code models of sparc64. */
847 sp64_medium_pic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
849 /* Check for (const (minus (symbol_ref:GOT)
850 (const (minus (label) (pc))))). */
851 if (GET_CODE (op
) != CONST
)
854 if (GET_CODE (op
) != MINUS
)
856 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
858 /* ??? Ensure symbol is GOT. */
859 if (GET_CODE (XEXP (op
, 1)) != CONST
)
861 if (GET_CODE (XEXP (XEXP (op
, 1), 0)) != MINUS
)
866 /* Return 1 if the operand is a data segment reference. This includes
867 the readonly data segment, or in other words anything but the text segment.
868 This is needed in the medium/anywhere code model on v9. These values
869 are accessed with EMBMEDANY_BASE_REG. */
872 data_segment_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
874 switch (GET_CODE (op
))
877 return ! SYMBOL_REF_FUNCTION_P (op
);
879 /* Assume canonical format of symbol + constant.
882 return data_segment_operand (XEXP (op
, 0), VOIDmode
);
888 /* Return 1 if the operand is a text segment reference.
889 This is needed in the medium/anywhere code model on v9. */
892 text_segment_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
894 switch (GET_CODE (op
))
899 return SYMBOL_REF_FUNCTION_P (op
);
901 /* Assume canonical format of symbol + constant.
904 return text_segment_operand (XEXP (op
, 0), VOIDmode
);
910 /* Return 1 if the operand is either a register or a memory operand that is
914 reg_or_nonsymb_mem_operand (register rtx op
, enum machine_mode mode
)
916 if (register_operand (op
, mode
))
919 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
926 splittable_symbolic_memory_operand (rtx op
,
927 enum machine_mode mode ATTRIBUTE_UNUSED
)
929 if (GET_CODE (op
) != MEM
)
931 if (! symbolic_operand (XEXP (op
, 0), Pmode
))
937 splittable_immediate_memory_operand (rtx op
,
938 enum machine_mode mode ATTRIBUTE_UNUSED
)
940 if (GET_CODE (op
) != MEM
)
942 if (! immediate_operand (XEXP (op
, 0), Pmode
))
947 /* Return truth value of whether OP is EQ or NE. */
950 eq_or_neq (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
952 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
955 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
956 or LTU for non-floating-point. We handle those specially. */
959 normal_comp_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
961 enum rtx_code code
= GET_CODE (op
);
963 if (GET_RTX_CLASS (code
) != '<')
966 if (GET_MODE (XEXP (op
, 0)) == CCFPmode
967 || GET_MODE (XEXP (op
, 0)) == CCFPEmode
)
970 return (code
!= NE
&& code
!= EQ
&& code
!= GEU
&& code
!= LTU
);
973 /* Return 1 if this is a comparison operator. This allows the use of
974 MATCH_OPERATOR to recognize all the branch insns. */
977 noov_compare_op (register rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
979 enum rtx_code code
= GET_CODE (op
);
981 if (GET_RTX_CLASS (code
) != '<')
984 if (GET_MODE (XEXP (op
, 0)) == CC_NOOVmode
985 || GET_MODE (XEXP (op
, 0)) == CCX_NOOVmode
)
986 /* These are the only branches which work with CC_NOOVmode. */
987 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
991 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
992 MATCH_OPERATOR to recognize all the branch insns. */
995 noov_compare64_op (register rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
997 enum rtx_code code
= GET_CODE (op
);
1002 if (GET_RTX_CLASS (code
) != '<')
1005 if (GET_MODE (XEXP (op
, 0)) == CCX_NOOVmode
)
1006 /* These are the only branches which work with CCX_NOOVmode. */
1007 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
1008 return (GET_MODE (XEXP (op
, 0)) == CCXmode
);
1011 /* Nonzero if OP is a comparison operator suitable for use in v9
1012 conditional move or branch on register contents instructions. */
1015 v9_regcmp_op (register rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1017 enum rtx_code code
= GET_CODE (op
);
1019 if (GET_RTX_CLASS (code
) != '<')
1022 return v9_regcmp_p (code
);
1025 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1028 extend_op (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1030 return GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
;
1033 /* Return nonzero if OP is an operator of mode MODE which can set
1034 the condition codes explicitly. We do not include PLUS and MINUS
1035 because these require CC_NOOVmode, which we handle explicitly. */
1038 cc_arithop (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1040 if (GET_CODE (op
) == AND
1041 || GET_CODE (op
) == IOR
1042 || GET_CODE (op
) == XOR
)
1048 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1049 complement its second operand and set the condition codes explicitly. */
1052 cc_arithopn (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1054 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1055 and (xor ... (not ...)) to (not (xor ...)). */
1056 return (GET_CODE (op
) == AND
1057 || GET_CODE (op
) == IOR
);
1060 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1061 signed 13 bit immediate field. This is an acceptable SImode operand for
1062 most 3 address instructions. */
1065 arith_operand (rtx op
, enum machine_mode mode
)
1067 if (register_operand (op
, mode
))
1069 if (GET_CODE (op
) != CONST_INT
)
1071 return SMALL_INT32 (op
);
1074 /* Return true if OP is a constant 4096 */
1077 arith_4096_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1079 if (GET_CODE (op
) != CONST_INT
)
1082 return INTVAL (op
) == 4096;
1085 /* Return true if OP is suitable as second operand for add/sub */
1088 arith_add_operand (rtx op
, enum machine_mode mode
)
1090 return arith_operand (op
, mode
) || arith_4096_operand (op
, mode
);
1093 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1094 immediate field of OR and XOR instructions. Used for 64-bit
1095 constant formation patterns. */
1097 const64_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1099 return ((GET_CODE (op
) == CONST_INT
1100 && SPARC_SIMM13_P (INTVAL (op
)))
1101 #if HOST_BITS_PER_WIDE_INT != 64
1102 || (GET_CODE (op
) == CONST_DOUBLE
1103 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1104 && (CONST_DOUBLE_HIGH (op
) ==
1105 ((CONST_DOUBLE_LOW (op
) & 0x80000000) != 0 ?
1106 (HOST_WIDE_INT
)-1 : 0)))
1111 /* The same, but only for sethi instructions. */
1113 const64_high_operand (rtx op
, enum machine_mode mode
)
1115 return ((GET_CODE (op
) == CONST_INT
1116 && (INTVAL (op
) & ~(HOST_WIDE_INT
)0x3ff) != 0
1117 && SPARC_SETHI_P (INTVAL (op
) & GET_MODE_MASK (mode
))
1119 || (GET_CODE (op
) == CONST_DOUBLE
1120 && CONST_DOUBLE_HIGH (op
) == 0
1121 && (CONST_DOUBLE_LOW (op
) & ~(HOST_WIDE_INT
)0x3ff) != 0
1122 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
))));
1125 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1126 signed 11 bit immediate field. This is an acceptable SImode operand for
1127 the movcc instructions. */
1130 arith11_operand (rtx op
, enum machine_mode mode
)
1132 return (register_operand (op
, mode
)
1133 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM11_P (INTVAL (op
))));
1136 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1137 signed 10 bit immediate field. This is an acceptable SImode operand for
1138 the movrcc instructions. */
1141 arith10_operand (rtx op
, enum machine_mode mode
)
1143 return (register_operand (op
, mode
)
1144 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM10_P (INTVAL (op
))));
1147 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1148 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1150 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1151 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1152 for most 3 address instructions. */
1155 arith_double_operand (rtx op
, enum machine_mode mode
)
1157 return (register_operand (op
, mode
)
1158 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1160 && GET_CODE (op
) == CONST_DOUBLE
1161 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1162 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_HIGH (op
) + 0x1000) < 0x2000)
1164 && GET_CODE (op
) == CONST_DOUBLE
1165 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1166 && ((CONST_DOUBLE_HIGH (op
) == -1
1167 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0x1000)
1168 || (CONST_DOUBLE_HIGH (op
) == 0
1169 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
1172 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1175 arith_double_4096_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1177 return (TARGET_ARCH64
&&
1178 ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 4096) ||
1179 (GET_CODE (op
) == CONST_DOUBLE
&&
1180 CONST_DOUBLE_LOW (op
) == 4096 &&
1181 CONST_DOUBLE_HIGH (op
) == 0)));
1184 /* Return true if OP is suitable as second operand for add/sub in DImode */
1187 arith_double_add_operand (rtx op
, enum machine_mode mode
)
1189 return arith_double_operand (op
, mode
) || arith_double_4096_operand (op
, mode
);
1192 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1193 can fit in an 11 bit immediate field. This is an acceptable DImode
1194 operand for the movcc instructions. */
1195 /* ??? Replace with arith11_operand? */
1198 arith11_double_operand (rtx op
, enum machine_mode mode
)
1200 return (register_operand (op
, mode
)
1201 || (GET_CODE (op
) == CONST_DOUBLE
1202 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1203 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x400) < 0x800
1204 && ((CONST_DOUBLE_HIGH (op
) == -1
1205 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0x400)
1206 || (CONST_DOUBLE_HIGH (op
) == 0
1207 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0)))
1208 || (GET_CODE (op
) == CONST_INT
1209 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1210 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x400) < 0x800));
1213 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1214 can fit in an 10 bit immediate field. This is an acceptable DImode
1215 operand for the movrcc instructions. */
1216 /* ??? Replace with arith10_operand? */
1219 arith10_double_operand (rtx op
, enum machine_mode mode
)
1221 return (register_operand (op
, mode
)
1222 || (GET_CODE (op
) == CONST_DOUBLE
1223 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1224 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x200) < 0x400
1225 && ((CONST_DOUBLE_HIGH (op
) == -1
1226 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0x200)
1227 || (CONST_DOUBLE_HIGH (op
) == 0
1228 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0)))
1229 || (GET_CODE (op
) == CONST_INT
1230 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1231 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x200) < 0x400));
1234 /* Return truth value of whether OP is an integer which fits the
1235 range constraining immediate operands in most three-address insns,
1236 which have a 13 bit immediate field. */
1239 small_int (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1241 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
1245 small_int_or_double (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1247 return ((GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1248 || (GET_CODE (op
) == CONST_DOUBLE
1249 && CONST_DOUBLE_HIGH (op
) == 0
1250 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))));
1253 /* Recognize operand values for the umul instruction. That instruction sign
1254 extends immediate values just like all other sparc instructions, but
1255 interprets the extended result as an unsigned number. */
1258 uns_small_int (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1260 #if HOST_BITS_PER_WIDE_INT > 32
1261 /* All allowed constants will fit a CONST_INT. */
1262 return (GET_CODE (op
) == CONST_INT
1263 && ((INTVAL (op
) >= 0 && INTVAL (op
) < 0x1000)
1264 || (INTVAL (op
) >= 0xFFFFF000
1265 && INTVAL (op
) <= 0xFFFFFFFF)));
1267 return ((GET_CODE (op
) == CONST_INT
&& (unsigned) INTVAL (op
) < 0x1000)
1268 || (GET_CODE (op
) == CONST_DOUBLE
1269 && CONST_DOUBLE_HIGH (op
) == 0
1270 && (unsigned) CONST_DOUBLE_LOW (op
) - 0xFFFFF000 < 0x1000));
1275 uns_arith_operand (rtx op
, enum machine_mode mode
)
1277 return register_operand (op
, mode
) || uns_small_int (op
, mode
);
1280 /* Return truth value of statement that OP is a call-clobbered register. */
1282 clobbered_register (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1284 return (GET_CODE (op
) == REG
&& call_used_regs
[REGNO (op
)]);
1287 /* Return 1 if OP is a valid operand for the source of a move insn. */
1290 input_operand (rtx op
, enum machine_mode mode
)
1292 /* If both modes are non-void they must be the same. */
1293 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1296 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1297 if (GET_CODE (op
) == CONSTANT_P_RTX
)
1300 /* Allow any one instruction integer constant, and all CONST_INT
1301 variants when we are working in DImode and !arch64. */
1302 if (GET_MODE_CLASS (mode
) == MODE_INT
1303 && ((GET_CODE (op
) == CONST_INT
1304 && (SPARC_SETHI_P (INTVAL (op
) & GET_MODE_MASK (mode
))
1305 || SPARC_SIMM13_P (INTVAL (op
))
1307 && ! TARGET_ARCH64
)))
1309 && GET_CODE (op
) == CONST_DOUBLE
1310 && ((CONST_DOUBLE_HIGH (op
) == 0
1311 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
)))
1313 #if HOST_BITS_PER_WIDE_INT == 64
1314 (CONST_DOUBLE_HIGH (op
) == 0
1315 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
)))
1317 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1318 && (((CONST_DOUBLE_LOW (op
) & 0x80000000) == 0
1319 && CONST_DOUBLE_HIGH (op
) == 0)
1320 || (CONST_DOUBLE_HIGH (op
) == -1
1321 && CONST_DOUBLE_LOW (op
) & 0x80000000) != 0))
1326 /* If !arch64 and this is a DImode const, allow it so that
1327 the splits can be generated. */
1330 && GET_CODE (op
) == CONST_DOUBLE
)
1333 if (register_operand (op
, mode
))
1336 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
1337 && GET_CODE (op
) == CONST_DOUBLE
)
1340 /* If this is a SUBREG, look inside so that we handle
1341 paradoxical ones. */
1342 if (GET_CODE (op
) == SUBREG
)
1343 op
= SUBREG_REG (op
);
1345 /* Check for valid MEM forms. */
1346 if (GET_CODE (op
) == MEM
)
1348 rtx inside
= XEXP (op
, 0);
1350 if (GET_CODE (inside
) == LO_SUM
)
1352 /* We can't allow these because all of the splits
1353 (eventually as they trickle down into DFmode
1354 splits) require offsettable memory references. */
1356 && GET_MODE (op
) == TFmode
)
1359 return (register_operand (XEXP (inside
, 0), Pmode
)
1360 && CONSTANT_P (XEXP (inside
, 1)));
1362 return memory_address_p (mode
, inside
);
1369 /* We know it can't be done in one insn when we get here,
1370 the movsi expander guarantees this. */
1372 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1374 enum machine_mode mode
= GET_MODE (op0
);
1377 if (GET_CODE (op1
) == CONST_INT
)
1379 HOST_WIDE_INT value
= INTVAL (op1
);
1381 if (SPARC_SETHI_P (value
& GET_MODE_MASK (mode
))
1382 || SPARC_SIMM13_P (value
))
1386 /* Full 2-insn decomposition is needed. */
1387 if (reload_in_progress
|| reload_completed
)
1390 temp
= gen_reg_rtx (mode
);
1392 if (GET_CODE (op1
) == CONST_INT
)
1394 /* Emit them as real moves instead of a HIGH/LO_SUM,
1395 this way CSE can see everything and reuse intermediate
1396 values if it wants. */
1398 && HOST_BITS_PER_WIDE_INT
!= 64
1399 && (INTVAL (op1
) & 0x80000000) != 0)
1400 emit_insn (gen_rtx_SET
1402 immed_double_const (INTVAL (op1
) & ~(HOST_WIDE_INT
)0x3ff,
1405 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1406 GEN_INT (INTVAL (op1
)
1407 & ~(HOST_WIDE_INT
)0x3ff)));
1409 emit_insn (gen_rtx_SET (VOIDmode
,
1411 gen_rtx_IOR (mode
, temp
,
1412 GEN_INT (INTVAL (op1
) & 0x3ff))));
1416 /* A symbol, emit in the traditional way. */
1417 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1418 gen_rtx_HIGH (mode
, op1
)));
1419 emit_insn (gen_rtx_SET (VOIDmode
,
1420 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1426 /* SPARC-v9 code-model support. */
1428 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp1
)
1432 if (temp1
&& GET_MODE (temp1
) == TImode
)
1435 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
));
1438 switch (sparc_cmodel
)
1441 /* The range spanned by all instructions in the object is less
1442 than 2^31 bytes (2GB) and the distance from any instruction
1443 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1444 than 2^31 bytes (2GB).
1446 The executable must be in the low 4TB of the virtual address
1449 sethi %hi(symbol), %temp
1450 or %temp, %lo(symbol), %reg */
1451 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1452 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1456 /* The range spanned by all instructions in the object is less
1457 than 2^31 bytes (2GB) and the distance from any instruction
1458 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1459 than 2^31 bytes (2GB).
1461 The executable must be in the low 16TB of the virtual address
1464 sethi %h44(symbol), %temp1
1465 or %temp1, %m44(symbol), %temp2
1466 sllx %temp2, 12, %temp3
1467 or %temp3, %l44(symbol), %reg */
1468 emit_insn (gen_seth44 (op0
, op1
));
1469 emit_insn (gen_setm44 (op0
, op0
, op1
));
1470 emit_insn (gen_rtx_SET (VOIDmode
, temp1
,
1471 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (12))));
1472 emit_insn (gen_setl44 (op0
, temp1
, op1
));
1476 /* The range spanned by all instructions in the object is less
1477 than 2^31 bytes (2GB) and the distance from any instruction
1478 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1479 than 2^31 bytes (2GB).
1481 The executable can be placed anywhere in the virtual address
1484 sethi %hh(symbol), %temp1
1485 sethi %lm(symbol), %temp2
1486 or %temp1, %hm(symbol), %temp3
1487 or %temp2, %lo(symbol), %temp4
1488 sllx %temp3, 32, %temp5
1489 or %temp4, %temp5, %reg */
1491 /* It is possible that one of the registers we got for operands[2]
1492 might coincide with that of operands[0] (which is why we made
1493 it TImode). Pick the other one to use as our scratch. */
1494 if (rtx_equal_p (temp1
, op0
))
1497 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
) + 1);
1502 emit_insn (gen_sethh (op0
, op1
));
1503 emit_insn (gen_setlm (temp1
, op1
));
1504 emit_insn (gen_sethm (op0
, op0
, op1
));
1505 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1506 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1507 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1508 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1509 emit_insn (gen_setlo (op0
, op0
, op1
));
1513 /* Old old old backwards compatibility kruft here.
1514 Essentially it is MEDLOW with a fixed 64-bit
1515 virtual base added to all data segment addresses.
1516 Text-segment stuff is computed like MEDANY, we can't
1517 reuse the code above because the relocation knobs
1520 Data segment: sethi %hi(symbol), %temp1
1521 or %temp1, %lo(symbol), %temp2
1522 add %temp2, EMBMEDANY_BASE_REG, %reg
1524 Text segment: sethi %uhi(symbol), %temp1
1525 sethi %hi(symbol), %temp2
1526 or %temp1, %ulo(symbol), %temp3
1527 or %temp2, %lo(symbol), %temp4
1528 sllx %temp3, 32, %temp5
1529 or %temp4, %temp5, %reg */
1530 if (data_segment_operand (op1
, GET_MODE (op1
)))
1532 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1533 emit_insn (gen_embmedany_brsum (op0
, temp1
));
1534 emit_insn (gen_embmedany_losum (op0
, op0
, op1
));
1538 /* It is possible that one of the registers we got for operands[2]
1539 might coincide with that of operands[0] (which is why we made
1540 it TImode). Pick the other one to use as our scratch. */
1541 if (rtx_equal_p (temp1
, op0
))
1544 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
) + 1);
1549 emit_insn (gen_embmedany_textuhi (op0
, op1
));
1550 emit_insn (gen_embmedany_texthi (temp1
, op1
));
1551 emit_insn (gen_embmedany_textulo (op0
, op0
, op1
));
1552 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1553 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1554 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1555 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1556 emit_insn (gen_embmedany_textlo (op0
, op0
, op1
));
1565 /* These avoid problems when cross compiling. If we do not
1566 go through all this hair then the optimizer will see
1567 invalid REG_EQUAL notes or in some cases none at all. */
1568 static void sparc_emit_set_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
1569 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
1570 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
1571 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
1573 #if HOST_BITS_PER_WIDE_INT == 64
1574 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1575 #define GEN_INT64(__x) GEN_INT (__x)
1577 #define GEN_HIGHINT64(__x) \
1578 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1579 #define GEN_INT64(__x) \
1580 immed_double_const ((__x) & 0xffffffff, \
1581 ((__x) & 0x80000000 ? -1 : 0), DImode)
1584 /* The optimizer is not to assume anything about exactly
1585 which bits are set for a HIGH, they are unspecified.
1586 Unfortunately this leads to many missed optimizations
1587 during CSE. We mask out the non-HIGH bits, and matches
1588 a plain movdi, to alleviate this problem. */
1590 sparc_emit_set_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
1592 emit_insn (gen_rtx_SET (VOIDmode
, dest
, GEN_HIGHINT64 (val
)));
1596 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
1598 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT64 (val
));
1602 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
1604 return gen_rtx_IOR (DImode
, src
, GEN_INT64 (val
));
1608 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
1610 return gen_rtx_XOR (DImode
, src
, GEN_INT64 (val
));
1613 /* Worker routines for 64-bit constant formation on arch64.
1614 One of the key things to be doing in these emissions is
1615 to create as many temp REGs as possible. This makes it
1616 possible for half-built constants to be used later when
1617 such values are similar to something required later on.
1618 Without doing this, the optimizer cannot see such
1621 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
1622 unsigned HOST_WIDE_INT
, int);
1625 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
1626 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
1628 unsigned HOST_WIDE_INT high_bits
;
1631 high_bits
= (~low_bits
) & 0xffffffff;
1633 high_bits
= low_bits
;
1635 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1638 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1639 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1643 /* If we are XOR'ing with -1, then we should emit a one's complement
1644 instead. This way the combiner will notice logical operations
1645 such as ANDN later on and substitute. */
1646 if ((low_bits
& 0x3ff) == 0x3ff)
1648 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1649 gen_rtx_NOT (DImode
, temp
)));
1653 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1654 gen_safe_XOR64 (temp
,
1655 (-(HOST_WIDE_INT
)0x400
1656 | (low_bits
& 0x3ff)))));
1661 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1662 unsigned HOST_WIDE_INT
, int);
1665 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
1666 unsigned HOST_WIDE_INT high_bits
,
1667 unsigned HOST_WIDE_INT low_immediate
,
1672 if ((high_bits
& 0xfffffc00) != 0)
1674 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1675 if ((high_bits
& ~0xfffffc00) != 0)
1676 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1677 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1683 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1687 /* Now shift it up into place. */
1688 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1689 gen_rtx_ASHIFT (DImode
, temp2
,
1690 GEN_INT (shift_count
))));
1692 /* If there is a low immediate part piece, finish up by
1693 putting that in as well. */
1694 if (low_immediate
!= 0)
1695 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1696 gen_safe_OR64 (op0
, low_immediate
)));
1699 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1700 unsigned HOST_WIDE_INT
);
1702 /* Full 64-bit constant decomposition. Even though this is the
1703 'worst' case, we still optimize a few things away. */
1705 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
1706 unsigned HOST_WIDE_INT high_bits
,
1707 unsigned HOST_WIDE_INT low_bits
)
1711 if (reload_in_progress
|| reload_completed
)
1714 sub_temp
= gen_reg_rtx (DImode
);
1716 if ((high_bits
& 0xfffffc00) != 0)
1718 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1719 if ((high_bits
& ~0xfffffc00) != 0)
1720 emit_insn (gen_rtx_SET (VOIDmode
,
1722 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1728 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1732 if (!reload_in_progress
&& !reload_completed
)
1734 rtx temp2
= gen_reg_rtx (DImode
);
1735 rtx temp3
= gen_reg_rtx (DImode
);
1736 rtx temp4
= gen_reg_rtx (DImode
);
1738 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1739 gen_rtx_ASHIFT (DImode
, sub_temp
,
1742 sparc_emit_set_safe_HIGH64 (temp2
, low_bits
);
1743 if ((low_bits
& ~0xfffffc00) != 0)
1745 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1746 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1747 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1748 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1752 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1753 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1758 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1759 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1760 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1763 /* We are in the middle of reload, so this is really
1764 painful. However we do still make an attempt to
1765 avoid emitting truly stupid code. */
1766 if (low1
!= const0_rtx
)
1768 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1769 gen_rtx_ASHIFT (DImode
, sub_temp
,
1770 GEN_INT (to_shift
))));
1771 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1772 gen_rtx_IOR (DImode
, op0
, low1
)));
1780 if (low2
!= const0_rtx
)
1782 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1783 gen_rtx_ASHIFT (DImode
, sub_temp
,
1784 GEN_INT (to_shift
))));
1785 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1786 gen_rtx_IOR (DImode
, op0
, low2
)));
1794 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1795 gen_rtx_ASHIFT (DImode
, sub_temp
,
1796 GEN_INT (to_shift
))));
1797 if (low3
!= const0_rtx
)
1798 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1799 gen_rtx_IOR (DImode
, op0
, low3
)));
1804 /* Analyze a 64-bit constant for certain properties. */
1805 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
1806 unsigned HOST_WIDE_INT
,
1807 int *, int *, int *);
1810 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
1811 unsigned HOST_WIDE_INT low_bits
,
1812 int *hbsp
, int *lbsp
, int *abbasp
)
1814 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1817 lowest_bit_set
= highest_bit_set
= -1;
1821 if ((lowest_bit_set
== -1)
1822 && ((low_bits
>> i
) & 1))
1824 if ((highest_bit_set
== -1)
1825 && ((high_bits
>> (32 - i
- 1)) & 1))
1826 highest_bit_set
= (64 - i
- 1);
1829 && ((highest_bit_set
== -1)
1830 || (lowest_bit_set
== -1)));
1836 if ((lowest_bit_set
== -1)
1837 && ((high_bits
>> i
) & 1))
1838 lowest_bit_set
= i
+ 32;
1839 if ((highest_bit_set
== -1)
1840 && ((low_bits
>> (32 - i
- 1)) & 1))
1841 highest_bit_set
= 32 - i
- 1;
1844 && ((highest_bit_set
== -1)
1845 || (lowest_bit_set
== -1)));
1847 /* If there are no bits set this should have gone out
1848 as one instruction! */
1849 if (lowest_bit_set
== -1
1850 || highest_bit_set
== -1)
1852 all_bits_between_are_set
= 1;
1853 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1857 if ((low_bits
& (1 << i
)) != 0)
1862 if ((high_bits
& (1 << (i
- 32))) != 0)
1865 all_bits_between_are_set
= 0;
1868 *hbsp
= highest_bit_set
;
1869 *lbsp
= lowest_bit_set
;
1870 *abbasp
= all_bits_between_are_set
;
1873 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
1876 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
1877 unsigned HOST_WIDE_INT low_bits
)
1879 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1882 || high_bits
== 0xffffffff)
1885 analyze_64bit_constant (high_bits
, low_bits
,
1886 &highest_bit_set
, &lowest_bit_set
,
1887 &all_bits_between_are_set
);
1889 if ((highest_bit_set
== 63
1890 || lowest_bit_set
== 0)
1891 && all_bits_between_are_set
!= 0)
1894 if ((highest_bit_set
- lowest_bit_set
) < 21)
1900 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
1901 unsigned HOST_WIDE_INT
,
1904 static unsigned HOST_WIDE_INT
1905 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
1906 unsigned HOST_WIDE_INT low_bits
,
1907 int lowest_bit_set
, int shift
)
1909 HOST_WIDE_INT hi
, lo
;
1911 if (lowest_bit_set
< 32)
1913 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1914 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1919 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1926 /* Here we are sure to be arch64 and this is an integer constant
1927 being loaded into a register. Emit the most efficient
1928 insn sequence possible. Detection of all the 1-insn cases
1929 has been done already. */
1931 sparc_emit_set_const64 (rtx op0
, rtx op1
)
1933 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1934 int lowest_bit_set
, highest_bit_set
;
1935 int all_bits_between_are_set
;
1938 /* Sanity check that we know what we are working with. */
1939 if (! TARGET_ARCH64
)
1942 if (GET_CODE (op0
) != SUBREG
)
1944 if (GET_CODE (op0
) != REG
1945 || (REGNO (op0
) >= SPARC_FIRST_FP_REG
1946 && REGNO (op0
) <= SPARC_LAST_V9_FP_REG
))
1950 if (reload_in_progress
|| reload_completed
)
1953 temp
= gen_reg_rtx (DImode
);
1955 if (GET_CODE (op1
) != CONST_DOUBLE
1956 && GET_CODE (op1
) != CONST_INT
)
1958 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1962 if (GET_CODE (op1
) == CONST_DOUBLE
)
1964 #if HOST_BITS_PER_WIDE_INT == 64
1965 high_bits
= (CONST_DOUBLE_LOW (op1
) >> 32) & 0xffffffff;
1966 low_bits
= CONST_DOUBLE_LOW (op1
) & 0xffffffff;
1968 high_bits
= CONST_DOUBLE_HIGH (op1
);
1969 low_bits
= CONST_DOUBLE_LOW (op1
);
1974 #if HOST_BITS_PER_WIDE_INT == 64
1975 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1976 low_bits
= (INTVAL (op1
) & 0xffffffff);
1978 high_bits
= ((INTVAL (op1
) < 0) ?
1981 low_bits
= INTVAL (op1
);
1985 /* low_bits bits 0 --> 31
1986 high_bits bits 32 --> 63 */
1988 analyze_64bit_constant (high_bits
, low_bits
,
1989 &highest_bit_set
, &lowest_bit_set
,
1990 &all_bits_between_are_set
);
1992 /* First try for a 2-insn sequence. */
1994 /* These situations are preferred because the optimizer can
1995 * do more things with them:
1997 * sllx %reg, shift, %reg
1999 * srlx %reg, shift, %reg
2000 * 3) mov some_small_const, %reg
2001 * sllx %reg, shift, %reg
2003 if (((highest_bit_set
== 63
2004 || lowest_bit_set
== 0)
2005 && all_bits_between_are_set
!= 0)
2006 || ((highest_bit_set
- lowest_bit_set
) < 12))
2008 HOST_WIDE_INT the_const
= -1;
2009 int shift
= lowest_bit_set
;
2011 if ((highest_bit_set
!= 63
2012 && lowest_bit_set
!= 0)
2013 || all_bits_between_are_set
== 0)
2016 create_simple_focus_bits (high_bits
, low_bits
,
2019 else if (lowest_bit_set
== 0)
2020 shift
= -(63 - highest_bit_set
);
2022 if (! SPARC_SIMM13_P (the_const
))
2025 emit_insn (gen_safe_SET64 (temp
, the_const
));
2027 emit_insn (gen_rtx_SET (VOIDmode
,
2029 gen_rtx_ASHIFT (DImode
,
2033 emit_insn (gen_rtx_SET (VOIDmode
,
2035 gen_rtx_LSHIFTRT (DImode
,
2037 GEN_INT (-shift
))));
2043 /* Now a range of 22 or less bits set somewhere.
2044 * 1) sethi %hi(focus_bits), %reg
2045 * sllx %reg, shift, %reg
2046 * 2) sethi %hi(focus_bits), %reg
2047 * srlx %reg, shift, %reg
2049 if ((highest_bit_set
- lowest_bit_set
) < 21)
2051 unsigned HOST_WIDE_INT focus_bits
=
2052 create_simple_focus_bits (high_bits
, low_bits
,
2053 lowest_bit_set
, 10);
2055 if (! SPARC_SETHI_P (focus_bits
))
2058 sparc_emit_set_safe_HIGH64 (temp
, focus_bits
);
2060 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2061 if (lowest_bit_set
< 10)
2062 emit_insn (gen_rtx_SET (VOIDmode
,
2064 gen_rtx_LSHIFTRT (DImode
, temp
,
2065 GEN_INT (10 - lowest_bit_set
))));
2066 else if (lowest_bit_set
> 10)
2067 emit_insn (gen_rtx_SET (VOIDmode
,
2069 gen_rtx_ASHIFT (DImode
, temp
,
2070 GEN_INT (lowest_bit_set
- 10))));
2076 /* 1) sethi %hi(low_bits), %reg
2077 * or %reg, %lo(low_bits), %reg
2078 * 2) sethi %hi(~low_bits), %reg
2079 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2082 || high_bits
== 0xffffffff)
2084 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2085 (high_bits
== 0xffffffff));
2089 /* Now, try 3-insn sequences. */
2091 /* 1) sethi %hi(high_bits), %reg
2092 * or %reg, %lo(high_bits), %reg
2093 * sllx %reg, 32, %reg
2097 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2101 /* We may be able to do something quick
2102 when the constant is negated, so try that. */
2103 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2104 (~low_bits
) & 0xfffffc00))
2106 /* NOTE: The trailing bits get XOR'd so we need the
2107 non-negated bits, not the negated ones. */
2108 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2110 if ((((~high_bits
) & 0xffffffff) == 0
2111 && ((~low_bits
) & 0x80000000) == 0)
2112 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2113 && ((~low_bits
) & 0x80000000) != 0))
2115 int fast_int
= (~low_bits
& 0xffffffff);
2117 if ((SPARC_SETHI_P (fast_int
)
2118 && (~high_bits
& 0xffffffff) == 0)
2119 || SPARC_SIMM13_P (fast_int
))
2120 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2122 sparc_emit_set_const64 (temp
, GEN_INT64 (fast_int
));
2127 #if HOST_BITS_PER_WIDE_INT == 64
2128 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2129 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2131 negated_const
= immed_double_const ((~low_bits
) & 0xfffffc00,
2132 (~high_bits
) & 0xffffffff,
2135 sparc_emit_set_const64 (temp
, negated_const
);
2138 /* If we are XOR'ing with -1, then we should emit a one's complement
2139 instead. This way the combiner will notice logical operations
2140 such as ANDN later on and substitute. */
2141 if (trailing_bits
== 0x3ff)
2143 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2144 gen_rtx_NOT (DImode
, temp
)));
2148 emit_insn (gen_rtx_SET (VOIDmode
,
2150 gen_safe_XOR64 (temp
,
2151 (-0x400 | trailing_bits
))));
2156 /* 1) sethi %hi(xxx), %reg
2157 * or %reg, %lo(xxx), %reg
2158 * sllx %reg, yyy, %reg
2160 * ??? This is just a generalized version of the low_bits==0
2161 * thing above, FIXME...
2163 if ((highest_bit_set
- lowest_bit_set
) < 32)
2165 unsigned HOST_WIDE_INT focus_bits
=
2166 create_simple_focus_bits (high_bits
, low_bits
,
2169 /* We can't get here in this state. */
2170 if (highest_bit_set
< 32
2171 || lowest_bit_set
>= 32)
2174 /* So what we know is that the set bits straddle the
2175 middle of the 64-bit word. */
2176 sparc_emit_set_const64_quick2 (op0
, temp
,
2182 /* 1) sethi %hi(high_bits), %reg
2183 * or %reg, %lo(high_bits), %reg
2184 * sllx %reg, 32, %reg
2185 * or %reg, low_bits, %reg
2187 if (SPARC_SIMM13_P(low_bits
)
2188 && ((int)low_bits
> 0))
2190 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2194 /* The easiest way when all else fails, is full decomposition. */
2196 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2197 high_bits
, low_bits
, ~high_bits
, ~low_bits
);
2199 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2202 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2203 return the mode to be used for the comparison. For floating-point,
2204 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2205 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2206 processing is needed. */
2209 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2211 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2237 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2238 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2240 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2241 return CCX_NOOVmode
;
2247 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2254 /* X and Y are two things to compare using CODE. Emit the compare insn and
2255 return the rtx for the cc reg in the proper mode. */
2258 gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
2260 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
2263 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2264 fcc regs (cse can't tell they're really call clobbered regs and will
2265 remove a duplicate comparison even if there is an intervening function
2266 call - it will then try to reload the cc reg via an int reg which is why
2267 we need the movcc patterns). It is possible to provide the movcc
2268 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2269 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2270 to tell cse that CCFPE mode registers (even pseudos) are call
2273 /* ??? This is an experiment. Rather than making changes to cse which may
2274 or may not be easy/clean, we do our own cse. This is possible because
2275 we will generate hard registers. Cse knows they're call clobbered (it
2276 doesn't know the same thing about pseudos). If we guess wrong, no big
2277 deal, but if we win, great! */
2279 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2280 #if 1 /* experiment */
2283 /* We cycle through the registers to ensure they're all exercised. */
2284 static int next_fcc_reg
= 0;
2285 /* Previous x,y for each fcc reg. */
2286 static rtx prev_args
[4][2];
2288 /* Scan prev_args for x,y. */
2289 for (reg
= 0; reg
< 4; reg
++)
2290 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2295 prev_args
[reg
][0] = x
;
2296 prev_args
[reg
][1] = y
;
2297 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2299 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2302 cc_reg
= gen_reg_rtx (mode
);
2303 #endif /* ! experiment */
2304 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2305 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2307 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2309 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
2310 gen_rtx_COMPARE (mode
, x
, y
)));
2315 /* This function is used for v9 only.
2316 CODE is the code for an Scc's comparison.
2317 OPERANDS[0] is the target of the Scc insn.
2318 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2319 been generated yet).
2321 This function is needed to turn
2324 (gt (reg:CCX 100 %icc)
2328 (gt:DI (reg:CCX 100 %icc)
2331 IE: The instruction recognizer needs to see the mode of the comparison to
2332 find the right instruction. We could use "gt:DI" right in the
2333 define_expand, but leaving it out allows us to handle DI, SI, etc.
2335 We refer to the global sparc compare operands sparc_compare_op0 and
2336 sparc_compare_op1. */
2339 gen_v9_scc (enum rtx_code compare_code
, register rtx
*operands
)
2344 && (GET_MODE (sparc_compare_op0
) == DImode
2345 || GET_MODE (operands
[0]) == DImode
))
2348 op0
= sparc_compare_op0
;
2349 op1
= sparc_compare_op1
;
2351 /* Try to use the movrCC insns. */
2353 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
2354 && op1
== const0_rtx
2355 && v9_regcmp_p (compare_code
))
2357 /* Special case for op0 != 0. This can be done with one instruction if
2358 operands[0] == sparc_compare_op0. */
2360 if (compare_code
== NE
2361 && GET_MODE (operands
[0]) == DImode
2362 && rtx_equal_p (op0
, operands
[0]))
2364 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2365 gen_rtx_IF_THEN_ELSE (DImode
,
2366 gen_rtx_fmt_ee (compare_code
, DImode
,
2373 if (reg_overlap_mentioned_p (operands
[0], op0
))
2375 /* Handle the case where operands[0] == sparc_compare_op0.
2376 We "early clobber" the result. */
2377 op0
= gen_reg_rtx (GET_MODE (sparc_compare_op0
));
2378 emit_move_insn (op0
, sparc_compare_op0
);
2381 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2382 if (GET_MODE (op0
) != DImode
)
2384 temp
= gen_reg_rtx (DImode
);
2385 convert_move (temp
, op0
, 0);
2389 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2390 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2391 gen_rtx_fmt_ee (compare_code
, DImode
,
2399 operands
[1] = gen_compare_reg (compare_code
, op0
, op1
);
2401 switch (GET_MODE (operands
[1]))
2411 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2412 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2413 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2414 gen_rtx_fmt_ee (compare_code
,
2415 GET_MODE (operands
[1]),
2416 operands
[1], const0_rtx
),
2417 const1_rtx
, operands
[0])));
2422 /* Emit a conditional jump insn for the v9 architecture using comparison code
2423 CODE and jump target LABEL.
2424 This function exists to take advantage of the v9 brxx insns. */
2427 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
2429 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2431 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2432 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2434 gen_rtx_LABEL_REF (VOIDmode
, label
),
2438 /* Generate a DFmode part of a hard TFmode register.
2439 REG is the TFmode hard register, LOW is 1 for the
2440 low 64bit of the register and 0 otherwise.
2443 gen_df_reg (rtx reg
, int low
)
2445 int regno
= REGNO (reg
);
2447 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2448 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2449 return gen_rtx_REG (DFmode
, regno
);
2452 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2453 Unlike normal calls, TFmode operands are passed by reference. It is
2454 assumed that no more than 3 operands are required. */
2457 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
2459 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2462 /* We only expect to be called for conversions, unary, and binary ops. */
2463 if (nargs
< 2 || nargs
> 3)
2466 for (i
= 0; i
< nargs
; ++i
)
2468 rtx this_arg
= operands
[i
];
2471 /* TFmode arguments and return values are passed by reference. */
2472 if (GET_MODE (this_arg
) == TFmode
)
2474 int force_stack_temp
;
2476 force_stack_temp
= 0;
2477 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2478 force_stack_temp
= 1;
2480 if (GET_CODE (this_arg
) == MEM
2481 && ! force_stack_temp
)
2482 this_arg
= XEXP (this_arg
, 0);
2483 else if (CONSTANT_P (this_arg
)
2484 && ! force_stack_temp
)
2486 this_slot
= force_const_mem (TFmode
, this_arg
);
2487 this_arg
= XEXP (this_slot
, 0);
2491 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2493 /* Operand 0 is the return value. We'll copy it out later. */
2495 emit_move_insn (this_slot
, this_arg
);
2497 ret_slot
= this_slot
;
2499 this_arg
= XEXP (this_slot
, 0);
2506 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2508 if (GET_MODE (operands
[0]) == TFmode
)
2511 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2512 arg
[0], GET_MODE (arg
[0]),
2513 arg
[1], GET_MODE (arg
[1]));
2515 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2516 arg
[0], GET_MODE (arg
[0]),
2517 arg
[1], GET_MODE (arg
[1]),
2518 arg
[2], GET_MODE (arg
[2]));
2521 emit_move_insn (operands
[0], ret_slot
);
2530 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2531 GET_MODE (operands
[0]), 1,
2532 arg
[1], GET_MODE (arg
[1]));
2534 if (ret
!= operands
[0])
2535 emit_move_insn (operands
[0], ret
);
2539 /* Expand soft-float TFmode calls to sparc abi routines. */
2542 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2564 emit_soft_tfmode_libcall (func
, 3, operands
);
2568 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2581 emit_soft_tfmode_libcall (func
, 2, operands
);
2585 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2592 switch (GET_MODE (operands
[1]))
2605 case FLOAT_TRUNCATE
:
2606 switch (GET_MODE (operands
[0]))
2620 switch (GET_MODE (operands
[1]))
2633 case UNSIGNED_FLOAT
:
2634 switch (GET_MODE (operands
[1]))
2648 switch (GET_MODE (operands
[0]))
2662 switch (GET_MODE (operands
[0]))
2679 emit_soft_tfmode_libcall (func
, 2, operands
);
2682 /* Expand a hard-float tfmode operation. All arguments must be in
2686 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
2690 if (GET_RTX_CLASS (code
) == '1')
2692 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2693 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2697 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2698 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2699 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2700 operands
[1], operands
[2]);
2703 if (register_operand (operands
[0], VOIDmode
))
2706 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2708 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2710 if (dest
!= operands
[0])
2711 emit_move_insn (operands
[0], dest
);
2715 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2717 if (TARGET_HARD_QUAD
)
2718 emit_hard_tfmode_operation (code
, operands
);
2720 emit_soft_tfmode_binop (code
, operands
);
2724 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2726 if (TARGET_HARD_QUAD
)
2727 emit_hard_tfmode_operation (code
, operands
);
2729 emit_soft_tfmode_unop (code
, operands
);
2733 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2735 if (TARGET_HARD_QUAD
)
2736 emit_hard_tfmode_operation (code
, operands
);
2738 emit_soft_tfmode_cvt (code
, operands
);
2741 /* Return nonzero if a return peephole merging return with
2742 setting of output register is ok. */
2744 leaf_return_peephole_ok (void)
2746 return (actual_fsize
== 0);
2749 /* Return nonzero if a branch/jump/call instruction will be emitting
2750 nop into its delay slot. */
2753 empty_delay_slot (rtx insn
)
2757 /* If no previous instruction (should not happen), return true. */
2758 if (PREV_INSN (insn
) == NULL
)
2761 seq
= NEXT_INSN (PREV_INSN (insn
));
2762 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2768 /* Return nonzero if TRIAL can go into the function epilogue's
2769 delay slot. SLOT is the slot we are trying to fill. */
2772 eligible_for_epilogue_delay (rtx trial
, int slot
)
2779 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2782 if (get_attr_length (trial
) != 1)
2785 /* If there are any call-saved registers, we should scan TRIAL if it
2786 does not reference them. For now just make it easy. */
2790 /* If the function uses __builtin_eh_return, the eh_return machinery
2791 occupies the delay slot. */
2792 if (current_function_calls_eh_return
)
2795 /* In the case of a true leaf function, anything can go into the delay slot.
2796 A delay slot only exists however if the frame size is zero, otherwise
2797 we will put an insn to adjust the stack after the return. */
2798 if (current_function_uses_only_leaf_regs
)
2800 if (leaf_return_peephole_ok ())
2801 return ((get_attr_in_uncond_branch_delay (trial
)
2802 == IN_BRANCH_DELAY_TRUE
));
2806 pat
= PATTERN (trial
);
2808 /* Otherwise, only operations which can be done in tandem with
2809 a `restore' or `return' insn can go into the delay slot. */
2810 if (GET_CODE (SET_DEST (pat
)) != REG
2811 || REGNO (SET_DEST (pat
)) < 24)
2814 /* If this instruction sets up floating point register and we have a return
2815 instruction, it can probably go in. But restore will not work
2817 if (REGNO (SET_DEST (pat
)) >= 32)
2819 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2820 && (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
))
2825 /* The set of insns matched here must agree precisely with the set of
2826 patterns paired with a RETURN in sparc.md. */
2828 src
= SET_SRC (pat
);
2830 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2831 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2832 && arith_operand (src
, GET_MODE (src
)))
2835 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2837 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2840 /* This matches "*return_di". */
2841 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2842 && arith_double_operand (src
, GET_MODE (src
)))
2843 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2845 /* This matches "*return_sf_no_fpu". */
2846 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
2847 && register_operand (src
, SFmode
))
2850 /* If we have return instruction, anything that does not use
2851 local or output registers and can go into a delay slot wins. */
2852 else if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2853 && (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
))
2856 /* This matches "*return_addsi". */
2857 else if (GET_CODE (src
) == PLUS
2858 && arith_operand (XEXP (src
, 0), SImode
)
2859 && arith_operand (XEXP (src
, 1), SImode
)
2860 && (register_operand (XEXP (src
, 0), SImode
)
2861 || register_operand (XEXP (src
, 1), SImode
)))
2864 /* This matches "*return_adddi". */
2865 else if (GET_CODE (src
) == PLUS
2866 && arith_double_operand (XEXP (src
, 0), DImode
)
2867 && arith_double_operand (XEXP (src
, 1), DImode
)
2868 && (register_operand (XEXP (src
, 0), DImode
)
2869 || register_operand (XEXP (src
, 1), DImode
)))
2872 /* This can match "*return_losum_[sd]i".
2873 Catch only some cases, so that return_losum* don't have
2875 else if (GET_CODE (src
) == LO_SUM
2876 && ! TARGET_CM_MEDMID
2877 && ((register_operand (XEXP (src
, 0), SImode
)
2878 && immediate_operand (XEXP (src
, 1), SImode
))
2880 && register_operand (XEXP (src
, 0), DImode
)
2881 && immediate_operand (XEXP (src
, 1), DImode
))))
2884 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2885 else if (GET_CODE (src
) == ASHIFT
2886 && (register_operand (XEXP (src
, 0), SImode
)
2887 || register_operand (XEXP (src
, 0), DImode
))
2888 && XEXP (src
, 1) == const1_rtx
)
2894 /* Return nonzero if TRIAL can go into the call delay slot. */
2896 tls_call_delay (rtx trial
)
2901 call __tls_get_addr, %tgd_call (foo)
2902 add %l7, %o0, %o0, %tgd_add (foo)
2903 while Sun as/ld does not. */
2904 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
2907 pat
= PATTERN (trial
);
2908 if (GET_CODE (pat
) != SET
|| GET_CODE (SET_DEST (pat
)) != PLUS
)
2911 unspec
= XEXP (SET_DEST (pat
), 1);
2912 if (GET_CODE (unspec
) != UNSPEC
2913 || (XINT (unspec
, 1) != UNSPEC_TLSGD
2914 && XINT (unspec
, 1) != UNSPEC_TLSLDM
))
2920 /* Return nonzero if TRIAL can go into the sibling call
2924 eligible_for_sibcall_delay (rtx trial
)
2928 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2931 if (get_attr_length (trial
) != 1)
2934 pat
= PATTERN (trial
);
2936 if (current_function_uses_only_leaf_regs
)
2938 /* If the tail call is done using the call instruction,
2939 we have to restore %o7 in the delay slot. */
2940 if ((TARGET_ARCH64
&& ! TARGET_CM_MEDLOW
) || flag_pic
)
2943 /* %g1 is used to build the function address */
2944 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2950 /* Otherwise, only operations which can be done in tandem with
2951 a `restore' insn can go into the delay slot. */
2952 if (GET_CODE (SET_DEST (pat
)) != REG
2953 || REGNO (SET_DEST (pat
)) < 24
2954 || REGNO (SET_DEST (pat
)) >= 32)
2957 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2959 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2962 src
= SET_SRC (pat
);
2964 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2965 && arith_operand (src
, GET_MODE (src
)))
2968 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2970 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2973 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2974 && arith_double_operand (src
, GET_MODE (src
)))
2975 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2977 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
2978 && register_operand (src
, SFmode
))
2981 else if (GET_CODE (src
) == PLUS
2982 && arith_operand (XEXP (src
, 0), SImode
)
2983 && arith_operand (XEXP (src
, 1), SImode
)
2984 && (register_operand (XEXP (src
, 0), SImode
)
2985 || register_operand (XEXP (src
, 1), SImode
)))
2988 else if (GET_CODE (src
) == PLUS
2989 && arith_double_operand (XEXP (src
, 0), DImode
)
2990 && arith_double_operand (XEXP (src
, 1), DImode
)
2991 && (register_operand (XEXP (src
, 0), DImode
)
2992 || register_operand (XEXP (src
, 1), DImode
)))
2995 else if (GET_CODE (src
) == LO_SUM
2996 && ! TARGET_CM_MEDMID
2997 && ((register_operand (XEXP (src
, 0), SImode
)
2998 && immediate_operand (XEXP (src
, 1), SImode
))
3000 && register_operand (XEXP (src
, 0), DImode
)
3001 && immediate_operand (XEXP (src
, 1), DImode
))))
3004 else if (GET_CODE (src
) == ASHIFT
3005 && (register_operand (XEXP (src
, 0), SImode
)
3006 || register_operand (XEXP (src
, 0), DImode
))
3007 && XEXP (src
, 1) == const1_rtx
)
3014 check_return_regs (rtx x
)
3016 switch (GET_CODE (x
))
3019 return IN_OR_GLOBAL_P (x
);
3034 if (check_return_regs (XEXP (x
, 1)) == 0)
3039 return check_return_regs (XEXP (x
, 0));
3048 short_branch (int uid1
, int uid2
)
3050 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
3052 /* Leave a few words of "slop". */
3053 if (delta
>= -1023 && delta
<= 1022)
3059 /* Return nonzero if REG is not used after INSN.
3060 We assume REG is a reload reg, and therefore does
3061 not live past labels or calls or jumps. */
3063 reg_unused_after (rtx reg
, rtx insn
)
3065 enum rtx_code code
, prev_code
= UNKNOWN
;
3067 while ((insn
= NEXT_INSN (insn
)))
3069 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
3072 code
= GET_CODE (insn
);
3073 if (GET_CODE (insn
) == CODE_LABEL
)
3076 if (GET_RTX_CLASS (code
) == 'i')
3078 rtx set
= single_set (insn
);
3079 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
3082 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
3084 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
3092 /* Determine if it's legal to put X into the constant pool. This
3093 is not possible if X contains the address of a symbol that is
3094 not constant (TLS) or not known at final link time (PIC). */
3097 sparc_cannot_force_const_mem (rtx x
)
3099 switch (GET_CODE (x
))
3103 /* Accept all non-symbolic constants. */
3107 /* Labels are OK iff we are non-PIC. */
3108 return flag_pic
!= 0;
3111 /* 'Naked' TLS symbol references are never OK,
3112 non-TLS symbols are OK iff we are non-PIC. */
3113 if (SYMBOL_REF_TLS_MODEL (x
))
3116 return flag_pic
!= 0;
3119 return sparc_cannot_force_const_mem (XEXP (x
, 0));
3122 return sparc_cannot_force_const_mem (XEXP (x
, 0))
3123 || sparc_cannot_force_const_mem (XEXP (x
, 1));
3131 /* The table we use to reference PIC data. */
3132 static GTY(()) rtx global_offset_table
;
3134 /* The function we use to get at it. */
3135 static GTY(()) rtx get_pc_symbol
;
3136 static char get_pc_symbol_name
[256];
3138 /* Ensure that we are not using patterns that are not OK with PIC. */
3146 if (GET_CODE (recog_data
.operand
[i
]) == SYMBOL_REF
3147 || (GET_CODE (recog_data
.operand
[i
]) == CONST
3148 && ! (GET_CODE (XEXP (recog_data
.operand
[i
], 0)) == MINUS
3149 && (XEXP (XEXP (recog_data
.operand
[i
], 0), 0)
3150 == global_offset_table
)
3151 && (GET_CODE (XEXP (XEXP (recog_data
.operand
[i
], 0), 1))
3160 /* Return true if X is an address which needs a temporary register when
3161 reloaded while generating PIC code. */
3164 pic_address_needs_scratch (rtx x
)
3166 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3167 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3168 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3169 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3170 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3176 /* Determine if a given RTX is a valid constant. We already know this
3177 satisfies CONSTANT_P. */
3180 legitimate_constant_p (rtx x
)
3184 switch (GET_CODE (x
))
3187 /* TLS symbols are not constant. */
3188 if (SYMBOL_REF_TLS_MODEL (x
))
3193 inner
= XEXP (x
, 0);
3195 /* Offsets of TLS symbols are never valid.
3196 Discourage CSE from creating them. */
3197 if (GET_CODE (inner
) == PLUS
3198 && tls_symbolic_operand (XEXP (inner
, 0)))
3203 if (GET_MODE (x
) == VOIDmode
)
3206 /* Floating point constants are generally not ok.
3207 The only exception is 0.0 in VIS. */
3209 && (GET_MODE (x
) == SFmode
3210 || GET_MODE (x
) == DFmode
3211 || GET_MODE (x
) == TFmode
)
3212 && fp_zero_operand (x
, GET_MODE (x
)))
3224 /* Determine if a given RTX is a valid constant address. */
3227 constant_address_p (rtx x
)
3229 switch (GET_CODE (x
))
3237 if (flag_pic
&& pic_address_needs_scratch (x
))
3239 return legitimate_constant_p (x
);
3242 return !flag_pic
&& legitimate_constant_p (x
);
3249 /* Nonzero if the constant value X is a legitimate general operand
3250 when generating PIC code. It is given that flag_pic is on and
3251 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3254 legitimate_pic_operand_p (rtx x
)
3256 if (pic_address_needs_scratch (x
))
3258 if (tls_symbolic_operand (x
)
3259 || (GET_CODE (x
) == CONST
3260 && GET_CODE (XEXP (x
, 0)) == PLUS
3261 && tls_symbolic_operand (XEXP (XEXP (x
, 0), 0))))
3266 /* Return nonzero if ADDR is a valid memory address.
3267 STRICT specifies whether strict register checking applies. */
3270 legitimate_address_p (enum machine_mode mode
, rtx addr
, int strict
)
3272 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
, imm2
;
3274 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3276 else if (GET_CODE (addr
) == PLUS
)
3278 rs1
= XEXP (addr
, 0);
3279 rs2
= XEXP (addr
, 1);
3281 /* Canonicalize. REG comes first, if there are no regs,
3282 LO_SUM comes first. */
3284 && GET_CODE (rs1
) != SUBREG
3286 || GET_CODE (rs2
) == SUBREG
3287 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3289 rs1
= XEXP (addr
, 1);
3290 rs2
= XEXP (addr
, 0);
3294 && rs1
== pic_offset_table_rtx
3296 && GET_CODE (rs2
) != SUBREG
3297 && GET_CODE (rs2
) != LO_SUM
3298 && GET_CODE (rs2
) != MEM
3299 && !tls_symbolic_operand (rs2
)
3300 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3301 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3303 || GET_CODE (rs1
) == SUBREG
)
3304 && RTX_OK_FOR_OFFSET_P (rs2
)))
3309 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3310 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3312 /* We prohibit REG + REG for TFmode when there are no instructions
3313 which accept REG+REG instructions. We do this because REG+REG
3314 is not an offsetable address. If we get the situation in reload
3315 where source and destination of a movtf pattern are both MEMs with
3316 REG+REG address, then only one of them gets converted to an
3317 offsetable address. */
3319 && !(TARGET_FPU
&& TARGET_ARCH64
&& TARGET_V9
3320 && TARGET_HARD_QUAD
))
3323 /* We prohibit REG + REG on ARCH32 if not optimizing for
3324 DFmode/DImode because then mem_min_alignment is likely to be zero
3325 after reload and the forced split would lack a matching splitter
3327 if (TARGET_ARCH32
&& !optimize
3328 && (mode
== DFmode
|| mode
== DImode
))
3331 else if (USE_AS_OFFSETABLE_LO10
3332 && GET_CODE (rs1
) == LO_SUM
3334 && ! TARGET_CM_MEDMID
3335 && RTX_OK_FOR_OLO10_P (rs2
))
3339 imm1
= XEXP (rs1
, 1);
3340 rs1
= XEXP (rs1
, 0);
3341 if (! CONSTANT_P (imm1
) || tls_symbolic_operand (rs1
))
3345 else if (GET_CODE (addr
) == LO_SUM
)
3347 rs1
= XEXP (addr
, 0);
3348 imm1
= XEXP (addr
, 1);
3350 if (! CONSTANT_P (imm1
) || tls_symbolic_operand (rs1
))
3353 /* We can't allow TFmode, because an offset greater than or equal to the
3354 alignment (8) may cause the LO_SUM to overflow if !v9. */
3355 if (mode
== TFmode
&& !TARGET_V9
)
3358 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
3363 if (GET_CODE (rs1
) == SUBREG
)
3364 rs1
= SUBREG_REG (rs1
);
3370 if (GET_CODE (rs2
) == SUBREG
)
3371 rs2
= SUBREG_REG (rs2
);
3378 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
3379 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
3384 if ((REGNO (rs1
) >= 32
3385 && REGNO (rs1
) != FRAME_POINTER_REGNUM
3386 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
3388 && (REGNO (rs2
) >= 32
3389 && REGNO (rs2
) != FRAME_POINTER_REGNUM
3390 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
3396 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3398 static GTY(()) rtx sparc_tls_symbol
;
3400 sparc_tls_get_addr (void)
3402 if (!sparc_tls_symbol
)
3403 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
3405 return sparc_tls_symbol
;
3409 sparc_tls_got (void)
3414 current_function_uses_pic_offset_table
= 1;
3415 return pic_offset_table_rtx
;
3418 if (!global_offset_table
)
3419 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3420 temp
= gen_reg_rtx (Pmode
);
3421 emit_move_insn (temp
, global_offset_table
);
3426 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3427 this (thread-local) address. */
3430 legitimize_tls_address (rtx addr
)
3432 rtx temp1
, temp2
, temp3
, ret
, o0
, got
, insn
;
3437 if (GET_CODE (addr
) == SYMBOL_REF
)
3438 switch (SYMBOL_REF_TLS_MODEL (addr
))
3440 case TLS_MODEL_GLOBAL_DYNAMIC
:
3442 temp1
= gen_reg_rtx (SImode
);
3443 temp2
= gen_reg_rtx (SImode
);
3444 ret
= gen_reg_rtx (Pmode
);
3445 o0
= gen_rtx_REG (Pmode
, 8);
3446 got
= sparc_tls_got ();
3447 emit_insn (gen_tgd_hi22 (temp1
, addr
));
3448 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
3451 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
3452 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
3457 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
3458 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
3461 CALL_INSN_FUNCTION_USAGE (insn
)
3462 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, o0
),
3463 CALL_INSN_FUNCTION_USAGE (insn
));
3464 insn
= get_insns ();
3466 emit_libcall_block (insn
, ret
, o0
, addr
);
3469 case TLS_MODEL_LOCAL_DYNAMIC
:
3471 temp1
= gen_reg_rtx (SImode
);
3472 temp2
= gen_reg_rtx (SImode
);
3473 temp3
= gen_reg_rtx (Pmode
);
3474 ret
= gen_reg_rtx (Pmode
);
3475 o0
= gen_rtx_REG (Pmode
, 8);
3476 got
= sparc_tls_got ();
3477 emit_insn (gen_tldm_hi22 (temp1
));
3478 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
3481 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
3482 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
3487 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
3488 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
3491 CALL_INSN_FUNCTION_USAGE (insn
)
3492 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, o0
),
3493 CALL_INSN_FUNCTION_USAGE (insn
));
3494 insn
= get_insns ();
3496 emit_libcall_block (insn
, temp3
, o0
,
3497 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3498 UNSPEC_TLSLD_BASE
));
3499 temp1
= gen_reg_rtx (SImode
);
3500 temp2
= gen_reg_rtx (SImode
);
3501 emit_insn (gen_tldo_hix22 (temp1
, addr
));
3502 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
3504 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
3506 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
3509 case TLS_MODEL_INITIAL_EXEC
:
3510 temp1
= gen_reg_rtx (SImode
);
3511 temp2
= gen_reg_rtx (SImode
);
3512 temp3
= gen_reg_rtx (Pmode
);
3513 got
= sparc_tls_got ();
3514 emit_insn (gen_tie_hi22 (temp1
, addr
));
3515 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
3517 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
3519 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
3522 ret
= gen_reg_rtx (Pmode
);
3524 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
3527 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
3531 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
3534 case TLS_MODEL_LOCAL_EXEC
:
3535 temp1
= gen_reg_rtx (Pmode
);
3536 temp2
= gen_reg_rtx (Pmode
);
3539 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
3540 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
3544 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
3545 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
3547 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
3555 abort (); /* for now ... */
3561 /* Legitimize PIC addresses. If the address is already position-independent,
3562 we return ORIG. Newly generated position-independent addresses go into a
3563 reg. This is REG if nonzero, otherwise we allocate register(s) as
3567 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
3570 if (GET_CODE (orig
) == SYMBOL_REF
)
3572 rtx pic_ref
, address
;
3577 if (reload_in_progress
|| reload_completed
)
3580 reg
= gen_reg_rtx (Pmode
);
3585 /* If not during reload, allocate another temp reg here for loading
3586 in the address, so that these instructions can be optimized
3588 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3589 ? reg
: gen_reg_rtx (Pmode
));
3591 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3592 won't get confused into thinking that these two instructions
3593 are loading in the true address of the symbol. If in the
3594 future a PIC rtx exists, that should be used instead. */
3595 if (Pmode
== SImode
)
3597 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3598 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3602 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3603 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3610 pic_ref
= gen_rtx_MEM (Pmode
,
3611 gen_rtx_PLUS (Pmode
,
3612 pic_offset_table_rtx
, address
));
3613 current_function_uses_pic_offset_table
= 1;
3614 RTX_UNCHANGING_P (pic_ref
) = 1;
3615 insn
= emit_move_insn (reg
, pic_ref
);
3616 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3618 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3622 else if (GET_CODE (orig
) == CONST
)
3626 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3627 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3632 if (reload_in_progress
|| reload_completed
)
3635 reg
= gen_reg_rtx (Pmode
);
3638 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
3640 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3641 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3642 base
== reg
? 0 : reg
);
3647 if (GET_CODE (offset
) == CONST_INT
)
3649 if (SMALL_INT (offset
))
3650 return plus_constant (base
, INTVAL (offset
));
3651 else if (! reload_in_progress
&& ! reload_completed
)
3652 offset
= force_reg (Pmode
, offset
);
3654 /* If we reach here, then something is seriously wrong. */
3657 return gen_rtx_PLUS (Pmode
, base
, offset
);
3659 else if (GET_CODE (orig
) == LABEL_REF
)
3660 /* ??? Why do we do this? */
3661 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3662 the register is live instead, in case it is eliminated. */
3663 current_function_uses_pic_offset_table
= 1;
3668 /* Try machine-dependent ways of modifying an illegitimate address X
3669 to be legitimate. If we find one, return the new, valid address.
3671 OLDX is the address as it was before break_out_memory_refs was called.
3672 In some cases it is useful to look at this to decide what needs to be done.
3674 MODE is the mode of the operand pointed to by X. */
3677 legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
, enum machine_mode mode
)
3681 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
3682 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3683 force_operand (XEXP (x
, 0), NULL_RTX
));
3684 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
3685 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3686 force_operand (XEXP (x
, 1), NULL_RTX
));
3687 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3688 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
3690 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
3691 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3692 force_operand (XEXP (x
, 1), NULL_RTX
));
3694 if (x
!= orig_x
&& legitimate_address_p (mode
, x
, FALSE
))
3697 if (tls_symbolic_operand (x
))
3698 x
= legitimize_tls_address (x
);
3700 x
= legitimize_pic_address (x
, mode
, 0);
3701 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
3702 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3703 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
3704 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
3705 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3706 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
3707 else if (GET_CODE (x
) == SYMBOL_REF
3708 || GET_CODE (x
) == CONST
3709 || GET_CODE (x
) == LABEL_REF
)
3710 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
3714 /* Emit special PIC prologues. */
3717 load_pic_register (void)
3719 /* Labels to get the PC in the prologue of this function. */
3720 int orig_flag_pic
= flag_pic
;
3725 /* If we haven't emitted the special get_pc helper function, do so now. */
3726 if (get_pc_symbol_name
[0] == 0)
3730 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name
, "LGETPC", 0);
3733 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
3735 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
3736 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LGETPC", 0);
3737 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file
);
3740 /* Initialize every time through, since we can't easily
3741 know this to be permanent. */
3742 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3743 get_pc_symbol
= gen_rtx_SYMBOL_REF (Pmode
, get_pc_symbol_name
);
3746 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
3749 flag_pic
= orig_flag_pic
;
3751 /* Need to emit this whether or not we obey regdecls,
3752 since setjmp/longjmp can cause life info to screw up.
3753 ??? In the case where we don't obey regdecls, this is not sufficient
3754 since we may not fall out the bottom. */
3755 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3758 /* Return 1 if RTX is a MEM which is known to be aligned to at
3759 least a DESIRED byte boundary. */
3762 mem_min_alignment (rtx mem
, int desired
)
3764 rtx addr
, base
, offset
;
3766 /* If it's not a MEM we can't accept it. */
3767 if (GET_CODE (mem
) != MEM
)
3770 addr
= XEXP (mem
, 0);
3771 base
= offset
= NULL_RTX
;
3772 if (GET_CODE (addr
) == PLUS
)
3774 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3776 base
= XEXP (addr
, 0);
3778 /* What we are saying here is that if the base
3779 REG is aligned properly, the compiler will make
3780 sure any REG based index upon it will be so
3782 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3783 offset
= XEXP (addr
, 1);
3785 offset
= const0_rtx
;
3788 else if (GET_CODE (addr
) == REG
)
3791 offset
= const0_rtx
;
3794 if (base
!= NULL_RTX
)
3796 int regno
= REGNO (base
);
3798 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3800 /* Check if the compiler has recorded some information
3801 about the alignment of the base REG. If reload has
3802 completed, we already matched with proper alignments.
3803 If not running global_alloc, reload might give us
3804 unaligned pointer to local stack though. */
3806 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3807 || (optimize
&& reload_completed
))
3808 && (INTVAL (offset
) & (desired
- 1)) == 0)
3813 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3817 else if (! TARGET_UNALIGNED_DOUBLES
3818 || CONSTANT_P (addr
)
3819 || GET_CODE (addr
) == LO_SUM
)
3821 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3822 is true, in which case we can only assume that an access is aligned if
3823 it is to a constant address, or the address involves a LO_SUM. */
3827 /* An obviously unaligned address. */
3832 /* Vectors to keep interesting information about registers where it can easily
3833 be got. We used to use the actual mode value as the bit number, but there
3834 are more than 32 modes now. Instead we use two tables: one indexed by
3835 hard register number, and one indexed by mode. */
3837 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3838 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3839 mapped into one sparc_mode_class mode. */
3841 enum sparc_mode_class
{
3842 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
3843 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
3847 /* Modes for single-word and smaller quantities. */
3848 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3850 /* Modes for double-word and smaller quantities. */
3851 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3853 /* Modes for quad-word and smaller quantities. */
3854 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3856 /* Modes for 8-word and smaller quantities. */
3857 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3859 /* Modes for single-float quantities. We must allow any single word or
3860 smaller quantity. This is because the fix/float conversion instructions
3861 take integer inputs/outputs from the float registers. */
3862 #define SF_MODES (S_MODES)
3864 /* Modes for double-float and smaller quantities. */
3865 #define DF_MODES (S_MODES | D_MODES)
3867 /* Modes for double-float only quantities. */
3868 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3870 /* Modes for quad-float only quantities. */
3871 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3873 /* Modes for quad-float and smaller quantities. */
3874 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3876 /* Modes for quad-float and double-float quantities. */
3877 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3879 /* Modes for quad-float pair only quantities. */
3880 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3882 /* Modes for quad-float pairs and smaller quantities. */
3883 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3885 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3887 /* Modes for condition codes. */
3888 #define CC_MODES (1 << (int) CC_MODE)
3889 #define CCFP_MODES (1 << (int) CCFP_MODE)
3891 /* Value is 1 if register/mode pair is acceptable on sparc.
3892 The funny mixture of D and T modes is because integer operations
3893 do not specially operate on tetra quantities, so non-quad-aligned
3894 registers can hold quadword quantities (except %o4 and %i4 because
3895 they cross fixed registers). */
3897 /* This points to either the 32 bit or the 64 bit version. */
3898 const int *hard_regno_mode_classes
;
3900 static const int hard_32bit_mode_classes
[] = {
3901 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3902 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3903 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3904 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3906 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3907 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3908 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3909 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3911 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3912 and none can hold SFmode/SImode values. */
3913 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3914 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3915 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3916 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3919 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3925 static const int hard_64bit_mode_classes
[] = {
3926 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3927 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3928 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3929 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3931 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3932 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3933 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3934 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3936 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3937 and none can hold SFmode/SImode values. */
3938 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3939 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3940 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3941 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3944 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3950 int sparc_mode_class
[NUM_MACHINE_MODES
];
3952 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
3955 sparc_init_modes (void)
3959 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
3961 switch (GET_MODE_CLASS (i
))
3964 case MODE_PARTIAL_INT
:
3965 case MODE_COMPLEX_INT
:
3966 if (GET_MODE_SIZE (i
) <= 4)
3967 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
3968 else if (GET_MODE_SIZE (i
) == 8)
3969 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
3970 else if (GET_MODE_SIZE (i
) == 16)
3971 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
3972 else if (GET_MODE_SIZE (i
) == 32)
3973 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
3975 sparc_mode_class
[i
] = 0;
3978 case MODE_COMPLEX_FLOAT
:
3979 if (GET_MODE_SIZE (i
) <= 4)
3980 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
3981 else if (GET_MODE_SIZE (i
) == 8)
3982 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
3983 else if (GET_MODE_SIZE (i
) == 16)
3984 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
3985 else if (GET_MODE_SIZE (i
) == 32)
3986 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
3988 sparc_mode_class
[i
] = 0;
3991 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
3992 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
3994 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
3997 sparc_mode_class
[i
] = 0;
4003 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4005 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4007 /* Initialize the array used by REGNO_REG_CLASS. */
4008 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4010 if (i
< 16 && TARGET_V8PLUS
)
4011 sparc_regno_reg_class
[i
] = I64_REGS
;
4012 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4013 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4015 sparc_regno_reg_class
[i
] = FP_REGS
;
4017 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4019 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4021 sparc_regno_reg_class
[i
] = NO_REGS
;
4025 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
4026 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4027 v9 int regs as it simplifies the code. */
4030 save_regs (FILE *file
, int low
, int high
, const char *base
,
4031 int offset
, int n_regs
, HOST_WIDE_INT real_offset
)
4035 if (TARGET_ARCH64
&& high
<= 32)
4037 for (i
= low
; i
< high
; i
++)
4039 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
4041 fprintf (file
, "\tstx\t%s, [%s+%d]\n",
4042 reg_names
[i
], base
, offset
+ 4 * n_regs
);
4043 if (dwarf2out_do_frame ())
4044 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
4051 for (i
= low
; i
< high
; i
+= 2)
4053 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
4055 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
4057 fprintf (file
, "\tstd\t%s, [%s+%d]\n",
4058 reg_names
[i
], base
, offset
+ 4 * n_regs
);
4059 if (dwarf2out_do_frame ())
4061 char *l
= dwarf2out_cfi_label ();
4062 dwarf2out_reg_save (l
, i
, real_offset
+ 4 * n_regs
);
4063 dwarf2out_reg_save (l
, i
+1, real_offset
+ 4 * n_regs
+ 4);
4069 fprintf (file
, "\tst\t%s, [%s+%d]\n",
4070 reg_names
[i
], base
, offset
+ 4 * n_regs
);
4071 if (dwarf2out_do_frame ())
4072 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
4078 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
4080 fprintf (file
, "\tst\t%s, [%s+%d]\n",
4081 reg_names
[i
+1], base
, offset
+ 4 * n_regs
+ 4);
4082 if (dwarf2out_do_frame ())
4083 dwarf2out_reg_save ("", i
+ 1, real_offset
+ 4 * n_regs
+ 4);
4092 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
4094 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4095 v9 int regs as it simplifies the code. */
4098 restore_regs (FILE *file
, int low
, int high
, const char *base
,
4099 int offset
, int n_regs
)
4103 if (TARGET_ARCH64
&& high
<= 32)
4105 for (i
= low
; i
< high
; i
++)
4107 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
4108 fprintf (file
, "\tldx\t[%s+%d], %s\n",
4109 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
4115 for (i
= low
; i
< high
; i
+= 2)
4117 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
4118 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
4119 fprintf (file
, "\tldd\t[%s+%d], %s\n",
4120 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
4123 fprintf (file
, "\tld\t[%s+%d], %s\n",
4124 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
4126 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
4127 fprintf (file
, "\tld\t[%s+%d], %s\n",
4128 base
, offset
+ 4 * n_regs
+ 4, reg_names
[i
+1]),
4135 /* Compute the frame size required by the function. This function is called
4136 during the reload pass and also by output_function_prologue(). */
4139 compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
4142 int outgoing_args_size
= (current_function_outgoing_args_size
4143 + REG_PARM_STACK_SPACE (current_function_decl
));
4145 /* N_REGS is the number of 4-byte regs saved thus far. This applies
4146 even to v9 int regs to be consistent with save_regs/restore_regs. */
4150 for (i
= 0; i
< 8; i
++)
4151 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
4156 for (i
= 0; i
< 8; i
+= 2)
4157 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
4158 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
4162 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
4163 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
4164 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
4167 /* Set up values for use in `function_epilogue'. */
4168 num_gfregs
= n_regs
;
4170 if (leaf_function
&& n_regs
== 0
4171 && size
== 0 && current_function_outgoing_args_size
== 0)
4173 actual_fsize
= apparent_fsize
= 0;
4177 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4178 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
4179 apparent_fsize
+= n_regs
* 4;
4180 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
4183 /* Make sure nothing can clobber our register windows.
4184 If a SAVE must be done, or there is a stack-local variable,
4185 the register window area must be allocated.
4186 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4187 if (leaf_function
== 0 || size
> 0)
4188 actual_fsize
+= (16 * UNITS_PER_WORD
) + (TARGET_ARCH64
? 0 : 8);
4190 return SPARC_STACK_ALIGN (actual_fsize
);
4193 /* Build big number NUM in register REG and output the result to FILE.
4194 REG is guaranteed to be the only clobbered register. The function
4195 will very likely emit several instructions, so it must not be called
4196 from within a delay slot. */
4199 build_big_number (FILE *file
, HOST_WIDE_INT num
, const char *reg
)
4201 #if HOST_BITS_PER_WIDE_INT == 64
4202 HOST_WIDE_INT high_bits
= (num
>> 32) & 0xffffffff;
4210 /* We don't use the 'set' macro because it appears to be broken
4211 in the Solaris 7 assembler. */
4212 fprintf (file
, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC
"), %s\n",
4214 if ((num
& 0x3ff) != 0)
4215 fprintf (file
, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC
"), %s\n",
4218 #if HOST_BITS_PER_WIDE_INT == 64
4219 else if (high_bits
== 0xffffffff) /* && TARGET_ARCH64 */
4221 else /* num < 0 && TARGET_ARCH64 */
4224 /* Sethi does not sign extend, so we must use a little trickery
4225 to use it for negative numbers. Invert the constant before
4226 loading it in, then use xor immediate to invert the loaded bits
4227 (along with the upper 32 bits) to the desired constant. This
4228 works because the sethi and immediate fields overlap. */
4229 HOST_WIDE_INT inv
= ~num
;
4230 HOST_WIDE_INT low
= -0x400 + (num
& 0x3ff);
4232 fprintf (file
, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC
"), %s\n",
4234 fprintf (file
, "\txor\t%s, "HOST_WIDE_INT_PRINT_DEC
", %s\n",
4237 #if HOST_BITS_PER_WIDE_INT == 64
4238 else /* TARGET_ARCH64 */
4240 /* We don't use the 'setx' macro because if requires a scratch register.
4241 This is the translation of sparc_emit_set_const64_longway into asm.
4242 Hopefully we will soon have prologue/epilogue emitted as RTL. */
4243 HOST_WIDE_INT low1
= (num
>> (32 - 12)) & 0xfff;
4244 HOST_WIDE_INT low2
= (num
>> (32 - 12 - 12)) & 0xfff;
4245 HOST_WIDE_INT low3
= (num
>> (32 - 12 - 12 - 8)) & 0x0ff;
4248 /* We don't use the 'set' macro because it appears to be broken
4249 in the Solaris 7 assembler. */
4250 fprintf (file
, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC
"), %s\n",
4252 if ((high_bits
& 0x3ff) != 0)
4253 fprintf (file
, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC
"), %s\n",
4254 reg
, high_bits
, reg
);
4258 fprintf (file
, "\tsllx\t%s, %d, %s\n", reg
, to_shift
, reg
);
4259 fprintf (file
, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC
", %s\n",
4269 fprintf (file
, "\tsllx\t%s, %d, %s\n", reg
, to_shift
, reg
);
4270 fprintf (file
, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC
", %s\n",
4278 fprintf (file
, "\tsllx\t%s, %d, %s\n", reg
, to_shift
, reg
);
4280 fprintf (file
, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC
", %s\n",
4286 /* Output any necessary .register pseudo-ops. */
4288 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
4290 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4296 /* Check if %g[2367] were used without
4297 .register being printed for them already. */
4298 for (i
= 2; i
< 8; i
++)
4300 if (regs_ever_live
[i
]
4301 && ! sparc_hard_reg_printed
[i
])
4303 sparc_hard_reg_printed
[i
] = 1;
4304 fprintf (file
, "\t.register\t%%g%d, #scratch\n", i
);
4311 /* This function generates the assembly code for function entry.
4312 FILE is a stdio stream to output the code to.
4313 SIZE is an int: how many units of temporary storage to allocate.
4314 Refer to the array `regs_ever_live' to determine which registers
4315 to save; `regs_ever_live[I]' is nonzero if register number I
4316 is ever used in the function. This macro is responsible for
4317 knowing which registers should not be saved even if used. */
4319 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
4320 of memory. If any fpu reg is used in the function, we allocate
4321 such a block here, at the bottom of the frame, just in case it's needed.
4323 If this function is a leaf procedure, then we may choose not
4324 to do a "save" insn. The decision about whether or not
4325 to do this is made in regclass.c. */
4328 sparc_output_function_prologue (FILE *file
, HOST_WIDE_INT size
)
4330 sparc_function_prologue (file
, size
,
4331 current_function_uses_only_leaf_regs
);
4334 /* Output code for the function prologue. */
4337 sparc_function_prologue (FILE *file
, HOST_WIDE_INT size
, int leaf_function
)
4339 sparc_output_scratch_registers (file
);
4341 /* Need to use actual_fsize, since we are also allocating
4342 space for our callee (and our own register save area). */
4343 actual_fsize
= compute_frame_size (size
, leaf_function
);
4347 frame_base_name
= "%sp";
4348 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
4352 frame_base_name
= "%fp";
4353 frame_base_offset
= SPARC_STACK_BIAS
;
4356 /* This is only for the human reader. */
4357 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
4359 if (actual_fsize
== 0)
4361 else if (! leaf_function
)
4363 if (actual_fsize
<= 4096)
4364 fprintf (file
, "\tsave\t%%sp, -"HOST_WIDE_INT_PRINT_DEC
", %%sp\n",
4366 else if (actual_fsize
<= 8192)
4368 fprintf (file
, "\tsave\t%%sp, -4096, %%sp\n");
4369 fprintf (file
, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC
", %%sp\n",
4370 actual_fsize
- 4096);
4374 build_big_number (file
, -actual_fsize
, "%g1");
4375 fprintf (file
, "\tsave\t%%sp, %%g1, %%sp\n");
4378 else /* leaf function */
4380 if (actual_fsize
<= 4096)
4381 fprintf (file
, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC
", %%sp\n",
4383 else if (actual_fsize
<= 8192)
4385 fprintf (file
, "\tadd\t%%sp, -4096, %%sp\n");
4386 fprintf (file
, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC
", %%sp\n",
4387 actual_fsize
- 4096);
4391 build_big_number (file
, -actual_fsize
, "%g1");
4392 fprintf (file
, "\tadd\t%%sp, %%g1, %%sp\n");
4396 if (dwarf2out_do_frame () && actual_fsize
)
4398 char *label
= dwarf2out_cfi_label ();
4400 /* The canonical frame address refers to the top of the frame. */
4401 dwarf2out_def_cfa (label
, (leaf_function
? STACK_POINTER_REGNUM
4402 : HARD_FRAME_POINTER_REGNUM
),
4405 if (! leaf_function
)
4407 /* Note the register window save. This tells the unwinder that
4408 it needs to restore the window registers from the previous
4409 frame's window save area at 0(cfa). */
4410 dwarf2out_window_save (label
);
4412 /* The return address (-8) is now in %i7. */
4413 dwarf2out_return_reg (label
, 31);
4417 /* If doing anything with PIC, do it now. */
4419 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
4421 /* Call saved registers are saved just above the outgoing argument area. */
4424 HOST_WIDE_INT offset
, real_offset
;
4428 real_offset
= -apparent_fsize
;
4429 offset
= -apparent_fsize
+ frame_base_offset
;
4430 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096)
4432 /* ??? This might be optimized a little as %g1 might already have a
4433 value close enough that a single add insn will do. */
4434 /* ??? Although, all of this is probably only a temporary fix
4435 because if %g1 can hold a function result, then
4436 output_function_epilogue will lose (the result will get
4438 build_big_number (file
, offset
, "%g1");
4439 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
4445 base
= frame_base_name
;
4448 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0, real_offset
);
4449 save_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
,
4454 /* Output code to restore any call saved registers. */
4457 output_restore_regs (FILE *file
, int leaf_function ATTRIBUTE_UNUSED
)
4459 HOST_WIDE_INT offset
;
4463 offset
= -apparent_fsize
+ frame_base_offset
;
4464 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096 - 8 /*double*/)
4466 build_big_number (file
, offset
, "%g1");
4467 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
4473 base
= frame_base_name
;
4476 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
4477 restore_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
);
4480 /* This function generates the assembly code for function exit,
4481 on machines that need it.
4483 The function epilogue should not depend on the current stack pointer!
4484 It should use the frame pointer only. This is mandatory because
4485 of alloca; we also take advantage of it to omit stack adjustments
4486 before returning. */
4489 sparc_output_function_epilogue (FILE *file
, HOST_WIDE_INT size
)
4491 sparc_function_epilogue (file
, size
,
4492 current_function_uses_only_leaf_regs
);
4495 /* Output code for the function epilogue. */
4498 sparc_function_epilogue (FILE *file
,
4499 HOST_WIDE_INT size ATTRIBUTE_UNUSED
,
4504 if (current_function_epilogue_delay_list
== 0)
4506 /* If code does not drop into the epilogue, we need
4507 do nothing except output pending case vectors.
4509 We have to still output a dummy nop for the sake of
4510 sane backtraces. Otherwise, if the last two instructions
4511 of a function were call foo; dslot; this can make the return
4512 PC of foo (ie. address of call instruction plus 8) point to
4513 the first instruction in the next function. */
4514 rtx insn
, last_real_insn
;
4516 insn
= get_last_insn ();
4518 last_real_insn
= prev_real_insn (insn
);
4520 && GET_CODE (last_real_insn
) == INSN
4521 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
4522 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
4524 if (last_real_insn
&& GET_CODE (last_real_insn
) == CALL_INSN
)
4525 fputs("\tnop\n", file
);
4527 if (GET_CODE (insn
) == NOTE
)
4528 insn
= prev_nonnote_insn (insn
);
4529 if (insn
&& GET_CODE (insn
) == BARRIER
)
4530 goto output_vectors
;
4534 output_restore_regs (file
, leaf_function
);
4536 /* Work out how to skip the caller's unimp instruction if required. */
4538 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%o7+12" : "retl");
4540 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%i7+12" : "ret");
4542 if (! leaf_function
)
4544 if (current_function_calls_eh_return
)
4546 if (current_function_epilogue_delay_list
)
4548 if (SKIP_CALLERS_UNIMP_P
)
4551 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file
);
4553 /* If we wound up with things in our delay slot, flush them here. */
4554 else if (current_function_epilogue_delay_list
)
4556 rtx delay
= PATTERN (XEXP (current_function_epilogue_delay_list
, 0));
4558 if (TARGET_V9
&& ! epilogue_renumber (&delay
, 1))
4560 epilogue_renumber (&delay
, 0);
4561 fputs (SKIP_CALLERS_UNIMP_P
4562 ? "\treturn\t%i7+12\n"
4563 : "\treturn\t%i7+8\n", file
);
4564 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
4565 file
, 1, 0, 0, NULL
);
4571 if (GET_CODE (delay
) != SET
)
4574 src
= SET_SRC (delay
);
4575 if (GET_CODE (src
) == ASHIFT
)
4577 if (XEXP (src
, 1) != const1_rtx
)
4580 = gen_rtx_PLUS (GET_MODE (src
), XEXP (src
, 0),
4584 insn
= gen_rtx_PARALLEL (VOIDmode
,
4585 gen_rtvec (2, delay
,
4586 gen_rtx_RETURN (VOIDmode
)));
4587 insn
= emit_jump_insn (insn
);
4589 sparc_emitting_epilogue
= true;
4590 final_scan_insn (insn
, file
, 1, 0, 1, NULL
);
4591 sparc_emitting_epilogue
= false;
4594 else if (TARGET_V9
&& ! SKIP_CALLERS_UNIMP_P
)
4595 fputs ("\treturn\t%i7+8\n\tnop\n", file
);
4597 fprintf (file
, "\t%s\n\trestore\n", ret
);
4599 /* All of the following cases are for leaf functions. */
4600 else if (current_function_calls_eh_return
)
4602 else if (current_function_epilogue_delay_list
)
4604 /* eligible_for_epilogue_delay_slot ensures that if this is a
4605 leaf function, then we will only have insn in the delay slot
4606 if the frame size is zero, thus no adjust for the stack is
4608 if (actual_fsize
!= 0)
4610 fprintf (file
, "\t%s\n", ret
);
4611 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
4612 file
, 1, 0, 1, NULL
);
4614 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4615 avoid generating confusing assembly language output. */
4616 else if (actual_fsize
== 0)
4617 fprintf (file
, "\t%s\n\tnop\n", ret
);
4618 else if (actual_fsize
<= 4096)
4619 fprintf (file
, "\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC
", %%sp\n",
4621 else if (actual_fsize
<= 8192)
4622 fprintf (file
, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC
", %%sp\n",
4623 ret
, actual_fsize
- 4096);
4626 build_big_number (file
, actual_fsize
, "%g1");
4627 fprintf (file
, "\t%s\n\tadd\t%%sp, %%g1, %%sp\n", ret
);
4631 sparc_output_deferred_case_vectors ();
4634 /* Output a sibling call. */
4637 output_sibcall (rtx insn
, rtx call_operand
)
4639 int leaf_regs
= current_function_uses_only_leaf_regs
;
4641 int delay_slot
= dbr_sequence_length () > 0;
4645 /* Call to restore global regs might clobber
4646 the delay slot. Instead of checking for this
4647 output the delay slot now. */
4650 rtx delay
= NEXT_INSN (insn
);
4655 final_scan_insn (delay
, asm_out_file
, 1, 0, 1, NULL
);
4656 PATTERN (delay
) = gen_blockage ();
4657 INSN_CODE (delay
) = -1;
4660 output_restore_regs (asm_out_file
, leaf_regs
);
4663 operands
[0] = call_operand
;
4667 #ifdef HAVE_AS_RELAX_OPTION
4668 /* If as and ld are relaxing tail call insns into branch always,
4669 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4670 be optimized. With sethi/jmpl as nor ld has no easy way how to
4671 find out if somebody does not branch between the sethi and jmpl. */
4674 int spare_slot
= ((TARGET_ARCH32
|| TARGET_CM_MEDLOW
) && ! flag_pic
);
4676 HOST_WIDE_INT size
= 0;
4678 if ((actual_fsize
|| ! spare_slot
) && delay_slot
)
4680 rtx delay
= NEXT_INSN (insn
);
4685 final_scan_insn (delay
, asm_out_file
, 1, 0, 1, NULL
);
4686 PATTERN (delay
) = gen_blockage ();
4687 INSN_CODE (delay
) = -1;
4692 if (actual_fsize
<= 4096)
4693 size
= actual_fsize
;
4694 else if (actual_fsize
<= 8192)
4696 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file
);
4697 size
= actual_fsize
- 4096;
4701 build_big_number (asm_out_file
, actual_fsize
, "%g1");
4702 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file
);
4707 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands
);
4708 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands
);
4710 fprintf (asm_out_file
, "\t sub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC
", %%sp\n", size
);
4711 else if (! delay_slot
)
4712 fputs ("\t nop\n", asm_out_file
);
4717 fprintf (asm_out_file
, "\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC
", %%sp\n", size
);
4718 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4719 it into branch if possible. */
4720 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands
);
4721 output_asm_insn ("call\t%a0, 0", operands
);
4722 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands
);
4727 output_asm_insn ("call\t%a0, 0", operands
);
4730 rtx delay
= NEXT_INSN (insn
), pat
;
4735 pat
= PATTERN (delay
);
4736 if (GET_CODE (pat
) != SET
)
4739 operands
[0] = SET_DEST (pat
);
4740 pat
= SET_SRC (pat
);
4741 switch (GET_CODE (pat
))
4744 operands
[1] = XEXP (pat
, 0);
4745 operands
[2] = XEXP (pat
, 1);
4746 output_asm_insn (" restore %r1, %2, %Y0", operands
);
4749 operands
[1] = XEXP (pat
, 0);
4750 operands
[2] = XEXP (pat
, 1);
4751 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
4754 operands
[1] = XEXP (pat
, 0);
4755 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
4759 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
4762 PATTERN (delay
) = gen_blockage ();
4763 INSN_CODE (delay
) = -1;
4766 fputs ("\t restore\n", asm_out_file
);
4770 /* Functions for handling argument passing.
4772 For v8 the first six args are normally in registers and the rest are
4773 pushed. Any arg that starts within the first 6 words is at least
4774 partially passed in a register unless its data type forbids.
4776 For v9, the argument registers are laid out as an array of 16 elements
4777 and arguments are added sequentially. The first 6 int args and up to the
4778 first 16 fp args (depending on size) are passed in regs.
4780 Slot Stack Integral Float Float in structure Double Long Double
4781 ---- ----- -------- ----- ------------------ ------ -----------
4782 15 [SP+248] %f31 %f30,%f31 %d30
4783 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4784 13 [SP+232] %f27 %f26,%f27 %d26
4785 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4786 11 [SP+216] %f23 %f22,%f23 %d22
4787 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4788 9 [SP+200] %f19 %f18,%f19 %d18
4789 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4790 7 [SP+184] %f15 %f14,%f15 %d14
4791 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4792 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4793 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4794 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4795 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4796 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4797 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4799 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4801 Integral arguments are always passed as 64 bit quantities appropriately
4804 Passing of floating point values is handled as follows.
4805 If a prototype is in scope:
4806 If the value is in a named argument (i.e. not a stdarg function or a
4807 value not part of the `...') then the value is passed in the appropriate
4809 If the value is part of the `...' and is passed in one of the first 6
4810 slots then the value is passed in the appropriate int reg.
4811 If the value is part of the `...' and is not passed in one of the first 6
4812 slots then the value is passed in memory.
4813 If a prototype is not in scope:
4814 If the value is one of the first 6 arguments the value is passed in the
4815 appropriate integer reg and the appropriate fp reg.
4816 If the value is not one of the first 6 arguments the value is passed in
4817 the appropriate fp reg and in memory.
4820 /* Maximum number of int regs for args. */
4821 #define SPARC_INT_ARG_MAX 6
4822 /* Maximum number of fp regs for args. */
4823 #define SPARC_FP_ARG_MAX 16
4825 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4827 /* Handle the INIT_CUMULATIVE_ARGS macro.
4828 Initialize a variable CUM of type CUMULATIVE_ARGS
4829 for a call to a function whose data type is FNTYPE.
4830 For a library call, FNTYPE is 0. */
4833 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
4834 rtx libname ATTRIBUTE_UNUSED
,
4835 tree fndecl ATTRIBUTE_UNUSED
)
4838 cum
->prototype_p
= fntype
&& TYPE_ARG_TYPES (fntype
);
4839 cum
->libcall_p
= fntype
== 0;
4842 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
4843 When a prototype says `char' or `short', really pass an `int'. */
4846 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED
)
4848 return TARGET_ARCH32
? true : false;
4851 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
4854 sparc_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
4856 /* For the V9 we want NAMED to mean what it says it means. */
4857 return TARGET_V9
? true : false;
4860 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
4861 Specify whether to return the return value in memory. */
4864 sparc_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
4866 /* SPARC ABI says that quad-precision floats and all structures are
4868 For V9: unions <= 32 bytes in size are returned in int regs,
4869 structures up to 32 bytes are returned in int and fp regs. */
4870 return (TARGET_ARCH32
4871 ? (TYPE_MODE (type
) == BLKmode
4872 || TYPE_MODE (type
) == TFmode
)
4873 : (TYPE_MODE (type
) == BLKmode
4874 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32));
4877 /* Handle the TARGET_STRUCT_VALUE target hook.
4878 Return where to find the structure return value address. */
4881 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED
, int incoming
)
4888 return gen_rtx_MEM (Pmode
, plus_constant (frame_pointer_rtx
,
4889 STRUCT_VALUE_OFFSET
));
4891 return gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
,
4892 STRUCT_VALUE_OFFSET
));
4896 /* Scan the record type TYPE and return the following predicates:
4897 - INTREGS_P: the record contains at least one field or sub-field
4898 that is eligible for promotion in integer registers.
4899 - FP_REGS_P: the record contains at least one field or sub-field
4900 that is eligible for promotion in floating-point registers.
4901 - PACKED_P: the record contains at least one field that is packed.
4903 Sub-fields are not taken into account for the PACKED_P predicate. */
4906 scan_record_type (tree type
, int *intregs_p
, int *fpregs_p
, int *packed_p
)
4910 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4912 if (TREE_CODE (field
) == FIELD_DECL
)
4914 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4915 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
4916 else if (FLOAT_TYPE_P (TREE_TYPE (field
)) && TARGET_FPU
)
4921 if (packed_p
&& DECL_PACKED (field
))
4927 /* Compute the slot number to pass an argument in.
4928 Return the slot number or -1 if passing on the stack.
4930 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4931 the preceding args and about the function being called.
4932 MODE is the argument's machine mode.
4933 TYPE is the data type of the argument (as a tree).
4934 This is null for libcalls where that information may
4936 NAMED is nonzero if this argument is a named parameter
4937 (otherwise it is an extra parameter matching an ellipsis).
4938 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4939 *PREGNO records the register number to use if scalar type.
4940 *PPADDING records the amount of padding needed in words. */
4943 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
4944 tree type
, int named
, int incoming_p
,
4945 int *pregno
, int *ppadding
)
4947 int regbase
= (incoming_p
4948 ? SPARC_INCOMING_INT_ARG_FIRST
4949 : SPARC_OUTGOING_INT_ARG_FIRST
);
4950 int slotno
= cum
->words
;
4955 if (type
!= 0 && TREE_ADDRESSABLE (type
))
4958 && type
!= 0 && mode
== BLKmode
4959 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
4965 /* MODE is VOIDmode when generating the actual call.
4969 case TImode
: case CTImode
:
4970 if (TARGET_ARCH64
&& (slotno
& 1) != 0)
4971 slotno
++, *ppadding
= 1;
4974 case QImode
: case CQImode
:
4975 case HImode
: case CHImode
:
4976 case SImode
: case CSImode
:
4977 case DImode
: case CDImode
:
4978 if (slotno
>= SPARC_INT_ARG_MAX
)
4980 regno
= regbase
+ slotno
;
4983 case TFmode
: case TCmode
:
4984 if (TARGET_ARCH64
&& (slotno
& 1) != 0)
4985 slotno
++, *ppadding
= 1;
4988 case SFmode
: case SCmode
:
4989 case DFmode
: case DCmode
:
4992 if (slotno
>= SPARC_INT_ARG_MAX
)
4994 regno
= regbase
+ slotno
;
4998 if (TARGET_FPU
&& named
)
5000 if (slotno
>= SPARC_FP_ARG_MAX
)
5002 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
5008 if (slotno
>= SPARC_INT_ARG_MAX
)
5010 regno
= regbase
+ slotno
;
5016 /* For sparc64, objects requiring 16 byte alignment get it. */
5019 if (type
&& TYPE_ALIGN (type
) == 128 && (slotno
& 1) != 0)
5020 slotno
++, *ppadding
= 1;
5024 || (type
&& TREE_CODE (type
) == UNION_TYPE
))
5026 if (slotno
>= SPARC_INT_ARG_MAX
)
5028 regno
= regbase
+ slotno
;
5032 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
5034 /* First see what kinds of registers we would need. */
5035 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
5037 /* The ABI obviously doesn't specify how packed structures
5038 are passed. These are defined to be passed in int regs
5039 if possible, otherwise memory. */
5040 if (packed_p
|| !named
)
5041 fpregs_p
= 0, intregs_p
= 1;
5043 /* If all arg slots are filled, then must pass on stack. */
5044 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
5046 /* If there are only int args and all int arg slots are filled,
5047 then must pass on stack. */
5048 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
5050 /* Note that even if all int arg slots are filled, fp members may
5051 still be passed in regs if such regs are available.
5052 *PREGNO isn't set because there may be more than one, it's up
5053 to the caller to compute them. */
5066 /* Handle recursive register counting for structure field layout. */
5068 struct function_arg_record_value_parms
5070 rtx ret
; /* return expression being built. */
5071 int slotno
; /* slot number of the argument. */
5072 int named
; /* whether the argument is named. */
5073 int regbase
; /* regno of the base register. */
5074 int stack
; /* 1 if part of the argument is on the stack. */
5075 int intoffset
; /* offset of the first pending integer field. */
5076 unsigned int nregs
; /* number of words passed in registers. */
5079 static void function_arg_record_value_3
5080 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
5081 static void function_arg_record_value_2
5082 (tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5083 static void function_arg_record_value_1
5084 (tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5085 static rtx
function_arg_record_value (tree
, enum machine_mode
, int, int, int);
5086 static rtx
function_arg_union_value (int, int);
5088 /* A subroutine of function_arg_record_value. Traverse the structure
5089 recursively and determine how many registers will be required. */
5092 function_arg_record_value_1 (tree type
, HOST_WIDE_INT startbitpos
,
5093 struct function_arg_record_value_parms
*parms
,
5098 /* We need to compute how many registers are needed so we can
5099 allocate the PARALLEL but before we can do that we need to know
5100 whether there are any packed fields. The ABI obviously doesn't
5101 specify how structures are passed in this case, so they are
5102 defined to be passed in int regs if possible, otherwise memory,
5103 regardless of whether there are fp values present. */
5106 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5108 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5115 /* Compute how many registers we need. */
5116 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5118 if (TREE_CODE (field
) == FIELD_DECL
)
5120 HOST_WIDE_INT bitpos
= startbitpos
;
5122 if (DECL_SIZE (field
) != 0
5123 && host_integerp (bit_position (field
), 1))
5124 bitpos
+= int_bit_position (field
);
5126 /* ??? FIXME: else assume zero offset. */
5128 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5129 function_arg_record_value_1 (TREE_TYPE (field
),
5133 else if (FLOAT_TYPE_P (TREE_TYPE (field
))
5138 if (parms
->intoffset
!= -1)
5140 unsigned int startbit
, endbit
;
5141 int intslots
, this_slotno
;
5143 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
5144 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5146 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5147 this_slotno
= parms
->slotno
+ parms
->intoffset
5150 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5152 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5153 /* We need to pass this field on the stack. */
5157 parms
->nregs
+= intslots
;
5158 parms
->intoffset
= -1;
5161 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5162 If it wasn't true we wouldn't be here. */
5164 if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5169 if (parms
->intoffset
== -1)
5170 parms
->intoffset
= bitpos
;
5176 /* A subroutine of function_arg_record_value. Assign the bits of the
5177 structure between parms->intoffset and bitpos to integer registers. */
5180 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
5181 struct function_arg_record_value_parms
*parms
)
5183 enum machine_mode mode
;
5185 unsigned int startbit
, endbit
;
5186 int this_slotno
, intslots
, intoffset
;
5189 if (parms
->intoffset
== -1)
5192 intoffset
= parms
->intoffset
;
5193 parms
->intoffset
= -1;
5195 startbit
= intoffset
& -BITS_PER_WORD
;
5196 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5197 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5198 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
5200 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
5204 /* If this is the trailing part of a word, only load that much into
5205 the register. Otherwise load the whole register. Note that in
5206 the latter case we may pick up unwanted bits. It's not a problem
5207 at the moment but may wish to revisit. */
5209 if (intoffset
% BITS_PER_WORD
!= 0)
5210 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5215 intoffset
/= BITS_PER_UNIT
;
5218 regno
= parms
->regbase
+ this_slotno
;
5219 reg
= gen_rtx_REG (mode
, regno
);
5220 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5221 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5224 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5229 while (intslots
> 0);
5232 /* A subroutine of function_arg_record_value. Traverse the structure
5233 recursively and assign bits to floating point registers. Track which
5234 bits in between need integer registers; invoke function_arg_record_value_3
5235 to make that happen. */
5238 function_arg_record_value_2 (tree type
, HOST_WIDE_INT startbitpos
,
5239 struct function_arg_record_value_parms
*parms
,
5245 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5247 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5254 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5256 if (TREE_CODE (field
) == FIELD_DECL
)
5258 HOST_WIDE_INT bitpos
= startbitpos
;
5260 if (DECL_SIZE (field
) != 0
5261 && host_integerp (bit_position (field
), 1))
5262 bitpos
+= int_bit_position (field
);
5264 /* ??? FIXME: else assume zero offset. */
5266 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5267 function_arg_record_value_2 (TREE_TYPE (field
),
5271 else if (FLOAT_TYPE_P (TREE_TYPE (field
))
5276 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
5278 enum machine_mode mode
= DECL_MODE (field
);
5281 function_arg_record_value_3 (bitpos
, parms
);
5282 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2
5283 + ((mode
== SFmode
|| mode
== SCmode
)
5284 && (bitpos
& 32) != 0);
5287 case SCmode
: mode
= SFmode
; break;
5288 case DCmode
: mode
= DFmode
; break;
5289 case TCmode
: mode
= TFmode
; break;
5292 reg
= gen_rtx_REG (mode
, regno
);
5293 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5294 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5295 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5297 if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5299 regno
+= GET_MODE_SIZE (mode
) / 4;
5300 reg
= gen_rtx_REG (mode
, regno
);
5301 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5302 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5303 GEN_INT ((bitpos
+ GET_MODE_BITSIZE (mode
))
5310 if (parms
->intoffset
== -1)
5311 parms
->intoffset
= bitpos
;
5317 /* Used by function_arg and function_value to implement the complex
5318 conventions of the 64-bit ABI for passing and returning structures.
5319 Return an expression valid as a return value for the two macros
5320 FUNCTION_ARG and FUNCTION_VALUE.
5322 TYPE is the data type of the argument (as a tree).
5323 This is null for libcalls where that information may
5325 MODE is the argument's machine mode.
5326 SLOTNO is the index number of the argument's slot in the parameter array.
5327 NAMED is nonzero if this argument is a named parameter
5328 (otherwise it is an extra parameter matching an ellipsis).
5329 REGBASE is the regno of the base register for the parameter array. */
5332 function_arg_record_value (tree type
, enum machine_mode mode
,
5333 int slotno
, int named
, int regbase
)
5335 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
5336 struct function_arg_record_value_parms parms
;
5339 parms
.ret
= NULL_RTX
;
5340 parms
.slotno
= slotno
;
5341 parms
.named
= named
;
5342 parms
.regbase
= regbase
;
5345 /* Compute how many registers we need. */
5347 parms
.intoffset
= 0;
5348 function_arg_record_value_1 (type
, 0, &parms
, false);
5350 /* Take into account pending integer fields. */
5351 if (parms
.intoffset
!= -1)
5353 unsigned int startbit
, endbit
;
5354 int intslots
, this_slotno
;
5356 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
5357 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5358 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5359 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
5361 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5363 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5364 /* We need to pass this field on the stack. */
5368 parms
.nregs
+= intslots
;
5370 nregs
= parms
.nregs
;
5372 /* Allocate the vector and handle some annoying special cases. */
5375 /* ??? Empty structure has no value? Duh? */
5378 /* Though there's nothing really to store, return a word register
5379 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5380 leads to breakage due to the fact that there are zero bytes to
5382 return gen_rtx_REG (mode
, regbase
);
5386 /* ??? C++ has structures with no fields, and yet a size. Give up
5387 for now and pass everything back in integer registers. */
5388 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5390 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
5391 nregs
= SPARC_INT_ARG_MAX
- slotno
;
5396 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
5398 /* If at least one field must be passed on the stack, generate
5399 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5400 also be passed on the stack. We can't do much better because the
5401 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5402 of structures for which the fields passed exclusively in registers
5403 are not at the beginning of the structure. */
5405 XVECEXP (parms
.ret
, 0, 0)
5406 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5408 /* Fill in the entries. */
5410 parms
.intoffset
= 0;
5411 function_arg_record_value_2 (type
, 0, &parms
, false);
5412 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
5414 if (parms
.nregs
!= nregs
)
5420 /* Used by function_arg and function_value to implement the conventions
5421 of the 64-bit ABI for passing and returning unions.
5422 Return an expression valid as a return value for the two macros
5423 FUNCTION_ARG and FUNCTION_VALUE.
5425 SIZE is the size in bytes of the union.
5426 REGNO is the hard register the union will be passed in. */
5429 function_arg_union_value (int size
, int regno
)
5431 enum machine_mode mode
;
5434 if (size
<= UNITS_PER_WORD
)
5437 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5439 reg
= gen_rtx_REG (mode
, regno
);
5441 /* Unions are passed left-justified. */
5442 return gen_rtx_PARALLEL (mode
,
5443 gen_rtvec (1, gen_rtx_EXPR_LIST (VOIDmode
,
5448 /* Handle the FUNCTION_ARG macro.
5449 Determine where to put an argument to a function.
5450 Value is zero to push the argument on the stack,
5451 or a hard register in which to store the argument.
5453 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5454 the preceding args and about the function being called.
5455 MODE is the argument's machine mode.
5456 TYPE is the data type of the argument (as a tree).
5457 This is null for libcalls where that information may
5459 NAMED is nonzero if this argument is a named parameter
5460 (otherwise it is an extra parameter matching an ellipsis).
5461 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5464 function_arg (const struct sparc_args
*cum
, enum machine_mode mode
,
5465 tree type
, int named
, int incoming_p
)
5467 int regbase
= (incoming_p
5468 ? SPARC_INCOMING_INT_ARG_FIRST
5469 : SPARC_OUTGOING_INT_ARG_FIRST
);
5470 int slotno
, regno
, padding
;
5473 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
5481 reg
= gen_rtx_REG (mode
, regno
);
5485 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
5487 /* Structures up to 16 bytes in size are passed in arg slots on the
5488 stack and are promoted to registers where possible. */
5490 if (int_size_in_bytes (type
) > 16)
5491 abort (); /* shouldn't get here */
5493 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
5495 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
5497 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5500 abort (); /* shouldn't get here */
5502 return function_arg_union_value (size
, regno
);
5504 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5505 but also have the slot allocated for them.
5506 If no prototype is in scope fp values in register slots get passed
5507 in two places, either fp regs and int regs or fp regs and memory. */
5508 else if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5509 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5510 && SPARC_FP_REG_P (regno
))
5512 reg
= gen_rtx_REG (mode
, regno
);
5513 if (cum
->prototype_p
|| cum
->libcall_p
)
5515 /* "* 2" because fp reg numbers are recorded in 4 byte
5518 /* ??? This will cause the value to be passed in the fp reg and
5519 in the stack. When a prototype exists we want to pass the
5520 value in the reg but reserve space on the stack. That's an
5521 optimization, and is deferred [for a bit]. */
5522 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
5523 return gen_rtx_PARALLEL (mode
,
5525 gen_rtx_EXPR_LIST (VOIDmode
,
5526 NULL_RTX
, const0_rtx
),
5527 gen_rtx_EXPR_LIST (VOIDmode
,
5531 /* ??? It seems that passing back a register even when past
5532 the area declared by REG_PARM_STACK_SPACE will allocate
5533 space appropriately, and will not copy the data onto the
5534 stack, exactly as we desire.
5536 This is due to locate_and_pad_parm being called in
5537 expand_call whenever reg_parm_stack_space > 0, which
5538 while beneficial to our example here, would seem to be
5539 in error from what had been intended. Ho hum... -- r~ */
5547 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
5551 /* On incoming, we don't need to know that the value
5552 is passed in %f0 and %i0, and it confuses other parts
5553 causing needless spillage even on the simplest cases. */
5557 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
5558 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
5560 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
5561 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
5563 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
5567 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5568 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
5569 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
5575 /* Scalar or complex int. */
5576 reg
= gen_rtx_REG (mode
, regno
);
5582 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5583 For an arg passed partly in registers and partly in memory,
5584 this is the number of registers used.
5585 For args passed entirely in registers or entirely in memory, zero.
5587 Any arg that starts in the first 6 regs but won't entirely fit in them
5588 needs partial registers on v8. On v9, structures with integer
5589 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5590 values that begin in the last fp reg [where "last fp reg" varies with the
5591 mode] will be split between that reg and memory. */
5594 function_arg_partial_nregs (const struct sparc_args
*cum
,
5595 enum machine_mode mode
, tree type
, int named
)
5597 int slotno
, regno
, padding
;
5599 /* We pass 0 for incoming_p here, it doesn't matter. */
5600 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5607 if ((slotno
+ (mode
== BLKmode
5608 ? ROUND_ADVANCE (int_size_in_bytes (type
))
5609 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
5610 > NPARM_REGS (SImode
))
5611 return NPARM_REGS (SImode
) - slotno
;
5616 if (type
&& AGGREGATE_TYPE_P (type
))
5618 int size
= int_size_in_bytes (type
);
5619 int align
= TYPE_ALIGN (type
);
5622 slotno
+= slotno
& 1;
5623 if (size
> 8 && size
<= 16
5624 && slotno
== SPARC_INT_ARG_MAX
- 1)
5627 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
5628 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5629 && ! (TARGET_FPU
&& named
)))
5631 /* The complex types are passed as packed types. */
5632 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
5635 if (GET_MODE_ALIGNMENT (mode
) == 128)
5637 slotno
+= slotno
& 1;
5639 /* ??? The mode needs 3 slots? */
5640 if (slotno
== SPARC_INT_ARG_MAX
- 2)
5645 if (slotno
== SPARC_INT_ARG_MAX
- 1)
5649 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5651 if (GET_MODE_ALIGNMENT (mode
) == 128)
5652 slotno
+= slotno
& 1;
5653 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
5661 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5662 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5663 quad-precision floats by invisible reference.
5664 v9: Aggregates greater than 16 bytes are passed by reference.
5665 For Pascal, also pass arrays by reference. */
5668 function_arg_pass_by_reference (const struct sparc_args
*cum ATTRIBUTE_UNUSED
,
5669 enum machine_mode mode
, tree type
,
5670 int named ATTRIBUTE_UNUSED
)
5674 return ((type
&& AGGREGATE_TYPE_P (type
))
5676 || GET_MODE_SIZE (mode
) > 8);
5680 return ((type
&& TREE_CODE (type
) == ARRAY_TYPE
)
5681 /* Consider complex values as aggregates, so care
5682 for CTImode and TCmode. */
5683 || GET_MODE_SIZE (mode
) > 16
5685 && AGGREGATE_TYPE_P (type
)
5686 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16));
5690 /* Handle the FUNCTION_ARG_ADVANCE macro.
5691 Update the data in CUM to advance over an argument
5692 of mode MODE and data type TYPE.
5693 TYPE is null for libcalls where that information may not be available. */
5696 function_arg_advance (struct sparc_args
*cum
, enum machine_mode mode
,
5697 tree type
, int named
)
5699 int slotno
, regno
, padding
;
5701 /* We pass 0 for incoming_p here, it doesn't matter. */
5702 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5704 /* If register required leading padding, add it. */
5706 cum
->words
+= padding
;
5710 cum
->words
+= (mode
!= BLKmode
5711 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5712 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5716 if (type
&& AGGREGATE_TYPE_P (type
))
5718 int size
= int_size_in_bytes (type
);
5722 else if (size
<= 16)
5724 else /* passed by reference */
5729 cum
->words
+= (mode
!= BLKmode
5730 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5731 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5736 /* Handle the FUNCTION_ARG_PADDING macro.
5737 For the 64 bit ABI structs are always stored left shifted in their
5741 function_arg_padding (enum machine_mode mode
, tree type
)
5743 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
5746 /* Fall back to the default. */
5747 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
5750 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5751 For v9, function return values are subject to the same rules as arguments,
5752 except that up to 32-bytes may be returned in registers. */
5755 function_value (tree type
, enum machine_mode mode
, int incoming_p
)
5759 if (TARGET_ARCH64
&& type
)
5761 int regbase
= (incoming_p
5762 ? SPARC_OUTGOING_INT_ARG_FIRST
5763 : SPARC_INCOMING_INT_ARG_FIRST
);
5765 if (TREE_CODE (type
) == RECORD_TYPE
)
5767 /* Structures up to 32 bytes in size are passed in registers,
5768 promoted to fp registers where possible. */
5770 if (int_size_in_bytes (type
) > 32)
5771 abort (); /* shouldn't get here */
5773 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
5775 else if (TREE_CODE (type
) == UNION_TYPE
)
5777 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5780 abort (); /* shouldn't get here */
5782 return function_arg_union_value (size
, regbase
);
5784 else if (AGGREGATE_TYPE_P (type
))
5786 /* All other aggregate types are passed in an integer register
5787 in a mode corresponding to the size of the type. */
5788 HOST_WIDE_INT bytes
= int_size_in_bytes (type
);
5793 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
5795 else if (GET_MODE_CLASS (mode
) == MODE_INT
5796 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5801 regno
= BASE_RETURN_VALUE_REG (mode
);
5803 regno
= BASE_OUTGOING_VALUE_REG (mode
);
5805 return gen_rtx_REG (mode
, regno
);
5808 /* Do what is necessary for `va_start'. We look at the current function
5809 to determine if stdarg or varargs is used and return the address of
5810 the first unnamed parameter. */
5813 sparc_builtin_saveregs (void)
5815 int first_reg
= current_function_args_info
.words
;
5819 for (regno
= first_reg
; regno
< NPARM_REGS (word_mode
); regno
++)
5820 emit_move_insn (gen_rtx_MEM (word_mode
,
5821 gen_rtx_PLUS (Pmode
,
5823 GEN_INT (FIRST_PARM_OFFSET (0)
5826 gen_rtx_REG (word_mode
,
5827 BASE_INCOMING_ARG_REG (word_mode
) + regno
));
5829 address
= gen_rtx_PLUS (Pmode
,
5831 GEN_INT (FIRST_PARM_OFFSET (0)
5832 + UNITS_PER_WORD
* first_reg
));
5837 /* Implement `va_start' for varargs and stdarg. */
5840 sparc_va_start (tree valist
, rtx nextarg
)
5842 nextarg
= expand_builtin_saveregs ();
5843 std_expand_builtin_va_start (valist
, nextarg
);
5846 /* Implement `va_arg'. */
5849 sparc_va_arg (tree valist
, tree type
)
5851 HOST_WIDE_INT size
, rsize
, align
;
5856 /* Round up sizeof(type) to a word. */
5857 size
= int_size_in_bytes (type
);
5858 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5863 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
5864 align
= 2 * UNITS_PER_WORD
;
5866 /* Consider complex values as aggregates, so care
5867 for CTImode and TCmode. */
5868 if ((unsigned HOST_WIDE_INT
) size
> 16)
5871 size
= rsize
= UNITS_PER_WORD
;
5874 else if (AGGREGATE_TYPE_P (type
))
5876 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5877 are given whole slots as needed. */
5879 size
= rsize
= UNITS_PER_WORD
;
5886 if (AGGREGATE_TYPE_P (type
)
5887 || TYPE_MODE (type
) == SCmode
5888 || GET_MODE_SIZE (TYPE_MODE (type
)) > 8)
5891 size
= rsize
= UNITS_PER_WORD
;
5898 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5899 build_int_2 (align
- 1, 0)));
5900 incr
= fold (build (BIT_AND_EXPR
, ptr_type_node
, incr
,
5901 build_int_2 (-align
, -1)));
5904 addr
= incr
= save_expr (incr
);
5905 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
5907 addr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5908 build_int_2 (rsize
- size
, 0)));
5910 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5911 build_int_2 (rsize
, 0)));
5913 incr
= build (MODIFY_EXPR
, ptr_type_node
, valist
, incr
);
5914 TREE_SIDE_EFFECTS (incr
) = 1;
5915 expand_expr (incr
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5917 addr_rtx
= expand_expr (addr
, NULL
, Pmode
, EXPAND_NORMAL
);
5919 /* If the address isn't aligned properly for the type,
5920 we may need to copy to a temporary.
5921 FIXME: This is inefficient. Usually we can do this
5924 && TYPE_ALIGN (type
) > BITS_PER_WORD
5927 /* FIXME: We really need to specify that the temporary is live
5928 for the whole function because expand_builtin_va_arg wants
5929 the alias set to be get_varargs_alias_set (), but in this
5930 case the alias set is that for TYPE and if the memory gets
5931 reused it will be reused with alias set TYPE. */
5932 rtx tmp
= assign_temp (type
, 0, 1, 0);
5935 addr_rtx
= force_reg (Pmode
, addr_rtx
);
5936 addr_rtx
= gen_rtx_MEM (BLKmode
, addr_rtx
);
5937 set_mem_alias_set (addr_rtx
, get_varargs_alias_set ());
5938 set_mem_align (addr_rtx
, BITS_PER_WORD
);
5939 tmp
= shallow_copy_rtx (tmp
);
5940 PUT_MODE (tmp
, BLKmode
);
5941 set_mem_alias_set (tmp
, 0);
5943 dest_addr
= emit_block_move (tmp
, addr_rtx
, GEN_INT (rsize
),
5945 if (dest_addr
!= NULL_RTX
)
5946 addr_rtx
= dest_addr
;
5948 addr_rtx
= XCEXP (tmp
, 0, MEM
);
5953 addr_rtx
= force_reg (Pmode
, addr_rtx
);
5954 addr_rtx
= gen_rtx_MEM (Pmode
, addr_rtx
);
5955 set_mem_alias_set (addr_rtx
, get_varargs_alias_set ());
5961 /* Return the string to output a conditional branch to LABEL, which is
5962 the operand number of the label. OP is the conditional expression.
5963 XEXP (OP, 0) is assumed to be a condition code register (integer or
5964 floating point) and its mode specifies what kind of comparison we made.
5966 REVERSED is nonzero if we should reverse the sense of the comparison.
5968 ANNUL is nonzero if we should generate an annulling branch.
5970 NOOP is nonzero if we have to follow this branch by a noop.
5972 INSN, if set, is the insn. */
5975 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
5978 static char string
[50];
5979 enum rtx_code code
= GET_CODE (op
);
5980 rtx cc_reg
= XEXP (op
, 0);
5981 enum machine_mode mode
= GET_MODE (cc_reg
);
5982 const char *labelno
, *branch
;
5983 int spaces
= 8, far
;
5986 /* v9 branches are limited to +-1MB. If it is too far away,
5999 fbne,a,pn %fcc2, .LC29
6007 far
= get_attr_length (insn
) >= 3;
6010 /* Reversal of FP compares takes care -- an ordered compare
6011 becomes an unordered compare and vice versa. */
6012 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6013 code
= reverse_condition_maybe_unordered (code
);
6015 code
= reverse_condition (code
);
6018 /* Start by writing the branch condition. */
6019 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6070 /* ??? !v9: FP branches cannot be preceded by another floating point
6071 insn. Because there is currently no concept of pre-delay slots,
6072 we can fix this only by always emitting a nop before a floating
6077 strcpy (string
, "nop\n\t");
6078 strcat (string
, branch
);
6091 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
6103 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
6124 strcpy (string
, branch
);
6126 spaces
-= strlen (branch
);
6127 p
= strchr (string
, '\0');
6129 /* Now add the annulling, the label, and a possible noop. */
6144 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
6146 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6147 - INSN_ADDRESSES (INSN_UID (insn
)));
6148 /* Leave some instructions for "slop". */
6149 if (delta
< -260000 || delta
>= 260000)
6153 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6155 static char v9_fcc_labelno
[] = "%%fccX, ";
6156 /* Set the char indicating the number of the fcc reg to use. */
6157 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
6158 labelno
= v9_fcc_labelno
;
6161 if (REGNO (cc_reg
) == SPARC_FCC_REG
)
6167 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
6169 labelno
= "%%xcc, ";
6175 labelno
= "%%icc, ";
6180 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
6183 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
6193 strcpy (p
, labelno
);
6194 p
= strchr (p
, '\0');
6197 strcpy (p
, ".+12\n\tnop\n\tb\t");
6204 /* Set the char indicating the number of the operand containing the
6209 strcpy (p
, "\n\tnop");
6214 /* Emit a library call comparison between floating point X and Y.
6215 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6216 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6217 values as arguments instead of the TFmode registers themselves,
6218 that's why we cannot call emit_float_lib_cmp. */
6220 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
6223 rtx slot0
, slot1
, result
, tem
, tem2
;
6224 enum machine_mode mode
;
6229 qpfunc
= (TARGET_ARCH64
) ? "_Qp_feq" : "_Q_feq";
6233 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fne" : "_Q_fne";
6237 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fgt" : "_Q_fgt";
6241 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fge" : "_Q_fge";
6245 qpfunc
= (TARGET_ARCH64
) ? "_Qp_flt" : "_Q_flt";
6249 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fle" : "_Q_fle";
6260 qpfunc
= (TARGET_ARCH64
) ? "_Qp_cmp" : "_Q_cmp";
6270 if (GET_CODE (x
) != MEM
)
6272 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
6273 emit_insn (gen_rtx_SET (VOIDmode
, slot0
, x
));
6278 if (GET_CODE (y
) != MEM
)
6280 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
6281 emit_insn (gen_rtx_SET (VOIDmode
, slot1
, y
));
6286 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
6288 XEXP (slot0
, 0), Pmode
,
6289 XEXP (slot1
, 0), Pmode
);
6295 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
6297 x
, TFmode
, y
, TFmode
);
6303 /* Immediately move the result of the libcall into a pseudo
6304 register so reload doesn't clobber the value if it needs
6305 the return register for a spill reg. */
6306 result
= gen_reg_rtx (mode
);
6307 emit_move_insn (result
, hard_libcall_value (mode
));
6312 emit_cmp_insn (result
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
6316 emit_cmp_insn (result
, GEN_INT(3), comparison
== UNORDERED
? EQ
: NE
,
6321 emit_cmp_insn (result
, const1_rtx
,
6322 comparison
== UNGT
? GT
: NE
, NULL_RTX
, mode
, 0);
6325 emit_cmp_insn (result
, const2_rtx
, NE
, NULL_RTX
, mode
, 0);
6328 tem
= gen_reg_rtx (mode
);
6330 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
6332 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
6333 emit_cmp_insn (tem
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
6337 tem
= gen_reg_rtx (mode
);
6339 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
6341 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
6342 tem2
= gen_reg_rtx (mode
);
6344 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
6346 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
6347 emit_cmp_insn (tem2
, const0_rtx
, comparison
== UNEQ
? EQ
: NE
,
6353 /* Generate an unsigned DImode to FP conversion. This is the same code
6354 optabs would emit if we didn't have TFmode patterns. */
6357 sparc_emit_floatunsdi (rtx
*operands
)
6359 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
6360 enum machine_mode mode
;
6363 in
= force_reg (DImode
, operands
[1]);
6364 mode
= GET_MODE (out
);
6365 neglab
= gen_label_rtx ();
6366 donelab
= gen_label_rtx ();
6367 i0
= gen_reg_rtx (DImode
);
6368 i1
= gen_reg_rtx (DImode
);
6369 f0
= gen_reg_rtx (mode
);
6371 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
6373 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
6374 emit_jump_insn (gen_jump (donelab
));
6377 emit_label (neglab
);
6379 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
6380 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
6381 emit_insn (gen_iordi3 (i0
, i0
, i1
));
6382 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
6383 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
6385 emit_label (donelab
);
6388 /* Return the string to output a conditional branch to LABEL, testing
6389 register REG. LABEL is the operand number of the label; REG is the
6390 operand number of the reg. OP is the conditional expression. The mode
6391 of REG says what kind of comparison we made.
6393 REVERSED is nonzero if we should reverse the sense of the comparison.
6395 ANNUL is nonzero if we should generate an annulling branch.
6397 NOOP is nonzero if we have to follow this branch by a noop. */
6400 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
6401 int annul
, int noop
, rtx insn
)
6403 static char string
[50];
6404 enum rtx_code code
= GET_CODE (op
);
6405 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
6410 /* branch on register are limited to +-128KB. If it is too far away,
6423 brgez,a,pn %o1, .LC29
6429 ba,pt %xcc, .LC29 */
6431 far
= get_attr_length (insn
) >= 3;
6433 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6435 code
= reverse_condition (code
);
6437 /* Only 64 bit versions of these instructions exist. */
6441 /* Start by writing the branch condition. */
6446 strcpy (string
, "brnz");
6450 strcpy (string
, "brz");
6454 strcpy (string
, "brgez");
6458 strcpy (string
, "brlz");
6462 strcpy (string
, "brlez");
6466 strcpy (string
, "brgz");
6473 p
= strchr (string
, '\0');
6475 /* Now add the annulling, reg, label, and nop. */
6482 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
6485 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
6490 *p
= p
< string
+ 8 ? '\t' : ' ';
6498 int veryfar
= 1, delta
;
6500 if (INSN_ADDRESSES_SET_P ())
6502 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6503 - INSN_ADDRESSES (INSN_UID (insn
)));
6504 /* Leave some instructions for "slop". */
6505 if (delta
>= -260000 && delta
< 260000)
6509 strcpy (p
, ".+12\n\tnop\n\t");
6520 strcpy (p
, "ba,pt\t%%xcc, ");
6530 strcpy (p
, "\n\tnop");
6535 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6536 Such instructions cannot be used in the delay slot of return insn on v9.
6537 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6541 epilogue_renumber (register rtx
*where
, int test
)
6543 register const char *fmt
;
6545 register enum rtx_code code
;
6550 code
= GET_CODE (*where
);
6555 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
6557 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
6558 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
6566 /* Do not replace the frame pointer with the stack pointer because
6567 it can cause the delayed instruction to load below the stack.
6568 This occurs when instructions like:
6570 (set (reg/i:SI 24 %i0)
6571 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6572 (const_int -20 [0xffffffec])) 0))
6574 are in the return delayed slot. */
6576 if (GET_CODE (XEXP (*where
, 0)) == REG
6577 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
6578 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
6579 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
6584 if (SPARC_STACK_BIAS
6585 && GET_CODE (XEXP (*where
, 0)) == REG
6586 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
6594 fmt
= GET_RTX_FORMAT (code
);
6596 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6601 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
6602 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
6605 else if (fmt
[i
] == 'e'
6606 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
6612 /* Leaf functions and non-leaf functions have different needs. */
6615 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
6618 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
6620 static const int *const reg_alloc_orders
[] = {
6621 reg_leaf_alloc_order
,
6622 reg_nonleaf_alloc_order
};
6625 order_regs_for_local_alloc (void)
6627 static int last_order_nonleaf
= 1;
6629 if (regs_ever_live
[15] != last_order_nonleaf
)
6631 last_order_nonleaf
= !last_order_nonleaf
;
6632 memcpy ((char *) reg_alloc_order
,
6633 (const char *) reg_alloc_orders
[last_order_nonleaf
],
6634 FIRST_PSEUDO_REGISTER
* sizeof (int));
6638 /* Return 1 if REG and MEM are legitimate enough to allow the various
6639 mem<-->reg splits to be run. */
6642 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
6644 /* Punt if we are here by mistake. */
6645 if (! reload_completed
)
6648 /* We must have an offsettable memory reference. */
6649 if (! offsettable_memref_p (mem
))
6652 /* If we have legitimate args for ldd/std, we do not want
6653 the split to happen. */
6654 if ((REGNO (reg
) % 2) == 0
6655 && mem_min_alignment (mem
, 8))
6662 /* Return 1 if x and y are some kind of REG and they refer to
6663 different hard registers. This test is guaranteed to be
6664 run after reload. */
6667 sparc_absnegfloat_split_legitimate (rtx x
, rtx y
)
6669 if (GET_CODE (x
) != REG
)
6671 if (GET_CODE (y
) != REG
)
6673 if (REGNO (x
) == REGNO (y
))
6678 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6679 This makes them candidates for using ldd and std insns.
6681 Note reg1 and reg2 *must* be hard registers. */
6684 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
6686 /* We might have been passed a SUBREG. */
6687 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
6690 if (REGNO (reg1
) % 2 != 0)
6693 /* Integer ldd is deprecated in SPARC V9 */
6694 if (TARGET_V9
&& REGNO (reg1
) < 32)
6697 return (REGNO (reg1
) == REGNO (reg2
) - 1);
6700 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6703 This can only happen when addr1 and addr2, the addresses in mem1
6704 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6705 addr1 must also be aligned on a 64-bit boundary.
6707 Also iff dependent_reg_rtx is not null it should not be used to
6708 compute the address for mem1, i.e. we cannot optimize a sequence
6720 But, note that the transformation from:
6725 is perfectly fine. Thus, the peephole2 patterns always pass us
6726 the destination register of the first load, never the second one.
6728 For stores we don't have a similar problem, so dependent_reg_rtx is
6732 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
6736 HOST_WIDE_INT offset1
;
6738 /* The mems cannot be volatile. */
6739 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
6742 /* MEM1 should be aligned on a 64-bit boundary. */
6743 if (MEM_ALIGN (mem1
) < 64)
6746 addr1
= XEXP (mem1
, 0);
6747 addr2
= XEXP (mem2
, 0);
6749 /* Extract a register number and offset (if used) from the first addr. */
6750 if (GET_CODE (addr1
) == PLUS
)
6752 /* If not a REG, return zero. */
6753 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
6757 reg1
= REGNO (XEXP (addr1
, 0));
6758 /* The offset must be constant! */
6759 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
6761 offset1
= INTVAL (XEXP (addr1
, 1));
6764 else if (GET_CODE (addr1
) != REG
)
6768 reg1
= REGNO (addr1
);
6769 /* This was a simple (mem (reg)) expression. Offset is 0. */
6773 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6774 if (GET_CODE (addr2
) != PLUS
)
6777 if (GET_CODE (XEXP (addr2
, 0)) != REG
6778 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
6781 if (reg1
!= REGNO (XEXP (addr2
, 0)))
6784 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
6787 /* The first offset must be evenly divisible by 8 to ensure the
6788 address is 64 bit aligned. */
6789 if (offset1
% 8 != 0)
6792 /* The offset for the second addr must be 4 more than the first addr. */
6793 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
6796 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6801 /* Return 1 if reg is a pseudo, or is the first register in
6802 a hard register pair. This makes it a candidate for use in
6803 ldd and std insns. */
6806 register_ok_for_ldd (rtx reg
)
6808 /* We might have been passed a SUBREG. */
6809 if (GET_CODE (reg
) != REG
)
6812 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
6813 return (REGNO (reg
) % 2 == 0);
6818 /* Print operand X (an rtx) in assembler syntax to file FILE.
6819 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6820 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6823 print_operand (FILE *file
, rtx x
, int code
)
6828 /* Output a 'nop' if there's nothing for the delay slot. */
6829 if (dbr_sequence_length () == 0)
6830 fputs ("\n\t nop", file
);
6833 /* Output an annul flag if there's nothing for the delay slot and we
6834 are optimizing. This is always used with '(' below. */
6835 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6836 this is a dbx bug. So, we only do this when optimizing. */
6837 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6838 Always emit a nop in case the next instruction is a branch. */
6839 if (dbr_sequence_length () == 0
6840 && (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6844 /* Output a 'nop' if there's nothing for the delay slot and we are
6845 not optimizing. This is always used with '*' above. */
6846 if (dbr_sequence_length () == 0
6847 && ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6848 fputs ("\n\t nop", file
);
6851 /* Output the Embedded Medium/Anywhere code model base register. */
6852 fputs (EMBMEDANY_BASE_REG
, file
);
6855 /* Print out what we are using as the frame pointer. This might
6856 be %fp, or might be %sp+offset. */
6857 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6858 fprintf (file
, "%s+"HOST_WIDE_INT_PRINT_DEC
, frame_base_name
, frame_base_offset
);
6861 /* Print some local dynamic TLS name. */
6862 assemble_name (file
, get_some_local_dynamic_name ());
6865 /* Adjust the operand to take into account a RESTORE operation. */
6866 if (GET_CODE (x
) == CONST_INT
)
6868 else if (GET_CODE (x
) != REG
)
6869 output_operand_lossage ("invalid %%Y operand");
6870 else if (REGNO (x
) < 8)
6871 fputs (reg_names
[REGNO (x
)], file
);
6872 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
6873 fputs (reg_names
[REGNO (x
)-16], file
);
6875 output_operand_lossage ("invalid %%Y operand");
6878 /* Print out the low order register name of a register pair. */
6879 if (WORDS_BIG_ENDIAN
)
6880 fputs (reg_names
[REGNO (x
)+1], file
);
6882 fputs (reg_names
[REGNO (x
)], file
);
6885 /* Print out the high order register name of a register pair. */
6886 if (WORDS_BIG_ENDIAN
)
6887 fputs (reg_names
[REGNO (x
)], file
);
6889 fputs (reg_names
[REGNO (x
)+1], file
);
6892 /* Print out the second register name of a register pair or quad.
6893 I.e., R (%o0) => %o1. */
6894 fputs (reg_names
[REGNO (x
)+1], file
);
6897 /* Print out the third register name of a register quad.
6898 I.e., S (%o0) => %o2. */
6899 fputs (reg_names
[REGNO (x
)+2], file
);
6902 /* Print out the fourth register name of a register quad.
6903 I.e., T (%o0) => %o3. */
6904 fputs (reg_names
[REGNO (x
)+3], file
);
6907 /* Print a condition code register. */
6908 if (REGNO (x
) == SPARC_ICC_REG
)
6910 /* We don't handle CC[X]_NOOVmode because they're not supposed
6912 if (GET_MODE (x
) == CCmode
)
6913 fputs ("%icc", file
);
6914 else if (GET_MODE (x
) == CCXmode
)
6915 fputs ("%xcc", file
);
6920 /* %fccN register */
6921 fputs (reg_names
[REGNO (x
)], file
);
6924 /* Print the operand's address only. */
6925 output_address (XEXP (x
, 0));
6928 /* In this case we need a register. Use %g0 if the
6929 operand is const0_rtx. */
6931 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
6933 fputs ("%g0", file
);
6940 switch (GET_CODE (x
))
6942 case IOR
: fputs ("or", file
); break;
6943 case AND
: fputs ("and", file
); break;
6944 case XOR
: fputs ("xor", file
); break;
6945 default: output_operand_lossage ("invalid %%A operand");
6950 switch (GET_CODE (x
))
6952 case IOR
: fputs ("orn", file
); break;
6953 case AND
: fputs ("andn", file
); break;
6954 case XOR
: fputs ("xnor", file
); break;
6955 default: output_operand_lossage ("invalid %%B operand");
6959 /* These are used by the conditional move instructions. */
6963 enum rtx_code rc
= GET_CODE (x
);
6967 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
6968 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6969 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
6971 rc
= reverse_condition (GET_CODE (x
));
6975 case NE
: fputs ("ne", file
); break;
6976 case EQ
: fputs ("e", file
); break;
6977 case GE
: fputs ("ge", file
); break;
6978 case GT
: fputs ("g", file
); break;
6979 case LE
: fputs ("le", file
); break;
6980 case LT
: fputs ("l", file
); break;
6981 case GEU
: fputs ("geu", file
); break;
6982 case GTU
: fputs ("gu", file
); break;
6983 case LEU
: fputs ("leu", file
); break;
6984 case LTU
: fputs ("lu", file
); break;
6985 case LTGT
: fputs ("lg", file
); break;
6986 case UNORDERED
: fputs ("u", file
); break;
6987 case ORDERED
: fputs ("o", file
); break;
6988 case UNLT
: fputs ("ul", file
); break;
6989 case UNLE
: fputs ("ule", file
); break;
6990 case UNGT
: fputs ("ug", file
); break;
6991 case UNGE
: fputs ("uge", file
); break;
6992 case UNEQ
: fputs ("ue", file
); break;
6993 default: output_operand_lossage (code
== 'c'
6994 ? "invalid %%c operand"
6995 : "invalid %%C operand");
7000 /* These are used by the movr instruction pattern. */
7004 enum rtx_code rc
= (code
== 'd'
7005 ? reverse_condition (GET_CODE (x
))
7009 case NE
: fputs ("ne", file
); break;
7010 case EQ
: fputs ("e", file
); break;
7011 case GE
: fputs ("gez", file
); break;
7012 case LT
: fputs ("lz", file
); break;
7013 case LE
: fputs ("lez", file
); break;
7014 case GT
: fputs ("gz", file
); break;
7015 default: output_operand_lossage (code
== 'd'
7016 ? "invalid %%d operand"
7017 : "invalid %%D operand");
7024 /* Print a sign-extended character. */
7025 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
7026 fprintf (file
, "%d", i
);
7031 /* Operand must be a MEM; write its address. */
7032 if (GET_CODE (x
) != MEM
)
7033 output_operand_lossage ("invalid %%f operand");
7034 output_address (XEXP (x
, 0));
7039 /* Print a sign-extended 32-bit value. */
7041 if (GET_CODE(x
) == CONST_INT
)
7043 else if (GET_CODE(x
) == CONST_DOUBLE
)
7044 i
= CONST_DOUBLE_LOW (x
);
7047 output_operand_lossage ("invalid %%s operand");
7050 i
= trunc_int_for_mode (i
, SImode
);
7051 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
7056 /* Do nothing special. */
7060 /* Undocumented flag. */
7061 output_operand_lossage ("invalid operand output code");
7064 if (GET_CODE (x
) == REG
)
7065 fputs (reg_names
[REGNO (x
)], file
);
7066 else if (GET_CODE (x
) == MEM
)
7069 /* Poor Sun assembler doesn't understand absolute addressing. */
7070 if (CONSTANT_P (XEXP (x
, 0)))
7071 fputs ("%g0+", file
);
7072 output_address (XEXP (x
, 0));
7075 else if (GET_CODE (x
) == HIGH
)
7077 fputs ("%hi(", file
);
7078 output_addr_const (file
, XEXP (x
, 0));
7081 else if (GET_CODE (x
) == LO_SUM
)
7083 print_operand (file
, XEXP (x
, 0), 0);
7084 if (TARGET_CM_MEDMID
)
7085 fputs ("+%l44(", file
);
7087 fputs ("+%lo(", file
);
7088 output_addr_const (file
, XEXP (x
, 1));
7091 else if (GET_CODE (x
) == CONST_DOUBLE
7092 && (GET_MODE (x
) == VOIDmode
7093 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
7095 if (CONST_DOUBLE_HIGH (x
) == 0)
7096 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
7097 else if (CONST_DOUBLE_HIGH (x
) == -1
7098 && CONST_DOUBLE_LOW (x
) < 0)
7099 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
7101 output_operand_lossage ("long long constant not a valid immediate operand");
7103 else if (GET_CODE (x
) == CONST_DOUBLE
)
7104 output_operand_lossage ("floating point constant not a valid immediate operand");
7105 else { output_addr_const (file
, x
); }
7108 /* Target hook for assembling integer objects. The sparc version has
7109 special handling for aligned DI-mode objects. */
7112 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
7114 /* ??? We only output .xword's for symbols and only then in environments
7115 where the assembler can handle them. */
7116 if (aligned_p
&& size
== 8
7117 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
7121 assemble_integer_with_op ("\t.xword\t", x
);
7126 assemble_aligned_integer (4, const0_rtx
);
7127 assemble_aligned_integer (4, x
);
7131 return default_assemble_integer (x
, size
, aligned_p
);
7134 /* Return the value of a code used in the .proc pseudo-op that says
7135 what kind of result this function returns. For non-C types, we pick
7136 the closest C type. */
7138 #ifndef SHORT_TYPE_SIZE
7139 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7142 #ifndef INT_TYPE_SIZE
7143 #define INT_TYPE_SIZE BITS_PER_WORD
7146 #ifndef LONG_TYPE_SIZE
7147 #define LONG_TYPE_SIZE BITS_PER_WORD
7150 #ifndef LONG_LONG_TYPE_SIZE
7151 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7154 #ifndef FLOAT_TYPE_SIZE
7155 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7158 #ifndef DOUBLE_TYPE_SIZE
7159 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7162 #ifndef LONG_DOUBLE_TYPE_SIZE
7163 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7167 sparc_type_code (register tree type
)
7169 register unsigned long qualifiers
= 0;
7170 register unsigned shift
;
7172 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7173 setting more, since some assemblers will give an error for this. Also,
7174 we must be careful to avoid shifts of 32 bits or more to avoid getting
7175 unpredictable results. */
7177 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
7179 switch (TREE_CODE (type
))
7185 qualifiers
|= (3 << shift
);
7190 qualifiers
|= (2 << shift
);
7194 case REFERENCE_TYPE
:
7196 qualifiers
|= (1 << shift
);
7200 return (qualifiers
| 8);
7203 case QUAL_UNION_TYPE
:
7204 return (qualifiers
| 9);
7207 return (qualifiers
| 10);
7210 return (qualifiers
| 16);
7213 /* If this is a range type, consider it to be the underlying
7215 if (TREE_TYPE (type
) != 0)
7218 /* Carefully distinguish all the standard types of C,
7219 without messing up if the language is not C. We do this by
7220 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
7221 look at both the names and the above fields, but that's redundant.
7222 Any type whose size is between two C types will be considered
7223 to be the wider of the two types. Also, we do not have a
7224 special code to use for "long long", so anything wider than
7225 long is treated the same. Note that we can't distinguish
7226 between "int" and "long" in this code if they are the same
7227 size, but that's fine, since neither can the assembler. */
7229 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
7230 return (qualifiers
| (TREE_UNSIGNED (type
) ? 12 : 2));
7232 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
7233 return (qualifiers
| (TREE_UNSIGNED (type
) ? 13 : 3));
7235 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
7236 return (qualifiers
| (TREE_UNSIGNED (type
) ? 14 : 4));
7239 return (qualifiers
| (TREE_UNSIGNED (type
) ? 15 : 5));
7242 /* If this is a range type, consider it to be the underlying
7244 if (TREE_TYPE (type
) != 0)
7247 /* Carefully distinguish all the standard types of C,
7248 without messing up if the language is not C. */
7250 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
7251 return (qualifiers
| 6);
7254 return (qualifiers
| 7);
7256 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
7257 /* ??? We need to distinguish between double and float complex types,
7258 but I don't know how yet because I can't reach this code from
7259 existing front-ends. */
7260 return (qualifiers
| 7); /* Who knows? */
7262 case CHAR_TYPE
: /* GNU Pascal CHAR type. Not used in C. */
7263 case BOOLEAN_TYPE
: /* GNU Fortran BOOLEAN type. */
7264 case FILE_TYPE
: /* GNU Pascal FILE type. */
7265 case SET_TYPE
: /* GNU Pascal SET type. */
7266 case LANG_TYPE
: /* ? */
7270 abort (); /* Not a type! */
7277 /* Nested function support. */
7279 /* Emit RTL insns to initialize the variable parts of a trampoline.
7280 FNADDR is an RTX for the address of the function's pure code.
7281 CXT is an RTX for the static chain value for the function.
7283 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7284 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7285 (to store insns). This is a bit excessive. Perhaps a different
7286 mechanism would be better here.
7288 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7291 sparc_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
7293 /* SPARC 32-bit trampoline:
7296 sethi %hi(static), %g2
7298 or %g2, %lo(static), %g2
7300 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7301 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7305 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 0)),
7306 expand_binop (SImode
, ior_optab
,
7307 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
7308 size_int (10), 0, 1),
7309 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
7310 NULL_RTX
, 1, OPTAB_DIRECT
));
7313 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
7314 expand_binop (SImode
, ior_optab
,
7315 expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
7316 size_int (10), 0, 1),
7317 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
7318 NULL_RTX
, 1, OPTAB_DIRECT
));
7321 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
7322 expand_binop (SImode
, ior_optab
,
7323 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
7324 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
7325 NULL_RTX
, 1, OPTAB_DIRECT
));
7328 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
7329 expand_binop (SImode
, ior_optab
,
7330 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
7331 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
7332 NULL_RTX
, 1, OPTAB_DIRECT
));
7334 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7335 aligned on a 16 byte boundary so one flush clears it all. */
7336 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
, tramp
))));
7337 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
7338 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
7339 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
,
7340 plus_constant (tramp
, 8)))));
7342 /* Call __enable_execute_stack after writing onto the stack to make sure
7343 the stack address is accessible. */
7344 #ifdef TRANSFER_FROM_TRAMPOLINE
7345 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
7346 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
7351 /* The 64-bit version is simpler because it makes more sense to load the
7352 values as "immediate" data out of the trampoline. It's also easier since
7353 we can read the PC without clobbering a register. */
7356 sparc64_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
7358 /* SPARC 64-bit trampoline:
7367 emit_move_insn (gen_rtx_MEM (SImode
, tramp
),
7368 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
7369 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
7370 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
7371 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
7372 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
7373 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
7374 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
7375 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)), cxt
);
7376 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 24)), fnaddr
);
7377 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, tramp
))));
7379 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
7380 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
7381 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)))));
7383 /* Call __enable_execute_stack after writing onto the stack to make sure
7384 the stack address is accessible. */
7385 #ifdef TRANSFER_FROM_TRAMPOLINE
7386 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
7387 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
7391 /* Adjust the cost of a scheduling dependency. Return the new cost of
7392 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7395 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
7397 enum attr_type insn_type
;
7399 if (! recog_memoized (insn
))
7402 insn_type
= get_attr_type (insn
);
7404 if (REG_NOTE_KIND (link
) == 0)
7406 /* Data dependency; DEP_INSN writes a register that INSN reads some
7409 /* if a load, then the dependence must be on the memory address;
7410 add an extra "cycle". Note that the cost could be two cycles
7411 if the reg was written late in an instruction group; we ca not tell
7413 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
7416 /* Get the delay only if the address of the store is the dependence. */
7417 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
7419 rtx pat
= PATTERN(insn
);
7420 rtx dep_pat
= PATTERN (dep_insn
);
7422 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7423 return cost
; /* This should not happen! */
7425 /* The dependency between the two instructions was on the data that
7426 is being stored. Assume that this implies that the address of the
7427 store is not dependent. */
7428 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7431 return cost
+ 3; /* An approximation. */
7434 /* A shift instruction cannot receive its data from an instruction
7435 in the same cycle; add a one cycle penalty. */
7436 if (insn_type
== TYPE_SHIFT
)
7437 return cost
+ 3; /* Split before cascade into shift. */
7441 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7442 INSN writes some cycles later. */
7444 /* These are only significant for the fpu unit; writing a fp reg before
7445 the fpu has finished with it stalls the processor. */
7447 /* Reusing an integer register causes no problems. */
7448 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7456 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
7458 enum attr_type insn_type
, dep_type
;
7459 rtx pat
= PATTERN(insn
);
7460 rtx dep_pat
= PATTERN (dep_insn
);
7462 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
7465 insn_type
= get_attr_type (insn
);
7466 dep_type
= get_attr_type (dep_insn
);
7468 switch (REG_NOTE_KIND (link
))
7471 /* Data dependency; DEP_INSN writes a register that INSN reads some
7478 /* Get the delay iff the address of the store is the dependence. */
7479 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7482 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7489 /* If a load, then the dependence must be on the memory address. If
7490 the addresses aren't equal, then it might be a false dependency */
7491 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
7493 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
7494 || GET_CODE (SET_DEST (dep_pat
)) != MEM
7495 || GET_CODE (SET_SRC (pat
)) != MEM
7496 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
7497 XEXP (SET_SRC (pat
), 0)))
7505 /* Compare to branch latency is 0. There is no benefit from
7506 separating compare and branch. */
7507 if (dep_type
== TYPE_COMPARE
)
7509 /* Floating point compare to branch latency is less than
7510 compare to conditional move. */
7511 if (dep_type
== TYPE_FPCMP
)
7520 /* Anti-dependencies only penalize the fpu unit. */
7521 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7533 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
7537 case PROCESSOR_SUPERSPARC
:
7538 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
7540 case PROCESSOR_HYPERSPARC
:
7541 case PROCESSOR_SPARCLITE86X
:
7542 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
7551 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
7552 int sched_verbose ATTRIBUTE_UNUSED
,
7553 int max_ready ATTRIBUTE_UNUSED
)
7558 sparc_use_dfa_pipeline_interface (void)
7560 if ((1 << sparc_cpu
) &
7561 ((1 << PROCESSOR_ULTRASPARC
) | (1 << PROCESSOR_CYPRESS
) |
7562 (1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
7563 (1 << PROCESSOR_SPARCLITE86X
) | (1 << PROCESSOR_TSC701
) |
7564 (1 << PROCESSOR_ULTRASPARC3
)))
7570 sparc_use_sched_lookahead (void)
7572 if (sparc_cpu
== PROCESSOR_ULTRASPARC
7573 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
7575 if ((1 << sparc_cpu
) &
7576 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
7577 (1 << PROCESSOR_SPARCLITE86X
)))
7583 sparc_issue_rate (void)
7590 /* Assume V9 processors are capable of at least dual-issue. */
7592 case PROCESSOR_SUPERSPARC
:
7594 case PROCESSOR_HYPERSPARC
:
7595 case PROCESSOR_SPARCLITE86X
:
7597 case PROCESSOR_ULTRASPARC
:
7598 case PROCESSOR_ULTRASPARC3
:
7604 set_extends (rtx insn
)
7606 register rtx pat
= PATTERN (insn
);
7608 switch (GET_CODE (SET_SRC (pat
)))
7610 /* Load and some shift instructions zero extend. */
7613 /* sethi clears the high bits */
7615 /* LO_SUM is used with sethi. sethi cleared the high
7616 bits and the values used with lo_sum are positive */
7618 /* Store flag stores 0 or 1 */
7628 rtx op0
= XEXP (SET_SRC (pat
), 0);
7629 rtx op1
= XEXP (SET_SRC (pat
), 1);
7630 if (GET_CODE (op1
) == CONST_INT
)
7631 return INTVAL (op1
) >= 0;
7632 if (GET_CODE (op0
) != REG
)
7634 if (sparc_check_64 (op0
, insn
) == 1)
7636 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7641 rtx op0
= XEXP (SET_SRC (pat
), 0);
7642 rtx op1
= XEXP (SET_SRC (pat
), 1);
7643 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
7645 if (GET_CODE (op1
) == CONST_INT
)
7646 return INTVAL (op1
) >= 0;
7647 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7650 return GET_MODE (SET_SRC (pat
)) == SImode
;
7651 /* Positive integers leave the high bits zero. */
7653 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
7655 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
7658 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
7660 return sparc_check_64 (SET_SRC (pat
), insn
);
7666 /* We _ought_ to have only one kind per function, but... */
7667 static GTY(()) rtx sparc_addr_diff_list
;
7668 static GTY(()) rtx sparc_addr_list
;
7671 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
7673 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
7675 sparc_addr_diff_list
7676 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
7678 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
7682 sparc_output_addr_vec (rtx vec
)
7684 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7685 int idx
, vlen
= XVECLEN (body
, 0);
7687 #ifdef ASM_OUTPUT_ADDR_VEC_START
7688 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7691 #ifdef ASM_OUTPUT_CASE_LABEL
7692 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7695 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7698 for (idx
= 0; idx
< vlen
; idx
++)
7700 ASM_OUTPUT_ADDR_VEC_ELT
7701 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
7704 #ifdef ASM_OUTPUT_ADDR_VEC_END
7705 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7710 sparc_output_addr_diff_vec (rtx vec
)
7712 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7713 rtx base
= XEXP (XEXP (body
, 0), 0);
7714 int idx
, vlen
= XVECLEN (body
, 1);
7716 #ifdef ASM_OUTPUT_ADDR_VEC_START
7717 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7720 #ifdef ASM_OUTPUT_CASE_LABEL
7721 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7724 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7727 for (idx
= 0; idx
< vlen
; idx
++)
7729 ASM_OUTPUT_ADDR_DIFF_ELT
7732 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
7733 CODE_LABEL_NUMBER (base
));
7736 #ifdef ASM_OUTPUT_ADDR_VEC_END
7737 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7742 sparc_output_deferred_case_vectors (void)
7747 if (sparc_addr_list
== NULL_RTX
7748 && sparc_addr_diff_list
== NULL_RTX
)
7751 /* Align to cache line in the function's code section. */
7752 function_section (current_function_decl
);
7754 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
7756 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
7758 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
7759 sparc_output_addr_vec (XEXP (t
, 0));
7760 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
7761 sparc_output_addr_diff_vec (XEXP (t
, 0));
7763 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
7766 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7767 unknown. Return 1 if the high bits are zero, -1 if the register is
7770 sparc_check_64 (rtx x
, rtx insn
)
7772 /* If a register is set only once it is safe to ignore insns this
7773 code does not know how to handle. The loop will either recognize
7774 the single set and return the correct value or fail to recognize
7779 if (GET_CODE (x
) != REG
)
7782 if (GET_MODE (x
) == DImode
)
7783 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
7785 if (flag_expensive_optimizations
7786 && REG_N_SETS (REGNO (y
)) == 1)
7792 insn
= get_last_insn_anywhere ();
7797 while ((insn
= PREV_INSN (insn
)))
7799 switch (GET_CODE (insn
))
7812 rtx pat
= PATTERN (insn
);
7813 if (GET_CODE (pat
) != SET
)
7815 if (rtx_equal_p (x
, SET_DEST (pat
)))
7816 return set_extends (insn
);
7817 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
7818 return set_extends (insn
);
7819 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
7827 /* Returns assembly code to perform a DImode shift using
7828 a 64-bit global or out register on SPARC-V8+. */
7830 sparc_v8plus_shift (rtx
*operands
, rtx insn
, const char *opcode
)
7832 static char asm_code
[60];
7834 /* The scratch register is only required when the destination
7835 register is not a 64-bit global or out register. */
7836 if (which_alternative
!= 2)
7837 operands
[3] = operands
[0];
7839 /* We can only shift by constants <= 63. */
7840 if (GET_CODE (operands
[2]) == CONST_INT
)
7841 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
7843 if (GET_CODE (operands
[1]) == CONST_INT
)
7845 output_asm_insn ("mov\t%1, %3", operands
);
7849 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
7850 if (sparc_check_64 (operands
[1], insn
) <= 0)
7851 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
7852 output_asm_insn ("or\t%L1, %3, %3", operands
);
7855 strcpy(asm_code
, opcode
);
7857 if (which_alternative
!= 2)
7858 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7860 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7863 /* Output rtl to increment the profiler label LABELNO
7864 for profiling a function entry. */
7867 sparc_profile_hook (int labelno
)
7872 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
7873 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
7874 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
7876 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
7879 #ifdef OBJECT_FORMAT_ELF
7881 sparc_elf_asm_named_section (const char *name
, unsigned int flags
)
7883 if (flags
& SECTION_MERGE
)
7885 /* entsize cannot be expressed in this section attributes
7887 default_elf_asm_named_section (name
, flags
);
7891 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
7893 if (!(flags
& SECTION_DEBUG
))
7894 fputs (",#alloc", asm_out_file
);
7895 if (flags
& SECTION_WRITE
)
7896 fputs (",#write", asm_out_file
);
7897 if (flags
& SECTION_TLS
)
7898 fputs (",#tls", asm_out_file
);
7899 if (flags
& SECTION_CODE
)
7900 fputs (",#execinstr", asm_out_file
);
7902 /* ??? Handle SECTION_BSS. */
7904 fputc ('\n', asm_out_file
);
7906 #endif /* OBJECT_FORMAT_ELF */
7908 /* We do not allow indirect calls to be optimized into sibling calls.
7910 Also, on SPARC 32-bit we cannot emit a sibling call when the
7911 current function returns a structure. This is because the "unimp
7912 after call" convention would cause the callee to return to the
7913 wrong place. The generic code already disallows cases where the
7914 function being called returns a structure.
7916 It may seem strange how this last case could occur. Usually there
7917 is code after the call which jumps to epilogue code which dumps the
7918 return value into the struct return area. That ought to invalidate
7919 the sibling call right? Well, in the c++ case we can end up passing
7920 the pointer to the struct return area to a constructor (which returns
7921 void) and then nothing else happens. Such a sibling call would look
7922 valid without the added check here. */
7924 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7926 return (decl
&& (TARGET_ARCH64
|| ! current_function_returns_struct
));
7929 /* libfunc renaming. */
7930 #include "config/gofast.h"
7933 sparc_init_libfuncs (void)
7937 /* Use the subroutines that Sun's library provides for integer
7938 multiply and divide. The `*' prevents an underscore from
7939 being prepended by the compiler. .umul is a little faster
7941 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
7942 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
7943 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
7944 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
7945 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
7947 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
7948 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
7949 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
7950 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
7951 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
7952 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
7954 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
7955 is because with soft-float, the SFmode and DFmode sqrt
7956 instructions will be absent, and the compiler will notice and
7957 try to use the TFmode sqrt instruction for calls to the
7958 builtin function sqrt, but this fails. */
7960 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
7962 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
7963 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
7964 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
7965 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
7966 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
7967 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
7969 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
7970 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
7971 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
7972 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
7974 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
7975 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
7976 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
7978 if (SUN_CONVERSION_LIBFUNCS
)
7980 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
7981 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
7982 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
7983 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
7988 /* In the SPARC 64bit ABI, SImode multiply and divide functions
7989 do not exist in the library. Make sure the compiler does not
7990 emit calls to them by accident. (It should always use the
7991 hardware instructions.) */
7992 set_optab_libfunc (smul_optab
, SImode
, 0);
7993 set_optab_libfunc (sdiv_optab
, SImode
, 0);
7994 set_optab_libfunc (udiv_optab
, SImode
, 0);
7995 set_optab_libfunc (smod_optab
, SImode
, 0);
7996 set_optab_libfunc (umod_optab
, SImode
, 0);
7998 if (SUN_INTEGER_MULTIPLY_64
)
8000 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
8001 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
8002 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
8003 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
8004 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
8007 if (SUN_CONVERSION_LIBFUNCS
)
8009 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
8010 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
8011 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
8012 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
8016 gofast_maybe_init_libfuncs ();
8019 /* ??? Similar to the standard section selection, but force reloc-y-ness
8020 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8021 pretending PIC always on), but that's what the old code did. */
8024 sparc_aout_select_section (tree t
, int reloc
, unsigned HOST_WIDE_INT align
)
8026 default_select_section (t
, reloc
| SUNOS4_SHARED_LIBRARIES
, align
);
8029 /* Use text section for a constant unless we need more alignment than
8033 sparc_aout_select_rtx_section (enum machine_mode mode
, rtx x
,
8034 unsigned HOST_WIDE_INT align
)
8036 if (align
<= MAX_TEXT_ALIGN
8037 && ! (flag_pic
&& (symbolic_operand (x
, mode
)
8038 || SUNOS4_SHARED_LIBRARIES
)))
8039 readonly_data_section ();
8045 sparc_extra_constraint_check (rtx op
, int c
, int strict
)
8050 && (c
== 'T' || c
== 'U'))
8056 return fp_sethi_p (op
);
8059 return fp_mov_p (op
);
8062 return fp_high_losum_p (op
);
8066 || (GET_CODE (op
) == REG
8067 && (REGNO (op
) < FIRST_PSEUDO_REGISTER
8068 || reg_renumber
[REGNO (op
)] >= 0)))
8069 return register_ok_for_ldd (op
);
8081 /* Our memory extra constraints have to emulate the
8082 behavior of 'm' and 'o' in order for reload to work
8084 if (GET_CODE (op
) == MEM
)
8087 if ((TARGET_ARCH64
|| mem_min_alignment (op
, 8))
8089 || strict_memory_address_p (Pmode
, XEXP (op
, 0))))
8094 reload_ok_mem
= (reload_in_progress
8095 && GET_CODE (op
) == REG
8096 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
8097 && reg_renumber
[REGNO (op
)] < 0);
8100 return reload_ok_mem
;
8103 /* ??? This duplicates information provided to the compiler by the
8104 ??? scheduler description. Some day, teach genautomata to output
8105 ??? the latencies and then CSE will just use that. */
8108 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
8112 case PLUS
: case MINUS
: case ABS
: case NEG
:
8113 case FLOAT
: case UNSIGNED_FLOAT
:
8114 case FIX
: case UNSIGNED_FIX
:
8115 case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
8116 if (FLOAT_MODE_P (GET_MODE (x
)))
8120 case PROCESSOR_ULTRASPARC
:
8121 case PROCESSOR_ULTRASPARC3
:
8122 *total
= COSTS_N_INSNS (4);
8125 case PROCESSOR_SUPERSPARC
:
8126 *total
= COSTS_N_INSNS (3);
8129 case PROCESSOR_CYPRESS
:
8130 *total
= COSTS_N_INSNS (5);
8133 case PROCESSOR_HYPERSPARC
:
8134 case PROCESSOR_SPARCLITE86X
:
8136 *total
= COSTS_N_INSNS (1);
8141 *total
= COSTS_N_INSNS (1);
8147 case PROCESSOR_ULTRASPARC
:
8148 if (GET_MODE (x
) == SFmode
)
8149 *total
= COSTS_N_INSNS (13);
8151 *total
= COSTS_N_INSNS (23);
8154 case PROCESSOR_ULTRASPARC3
:
8155 if (GET_MODE (x
) == SFmode
)
8156 *total
= COSTS_N_INSNS (20);
8158 *total
= COSTS_N_INSNS (29);
8161 case PROCESSOR_SUPERSPARC
:
8162 *total
= COSTS_N_INSNS (12);
8165 case PROCESSOR_CYPRESS
:
8166 *total
= COSTS_N_INSNS (63);
8169 case PROCESSOR_HYPERSPARC
:
8170 case PROCESSOR_SPARCLITE86X
:
8171 *total
= COSTS_N_INSNS (17);
8175 *total
= COSTS_N_INSNS (30);
8180 if (FLOAT_MODE_P (GET_MODE (x
)))
8184 case PROCESSOR_ULTRASPARC
:
8185 case PROCESSOR_ULTRASPARC3
:
8186 *total
= COSTS_N_INSNS (1);
8189 case PROCESSOR_SUPERSPARC
:
8190 *total
= COSTS_N_INSNS (3);
8193 case PROCESSOR_CYPRESS
:
8194 *total
= COSTS_N_INSNS (5);
8197 case PROCESSOR_HYPERSPARC
:
8198 case PROCESSOR_SPARCLITE86X
:
8200 *total
= COSTS_N_INSNS (1);
8205 /* ??? Maybe mark integer compares as zero cost on
8206 ??? all UltraSPARC processors because the result
8207 ??? can be bypassed to a branch in the same group. */
8209 *total
= COSTS_N_INSNS (1);
8213 if (FLOAT_MODE_P (GET_MODE (x
)))
8217 case PROCESSOR_ULTRASPARC
:
8218 case PROCESSOR_ULTRASPARC3
:
8219 *total
= COSTS_N_INSNS (4);
8222 case PROCESSOR_SUPERSPARC
:
8223 *total
= COSTS_N_INSNS (3);
8226 case PROCESSOR_CYPRESS
:
8227 *total
= COSTS_N_INSNS (7);
8230 case PROCESSOR_HYPERSPARC
:
8231 case PROCESSOR_SPARCLITE86X
:
8232 *total
= COSTS_N_INSNS (1);
8236 *total
= COSTS_N_INSNS (5);
8241 /* The latency is actually variable for Ultra-I/II
8242 And if one of the inputs have a known constant
8243 value, we could calculate this precisely.
8245 However, for that to be useful we would need to
8246 add some machine description changes which would
8247 make sure small constants ended up in rs1 of the
8248 multiply instruction. This is because the multiply
8249 latency is determined by the number of clear (or
8250 set if the value is negative) bits starting from
8251 the most significant bit of the first input.
8253 The algorithm for computing num_cycles of a multiply
8257 highest_bit = highest_clear_bit(rs1);
8259 highest_bit = highest_set_bit(rs1);
8262 num_cycles = 4 + ((highest_bit - 3) / 2);
8264 If we did that we would have to also consider register
8265 allocation issues that would result from forcing such
8266 a value into a register.
8268 There are other similar tricks we could play if we
8269 knew, for example, that one input was an array index.
8271 Since we do not play any such tricks currently the
8272 safest thing to do is report the worst case latency. */
8273 if (sparc_cpu
== PROCESSOR_ULTRASPARC
)
8275 *total
= (GET_MODE (x
) == DImode
8276 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8280 /* Multiply latency on Ultra-III, fortunately, is constant. */
8281 if (sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8283 *total
= COSTS_N_INSNS (6);
8287 if (sparc_cpu
== PROCESSOR_HYPERSPARC
8288 || sparc_cpu
== PROCESSOR_SPARCLITE86X
)
8290 *total
= COSTS_N_INSNS (17);
8294 *total
= (TARGET_HARD_MUL
? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
8301 if (FLOAT_MODE_P (GET_MODE (x
)))
8305 case PROCESSOR_ULTRASPARC
:
8306 if (GET_MODE (x
) == SFmode
)
8307 *total
= COSTS_N_INSNS (13);
8309 *total
= COSTS_N_INSNS (23);
8312 case PROCESSOR_ULTRASPARC3
:
8313 if (GET_MODE (x
) == SFmode
)
8314 *total
= COSTS_N_INSNS (17);
8316 *total
= COSTS_N_INSNS (20);
8319 case PROCESSOR_SUPERSPARC
:
8320 if (GET_MODE (x
) == SFmode
)
8321 *total
= COSTS_N_INSNS (6);
8323 *total
= COSTS_N_INSNS (9);
8326 case PROCESSOR_HYPERSPARC
:
8327 case PROCESSOR_SPARCLITE86X
:
8328 if (GET_MODE (x
) == SFmode
)
8329 *total
= COSTS_N_INSNS (8);
8331 *total
= COSTS_N_INSNS (12);
8335 *total
= COSTS_N_INSNS (7);
8340 if (sparc_cpu
== PROCESSOR_ULTRASPARC
)
8341 *total
= (GET_MODE (x
) == DImode
8342 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8343 else if (sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8344 *total
= (GET_MODE (x
) == DImode
8345 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8347 *total
= COSTS_N_INSNS (25);
8351 /* Conditional moves. */
8354 case PROCESSOR_ULTRASPARC
:
8355 *total
= COSTS_N_INSNS (2);
8358 case PROCESSOR_ULTRASPARC3
:
8359 if (FLOAT_MODE_P (GET_MODE (x
)))
8360 *total
= COSTS_N_INSNS (3);
8362 *total
= COSTS_N_INSNS (2);
8366 *total
= COSTS_N_INSNS (1);
8371 /* If outer-code is SIGN/ZERO extension we have to subtract
8372 out COSTS_N_INSNS (1) from whatever we return in determining
8376 case PROCESSOR_ULTRASPARC
:
8377 if (outer_code
== ZERO_EXTEND
)
8378 *total
= COSTS_N_INSNS (1);
8380 *total
= COSTS_N_INSNS (2);
8383 case PROCESSOR_ULTRASPARC3
:
8384 if (outer_code
== ZERO_EXTEND
)
8386 if (GET_MODE (x
) == QImode
8387 || GET_MODE (x
) == HImode
8388 || outer_code
== SIGN_EXTEND
)
8389 *total
= COSTS_N_INSNS (2);
8391 *total
= COSTS_N_INSNS (1);
8395 /* This handles sign extension (3 cycles)
8396 and everything else (2 cycles). */
8397 *total
= COSTS_N_INSNS (2);
8401 case PROCESSOR_SUPERSPARC
:
8402 if (FLOAT_MODE_P (GET_MODE (x
))
8403 || outer_code
== ZERO_EXTEND
8404 || outer_code
== SIGN_EXTEND
)
8405 *total
= COSTS_N_INSNS (0);
8407 *total
= COSTS_N_INSNS (1);
8410 case PROCESSOR_TSC701
:
8411 if (outer_code
== ZERO_EXTEND
8412 || outer_code
== SIGN_EXTEND
)
8413 *total
= COSTS_N_INSNS (2);
8415 *total
= COSTS_N_INSNS (3);
8418 case PROCESSOR_CYPRESS
:
8419 if (outer_code
== ZERO_EXTEND
8420 || outer_code
== SIGN_EXTEND
)
8421 *total
= COSTS_N_INSNS (1);
8423 *total
= COSTS_N_INSNS (2);
8426 case PROCESSOR_HYPERSPARC
:
8427 case PROCESSOR_SPARCLITE86X
:
8429 if (outer_code
== ZERO_EXTEND
8430 || outer_code
== SIGN_EXTEND
)
8431 *total
= COSTS_N_INSNS (0);
8433 *total
= COSTS_N_INSNS (1);
8438 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
8456 if (GET_MODE (x
) == DImode
8457 && ((XINT (x
, 3) == 0
8458 && (unsigned HOST_WIDE_INT
) XINT (x
, 2) < 0x1000)
8459 || (XINT (x
, 3) == -1
8461 && XINT (x
, 2) >= -0x1000)))
8472 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8473 Used for C++ multiple inheritance. */
8476 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
8477 HOST_WIDE_INT delta
,
8478 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
8481 rtx
this, insn
, funexp
, delta_rtx
, tmp
;
8483 reload_completed
= 1;
8484 epilogue_completed
= 1;
8486 current_function_uses_only_leaf_regs
= 1;
8488 emit_note (NOTE_INSN_PROLOGUE_END
);
8490 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8491 returns a structure, the structure return pointer is there instead. */
8492 if (TARGET_ARCH64
&& aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8493 this = gen_rtx_REG (Pmode
, SPARC_INCOMING_INT_ARG_FIRST
+ 1);
8495 this = gen_rtx_REG (Pmode
, SPARC_INCOMING_INT_ARG_FIRST
);
8497 /* Add DELTA. When possible use a plain add, otherwise load it into
8498 a register first. */
8499 delta_rtx
= GEN_INT (delta
);
8500 if (!SPARC_SIMM13_P (delta
))
8502 rtx scratch
= gen_rtx_REG (Pmode
, 1);
8504 if (input_operand (delta_rtx
, GET_MODE (scratch
)))
8505 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, delta_rtx
));
8509 sparc_emit_set_const64 (scratch
, delta_rtx
);
8511 sparc_emit_set_const32 (scratch
, delta_rtx
);
8514 delta_rtx
= scratch
;
8517 tmp
= gen_rtx_PLUS (Pmode
, this, delta_rtx
);
8518 emit_insn (gen_rtx_SET (VOIDmode
, this, tmp
));
8520 /* Generate a tail call to the target function. */
8521 if (! TREE_USED (function
))
8523 assemble_external (function
);
8524 TREE_USED (function
) = 1;
8526 funexp
= XEXP (DECL_RTL (function
), 0);
8527 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8528 insn
= emit_call_insn (gen_sibcall (funexp
));
8529 SIBLING_CALL_P (insn
) = 1;
8532 /* Run just enough of rest_of_compilation to get the insns emitted.
8533 There's not really enough bulk here to make other passes such as
8534 instruction scheduling worth while. Note that use_thunk calls
8535 assemble_start_function and assemble_end_function. */
8536 insn
= get_insns ();
8537 insn_locators_initialize ();
8538 shorten_branches (insn
);
8539 final_start_function (insn
, file
, 1);
8540 final (insn
, file
, 1, 0);
8541 final_end_function ();
8543 reload_completed
= 0;
8544 epilogue_completed
= 0;
8548 /* How to allocate a 'struct machine_function'. */
8550 static struct machine_function
*
8551 sparc_init_machine_status (void)
8553 return ggc_alloc_cleared (sizeof (struct machine_function
));
8556 /* Locate some local-dynamic symbol still in use by this function
8557 so that we can print its name in local-dynamic base patterns. */
8560 get_some_local_dynamic_name (void)
8564 if (cfun
->machine
->some_ld_name
)
8565 return cfun
->machine
->some_ld_name
;
8567 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8569 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
8570 return cfun
->machine
->some_ld_name
;
8576 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
8581 && GET_CODE (x
) == SYMBOL_REF
8582 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
8584 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
8591 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
8592 We need to emit DTP-relative relocations. */
8595 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8600 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
8603 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
8608 output_addr_const (file
, x
);
8612 #include "gt-sparc.h"