| blob | b2dd8f9bcc681a012e6329f6848ea6fca15ee1bb |
1 /* Definitions of target machine for GNU compiler for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
27 #define TARGET_VERSION \
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because hconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
35 /* Generate SDB debugging information. */
37 #define SDB_DEBUGGING_INFO
39 /* Output DBX (stabs) debugging information if doing -gstabs. */
46 %{m1:-D__sh1__} \
47 %{m2:-D__sh2__} \
48 %{m3:-D__sh3__} \
49 %{m3e:-D__SH3E__} \
50 %{m4-single-only:-D__SH4_SINGLE_ONLY__} \
51 %{m4-single:-D__SH4_SINGLE__} \
52 %{m4-nofpu:-D__sh3__ -D__SH4_NOFPU__} \
53 %{m4:-D__SH4__} \
54 %{!m1:%{!m2:%{!m3*:%{!m4*:%(cpp_default_cpu_spec)}}}} \
55 %{mnomacsave:-D__NOMACSAVE__} \
56 %{mhitachi:-D__HITACHI__} \
57 %(subtarget_cpp_spec) \
58 %(subtarget_cpp_ptr_spec) \
59 %(subtarget_cpp_endian_spec) "
61 #ifndef SUBTARGET_CPP_ENDIAN_SPEC
63 #endif
65 #ifndef SUBTARGET_CPP_SPEC
67 #endif
69 #ifndef CPP_DEFAULT_CPU_SPEC
71 #endif
73 #ifndef SUBTARGET_CPP_PTR_SPEC
75 #endif
77 #define EXTRA_SPECS \
89 /* We can not debug without a frame pointer. */
90 /* #define CAN_DEBUG_WITHOUT_FP */
92 #define CONDITIONAL_REGISTER_USAGE do \
93 { \
94 int regno; \
95 if (! TARGET_SH4 || ! TARGET_FMOVD) \
96 { \
97 for (regno = FIRST_XD_REG; regno <= LAST_XD_REG; regno++) \
98 fixed_regs[regno] = call_used_regs[regno] = 1; \
99 if (! TARGET_SH4) \
100 { \
101 if (! TARGET_SH3E) \
102 { \
103 for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \
104 fixed_regs[regno] = call_used_regs[regno] = 1; \
105 fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1; \
106 } \
107 } \
108 } \
109 if (flag_pic) \
110 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
112 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
113 { \
114 call_used_regs[MACH_REG] = 0; \
115 call_used_regs[MACL_REG] = 0; \
116 } \
117 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
118 if (! fixed_regs[regno] && call_used_regs[regno]) \
119 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
120 } while (0)
121 \f
122 /* ??? Need to write documentation for all SH options and add it to the
123 invoke.texi file. */
125 /* Run-time compilation parameters selecting different hardware subsets. */
128 #define ISIZE_BIT (1<<1)
129 #define DALIGN_BIT (1<<6)
130 #define SH1_BIT (1<<8)
131 #define SH2_BIT (1<<9)
132 #define SH3_BIT (1<<10)
133 #define SH3E_BIT (1<<11)
134 #define HARD_SH4_BIT (1<<5)
135 #define FPU_SINGLE_BIT (1<<7)
136 #define SH4_BIT (1<<12)
137 #define FMOVD_BIT (1<<4)
138 #define SPACE_BIT (1<<13)
139 #define BIGTABLE_BIT (1<<14)
140 #define RELAX_BIT (1<<15)
141 #define USERMODE_BIT (1<<16)
142 #define HITACHI_BIT (1<<22)
143 #define NOMACSAVE_BIT (1<<23)
144 #define PREFERGOT_BIT (1<<24)
145 #define PADSTRUCT_BIT (1<<28)
146 #define LITTLE_ENDIAN_BIT (1<<29)
147 #define IEEE_BIT (1<<30)
149 /* Nonzero if we should dump out instruction size info. */
150 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
152 /* Nonzero to align doubles on 64 bit boundaries. */
153 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
155 /* Nonzero if we should generate code using type 1 insns. */
156 #define TARGET_SH1 (target_flags & SH1_BIT)
158 /* Nonzero if we should generate code using type 2 insns. */
159 #define TARGET_SH2 (target_flags & SH2_BIT)
161 /* Nonzero if we should generate code using type 3 insns. */
162 #define TARGET_SH3 (target_flags & SH3_BIT)
164 /* Nonzero if we should generate code using type 3E insns. */
165 #define TARGET_SH3E (target_flags & SH3E_BIT)
167 /* Nonzero if the cache line size is 32. */
168 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT)
170 /* Nonzero if we schedule for a superscalar implementation. */
171 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
173 /* Nonzero if the target has separate instruction and data caches. */
174 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
176 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
177 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
179 /* Nonzero if the default precision of th FPU is single */
180 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
182 /* Nonzero if we should generate code using type 4 insns. */
183 #define TARGET_SH4 (target_flags & SH4_BIT)
185 /* Nonzero if we should generate fmovd. */
186 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
188 /* Nonzero if we respect NANs. */
189 #define TARGET_IEEE (target_flags & IEEE_BIT)
191 /* Nonzero if we should generate smaller code rather than faster code. */
192 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
194 /* Nonzero to use long jump tables. */
195 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
197 /* Nonzero to generate pseudo-ops needed by the assembler and linker
198 to do function call relaxing. */
199 #define TARGET_RELAX (target_flags & RELAX_BIT)
201 /* Nonzero if using Hitachi's calling convention. */
202 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
204 /* Nonzero if not saving macl/mach when using -mhitachi */
205 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
207 /* Nonzero if padding structures to a multiple of 4 bytes. This is
208 incompatible with Hitachi's compiler, and gives unusual structure layouts
209 which confuse programmers.
210 ??? This option is not useful, but is retained in case there are people
211 who are still relying on it. It may be deleted in the future. */
212 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
214 /* Nonzero if generating code for a little endian SH. */
215 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
217 /* Nonzero if we should do everything in userland. */
218 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
220 /* Nonzero if we should prefer @GOT calls when generating PIC. */
221 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
223 /* Reset all target-selection flags. */
224 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \
225 | HARD_SH4_BIT | FPU_SINGLE_BIT)
227 #define TARGET_SWITCHES \
259 SUBTARGET_SWITCHES \
261 }
263 /* This are meant to be redefined in the host dependent files */
264 #define SUBTARGET_SWITCHES
266 #define TARGET_DEFAULT (SH1_BIT)
268 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
269 do { \
270 if (LEVEL) \
271 flag_omit_frame_pointer = -1; \
272 if (SIZE) \
273 target_flags |= SPACE_BIT; \
274 } while (0)
276 #define ASSEMBLER_DIALECT assembler_dialect
280 #define OVERRIDE_OPTIONS \
281 do { \
282 sh_cpu = CPU_SH1; \
283 assembler_dialect = 0; \
284 if (TARGET_SH2) \
285 sh_cpu = CPU_SH2; \
286 if (TARGET_SH3) \
287 sh_cpu = CPU_SH3; \
288 if (TARGET_SH3E) \
289 sh_cpu = CPU_SH3E; \
290 if (TARGET_SH4) \
291 { \
292 assembler_dialect = 1; \
293 sh_cpu = CPU_SH4; \
294 } \
295 if (! TARGET_SH4 || ! TARGET_FMOVD) \
296 { \
297 /* Prevent usage of explicit register names for variables \
298 for registers not present / not addressable in the \
300 int regno; \
301 for (regno = (TARGET_SH3E) ? 17 : 0; \
302 regno <= 24; regno++) \
303 fp_reg_names[regno][0] = 0; \
304 } \
305 if (flag_omit_frame_pointer < 0) \
306 { \
307 /* The debugging information is sufficient, \
309 if (0) \
310 flag_omit_frame_pointer \
311 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
312 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
313 else \
314 flag_omit_frame_pointer = 0; \
315 } \
316 \
317 if (flag_pic && ! TARGET_PREFERGOT) \
318 flag_no_function_cse = 1; \
319 \
320 /* Never run scheduling before reload, since that can \
321 break global alloc, and generates slower code anyway due \
323 flag_schedule_insns = 0; \
324 } while (0)
325 \f
326 /* Target machine storage layout. */
328 /* Define to use software floating point emulator for REAL_ARITHMETIC and
329 decimal <-> binary conversion. */
330 #define REAL_ARITHMETIC
332 /* Define this if most significant bit is lowest numbered
333 in instructions that operate on numbered bit-fields. */
335 #define BITS_BIG_ENDIAN 0
337 /* Define this if most significant byte of a word is the lowest numbered. */
338 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
340 /* Define this if most significant word of a multiword number is the lowest
341 numbered. */
342 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
344 /* Define this to set the endianness to use in libgcc2.c, which can
345 not depend on target_flags. */
346 #if defined(__LITTLE_ENDIAN__)
347 #define LIBGCC2_WORDS_BIG_ENDIAN 0
348 #else
349 #define LIBGCC2_WORDS_BIG_ENDIAN 1
350 #endif
352 /* Number of bits in an addressable storage unit. */
353 #define BITS_PER_UNIT 8
355 /* Width in bits of a "word", which is the contents of a machine register.
356 Note that this is not necessarily the width of data type `int';
357 if using 16-bit ints on a 68000, this would still be 32.
358 But on a machine with 16-bit registers, this would be 16. */
359 #define BITS_PER_WORD 32
360 #define MAX_BITS_PER_WORD 32
362 /* Width of a word, in units (bytes). */
363 #define UNITS_PER_WORD 4
365 /* Width in bits of a pointer.
366 See also the macro `Pmode' defined below. */
367 #define POINTER_SIZE 32
369 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
370 #define PARM_BOUNDARY 32
372 /* Boundary (in *bits*) on which stack pointer should be aligned. */
373 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
375 /* The log (base 2) of the cache line size, in bytes. Processors prior to
376 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
377 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
378 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
380 /* Allocation boundary (in *bits*) for the code of a function.
381 32 bit alignment is faster, because instructions are always fetched as a
382 pair from a longword boundary. */
383 #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : (1 << CACHE_LOG) * 8)
385 /* Alignment of field after `int : 0' in a structure. */
386 #define EMPTY_FIELD_BOUNDARY 32
388 /* No data type wants to be aligned rounder than this. */
389 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
391 /* The best alignment to use in cases where we have a choice. */
392 #define FASTEST_ALIGNMENT 32
394 /* Make strings word-aligned so strcpy from constants will be faster. */
395 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
396 ((TREE_CODE (EXP) == STRING_CST \
397 && (ALIGN) < FASTEST_ALIGNMENT) \
398 ? FASTEST_ALIGNMENT : (ALIGN))
400 #ifndef MAX_OFILE_ALIGNMENT
401 #define MAX_OFILE_ALIGNMENT 128
402 #endif
404 /* Make arrays of chars word-aligned for the same reasons. */
405 #define DATA_ALIGNMENT(TYPE, ALIGN) \
406 (TREE_CODE (TYPE) == ARRAY_TYPE \
407 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
408 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
410 /* Number of bits which any structure or union's size must be a
411 multiple of. Each structure or union's size is rounded up to a
412 multiple of this. */
413 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
415 /* Set this nonzero if move instructions will actually fail to work
416 when given unaligned data. */
417 #define STRICT_ALIGNMENT 1
419 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
420 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
421 barrier_align (LABEL_AFTER_BARRIER)
423 #define LOOP_ALIGN(A_LABEL) \
424 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
425 ? 0 : sh_loop_align (A_LABEL))
427 #define LABEL_ALIGN(A_LABEL) \
428 ( \
429 (PREV_INSN (A_LABEL) \
430 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
431 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
432 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
434 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
435 : 0)
437 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
438 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
440 /* The base two logarithm of the known minimum alignment of an insn length. */
441 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
442 (GET_CODE (A_INSN) == INSN \
443 ? 1 \
444 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
445 ? 1 \
446 : CACHE_LOG)
447 \f
448 /* Standard register usage. */
450 /* Register allocation for the Hitachi calling convention:
452 r0 arg return
453 r1..r3 scratch
454 r4..r7 args in
455 r8..r13 call saved
456 r14 frame pointer/call saved
457 r15 stack pointer
458 ap arg pointer (doesn't really exist, always eliminated)
459 pr subroutine return address
460 t t bit
461 mach multiply/accumulate result, high part
462 macl multiply/accumulate result, low part.
463 fpul fp/int communication register
464 rap return address pointer register
465 fr0 fp arg return
466 fr1..fr3 scratch floating point registers
467 fr4..fr11 fp args in
468 fr12..fr15 call saved floating point registers */
470 /* Number of actual hardware registers.
471 The hardware registers are assigned numbers for the compiler
472 from 0 to just below FIRST_PSEUDO_REGISTER.
473 All registers that the compiler knows about must be given numbers,
474 even those that are not normally considered general registers. */
476 /* There are many other relevant definitions in sh.md's md_constants. */
478 #define FIRST_GENERAL_REG R0_REG
479 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + 15)
480 #define FIRST_FP_REG DR0_REG
481 #define LAST_FP_REG (FIRST_FP_REG + 15)
482 #define FIRST_XD_REG XD0_REG
483 #define LAST_XD_REG (FIRST_XD_REG + 7)
485 #define GENERAL_REGISTER_P(REGNO) \
486 IN_RANGE ((REGNO), FIRST_GENERAL_REG, LAST_GENERAL_REG)
488 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
489 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
491 #define FP_REGISTER_P(REGNO) \
492 ((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG)
494 #define XD_REGISTER_P(REGNO) \
495 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG)
497 #define FP_OR_XD_REGISTER_P(REGNO) \
498 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
500 #define FP_ANY_REGISTER_P(REGNO) \
501 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
503 #define SPECIAL_REGISTER_P(REGNO) \
504 ((REGNO) == GBR_REG || (REGNO) == T_REG \
505 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
507 #define FIRST_PSEUDO_REGISTER 49
509 /* 1 for registers that have pervasive standard uses
510 and are not available for the register allocator.
512 Mach register is fixed 'cause it's only 10 bits wide for SH1.
513 It is 32 bits wide for SH2. */
515 #define FIXED_REGISTERS \
516 { 0, 0, 0, 0, \
517 0, 0, 0, 0, \
518 0, 0, 0, 0, \
519 0, 0, 0, 1, \
520 1, 1, 1, 1, \
521 1, 1, 0, 1, \
522 0, 0, 0, 0, \
523 0, 0, 0, 0, \
524 0, 0, 0, 0, \
525 0, 0, 0, 0, \
526 0, 0, 0, 0, \
527 0, 0, 0, 0, \
528 1, \
529 }
531 /* 1 for registers not available across function calls.
532 These must include the FIXED_REGISTERS and also any
533 registers that can be used without being saved.
534 The latter must include the registers where values are returned
535 and the register where structure-value addresses are passed.
536 Aside from that, you can include as many other registers as you like. */
538 #define CALL_USED_REGISTERS \
539 { 1, 1, 1, 1, \
540 1, 1, 1, 1, \
541 0, 0, 0, 0, \
542 0, 0, 0, 1, \
543 1, 0, 1, 1, \
544 1, 1, 1, 1, \
545 1, 1, 1, 1, \
546 1, 1, 1, 1, \
547 1, 1, 1, 1, \
548 0, 0, 0, 0, \
549 1, 1, 1, 1, \
550 1, 1, 0, 0, \
551 1, \
552 }
554 /* Return number of consecutive hard regs needed starting at reg REGNO
555 to hold something of mode MODE.
556 This is ordinarily the length in words of a value of mode MODE
557 but can be less for certain modes in special long registers.
559 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
561 #define HARD_REGNO_NREGS(REGNO, MODE) \
562 (XD_REGISTER_P (REGNO) \
563 ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
564 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
566 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
567 We can allow any mode in any general register. The special registers
568 only allow SImode. Don't allow any mode in the PR. */
570 /* We cannot hold DCmode values in the XD registers because alter_reg
571 handles subregs of them incorrectly. We could work around this by
572 spacing the XD registers like the DR registers, but this would require
573 additional memory in every compilation to hold larger register vectors.
574 We could hold SFmode / SCmode values in XD registers, but that
575 would require a tertiary reload when reloading from / to memory,
576 and a secondary reload to reload from / to general regs; that
577 seems to be a loosing proposition. */
578 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
579 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
580 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
581 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
582 ? 1 \
583 : FP_REGISTER_P (REGNO) \
584 ? ((MODE) == SFmode \
585 || (TARGET_SH3E && (MODE) == SCmode) \
586 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode) \
587 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
588 : XD_REGISTER_P (REGNO) \
589 ? (MODE) == DFmode \
590 : (REGNO) == PR_REG ? 0 \
591 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
592 : 1)
594 /* Value is 1 if it is a good idea to tie two pseudo registers
595 when one has mode MODE1 and one has mode MODE2.
596 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
597 for any hard reg, then this must be 0 for correct output.
598 That's the case for xd registers: we don't hold SFmode values in
599 them, so we can't tie an SFmode pseudos with one in another
600 floating-point mode. */
602 #define MODES_TIEABLE_P(MODE1, MODE2) \
603 ((MODE1) == (MODE2) \
604 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
605 && (MODE1) != SFmode && (MODE2) != SFmode))
607 /* Specify the registers used for certain standard purposes.
608 The values of these macros are register numbers. */
610 /* Define this if the program counter is overloaded on a register. */
611 /* #define PC_REGNUM 15*/
613 /* Register to use for pushing function arguments. */
614 #define STACK_POINTER_REGNUM SP_REG
616 /* Base register for access to local variables of the function. */
617 #define FRAME_POINTER_REGNUM FP_REG
619 /* Fake register that holds the address on the stack of the
620 current function's return address. */
621 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
623 /* Register to hold the addressing base for position independent
624 code access to data items. */
625 #define PIC_OFFSET_TABLE_REGNUM PIC_REG
629 /* Value should be nonzero if functions must have frame pointers.
630 Zero means the frame pointer need not be set up (and parms may be accessed
631 via the stack pointer) in functions that seem suitable. */
633 #define FRAME_POINTER_REQUIRED 0
635 /* Definitions for register eliminations.
637 We have three registers that can be eliminated on the SH. First, the
638 frame pointer register can often be eliminated in favor of the stack
639 pointer register. Secondly, the argument pointer register can always be
640 eliminated; it is replaced with either the stack or frame pointer.
641 Third, there is the return address pointer, which can also be replaced
642 with either the stack or the frame pointer. */
644 /* This is an array of structures. Each structure initializes one pair
645 of eliminable registers. The "from" register number is given first,
646 followed by "to". Eliminations of the same "from" register are listed
647 in order of preference. */
649 /* If you add any registers here that are not actually hard registers,
650 and that have any alternative of elimination that doesn't always
651 apply, you need to amend calc_live_regs to exclude it, because
652 reload spills all eliminable registers where it sees an
653 can_eliminate == 0 entry, thus making them 'live' .
654 If you add any hard registers that can be eliminated in different
655 ways, you have to patch reload to spill them only when all alternatives
656 of elimination fail. */
658 #define ELIMINABLE_REGS \
659 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
660 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
661 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
662 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
663 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
665 /* Given FROM and TO register numbers, say whether this elimination
666 is allowed. */
667 #define CAN_ELIMINATE(FROM, TO) \
668 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
670 /* Define the offset between two registers, one to be eliminated, and the other
671 its replacement, at the start of a routine. */
673 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
674 OFFSET = initial_elimination_offset ((FROM), (TO))
676 /* Base register for access to arguments of the function. */
677 #define ARG_POINTER_REGNUM AP_REG
679 /* Register in which the static-chain is passed to a function. */
680 #define STATIC_CHAIN_REGNUM 3
682 /* The register in which a struct value address is passed. */
684 #define STRUCT_VALUE_REGNUM 2
686 /* If the structure value address is not passed in a register, define
687 `STRUCT_VALUE' as an expression returning an RTX for the place
688 where the address is passed. If it returns 0, the address is
689 passed as an "invisible" first argument. */
691 /* The Hitachi calling convention doesn't quite fit into this scheme since
692 the address is passed like an invisible argument, but one that is always
693 passed in memory. */
694 #define STRUCT_VALUE \
695 (TARGET_HITACHI ? 0 : gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM))
697 #define RETURN_IN_MEMORY(TYPE) \
698 (TYPE_MODE (TYPE) == BLKmode \
699 || TARGET_HITACHI && TREE_CODE (TYPE) == RECORD_TYPE)
701 /* Don't default to pcc-struct-return, because we have already specified
702 exactly how to return structures in the RETURN_IN_MEMORY macro. */
704 #define DEFAULT_PCC_STRUCT_RETURN 0
705 \f
706 /* Define the classes of registers for register constraints in the
707 machine description. Also define ranges of constants.
709 One of the classes must always be named ALL_REGS and include all hard regs.
710 If there is more than one class, another class must be named NO_REGS
711 and contain no registers.
713 The name GENERAL_REGS must be the name of a class (or an alias for
714 another name such as ALL_REGS). This is the class of registers
715 that is allowed by "g" or "r" in a register constraint.
716 Also, registers outside this class are allocated only when
717 instructions express preferences for them.
719 The classes must be numbered in nondecreasing order; that is,
720 a larger-numbered class must never be contained completely
721 in a smaller-numbered class.
723 For any two classes, it is very desirable that there be another
724 class that represents their union. */
726 /* The SH has two sorts of general registers, R0 and the rest. R0 can
727 be used as the destination of some of the arithmetic ops. There are
728 also some special purpose registers; the T bit register, the
729 Procedure Return Register and the Multiply Accumulate Registers. */
730 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
731 reg_class_subunion. We don't want to have an actual union class
732 of these, because it would only be used when both classes are calculated
733 to give the same cost, but there is only one FPUL register.
734 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
735 applying to the actual instruction alternative considered. E.g., the
736 y/r alternative of movsi_ie is considered to have no more cost that
737 the r/r alternative, which is patently untrue. */
739 enum reg_class
740 {
741 NO_REGS,
742 R0_REGS,
743 PR_REGS,
744 T_REGS,
745 MAC_REGS,
746 FPUL_REGS,
747 SIBCALL_REGS,
748 GENERAL_REGS,
749 FP0_REGS,
750 FP_REGS,
751 DF_REGS,
752 FPSCR_REGS,
753 GENERAL_FP_REGS,
754 ALL_REGS,
755 LIM_REG_CLASSES
756 };
758 #define N_REG_CLASSES (int) LIM_REG_CLASSES
760 /* Give names of register classes as strings for dump file. */
761 #define REG_CLASS_NAMES \
762 { \
777 }
779 /* Define which registers fit in which classes.
780 This is an initializer for a vector of HARD_REG_SET
781 of length N_REG_CLASSES. */
783 #define REG_CLASS_CONTENTS \
784 { \
800 }
802 /* The same information, inverted:
803 Return the class number of the smallest class containing
804 reg number REGNO. This could be a conditional expression
805 or could index an array. */
808 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
810 /* When defined, the compiler allows registers explicitly used in the
811 rtl to be used as spill registers but prevents the compiler from
812 extending the lifetime of these registers. */
814 #define SMALL_REGISTER_CLASSES 1
816 /* The order in which register should be allocated. */
817 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
818 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
819 spilled or used otherwise, we better have the FP_REGS allocated first. */
820 #define REG_ALLOC_ORDER \
821 { 25,26,27,28,29,30,31,24,32,33,34,35,36,37,38,39, \
822 40,41,42,43,44,45,46,47,48, \
823 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14, \
824 22,15,16,17,18,19,20,21,23 }
826 /* The class value for index registers, and the one for base regs. */
827 #define INDEX_REG_CLASS R0_REGS
828 #define BASE_REG_CLASS GENERAL_REGS
830 /* Get reg_class from a letter such as appears in the machine
831 description. */
834 #define REG_CLASS_FROM_LETTER(C) \
836 \f
837 /* The letters I, J, K, L and M in a register constraint string
838 can be used to stand for particular ranges of immediate operands.
839 This macro defines what the ranges are.
840 C is the letter, and VALUE is a constant value.
841 Return 1 if VALUE is in the range specified by C.
842 I: arithmetic operand -127..128, as used in add, sub, etc
843 K: shift operand 1,2,8 or 16
844 L: logical operand 0..255, as used in and, or, etc.
845 M: constant 1
846 N: constant 0 */
848 #define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
849 && ((HOST_WIDE_INT)(VALUE)) <= 127)
850 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
851 #define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
852 && ((HOST_WIDE_INT)(VALUE)) <= 255)
853 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
854 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
855 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
861 : 0)
863 /* Similar, but for floating constants, and defining letters G and H.
864 Here VALUE is the CONST_DOUBLE rtx itself. */
866 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
871 /* Given an rtx X being reloaded into a reg required to be
872 in class CLASS, return the class of reg to actually use.
873 In general this is just CLASS; but on some machines
874 in some cases it is preferable to use a more restrictive class. */
876 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
878 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
879 ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \
880 || (CLASS) == DF_REGS) \
881 && (GET_CODE (X) == REG && GENERAL_OR_AP_REGISTER_P (REGNO (X)))) \
882 || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \
883 && GET_CODE (X) == REG \
884 && FP_REGISTER_P (REGNO (X)))) \
885 && MODE == SFmode) \
886 ? FPUL_REGS \
887 : ((CLASS) == FPUL_REGS \
888 && (GET_CODE (X) == MEM \
889 || (GET_CODE (X) == REG \
890 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
891 || REGNO (X) == T_REG \
892 || system_reg_operand (X, VOIDmode))))) \
893 ? GENERAL_REGS \
894 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
895 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
896 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
897 ? GENERAL_REGS : NO_REGS)
899 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
900 ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS) \
901 && immediate_operand ((X), (MODE)) \
902 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
903 && (MODE) == SFmode && fldi_ok ())) \
904 ? R0_REGS \
905 : (CLASS == FPUL_REGS \
906 && ((GET_CODE (X) == REG \
907 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
908 || REGNO (X) == T_REG)))) \
909 ? GENERAL_REGS \
910 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
911 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \
912 ? GENERAL_REGS \
913 : R0_REGS) \
914 : (CLASS == FPSCR_REGS \
915 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
916 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
917 ? GENERAL_REGS \
918 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
920 /* Return the maximum number of consecutive registers
921 needed to represent mode MODE in a register of class CLASS.
923 On SH this is the size of MODE in words. */
924 #define CLASS_MAX_NREGS(CLASS, MODE) \
925 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
927 /* If defined, gives a class of registers that cannot be used as the
928 operand of a SUBREG that changes the mode of the object illegally. */
930 #define CLASS_CANNOT_CHANGE_MODE DF_REGS
932 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
934 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
935 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
936 \f
937 /* Stack layout; function entry, exit and calling. */
939 /* Define the number of registers that can hold parameters.
940 These macros are used only in other macro definitions below. */
942 #define NPARM_REGS(MODE) \
943 (TARGET_SH3E && (MODE) == SFmode \
944 ? 8 \
945 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
946 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
947 ? 8 \
948 : 4)
950 #define FIRST_PARM_REG (FIRST_GENERAL_REG + 4)
951 #define FIRST_RET_REG FIRST_GENERAL_REG
953 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
954 #define FIRST_FP_RET_REG FIRST_FP_REG
956 /* Define this if pushing a word on the stack
957 makes the stack pointer a smaller address. */
958 #define STACK_GROWS_DOWNWARD
960 /* Define this macro if the addresses of local variable slots are at
961 negative offsets from the frame pointer.
963 The SH only has positive indexes, so grow the frame up. */
964 /* #define FRAME_GROWS_DOWNWARD */
966 /* Offset from the frame pointer to the first local variable slot to
967 be allocated. */
968 #define STARTING_FRAME_OFFSET 0
970 /* If we generate an insn to push BYTES bytes,
971 this says how many the stack pointer really advances by. */
972 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
973 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
974 do correct alignment. */
975 #if 0
976 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
977 #endif
979 /* Offset of first parameter from the argument pointer register value. */
980 #define FIRST_PARM_OFFSET(FNDECL) 0
982 /* Value is the number of byte of arguments automatically
983 popped when returning from a subroutine call.
984 FUNDECL is the declaration node of the function (as a tree),
985 FUNTYPE is the data type of the function (as a tree),
986 or for a library call it is an identifier node for the subroutine name.
987 SIZE is the number of bytes of arguments passed on the stack.
989 On the SH, the caller does not pop any of its arguments that were passed
990 on the stack. */
991 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
993 /* Nonzero if we do not know how to pass TYPE solely in registers.
994 Values that come in registers with inconvenient padding are stored
995 to memory at the function start. */
997 #define MUST_PASS_IN_STACK(MODE,TYPE) \
998 ((TYPE) != 0 \
999 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1000 || TREE_ADDRESSABLE (TYPE)))
1001 /* Some subroutine macros specific to this machine. */
1003 #define BASE_RETURN_VALUE_REG(MODE) \
1004 ((TARGET_SH3E && ((MODE) == SFmode)) \
1005 ? FIRST_FP_RET_REG \
1006 : TARGET_SH3E && (MODE) == SCmode \
1007 ? FIRST_FP_RET_REG \
1008 : (TARGET_SH4 \
1009 && ((MODE) == DFmode || (MODE) == SFmode \
1010 || (MODE) == DCmode || (MODE) == SCmode )) \
1011 ? FIRST_FP_RET_REG \
1012 : FIRST_RET_REG)
1014 #define BASE_ARG_REG(MODE) \
1015 ((TARGET_SH3E && ((MODE) == SFmode)) \
1016 ? FIRST_FP_PARM_REG \
1017 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1018 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1019 ? FIRST_FP_PARM_REG \
1020 : FIRST_PARM_REG)
1022 /* Define how to find the value returned by a function.
1023 VALTYPE is the data type of the value (as a tree).
1024 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1025 otherwise, FUNC is 0.
1026 For the SH, this is like LIBCALL_VALUE, except that we must change the
1027 mode like PROMOTE_MODE does.
1028 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1029 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1031 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1032 gen_rtx (REG, \
1033 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1034 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1035 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1036 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1037 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1038 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1039 || TREE_CODE (VALTYPE) == REAL_TYPE \
1040 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1041 ? SImode : TYPE_MODE (VALTYPE)), \
1042 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1044 /* Define how to find the value returned by a library function
1045 assuming the value has mode MODE. */
1046 #define LIBCALL_VALUE(MODE) \
1047 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1049 /* 1 if N is a possible register number for a function value. */
1050 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1051 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG))
1053 /* 1 if N is a possible register number for function argument passing. */
1054 #define FUNCTION_ARG_REGNO_P(REGNO) \
1055 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4)) \
1056 || (TARGET_SH3E \
1057 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8)))
1058 \f
1059 /* Define a data type for recording info about an argument list
1060 during the scan of that argument list. This data type should
1061 hold all necessary information about the function itself
1062 and about the args processed so far, enough to enable macros
1063 such as FUNCTION_ARG to determine where the next arg should go.
1065 On SH, this is a single integer, which is a number of words
1066 of arguments scanned so far (including the invisible argument,
1067 if any, which holds the structure-value-address).
1068 Thus NARGREGS or more means all following args should go on the stack. */
1074 };
1076 #define CUMULATIVE_ARGS struct sh_args
1078 #define GET_SH_ARG_CLASS(MODE) \
1079 ((TARGET_SH3E && (MODE) == SFmode) \
1080 ? SH_ARG_FLOAT \
1081 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1082 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1083 ? SH_ARG_FLOAT : SH_ARG_INT)
1085 #define ROUND_ADVANCE(SIZE) \
1086 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1088 /* Round a register number up to a proper boundary for an arg of mode
1089 MODE.
1091 The SH doesn't care about double alignment, so we only
1092 round doubles to even regs when asked to explicitly. */
1094 #define ROUND_REG(CUM, MODE) \
1095 (((TARGET_ALIGN_DOUBLE \
1096 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1097 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1098 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1099 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1100 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1101 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1103 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1104 for a call to a function whose data type is FNTYPE.
1105 For a library call, FNTYPE is 0.
1107 On SH, the offset always starts at 0: the first parm reg is always
1108 the same reg for a given argument class.
1110 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1112 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1113 do { \
1114 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1115 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1116 (CUM).force_mem \
1117 = (TARGET_HITACHI && FNTYPE \
1118 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1119 } while (0)
1121 /* Update the data in CUM to advance over an argument
1122 of mode MODE and data type TYPE.
1123 (TYPE is null for libcalls where that information may not be
1124 available.) */
1126 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1127 if ((CUM).force_mem) \
1128 (CUM).force_mem = 0; \
1129 else if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
1130 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1131 = (ROUND_REG ((CUM), (MODE)) \
1132 + ((MODE) == BLKmode \
1133 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1134 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
1136 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1137 This macro is only used in this file. */
1139 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1140 (((TYPE) == 0 \
1141 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1142 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
1143 && ! (CUM).force_mem \
1144 && (TARGET_SH3E \
1145 ? ((MODE) == BLKmode \
1146 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1147 + int_size_in_bytes (TYPE)) \
1148 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1149 : ((ROUND_REG((CUM), (MODE)) \
1150 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1151 <= NPARM_REGS (MODE))) \
1152 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1154 /* Define where to put the arguments to a function.
1155 Value is zero to push the argument on the stack,
1156 or a hard register in which to store the argument.
1158 MODE is the argument's machine mode.
1159 TYPE is the data type of the argument (as a tree).
1160 This is null for libcalls where that information may
1161 not be available.
1162 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1163 the preceding args and about the function being called.
1164 NAMED is nonzero if this argument is a named parameter
1165 (otherwise it is an extra parameter matching an ellipsis).
1167 On SH the first args are normally in registers
1168 and the rest are pushed. Any arg that starts within the first
1169 NPARM_REGS words is at least partially passed in a register unless
1170 its data type forbids. */
1172 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1173 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1174 && ((NAMED) \
1175 || (! TARGET_HITACHI && (TARGET_SH3E || ! current_function_varargs)))) \
1176 ? gen_rtx_REG ((MODE), \
1177 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
1178 ^ ((MODE) == SFmode && TARGET_SH4 \
1179 && TARGET_LITTLE_ENDIAN != 0))) \
1180 : 0)
1182 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI)
1184 /* For an arg passed partly in registers and partly in memory,
1185 this is the number of registers used.
1186 For args passed entirely in registers or entirely in memory, zero.
1188 We sometimes split args. */
1190 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1191 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1192 && ! TARGET_SH4 \
1193 && (ROUND_REG ((CUM), (MODE)) \
1194 + ((MODE) != BLKmode \
1195 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
1196 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
1197 > NPARM_REGS (MODE))) \
1198 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
1199 : 0)
1203 /* Perform any needed actions needed for a function that is receiving a
1204 variable number of arguments. */
1206 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
1207 current_function_anonymous_args = 1;
1209 /* Define the `__builtin_va_list' type for the ABI. */
1210 #define BUILD_VA_LIST_TYPE(VALIST) \
1211 (VALIST) = sh_build_va_list ()
1213 /* Implement `va_start' for varargs and stdarg. */
1214 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1215 sh_va_start (stdarg, valist, nextarg)
1217 /* Implement `va_arg'. */
1218 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1219 sh_va_arg (valist, type)
1221 /* Call the function profiler with a given profile label.
1222 We use two .aligns, so as to make sure that both the .long is aligned
1223 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1224 from the trapa instruction. */
1226 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1227 { \
1232 }
1234 /* Define this macro if the code for function profiling should come
1235 before the function prologue. Normally, the profiling code comes
1236 after. */
1238 #define PROFILE_BEFORE_PROLOGUE
1240 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1241 the stack pointer does not matter. The value is tested only in
1242 functions that have frame pointers.
1243 No definition is equivalent to always zero. */
1245 #define EXIT_IGNORE_STACK 1
1247 /*
1248 On the SH, the trampoline looks like
1249 2 0002 D202 mov.l l2,r2
1250 1 0000 D301 mov.l l1,r3
1251 3 0004 422B jmp @r2
1252 4 0006 0009 nop
1253 5 0008 00000000 l1: .long area
1254 6 000c 00000000 l2: .long function */
1256 /* Length in units of the trampoline for entering a nested function. */
1257 #define TRAMPOLINE_SIZE 16
1259 /* Alignment required for a trampoline in bits . */
1260 #define TRAMPOLINE_ALIGNMENT \
1261 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 : 64)
1263 /* Emit RTL insns to initialize the variable parts of a trampoline.
1264 FNADDR is an RTX for the address of the function's pure code.
1265 CXT is an RTX for the static chain value for the function. */
1267 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) do \
1268 { \
1269 emit_move_insn (gen_rtx_MEM (SImode, (TRAMP)), \
1270 GEN_INT (trunc_int_for_mode \
1271 (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,\
1272 SImode))); \
1273 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 4)), \
1274 GEN_INT (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009));\
1275 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1276 (CXT)); \
1277 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1278 (FNADDR)); \
1279 if (TARGET_HARVARD) \
1280 { \
1281 if (TARGET_USERMODE) \
1283 0, VOIDmode, 1, (TRAMP), SImode); \
1284 else \
1285 emit_insn (gen_ic_invalidate_line (TRAMP)); \
1286 } \
1287 } while (0)
1289 /* A C expression whose value is RTL representing the value of the return
1290 address for the frame COUNT steps up from the current frame.
1291 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1292 can ignore COUNT. */
1294 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1295 (((COUNT) == 0) \
1296 ? get_hard_reg_initial_val (Pmode, PR_REG) \
1297 : (rtx) 0)
1298 \f
1299 /* Generate necessary RTL for __builtin_saveregs(). */
1300 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
1301 \f
1302 /* Addressing modes, and classification of registers for them. */
1303 #define HAVE_POST_INCREMENT 1
1304 /*#define HAVE_PRE_INCREMENT 1*/
1305 /*#define HAVE_POST_DECREMENT 1*/
1306 #define HAVE_PRE_DECREMENT 1
1308 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1309 ? 0 : 1)
1310 #define USE_LOAD_PRE_DECREMENT(mode) 0
1311 #define USE_STORE_POST_INCREMENT(mode) 0
1312 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1313 ? 0 : 1)
1315 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
1316 < (TARGET_SMALLCODE ? 2 : \
1317 ((ALIGN >= 32) ? 16 : 2)))
1319 /* Macros to check register numbers against specific register classes. */
1321 /* These assume that REGNO is a hard or pseudo reg number.
1322 They give nonzero only if REGNO is a hard reg of the suitable class
1323 or a pseudo reg currently allocated to a suitable hard reg.
1324 Since they use reg_renumber, they are safe only once reg_renumber
1325 has been allocated, which happens in local-alloc.c. */
1327 #define REGNO_OK_FOR_BASE_P(REGNO) \
1328 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1329 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1330 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1331 ((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1333 /* Maximum number of registers that can appear in a valid memory
1334 address. */
1336 #define MAX_REGS_PER_ADDRESS 2
1338 /* Recognize any constant value that is a valid address. */
1340 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1342 /* Nonzero if the constant value X is a legitimate general operand. */
1344 #define LEGITIMATE_CONSTANT_P(X) \
1345 (GET_CODE (X) != CONST_DOUBLE \
1346 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
1347 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X))))
1349 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1350 and check its validity for a certain class.
1351 We have two alternate definitions for each of them.
1352 The usual definition accepts all pseudo regs; the other rejects
1353 them unless they have been allocated suitable hard regs.
1354 The symbol REG_OK_STRICT causes the latter definition to be used. */
1356 #ifndef REG_OK_STRICT
1358 /* Nonzero if X is a hard reg that can be used as a base reg
1359 or if it is a pseudo reg. */
1360 #define REG_OK_FOR_BASE_P(X) \
1361 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1363 /* Nonzero if X is a hard reg that can be used as an index
1364 or if it is a pseudo reg. */
1365 #define REG_OK_FOR_INDEX_P(X) \
1366 (REGNO (X) == R0_REG || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1368 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
1369 or if X is a pseudo reg. */
1370 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
1371 ((REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1373 #else
1375 /* Nonzero if X is a hard reg that can be used as a base reg. */
1376 #define REG_OK_FOR_BASE_P(X) \
1377 REGNO_OK_FOR_BASE_P (REGNO (X))
1379 /* Nonzero if X is a hard reg that can be used as an index. */
1380 #define REG_OK_FOR_INDEX_P(X) \
1381 REGNO_OK_FOR_INDEX_P (REGNO (X))
1383 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
1384 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
1385 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
1387 #endif
1389 /* The 'Q' constraint is a pc relative load operand. */
1390 #define EXTRA_CONSTRAINT_Q(OP) \
1391 (GET_CODE (OP) == MEM \
1392 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
1393 || (GET_CODE (XEXP ((OP), 0)) == CONST \
1394 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
1395 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
1396 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
1398 #define EXTRA_CONSTRAINT(OP, C) \
1400 : 0)
1401 \f
1402 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1403 that is a valid memory address for an instruction.
1404 The MODE argument is the machine mode for the MEM expression
1405 that wants to use this address. */
1407 #define MODE_DISP_OK_4(X,MODE) \
1408 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
1409 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
1411 #define MODE_DISP_OK_8(X,MODE) \
1412 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
1413 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
1415 #define BASE_REGISTER_RTX_P(X) \
1416 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1417 || (GET_CODE (X) == SUBREG \
1418 && GET_CODE (SUBREG_REG (X)) == REG \
1419 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1421 /* Since this must be r0, which is a single register class, we must check
1422 SUBREGs more carefully, to be sure that we don't accept one that extends
1423 outside the class. */
1424 #define INDEX_REGISTER_RTX_P(X) \
1425 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1426 || (GET_CODE (X) == SUBREG \
1427 && GET_CODE (SUBREG_REG (X)) == REG \
1428 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
1430 /* Jump to LABEL if X is a valid address RTX. This must also take
1431 REG_OK_STRICT into account when deciding about valid registers, but it uses
1432 the above macros so we are in luck.
1434 Allow REG
1435 REG+disp
1436 REG+r0
1437 REG++
1438 --REG */
1440 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
1441 into the FRx registers. We implement this by setting the maximum offset
1442 to zero when the value is SFmode. This also restricts loading of SFmode
1443 values into the integer registers, but that can't be helped. */
1445 /* The SH allows a displacement in a QI or HI amode, but only when the
1446 other operand is R0. GCC doesn't handle this very well, so we forgo
1447 all of that.
1449 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
1450 DI can be any number 0..60. */
1452 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
1453 do { \
1454 if (GET_CODE (OP) == CONST_INT) \
1455 { \
1456 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
1457 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
1458 } \
1459 } while(0)
1461 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1462 { \
1463 if (BASE_REGISTER_RTX_P (X)) \
1464 goto LABEL; \
1465 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1466 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
1467 goto LABEL; \
1468 else if (GET_CODE (X) == PLUS \
1469 && ((MODE) != PSImode || reload_completed)) \
1470 { \
1471 rtx xop0 = XEXP ((X), 0); \
1472 rtx xop1 = XEXP ((X), 1); \
1473 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
1474 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
1475 if (GET_MODE_SIZE (MODE) <= 4 \
1476 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
1477 { \
1478 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
1479 goto LABEL; \
1480 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
1481 goto LABEL; \
1482 } \
1483 } \
1484 }
1485 \f
1486 /* Try machine-dependent ways of modifying an illegitimate address
1487 to be legitimate. If we find one, return the new, valid address.
1488 This macro is used in only one place: `memory_address' in explow.c.
1490 OLDX is the address as it was before break_out_memory_refs was called.
1491 In some cases it is useful to look at this to decide what needs to be done.
1493 MODE and WIN are passed so that this macro can use
1494 GO_IF_LEGITIMATE_ADDRESS.
1496 It is always safe for this macro to do nothing. It exists to recognize
1497 opportunities to optimize the output.
1499 For the SH, if X is almost suitable for indexing, but the offset is
1500 out of range, convert it into a normal form so that cse has a chance
1501 of reducing the number of address registers used. */
1503 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1504 { \
1505 if (flag_pic) \
1506 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1507 if (GET_CODE (X) == PLUS \
1508 && (GET_MODE_SIZE (MODE) == 4 \
1509 || GET_MODE_SIZE (MODE) == 8) \
1510 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
1511 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
1512 && ! (TARGET_SH4 && (MODE) == DFmode) \
1513 && ! (TARGET_SH3E && (MODE) == SFmode)) \
1514 { \
1515 rtx index_rtx = XEXP ((X), 1); \
1516 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
1517 rtx sum; \
1518 \
1519 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
1520 /* On rare occasions, we might get an unaligned pointer \
1521 that is indexed in a way to give an aligned address. \
1523 /* Instead of offset_base 128..131 use 124..127, so that \
1525 if (offset > 127) \
1526 { \
1527 offset_base = ((offset + 4) & ~60) - 4; \
1528 } \
1529 else \
1530 offset_base = offset & ~60; \
1531 /* Sometimes the normal form does not suit DImode. We \
1532 could avoid that by using smaller ranges, but that \
1533 would give less optimized code when SImode is \
1535 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
1536 { \
1537 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
1538 GEN_INT (offset_base), NULL_RTX, 0, \
1539 OPTAB_LIB_WIDEN); \
1540 \
1541 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
1542 goto WIN; \
1543 } \
1544 } \
1545 }
1547 /* A C compound statement that attempts to replace X, which is an address
1548 that needs reloading, with a valid memory address for an operand of
1549 mode MODE. WIN is a C statement label elsewhere in the code.
1551 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
1552 of the address. That will allow inheritance of the address reloads. */
1554 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1555 { \
1556 if (GET_CODE (X) == PLUS \
1557 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
1558 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1559 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1560 && ! (TARGET_SH4 && (MODE) == DFmode) \
1561 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
1562 { \
1563 rtx index_rtx = XEXP (X, 1); \
1564 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
1565 rtx sum; \
1566 \
1567 if (TARGET_SH3E && MODE == SFmode) \
1568 { \
1569 X = copy_rtx (X); \
1570 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
1571 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
1572 (TYPE)); \
1573 goto WIN; \
1574 } \
1575 /* Instead of offset_base 128..131 use 124..127, so that \
1577 if (offset > 127) \
1578 { \
1579 offset_base = ((offset + 4) & ~60) - 4; \
1580 } \
1581 else \
1582 offset_base = offset & ~60; \
1583 /* Sometimes the normal form does not suit DImode. We \
1584 could avoid that by using smaller ranges, but that \
1585 would give less optimized code when SImode is \
1587 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
1588 { \
1589 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1590 GEN_INT (offset_base)); \
1591 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
1592 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
1593 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
1594 (TYPE)); \
1595 goto WIN; \
1596 } \
1597 } \
1599 else if (GET_CODE (X) == PLUS \
1600 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
1601 && GET_CODE (XEXP (X, 0)) == PLUS \
1602 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1603 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
1604 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1605 && ! (TARGET_SH3E && MODE == SFmode)) \
1606 { \
1607 /* Because this address is so complex, we know it must have \
1608 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
1610 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
1611 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
1612 goto WIN; \
1613 } \
1614 }
1616 /* Go to LABEL if ADDR (a legitimate address expression)
1617 has an effect that depends on the machine mode it is used for.
1619 ??? Strictly speaking, we should also include all indexed addressing,
1620 because the index scale factor is the length of the operand.
1621 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
1622 high if we did that. So we rely on reload to fix things up. */
1624 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1625 { \
1626 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
1627 goto LABEL; \
1628 }
1629 \f
1630 /* Specify the machine mode that this machine uses
1631 for the index in the tablejump instruction. */
1632 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
1634 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1635 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1636 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1637 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1638 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1639 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1640 : SImode)
1642 /* Define as C expression which evaluates to nonzero if the tablejump
1643 instruction expects the table to contain offsets from the address of the
1644 table.
1645 Do not define this if the table should contain absolute addresses. */
1646 #define CASE_VECTOR_PC_RELATIVE 1
1648 /* Specify the tree operation to be used to convert reals to integers. */
1649 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1651 /* This is the kind of divide that is easiest to do in the general case. */
1652 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1654 /* Since the SH3e has only `float' support, it is desirable to make all
1655 floating point types equivalent to `float'. */
1656 #define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64)
1658 /* 'char' is signed by default. */
1659 #define DEFAULT_SIGNED_CHAR 1
1661 /* The type of size_t unsigned int. */
1665 #define WCHAR_TYPE_SIZE 16
1667 /* Don't cse the address of the function being compiled. */
1668 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
1670 /* Max number of bytes we can move from memory to memory
1671 in one reasonably fast instruction. */
1672 #define MOVE_MAX 4
1674 /* Max number of bytes we want move_by_pieces to be able to copy
1675 efficiently. */
1676 #define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4)
1678 /* Define if operations between registers always perform the operation
1679 on the full register even if a narrower mode is specified. */
1680 #define WORD_REGISTER_OPERATIONS
1682 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1683 will either zero-extend or sign-extend. The value of this macro should
1684 be the code that says which one of the two operations is implicitly
1685 done, NIL if none. */
1686 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1688 /* Define if loading short immediate values into registers sign extends. */
1689 #define SHORT_IMMEDIATES_SIGN_EXTEND
1691 /* Define this if zero-extension is slow (more than one real instruction).
1692 On the SH, it's only one instruction. */
1693 /* #define SLOW_ZERO_EXTEND */
1695 /* Nonzero if access to memory by bytes is no faster than for words. */
1696 #define SLOW_BYTE_ACCESS 1
1698 /* We assume that the store-condition-codes instructions store 0 for false
1699 and some other value for true. This is the value stored for true. */
1701 #define STORE_FLAG_VALUE 1
1703 /* Immediate shift counts are truncated by the output routines (or was it
1704 the assembler?). Shift counts in a register are truncated by SH. Note
1705 that the native compiler puts too large (> 32) immediate shift counts
1706 into a register and shifts by the register, letting the SH decide what
1707 to do instead of doing that itself. */
1708 /* ??? The library routines in lib1funcs.asm truncate the shift count.
1709 However, the SH3 has hardware shifts that do not truncate exactly as gcc
1710 expects - the sign bit is significant - so it appears that we need to
1711 leave this zero for correct SH3 code. */
1712 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
1714 /* All integers have the same format so truncation is easy. */
1715 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1717 /* Define this if addresses of constant functions
1718 shouldn't be put through pseudo regs where they can be cse'd.
1719 Desirable on machines where ordinary constants are expensive
1720 but a CALL with constant address is cheap. */
1721 /*#define NO_FUNCTION_CSE 1*/
1723 /* Chars and shorts should be passed as ints. */
1724 #define PROMOTE_PROTOTYPES 1
1726 /* The machine modes of pointers and functions. */
1727 #define Pmode SImode
1728 #define FUNCTION_MODE Pmode
1730 /* The relative costs of various types of constants. */
1732 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1733 case CONST_INT: \
1734 if (CONST_OK_FOR_I (INTVAL (RTX))) \
1735 return 0; \
1736 else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \
1737 && CONST_OK_FOR_L (INTVAL (RTX))) \
1738 return 1; \
1739 else \
1740 return 8; \
1741 case CONST: \
1742 case LABEL_REF: \
1743 case SYMBOL_REF: \
1744 return 5; \
1745 case CONST_DOUBLE: \
1746 return 10;
1748 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1749 case PLUS: \
1750 return COSTS_N_INSNS (addsubcosts (X)); \
1751 case AND: \
1752 return COSTS_N_INSNS (andcosts (X)); \
1753 case MULT: \
1754 return COSTS_N_INSNS (multcosts (X)); \
1755 case ASHIFT: \
1756 case ASHIFTRT: \
1757 case LSHIFTRT: \
1758 return COSTS_N_INSNS (shiftcosts (X)); \
1759 case DIV: \
1760 case UDIV: \
1761 case MOD: \
1762 case UMOD: \
1763 return COSTS_N_INSNS (20); \
1764 case FLOAT: \
1765 case FIX: \
1766 return 100;
1768 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1769 are actually function calls with some special constraints on arguments
1770 and register usage.
1772 These macros tell reorg that the references to arguments and
1773 register clobbers for insns of type sfunc do not appear to happen
1774 until after the millicode call. This allows reorg to put insns
1775 which set the argument registers into the delay slot of the millicode
1776 call -- thus they act more like traditional CALL_INSNs.
1778 get_attr_is_sfunc will try to recognize the given insn, so make sure to
1779 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1780 in particular. */
1782 #define INSN_SETS_ARE_DELAYED(X) \
1783 ((GET_CODE (X) == INSN \
1784 && GET_CODE (PATTERN (X)) != SEQUENCE \
1785 && GET_CODE (PATTERN (X)) != USE \
1786 && GET_CODE (PATTERN (X)) != CLOBBER \
1787 && get_attr_is_sfunc (X)))
1789 #define INSN_REFERENCES_ARE_DELAYED(X) \
1790 ((GET_CODE (X) == INSN \
1791 && GET_CODE (PATTERN (X)) != SEQUENCE \
1792 && GET_CODE (PATTERN (X)) != USE \
1793 && GET_CODE (PATTERN (X)) != CLOBBER \
1794 && get_attr_is_sfunc (X)))
1796 \f
1797 /* Position Independent Code. */
1798 /* Define this macro if references to a symbol must be treated
1799 differently depending on something about the variable or function
1800 named by the symbol (such as what section it is in).
1802 On SH, if using PIC, mark a SYMBOL_REF for a non-global symbol
1803 so that we may access it using GOTOFF instead of GOT. */
1805 #define ENCODE_SECTION_INFO(DECL) \
1806 do \
1807 { \
1808 if (flag_pic) \
1809 { \
1811 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
1812 \
1813 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = \
1815 || ! TREE_PUBLIC (DECL)); \
1816 } \
1817 } \
1818 while (0)
1820 /* We can't directly access anything that contains a symbol,
1821 nor can we indirect via the constant pool. */
1822 #define LEGITIMATE_PIC_OPERAND_P(X) \
1823 (! nonpic_symbol_mentioned_p (X) \
1824 && (! CONSTANT_POOL_ADDRESS_P (X) \
1825 || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))
1827 #define SYMBOLIC_CONST_P(X) \
1828 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
1829 && nonpic_symbol_mentioned_p (X))
1830 \f
1831 /* Compute the cost of an address. For the SH, all valid addresses are
1832 the same cost. Use a slightly higher cost for reg + reg addressing,
1833 since it increases pressure on r0. */
1835 #define ADDRESS_COST(X) (GET_CODE (X) == PLUS && ! CONSTANT_P (XEXP (X, 1)) \
1836 ? 1 : 0)
1838 /* Compute extra cost of moving data between one register class
1839 and another. */
1841 /* Regclass always uses 2 for moves in the same register class;
1842 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
1843 it uses this information. Hence, the general register <-> floating point
1844 register information here is not used for SFmode. */
1845 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
1846 ((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
1847 : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS || (DSTCLASS) == DF_REGS) \
1848 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
1849 || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \
1850 && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
1851 || (SRCCLASS) == DF_REGS))) \
1852 ? TARGET_FMOVD ? 8 : 12 \
1853 : (((DSTCLASS) == FPUL_REGS \
1854 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
1855 || (SRCCLASS == FPUL_REGS \
1856 && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS))) \
1857 ? 5 \
1858 : (((DSTCLASS) == FPUL_REGS \
1859 && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS \
1860 || (SRCCLASS) == T_REGS)) \
1861 || ((SRCCLASS) == FPUL_REGS \
1862 && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \
1863 ? 7 \
1864 : 2)
1866 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1867 would be so that people with slow memory systems could generate
1868 different code that does fewer memory accesses. */
1870 /* A C expression for the cost of a branch instruction. A value of 1
1871 is the default; other values are interpreted relative to that.
1872 The SH1 does not have delay slots, hence we get a pipeline stall
1873 at every branch. The SH4 is superscalar, so the single delay slot
1874 is not sufficient to keep both pipelines filled. */
1875 #define BRANCH_COST (! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
1876 \f
1877 /* Assembler output control. */
1879 /* A C string constant describing how to begin a comment in the target
1880 assembler language. The compiler assumes that the comment will end at
1881 the end of the line. */
1884 /* The text to go at the start of the assembler file. */
1885 #define ASM_FILE_START(STREAM) \
1886 output_file_start (STREAM)
1888 #define ASM_FILE_END(STREAM)
1896 /* How to change between sections. */
1901 /* If defined, a C expression whose value is a string containing the
1902 assembler operation to identify the following data as
1903 uninitialized global data. If not defined, and neither
1904 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
1905 uninitialized global data will be output in the data section if
1906 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
1907 used. */
1908 #ifndef BSS_SECTION_ASM_OP
1910 #endif
1912 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
1913 separate, explicit argument. If you define this macro, it is used
1914 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
1915 handling the required alignment of the variable. The alignment is
1916 specified as the number of bits.
1918 Try to use function `asm_output_aligned_bss' defined in file
1919 `varasm.c' when defining this macro. */
1920 #ifndef ASM_OUTPUT_ALIGNED_BSS
1921 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1922 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1923 #endif
1925 /* Define this so that jump tables go in same section as the current function,
1926 which could be text or it could be a user defined section. */
1927 #define JUMP_TABLES_IN_TEXT_SECTION 1
1929 /* Switch into a generic section. */
1930 #define TARGET_ASM_NAMED_SECTION sh_asm_named_section
1932 #undef DO_GLOBAL_CTORS_BODY
1933 #define DO_GLOBAL_CTORS_BODY \
1934 { \
1935 typedef (*pfunc)(); \
1936 extern pfunc __ctors[]; \
1937 extern pfunc __ctors_end[]; \
1938 pfunc *p; \
1939 for (p = __ctors_end; p > __ctors; ) \
1940 { \
1941 (*--p)(); \
1942 } \
1943 }
1945 #undef DO_GLOBAL_DTORS_BODY
1946 #define DO_GLOBAL_DTORS_BODY \
1947 { \
1948 typedef (*pfunc)(); \
1949 extern pfunc __dtors[]; \
1950 extern pfunc __dtors_end[]; \
1951 pfunc *p; \
1952 for (p = __dtors; p < __dtors_end; p++) \
1953 { \
1954 (*p)(); \
1955 } \
1956 }
1958 #define ASM_OUTPUT_REG_PUSH(file, v) \
1961 #define ASM_OUTPUT_REG_POP(file, v) \
1964 /* The assembler's names for the registers. RFP need not always be used as
1965 the Real framepointer; it can also be used as a normal general register.
1966 Note that the name `fp' is horribly misleading since `fp' is in fact only
1967 the argument-and-return-context pointer. */
1971 #define REGISTER_NAMES \
1972 { \
1976 fp_reg_names[0], fp_reg_names[1] , fp_reg_names[2], fp_reg_names[3], \
1977 fp_reg_names[4], fp_reg_names[5], fp_reg_names[6], fp_reg_names[7], \
1978 fp_reg_names[8], fp_reg_names[9], fp_reg_names[10], fp_reg_names[11], \
1979 fp_reg_names[12], fp_reg_names[13], fp_reg_names[14], fp_reg_names[15], \
1980 fp_reg_names[17], fp_reg_names[18], fp_reg_names[19], fp_reg_names[20], \
1981 fp_reg_names[21], fp_reg_names[22], fp_reg_names[23], fp_reg_names[24], \
1983 }
1985 #define DEBUG_REGISTER_NAMES \
1986 { \
1994 }
1996 /* DBX register number for a given compiler register number. */
1997 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
1998 to match gdb. */
1999 #define DBX_REGISTER_NUMBER(REGNO) \
2000 (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO))
2002 /* Output a label definition. */
2003 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2006 /* This is how to output an assembler line
2007 that says to advance the location counter
2008 to a multiple of 2**LOG bytes. */
2010 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2011 if ((LOG) != 0) \
2014 /* Output a function label definition. */
2015 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
2016 ASM_OUTPUT_LABEL((STREAM), (NAME))
2018 /* Output a globalising directive for a label. */
2019 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
2021 assemble_name ((STREAM), (NAME)), \
2024 /* The prefix to add to user-visible assembler symbols. */
2028 /* The prefix to add to an internally generated label. */
2032 /* Make an internal label into a string. */
2033 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
2036 /* Output an internal label definition. */
2037 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2040 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2042 /* Construct a private name. */
2043 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
2044 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
2047 /* Output a relative address table. */
2049 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2050 switch (GET_MODE (BODY)) \
2051 { \
2052 case SImode: \
2054 break; \
2055 case HImode: \
2057 break; \
2058 case QImode: \
2060 break; \
2061 default: \
2062 break; \
2063 }
2065 /* Output an absolute table element. */
2067 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2068 if (TARGET_BIGTABLE) \
2070 else \
2073 /* Output various types of constants. */
2075 /* This is how to output an assembler line defining a `double'. */
2077 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2078 do { char dstr[30]; \
2081 } while (0)
2083 /* This is how to output an assembler line defining a `float' constant. */
2084 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2085 do { char dstr[30]; \
2088 } while (0)
2090 /* Loop alignment is now done in machine_dependent_reorg, so that
2091 branch shortening can know about it. */
2093 /* This is how to output an assembler line
2094 that says to advance the location counter by SIZE bytes. */
2096 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2099 /* This says how to output an assembler line
2100 to define a global common symbol. */
2102 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2104 assemble_name ((FILE), (NAME)), \
2107 /* This says how to output an assembler line
2108 to define a local common symbol. */
2110 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2112 assemble_name ((FILE), (NAME)), \
2114 \f
2115 /* A C statement to be executed just prior to the output of
2116 assembler code for INSN, to modify the extracted operands so
2117 they will be output differently.
2119 Here the argument OPVEC is the vector containing the operands
2120 extracted from INSN, and NOPERANDS is the number of elements of
2121 the vector which contain meaningful data for this insn.
2122 The contents of this vector are what will be used to convert the insn
2123 template into assembler code, so you can change the assembler output
2124 by changing the contents of the vector. */
2126 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2127 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2129 /* Print operand X (an rtx) in assembler syntax to file FILE.
2130 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2131 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2133 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
2135 /* Print a memory address as an operand to reference that memory location. */
2137 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
2139 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2143 /* Recognize machine-specific patterns that may appear within
2144 constants. Used for PIC-specific UNSPECs. */
2145 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2146 do \
2147 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
2148 { \
2149 switch (XINT ((X), 1)) \
2150 { \
2151 case UNSPEC_PIC: \
2153 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2154 break; \
2155 case UNSPEC_GOT: \
2156 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2158 break; \
2159 case UNSPEC_GOTOFF: \
2160 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2162 break; \
2163 case UNSPEC_PLT: \
2164 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2166 break; \
2167 case UNSPEC_CALLER: \
2168 { \
2169 char name[32]; \
2171 ASM_GENERATE_INTERNAL_LABEL \
2173 assemble_name ((STREAM), name); \
2174 } \
2175 break; \
2176 default: \
2177 goto FAIL; \
2178 } \
2179 break; \
2180 } \
2181 else \
2182 goto FAIL; \
2183 while (0)
2185 \f
2189 /* Which processor to schedule for. The elements of the enumeration must
2190 match exactly the cpu attribute in the sh.md file. */
2193 PROCESSOR_SH1,
2194 PROCESSOR_SH2,
2195 PROCESSOR_SH3,
2196 PROCESSOR_SH3E,
2197 PROCESSOR_SH4
2198 };
2200 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2205 enum mdep_reorg_phase_e
2206 {
2207 SH_BEFORE_MDEP_REORG,
2208 SH_INSERT_USES_LABELS,
2209 SH_SHORTEN_BRANCHES0,
2210 SH_FIXUP_PCLOAD,
2211 SH_SHORTEN_BRANCHES1,
2212 SH_AFTER_MDEP_REORG
2213 };
2217 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
2219 /* Generate calls to memcpy, memcmp and memset. */
2221 #define TARGET_MEM_FUNCTIONS
2223 /* Handle Hitachi compiler's pragmas. */
2224 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2228 } while (0)
2230 /* Set when processing a function with pragma interrupt turned on. */
2234 /* Set when processing a function with interrupt attribute. */
2238 /* Set to an RTX containing the address of the stack to switch to
2239 for interrupt functions. */
2245 \f
2246 /* Instructions with unfilled delay slots take up an
2247 extra two bytes for the nop in the delay slot.
2248 sh-dsp parallel processing insns are four bytes long. */
2250 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2251 (LENGTH) += sh_insn_length_adjustment (X);
2252 \f
2253 /* Define the codes that are matched by predicates in sh.c. */
2254 #define PREDICATE_CODES \
2270 /* Define this macro if it is advisable to hold scalars in registers
2271 in a wider mode than that declared by the program. In such cases,
2272 the value is constrained to be within the bounds of the declared
2273 type, but kept valid in the wider mode. The signedness of the
2274 extension may differ from that of the type.
2276 Leaving the unsignedp unchanged gives better code than always setting it
2277 to 0. This is despite the fact that we have only signed char and short
2278 load instructions. */
2279 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2280 if (GET_MODE_CLASS (MODE) == MODE_INT \
2281 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
2282 (MODE) = SImode;
2284 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
2285 extensions applied to char/short functions arguments. Defining
2286 PROMOTE_FUNCTION_RETURN does the same for function returns. */
2288 #define PROMOTE_FUNCTION_ARGS
2289 #define PROMOTE_FUNCTION_RETURN
2291 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
2292 and poping arguments. However, we do have push/pop instructions, and
2293 rather limited offsets (4 bits) in load/store instructions, so it isn't
2294 clear if this would give better code. If implemented, should check for
2295 compatibility problems. */
2297 #define SH_DYNAMIC_SHIFT_COST \
2298 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
2301 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2303 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
2305 #define NORMAL_MODE(ENTITY) \
2306 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2308 #define EPILOGUE_USES(REGNO) ((TARGET_SH3E || TARGET_SH4) \
2309 && (REGNO) == FPSCR_REG)
2311 #define MODE_NEEDED(ENTITY, INSN) \
2312 (recog_memoized (INSN) >= 0 \
2313 ? get_attr_fp_mode (INSN) \
2314 : FP_MODE_NONE)
2316 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2317 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2319 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2320 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2322 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
2323 sh_can_redirect_branch ((INSN), (SEQ))
2325 #define DWARF_LINE_MIN_INSTR_LENGTH 2
2327 /* SH constant pool breaks the devices in crtstuff.c to control section
2328 in where code resides. We have to write it as asm code. */
2329 #define CRT_CALL_STATIC_FUNCTION(func) \
2330 if (0) \
2332 func (); \
2333 else \
2334 /* We should be passing FUNC to the asm statement as an asm input \
2336 asm \
2345 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
2346 (REGNO (hard_reg) == PR_REG \
2347 ? (current_function_is_leaf && ! sh_pr_n_sets () \
2348 ? (hard_reg) \
2349 : gen_rtx_MEM (Pmode, arg_pointer_rtx)) \
2350 : NULL_RTX)