1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
33 #include "insn-attr.h"
40 #include "target-def.h"
43 /* Needed for use_return_insn. */
46 #ifdef SUPPORT_SUN_FPA
48 /* Index into this array by (register number >> 3) to find the
49 smallest class which contains that register. */
50 enum reg_class regno_reg_class
[]
51 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
52 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
54 #endif /* defined SUPPORT_SUN_FPA */
56 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
57 if SGS_SWITCH_TABLE. */
58 int switch_table_difference_label_flag
;
60 static rtx find_addr_reg
PARAMS ((rtx
));
61 static const char *singlemove_string
PARAMS ((rtx
*));
62 static void m68k_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
63 static void m68k_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
64 static void m68k_coff_asm_named_section
PARAMS ((const char *, unsigned int));
65 #ifdef CTOR_LIST_BEGIN
66 static void m68k_svr3_asm_out_constructor
PARAMS ((rtx
, int));
70 /* Alignment to use for loops and jumps */
71 /* Specify power of two alignment used for loops. */
72 const char *m68k_align_loops_string
;
73 /* Specify power of two alignment used for non-loop jumps. */
74 const char *m68k_align_jumps_string
;
75 /* Specify power of two alignment used for functions. */
76 const char *m68k_align_funcs_string
;
78 /* Specify power of two alignment used for loops. */
80 /* Specify power of two alignment used for non-loop jumps. */
82 /* Specify power of two alignment used for functions. */
85 /* Nonzero if the last compare/test insn had FP operands. The
86 sCC expanders peek at this to determine what to do for the
87 68060, which has no fsCC instructions. */
88 int m68k_last_compare_had_fp_operands
;
90 /* Initialize the GCC target structure. */
92 #if INT_OP_GROUP == INT_OP_DOT_WORD
93 #undef TARGET_ASM_ALIGNED_HI_OP
94 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
97 #if INT_OP_GROUP == INT_OP_NO_DOT
98 #undef TARGET_ASM_BYTE_OP
99 #define TARGET_ASM_BYTE_OP "\tbyte\t"
100 #undef TARGET_ASM_ALIGNED_HI_OP
101 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
102 #undef TARGET_ASM_ALIGNED_SI_OP
103 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
106 #if INT_OP_GROUP == INT_OP_DC
107 #undef TARGET_ASM_BYTE_OP
108 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
109 #undef TARGET_ASM_ALIGNED_HI_OP
110 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
111 #undef TARGET_ASM_ALIGNED_SI_OP
112 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
115 #undef TARGET_ASM_UNALIGNED_HI_OP
116 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
117 #undef TARGET_ASM_UNALIGNED_SI_OP
118 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
120 #undef TARGET_ASM_FUNCTION_PROLOGUE
121 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
122 #undef TARGET_ASM_FUNCTION_EPILOGUE
123 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
125 struct gcc_target targetm
= TARGET_INITIALIZER
;
127 /* Sometimes certain combinations of command options do not make
128 sense on a particular target machine. You can define a macro
129 `OVERRIDE_OPTIONS' to take account of this. This macro, if
130 defined, is executed once just after all the command options have
133 Don't use this macro to turn on various extra optimizations for
134 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
144 /* Validate -malign-loops= value, or provide default */
145 m68k_align_loops
= def_align
;
146 if (m68k_align_loops_string
)
148 i
= atoi (m68k_align_loops_string
);
149 if (i
< 1 || i
> MAX_CODE_ALIGN
)
150 error ("-malign-loops=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
152 m68k_align_loops
= i
;
155 /* Validate -malign-jumps= value, or provide default */
156 m68k_align_jumps
= def_align
;
157 if (m68k_align_jumps_string
)
159 i
= atoi (m68k_align_jumps_string
);
160 if (i
< 1 || i
> MAX_CODE_ALIGN
)
161 error ("-malign-jumps=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
163 m68k_align_jumps
= i
;
166 /* Validate -malign-functions= value, or provide default */
167 m68k_align_funcs
= def_align
;
168 if (m68k_align_funcs_string
)
170 i
= atoi (m68k_align_funcs_string
);
171 if (i
< 1 || i
> MAX_CODE_ALIGN
)
172 error ("-malign-functions=%d is not between 1 and %d",
175 m68k_align_funcs
= i
;
179 /* This function generates the assembly code for function entry.
180 STREAM is a stdio stream to output the code to.
181 SIZE is an int: how many units of temporary storage to allocate.
182 Refer to the array `regs_ever_live' to determine which registers
183 to save; `regs_ever_live[I]' is nonzero if register number I
184 is ever used in the function. This function is responsible for
185 knowing which registers should not be saved even if used. */
188 /* Note that the order of the bit mask for fmovem is the opposite
189 of the order for movem! */
194 m68k_output_function_prologue (stream
, size
)
199 register int mask
= 0;
200 extern char call_used_regs
[];
201 HOST_WIDE_INT fsize
= ((size
) + 3) & -4;
203 /* unos stack probe */
206 fprintf (stream
, "\tmovel sp,a0\n");
207 fprintf (stream
, "\taddl $-%d,a0\n", 2048 + fsize
);
208 fprintf (stream
, "\ttstb (a0)\n");
211 fprintf (stream
, "\ttstb -%d(sp)\n", 2048 + fsize
);
213 if (frame_pointer_needed
)
215 if (TARGET_68020
|| fsize
< 0x8000)
216 fprintf (stream
, "\tlink a6,$%d\n", -fsize
);
218 fprintf (stream
, "\tlink a6,$0\n\tsubl $%d,sp\n", fsize
);
222 /* Adding negative number is faster on the 68040. */
223 if (fsize
+ 4 < 0x8000)
224 fprintf (stream
, "\tadd.w #%d,sp\n", - (fsize
+ 4));
226 fprintf (stream
, "\tadd.l #%d,sp\n", - (fsize
+ 4));
229 for (regno
= 16; regno
< 24; regno
++)
230 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
231 mask
|= 1 << (regno
- 16);
233 if ((mask
& 0xff) != 0)
234 fprintf (stream
, "\tfmovem $0x%x,-(sp)\n", mask
& 0xff);
237 for (regno
= 0; regno
< 16; regno
++)
238 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
239 mask
|= 1 << (15 - regno
);
240 if (frame_pointer_needed
)
241 mask
&= ~ (1 << (15-FRAME_POINTER_REGNUM
));
243 if (exact_log2 (mask
) >= 0)
244 fprintf (stream
, "\tmovel %s,-(sp)\n", reg_names
[15 - exact_log2 (mask
)]);
246 fprintf (stream
, "\tmovem $0x%x,-(sp)\n", mask
);
250 #if defined (DPX2) && defined (MOTOROLA)
253 m68k_output_function_prologue (stream
, size
)
258 register int mask
= 0;
259 int num_saved_regs
= 0, first
= 1;
260 extern char call_used_regs
[];
261 HOST_WIDE_INT fsize
= ((size
) + 3) & -4;
263 if (frame_pointer_needed
)
265 /* Adding negative number is faster on the 68040. */
266 if (fsize
< 0x8000 && !TARGET_68040
)
267 fprintf (stream
, "\tlink %s,#%d\n",
268 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
269 else if (TARGET_68020
)
270 fprintf (stream
, "\tlink %s,#%d\n",
271 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
273 fprintf (stream
, "\tlink %s,#0\n\tadd.l #%d,sp\n",
274 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
278 /* Adding negative number is faster on the 68040. */
279 if (fsize
+ 4 < 0x8000)
280 fprintf (stream
, "\tadd.w #%d,sp\n", - (fsize
+ 4));
282 fprintf (stream
, "\tadd.l #%d,sp\n", - (fsize
+ 4));
285 for (regno
= 23; regno
>= 16; regno
--)
286 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
290 fprintf (stream
, "\tfmovem.x %s", reg_names
[regno
]);
294 fprintf (stream
, "/%s", reg_names
[regno
]);
297 fprintf (stream
, ",-(sp)\n");
300 for (regno
= 0; regno
< 16; regno
++)
301 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
303 mask
|= 1 << (15 - regno
);
307 if (frame_pointer_needed
)
309 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
313 if (num_saved_regs
<= 2)
315 /* Store each separately in the same order moveml uses.
316 Using two movel instructions instead of a single moveml
317 is about 15% faster for the 68020 and 68030 at no expense
322 /* Undo the work from above. */
323 for (i
= 0; i
< 16; i
++)
325 fprintf (stream
, "\tmove.l %s,-(sp)\n", reg_names
[15 - i
]);
330 for (regno
= 0; regno
< 16; regno
++)
331 if (mask
& (1 << regno
))
335 fprintf (stream
, "\tmovem.l %s", reg_names
[15 - regno
]);
339 fprintf (stream
, "/%s", reg_names
[15 - regno
]);
341 fprintf (stream
, ",-(sp)\n");
344 if (flag_pic
&& current_function_uses_pic_offset_table
)
346 fprintf (stream
, "\tmove.l #__GLOBAL_OFFSET_TABLE_, %s\n",
347 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
348 fprintf (stream
, "\tlea.l (pc,%s.l),%s\n",
349 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
350 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
355 #if defined (NEWS) && defined (MOTOROLA)
358 m68k_output_function_prologue (stream
, size
)
363 register int mask
= 0;
364 extern char call_used_regs
[];
365 HOST_WIDE_INT fsize
= ((size
) + 3) & -4;
367 if (frame_pointer_needed
)
370 fprintf (stream
, "\tlink fp,#%d\n", -fsize
);
371 else if (TARGET_68020
)
372 fprintf (stream
, "\tlink.l fp,#%d\n", -fsize
);
374 fprintf (stream
, "\tlink fp,#0\n\tsub.l #%d,sp\n", fsize
);
379 /* Adding negative number is faster on the 68040. */
380 if (fsize
+ 4 < 0x8000)
381 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - amt
);
383 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - amt
);
386 for (regno
= 16; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
387 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
388 mask
|= 1 << (regno
- 16);
391 fprintf (stream
, "\tfmovem.x #0x%x,-(sp)\n", mask
& 0xff);
394 for (regno
= 0; regno
< 16; regno
++)
395 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
396 mask
|= 1 << (15 - regno
);
398 if (frame_pointer_needed
)
399 mask
&= ~ (1 << (15-FRAME_POINTER_REGNUM
));
401 if (exact_log2 (mask
) >= 0)
402 fprintf (stream
, "\tmove.l %s,-(sp)\n", reg_names
[15 - exact_log2 (mask
)]);
404 if (mask
) fprintf (stream
, "\tmovem.l #0x%x,-(sp)\n", mask
);
407 #else /* !CRDS && ! (NEWS && MOTOROLA) && ! (DPX2 && MOTOROLA) */
410 m68k_output_function_prologue (stream
, size
)
415 register int mask
= 0;
416 int num_saved_regs
= 0;
417 extern char call_used_regs
[];
418 HOST_WIDE_INT fsize
= (size
+ 3) & -4;
419 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
420 HOST_WIDE_INT cfa_store_offset
= cfa_offset
;
422 /* If the stack limit is a symbol, we can check it here,
423 before actually allocating the space. */
424 if (current_function_limit_stack
425 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
427 #if defined (MOTOROLA)
428 asm_fprintf (stream
, "\tcmp.l %0I%s+%d,%Rsp\n\ttrapcs\n",
429 XSTR (stack_limit_rtx
, 0), fsize
+ 4);
431 asm_fprintf (stream
, "\tcmpl %0I%s+%d,%Rsp\n\ttrapcs\n",
432 XSTR (stack_limit_rtx
, 0), fsize
+ 4);
436 if (frame_pointer_needed
)
438 if (fsize
== 0 && TARGET_68040
)
440 /* on the 68040, pea + move is faster than link.w 0 */
442 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
443 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
444 reg_names
[FRAME_POINTER_REGNUM
]);
446 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
447 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
448 reg_names
[FRAME_POINTER_REGNUM
]);
451 else if (fsize
< 0x8000)
454 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
455 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
457 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
458 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
461 else if (TARGET_68020
)
464 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
465 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
467 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
468 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
473 /* Adding negative number is faster on the 68040. */
475 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
476 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
478 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
479 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
482 if (dwarf2out_do_frame ())
485 l
= (char *) dwarf2out_cfi_label ();
486 cfa_store_offset
+= 4;
487 cfa_offset
= cfa_store_offset
;
488 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_store_offset
);
489 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
490 cfa_store_offset
+= fsize
;
495 if (fsize
+ 4 < 0x8000)
502 /* asm_fprintf() cannot handle %. */
504 asm_fprintf (stream
, "\tsubq.w %0I%d,%Rsp\n", fsize
+ 4);
506 asm_fprintf (stream
, "\tsubqw %0I%d,%Rsp\n", fsize
+ 4);
511 /* asm_fprintf() cannot handle %. */
513 asm_fprintf (stream
, "\tsubq.l %0I%d,%Rsp\n", fsize
+ 4);
515 asm_fprintf (stream
, "\tsubql %0I%d,%Rsp\n", fsize
+ 4);
519 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
521 /* On the CPU32 it is faster to use two subqw instructions to
522 subtract a small integer (8 < N <= 16) to a register. */
523 /* asm_fprintf() cannot handle %. */
525 asm_fprintf (stream
, "\tsubq.w %0I8,%Rsp\n\tsubq.w %0I%d,%Rsp\n",
528 asm_fprintf (stream
, "\tsubqw %0I8,%Rsp\n\tsubqw %0I%d,%Rsp\n",
533 #endif /* not NO_ADDSUB_Q */
536 /* Adding negative number is faster on the 68040. */
537 /* asm_fprintf() cannot handle %. */
539 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
541 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
547 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", - (fsize
+ 4));
549 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", - (fsize
+ 4));
555 /* asm_fprintf() cannot handle %. */
557 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
559 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
562 if (dwarf2out_do_frame ())
564 cfa_store_offset
+= fsize
;
565 cfa_offset
= cfa_store_offset
;
566 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
569 #ifdef SUPPORT_SUN_FPA
570 for (regno
= 24; regno
< 56; regno
++)
571 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
574 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
577 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
580 if (dwarf2out_do_frame ())
582 char *l
= dwarf2out_cfi_label ();
584 cfa_store_offset
+= 8;
585 if (! frame_pointer_needed
)
587 cfa_offset
= cfa_store_offset
;
588 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
590 dwarf2out_reg_save (l
, regno
, -cfa_store_offset
);
596 for (regno
= 16; regno
< 24; regno
++)
597 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
599 mask
|= 1 << (regno
- 16);
602 if ((mask
& 0xff) != 0)
605 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
607 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
609 if (dwarf2out_do_frame ())
611 char *l
= (char *) dwarf2out_cfi_label ();
614 cfa_store_offset
+= num_saved_regs
* 12;
615 if (! frame_pointer_needed
)
617 cfa_offset
= cfa_store_offset
;
618 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
620 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
621 if (mask
& (1 << (regno
- 16)))
622 dwarf2out_reg_save (l
, regno
,
623 -cfa_store_offset
+ n_regs
++ * 12);
629 for (regno
= 0; regno
< 16; regno
++)
630 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
632 mask
|= 1 << (15 - regno
);
635 if (frame_pointer_needed
)
637 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
640 if (flag_pic
&& current_function_uses_pic_offset_table
)
642 mask
|= 1 << (15 - PIC_OFFSET_TABLE_REGNUM
);
648 asm_fprintf (stream
, "\ttst.l %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
650 asm_fprintf (stream
, "\ttstl %Rsp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
654 /* If the stack limit is not a symbol, check it here.
655 This has the disadvantage that it may be too late... */
656 if (current_function_limit_stack
)
658 if (REG_P (stack_limit_rtx
))
660 #if defined (MOTOROLA)
661 asm_fprintf (stream
, "\tcmp.l %s,%Rsp\n\ttrapcs\n",
662 reg_names
[REGNO (stack_limit_rtx
)]);
664 asm_fprintf (stream
, "\tcmpl %s,%Rsp\n\ttrapcs\n",
665 reg_names
[REGNO (stack_limit_rtx
)]);
668 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
669 warning ("stack limit expression is not supported");
672 if (num_saved_regs
<= 2)
674 /* Store each separately in the same order moveml uses.
675 Using two movel instructions instead of a single moveml
676 is about 15% faster for the 68020 and 68030 at no expense
681 /* Undo the work from above. */
682 for (i
= 0; i
< 16; i
++)
687 "\t%Omove.l %s,-(%Rsp)\n",
689 "\tmovel %s,%Rsp@-\n",
692 if (dwarf2out_do_frame ())
694 char *l
= (char *) dwarf2out_cfi_label ();
696 cfa_store_offset
+= 4;
697 if (! frame_pointer_needed
)
699 cfa_offset
= cfa_store_offset
;
700 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
702 dwarf2out_reg_save (l
, 15 - i
, -cfa_store_offset
);
710 /* The coldfire does not support the predecrement form of the
711 movml instruction, so we must adjust the stack pointer and
712 then use the plain address register indirect mode. We also
713 have to invert the register save mask to use the new mode.
715 FIXME: if num_saved_regs was calculated earlier, we could
716 combine the stack pointer adjustment with any adjustment
717 done when the initial stack frame is created. This would
718 save an instruction */
723 for (i
= 0; i
< 16; i
++)
725 newmask
|= (1 << (15-i
));
728 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
729 asm_fprintf (stream
, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask
);
731 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs
*4);
732 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@\n", newmask
);
738 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
740 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
743 if (dwarf2out_do_frame ())
745 char *l
= (char *) dwarf2out_cfi_label ();
748 cfa_store_offset
+= num_saved_regs
* 4;
749 if (! frame_pointer_needed
)
751 cfa_offset
= cfa_store_offset
;
752 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
754 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
755 if (mask
& (1 << (15 - regno
)))
756 dwarf2out_reg_save (l
, regno
,
757 -cfa_store_offset
+ n_regs
++ * 4);
760 if (flag_pic
&& current_function_uses_pic_offset_table
)
763 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
764 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
766 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
767 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
768 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
769 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
770 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
774 #endif /* ! (DPX2 && MOTOROLA) */
775 #endif /* ! (NEWS && MOTOROLA) */
778 /* Return true if this function's epilogue can be output as RTL. */
785 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
788 /* Copied from output_function_epilogue (). We should probably create a
789 separate layout routine to perform the common work. */
791 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
792 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
795 if (flag_pic
&& current_function_uses_pic_offset_table
)
801 /* This function generates the assembly code for function exit,
802 on machines that need it.
804 The function epilogue should not depend on the current stack pointer!
805 It should use the frame pointer only, if there is a frame pointer.
806 This is mandatory because of alloca; we also take advantage of it to
807 omit stack adjustments before returning. */
812 m68k_output_function_epilogue (stream
, size
)
817 register int mask
, fmask
;
819 HOST_WIDE_INT offset
, foffset
, fpoffset
;
820 extern char call_used_regs
[];
821 HOST_WIDE_INT fsize
= ((size
) + 3) & -4;
824 nregs
= 0; fmask
= 0; fpoffset
= 0;
825 for (regno
= 16; regno
< 24; regno
++)
826 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
829 fmask
|= 1 << (23 - regno
);
832 foffset
= fpoffset
+ nregs
* 12;
834 if (frame_pointer_needed
)
835 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
837 for (regno
= 0; regno
< 16; regno
++)
838 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
844 offset
= foffset
+ nregs
* 4;
845 if (offset
+ fsize
>= 0x8000
846 && frame_pointer_needed
847 && (mask
|| fmask
|| fpoffset
))
849 fprintf (stream
, "\tmovel $%d,a0\n", -fsize
);
853 if (exact_log2 (mask
) >= 0)
856 fprintf (stream
, "\tmovel -%d(a6,a0.l),%s\n",
857 offset
+ fsize
, reg_names
[exact_log2 (mask
)]);
858 else if (! frame_pointer_needed
)
859 fprintf (stream
, "\tmovel (sp)+,%s\n",
860 reg_names
[exact_log2 (mask
)]);
862 fprintf (stream
, "\tmovel -%d(a6),%s\n",
863 offset
+ fsize
, reg_names
[exact_log2 (mask
)]);
868 fprintf (stream
, "\tmovem -%d(a6,a0.l),$0x%x\n",
869 offset
+ fsize
, mask
);
870 else if (! frame_pointer_needed
)
871 fprintf (stream
, "\tmovem (sp)+,$0x%x\n", mask
);
873 fprintf (stream
, "\tmovem -%d(a6),$0x%x\n",
874 offset
+ fsize
, mask
);
880 fprintf (stream
, "\tfmovem -%d(a6,a0.l),$0x%x\n",
881 foffset
+ fsize
, fmask
);
882 else if (! frame_pointer_needed
)
883 fprintf (stream
, "\tfmovem (sp)+,$0x%x\n", fmask
);
885 fprintf (stream
, "\tfmovem -%d(a6),$0x%x\n",
886 foffset
+ fsize
, fmask
);
890 for (regno
= 55; regno
>= 24; regno
--)
891 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
894 fprintf(stream
, "\tfpmoved -%d(a6,a0.l), %s\n",
895 fpoffset
+ fsize
, reg_names
[regno
]);
896 else if (! frame_pointer_needed
)
897 fprintf(stream
, "\tfpmoved (sp)+, %s\n",
900 fprintf(stream
, "\tfpmoved -%d(a6), %s\n",
901 fpoffset
+ fsize
, reg_names
[regno
]);
905 if (frame_pointer_needed
)
906 fprintf (stream
, "\tunlk a6\n");
909 if (fsize
+ 4 < 0x8000)
910 fprintf (stream
, "\tadd.w #%d,sp\n", fsize
+ 4);
912 fprintf (stream
, "\tadd.l #%d,sp\n", fsize
+ 4);
915 if (current_function_pops_args
)
916 fprintf (stream
, "\trtd $%d\n", current_function_pops_args
);
918 fprintf (stream
, "\trts\n");
922 #if defined (DPX2) && defined (MOTOROLA)
925 m68k_output_function_epilogue (stream
, size
)
930 register int mask
, fmask
;
932 HOST_WIDE_INT offset
, foffset
, fpoffset
, first
= 1;
933 extern char call_used_regs
[];
934 HOST_WIDE_INT fsize
= ((size
) + 3) & -4;
936 rtx insn
= get_last_insn ();
938 /* If the last insn was a BARRIER, we don't have to write any code. */
939 if (GET_CODE (insn
) == NOTE
)
940 insn
= prev_nonnote_insn (insn
);
941 if (insn
&& GET_CODE (insn
) == BARRIER
)
943 /* Output just a no-op so that debuggers don't get confused
944 about which function the pc is in at this address. */
945 fprintf (stream
, "\tnop\n");
949 nregs
= 0; fmask
= 0; fpoffset
= 0;
950 for (regno
= 16; regno
< 24; regno
++)
951 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
954 fmask
|= 1 << (23 - regno
);
957 foffset
= fpoffset
+ nregs
* 12;
959 if (frame_pointer_needed
)
960 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
962 for (regno
= 0; regno
< 16; regno
++)
963 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
969 offset
= foffset
+ nregs
* 4;
970 if (offset
+ fsize
>= 0x8000
971 && frame_pointer_needed
972 && (mask
|| fmask
|| fpoffset
))
974 fprintf (stream
, "\tmove.l #%d,a0\n", -fsize
);
980 /* Restore each separately in the same order moveml does.
981 Using two movel instructions instead of a single moveml
982 is about 15% faster for the 68020 and 68030 at no expense
987 /* Undo the work from above. */
988 for (i
= 0; i
< 16; i
++)
992 fprintf (stream
, "\tmove.l -%d(%s,a0.l),%s\n",
994 reg_names
[FRAME_POINTER_REGNUM
],
996 else if (! frame_pointer_needed
)
997 fprintf (stream
, "\tmove.l (sp)+,%s\n",
1000 fprintf (stream
, "\tmove.l -%d(%s),%s\n",
1002 reg_names
[FRAME_POINTER_REGNUM
],
1004 offset
= offset
- 4;
1010 for (regno
= 0; regno
< 16; regno
++)
1011 if (mask
& (1 << regno
))
1015 fprintf (stream
, "\tmovem.l -%d(%s,a0.l),%s",
1017 reg_names
[FRAME_POINTER_REGNUM
],
1021 else if (first
&& ! frame_pointer_needed
)
1023 fprintf (stream
, "\tmovem.l (sp)+,%s",
1029 fprintf (stream
, "\tmovem.l -%d(%s),%s",
1031 reg_names
[FRAME_POINTER_REGNUM
],
1036 fprintf (stream
, "/%s", reg_names
[regno
]);
1038 fprintf (stream
, "\n");
1044 for (regno
= 16; regno
< 24; regno
++)
1045 if (fmask
& (1 << (23 - regno
)))
1049 fprintf (stream
, "\tfmovem.x -%d(%s,a0.l),%s",
1051 reg_names
[FRAME_POINTER_REGNUM
],
1055 else if (first
&& ! frame_pointer_needed
)
1057 fprintf (stream
, "\tfmovem.x (sp)+,%s",
1063 fprintf (stream
, "\tfmovem.x -%d(%s),%s",
1065 reg_names
[FRAME_POINTER_REGNUM
],
1070 fprintf (stream
, "/%s", reg_names
[regno
]);
1072 fprintf (stream
, "\n");
1075 if (frame_pointer_needed
)
1076 fprintf (stream
, "\tunlk %s\n",
1077 reg_names
[FRAME_POINTER_REGNUM
]);
1080 if (fsize
+ 4 < 0x8000)
1081 fprintf (stream
, "\tadd.w #%d,sp\n", fsize
+ 4);
1083 fprintf (stream
, "\tadd.l #%d,sp\n", fsize
+ 4);
1086 if (current_function_pops_args
)
1087 fprintf (stream
, "\trtd #%d\n", current_function_pops_args
);
1089 fprintf (stream
, "\trts\n");
1093 #if defined (NEWS) && defined (MOTOROLA)
1096 m68k_output_function_epilogue (stream
, size
)
1101 register int mask
, fmask
;
1103 HOST_WIDE_INT offset
, foffset
;
1104 extern char call_used_regs
[];
1105 HOST_WIDE_INT fsize
= ((size
) + 3) & -4;
1108 nregs
= 0; fmask
= 0;
1109 for (regno
= 16; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1110 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1113 fmask
|= 1 << (23 - regno
);
1116 foffset
= nregs
* 12;
1117 nregs
= 0; mask
= 0;
1118 if (frame_pointer_needed
)
1119 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
1121 for (regno
= 0; regno
< 16; regno
++)
1122 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1128 offset
= foffset
+ nregs
* 4;
1129 if (offset
+ fsize
>= 0x8000
1130 && frame_pointer_needed
1133 fprintf (stream
, "\tmove.l #%d,a0\n", -fsize
);
1137 if (exact_log2 (mask
) >= 0)
1140 fprintf (stream
, "\tmove.l (-%d,fp,a0.l),%s\n",
1141 offset
+ fsize
, reg_names
[exact_log2 (mask
)]);
1142 else if (! frame_pointer_needed
)
1143 fprintf (stream
, "\tmove.l (sp)+,%s\n",
1144 reg_names
[exact_log2 (mask
)]);
1146 fprintf (stream
, "\tmove.l (-%d,fp),%s\n",
1147 offset
+ fsize
, reg_names
[exact_log2 (mask
)]);
1152 fprintf (stream
, "\tmovem.l (-%d,fp,a0.l),#0x%x\n",
1153 offset
+ fsize
, mask
);
1154 else if (! frame_pointer_needed
)
1155 fprintf (stream
, "\tmovem.l (sp)+,#0x%x\n", mask
);
1157 fprintf (stream
, "\tmovem.l (-%d,fp),#0x%x\n",
1158 offset
+ fsize
, mask
);
1164 fprintf (stream
, "\tfmovem.x (-%d,fp,a0.l),#0x%x\n",
1165 foffset
+ fsize
, fmask
);
1166 else if (! frame_pointer_needed
)
1167 fprintf (stream
, "\tfmovem.x (sp)+,#0x%x\n", fmask
);
1169 fprintf (stream
, "\tfmovem.x (-%d,fp),#0x%x\n",
1170 foffset
+ fsize
, fmask
);
1173 if (frame_pointer_needed
)
1174 fprintf (stream
, "\tunlk fp\n");
1177 if (fsize
+ 4 < 0x8000)
1178 fprintf (stream
, "\tadd.w #%d,sp\n", fsize
+ 4);
1180 fprintf (stream
, "\tadd.l #%d,sp\n", fsize
+ 4);
1183 if (current_function_pops_args
)
1184 fprintf (stream
, "\trtd #%d\n", current_function_pops_args
);
1186 fprintf (stream
, "\trts\n");
1189 #else /* !CRDS && ! (NEWS && MOTOROLA) && ! (DPX2 && MOTOROLA) */
1192 m68k_output_function_epilogue (stream
, size
)
1197 register int mask
, fmask
;
1199 HOST_WIDE_INT offset
, foffset
, fpoffset
;
1200 extern char call_used_regs
[];
1201 HOST_WIDE_INT fsize
= (size
+ 3) & -4;
1203 rtx insn
= get_last_insn ();
1204 int restore_from_sp
= 0;
1206 /* If the last insn was a BARRIER, we don't have to write any code. */
1207 if (GET_CODE (insn
) == NOTE
)
1208 insn
= prev_nonnote_insn (insn
);
1209 if (insn
&& GET_CODE (insn
) == BARRIER
)
1211 /* Output just a no-op so that debuggers don't get confused
1212 about which function the pc is in at this address. */
1213 asm_fprintf (stream
, "\tnop\n");
1217 #ifdef FUNCTION_EXTRA_EPILOGUE
1218 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
1220 nregs
= 0; fmask
= 0; fpoffset
= 0;
1221 #ifdef SUPPORT_SUN_FPA
1222 for (regno
= 24 ; regno
< 56 ; regno
++)
1223 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1225 fpoffset
= nregs
* 8;
1230 for (regno
= 16; regno
< 24; regno
++)
1231 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1234 fmask
|= 1 << (23 - regno
);
1237 foffset
= fpoffset
+ nregs
* 12;
1238 nregs
= 0; mask
= 0;
1239 if (frame_pointer_needed
)
1240 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
1241 for (regno
= 0; regno
< 16; regno
++)
1242 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1247 if (flag_pic
&& current_function_uses_pic_offset_table
)
1250 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
1252 offset
= foffset
+ nregs
* 4;
1253 /* FIXME : leaf_function_p below is too strong.
1254 What we really need to know there is if there could be pending
1255 stack adjustment needed at that point. */
1256 restore_from_sp
= ! frame_pointer_needed
1257 || (! current_function_calls_alloca
&& leaf_function_p ());
1258 if (offset
+ fsize
>= 0x8000
1259 && ! restore_from_sp
1260 && (mask
|| fmask
|| fpoffset
))
1263 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
1265 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
1269 if (TARGET_5200
|| nregs
<= 2)
1271 /* Restore each separately in the same order moveml does.
1272 Using two movel instructions instead of a single moveml
1273 is about 15% faster for the 68020 and 68030 at no expense
1278 /* Undo the work from above. */
1279 for (i
= 0; i
< 16; i
++)
1280 if (mask
& (1 << i
))
1285 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
1287 reg_names
[FRAME_POINTER_REGNUM
],
1290 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
1291 reg_names
[FRAME_POINTER_REGNUM
],
1292 offset
+ fsize
, reg_names
[i
]);
1295 else if (restore_from_sp
)
1298 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
1301 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
1308 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
1310 reg_names
[FRAME_POINTER_REGNUM
],
1313 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
1314 reg_names
[FRAME_POINTER_REGNUM
],
1315 offset
+ fsize
, reg_names
[i
]);
1318 offset
= offset
- 4;
1326 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
1328 reg_names
[FRAME_POINTER_REGNUM
],
1331 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
1332 reg_names
[FRAME_POINTER_REGNUM
],
1333 offset
+ fsize
, mask
);
1336 else if (restore_from_sp
)
1339 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
1341 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
1347 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
1349 reg_names
[FRAME_POINTER_REGNUM
],
1352 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
1353 reg_names
[FRAME_POINTER_REGNUM
],
1354 offset
+ fsize
, mask
);
1363 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
1365 reg_names
[FRAME_POINTER_REGNUM
],
1368 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
1369 reg_names
[FRAME_POINTER_REGNUM
],
1370 foffset
+ fsize
, fmask
);
1373 else if (restore_from_sp
)
1376 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
1378 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
1384 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
1386 reg_names
[FRAME_POINTER_REGNUM
],
1389 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
1390 reg_names
[FRAME_POINTER_REGNUM
],
1391 foffset
+ fsize
, fmask
);
1396 for (regno
= 55; regno
>= 24; regno
--)
1397 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1402 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
1404 reg_names
[FRAME_POINTER_REGNUM
],
1407 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
1408 reg_names
[FRAME_POINTER_REGNUM
],
1409 fpoffset
+ fsize
, reg_names
[regno
]);
1412 else if (restore_from_sp
)
1415 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
1418 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
1425 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
1427 reg_names
[FRAME_POINTER_REGNUM
],
1430 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
1431 reg_names
[FRAME_POINTER_REGNUM
],
1432 fpoffset
+ fsize
, reg_names
[regno
]);
1437 if (frame_pointer_needed
)
1438 fprintf (stream
, "\tunlk %s\n",
1439 reg_names
[FRAME_POINTER_REGNUM
]);
1448 asm_fprintf (stream
, "\taddq.w %0I%d,%Rsp\n", fsize
+ 4);
1450 asm_fprintf (stream
, "\taddqw %0I%d,%Rsp\n", fsize
+ 4);
1456 asm_fprintf (stream
, "\taddq.l %0I%d,%Rsp\n", fsize
+ 4);
1458 asm_fprintf (stream
, "\taddql %0I%d,%Rsp\n", fsize
+ 4);
1462 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
1464 /* On the CPU32 it is faster to use two addqw instructions to
1465 add a small integer (8 < N <= 16) to a register. */
1466 /* asm_fprintf() cannot handle %. */
1468 asm_fprintf (stream
, "\taddq.w %0I8,%Rsp\n\taddq.w %0I%d,%Rsp\n",
1471 asm_fprintf (stream
, "\taddqw %0I8,%Rsp\n\taddqw %0I%d,%Rsp\n",
1476 #endif /* not NO_ADDSUB_Q */
1477 if (fsize
+ 4 < 0x8000)
1481 /* asm_fprintf() cannot handle %. */
1483 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
1485 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
1491 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", fsize
+ 4);
1493 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", fsize
+ 4);
1499 /* asm_fprintf() cannot handle %. */
1501 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
1503 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
1507 if (current_function_pops_args
)
1508 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
1510 fprintf (stream
, "\trts\n");
1513 #endif /* ! (DPX2 && MOTOROLA) */
1514 #endif /* ! (NEWS && MOTOROLA) */
1517 /* Similar to general_operand, but exclude stack_pointer_rtx. */
1520 not_sp_operand (op
, mode
)
1522 enum machine_mode mode
;
1524 return op
!= stack_pointer_rtx
&& nonimmediate_operand (op
, mode
);
1527 /* Return TRUE if X is a valid comparison operator for the dbcc
1530 Note it rejects floating point comparison operators.
1531 (In the future we could use Fdbcc).
1533 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1536 valid_dbcc_comparison_p (x
, mode
)
1538 enum machine_mode mode ATTRIBUTE_UNUSED
;
1540 switch (GET_CODE (x
))
1542 case EQ
: case NE
: case GTU
: case LTU
:
1546 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1548 case GT
: case LT
: case GE
: case LE
:
1549 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1555 /* Return non-zero if flags are currently in the 68881 flag register. */
1559 /* We could add support for these in the future */
1560 return cc_status
.flags
& CC_IN_68881
;
1563 /* Output a dbCC; jCC sequence. Note we do not handle the
1564 floating point version of this sequence (Fdbcc). We also
1565 do not handle alternative conditions when CC_NO_OVERFLOW is
1566 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1567 kick those out before we get here. */
1570 output_dbcc_and_branch (operands
)
1573 switch (GET_CODE (operands
[3]))
1577 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
1579 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1585 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
1587 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1593 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
1595 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1601 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
1603 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1609 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
1611 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1617 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
1619 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1625 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
1627 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1633 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
1635 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1641 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
1643 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1649 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
1651 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1659 /* If the decrement is to be done in SImode, then we have
1660 to compensate for the fact that dbcc decrements in HImode. */
1661 switch (GET_MODE (operands
[0]))
1665 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
1667 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
1680 output_scc_di(op
, operand1
, operand2
, dest
)
1687 enum rtx_code op_code
= GET_CODE (op
);
1689 /* This does not produce a useful cc. */
1692 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1693 below. Swap the operands and change the op if these requirements
1694 are not fulfilled. */
1695 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1699 operand1
= operand2
;
1701 op_code
= swap_condition (op_code
);
1703 loperands
[0] = operand1
;
1704 if (GET_CODE (operand1
) == REG
)
1705 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1707 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1708 if (operand2
!= const0_rtx
)
1710 loperands
[2] = operand2
;
1711 if (GET_CODE (operand2
) == REG
)
1712 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1714 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1716 loperands
[4] = gen_label_rtx();
1717 if (operand2
!= const0_rtx
)
1720 #ifdef SGS_CMP_ORDER
1721 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1723 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1726 #ifdef SGS_CMP_ORDER
1727 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1729 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1735 if (TARGET_68020
|| TARGET_5200
|| ! ADDRESS_REG_P (loperands
[0]))
1736 output_asm_insn ("tst%.l %0", loperands
);
1739 #ifdef SGS_CMP_ORDER
1740 output_asm_insn ("cmp%.w %0,%#0", loperands
);
1742 output_asm_insn ("cmp%.w %#0,%0", loperands
);
1747 output_asm_insn ("jbne %l4", loperands
);
1749 output_asm_insn ("jne %l4", loperands
);
1752 if (TARGET_68020
|| TARGET_5200
|| ! ADDRESS_REG_P (loperands
[1]))
1753 output_asm_insn ("tst%.l %1", loperands
);
1756 #ifdef SGS_CMP_ORDER
1757 output_asm_insn ("cmp%.w %1,%#0", loperands
);
1759 output_asm_insn ("cmp%.w %#0,%1", loperands
);
1764 loperands
[5] = dest
;
1769 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1770 CODE_LABEL_NUMBER (loperands
[4]));
1771 output_asm_insn ("seq %5", loperands
);
1775 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1776 CODE_LABEL_NUMBER (loperands
[4]));
1777 output_asm_insn ("sne %5", loperands
);
1781 loperands
[6] = gen_label_rtx();
1783 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1785 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1787 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1788 CODE_LABEL_NUMBER (loperands
[4]));
1789 output_asm_insn ("sgt %5", loperands
);
1790 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1791 CODE_LABEL_NUMBER (loperands
[6]));
1795 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1796 CODE_LABEL_NUMBER (loperands
[4]));
1797 output_asm_insn ("shi %5", loperands
);
1801 loperands
[6] = gen_label_rtx();
1803 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1805 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1807 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1808 CODE_LABEL_NUMBER (loperands
[4]));
1809 output_asm_insn ("slt %5", loperands
);
1810 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1811 CODE_LABEL_NUMBER (loperands
[6]));
1815 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1816 CODE_LABEL_NUMBER (loperands
[4]));
1817 output_asm_insn ("scs %5", loperands
);
1821 loperands
[6] = gen_label_rtx();
1823 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1825 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1827 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1828 CODE_LABEL_NUMBER (loperands
[4]));
1829 output_asm_insn ("sge %5", loperands
);
1830 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1831 CODE_LABEL_NUMBER (loperands
[6]));
1835 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1836 CODE_LABEL_NUMBER (loperands
[4]));
1837 output_asm_insn ("scc %5", loperands
);
1841 loperands
[6] = gen_label_rtx();
1843 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1845 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1847 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1848 CODE_LABEL_NUMBER (loperands
[4]));
1849 output_asm_insn ("sle %5", loperands
);
1850 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1851 CODE_LABEL_NUMBER (loperands
[6]));
1855 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1856 CODE_LABEL_NUMBER (loperands
[4]));
1857 output_asm_insn ("sls %5", loperands
);
1867 output_btst (operands
, countop
, dataop
, insn
, signpos
)
1869 rtx countop
, dataop
;
1873 operands
[0] = countop
;
1874 operands
[1] = dataop
;
1876 if (GET_CODE (countop
) == CONST_INT
)
1878 register int count
= INTVAL (countop
);
1879 /* If COUNT is bigger than size of storage unit in use,
1880 advance to the containing unit of same size. */
1881 if (count
> signpos
)
1883 int offset
= (count
& ~signpos
) / 8;
1884 count
= count
& signpos
;
1885 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1887 if (count
== signpos
)
1888 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1890 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1892 /* These three statements used to use next_insns_test_no...
1893 but it appears that this should do the same job. */
1895 && next_insn_tests_no_inequality (insn
))
1898 && next_insn_tests_no_inequality (insn
))
1901 && next_insn_tests_no_inequality (insn
))
1904 cc_status
.flags
= CC_NOT_NEGATIVE
;
1906 return "btst %0,%1";
1909 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1910 reference and a constant. */
1913 symbolic_operand (op
, mode
)
1915 enum machine_mode mode ATTRIBUTE_UNUSED
;
1917 switch (GET_CODE (op
))
1925 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1926 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1927 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1929 #if 0 /* Deleted, with corresponding change in m68k.h,
1930 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1932 return GET_MODE (op
) == mode
;
1940 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1943 extend_operator(x
, mode
)
1945 enum machine_mode mode
;
1947 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1949 switch (GET_CODE(x
))
1960 /* Legitimize PIC addresses. If the address is already
1961 position-independent, we return ORIG. Newly generated
1962 position-independent addresses go to REG. If we need more
1963 than one register, we lose.
1965 An address is legitimized by making an indirect reference
1966 through the Global Offset Table with the name of the symbol
1969 The assembler and linker are responsible for placing the
1970 address of the symbol in the GOT. The function prologue
1971 is responsible for initializing a5 to the starting address
1974 The assembler is also responsible for translating a symbol name
1975 into a constant displacement from the start of the GOT.
1977 A quick example may make things a little clearer:
1979 When not generating PIC code to store the value 12345 into _foo
1980 we would generate the following code:
1984 When generating PIC two transformations are made. First, the compiler
1985 loads the address of foo into a register. So the first transformation makes:
1990 The code in movsi will intercept the lea instruction and call this
1991 routine which will transform the instructions into:
1993 movel a5@(_foo:w), a0
1997 That (in a nutshell) is how *all* symbol and label references are
2001 legitimize_pic_address (orig
, mode
, reg
)
2003 enum machine_mode mode ATTRIBUTE_UNUSED
;
2007 /* First handle a simple SYMBOL_REF or LABEL_REF */
2008 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2013 pic_ref
= gen_rtx_MEM (Pmode
,
2014 gen_rtx_PLUS (Pmode
,
2015 pic_offset_table_rtx
, orig
));
2016 current_function_uses_pic_offset_table
= 1;
2017 RTX_UNCHANGING_P (pic_ref
) = 1;
2018 emit_move_insn (reg
, pic_ref
);
2021 else if (GET_CODE (orig
) == CONST
)
2025 /* Make sure this is CONST has not already been legitimized */
2026 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2027 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2033 /* legitimize both operands of the PLUS */
2034 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2036 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2037 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2038 base
== reg
? 0 : reg
);
2042 if (GET_CODE (orig
) == CONST_INT
)
2043 return plus_constant (base
, INTVAL (orig
));
2044 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2045 /* Likewise, should we set special REG_NOTEs here? */
2051 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
2053 static CONST_METHOD const_method
PARAMS ((rtx
));
2055 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
2058 const_method (constant
)
2064 i
= INTVAL (constant
);
2068 /* The Coldfire doesn't have byte or word operations. */
2069 /* FIXME: This may not be useful for the m68060 either */
2072 /* if -256 < N < 256 but N is not in range for a moveq
2073 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2074 if (USE_MOVQ (i
^ 0xff))
2076 /* Likewise, try with not.w */
2077 if (USE_MOVQ (i
^ 0xffff))
2079 /* This is the only value where neg.w is useful */
2082 /* Try also with swap */
2084 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2087 /* Otherwise, use move.l */
2092 const_int_cost (constant
)
2095 switch (const_method (constant
))
2098 /* Constants between -128 and 127 are cheap due to moveq */
2104 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
2114 output_move_const_into_data_reg (operands
)
2119 i
= INTVAL (operands
[1]);
2120 switch (const_method (operands
[1]))
2123 #if defined (MOTOROLA) && !defined (CRDS)
2124 return "moveq%.l %1,%0";
2126 return "moveq %1,%0";
2129 operands
[1] = GEN_INT (i
^ 0xff);
2130 #if defined (MOTOROLA) && !defined (CRDS)
2131 return "moveq%.l %1,%0\n\tnot%.b %0";
2133 return "moveq %1,%0\n\tnot%.b %0";
2136 operands
[1] = GEN_INT (i
^ 0xffff);
2137 #if defined (MOTOROLA) && !defined (CRDS)
2138 return "moveq%.l %1,%0\n\tnot%.w %0";
2140 return "moveq %1,%0\n\tnot%.w %0";
2143 #if defined (MOTOROLA) && !defined (CRDS)
2144 return "moveq%.l %#-128,%0\n\tneg%.w %0";
2146 return "moveq %#-128,%0\n\tneg%.w %0";
2152 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2153 #if defined (MOTOROLA) && !defined (CRDS)
2154 return "moveq%.l %1,%0\n\tswap %0";
2156 return "moveq %1,%0\n\tswap %0";
2160 return "move%.l %1,%0";
2167 output_move_simode_const (operands
)
2170 if (operands
[1] == const0_rtx
2171 && (DATA_REG_P (operands
[0])
2172 || GET_CODE (operands
[0]) == MEM
)
2173 /* clr insns on 68000 read before writing.
2174 This isn't so on the 68010, but we have no TARGET_68010. */
2175 && ((TARGET_68020
|| TARGET_5200
)
2176 || !(GET_CODE (operands
[0]) == MEM
2177 && MEM_VOLATILE_P (operands
[0]))))
2179 else if (operands
[1] == const0_rtx
2180 && ADDRESS_REG_P (operands
[0]))
2181 return "sub%.l %0,%0";
2182 else if (DATA_REG_P (operands
[0]))
2183 return output_move_const_into_data_reg (operands
);
2184 else if (ADDRESS_REG_P (operands
[0])
2185 && INTVAL (operands
[1]) < 0x8000
2186 && INTVAL (operands
[1]) >= -0x8000)
2187 return "move%.w %1,%0";
2188 else if (GET_CODE (operands
[0]) == MEM
2189 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2190 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2191 && INTVAL (operands
[1]) < 0x8000
2192 && INTVAL (operands
[1]) >= -0x8000)
2194 return "move%.l %1,%0";
2198 output_move_simode (operands
)
2201 if (GET_CODE (operands
[1]) == CONST_INT
)
2202 return output_move_simode_const (operands
);
2203 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2204 || GET_CODE (operands
[1]) == CONST
)
2205 && push_operand (operands
[0], SImode
))
2207 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2208 || GET_CODE (operands
[1]) == CONST
)
2209 && ADDRESS_REG_P (operands
[0]))
2210 return "lea %a1,%0";
2211 return "move%.l %1,%0";
2215 output_move_himode (operands
)
2218 if (GET_CODE (operands
[1]) == CONST_INT
)
2220 if (operands
[1] == const0_rtx
2221 && (DATA_REG_P (operands
[0])
2222 || GET_CODE (operands
[0]) == MEM
)
2223 /* clr insns on 68000 read before writing.
2224 This isn't so on the 68010, but we have no TARGET_68010. */
2225 && ((TARGET_68020
|| TARGET_5200
)
2226 || !(GET_CODE (operands
[0]) == MEM
2227 && MEM_VOLATILE_P (operands
[0]))))
2229 else if (operands
[1] == const0_rtx
2230 && ADDRESS_REG_P (operands
[0]))
2231 return "sub%.l %0,%0";
2232 else if (DATA_REG_P (operands
[0])
2233 && INTVAL (operands
[1]) < 128
2234 && INTVAL (operands
[1]) >= -128)
2236 #if defined(MOTOROLA) && !defined(CRDS)
2237 return "moveq%.l %1,%0";
2239 return "moveq %1,%0";
2242 else if (INTVAL (operands
[1]) < 0x8000
2243 && INTVAL (operands
[1]) >= -0x8000)
2244 return "move%.w %1,%0";
2246 else if (CONSTANT_P (operands
[1]))
2247 return "move%.l %1,%0";
2249 /* Recognize the insn before a tablejump, one that refers
2250 to a table of offsets. Such an insn will need to refer
2251 to a label on the insn. So output one. Use the label-number
2252 of the table of offsets to generate this label. This code,
2253 and similar code below, assumes that there will be at most one
2254 reference to each table. */
2255 if (GET_CODE (operands
[1]) == MEM
2256 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2257 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
2258 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
2260 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
2261 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
2263 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
2264 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2266 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
2267 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2268 #endif /* not SGS */
2269 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
2270 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LI",
2271 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2272 #ifdef SGS_SWITCH_TABLES
2273 /* Set flag saying we need to define the symbol
2274 LD%n (with value L%n-LI%n) at the end of the switch table. */
2275 switch_table_difference_label_flag
= 1;
2276 #endif /* SGS_SWITCH_TABLES */
2277 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
2279 #endif /* SGS_NO_LI */
2280 return "move%.w %1,%0";
2284 output_move_qimode (operands
)
2289 /* This is probably useless, since it loses for pushing a struct
2290 of several bytes a byte at a time. */
2291 /* 68k family always modifies the stack pointer by at least 2, even for
2292 byte pushes. The 5200 (coldfire) does not do this. */
2293 if (GET_CODE (operands
[0]) == MEM
2294 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2295 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2296 && ! ADDRESS_REG_P (operands
[1])
2299 xoperands
[1] = operands
[1];
2301 = gen_rtx_MEM (QImode
,
2302 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
2303 /* Just pushing a byte puts it in the high byte of the halfword. */
2304 /* We must put it in the low-order, high-numbered byte. */
2305 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
2307 xoperands
[3] = stack_pointer_rtx
;
2309 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
2311 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
2315 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
2319 /* clr and st insns on 68000 read before writing.
2320 This isn't so on the 68010, but we have no TARGET_68010. */
2321 if (!ADDRESS_REG_P (operands
[0])
2322 && ((TARGET_68020
|| TARGET_5200
)
2323 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2325 if (operands
[1] == const0_rtx
)
2327 if ((!TARGET_5200
|| DATA_REG_P (operands
[0]))
2328 && GET_CODE (operands
[1]) == CONST_INT
2329 && (INTVAL (operands
[1]) & 255) == 255)
2335 if (GET_CODE (operands
[1]) == CONST_INT
2336 && DATA_REG_P (operands
[0])
2337 && INTVAL (operands
[1]) < 128
2338 && INTVAL (operands
[1]) >= -128)
2340 #if defined(MOTOROLA) && !defined(CRDS)
2341 return "moveq%.l %1,%0";
2343 return "moveq %1,%0";
2346 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2347 return "sub%.l %0,%0";
2348 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2349 return "move%.l %1,%0";
2350 /* 68k family (including the 5200 coldfire) does not support byte moves to
2351 from address registers. */
2352 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2353 return "move%.w %1,%0";
2354 return "move%.b %1,%0";
2358 output_move_stricthi (operands
)
2361 if (operands
[1] == const0_rtx
2362 /* clr insns on 68000 read before writing.
2363 This isn't so on the 68010, but we have no TARGET_68010. */
2364 && ((TARGET_68020
|| TARGET_5200
)
2365 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2367 return "move%.w %1,%0";
2371 output_move_strictqi (operands
)
2374 if (operands
[1] == const0_rtx
2375 /* clr insns on 68000 read before writing.
2376 This isn't so on the 68010, but we have no TARGET_68010. */
2377 && ((TARGET_68020
|| TARGET_5200
)
2378 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2380 return "move%.b %1,%0";
2383 /* Return the best assembler insn template
2384 for moving operands[1] into operands[0] as a fullword. */
2387 singlemove_string (operands
)
2390 #ifdef SUPPORT_SUN_FPA
2391 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
2392 return "fpmoves %1,%0";
2394 if (GET_CODE (operands
[1]) == CONST_INT
)
2395 return output_move_simode_const (operands
);
2396 return "move%.l %1,%0";
2400 /* Output assembler code to perform a doubleword move insn
2401 with operands OPERANDS. */
2404 output_move_double (operands
)
2409 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2414 rtx addreg0
= 0, addreg1
= 0;
2415 int dest_overlapped_low
= 0;
2416 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2421 /* First classify both operands. */
2423 if (REG_P (operands
[0]))
2425 else if (offsettable_memref_p (operands
[0]))
2427 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2429 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2431 else if (GET_CODE (operands
[0]) == MEM
)
2436 if (REG_P (operands
[1]))
2438 else if (CONSTANT_P (operands
[1]))
2440 else if (offsettable_memref_p (operands
[1]))
2442 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2444 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2446 else if (GET_CODE (operands
[1]) == MEM
)
2451 /* Check for the cases that the operand constraints are not
2452 supposed to allow to happen. Abort if we get one,
2453 because generating code for these cases is painful. */
2455 if (optype0
== RNDOP
|| optype1
== RNDOP
)
2458 /* If one operand is decrementing and one is incrementing
2459 decrement the former register explicitly
2460 and change that operand into ordinary indexing. */
2462 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2464 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2466 output_asm_insn ("sub%.l %#12,%0", operands
);
2468 output_asm_insn ("subq%.l %#8,%0", operands
);
2469 if (GET_MODE (operands
[1]) == XFmode
)
2470 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2471 else if (GET_MODE (operands
[0]) == DFmode
)
2472 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2474 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2477 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2479 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2481 output_asm_insn ("sub%.l %#12,%1", operands
);
2483 output_asm_insn ("subq%.l %#8,%1", operands
);
2484 if (GET_MODE (operands
[1]) == XFmode
)
2485 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2486 else if (GET_MODE (operands
[1]) == DFmode
)
2487 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2489 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2493 /* If an operand is an unoffsettable memory ref, find a register
2494 we can increment temporarily to make it refer to the second word. */
2496 if (optype0
== MEMOP
)
2497 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2499 if (optype1
== MEMOP
)
2500 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2502 /* Ok, we can do one word at a time.
2503 Normally we do the low-numbered word first,
2504 but if either operand is autodecrementing then we
2505 do the high-numbered word first.
2507 In either case, set up in LATEHALF the operands to use
2508 for the high-numbered word and in some cases alter the
2509 operands in OPERANDS to be suitable for the low-numbered word. */
2513 if (optype0
== REGOP
)
2515 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2516 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2518 else if (optype0
== OFFSOP
)
2520 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2521 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2525 middlehalf
[0] = operands
[0];
2526 latehalf
[0] = operands
[0];
2529 if (optype1
== REGOP
)
2531 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2532 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2534 else if (optype1
== OFFSOP
)
2536 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2537 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2539 else if (optype1
== CNSTOP
)
2541 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2546 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2547 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2548 operands
[1] = GEN_INT (l
[0]);
2549 middlehalf
[1] = GEN_INT (l
[1]);
2550 latehalf
[1] = GEN_INT (l
[2]);
2552 else if (CONSTANT_P (operands
[1]))
2554 /* actually, no non-CONST_DOUBLE constant should ever
2557 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
2558 latehalf
[1] = constm1_rtx
;
2560 latehalf
[1] = const0_rtx
;
2565 middlehalf
[1] = operands
[1];
2566 latehalf
[1] = operands
[1];
2570 /* size is not 12: */
2572 if (optype0
== REGOP
)
2573 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2574 else if (optype0
== OFFSOP
)
2575 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2577 latehalf
[0] = operands
[0];
2579 if (optype1
== REGOP
)
2580 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2581 else if (optype1
== OFFSOP
)
2582 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2583 else if (optype1
== CNSTOP
)
2584 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2586 latehalf
[1] = operands
[1];
2589 /* If insn is effectively movd N(sp),-(sp) then we will do the
2590 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2591 for the low word as well, to compensate for the first decrement of sp. */
2592 if (optype0
== PUSHOP
2593 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2594 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2595 operands
[1] = middlehalf
[1] = latehalf
[1];
2597 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2598 if the upper part of reg N does not appear in the MEM, arrange to
2599 emit the move late-half first. Otherwise, compute the MEM address
2600 into the upper part of N and use that as a pointer to the memory
2602 if (optype0
== REGOP
2603 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2605 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2607 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2608 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2610 /* If both halves of dest are used in the src memory address,
2611 compute the address into latehalf of dest.
2612 Note that this can't happen if the dest is two data regs. */
2614 xops
[0] = latehalf
[0];
2615 xops
[1] = XEXP (operands
[1], 0);
2616 output_asm_insn ("lea %a1,%0", xops
);
2617 if (GET_MODE (operands
[1]) == XFmode
)
2619 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2620 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2621 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2625 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2626 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2630 && reg_overlap_mentioned_p (middlehalf
[0],
2631 XEXP (operands
[1], 0)))
2633 /* Check for two regs used by both source and dest.
2634 Note that this can't happen if the dest is all data regs.
2635 It can happen if the dest is d6, d7, a0.
2636 But in that case, latehalf is an addr reg, so
2637 the code at compadr does ok. */
2639 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2640 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2643 /* JRV says this can't happen: */
2644 if (addreg0
|| addreg1
)
2647 /* Only the middle reg conflicts; simply put it last. */
2648 output_asm_insn (singlemove_string (operands
), operands
);
2649 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2650 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2653 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2654 /* If the low half of dest is mentioned in the source memory
2655 address, the arrange to emit the move late half first. */
2656 dest_overlapped_low
= 1;
2659 /* If one or both operands autodecrementing,
2660 do the two words, high-numbered first. */
2662 /* Likewise, the first move would clobber the source of the second one,
2663 do them in the other order. This happens only for registers;
2664 such overlap can't happen in memory unless the user explicitly
2665 sets it up, and that is an undefined circumstance. */
2667 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2668 || (optype0
== REGOP
&& optype1
== REGOP
2669 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2670 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2671 || dest_overlapped_low
)
2673 /* Make any unoffsettable addresses point at high-numbered word. */
2677 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
2679 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2684 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
2686 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2690 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2692 /* Undo the adds we just did. */
2694 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2696 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2700 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2702 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2704 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2707 /* Do low-numbered word. */
2708 return singlemove_string (operands
);
2711 /* Normal case: do the two words, low-numbered first. */
2713 output_asm_insn (singlemove_string (operands
), operands
);
2715 /* Do the middle one of the three words for long double */
2719 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2721 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2723 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2726 /* Make any unoffsettable addresses point at high-numbered word. */
2728 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2730 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2733 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2735 /* Undo the adds we just did. */
2739 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2741 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2746 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2748 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2754 /* Return a REG that occurs in ADDR with coefficient 1.
2755 ADDR can be effectively incremented by incrementing REG. */
2758 find_addr_reg (addr
)
2761 while (GET_CODE (addr
) == PLUS
)
2763 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2764 addr
= XEXP (addr
, 0);
2765 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2766 addr
= XEXP (addr
, 1);
2767 else if (CONSTANT_P (XEXP (addr
, 0)))
2768 addr
= XEXP (addr
, 1);
2769 else if (CONSTANT_P (XEXP (addr
, 1)))
2770 addr
= XEXP (addr
, 0);
2774 if (GET_CODE (addr
) == REG
)
2779 /* Output assembler code to perform a 32 bit 3 operand add. */
2782 output_addsi3 (operands
)
2785 if (! operands_match_p (operands
[0], operands
[1]))
2787 if (!ADDRESS_REG_P (operands
[1]))
2789 rtx tmp
= operands
[1];
2791 operands
[1] = operands
[2];
2795 /* These insns can result from reloads to access
2796 stack slots over 64k from the frame pointer. */
2797 if (GET_CODE (operands
[2]) == CONST_INT
2798 && INTVAL (operands
[2]) + 0x8000 >= (unsigned) 0x10000)
2799 return "move%.l %2,%0\n\tadd%.l %1,%0";
2801 if (GET_CODE (operands
[2]) == REG
)
2802 return "lea 0(%1,%2.l),%0";
2804 return "lea %c2(%1),%0";
2807 if (GET_CODE (operands
[2]) == REG
)
2808 return "lea (%1,%2.l),%0";
2810 return "lea (%c2,%1),%0";
2811 #else /* not MOTOROLA (MIT syntax) */
2812 if (GET_CODE (operands
[2]) == REG
)
2813 return "lea %1@(0,%2:l),%0";
2815 return "lea %1@(%c2),%0";
2816 #endif /* not MOTOROLA */
2817 #endif /* not SGS */
2819 if (GET_CODE (operands
[2]) == CONST_INT
)
2822 if (INTVAL (operands
[2]) > 0
2823 && INTVAL (operands
[2]) <= 8)
2824 return "addq%.l %2,%0";
2825 if (INTVAL (operands
[2]) < 0
2826 && INTVAL (operands
[2]) >= -8)
2828 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2829 return "subq%.l %2,%0";
2831 /* On the CPU32 it is faster to use two addql instructions to
2832 add a small integer (8 < N <= 16) to a register.
2833 Likewise for subql. */
2834 if (TARGET_CPU32
&& REG_P (operands
[0]))
2836 if (INTVAL (operands
[2]) > 8
2837 && INTVAL (operands
[2]) <= 16)
2839 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2840 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2842 if (INTVAL (operands
[2]) < -8
2843 && INTVAL (operands
[2]) >= -16)
2845 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2846 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2850 if (ADDRESS_REG_P (operands
[0])
2851 && INTVAL (operands
[2]) >= -0x8000
2852 && INTVAL (operands
[2]) < 0x8000)
2855 return "add%.w %2,%0";
2858 return "lea (%c2,%0),%0";
2860 return "lea %0@(%c2),%0";
2864 return "add%.l %2,%0";
2867 /* Store in cc_status the expressions that the condition codes will
2868 describe after execution of an instruction whose pattern is EXP.
2869 Do not alter them if the instruction would not alter the cc's. */
2871 /* On the 68000, all the insns to store in an address register fail to
2872 set the cc's. However, in some cases these instructions can make it
2873 possibly invalid to use the saved cc's. In those cases we clear out
2874 some or all of the saved cc's so they won't be used. */
2877 notice_update_cc (exp
, insn
)
2881 /* If the cc is being set from the fpa and the expression is not an
2882 explicit floating point test instruction (which has code to deal with
2883 this), reinit the CC. */
2884 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2885 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
2886 && !(GET_CODE (exp
) == PARALLEL
2887 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
2888 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
2892 else if (GET_CODE (exp
) == SET
)
2894 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2898 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2900 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2901 cc_status
.value1
= 0;
2902 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2903 cc_status
.value2
= 0;
2905 else if (!FP_REG_P (SET_DEST (exp
))
2906 && SET_DEST (exp
) != cc0_rtx
2907 && (FP_REG_P (SET_SRC (exp
))
2908 || GET_CODE (SET_SRC (exp
)) == FIX
2909 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2910 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2914 /* A pair of move insns doesn't produce a useful overall cc. */
2915 else if (!FP_REG_P (SET_DEST (exp
))
2916 && !FP_REG_P (SET_SRC (exp
))
2917 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2918 && (GET_CODE (SET_SRC (exp
)) == REG
2919 || GET_CODE (SET_SRC (exp
)) == MEM
2920 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2924 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2928 else if (XEXP (exp
, 0) != pc_rtx
)
2930 cc_status
.flags
= 0;
2931 cc_status
.value1
= XEXP (exp
, 0);
2932 cc_status
.value2
= XEXP (exp
, 1);
2935 else if (GET_CODE (exp
) == PARALLEL
2936 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2938 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2940 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2942 cc_status
.flags
= 0;
2943 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2944 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2949 if (cc_status
.value2
!= 0
2950 && ADDRESS_REG_P (cc_status
.value2
)
2951 && GET_MODE (cc_status
.value2
) == QImode
)
2953 if (cc_status
.value2
!= 0
2954 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
2955 switch (GET_CODE (cc_status
.value2
))
2957 case PLUS
: case MINUS
: case MULT
:
2958 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2959 #if 0 /* These instructions always clear the overflow bit */
2960 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2961 case ROTATE
: case ROTATERT
:
2963 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2964 cc_status
.flags
|= CC_NO_OVERFLOW
;
2967 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2968 ends with a move insn moving r2 in r2's mode.
2969 Thus, the cc's are set for r2.
2970 This can set N bit spuriously. */
2971 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2976 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2978 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2979 cc_status
.value2
= 0;
2980 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2981 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
2982 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2983 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
2984 cc_status
.flags
= CC_IN_68881
;
2988 output_move_const_double (operands
)
2991 #ifdef SUPPORT_SUN_FPA
2992 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
2994 int code
= standard_sun_fpa_constant_p (operands
[1]);
2998 static char buf
[40];
3000 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
3003 return "fpmove%.d %1,%0";
3008 int code
= standard_68881_constant_p (operands
[1]);
3012 static char buf
[40];
3014 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
3017 return "fmove%.d %1,%0";
3022 output_move_const_single (operands
)
3025 #ifdef SUPPORT_SUN_FPA
3028 int code
= standard_sun_fpa_constant_p (operands
[1]);
3032 static char buf
[40];
3034 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
3037 return "fpmove%.s %1,%0";
3040 #endif /* defined SUPPORT_SUN_FPA */
3042 int code
= standard_68881_constant_p (operands
[1]);
3046 static char buf
[40];
3048 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
3051 return "fmove%.s %f1,%0";
3055 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3056 from the "fmovecr" instruction.
3057 The value, anded with 0xff, gives the code to use in fmovecr
3058 to get the desired constant. */
3060 /* This code has been fixed for cross-compilation. */
3062 static int inited_68881_table
= 0;
3064 static const char *const strings_68881
[7] = {
3074 static const int codes_68881
[7] = {
3084 REAL_VALUE_TYPE values_68881
[7];
3086 /* Set up values_68881 array by converting the decimal values
3087 strings_68881 to binary. */
3094 enum machine_mode mode
;
3097 for (i
= 0; i
< 7; i
++)
3101 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
3102 values_68881
[i
] = r
;
3104 inited_68881_table
= 1;
3108 standard_68881_constant_p (x
)
3114 #ifdef NO_ASM_FMOVECR
3118 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3119 used at all on those chips. */
3120 if (TARGET_68040
|| TARGET_68060
)
3123 #ifndef REAL_ARITHMETIC
3124 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
3125 if (! flag_pretend_float
)
3130 if (! inited_68881_table
)
3131 init_68881_table ();
3133 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3135 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3137 for (i
= 0; i
< 6; i
++)
3139 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3140 return (codes_68881
[i
]);
3143 if (GET_MODE (x
) == SFmode
)
3146 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3147 return (codes_68881
[6]);
3149 /* larger powers of ten in the constants ram are not used
3150 because they are not equal to a `double' C constant. */
3154 /* If X is a floating-point constant, return the logarithm of X base 2,
3155 or 0 if X is not a power of 2. */
3158 floating_exact_log2 (x
)
3161 REAL_VALUE_TYPE r
, r1
;
3164 #ifndef REAL_ARITHMETIC
3165 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
3166 if (! flag_pretend_float
)
3171 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3173 if (REAL_VALUES_LESS (r
, dconst0
))
3178 while (REAL_VALUES_LESS (r1
, r
))
3180 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
3181 if (REAL_VALUES_EQUAL (r1
, r
))
3188 #ifdef SUPPORT_SUN_FPA
3189 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3190 from the Sun FPA's constant RAM.
3191 The value returned, anded with 0x1ff, gives the code to use in fpmove
3192 to get the desired constant. */
3194 static int inited_FPA_table
= 0;
3196 static const char *const strings_FPA
[38] = {
3197 /* small rationals */
3210 /* Decimal equivalents of double precision values */
3211 "2.718281828459045091", /* D_E */
3212 "6.283185307179586477", /* 2 pi */
3213 "3.141592653589793116", /* D_PI */
3214 "1.570796326794896619", /* pi/2 */
3215 "1.414213562373095145", /* D_SQRT2 */
3216 "0.7071067811865475244", /* 1/sqrt(2) */
3217 "-1.570796326794896619", /* -pi/2 */
3218 "1.442695040888963387", /* D_LOG2ofE */
3219 "3.321928024887362182", /* D_LOG2of10 */
3220 "0.6931471805599452862", /* D_LOGEof2 */
3221 "2.302585092994045901", /* D_LOGEof10 */
3222 "0.3010299956639811980", /* D_LOG10of2 */
3223 "0.4342944819032518167", /* D_LOG10ofE */
3224 /* Decimal equivalents of single precision values */
3225 "2.718281745910644531", /* S_E */
3226 "6.283185307179586477", /* 2 pi */
3227 "3.141592741012573242", /* S_PI */
3228 "1.570796326794896619", /* pi/2 */
3229 "1.414213538169860840", /* S_SQRT2 */
3230 "0.7071067811865475244", /* 1/sqrt(2) */
3231 "-1.570796326794896619", /* -pi/2 */
3232 "1.442695021629333496", /* S_LOG2ofE */
3233 "3.321928024291992188", /* S_LOG2of10 */
3234 "0.6931471824645996094", /* S_LOGEof2 */
3235 "2.302585124969482442", /* S_LOGEof10 */
3236 "0.3010300099849700928", /* S_LOG10of2 */
3237 "0.4342944920063018799", /* S_LOG10ofE */
3241 static const int codes_FPA
[38] = {
3242 /* small rationals */
3255 /* double precision */
3269 /* single precision */
3285 REAL_VALUE_TYPE values_FPA
[38];
3287 /* This code has been fixed for cross-compilation. */
3289 static void init_FPA_table
PARAMS ((void));
3293 enum machine_mode mode
;
3298 for (i
= 0; i
< 38; i
++)
3302 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
3305 inited_FPA_table
= 1;
3310 standard_sun_fpa_constant_p (x
)
3316 #ifndef REAL_ARITHMETIC
3317 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
3318 if (! flag_pretend_float
)
3323 if (! inited_FPA_table
)
3326 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3328 for (i
=0; i
<12; i
++)
3330 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
3331 return (codes_FPA
[i
]);
3334 if (GET_MODE (x
) == SFmode
)
3336 for (i
=25; i
<38; i
++)
3338 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
3339 return (codes_FPA
[i
]);
3344 for (i
=12; i
<25; i
++)
3346 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
3347 return (codes_FPA
[i
]);
3352 #endif /* define SUPPORT_SUN_FPA */
3354 /* A C compound statement to output to stdio stream STREAM the
3355 assembler syntax for an instruction operand X. X is an RTL
3358 CODE is a value that can be used to specify one of several ways
3359 of printing the operand. It is used when identical operands
3360 must be printed differently depending on the context. CODE
3361 comes from the `%' specification that was used to request
3362 printing of the operand. If the specification was just `%DIGIT'
3363 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3364 is the ASCII code for LTR.
3366 If X is a register, this macro should print the register's name.
3367 The names can be found in an array `reg_names' whose type is
3368 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3370 When the machine description has a specification `%PUNCT' (a `%'
3371 followed by a punctuation character), this macro is called with
3372 a null pointer for X and the punctuation character for CODE.
3374 The m68k specific codes are:
3376 '.' for dot needed in Motorola-style opcode names.
3377 '-' for an operand pushing on the stack:
3378 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3379 '+' for an operand pushing on the stack:
3380 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3381 '@' for a reference to the top word on the stack:
3382 sp@, (sp) or (%sp) depending on the style of syntax.
3383 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3384 but & in SGS syntax, $ in CRDS/UNOS syntax).
3385 '!' for the cc register (used in an `and to cc' insn).
3386 '$' for the letter `s' in an op code, but only on the 68040.
3387 '&' for the letter `d' in an op code, but only on the 68040.
3388 '/' for register prefix needed by longlong.h.
3390 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3391 'd' to force memory addressing to be absolute, not relative.
3392 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3393 'o' for operands to go directly to output_operand_address (bypassing
3394 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
3395 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
3396 than directly). Second part of 'y' below.
3397 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3398 or print pair of registers as rx:ry.
3399 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
3400 CONST_DOUBLE's as SunFPA constant RAM registers if
3401 possible, so it should not be used except for the SunFPA.
3406 print_operand (file
, op
, letter
)
3407 FILE *file
; /* file to write to */
3408 rtx op
; /* operand to print */
3409 int letter
; /* %<letter> or 0 */
3411 #ifdef SUPPORT_SUN_FPA
3417 #if defined (MOTOROLA) && !defined (CRDS)
3418 asm_fprintf (file
, ".");
3421 else if (letter
== '#')
3423 asm_fprintf (file
, "%0I");
3425 else if (letter
== '-')
3428 asm_fprintf (file
, "-(%Rsp)");
3430 asm_fprintf (file
, "%Rsp@-");
3433 else if (letter
== '+')
3436 asm_fprintf (file
, "(%Rsp)+");
3438 asm_fprintf (file
, "%Rsp@+");
3441 else if (letter
== '@')
3444 asm_fprintf (file
, "(%Rsp)");
3446 asm_fprintf (file
, "%Rsp@");
3449 else if (letter
== '!')
3451 asm_fprintf (file
, "%Rfpcr");
3453 else if (letter
== '$')
3455 if (TARGET_68040_ONLY
)
3457 fprintf (file
, "s");
3460 else if (letter
== '&')
3462 if (TARGET_68040_ONLY
)
3464 fprintf (file
, "d");
3467 else if (letter
== '/')
3469 asm_fprintf (file
, "%R");
3471 else if (letter
== 'o')
3473 /* This is only for direct addresses with TARGET_PCREL */
3474 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
3477 output_addr_const (file
, XEXP (op
, 0));
3479 else if (GET_CODE (op
) == REG
)
3481 #ifdef SUPPORT_SUN_FPA
3483 && (letter
== 'y' || letter
== 'x')
3484 && GET_MODE (op
) == DFmode
)
3486 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
3487 reg_names
[REGNO (op
)+1]);
3493 /* Print out the second register name of a register pair.
3494 I.e., R (6) => 7. */
3495 fputs (reg_names
[REGNO (op
) + 1], file
);
3497 fputs (reg_names
[REGNO (op
)], file
);
3500 else if (GET_CODE (op
) == MEM
)
3502 output_address (XEXP (op
, 0));
3503 if (letter
== 'd' && ! TARGET_68020
3504 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3505 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3506 && INTVAL (XEXP (op
, 0)) < 0x8000
3507 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3510 fprintf (file
, ".l");
3512 fprintf (file
, ":l");
3516 #ifdef SUPPORT_SUN_FPA
3517 else if ((letter
== 'y' || letter
== 'w')
3518 && GET_CODE (op
) == CONST_DOUBLE
3519 && (i
= standard_sun_fpa_constant_p (op
)))
3521 fprintf (file
, "%%%d", i
& 0x1ff);
3524 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3527 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3528 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3530 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3533 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3534 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3536 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3539 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3540 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3544 /* Use `print_operand_address' instead of `output_addr_const'
3545 to ensure that we print relevant PIC stuff. */
3546 asm_fprintf (file
, "%0I");
3548 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3549 print_operand_address (file
, op
);
3551 output_addr_const (file
, op
);
3556 /* A C compound statement to output to stdio stream STREAM the
3557 assembler syntax for an instruction operand that is a memory
3558 reference whose address is ADDR. ADDR is an RTL expression.
3560 Note that this contains a kludge that knows that the only reason
3561 we have an address (plus (label_ref...) (reg...)) when not generating
3562 PIC code is in the insn before a tablejump, and we know that m68k.md
3563 generates a label LInnn: on such an insn.
3565 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3566 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3568 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3569 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3570 we want. This difference can be accommodated by using an assembler
3571 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3572 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3573 macro. See m68k/sgs.h for an example; for versions without the bug.
3574 Some assemblers refuse all the above solutions. The workaround is to
3575 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3578 They also do not like things like "pea 1.w", so we simple leave off
3579 the .w on small constants.
3581 This routine is responsible for distinguishing between -fpic and -fPIC
3582 style relocations in an address. When generating -fpic code the
3583 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
3584 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
3586 #ifndef ASM_OUTPUT_CASE_FETCH
3589 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
3590 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
3592 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
3593 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
3596 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
3597 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
3599 #endif /* ASM_OUTPUT_CASE_FETCH */
3602 print_operand_address (file
, addr
)
3606 register rtx reg1
, reg2
, breg
, ireg
;
3609 switch (GET_CODE (addr
))
3613 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
3615 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
3620 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
3622 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
3627 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
3629 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
3633 reg1
= reg2
= ireg
= breg
= offset
= 0;
3634 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
3636 offset
= XEXP (addr
, 0);
3637 addr
= XEXP (addr
, 1);
3639 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
3641 offset
= XEXP (addr
, 1);
3642 addr
= XEXP (addr
, 0);
3644 if (GET_CODE (addr
) != PLUS
)
3648 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
3650 reg1
= XEXP (addr
, 0);
3651 addr
= XEXP (addr
, 1);
3653 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
3655 reg1
= XEXP (addr
, 1);
3656 addr
= XEXP (addr
, 0);
3658 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3660 reg1
= XEXP (addr
, 0);
3661 addr
= XEXP (addr
, 1);
3663 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
3665 reg1
= XEXP (addr
, 1);
3666 addr
= XEXP (addr
, 0);
3668 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
3670 reg1
= XEXP (addr
, 0);
3671 addr
= XEXP (addr
, 1);
3673 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3675 reg1
= XEXP (addr
, 1);
3676 addr
= XEXP (addr
, 0);
3678 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3679 || GET_CODE (addr
) == SIGN_EXTEND
)
3691 #if 0 /* for OLD_INDEXING */
3692 else if (GET_CODE (addr
) == PLUS
)
3694 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3696 reg2
= XEXP (addr
, 0);
3697 addr
= XEXP (addr
, 1);
3699 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3701 reg2
= XEXP (addr
, 1);
3702 addr
= XEXP (addr
, 0);
3714 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3715 || GET_CODE (reg1
) == MULT
))
3716 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3721 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3726 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3727 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3730 if (GET_CODE (ireg
) == MULT
)
3732 scale
= INTVAL (XEXP (ireg
, 1));
3733 ireg
= XEXP (ireg
, 0);
3735 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3737 ASM_OUTPUT_CASE_FETCH (file
,
3738 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3739 reg_names
[REGNO (XEXP (ireg
, 0))]);
3740 fprintf (file
, "w");
3744 ASM_OUTPUT_CASE_FETCH (file
,
3745 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3746 reg_names
[REGNO (ireg
)]);
3747 fprintf (file
, "l");
3752 fprintf (file
, "*%d", scale
);
3754 fprintf (file
, ":%d", scale
);
3760 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3761 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3763 ASM_OUTPUT_CASE_FETCH (file
,
3764 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3765 reg_names
[REGNO (breg
)]);
3766 fprintf (file
, "l)");
3769 if (ireg
!= 0 || breg
!= 0)
3776 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
3783 output_addr_const (file
, addr
);
3784 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3786 fprintf (file
, "@GOT");
3788 fprintf (file
, ".w");
3791 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
3797 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
3800 output_addr_const (file
, addr
);
3801 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
3802 fprintf (file
, ":w");
3803 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
3804 fprintf (file
, ":l");
3806 if (addr
!= 0 && ireg
!= 0)
3811 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3813 scale
= INTVAL (XEXP (ireg
, 1));
3814 ireg
= XEXP (ireg
, 0);
3816 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3819 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3821 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3827 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
3829 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
3835 fprintf (file
, "*%d", scale
);
3837 fprintf (file
, ":%d", scale
);
3843 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3844 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3846 ASM_OUTPUT_CASE_FETCH (file
,
3847 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3848 reg_names
[REGNO (reg1
)]);
3849 fprintf (file
, "l)");
3852 /* FALL-THROUGH (is this really what we want?) */
3854 if (GET_CODE (addr
) == CONST_INT
3855 && INTVAL (addr
) < 0x8000
3856 && INTVAL (addr
) >= -0x8000)
3860 /* Many SGS assemblers croak on size specifiers for constants. */
3861 fprintf (file
, "%d", (int) INTVAL (addr
));
3863 fprintf (file
, "%d.w", (int) INTVAL (addr
));
3866 fprintf (file
, "%d:w", (int) INTVAL (addr
));
3869 else if (GET_CODE (addr
) == CONST_INT
)
3871 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3873 else if (TARGET_PCREL
)
3876 output_addr_const (file
, addr
);
3878 asm_fprintf (file
, ":w,%Rpc)");
3880 asm_fprintf (file
, ":l,%Rpc)");
3884 /* Special case for SYMBOL_REF if the symbol name ends in
3885 `.<letter>', this can be mistaken as a size suffix. Put
3886 the name in parentheses. */
3887 if (GET_CODE (addr
) == SYMBOL_REF
3888 && strlen (XSTR (addr
, 0)) > 2
3889 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3892 output_addr_const (file
, addr
);
3896 output_addr_const (file
, addr
);
3902 /* Check for cases where a clr insns can be omitted from code using
3903 strict_low_part sets. For example, the second clrl here is not needed:
3904 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3906 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3907 insn we are checking for redundancy. TARGET is the register set by the
3911 strict_low_part_peephole_ok (mode
, first_insn
, target
)
3912 enum machine_mode mode
;
3918 p
= prev_nonnote_insn (first_insn
);
3922 /* If it isn't an insn, then give up. */
3923 if (GET_CODE (p
) != INSN
)
3926 if (reg_set_p (target
, p
))
3928 rtx set
= single_set (p
);
3931 /* If it isn't an easy to recognize insn, then give up. */
3935 dest
= SET_DEST (set
);
3937 /* If this sets the entire target register to zero, then our
3938 first_insn is redundant. */
3939 if (rtx_equal_p (dest
, target
)
3940 && SET_SRC (set
) == const0_rtx
)
3942 else if (GET_CODE (dest
) == STRICT_LOW_PART
3943 && GET_CODE (XEXP (dest
, 0)) == REG
3944 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3945 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3946 <= GET_MODE_SIZE (mode
)))
3947 /* This is a strict low part set which modifies less than
3948 we are using, so it is safe. */
3954 p
= prev_nonnote_insn (p
);
3961 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3962 range carefully since this predicate is used in DImode contexts. Also, we
3963 need some extra crud to make it work when hosted on 64-bit machines. */
3966 const_uint32_operand (op
, mode
)
3968 enum machine_mode mode
;
3970 /* It doesn't make sense to ask this question with a mode that is
3971 not larger than 32 bits. */
3972 if (GET_MODE_BITSIZE (mode
) <= 32)
3975 #if HOST_BITS_PER_WIDE_INT > 32
3976 /* All allowed constants will fit a CONST_INT. */
3977 return (GET_CODE (op
) == CONST_INT
3978 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3980 return (GET_CODE (op
) == CONST_INT
3981 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3985 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3986 to check the range carefully since this predicate is used in DImode
3990 const_sint32_operand (op
, mode
)
3992 enum machine_mode mode
;
3994 /* It doesn't make sense to ask this question with a mode that is
3995 not larger than 32 bits. */
3996 if (GET_MODE_BITSIZE (mode
) <= 32)
3999 /* All allowed constants will fit a CONST_INT. */
4000 return (GET_CODE (op
) == CONST_INT
4001 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
4004 /* Operand predicates for implementing asymmetric pc-relative addressing
4005 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4006 when used as a source operand, but not as a destintation operand.
4008 We model this by restricting the meaning of the basic predicates
4009 (general_operand, memory_operand, etc) to forbid the use of this
4010 addressing mode, and then define the following predicates that permit
4011 this addressing mode. These predicates can then be used for the
4012 source operands of the appropriate instructions.
4014 n.b. While it is theoretically possible to change all machine patterns
4015 to use this addressing more where permitted by the architecture,
4016 it has only been implemented for "common" cases: SImode, HImode, and
4017 QImode operands, and only for the principle operations that would
4018 require this addressing mode: data movement and simple integer operations.
4020 In parallel with these new predicates, two new constraint letters
4021 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4022 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4023 In the pcrel case 's' is only valid in combination with 'a' registers.
4024 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4025 of how these constraints are used.
4027 The use of these predicates is strictly optional, though patterns that
4028 don't will cause an extra reload register to be allocated where one
4031 lea (abc:w,%pc),%a0 ; need to reload address
4032 moveq &1,%d1 ; since write to pc-relative space
4033 movel %d1,%a0@ ; is not allowed
4035 lea (abc:w,%pc),%a1 ; no need to reload address here
4036 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4038 For more info, consult tiemann@cygnus.com.
4041 All of the ugliness with predicates and constraints is due to the
4042 simple fact that the m68k does not allow a pc-relative addressing
4043 mode as a destination. gcc does not distinguish between source and
4044 destination addresses. Hence, if we claim that pc-relative address
4045 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
4046 end up with invalid code. To get around this problem, we left
4047 pc-relative modes as invalid addresses, and then added special
4048 predicates and constraints to accept them.
4050 A cleaner way to handle this is to modify gcc to distinguish
4051 between source and destination addresses. We can then say that
4052 pc-relative is a valid source address but not a valid destination
4053 address, and hopefully avoid a lot of the predicate and constraint
4054 hackery. Unfortunately, this would be a pretty big change. It would
4055 be a useful change for a number of ports, but there aren't any current
4056 plans to undertake this.
4058 ***************************************************************************/
4061 /* Special case of a general operand that's used as a source operand.
4062 Use this to permit reads from PC-relative memory when -mpcrel
4066 general_src_operand (op
, mode
)
4068 enum machine_mode mode
;
4071 && GET_CODE (op
) == MEM
4072 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
4073 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
4074 || GET_CODE (XEXP (op
, 0)) == CONST
))
4076 return general_operand (op
, mode
);
4079 /* Special case of a nonimmediate operand that's used as a source.
4080 Use this to permit reads from PC-relative memory when -mpcrel
4084 nonimmediate_src_operand (op
, mode
)
4086 enum machine_mode mode
;
4088 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
4089 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
4090 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
4091 || GET_CODE (XEXP (op
, 0)) == CONST
))
4093 return nonimmediate_operand (op
, mode
);
4096 /* Special case of a memory operand that's used as a source.
4097 Use this to permit reads from PC-relative memory when -mpcrel
4101 memory_src_operand (op
, mode
)
4103 enum machine_mode mode
;
4105 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
4106 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
4107 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
4108 || GET_CODE (XEXP (op
, 0)) == CONST
))
4110 return memory_operand (op
, mode
);
4113 /* Predicate that accepts only a pc-relative address. This is needed
4114 because pc-relative addresses don't satisfy the predicate
4115 "general_src_operand". */
4118 pcrel_address (op
, mode
)
4120 enum machine_mode mode ATTRIBUTE_UNUSED
;
4122 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
4123 || GET_CODE (op
) == CONST
);
4127 output_andsi3 (operands
)
4131 if (GET_CODE (operands
[2]) == CONST_INT
4132 && (INTVAL (operands
[2]) | 0xffff) == 0xffffffff
4133 && (DATA_REG_P (operands
[0])
4134 || offsettable_memref_p (operands
[0]))
4137 if (GET_CODE (operands
[0]) != REG
)
4138 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4139 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4140 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4142 if (operands
[2] == const0_rtx
)
4144 return "and%.w %2,%0";
4146 if (GET_CODE (operands
[2]) == CONST_INT
4147 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
4148 && (DATA_REG_P (operands
[0])
4149 || offsettable_memref_p (operands
[0])))
4151 if (DATA_REG_P (operands
[0]))
4153 operands
[1] = GEN_INT (logval
);
4157 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4158 operands
[1] = GEN_INT (logval
% 8);
4160 /* This does not set condition codes in a standard way. */
4162 return "bclr %1,%0";
4164 return "and%.l %2,%0";
4168 output_iorsi3 (operands
)
4171 register int logval
;
4172 if (GET_CODE (operands
[2]) == CONST_INT
4173 && INTVAL (operands
[2]) >> 16 == 0
4174 && (DATA_REG_P (operands
[0])
4175 || offsettable_memref_p (operands
[0]))
4178 if (GET_CODE (operands
[0]) != REG
)
4179 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4180 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4182 if (INTVAL (operands
[2]) == 0xffff)
4183 return "mov%.w %2,%0";
4184 return "or%.w %2,%0";
4186 if (GET_CODE (operands
[2]) == CONST_INT
4187 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
4188 && (DATA_REG_P (operands
[0])
4189 || offsettable_memref_p (operands
[0])))
4191 if (DATA_REG_P (operands
[0]))
4192 operands
[1] = GEN_INT (logval
);
4195 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4196 operands
[1] = GEN_INT (logval
% 8);
4199 return "bset %1,%0";
4201 return "or%.l %2,%0";
4205 output_xorsi3 (operands
)
4208 register int logval
;
4209 if (GET_CODE (operands
[2]) == CONST_INT
4210 && INTVAL (operands
[2]) >> 16 == 0
4211 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4214 if (! DATA_REG_P (operands
[0]))
4215 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4216 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4218 if (INTVAL (operands
[2]) == 0xffff)
4220 return "eor%.w %2,%0";
4222 if (GET_CODE (operands
[2]) == CONST_INT
4223 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
4224 && (DATA_REG_P (operands
[0])
4225 || offsettable_memref_p (operands
[0])))
4227 if (DATA_REG_P (operands
[0]))
4228 operands
[1] = GEN_INT (logval
);
4231 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4232 operands
[1] = GEN_INT (logval
% 8);
4235 return "bchg %1,%0";
4237 return "eor%.l %2,%0";
4240 /* Output assembly to switch to section NAME with attribute FLAGS. */
4243 m68k_coff_asm_named_section (name
, flags
)
4249 if (flags
& SECTION_WRITE
)
4254 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
4257 #ifdef CTOR_LIST_BEGIN
4259 m68k_svr3_asm_out_constructor (symbol
, priority
)
4261 int priority ATTRIBUTE_UNUSED
;
4266 xop
[0] = gen_rtx_MEM (SImode
, gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
));
4269 output_asm_insn (output_move_simode (xop
), xop
);