gcc/reload1.c

   1 /* Reload pseudo regs into hard regs for insns that require hard regs.
   2    Copyright (C) 1987-2015 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24
  25 #include "machmode.h"
  26 #include "hard-reg-set.h"
  27 #include "rtl-error.h"
  28 #include "tm_p.h"
  29 #include "obstack.h"
  30 #include "insn-config.h"
  31 #include "ggc.h"
  32 #include "flags.h"
  33 #include "hashtab.h"
  34 #include "hash-set.h"
  35 #include "vec.h"
  36 #include "input.h"
  37 #include "function.h"
  38 #include "symtab.h"
  39 #include "rtl.h"
  40 #include "statistics.h"
  41 #include "double-int.h"
  42 #include "real.h"
  43 #include "fixed-value.h"
  44 #include "alias.h"
  45 #include "wide-int.h"
  46 #include "inchash.h"
  47 #include "tree.h"
  48 #include "expmed.h"
  49 #include "dojump.h"
  50 #include "explow.h"
  51 #include "calls.h"
  52 #include "emit-rtl.h"
  53 #include "varasm.h"
  54 #include "stmt.h"
  55 #include "expr.h"
  56 #include "insn-codes.h"
  57 #include "optabs.h"
  58 #include "regs.h"
  59 #include "addresses.h"
  60 #include "predict.h"
  61 #include "dominance.h"
  62 #include "cfg.h"
  63 #include "cfgrtl.h"
  64 #include "cfgbuild.h"
  65 #include "basic-block.h"
  66 #include "df.h"
  67 #include "reload.h"
  68 #include "recog.h"
  69 #include "except.h"
  70 #include "ira.h"
  71 #include "target.h"
  72 #include "dumpfile.h"
  73 #include "rtl-iter.h"
  74
  75 /* This file contains the reload pass of the compiler, which is
  76    run after register allocation has been done.  It checks that
  77    each insn is valid (operands required to be in registers really
  78    are in registers of the proper class) and fixes up invalid ones
  79    by copying values temporarily into registers for the insns
  80    that need them.
  81
  82    The results of register allocation are described by the vector
  83    reg_renumber; the insns still contain pseudo regs, but reg_renumber
  84    can be used to find which hard reg, if any, a pseudo reg is in.
  85
  86    The technique we always use is to free up a few hard regs that are
  87    called ``reload regs'', and for each place where a pseudo reg
  88    must be in a hard reg, copy it temporarily into one of the reload regs.
  89
  90    Reload regs are allocated locally for every instruction that needs
  91    reloads.  When there are pseudos which are allocated to a register that
  92    has been chosen as a reload reg, such pseudos must be ``spilled''.
  93    This means that they go to other hard regs, or to stack slots if no other
  94    available hard regs can be found.  Spilling can invalidate more
  95    insns, requiring additional need for reloads, so we must keep checking
  96    until the process stabilizes.
  97
  98    For machines with different classes of registers, we must keep track
  99    of the register class needed for each reload, and make sure that
 100    we allocate enough reload registers of each class.
 101
 102    The file reload.c contains the code that checks one insn for
 103    validity and reports the reloads that it needs.  This file
 104    is in charge of scanning the entire rtl code, accumulating the
 105    reload needs, spilling, assigning reload registers to use for
 106    fixing up each insn, and generating the new insns to copy values
 107    into the reload registers.  */
 108 \f
 109 struct target_reload default_target_reload;
 110 #if SWITCHABLE_TARGET
 111 struct target_reload *this_target_reload = &default_target_reload;
 112 #endif
 113
 114 #define spill_indirect_levels                   \
 115   (this_target_reload->x_spill_indirect_levels)
 116
 117 /* During reload_as_needed, element N contains a REG rtx for the hard reg
 118    into which reg N has been reloaded (perhaps for a previous insn).  */
 119 static rtx *reg_last_reload_reg;
 120
 121 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
 122    for an output reload that stores into reg N.  */
 123 static regset_head reg_has_output_reload;
 124
 125 /* Indicates which hard regs are reload-registers for an output reload
 126    in the current insn.  */
 127 static HARD_REG_SET reg_is_output_reload;
 128
 129 /* Widest width in which each pseudo reg is referred to (via subreg).  */
 130 static unsigned int *reg_max_ref_width;
 131
 132 /* Vector to remember old contents of reg_renumber before spilling.  */
 133 static short *reg_old_renumber;
 134
 135 /* During reload_as_needed, element N contains the last pseudo regno reloaded
 136    into hard register N.  If that pseudo reg occupied more than one register,
 137    reg_reloaded_contents points to that pseudo for each spill register in
 138    use; all of these must remain set for an inheritance to occur.  */
 139 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
 140
 141 /* During reload_as_needed, element N contains the insn for which
 142    hard register N was last used.   Its contents are significant only
 143    when reg_reloaded_valid is set for this register.  */
 144 static rtx_insn *reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
 145
 146 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid.  */
 147 static HARD_REG_SET reg_reloaded_valid;
 148 /* Indicate if the register was dead at the end of the reload.
 149    This is only valid if reg_reloaded_contents is set and valid.  */
 150 static HARD_REG_SET reg_reloaded_dead;
 151
 152 /* Indicate whether the register's current value is one that is not
 153    safe to retain across a call, even for registers that are normally
 154    call-saved.  This is only meaningful for members of reg_reloaded_valid.  */
 155 static HARD_REG_SET reg_reloaded_call_part_clobbered;
 156
 157 /* Number of spill-regs so far; number of valid elements of spill_regs.  */
 158 static int n_spills;
 159
 160 /* In parallel with spill_regs, contains REG rtx's for those regs.
 161    Holds the last rtx used for any given reg, or 0 if it has never
 162    been used for spilling yet.  This rtx is reused, provided it has
 163    the proper mode.  */
 164 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
 165
 166 /* In parallel with spill_regs, contains nonzero for a spill reg
 167    that was stored after the last time it was used.
 168    The precise value is the insn generated to do the store.  */
 169 static rtx_insn *spill_reg_store[FIRST_PSEUDO_REGISTER];
 170
 171 /* This is the register that was stored with spill_reg_store.  This is a
 172    copy of reload_out / reload_out_reg when the value was stored; if
 173    reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg.  */
 174 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
 175
 176 /* This table is the inverse mapping of spill_regs:
 177    indexed by hard reg number,
 178    it contains the position of that reg in spill_regs,
 179    or -1 for something that is not in spill_regs.
 180
 181    ?!?  This is no longer accurate.  */
 182 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
 183
 184 /* This reg set indicates registers that can't be used as spill registers for
 185    the currently processed insn.  These are the hard registers which are live
 186    during the insn, but not allocated to pseudos, as well as fixed
 187    registers.  */
 188 static HARD_REG_SET bad_spill_regs;
 189
 190 /* These are the hard registers that can't be used as spill register for any
 191    insn.  This includes registers used for user variables and registers that
 192    we can't eliminate.  A register that appears in this set also can't be used
 193    to retry register allocation.  */
 194 static HARD_REG_SET bad_spill_regs_global;
 195
 196 /* Describes order of use of registers for reloading
 197    of spilled pseudo-registers.  `n_spills' is the number of
 198    elements that are actually valid; new ones are added at the end.
 199
 200    Both spill_regs and spill_reg_order are used on two occasions:
 201    once during find_reload_regs, where they keep track of the spill registers
 202    for a single insn, but also during reload_as_needed where they show all
 203    the registers ever used by reload.  For the latter case, the information
 204    is calculated during finish_spills.  */
 205 static short spill_regs[FIRST_PSEUDO_REGISTER];
 206
 207 /* This vector of reg sets indicates, for each pseudo, which hard registers
 208    may not be used for retrying global allocation because the register was
 209    formerly spilled from one of them.  If we allowed reallocating a pseudo to
 210    a register that it was already allocated to, reload might not
 211    terminate.  */
 212 static HARD_REG_SET *pseudo_previous_regs;
 213
 214 /* This vector of reg sets indicates, for each pseudo, which hard
 215    registers may not be used for retrying global allocation because they
 216    are used as spill registers during one of the insns in which the
 217    pseudo is live.  */
 218 static HARD_REG_SET *pseudo_forbidden_regs;
 219
 220 /* All hard regs that have been used as spill registers for any insn are
 221    marked in this set.  */
 222 static HARD_REG_SET used_spill_regs;
 223
 224 /* Index of last register assigned as a spill register.  We allocate in
 225    a round-robin fashion.  */
 226 static int last_spill_reg;
 227
 228 /* Record the stack slot for each spilled hard register.  */
 229 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
 230
 231 /* Width allocated so far for that stack slot.  */
 232 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
 233
 234 /* Record which pseudos needed to be spilled.  */
 235 static regset_head spilled_pseudos;
 236
 237 /* Record which pseudos changed their allocation in finish_spills.  */
 238 static regset_head changed_allocation_pseudos;
 239
 240 /* Used for communication between order_regs_for_reload and count_pseudo.
 241    Used to avoid counting one pseudo twice.  */
 242 static regset_head pseudos_counted;
 243
 244 /* First uid used by insns created by reload in this function.
 245    Used in find_equiv_reg.  */
 246 int reload_first_uid;
 247
 248 /* Flag set by local-alloc or global-alloc if anything is live in
 249    a call-clobbered reg across calls.  */
 250 int caller_save_needed;
 251
 252 /* Set to 1 while reload_as_needed is operating.
 253    Required by some machines to handle any generated moves differently.  */
 254 int reload_in_progress = 0;
 255
 256 /* This obstack is used for allocation of rtl during register elimination.
 257    The allocated storage can be freed once find_reloads has processed the
 258    insn.  */
 259 static struct obstack reload_obstack;
 260
 261 /* Points to the beginning of the reload_obstack.  All insn_chain structures
 262    are allocated first.  */
 263 static char *reload_startobj;
 264
 265 /* The point after all insn_chain structures.  Used to quickly deallocate
 266    memory allocated in copy_reloads during calculate_needs_all_insns.  */
 267 static char *reload_firstobj;
 268
 269 /* This points before all local rtl generated by register elimination.
 270    Used to quickly free all memory after processing one insn.  */
 271 static char *reload_insn_firstobj;
 272
 273 /* List of insn_chain instructions, one for every insn that reload needs to
 274    examine.  */
 275 struct insn_chain *reload_insn_chain;
 276
 277 /* TRUE if we potentially left dead insns in the insn stream and want to
 278    run DCE immediately after reload, FALSE otherwise.  */
 279 static bool need_dce;
 280
 281 /* List of all insns needing reloads.  */
 282 static struct insn_chain *insns_need_reload;
 283 \f
 284 /* This structure is used to record information about register eliminations.
 285    Each array entry describes one possible way of eliminating a register
 286    in favor of another.   If there is more than one way of eliminating a
 287    particular register, the most preferred should be specified first.  */
 288
 289 struct elim_table
 290 {
 291   int from;                     /* Register number to be eliminated.  */
 292   int to;                       /* Register number used as replacement.  */
 293   HOST_WIDE_INT initial_offset; /* Initial difference between values.  */
 294   int can_eliminate;            /* Nonzero if this elimination can be done.  */
 295   int can_eliminate_previous;   /* Value returned by TARGET_CAN_ELIMINATE
 296                                    target hook in previous scan over insns
 297                                    made by reload.  */
 298   HOST_WIDE_INT offset;         /* Current offset between the two regs.  */
 299   HOST_WIDE_INT previous_offset;/* Offset at end of previous insn.  */
 300   int ref_outside_mem;          /* "to" has been referenced outside a MEM.  */
 301   rtx from_rtx;                 /* REG rtx for the register to be eliminated.
 302                                    We cannot simply compare the number since
 303                                    we might then spuriously replace a hard
 304                                    register corresponding to a pseudo
 305                                    assigned to the reg to be eliminated.  */
 306   rtx to_rtx;                   /* REG rtx for the replacement.  */
 307 };
 308
 309 static struct elim_table *reg_eliminate = 0;
 310
 311 /* This is an intermediate structure to initialize the table.  It has
 312    exactly the members provided by ELIMINABLE_REGS.  */
 313 static const struct elim_table_1
 314 {
 315   const int from;
 316   const int to;
 317 } reg_eliminate_1[] =
 318
 319 /* If a set of eliminable registers was specified, define the table from it.
 320    Otherwise, default to the normal case of the frame pointer being
 321    replaced by the stack pointer.  */
 322
 323 #ifdef ELIMINABLE_REGS
 324   ELIMINABLE_REGS;
 325 #else
 326   {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
 327 #endif
 328
 329 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
 330
 331 /* Record the number of pending eliminations that have an offset not equal
 332    to their initial offset.  If nonzero, we use a new copy of each
 333    replacement result in any insns encountered.  */
 334 int num_not_at_initial_offset;
 335
 336 /* Count the number of registers that we may be able to eliminate.  */
 337 static int num_eliminable;
 338 /* And the number of registers that are equivalent to a constant that
 339    can be eliminated to frame_pointer / arg_pointer + constant.  */
 340 static int num_eliminable_invariants;
 341
 342 /* For each label, we record the offset of each elimination.  If we reach
 343    a label by more than one path and an offset differs, we cannot do the
 344    elimination.  This information is indexed by the difference of the
 345    number of the label and the first label number.  We can't offset the
 346    pointer itself as this can cause problems on machines with segmented
 347    memory.  The first table is an array of flags that records whether we
 348    have yet encountered a label and the second table is an array of arrays,
 349    one entry in the latter array for each elimination.  */
 350
 351 static int first_label_num;
 352 static char *offsets_known_at;
 353 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
 354
 355 vec<reg_equivs_t, va_gc> *reg_equivs;
 356
 357 /* Stack of addresses where an rtx has been changed.  We can undo the
 358    changes by popping items off the stack and restoring the original
 359    value at each location.
 360
 361    We use this simplistic undo capability rather than copy_rtx as copy_rtx
 362    will not make a deep copy of a normally sharable rtx, such as
 363    (const (plus (symbol_ref) (const_int))).  If such an expression appears
 364    as R1 in gen_reload_chain_without_interm_reg_p, then a shared
 365    rtx expression would be changed.  See PR 42431.  */
 366
 367 typedef rtx *rtx_p;
 368 static vec<rtx_p> substitute_stack;
 369
 370 /* Number of labels in the current function.  */
 371
 372 static int num_labels;
 373 \f
 374 static void replace_pseudos_in (rtx *, machine_mode, rtx);
 375 static void maybe_fix_stack_asms (void);
 376 static void copy_reloads (struct insn_chain *);
 377 static void calculate_needs_all_insns (int);
 378 static int find_reg (struct insn_chain *, int);
 379 static void find_reload_regs (struct insn_chain *);
 380 static void select_reload_regs (void);
 381 static void delete_caller_save_insns (void);
 382
 383 static void spill_failure (rtx_insn *, enum reg_class);
 384 static void count_spilled_pseudo (int, int, int);
 385 static void delete_dead_insn (rtx_insn *);
 386 static void alter_reg (int, int, bool);
 387 static void set_label_offsets (rtx, rtx_insn *, int);
 388 static void check_eliminable_occurrences (rtx);
 389 static void elimination_effects (rtx, machine_mode);
 390 static rtx eliminate_regs_1 (rtx, machine_mode, rtx, bool, bool);
 391 static int eliminate_regs_in_insn (rtx_insn *, int);
 392 static void update_eliminable_offsets (void);
 393 static void mark_not_eliminable (rtx, const_rtx, void *);
 394 static void set_initial_elim_offsets (void);
 395 static bool verify_initial_elim_offsets (void);
 396 static void set_initial_label_offsets (void);
 397 static void set_offsets_for_label (rtx_insn *);
 398 static void init_eliminable_invariants (rtx_insn *, bool);
 399 static void init_elim_table (void);
 400 static void free_reg_equiv (void);
 401 static void update_eliminables (HARD_REG_SET *);
 402 static bool update_eliminables_and_spill (void);
 403 static void elimination_costs_in_insn (rtx_insn *);
 404 static void spill_hard_reg (unsigned int, int);
 405 static int finish_spills (int);
 406 static void scan_paradoxical_subregs (rtx);
 407 static void count_pseudo (int);
 408 static void order_regs_for_reload (struct insn_chain *);
 409 static void reload_as_needed (int);
 410 static void forget_old_reloads_1 (rtx, const_rtx, void *);
 411 static void forget_marked_reloads (regset);
 412 static int reload_reg_class_lower (const void *, const void *);
 413 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
 414                                     machine_mode);
 415 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
 416                                      machine_mode);
 417 static int reload_reg_free_p (unsigned int, int, enum reload_type);
 418 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
 419                                         rtx, rtx, int, int);
 420 static int free_for_value_p (int, machine_mode, int, enum reload_type,
 421                              rtx, rtx, int, int);
 422 static int allocate_reload_reg (struct insn_chain *, int, int);
 423 static int conflicts_with_override (rtx);
 424 static void failed_reload (rtx_insn *, int);
 425 static int set_reload_reg (int, int);
 426 static void choose_reload_regs_init (struct insn_chain *, rtx *);
 427 static void choose_reload_regs (struct insn_chain *);
 428 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
 429                                      rtx, int);
 430 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
 431                                       int);
 432 static void do_input_reload (struct insn_chain *, struct reload *, int);
 433 static void do_output_reload (struct insn_chain *, struct reload *, int);
 434 static void emit_reload_insns (struct insn_chain *);
 435 static void delete_output_reload (rtx_insn *, int, int, rtx);
 436 static void delete_address_reloads (rtx_insn *, rtx_insn *);
 437 static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
 438 static void inc_for_reload (rtx, rtx, rtx, int);
 439 #ifdef AUTO_INC_DEC
 440 static void add_auto_inc_notes (rtx_insn *, rtx);
 441 #endif
 442 static void substitute (rtx *, const_rtx, rtx);
 443 static bool gen_reload_chain_without_interm_reg_p (int, int);
 444 static int reloads_conflict (int, int);
 445 static rtx_insn *gen_reload (rtx, rtx, int, enum reload_type);
 446 static rtx_insn *emit_insn_if_valid_for_reload (rtx);
 447 \f
 448 /* Initialize the reload pass.  This is called at the beginning of compilation
 449    and may be called again if the target is reinitialized.  */
 450
 451 void
 452 init_reload (void)
 453 {
 454   int i;
 455
 456   /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
 457      Set spill_indirect_levels to the number of levels such addressing is
 458      permitted, zero if it is not permitted at all.  */
 459
 460   rtx tem
 461     = gen_rtx_MEM (Pmode,
 462                    gen_rtx_PLUS (Pmode,
 463                                  gen_rtx_REG (Pmode,
 464                                               LAST_VIRTUAL_REGISTER + 1),
 465                                  gen_int_mode (4, Pmode)));
 466   spill_indirect_levels = 0;
 467
 468   while (memory_address_p (QImode, tem))
 469     {
 470       spill_indirect_levels++;
 471       tem = gen_rtx_MEM (Pmode, tem);
 472     }
 473
 474   /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)).  */
 475
 476   tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
 477   indirect_symref_ok = memory_address_p (QImode, tem);
 478
 479   /* See if reg+reg is a valid (and offsettable) address.  */
 480
 481   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 482     {
 483       tem = gen_rtx_PLUS (Pmode,
 484                           gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
 485                           gen_rtx_REG (Pmode, i));
 486
 487       /* This way, we make sure that reg+reg is an offsettable address.  */
 488       tem = plus_constant (Pmode, tem, 4);
 489
 490       if (memory_address_p (QImode, tem))
 491         {
 492           double_reg_address_ok = 1;
 493           break;
 494         }
 495     }
 496
 497   /* Initialize obstack for our rtl allocation.  */
 498   if (reload_startobj == NULL)
 499     {
 500       gcc_obstack_init (&reload_obstack);
 501       reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
 502     }
 503
 504   INIT_REG_SET (&spilled_pseudos);
 505   INIT_REG_SET (&changed_allocation_pseudos);
 506   INIT_REG_SET (&pseudos_counted);
 507 }
 508
 509 /* List of insn chains that are currently unused.  */
 510 static struct insn_chain *unused_insn_chains = 0;
 511
 512 /* Allocate an empty insn_chain structure.  */
 513 struct insn_chain *
 514 new_insn_chain (void)
 515 {
 516   struct insn_chain *c;
 517
 518   if (unused_insn_chains == 0)
 519     {
 520       c = XOBNEW (&reload_obstack, struct insn_chain);
 521       INIT_REG_SET (&c->live_throughout);
 522       INIT_REG_SET (&c->dead_or_set);
 523     }
 524   else
 525     {
 526       c = unused_insn_chains;
 527       unused_insn_chains = c->next;
 528     }
 529   c->is_caller_save_insn = 0;
 530   c->need_operand_change = 0;
 531   c->need_reload = 0;
 532   c->need_elim = 0;
 533   return c;
 534 }
 535
 536 /* Small utility function to set all regs in hard reg set TO which are
 537    allocated to pseudos in regset FROM.  */
 538
 539 void
 540 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
 541 {
 542   unsigned int regno;
 543   reg_set_iterator rsi;
 544
 545   EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
 546     {
 547       int r = reg_renumber[regno];
 548
 549       if (r < 0)
 550         {
 551           /* reload_combine uses the information from DF_LIVE_IN,
 552              which might still contain registers that have not
 553              actually been allocated since they have an
 554              equivalence.  */
 555           gcc_assert (ira_conflicts_p || reload_completed);
 556         }
 557       else
 558         add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
 559     }
 560 }
 561
 562 /* Replace all pseudos found in LOC with their corresponding
 563    equivalences.  */
 564
 565 static void
 566 replace_pseudos_in (rtx *loc, machine_mode mem_mode, rtx usage)
 567 {
 568   rtx x = *loc;
 569   enum rtx_code code;
 570   const char *fmt;
 571   int i, j;
 572
 573   if (! x)
 574     return;
 575
 576   code = GET_CODE (x);
 577   if (code == REG)
 578     {
 579       unsigned int regno = REGNO (x);
 580
 581       if (regno < FIRST_PSEUDO_REGISTER)
 582         return;
 583
 584       x = eliminate_regs_1 (x, mem_mode, usage, true, false);
 585       if (x != *loc)
 586         {
 587           *loc = x;
 588           replace_pseudos_in (loc, mem_mode, usage);
 589           return;
 590         }
 591
 592       if (reg_equiv_constant (regno))
 593         *loc = reg_equiv_constant (regno);
 594       else if (reg_equiv_invariant (regno))
 595         *loc = reg_equiv_invariant (regno);
 596       else if (reg_equiv_mem (regno))
 597         *loc = reg_equiv_mem (regno);
 598       else if (reg_equiv_address (regno))
 599         *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
 600       else
 601         {
 602           gcc_assert (!REG_P (regno_reg_rtx[regno])
 603                       || REGNO (regno_reg_rtx[regno]) != regno);
 604           *loc = regno_reg_rtx[regno];
 605         }
 606
 607       return;
 608     }
 609   else if (code == MEM)
 610     {
 611       replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
 612       return;
 613     }
 614
 615   /* Process each of our operands recursively.  */
 616   fmt = GET_RTX_FORMAT (code);
 617   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
 618     if (*fmt == 'e')
 619       replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
 620     else if (*fmt == 'E')
 621       for (j = 0; j < XVECLEN (x, i); j++)
 622         replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
 623 }
 624
 625 /* Determine if the current function has an exception receiver block
 626    that reaches the exit block via non-exceptional edges  */
 627
 628 static bool
 629 has_nonexceptional_receiver (void)
 630 {
 631   edge e;
 632   edge_iterator ei;
 633   basic_block *tos, *worklist, bb;
 634
 635   /* If we're not optimizing, then just err on the safe side.  */
 636   if (!optimize)
 637     return true;
 638
 639   /* First determine which blocks can reach exit via normal paths.  */
 640   tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1);
 641
 642   FOR_EACH_BB_FN (bb, cfun)
 643     bb->flags &= ~BB_REACHABLE;
 644
 645   /* Place the exit block on our worklist.  */
 646   EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE;
 647   *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun);
 648
 649   /* Iterate: find everything reachable from what we've already seen.  */
 650   while (tos != worklist)
 651     {
 652       bb = *--tos;
 653
 654       FOR_EACH_EDGE (e, ei, bb->preds)
 655         if (!(e->flags & EDGE_ABNORMAL))
 656           {
 657             basic_block src = e->src;
 658
 659             if (!(src->flags & BB_REACHABLE))
 660               {
 661                 src->flags |= BB_REACHABLE;
 662                 *tos++ = src;
 663               }
 664           }
 665     }
 666   free (worklist);
 667
 668   /* Now see if there's a reachable block with an exceptional incoming
 669      edge.  */
 670   FOR_EACH_BB_FN (bb, cfun)
 671     if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
 672       return true;
 673
 674   /* No exceptional block reached exit unexceptionally.  */
 675   return false;
 676 }
 677
 678 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
 679    zero elements) to MAX_REG_NUM elements.
 680
 681    Initialize all new fields to NULL and update REG_EQUIVS_SIZE.  */
 682 void
 683 grow_reg_equivs (void)
 684 {
 685   int old_size = vec_safe_length (reg_equivs);
 686   int max_regno = max_reg_num ();
 687   int i;
 688   reg_equivs_t ze;
 689
 690   memset (&ze, 0, sizeof (reg_equivs_t));
 691   vec_safe_reserve (reg_equivs, max_regno);
 692   for (i = old_size; i < max_regno; i++)
 693     reg_equivs->quick_insert (i, ze);
 694 }
 695
 696 \f
 697 /* Global variables used by reload and its subroutines.  */
 698
 699 /* The current basic block while in calculate_elim_costs_all_insns.  */
 700 static basic_block elim_bb;
 701
 702 /* Set during calculate_needs if an insn needs register elimination.  */
 703 static int something_needs_elimination;
 704 /* Set during calculate_needs if an insn needs an operand changed.  */
 705 static int something_needs_operands_changed;
 706 /* Set by alter_regs if we spilled a register to the stack.  */
 707 static bool something_was_spilled;
 708
 709 /* Nonzero means we couldn't get enough spill regs.  */
 710 static int failure;
 711
 712 /* Temporary array of pseudo-register number.  */
 713 static int *temp_pseudo_reg_arr;
 714
 715 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
 716    If that insn didn't set the register (i.e., it copied the register to
 717    memory), just delete that insn instead of the equivalencing insn plus
 718    anything now dead.  If we call delete_dead_insn on that insn, we may
 719    delete the insn that actually sets the register if the register dies
 720    there and that is incorrect.  */
 721 static void
 722 remove_init_insns ()
 723 {
 724   for (int i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
 725     {
 726       if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
 727         {
 728           rtx list;
 729           for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
 730             {
 731               rtx_insn *equiv_insn = as_a <rtx_insn *> (XEXP (list, 0));
 732
 733               /* If we already deleted the insn or if it may trap, we can't
 734                  delete it.  The latter case shouldn't happen, but can
 735                  if an insn has a variable address, gets a REG_EH_REGION
 736                  note added to it, and then gets converted into a load
 737                  from a constant address.  */
 738               if (NOTE_P (equiv_insn)
 739                   || can_throw_internal (equiv_insn))
 740                 ;
 741               else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
 742                 delete_dead_insn (equiv_insn);
 743               else
 744                 SET_INSN_DELETED (equiv_insn);
 745             }
 746         }
 747     }
 748 }
 749
 750 /* Return true if remove_init_insns will delete INSN.  */
 751 static bool
 752 will_delete_init_insn_p (rtx_insn *insn)
 753 {
 754   rtx set = single_set (insn);
 755   if (!set || !REG_P (SET_DEST (set)))
 756     return false;
 757   unsigned regno = REGNO (SET_DEST (set));
 758
 759   if (can_throw_internal (insn))
 760     return false;
 761
 762   if (regno < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
 763     return false;
 764
 765   for (rtx list = reg_equiv_init (regno); list; list = XEXP (list, 1))
 766     {
 767       rtx equiv_insn = XEXP (list, 0);
 768       if (equiv_insn == insn)
 769         return true;
 770     }
 771   return false;
 772 }
 773
 774 /* Main entry point for the reload pass.
 775
 776    FIRST is the first insn of the function being compiled.
 777
 778    GLOBAL nonzero means we were called from global_alloc
 779    and should attempt to reallocate any pseudoregs that we
 780    displace from hard regs we will use for reloads.
 781    If GLOBAL is zero, we do not have enough information to do that,
 782    so any pseudo reg that is spilled must go to the stack.
 783
 784    Return value is TRUE if reload likely left dead insns in the
 785    stream and a DCE pass should be run to elimiante them.  Else the
 786    return value is FALSE.  */
 787
 788 bool
 789 reload (rtx_insn *first, int global)
 790 {
 791   int i, n;
 792   rtx_insn *insn;
 793   struct elim_table *ep;
 794   basic_block bb;
 795   bool inserted;
 796
 797   /* Make sure even insns with volatile mem refs are recognizable.  */
 798   init_recog ();
 799
 800   failure = 0;
 801
 802   reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
 803
 804   /* Make sure that the last insn in the chain
 805      is not something that needs reloading.  */
 806   emit_note (NOTE_INSN_DELETED);
 807
 808   /* Enable find_equiv_reg to distinguish insns made by reload.  */
 809   reload_first_uid = get_max_uid ();
 810
 811 #ifdef SECONDARY_MEMORY_NEEDED
 812   /* Initialize the secondary memory table.  */
 813   clear_secondary_mem ();
 814 #endif
 815
 816   /* We don't have a stack slot for any spill reg yet.  */
 817   memset (spill_stack_slot, 0, sizeof spill_stack_slot);
 818   memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
 819
 820   /* Initialize the save area information for caller-save, in case some
 821      are needed.  */
 822   init_save_areas ();
 823
 824   /* Compute which hard registers are now in use
 825      as homes for pseudo registers.
 826      This is done here rather than (eg) in global_alloc
 827      because this point is reached even if not optimizing.  */
 828   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
 829     mark_home_live (i);
 830
 831   /* A function that has a nonlocal label that can reach the exit
 832      block via non-exceptional paths must save all call-saved
 833      registers.  */
 834   if (cfun->has_nonlocal_label
 835       && has_nonexceptional_receiver ())
 836     crtl->saves_all_registers = 1;
 837
 838   if (crtl->saves_all_registers)
 839     for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 840       if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
 841         df_set_regs_ever_live (i, true);
 842
 843   /* Find all the pseudo registers that didn't get hard regs
 844      but do have known equivalent constants or memory slots.
 845      These include parameters (known equivalent to parameter slots)
 846      and cse'd or loop-moved constant memory addresses.
 847
 848      Record constant equivalents in reg_equiv_constant
 849      so they will be substituted by find_reloads.
 850      Record memory equivalents in reg_mem_equiv so they can
 851      be substituted eventually by altering the REG-rtx's.  */
 852
 853   grow_reg_equivs ();
 854   reg_old_renumber = XCNEWVEC (short, max_regno);
 855   memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
 856   pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
 857   pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
 858
 859   CLEAR_HARD_REG_SET (bad_spill_regs_global);
 860
 861   init_eliminable_invariants (first, true);
 862   init_elim_table ();
 863
 864   /* Alter each pseudo-reg rtx to contain its hard reg number.  Assign
 865      stack slots to the pseudos that lack hard regs or equivalents.
 866      Do not touch virtual registers.  */
 867
 868   temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
 869   for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
 870     temp_pseudo_reg_arr[n++] = i;
 871
 872   if (ira_conflicts_p)
 873     /* Ask IRA to order pseudo-registers for better stack slot
 874        sharing.  */
 875     ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
 876
 877   for (i = 0; i < n; i++)
 878     alter_reg (temp_pseudo_reg_arr[i], -1, false);
 879
 880   /* If we have some registers we think can be eliminated, scan all insns to
 881      see if there is an insn that sets one of these registers to something
 882      other than itself plus a constant.  If so, the register cannot be
 883      eliminated.  Doing this scan here eliminates an extra pass through the
 884      main reload loop in the most common case where register elimination
 885      cannot be done.  */
 886   for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
 887     if (INSN_P (insn))
 888       note_stores (PATTERN (insn), mark_not_eliminable, NULL);
 889
 890   maybe_fix_stack_asms ();
 891
 892   insns_need_reload = 0;
 893   something_needs_elimination = 0;
 894
 895   /* Initialize to -1, which means take the first spill register.  */
 896   last_spill_reg = -1;
 897
 898   /* Spill any hard regs that we know we can't eliminate.  */
 899   CLEAR_HARD_REG_SET (used_spill_regs);
 900   /* There can be multiple ways to eliminate a register;
 901      they should be listed adjacently.
 902      Elimination for any register fails only if all possible ways fail.  */
 903   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; )
 904     {
 905       int from = ep->from;
 906       int can_eliminate = 0;
 907       do
 908         {
 909           can_eliminate |= ep->can_eliminate;
 910           ep++;
 911         }
 912       while (ep < &reg_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
 913       if (! can_eliminate)
 914         spill_hard_reg (from, 1);
 915     }
 916
 917   if (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed)
 918     spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
 919
 920   finish_spills (global);
 921
 922   /* From now on, we may need to generate moves differently.  We may also
 923      allow modifications of insns which cause them to not be recognized.
 924      Any such modifications will be cleaned up during reload itself.  */
 925   reload_in_progress = 1;
 926
 927   /* This loop scans the entire function each go-round
 928      and repeats until one repetition spills no additional hard regs.  */
 929   for (;;)
 930     {
 931       int something_changed;
 932       int did_spill;
 933       HOST_WIDE_INT starting_frame_size;
 934
 935       starting_frame_size = get_frame_size ();
 936       something_was_spilled = false;
 937
 938       set_initial_elim_offsets ();
 939       set_initial_label_offsets ();
 940
 941       /* For each pseudo register that has an equivalent location defined,
 942          try to eliminate any eliminable registers (such as the frame pointer)
 943          assuming initial offsets for the replacement register, which
 944          is the normal case.
 945
 946          If the resulting location is directly addressable, substitute
 947          the MEM we just got directly for the old REG.
 948
 949          If it is not addressable but is a constant or the sum of a hard reg
 950          and constant, it is probably not addressable because the constant is
 951          out of range, in that case record the address; we will generate
 952          hairy code to compute the address in a register each time it is
 953          needed.  Similarly if it is a hard register, but one that is not
 954          valid as an address register.
 955
 956          If the location is not addressable, but does not have one of the
 957          above forms, assign a stack slot.  We have to do this to avoid the
 958          potential of producing lots of reloads if, e.g., a location involves
 959          a pseudo that didn't get a hard register and has an equivalent memory
 960          location that also involves a pseudo that didn't get a hard register.
 961
 962          Perhaps at some point we will improve reload_when_needed handling
 963          so this problem goes away.  But that's very hairy.  */
 964
 965       for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
 966         if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
 967           {
 968             rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
 969                                     NULL_RTX);
 970
 971             if (strict_memory_address_addr_space_p
 972                   (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
 973                    MEM_ADDR_SPACE (x)))
 974               reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
 975             else if (CONSTANT_P (XEXP (x, 0))
 976                      || (REG_P (XEXP (x, 0))
 977                          && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
 978                      || (GET_CODE (XEXP (x, 0)) == PLUS
 979                          && REG_P (XEXP (XEXP (x, 0), 0))
 980                          && (REGNO (XEXP (XEXP (x, 0), 0))
 981                              < FIRST_PSEUDO_REGISTER)
 982                          && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
 983               reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
 984             else
 985               {
 986                 /* Make a new stack slot.  Then indicate that something
 987                    changed so we go back and recompute offsets for
 988                    eliminable registers because the allocation of memory
 989                    below might change some offset.  reg_equiv_{mem,address}
 990                    will be set up for this pseudo on the next pass around
 991                    the loop.  */
 992                 reg_equiv_memory_loc (i) = 0;
 993                 reg_equiv_init (i) = 0;
 994                 alter_reg (i, -1, true);
 995               }
 996           }
 997
 998       if (caller_save_needed)
 999         setup_save_areas ();
1000
1001       if (starting_frame_size && crtl->stack_alignment_needed)
1002         {
1003           /* If we have a stack frame, we must align it now.  The
1004              stack size may be a part of the offset computation for
1005              register elimination.  So if this changes the stack size,
1006              then repeat the elimination bookkeeping.  We don't
1007              realign when there is no stack, as that will cause a
1008              stack frame when none is needed should
1009              STARTING_FRAME_OFFSET not be already aligned to
1010              STACK_BOUNDARY.  */
1011           assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1012         }
1013       /* If we allocated another stack slot, redo elimination bookkeeping.  */
1014       if (something_was_spilled || starting_frame_size != get_frame_size ())
1015         {
1016           update_eliminables_and_spill ();
1017           continue;
1018         }
1019
1020       if (caller_save_needed)
1021         {
1022           save_call_clobbered_regs ();
1023           /* That might have allocated new insn_chain structures.  */
1024           reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1025         }
1026
1027       calculate_needs_all_insns (global);
1028
1029       if (! ira_conflicts_p)
1030         /* Don't do it for IRA.  We need this info because we don't
1031            change live_throughout and dead_or_set for chains when IRA
1032            is used.  */
1033         CLEAR_REG_SET (&spilled_pseudos);
1034
1035       did_spill = 0;
1036
1037       something_changed = 0;
1038
1039       /* If we allocated any new memory locations, make another pass
1040          since it might have changed elimination offsets.  */
1041       if (something_was_spilled || starting_frame_size != get_frame_size ())
1042         something_changed = 1;
1043
1044       /* Even if the frame size remained the same, we might still have
1045          changed elimination offsets, e.g. if find_reloads called
1046          force_const_mem requiring the back end to allocate a constant
1047          pool base register that needs to be saved on the stack.  */
1048       else if (!verify_initial_elim_offsets ())
1049         something_changed = 1;
1050
1051       if (update_eliminables_and_spill ())
1052         {
1053           did_spill = 1;
1054           something_changed = 1;
1055         }
1056
1057       select_reload_regs ();
1058       if (failure)
1059         goto failed;
1060
1061       if (insns_need_reload != 0 || did_spill)
1062         something_changed |= finish_spills (global);
1063
1064       if (! something_changed)
1065         break;
1066
1067       if (caller_save_needed)
1068         delete_caller_save_insns ();
1069
1070       obstack_free (&reload_obstack, reload_firstobj);
1071     }
1072
1073   /* If global-alloc was run, notify it of any register eliminations we have
1074      done.  */
1075   if (global)
1076     for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1077       if (ep->can_eliminate)
1078         mark_elimination (ep->from, ep->to);
1079
1080   remove_init_insns ();
1081
1082   /* Use the reload registers where necessary
1083      by generating move instructions to move the must-be-register
1084      values into or out of the reload registers.  */
1085
1086   if (insns_need_reload != 0 || something_needs_elimination
1087       || something_needs_operands_changed)
1088     {
1089       HOST_WIDE_INT old_frame_size = get_frame_size ();
1090
1091       reload_as_needed (global);
1092
1093       gcc_assert (old_frame_size == get_frame_size ());
1094
1095       gcc_assert (verify_initial_elim_offsets ());
1096     }
1097
1098   /* If we were able to eliminate the frame pointer, show that it is no
1099      longer live at the start of any basic block.  If it ls live by
1100      virtue of being in a pseudo, that pseudo will be marked live
1101      and hence the frame pointer will be known to be live via that
1102      pseudo.  */
1103
1104   if (! frame_pointer_needed)
1105     FOR_EACH_BB_FN (bb, cfun)
1106       bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1107
1108   /* Come here (with failure set nonzero) if we can't get enough spill
1109      regs.  */
1110  failed:
1111
1112   CLEAR_REG_SET (&changed_allocation_pseudos);
1113   CLEAR_REG_SET (&spilled_pseudos);
1114   reload_in_progress = 0;
1115
1116   /* Now eliminate all pseudo regs by modifying them into
1117      their equivalent memory references.
1118      The REG-rtx's for the pseudos are modified in place,
1119      so all insns that used to refer to them now refer to memory.
1120
1121      For a reg that has a reg_equiv_address, all those insns
1122      were changed by reloading so that no insns refer to it any longer;
1123      but the DECL_RTL of a variable decl may refer to it,
1124      and if so this causes the debugging info to mention the variable.  */
1125
1126   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1127     {
1128       rtx addr = 0;
1129
1130       if (reg_equiv_mem (i))
1131         addr = XEXP (reg_equiv_mem (i), 0);
1132
1133       if (reg_equiv_address (i))
1134         addr = reg_equiv_address (i);
1135
1136       if (addr)
1137         {
1138           if (reg_renumber[i] < 0)
1139             {
1140               rtx reg = regno_reg_rtx[i];
1141
1142               REG_USERVAR_P (reg) = 0;
1143               PUT_CODE (reg, MEM);
1144               XEXP (reg, 0) = addr;
1145               if (reg_equiv_memory_loc (i))
1146                 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1147               else
1148                 MEM_ATTRS (reg) = 0;
1149               MEM_NOTRAP_P (reg) = 1;
1150             }
1151           else if (reg_equiv_mem (i))
1152             XEXP (reg_equiv_mem (i), 0) = addr;
1153         }
1154
1155       /* We don't want complex addressing modes in debug insns
1156          if simpler ones will do, so delegitimize equivalences
1157          in debug insns.  */
1158       if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1159         {
1160           rtx reg = regno_reg_rtx[i];
1161           rtx equiv = 0;
1162           df_ref use, next;
1163
1164           if (reg_equiv_constant (i))
1165             equiv = reg_equiv_constant (i);
1166           else if (reg_equiv_invariant (i))
1167             equiv = reg_equiv_invariant (i);
1168           else if (reg && MEM_P (reg))
1169             equiv = targetm.delegitimize_address (reg);
1170           else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1171             equiv = reg;
1172
1173           if (equiv == reg)
1174             continue;
1175
1176           for (use = DF_REG_USE_CHAIN (i); use; use = next)
1177             {
1178               insn = DF_REF_INSN (use);
1179
1180               /* Make sure the next ref is for a different instruction,
1181                  so that we're not affected by the rescan.  */
1182               next = DF_REF_NEXT_REG (use);
1183               while (next && DF_REF_INSN (next) == insn)
1184                 next = DF_REF_NEXT_REG (next);
1185
1186               if (DEBUG_INSN_P (insn))
1187                 {
1188                   if (!equiv)
1189                     {
1190                       INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1191                       df_insn_rescan_debug_internal (insn);
1192                     }
1193                   else
1194                     INSN_VAR_LOCATION_LOC (insn)
1195                       = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1196                                               reg, equiv);
1197                 }
1198             }
1199         }
1200     }
1201
1202   /* We must set reload_completed now since the cleanup_subreg_operands call
1203      below will re-recognize each insn and reload may have generated insns
1204      which are only valid during and after reload.  */
1205   reload_completed = 1;
1206
1207   /* Make a pass over all the insns and delete all USEs which we inserted
1208      only to tag a REG_EQUAL note on them.  Remove all REG_DEAD and REG_UNUSED
1209      notes.  Delete all CLOBBER insns, except those that refer to the return
1210      value and the special mem:BLK CLOBBERs added to prevent the scheduler
1211      from misarranging variable-array code, and simplify (subreg (reg))
1212      operands.  Strip and regenerate REG_INC notes that may have been moved
1213      around.  */
1214
1215   for (insn = first; insn; insn = NEXT_INSN (insn))
1216     if (INSN_P (insn))
1217       {
1218         rtx *pnote;
1219
1220         if (CALL_P (insn))
1221           replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1222                               VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1223
1224         if ((GET_CODE (PATTERN (insn)) == USE
1225              /* We mark with QImode USEs introduced by reload itself.  */
1226              && (GET_MODE (insn) == QImode
1227                  || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1228             || (GET_CODE (PATTERN (insn)) == CLOBBER
1229                 && (!MEM_P (XEXP (PATTERN (insn), 0))
1230                     || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1231                     || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1232                         && XEXP (XEXP (PATTERN (insn), 0), 0)
1233                                 != stack_pointer_rtx))
1234                 && (!REG_P (XEXP (PATTERN (insn), 0))
1235                     || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1236           {
1237             delete_insn (insn);
1238             continue;
1239           }
1240
1241         /* Some CLOBBERs may survive until here and still reference unassigned
1242            pseudos with const equivalent, which may in turn cause ICE in later
1243            passes if the reference remains in place.  */
1244         if (GET_CODE (PATTERN (insn)) == CLOBBER)
1245           replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1246                               VOIDmode, PATTERN (insn));
1247
1248         /* Discard obvious no-ops, even without -O.  This optimization
1249            is fast and doesn't interfere with debugging.  */
1250         if (NONJUMP_INSN_P (insn)
1251             && GET_CODE (PATTERN (insn)) == SET
1252             && REG_P (SET_SRC (PATTERN (insn)))
1253             && REG_P (SET_DEST (PATTERN (insn)))
1254             && (REGNO (SET_SRC (PATTERN (insn)))
1255                 == REGNO (SET_DEST (PATTERN (insn)))))
1256           {
1257             delete_insn (insn);
1258             continue;
1259           }
1260
1261         pnote = &REG_NOTES (insn);
1262         while (*pnote != 0)
1263           {
1264             if (REG_NOTE_KIND (*pnote) == REG_DEAD
1265                 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1266                 || REG_NOTE_KIND (*pnote) == REG_INC)
1267               *pnote = XEXP (*pnote, 1);
1268             else
1269               pnote = &XEXP (*pnote, 1);
1270           }
1271
1272 #ifdef AUTO_INC_DEC
1273         add_auto_inc_notes (insn, PATTERN (insn));
1274 #endif
1275
1276         /* Simplify (subreg (reg)) if it appears as an operand.  */
1277         cleanup_subreg_operands (insn);
1278
1279         /* Clean up invalid ASMs so that they don't confuse later passes.
1280            See PR 21299.  */
1281         if (asm_noperands (PATTERN (insn)) >= 0)
1282           {
1283             extract_insn (insn);
1284             if (!constrain_operands (1, get_enabled_alternatives (insn)))
1285               {
1286                 error_for_asm (insn,
1287                                "%<asm%> operand has impossible constraints");
1288                 delete_insn (insn);
1289                 continue;
1290               }
1291           }
1292       }
1293
1294   /* If we are doing generic stack checking, give a warning if this
1295      function's frame size is larger than we expect.  */
1296   if (flag_stack_check == GENERIC_STACK_CHECK)
1297     {
1298       HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1299       static int verbose_warned = 0;
1300
1301       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1302         if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1303           size += UNITS_PER_WORD;
1304
1305       if (size > STACK_CHECK_MAX_FRAME_SIZE)
1306         {
1307           warning (0, "frame size too large for reliable stack checking");
1308           if (! verbose_warned)
1309             {
1310               warning (0, "try reducing the number of local variables");
1311               verbose_warned = 1;
1312             }
1313         }
1314     }
1315
1316   free (temp_pseudo_reg_arr);
1317
1318   /* Indicate that we no longer have known memory locations or constants.  */
1319   free_reg_equiv ();
1320
1321   free (reg_max_ref_width);
1322   free (reg_old_renumber);
1323   free (pseudo_previous_regs);
1324   free (pseudo_forbidden_regs);
1325
1326   CLEAR_HARD_REG_SET (used_spill_regs);
1327   for (i = 0; i < n_spills; i++)
1328     SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1329
1330   /* Free all the insn_chain structures at once.  */
1331   obstack_free (&reload_obstack, reload_startobj);
1332   unused_insn_chains = 0;
1333
1334   inserted = fixup_abnormal_edges ();
1335
1336   /* We've possibly turned single trapping insn into multiple ones.  */
1337   if (cfun->can_throw_non_call_exceptions)
1338     {
1339       sbitmap blocks;
1340       blocks = sbitmap_alloc (last_basic_block_for_fn (cfun));
1341       bitmap_ones (blocks);
1342       find_many_sub_basic_blocks (blocks);
1343       sbitmap_free (blocks);
1344     }
1345
1346   if (inserted)
1347     commit_edge_insertions ();
1348
1349   /* Replacing pseudos with their memory equivalents might have
1350      created shared rtx.  Subsequent passes would get confused
1351      by this, so unshare everything here.  */
1352   unshare_all_rtl_again (first);
1353
1354 #ifdef STACK_BOUNDARY
1355   /* init_emit has set the alignment of the hard frame pointer
1356      to STACK_BOUNDARY.  It is very likely no longer valid if
1357      the hard frame pointer was used for register allocation.  */
1358   if (!frame_pointer_needed)
1359     REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1360 #endif
1361
1362   substitute_stack.release ();
1363
1364   gcc_assert (bitmap_empty_p (&spilled_pseudos));
1365
1366   reload_completed = !failure;
1367
1368   return need_dce;
1369 }
1370
1371 /* Yet another special case.  Unfortunately, reg-stack forces people to
1372    write incorrect clobbers in asm statements.  These clobbers must not
1373    cause the register to appear in bad_spill_regs, otherwise we'll call
1374    fatal_insn later.  We clear the corresponding regnos in the live
1375    register sets to avoid this.
1376    The whole thing is rather sick, I'm afraid.  */
1377
1378 static void
1379 maybe_fix_stack_asms (void)
1380 {
1381 #ifdef STACK_REGS
1382   const char *constraints[MAX_RECOG_OPERANDS];
1383   machine_mode operand_mode[MAX_RECOG_OPERANDS];
1384   struct insn_chain *chain;
1385
1386   for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1387     {
1388       int i, noperands;
1389       HARD_REG_SET clobbered, allowed;
1390       rtx pat;
1391
1392       if (! INSN_P (chain->insn)
1393           || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1394         continue;
1395       pat = PATTERN (chain->insn);
1396       if (GET_CODE (pat) != PARALLEL)
1397         continue;
1398
1399       CLEAR_HARD_REG_SET (clobbered);
1400       CLEAR_HARD_REG_SET (allowed);
1401
1402       /* First, make a mask of all stack regs that are clobbered.  */
1403       for (i = 0; i < XVECLEN (pat, 0); i++)
1404         {
1405           rtx t = XVECEXP (pat, 0, i);
1406           if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1407             SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1408         }
1409
1410       /* Get the operand values and constraints out of the insn.  */
1411       decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1412                            constraints, operand_mode, NULL);
1413
1414       /* For every operand, see what registers are allowed.  */
1415       for (i = 0; i < noperands; i++)
1416         {
1417           const char *p = constraints[i];
1418           /* For every alternative, we compute the class of registers allowed
1419              for reloading in CLS, and merge its contents into the reg set
1420              ALLOWED.  */
1421           int cls = (int) NO_REGS;
1422
1423           for (;;)
1424             {
1425               char c = *p;
1426
1427               if (c == '\0' || c == ',' || c == '#')
1428                 {
1429                   /* End of one alternative - mark the regs in the current
1430                      class, and reset the class.  */
1431                   IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1432                   cls = NO_REGS;
1433                   p++;
1434                   if (c == '#')
1435                     do {
1436                       c = *p++;
1437                     } while (c != '\0' && c != ',');
1438                   if (c == '\0')
1439                     break;
1440                   continue;
1441                 }
1442
1443               switch (c)
1444                 {
1445                 case 'g':
1446                   cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1447                   break;
1448
1449                 default:
1450                   enum constraint_num cn = lookup_constraint (p);
1451                   if (insn_extra_address_constraint (cn))
1452                     cls = (int) reg_class_subunion[cls]
1453                       [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1454                                              ADDRESS, SCRATCH)];
1455                   else
1456                     cls = (int) reg_class_subunion[cls]
1457                       [reg_class_for_constraint (cn)];
1458                   break;
1459                 }
1460               p += CONSTRAINT_LEN (c, p);
1461             }
1462         }
1463       /* Those of the registers which are clobbered, but allowed by the
1464          constraints, must be usable as reload registers.  So clear them
1465          out of the life information.  */
1466       AND_HARD_REG_SET (allowed, clobbered);
1467       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1468         if (TEST_HARD_REG_BIT (allowed, i))
1469           {
1470             CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1471             CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1472           }
1473     }
1474
1475 #endif
1476 }
1477 \f
1478 /* Copy the global variables n_reloads and rld into the corresponding elts
1479    of CHAIN.  */
1480 static void
1481 copy_reloads (struct insn_chain *chain)
1482 {
1483   chain->n_reloads = n_reloads;
1484   chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1485   memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1486   reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1487 }
1488
1489 /* Walk the chain of insns, and determine for each whether it needs reloads
1490    and/or eliminations.  Build the corresponding insns_need_reload list, and
1491    set something_needs_elimination as appropriate.  */
1492 static void
1493 calculate_needs_all_insns (int global)
1494 {
1495   struct insn_chain **pprev_reload = &insns_need_reload;
1496   struct insn_chain *chain, *next = 0;
1497
1498   something_needs_elimination = 0;
1499
1500   reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1501   for (chain = reload_insn_chain; chain != 0; chain = next)
1502     {
1503       rtx_insn *insn = chain->insn;
1504
1505       next = chain->next;
1506
1507       /* Clear out the shortcuts.  */
1508       chain->n_reloads = 0;
1509       chain->need_elim = 0;
1510       chain->need_reload = 0;
1511       chain->need_operand_change = 0;
1512
1513       /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1514          include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1515          what effects this has on the known offsets at labels.  */
1516
1517       if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1518           || (INSN_P (insn) && REG_NOTES (insn) != 0))
1519         set_label_offsets (insn, insn, 0);
1520
1521       if (INSN_P (insn))
1522         {
1523           rtx old_body = PATTERN (insn);
1524           int old_code = INSN_CODE (insn);
1525           rtx old_notes = REG_NOTES (insn);
1526           int did_elimination = 0;
1527           int operands_changed = 0;
1528
1529           /* Skip insns that only set an equivalence.  */
1530           if (will_delete_init_insn_p (insn))
1531             continue;
1532
1533           /* If needed, eliminate any eliminable registers.  */
1534           if (num_eliminable || num_eliminable_invariants)
1535             did_elimination = eliminate_regs_in_insn (insn, 0);
1536
1537           /* Analyze the instruction.  */
1538           operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1539                                            global, spill_reg_order);
1540
1541           /* If a no-op set needs more than one reload, this is likely
1542              to be something that needs input address reloads.  We
1543              can't get rid of this cleanly later, and it is of no use
1544              anyway, so discard it now.
1545              We only do this when expensive_optimizations is enabled,
1546              since this complements reload inheritance / output
1547              reload deletion, and it can make debugging harder.  */
1548           if (flag_expensive_optimizations && n_reloads > 1)
1549             {
1550               rtx set = single_set (insn);
1551               if (set
1552                   &&
1553                   ((SET_SRC (set) == SET_DEST (set)
1554                     && REG_P (SET_SRC (set))
1555                     && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1556                    || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1557                        && reg_renumber[REGNO (SET_SRC (set))] < 0
1558                        && reg_renumber[REGNO (SET_DEST (set))] < 0
1559                        && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1560                        && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1561                        && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1562                                        reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1563                 {
1564                   if (ira_conflicts_p)
1565                     /* Inform IRA about the insn deletion.  */
1566                     ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1567                                                    REGNO (SET_SRC (set)));
1568                   delete_insn (insn);
1569                   /* Delete it from the reload chain.  */
1570                   if (chain->prev)
1571                     chain->prev->next = next;
1572                   else
1573                     reload_insn_chain = next;
1574                   if (next)
1575                     next->prev = chain->prev;
1576                   chain->next = unused_insn_chains;
1577                   unused_insn_chains = chain;
1578                   continue;
1579                 }
1580             }
1581           if (num_eliminable)
1582             update_eliminable_offsets ();
1583
1584           /* Remember for later shortcuts which insns had any reloads or
1585              register eliminations.  */
1586           chain->need_elim = did_elimination;
1587           chain->need_reload = n_reloads > 0;
1588           chain->need_operand_change = operands_changed;
1589
1590           /* Discard any register replacements done.  */
1591           if (did_elimination)
1592             {
1593               obstack_free (&reload_obstack, reload_insn_firstobj);
1594               PATTERN (insn) = old_body;
1595               INSN_CODE (insn) = old_code;
1596               REG_NOTES (insn) = old_notes;
1597               something_needs_elimination = 1;
1598             }
1599
1600           something_needs_operands_changed |= operands_changed;
1601
1602           if (n_reloads != 0)
1603             {
1604               copy_reloads (chain);
1605               *pprev_reload = chain;
1606               pprev_reload = &chain->next_need_reload;
1607             }
1608         }
1609     }
1610   *pprev_reload = 0;
1611 }
1612 \f
1613 /* This function is called from the register allocator to set up estimates
1614    for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1615    an invariant.  The structure is similar to calculate_needs_all_insns.  */
1616
1617 void
1618 calculate_elim_costs_all_insns (void)
1619 {
1620   int *reg_equiv_init_cost;
1621   basic_block bb;
1622   int i;
1623
1624   reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1625   init_elim_table ();
1626   init_eliminable_invariants (get_insns (), false);
1627
1628   set_initial_elim_offsets ();
1629   set_initial_label_offsets ();
1630
1631   FOR_EACH_BB_FN (bb, cfun)
1632     {
1633       rtx_insn *insn;
1634       elim_bb = bb;
1635
1636       FOR_BB_INSNS (bb, insn)
1637         {
1638           /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1639              include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1640              what effects this has on the known offsets at labels.  */
1641
1642           if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1643               || (INSN_P (insn) && REG_NOTES (insn) != 0))
1644             set_label_offsets (insn, insn, 0);
1645
1646           if (INSN_P (insn))
1647             {
1648               rtx set = single_set (insn);
1649
1650               /* Skip insns that only set an equivalence.  */
1651               if (set && REG_P (SET_DEST (set))
1652                   && reg_renumber[REGNO (SET_DEST (set))] < 0
1653                   && (reg_equiv_constant (REGNO (SET_DEST (set)))
1654                       || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1655                 {
1656                   unsigned regno = REGNO (SET_DEST (set));
1657                   rtx init = reg_equiv_init (regno);
1658                   if (init)
1659                     {
1660                       rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1661                                                 false, true);
1662                       int cost = set_src_cost (t, optimize_bb_for_speed_p (bb));
1663                       int freq = REG_FREQ_FROM_BB (bb);
1664
1665                       reg_equiv_init_cost[regno] = cost * freq;
1666                       continue;
1667                     }
1668                 }
1669               /* If needed, eliminate any eliminable registers.  */
1670               if (num_eliminable || num_eliminable_invariants)
1671                 elimination_costs_in_insn (insn);
1672
1673               if (num_eliminable)
1674                 update_eliminable_offsets ();
1675             }
1676         }
1677     }
1678   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1679     {
1680       if (reg_equiv_invariant (i))
1681         {
1682           if (reg_equiv_init (i))
1683             {
1684               int cost = reg_equiv_init_cost[i];
1685               if (dump_file)
1686                 fprintf (dump_file,
1687                          "Reg %d has equivalence, initial gains %d\n", i, cost);
1688               if (cost != 0)
1689                 ira_adjust_equiv_reg_cost (i, cost);
1690             }
1691           else
1692             {
1693               if (dump_file)
1694                 fprintf (dump_file,
1695                          "Reg %d had equivalence, but can't be eliminated\n",
1696                          i);
1697               ira_adjust_equiv_reg_cost (i, 0);
1698             }
1699         }
1700     }
1701
1702   free (reg_equiv_init_cost);
1703   free (offsets_known_at);
1704   free (offsets_at);
1705   offsets_at = NULL;
1706   offsets_known_at = NULL;
1707 }
1708 \f
1709 /* Comparison function for qsort to decide which of two reloads
1710    should be handled first.  *P1 and *P2 are the reload numbers.  */
1711
1712 static int
1713 reload_reg_class_lower (const void *r1p, const void *r2p)
1714 {
1715   int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1716   int t;
1717
1718   /* Consider required reloads before optional ones.  */
1719   t = rld[r1].optional - rld[r2].optional;
1720   if (t != 0)
1721     return t;
1722
1723   /* Count all solitary classes before non-solitary ones.  */
1724   t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1725        - (reg_class_size[(int) rld[r1].rclass] == 1));
1726   if (t != 0)
1727     return t;
1728
1729   /* Aside from solitaires, consider all multi-reg groups first.  */
1730   t = rld[r2].nregs - rld[r1].nregs;
1731   if (t != 0)
1732     return t;
1733
1734   /* Consider reloads in order of increasing reg-class number.  */
1735   t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1736   if (t != 0)
1737     return t;
1738
1739   /* If reloads are equally urgent, sort by reload number,
1740      so that the results of qsort leave nothing to chance.  */
1741   return r1 - r2;
1742 }
1743 \f
1744 /* The cost of spilling each hard reg.  */
1745 static int spill_cost[FIRST_PSEUDO_REGISTER];
1746
1747 /* When spilling multiple hard registers, we use SPILL_COST for the first
1748    spilled hard reg and SPILL_ADD_COST for subsequent regs.  SPILL_ADD_COST
1749    only the first hard reg for a multi-reg pseudo.  */
1750 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1751
1752 /* Map of hard regno to pseudo regno currently occupying the hard
1753    reg.  */
1754 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1755
1756 /* Update the spill cost arrays, considering that pseudo REG is live.  */
1757
1758 static void
1759 count_pseudo (int reg)
1760 {
1761   int freq = REG_FREQ (reg);
1762   int r = reg_renumber[reg];
1763   int nregs;
1764
1765   /* Ignore spilled pseudo-registers which can be here only if IRA is used.  */
1766   if (ira_conflicts_p && r < 0)
1767     return;
1768
1769   if (REGNO_REG_SET_P (&pseudos_counted, reg)
1770       || REGNO_REG_SET_P (&spilled_pseudos, reg))
1771     return;
1772
1773   SET_REGNO_REG_SET (&pseudos_counted, reg);
1774
1775   gcc_assert (r >= 0);
1776
1777   spill_add_cost[r] += freq;
1778   nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1779   while (nregs-- > 0)
1780     {
1781       hard_regno_to_pseudo_regno[r + nregs] = reg;
1782       spill_cost[r + nregs] += freq;
1783     }
1784 }
1785
1786 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1787    contents of BAD_SPILL_REGS for the insn described by CHAIN.  */
1788
1789 static void
1790 order_regs_for_reload (struct insn_chain *chain)
1791 {
1792   unsigned i;
1793   HARD_REG_SET used_by_pseudos;
1794   HARD_REG_SET used_by_pseudos2;
1795   reg_set_iterator rsi;
1796
1797   COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1798
1799   memset (spill_cost, 0, sizeof spill_cost);
1800   memset (spill_add_cost, 0, sizeof spill_add_cost);
1801   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1802     hard_regno_to_pseudo_regno[i] = -1;
1803
1804   /* Count number of uses of each hard reg by pseudo regs allocated to it
1805      and then order them by decreasing use.  First exclude hard registers
1806      that are live in or across this insn.  */
1807
1808   REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1809   REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1810   IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1811   IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1812
1813   /* Now find out which pseudos are allocated to it, and update
1814      hard_reg_n_uses.  */
1815   CLEAR_REG_SET (&pseudos_counted);
1816
1817   EXECUTE_IF_SET_IN_REG_SET
1818     (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1819     {
1820       count_pseudo (i);
1821     }
1822   EXECUTE_IF_SET_IN_REG_SET
1823     (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1824     {
1825       count_pseudo (i);
1826     }
1827   CLEAR_REG_SET (&pseudos_counted);
1828 }
1829 \f
1830 /* Vector of reload-numbers showing the order in which the reloads should
1831    be processed.  */
1832 static short reload_order[MAX_RELOADS];
1833
1834 /* This is used to keep track of the spill regs used in one insn.  */
1835 static HARD_REG_SET used_spill_regs_local;
1836
1837 /* We decided to spill hard register SPILLED, which has a size of
1838    SPILLED_NREGS.  Determine how pseudo REG, which is live during the insn,
1839    is affected.  We will add it to SPILLED_PSEUDOS if necessary, and we will
1840    update SPILL_COST/SPILL_ADD_COST.  */
1841
1842 static void
1843 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1844 {
1845   int freq = REG_FREQ (reg);
1846   int r = reg_renumber[reg];
1847   int nregs;
1848
1849   /* Ignore spilled pseudo-registers which can be here only if IRA is used.  */
1850   if (ira_conflicts_p && r < 0)
1851     return;
1852
1853   gcc_assert (r >= 0);
1854
1855   nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1856
1857   if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1858       || spilled + spilled_nregs <= r || r + nregs <= spilled)
1859     return;
1860
1861   SET_REGNO_REG_SET (&spilled_pseudos, reg);
1862
1863   spill_add_cost[r] -= freq;
1864   while (nregs-- > 0)
1865     {
1866       hard_regno_to_pseudo_regno[r + nregs] = -1;
1867       spill_cost[r + nregs] -= freq;
1868     }
1869 }
1870
1871 /* Find reload register to use for reload number ORDER.  */
1872
1873 static int
1874 find_reg (struct insn_chain *chain, int order)
1875 {
1876   int rnum = reload_order[order];
1877   struct reload *rl = rld + rnum;
1878   int best_cost = INT_MAX;
1879   int best_reg = -1;
1880   unsigned int i, j, n;
1881   int k;
1882   HARD_REG_SET not_usable;
1883   HARD_REG_SET used_by_other_reload;
1884   reg_set_iterator rsi;
1885   static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1886   static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1887
1888   COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1889   IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1890   IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1891
1892   CLEAR_HARD_REG_SET (used_by_other_reload);
1893   for (k = 0; k < order; k++)
1894     {
1895       int other = reload_order[k];
1896
1897       if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1898         for (j = 0; j < rld[other].nregs; j++)
1899           SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1900     }
1901
1902   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1903     {
1904 #ifdef REG_ALLOC_ORDER
1905       unsigned int regno = reg_alloc_order[i];
1906 #else
1907       unsigned int regno = i;
1908 #endif
1909
1910       if (! TEST_HARD_REG_BIT (not_usable, regno)
1911           && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1912           && HARD_REGNO_MODE_OK (regno, rl->mode))
1913         {
1914           int this_cost = spill_cost[regno];
1915           int ok = 1;
1916           unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1917
1918           for (j = 1; j < this_nregs; j++)
1919             {
1920               this_cost += spill_add_cost[regno + j];
1921               if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1922                   || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1923                 ok = 0;
1924             }
1925           if (! ok)
1926             continue;
1927
1928           if (ira_conflicts_p)
1929             {
1930               /* Ask IRA to find a better pseudo-register for
1931                  spilling.  */
1932               for (n = j = 0; j < this_nregs; j++)
1933                 {
1934                   int r = hard_regno_to_pseudo_regno[regno + j];
1935
1936                   if (r < 0)
1937                     continue;
1938                   if (n == 0 || regno_pseudo_regs[n - 1] != r)
1939                     regno_pseudo_regs[n++] = r;
1940                 }
1941               regno_pseudo_regs[n++] = -1;
1942               if (best_reg < 0
1943                   || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1944                                                       best_regno_pseudo_regs,
1945                                                       rl->in, rl->out,
1946                                                       chain->insn))
1947                 {
1948                   best_reg = regno;
1949                   for (j = 0;; j++)
1950                     {
1951                       best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1952                       if (regno_pseudo_regs[j] < 0)
1953                         break;
1954                     }
1955                 }
1956               continue;
1957             }
1958
1959           if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1960             this_cost--;
1961           if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1962             this_cost--;
1963           if (this_cost < best_cost
1964               /* Among registers with equal cost, prefer caller-saved ones, or
1965                  use REG_ALLOC_ORDER if it is defined.  */
1966               || (this_cost == best_cost
1967 #ifdef REG_ALLOC_ORDER
1968                   && (inv_reg_alloc_order[regno]
1969                       < inv_reg_alloc_order[best_reg])
1970 #else
1971                   && call_used_regs[regno]
1972                   && ! call_used_regs[best_reg]
1973 #endif
1974                   ))
1975             {
1976               best_reg = regno;
1977               best_cost = this_cost;
1978             }
1979         }
1980     }
1981   if (best_reg == -1)
1982     return 0;
1983
1984   if (dump_file)
1985     fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1986
1987   rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1988   rl->regno = best_reg;
1989
1990   EXECUTE_IF_SET_IN_REG_SET
1991     (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1992     {
1993       count_spilled_pseudo (best_reg, rl->nregs, j);
1994     }
1995
1996   EXECUTE_IF_SET_IN_REG_SET
1997     (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1998     {
1999       count_spilled_pseudo (best_reg, rl->nregs, j);
2000     }
2001
2002   for (i = 0; i < rl->nregs; i++)
2003     {
2004       gcc_assert (spill_cost[best_reg + i] == 0);
2005       gcc_assert (spill_add_cost[best_reg + i] == 0);
2006       gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
2007       SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
2008     }
2009   return 1;
2010 }
2011
2012 /* Find more reload regs to satisfy the remaining need of an insn, which
2013    is given by CHAIN.
2014    Do it by ascending class number, since otherwise a reg
2015    might be spilled for a big class and might fail to count
2016    for a smaller class even though it belongs to that class.  */
2017
2018 static void
2019 find_reload_regs (struct insn_chain *chain)
2020 {
2021   int i;
2022
2023   /* In order to be certain of getting the registers we need,
2024      we must sort the reloads into order of increasing register class.
2025      Then our grabbing of reload registers will parallel the process
2026      that provided the reload registers.  */
2027   for (i = 0; i < chain->n_reloads; i++)
2028     {
2029       /* Show whether this reload already has a hard reg.  */
2030       if (chain->rld[i].reg_rtx)
2031         {
2032           int regno = REGNO (chain->rld[i].reg_rtx);
2033           chain->rld[i].regno = regno;
2034           chain->rld[i].nregs
2035             = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2036         }
2037       else
2038         chain->rld[i].regno = -1;
2039       reload_order[i] = i;
2040     }
2041
2042   n_reloads = chain->n_reloads;
2043   memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2044
2045   CLEAR_HARD_REG_SET (used_spill_regs_local);
2046
2047   if (dump_file)
2048     fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2049
2050   qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2051
2052   /* Compute the order of preference for hard registers to spill.  */
2053
2054   order_regs_for_reload (chain);
2055
2056   for (i = 0; i < n_reloads; i++)
2057     {
2058       int r = reload_order[i];
2059
2060       /* Ignore reloads that got marked inoperative.  */
2061       if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2062           && ! rld[r].optional
2063           && rld[r].regno == -1)
2064         if (! find_reg (chain, i))
2065           {
2066             if (dump_file)
2067               fprintf (dump_file, "reload failure for reload %d\n", r);
2068             spill_failure (chain->insn, rld[r].rclass);
2069             failure = 1;
2070             return;
2071           }
2072     }
2073
2074   COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2075   IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2076
2077   memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2078 }
2079
2080 static void
2081 select_reload_regs (void)
2082 {
2083   struct insn_chain *chain;
2084
2085   /* Try to satisfy the needs for each insn.  */
2086   for (chain = insns_need_reload; chain != 0;
2087        chain = chain->next_need_reload)
2088     find_reload_regs (chain);
2089 }
2090 \f
2091 /* Delete all insns that were inserted by emit_caller_save_insns during
2092    this iteration.  */
2093 static void
2094 delete_caller_save_insns (void)
2095 {
2096   struct insn_chain *c = reload_insn_chain;
2097
2098   while (c != 0)
2099     {
2100       while (c != 0 && c->is_caller_save_insn)
2101         {
2102           struct insn_chain *next = c->next;
2103           rtx_insn *insn = c->insn;
2104
2105           if (c == reload_insn_chain)
2106             reload_insn_chain = next;
2107           delete_insn (insn);
2108
2109           if (next)
2110             next->prev = c->prev;
2111           if (c->prev)
2112             c->prev->next = next;
2113           c->next = unused_insn_chains;
2114           unused_insn_chains = c;
2115           c = next;
2116         }
2117       if (c != 0)
2118         c = c->next;
2119     }
2120 }
2121 \f
2122 /* Handle the failure to find a register to spill.
2123    INSN should be one of the insns which needed this particular spill reg.  */
2124
2125 static void
2126 spill_failure (rtx_insn *insn, enum reg_class rclass)
2127 {
2128   if (asm_noperands (PATTERN (insn)) >= 0)
2129     error_for_asm (insn, "can%'t find a register in class %qs while "
2130                    "reloading %<asm%>",
2131                    reg_class_names[rclass]);
2132   else
2133     {
2134       error ("unable to find a register to spill in class %qs",
2135              reg_class_names[rclass]);
2136
2137       if (dump_file)
2138         {
2139           fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2140           debug_reload_to_stream (dump_file);
2141         }
2142       fatal_insn ("this is the insn:", insn);
2143     }
2144 }
2145 \f
2146 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2147    data that is dead in INSN.  */
2148
2149 static void
2150 delete_dead_insn (rtx_insn *insn)
2151 {
2152   rtx_insn *prev = prev_active_insn (insn);
2153   rtx prev_dest;
2154
2155   /* If the previous insn sets a register that dies in our insn make
2156      a note that we want to run DCE immediately after reload.
2157
2158      We used to delete the previous insn & recurse, but that's wrong for
2159      block local equivalences.  Instead of trying to figure out the exact
2160      circumstances where we can delete the potentially dead insns, just
2161      let DCE do the job.  */
2162   if (prev && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn)
2163       && GET_CODE (PATTERN (prev)) == SET
2164       && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2165       && reg_mentioned_p (prev_dest, PATTERN (insn))
2166       && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2167       && ! side_effects_p (SET_SRC (PATTERN (prev))))
2168     need_dce = 1;
2169
2170   SET_INSN_DELETED (insn);
2171 }
2172
2173 /* Modify the home of pseudo-reg I.
2174    The new home is present in reg_renumber[I].
2175
2176    FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2177    or it may be -1, meaning there is none or it is not relevant.
2178    This is used so that all pseudos spilled from a given hard reg
2179    can share one stack slot.  */
2180
2181 static void
2182 alter_reg (int i, int from_reg, bool dont_share_p)
2183 {
2184   /* When outputting an inline function, this can happen
2185      for a reg that isn't actually used.  */
2186   if (regno_reg_rtx[i] == 0)
2187     return;
2188
2189   /* If the reg got changed to a MEM at rtl-generation time,
2190      ignore it.  */
2191   if (!REG_P (regno_reg_rtx[i]))
2192     return;
2193
2194   /* Modify the reg-rtx to contain the new hard reg
2195      number or else to contain its pseudo reg number.  */
2196   SET_REGNO (regno_reg_rtx[i],
2197              reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2198
2199   /* If we have a pseudo that is needed but has no hard reg or equivalent,
2200      allocate a stack slot for it.  */
2201
2202   if (reg_renumber[i] < 0
2203       && REG_N_REFS (i) > 0
2204       && reg_equiv_constant (i) == 0
2205       && (reg_equiv_invariant (i) == 0
2206           || reg_equiv_init (i) == 0)
2207       && reg_equiv_memory_loc (i) == 0)
2208     {
2209       rtx x = NULL_RTX;
2210       machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2211       unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2212       unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2213       unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2214       unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2215       int adjust = 0;
2216
2217       something_was_spilled = true;
2218
2219       if (ira_conflicts_p)
2220         {
2221           /* Mark the spill for IRA.  */
2222           SET_REGNO_REG_SET (&spilled_pseudos, i);
2223           if (!dont_share_p)
2224             x = ira_reuse_stack_slot (i, inherent_size, total_size);
2225         }
2226
2227       if (x)
2228         ;
2229
2230       /* Each pseudo reg has an inherent size which comes from its own mode,
2231          and a total size which provides room for paradoxical subregs
2232          which refer to the pseudo reg in wider modes.
2233
2234          We can use a slot already allocated if it provides both
2235          enough inherent space and enough total space.
2236          Otherwise, we allocate a new slot, making sure that it has no less
2237          inherent space, and no less total space, then the previous slot.  */
2238       else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2239         {
2240           rtx stack_slot;
2241
2242           /* No known place to spill from => no slot to reuse.  */
2243           x = assign_stack_local (mode, total_size,
2244                                   min_align > inherent_align
2245                                   || total_size > inherent_size ? -1 : 0);
2246
2247           stack_slot = x;
2248
2249           /* Cancel the big-endian correction done in assign_stack_local.
2250              Get the address of the beginning of the slot.  This is so we
2251              can do a big-endian correction unconditionally below.  */
2252           if (BYTES_BIG_ENDIAN)
2253             {
2254               adjust = inherent_size - total_size;
2255               if (adjust)
2256                 stack_slot
2257                   = adjust_address_nv (x, mode_for_size (total_size
2258                                                          * BITS_PER_UNIT,
2259                                                          MODE_INT, 1),
2260                                        adjust);
2261             }
2262
2263           if (! dont_share_p && ira_conflicts_p)
2264             /* Inform IRA about allocation a new stack slot.  */
2265             ira_mark_new_stack_slot (stack_slot, i, total_size);
2266         }
2267
2268       /* Reuse a stack slot if possible.  */
2269       else if (spill_stack_slot[from_reg] != 0
2270                && spill_stack_slot_width[from_reg] >= total_size
2271                && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2272                    >= inherent_size)
2273                && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2274         x = spill_stack_slot[from_reg];
2275
2276       /* Allocate a bigger slot.  */
2277       else
2278         {
2279           /* Compute maximum size needed, both for inherent size
2280              and for total size.  */
2281           rtx stack_slot;
2282
2283           if (spill_stack_slot[from_reg])
2284             {
2285               if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2286                   > inherent_size)
2287                 mode = GET_MODE (spill_stack_slot[from_reg]);
2288               if (spill_stack_slot_width[from_reg] > total_size)
2289                 total_size = spill_stack_slot_width[from_reg];
2290               if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2291                 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2292             }
2293
2294           /* Make a slot with that size.  */
2295           x = assign_stack_local (mode, total_size,
2296                                   min_align > inherent_align
2297                                   || total_size > inherent_size ? -1 : 0);
2298           stack_slot = x;
2299
2300           /* Cancel the  big-endian correction done in assign_stack_local.
2301              Get the address of the beginning of the slot.  This is so we
2302              can do a big-endian correction unconditionally below.  */
2303           if (BYTES_BIG_ENDIAN)
2304             {
2305               adjust = GET_MODE_SIZE (mode) - total_size;
2306               if (adjust)
2307                 stack_slot
2308                   = adjust_address_nv (x, mode_for_size (total_size
2309                                                          * BITS_PER_UNIT,
2310                                                          MODE_INT, 1),
2311                                        adjust);
2312             }
2313
2314           spill_stack_slot[from_reg] = stack_slot;
2315           spill_stack_slot_width[from_reg] = total_size;
2316         }
2317
2318       /* On a big endian machine, the "address" of the slot
2319          is the address of the low part that fits its inherent mode.  */
2320       if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2321         adjust += (total_size - inherent_size);
2322
2323       /* If we have any adjustment to make, or if the stack slot is the
2324          wrong mode, make a new stack slot.  */
2325       x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2326
2327       /* Set all of the memory attributes as appropriate for a spill.  */
2328       set_mem_attrs_for_spill (x);
2329
2330       /* Save the stack slot for later.  */
2331       reg_equiv_memory_loc (i) = x;
2332     }
2333 }
2334
2335 /* Mark the slots in regs_ever_live for the hard regs used by
2336    pseudo-reg number REGNO, accessed in MODE.  */
2337
2338 static void
2339 mark_home_live_1 (int regno, machine_mode mode)
2340 {
2341   int i, lim;
2342
2343   i = reg_renumber[regno];
2344   if (i < 0)
2345     return;
2346   lim = end_hard_regno (mode, i);
2347   while (i < lim)
2348     df_set_regs_ever_live (i++, true);
2349 }
2350
2351 /* Mark the slots in regs_ever_live for the hard regs
2352    used by pseudo-reg number REGNO.  */
2353
2354 void
2355 mark_home_live (int regno)
2356 {
2357   if (reg_renumber[regno] >= 0)
2358     mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2359 }
2360 \f
2361 /* This function handles the tracking of elimination offsets around branches.
2362
2363    X is a piece of RTL being scanned.
2364
2365    INSN is the insn that it came from, if any.
2366
2367    INITIAL_P is nonzero if we are to set the offset to be the initial
2368    offset and zero if we are setting the offset of the label to be the
2369    current offset.  */
2370
2371 static void
2372 set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
2373 {
2374   enum rtx_code code = GET_CODE (x);
2375   rtx tem;
2376   unsigned int i;
2377   struct elim_table *p;
2378
2379   switch (code)
2380     {
2381     case LABEL_REF:
2382       if (LABEL_REF_NONLOCAL_P (x))
2383         return;
2384
2385       x = LABEL_REF_LABEL (x);
2386
2387       /* ... fall through ...  */
2388
2389     case CODE_LABEL:
2390       /* If we know nothing about this label, set the desired offsets.  Note
2391          that this sets the offset at a label to be the offset before a label
2392          if we don't know anything about the label.  This is not correct for
2393          the label after a BARRIER, but is the best guess we can make.  If
2394          we guessed wrong, we will suppress an elimination that might have
2395          been possible had we been able to guess correctly.  */
2396
2397       if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2398         {
2399           for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2400             offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2401               = (initial_p ? reg_eliminate[i].initial_offset
2402                  : reg_eliminate[i].offset);
2403           offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2404         }
2405
2406       /* Otherwise, if this is the definition of a label and it is
2407          preceded by a BARRIER, set our offsets to the known offset of
2408          that label.  */
2409
2410       else if (x == insn
2411                && (tem = prev_nonnote_insn (insn)) != 0
2412                && BARRIER_P (tem))
2413         set_offsets_for_label (insn);
2414       else
2415         /* If neither of the above cases is true, compare each offset
2416            with those previously recorded and suppress any eliminations
2417            where the offsets disagree.  */
2418
2419         for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2420           if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2421               != (initial_p ? reg_eliminate[i].initial_offset
2422                   : reg_eliminate[i].offset))
2423             reg_eliminate[i].can_eliminate = 0;
2424
2425       return;
2426
2427     case JUMP_TABLE_DATA:
2428       set_label_offsets (PATTERN (insn), insn, initial_p);
2429       return;
2430
2431     case JUMP_INSN:
2432       set_label_offsets (PATTERN (insn), insn, initial_p);
2433
2434       /* ... fall through ...  */
2435
2436     case INSN:
2437     case CALL_INSN:
2438       /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2439          to indirectly and hence must have all eliminations at their
2440          initial offsets.  */
2441       for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2442         if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2443           set_label_offsets (XEXP (tem, 0), insn, 1);
2444       return;
2445
2446     case PARALLEL:
2447     case ADDR_VEC:
2448     case ADDR_DIFF_VEC:
2449       /* Each of the labels in the parallel or address vector must be
2450          at their initial offsets.  We want the first field for PARALLEL
2451          and ADDR_VEC and the second field for ADDR_DIFF_VEC.  */
2452
2453       for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2454         set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2455                            insn, initial_p);
2456       return;
2457
2458     case SET:
2459       /* We only care about setting PC.  If the source is not RETURN,
2460          IF_THEN_ELSE, or a label, disable any eliminations not at
2461          their initial offsets.  Similarly if any arm of the IF_THEN_ELSE
2462          isn't one of those possibilities.  For branches to a label,
2463          call ourselves recursively.
2464
2465          Note that this can disable elimination unnecessarily when we have
2466          a non-local goto since it will look like a non-constant jump to
2467          someplace in the current function.  This isn't a significant
2468          problem since such jumps will normally be when all elimination
2469          pairs are back to their initial offsets.  */
2470
2471       if (SET_DEST (x) != pc_rtx)
2472         return;
2473
2474       switch (GET_CODE (SET_SRC (x)))
2475         {
2476         case PC:
2477         case RETURN:
2478           return;
2479
2480         case LABEL_REF:
2481           set_label_offsets (SET_SRC (x), insn, initial_p);
2482           return;
2483
2484         case IF_THEN_ELSE:
2485           tem = XEXP (SET_SRC (x), 1);
2486           if (GET_CODE (tem) == LABEL_REF)
2487             set_label_offsets (LABEL_REF_LABEL (tem), insn, initial_p);
2488           else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2489             break;
2490
2491           tem = XEXP (SET_SRC (x), 2);
2492           if (GET_CODE (tem) == LABEL_REF)
2493             set_label_offsets (LABEL_REF_LABEL (tem), insn, initial_p);
2494           else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2495             break;
2496           return;
2497
2498         default:
2499           break;
2500         }
2501
2502       /* If we reach here, all eliminations must be at their initial
2503          offset because we are doing a jump to a variable address.  */
2504       for (p = reg_eliminate; p < &reg_eliminate[NUM_ELIMINABLE_REGS]; p++)
2505         if (p->offset != p->initial_offset)
2506           p->can_eliminate = 0;
2507       break;
2508
2509     default:
2510       break;
2511     }
2512 }
2513 \f
2514 /* This function examines every reg that occurs in X and adjusts the
2515    costs for its elimination which are gathered by IRA.  INSN is the
2516    insn in which X occurs.  We do not recurse into MEM expressions.  */
2517
2518 static void
2519 note_reg_elim_costly (const_rtx x, rtx insn)
2520 {
2521   subrtx_iterator::array_type array;
2522   FOR_EACH_SUBRTX (iter, array, x, NONCONST)
2523     {
2524       const_rtx x = *iter;
2525       if (MEM_P (x))
2526         iter.skip_subrtxes ();
2527       else if (REG_P (x)
2528                && REGNO (x) >= FIRST_PSEUDO_REGISTER
2529                && reg_equiv_init (REGNO (x))
2530                && reg_equiv_invariant (REGNO (x)))
2531         {
2532           rtx t = reg_equiv_invariant (REGNO (x));
2533           rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2534           int cost = set_src_cost (new_rtx, optimize_bb_for_speed_p (elim_bb));
2535           int freq = REG_FREQ_FROM_BB (elim_bb);
2536
2537           if (cost != 0)
2538             ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2539         }
2540     }
2541 }
2542
2543 /* Scan X and replace any eliminable registers (such as fp) with a
2544    replacement (such as sp), plus an offset.
2545
2546    MEM_MODE is the mode of an enclosing MEM.  We need this to know how
2547    much to adjust a register for, e.g., PRE_DEC.  Also, if we are inside a
2548    MEM, we are allowed to replace a sum of a register and the constant zero
2549    with the register, which we cannot do outside a MEM.  In addition, we need
2550    to record the fact that a register is referenced outside a MEM.
2551
2552    If INSN is an insn, it is the insn containing X.  If we replace a REG
2553    in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2554    CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2555    the REG is being modified.
2556
2557    Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2558    That's used when we eliminate in expressions stored in notes.
2559    This means, do not set ref_outside_mem even if the reference
2560    is outside of MEMs.
2561
2562    If FOR_COSTS is true, we are being called before reload in order to
2563    estimate the costs of keeping registers with an equivalence unallocated.
2564
2565    REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2566    replacements done assuming all offsets are at their initial values.  If
2567    they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2568    encounter, return the actual location so that find_reloads will do
2569    the proper thing.  */
2570
2571 static rtx
2572 eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
2573                   bool may_use_invariant, bool for_costs)
2574 {
2575   enum rtx_code code = GET_CODE (x);
2576   struct elim_table *ep;
2577   int regno;
2578   rtx new_rtx;
2579   int i, j;
2580   const char *fmt;
2581   int copied = 0;
2582
2583   if (! current_function_decl)
2584     return x;
2585
2586   switch (code)
2587     {
2588     CASE_CONST_ANY:
2589     case CONST:
2590     case SYMBOL_REF:
2591     case CODE_LABEL:
2592     case PC:
2593     case CC0:
2594     case ASM_INPUT:
2595     case ADDR_VEC:
2596     case ADDR_DIFF_VEC:
2597     case RETURN:
2598       return x;
2599
2600     case REG:
2601       regno = REGNO (x);
2602
2603       /* First handle the case where we encounter a bare register that
2604          is eliminable.  Replace it with a PLUS.  */
2605       if (regno < FIRST_PSEUDO_REGISTER)
2606         {
2607           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2608                ep++)
2609             if (ep->from_rtx == x && ep->can_eliminate)
2610               return plus_constant (Pmode, ep->to_rtx, ep->previous_offset);
2611
2612         }
2613       else if (reg_renumber && reg_renumber[regno] < 0
2614                && reg_equivs
2615                && reg_equiv_invariant (regno))
2616         {
2617           if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2618             return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2619                                      mem_mode, insn, true, for_costs);
2620           /* There exists at least one use of REGNO that cannot be
2621              eliminated.  Prevent the defining insn from being deleted.  */
2622           reg_equiv_init (regno) = NULL;
2623           if (!for_costs)
2624             alter_reg (regno, -1, true);
2625         }
2626       return x;
2627
2628     /* You might think handling MINUS in a manner similar to PLUS is a
2629        good idea.  It is not.  It has been tried multiple times and every
2630        time the change has had to have been reverted.
2631
2632        Other parts of reload know a PLUS is special (gen_reload for example)
2633        and require special code to handle code a reloaded PLUS operand.
2634
2635        Also consider backends where the flags register is clobbered by a
2636        MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2637        lea instruction comes to mind).  If we try to reload a MINUS, we
2638        may kill the flags register that was holding a useful value.
2639
2640        So, please before trying to handle MINUS, consider reload as a
2641        whole instead of this little section as well as the backend issues.  */
2642     case PLUS:
2643       /* If this is the sum of an eliminable register and a constant, rework
2644          the sum.  */
2645       if (REG_P (XEXP (x, 0))
2646           && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2647           && CONSTANT_P (XEXP (x, 1)))
2648         {
2649           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2650                ep++)
2651             if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2652               {
2653                 /* The only time we want to replace a PLUS with a REG (this
2654                    occurs when the constant operand of the PLUS is the negative
2655                    of the offset) is when we are inside a MEM.  We won't want
2656                    to do so at other times because that would change the
2657                    structure of the insn in a way that reload can't handle.
2658                    We special-case the commonest situation in
2659                    eliminate_regs_in_insn, so just replace a PLUS with a
2660                    PLUS here, unless inside a MEM.  */
2661                 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2662                     && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2663                   return ep->to_rtx;
2664                 else
2665                   return gen_rtx_PLUS (Pmode, ep->to_rtx,
2666                                        plus_constant (Pmode, XEXP (x, 1),
2667                                                       ep->previous_offset));
2668               }
2669
2670           /* If the register is not eliminable, we are done since the other
2671              operand is a constant.  */
2672           return x;
2673         }
2674
2675       /* If this is part of an address, we want to bring any constant to the
2676          outermost PLUS.  We will do this by doing register replacement in
2677          our operands and seeing if a constant shows up in one of them.
2678
2679          Note that there is no risk of modifying the structure of the insn,
2680          since we only get called for its operands, thus we are either
2681          modifying the address inside a MEM, or something like an address
2682          operand of a load-address insn.  */
2683
2684       {
2685         rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2686                                      for_costs);
2687         rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2688                                      for_costs);
2689
2690         if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2691           {
2692             /* If one side is a PLUS and the other side is a pseudo that
2693                didn't get a hard register but has a reg_equiv_constant,
2694                we must replace the constant here since it may no longer
2695                be in the position of any operand.  */
2696             if (GET_CODE (new0) == PLUS && REG_P (new1)
2697                 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2698                 && reg_renumber[REGNO (new1)] < 0
2699                 && reg_equivs
2700                 && reg_equiv_constant (REGNO (new1)) != 0)
2701               new1 = reg_equiv_constant (REGNO (new1));
2702             else if (GET_CODE (new1) == PLUS && REG_P (new0)
2703                      && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2704                      && reg_renumber[REGNO (new0)] < 0
2705                      && reg_equiv_constant (REGNO (new0)) != 0)
2706               new0 = reg_equiv_constant (REGNO (new0));
2707
2708             new_rtx = form_sum (GET_MODE (x), new0, new1);
2709
2710             /* As above, if we are not inside a MEM we do not want to
2711                turn a PLUS into something else.  We might try to do so here
2712                for an addition of 0 if we aren't optimizing.  */
2713             if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2714               return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2715             else
2716               return new_rtx;
2717           }
2718       }
2719       return x;
2720
2721     case MULT:
2722       /* If this is the product of an eliminable register and a
2723          constant, apply the distribute law and move the constant out
2724          so that we have (plus (mult ..) ..).  This is needed in order
2725          to keep load-address insns valid.   This case is pathological.
2726          We ignore the possibility of overflow here.  */
2727       if (REG_P (XEXP (x, 0))
2728           && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2729           && CONST_INT_P (XEXP (x, 1)))
2730         for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2731              ep++)
2732           if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2733             {
2734               if (! mem_mode
2735                   /* Refs inside notes or in DEBUG_INSNs don't count for
2736                      this purpose.  */
2737                   && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2738                                       || GET_CODE (insn) == INSN_LIST
2739                                       || DEBUG_INSN_P (insn))))
2740                 ep->ref_outside_mem = 1;
2741
2742               return
2743                 plus_constant (Pmode,
2744                                gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2745                                ep->previous_offset * INTVAL (XEXP (x, 1)));
2746             }
2747
2748       /* ... fall through ...  */
2749
2750     case CALL:
2751     case COMPARE:
2752     /* See comments before PLUS about handling MINUS.  */
2753     case MINUS:
2754     case DIV:      case UDIV:
2755     case MOD:      case UMOD:
2756     case AND:      case IOR:      case XOR:
2757     case ROTATERT: case ROTATE:
2758     case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2759     case NE:       case EQ:
2760     case GE:       case GT:       case GEU:    case GTU:
2761     case LE:       case LT:       case LEU:    case LTU:
2762       {
2763         rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2764                                      for_costs);
2765         rtx new1 = XEXP (x, 1)
2766           ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2767                               for_costs) : 0;
2768
2769         if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2770           return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2771       }
2772       return x;
2773
2774     case EXPR_LIST:
2775       /* If we have something in XEXP (x, 0), the usual case, eliminate it.  */
2776       if (XEXP (x, 0))
2777         {
2778           new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2779                                       for_costs);
2780           if (new_rtx != XEXP (x, 0))
2781             {
2782               /* If this is a REG_DEAD note, it is not valid anymore.
2783                  Using the eliminated version could result in creating a
2784                  REG_DEAD note for the stack or frame pointer.  */
2785               if (REG_NOTE_KIND (x) == REG_DEAD)
2786                 return (XEXP (x, 1)
2787                         ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2788                                             for_costs)
2789                         : NULL_RTX);
2790
2791               x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2792             }
2793         }
2794
2795       /* ... fall through ...  */
2796
2797     case INSN_LIST:
2798     case INT_LIST:
2799       /* Now do eliminations in the rest of the chain.  If this was
2800          an EXPR_LIST, this might result in allocating more memory than is
2801          strictly needed, but it simplifies the code.  */
2802       if (XEXP (x, 1))
2803         {
2804           new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2805                                       for_costs);
2806           if (new_rtx != XEXP (x, 1))
2807             return
2808               gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2809         }
2810       return x;
2811
2812     case PRE_INC:
2813     case POST_INC:
2814     case PRE_DEC:
2815     case POST_DEC:
2816       /* We do not support elimination of a register that is modified.
2817          elimination_effects has already make sure that this does not
2818          happen.  */
2819       return x;
2820
2821     case PRE_MODIFY:
2822     case POST_MODIFY:
2823       /* We do not support elimination of a register that is modified.
2824          elimination_effects has already make sure that this does not
2825          happen.  The only remaining case we need to consider here is
2826          that the increment value may be an eliminable register.  */
2827       if (GET_CODE (XEXP (x, 1)) == PLUS
2828           && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2829         {
2830           rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2831                                           insn, true, for_costs);
2832
2833           if (new_rtx != XEXP (XEXP (x, 1), 1))
2834             return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2835                                    gen_rtx_PLUS (GET_MODE (x),
2836                                                  XEXP (x, 0), new_rtx));
2837         }
2838       return x;
2839
2840     case STRICT_LOW_PART:
2841     case NEG:          case NOT:
2842     case SIGN_EXTEND:  case ZERO_EXTEND:
2843     case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2844     case FLOAT:        case FIX:
2845     case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2846     case ABS:
2847     case SQRT:
2848     case FFS:
2849     case CLZ:
2850     case CTZ:
2851     case POPCOUNT:
2852     case PARITY:
2853     case BSWAP:
2854       new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2855                                   for_costs);
2856       if (new_rtx != XEXP (x, 0))
2857         return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2858       return x;
2859
2860     case SUBREG:
2861       /* Similar to above processing, but preserve SUBREG_BYTE.
2862          Convert (subreg (mem)) to (mem) if not paradoxical.
2863          Also, if we have a non-paradoxical (subreg (pseudo)) and the
2864          pseudo didn't get a hard reg, we must replace this with the
2865          eliminated version of the memory location because push_reload
2866          may do the replacement in certain circumstances.  */
2867       if (REG_P (SUBREG_REG (x))
2868           && !paradoxical_subreg_p (x)
2869           && reg_equivs
2870           && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2871         {
2872           new_rtx = SUBREG_REG (x);
2873         }
2874       else
2875         new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2876
2877       if (new_rtx != SUBREG_REG (x))
2878         {
2879           int x_size = GET_MODE_SIZE (GET_MODE (x));
2880           int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2881
2882           if (MEM_P (new_rtx)
2883               && ((x_size < new_size
2884 #ifdef WORD_REGISTER_OPERATIONS
2885                    /* On these machines, combine can create rtl of the form
2886                       (set (subreg:m1 (reg:m2 R) 0) ...)
2887                       where m1 < m2, and expects something interesting to
2888                       happen to the entire word.  Moreover, it will use the
2889                       (reg:m2 R) later, expecting all bits to be preserved.
2890                       So if the number of words is the same, preserve the
2891                       subreg so that push_reload can see it.  */
2892                    && ! ((x_size - 1) / UNITS_PER_WORD
2893                          == (new_size -1 ) / UNITS_PER_WORD)
2894 #endif
2895                    )
2896                   || x_size == new_size)
2897               )
2898             return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2899           else
2900             return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2901         }
2902
2903       return x;
2904
2905     case MEM:
2906       /* Our only special processing is to pass the mode of the MEM to our
2907          recursive call and copy the flags.  While we are here, handle this
2908          case more efficiently.  */
2909
2910       new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2911                                   for_costs);
2912       if (for_costs
2913           && memory_address_p (GET_MODE (x), XEXP (x, 0))
2914           && !memory_address_p (GET_MODE (x), new_rtx))
2915         note_reg_elim_costly (XEXP (x, 0), insn);
2916
2917       return replace_equiv_address_nv (x, new_rtx);
2918
2919     case USE:
2920       /* Handle insn_list USE that a call to a pure function may generate.  */
2921       new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2922                                   for_costs);
2923       if (new_rtx != XEXP (x, 0))
2924         return gen_rtx_USE (GET_MODE (x), new_rtx);
2925       return x;
2926
2927     case CLOBBER:
2928     case ASM_OPERANDS:
2929       gcc_assert (insn && DEBUG_INSN_P (insn));
2930       break;
2931
2932     case SET:
2933       gcc_unreachable ();
2934
2935     default:
2936       break;
2937     }
2938
2939   /* Process each of our operands recursively.  If any have changed, make a
2940      copy of the rtx.  */
2941   fmt = GET_RTX_FORMAT (code);
2942   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2943     {
2944       if (*fmt == 'e')
2945         {
2946           new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2947                                       for_costs);
2948           if (new_rtx != XEXP (x, i) && ! copied)
2949             {
2950               x = shallow_copy_rtx (x);
2951               copied = 1;
2952             }
2953           XEXP (x, i) = new_rtx;
2954         }
2955       else if (*fmt == 'E')
2956         {
2957           int copied_vec = 0;
2958           for (j = 0; j < XVECLEN (x, i); j++)
2959             {
2960               new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2961                                           for_costs);
2962               if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2963                 {
2964                   rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2965                                              XVEC (x, i)->elem);
2966                   if (! copied)
2967                     {
2968                       x = shallow_copy_rtx (x);
2969                       copied = 1;
2970                     }
2971                   XVEC (x, i) = new_v;
2972                   copied_vec = 1;
2973                 }
2974               XVECEXP (x, i, j) = new_rtx;
2975             }
2976         }
2977     }
2978
2979   return x;
2980 }
2981
2982 rtx
2983 eliminate_regs (rtx x, machine_mode mem_mode, rtx insn)
2984 {
2985   if (reg_eliminate == NULL)
2986     {
2987       gcc_assert (targetm.no_register_allocation);
2988       return x;
2989     }
2990   return eliminate_regs_1 (x, mem_mode, insn, false, false);
2991 }
2992
2993 /* Scan rtx X for modifications of elimination target registers.  Update
2994    the table of eliminables to reflect the changed state.  MEM_MODE is
2995    the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM.  */
2996
2997 static void
2998 elimination_effects (rtx x, machine_mode mem_mode)
2999 {
3000   enum rtx_code code = GET_CODE (x);
3001   struct elim_table *ep;
3002   int regno;
3003   int i, j;
3004   const char *fmt;
3005
3006   switch (code)
3007     {
3008     CASE_CONST_ANY:
3009     case CONST:
3010     case SYMBOL_REF:
3011     case CODE_LABEL:
3012     case PC:
3013     case CC0:
3014     case ASM_INPUT:
3015     case ADDR_VEC:
3016     case ADDR_DIFF_VEC:
3017     case RETURN:
3018       return;
3019
3020     case REG:
3021       regno = REGNO (x);
3022
3023       /* First handle the case where we encounter a bare register that
3024          is eliminable.  Replace it with a PLUS.  */
3025       if (regno < FIRST_PSEUDO_REGISTER)
3026         {
3027           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3028                ep++)
3029             if (ep->from_rtx == x && ep->can_eliminate)
3030               {
3031                 if (! mem_mode)
3032                   ep->ref_outside_mem = 1;
3033                 return;
3034               }
3035
3036         }
3037       else if (reg_renumber[regno] < 0
3038                && reg_equivs
3039                && reg_equiv_constant (regno)
3040                && ! function_invariant_p (reg_equiv_constant (regno)))
3041         elimination_effects (reg_equiv_constant (regno), mem_mode);
3042       return;
3043
3044     case PRE_INC:
3045     case POST_INC:
3046     case PRE_DEC:
3047     case POST_DEC:
3048     case POST_MODIFY:
3049     case PRE_MODIFY:
3050       /* If we modify the source of an elimination rule, disable it.  */
3051       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3052         if (ep->from_rtx == XEXP (x, 0))
3053           ep->can_eliminate = 0;
3054
3055       /* If we modify the target of an elimination rule by adding a constant,
3056          update its offset.  If we modify the target in any other way, we'll
3057          have to disable the rule as well.  */
3058       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3059         if (ep->to_rtx == XEXP (x, 0))
3060           {
3061             int size = GET_MODE_SIZE (mem_mode);
3062
3063             /* If more bytes than MEM_MODE are pushed, account for them.  */
3064 #ifdef PUSH_ROUNDING
3065             if (ep->to_rtx == stack_pointer_rtx)
3066               size = PUSH_ROUNDING (size);
3067 #endif
3068             if (code == PRE_DEC || code == POST_DEC)
3069               ep->offset += size;
3070             else if (code == PRE_INC || code == POST_INC)
3071               ep->offset -= size;
3072             else if (code == PRE_MODIFY || code == POST_MODIFY)
3073               {
3074                 if (GET_CODE (XEXP (x, 1)) == PLUS
3075                     && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3076                     && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3077                   ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3078                 else
3079                   ep->can_eliminate = 0;
3080               }
3081           }
3082
3083       /* These two aren't unary operators.  */
3084       if (code == POST_MODIFY || code == PRE_MODIFY)
3085         break;
3086
3087       /* Fall through to generic unary operation case.  */
3088     case STRICT_LOW_PART:
3089     case NEG:          case NOT:
3090     case SIGN_EXTEND:  case ZERO_EXTEND:
3091     case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3092     case FLOAT:        case FIX:
3093     case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3094     case ABS:
3095     case SQRT:
3096     case FFS:
3097     case CLZ:
3098     case CTZ:
3099     case POPCOUNT:
3100     case PARITY:
3101     case BSWAP:
3102       elimination_effects (XEXP (x, 0), mem_mode);
3103       return;
3104
3105     case SUBREG:
3106       if (REG_P (SUBREG_REG (x))
3107           && (GET_MODE_SIZE (GET_MODE (x))
3108               <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3109           && reg_equivs
3110           && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3111         return;
3112
3113       elimination_effects (SUBREG_REG (x), mem_mode);
3114       return;
3115
3116     case USE:
3117       /* If using a register that is the source of an eliminate we still
3118          think can be performed, note it cannot be performed since we don't
3119          know how this register is used.  */
3120       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3121         if (ep->from_rtx == XEXP (x, 0))
3122           ep->can_eliminate = 0;
3123
3124       elimination_effects (XEXP (x, 0), mem_mode);
3125       return;
3126
3127     case CLOBBER:
3128       /* If clobbering a register that is the replacement register for an
3129          elimination we still think can be performed, note that it cannot
3130          be performed.  Otherwise, we need not be concerned about it.  */
3131       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3132         if (ep->to_rtx == XEXP (x, 0))
3133           ep->can_eliminate = 0;
3134
3135       elimination_effects (XEXP (x, 0), mem_mode);
3136       return;
3137
3138     case SET:
3139       /* Check for setting a register that we know about.  */
3140       if (REG_P (SET_DEST (x)))
3141         {
3142           /* See if this is setting the replacement register for an
3143              elimination.
3144
3145              If DEST is the hard frame pointer, we do nothing because we
3146              assume that all assignments to the frame pointer are for
3147              non-local gotos and are being done at a time when they are valid
3148              and do not disturb anything else.  Some machines want to
3149              eliminate a fake argument pointer (or even a fake frame pointer)
3150              with either the real frame or the stack pointer.  Assignments to
3151              the hard frame pointer must not prevent this elimination.  */
3152
3153           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3154                ep++)
3155             if (ep->to_rtx == SET_DEST (x)
3156                 && SET_DEST (x) != hard_frame_pointer_rtx)
3157               {
3158                 /* If it is being incremented, adjust the offset.  Otherwise,
3159                    this elimination can't be done.  */
3160                 rtx src = SET_SRC (x);
3161
3162                 if (GET_CODE (src) == PLUS
3163                     && XEXP (src, 0) == SET_DEST (x)
3164                     && CONST_INT_P (XEXP (src, 1)))
3165                   ep->offset -= INTVAL (XEXP (src, 1));
3166                 else
3167                   ep->can_eliminate = 0;
3168               }
3169         }
3170
3171       elimination_effects (SET_DEST (x), VOIDmode);
3172       elimination_effects (SET_SRC (x), VOIDmode);
3173       return;
3174
3175     case MEM:
3176       /* Our only special processing is to pass the mode of the MEM to our
3177          recursive call.  */
3178       elimination_effects (XEXP (x, 0), GET_MODE (x));
3179       return;
3180
3181     default:
3182       break;
3183     }
3184
3185   fmt = GET_RTX_FORMAT (code);
3186   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3187     {
3188       if (*fmt == 'e')
3189         elimination_effects (XEXP (x, i), mem_mode);
3190       else if (*fmt == 'E')
3191         for (j = 0; j < XVECLEN (x, i); j++)
3192           elimination_effects (XVECEXP (x, i, j), mem_mode);
3193     }
3194 }
3195
3196 /* Descend through rtx X and verify that no references to eliminable registers
3197    remain.  If any do remain, mark the involved register as not
3198    eliminable.  */
3199
3200 static void
3201 check_eliminable_occurrences (rtx x)
3202 {
3203   const char *fmt;
3204   int i;
3205   enum rtx_code code;
3206
3207   if (x == 0)
3208     return;
3209
3210   code = GET_CODE (x);
3211
3212   if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3213     {
3214       struct elim_table *ep;
3215
3216       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3217         if (ep->from_rtx == x)
3218           ep->can_eliminate = 0;
3219       return;
3220     }
3221
3222   fmt = GET_RTX_FORMAT (code);
3223   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3224     {
3225       if (*fmt == 'e')
3226         check_eliminable_occurrences (XEXP (x, i));
3227       else if (*fmt == 'E')
3228         {
3229           int j;
3230           for (j = 0; j < XVECLEN (x, i); j++)
3231             check_eliminable_occurrences (XVECEXP (x, i, j));
3232         }
3233     }
3234 }
3235 \f
3236 /* Scan INSN and eliminate all eliminable registers in it.
3237
3238    If REPLACE is nonzero, do the replacement destructively.  Also
3239    delete the insn as dead it if it is setting an eliminable register.
3240
3241    If REPLACE is zero, do all our allocations in reload_obstack.
3242
3243    If no eliminations were done and this insn doesn't require any elimination
3244    processing (these are not identical conditions: it might be updating sp,
3245    but not referencing fp; this needs to be seen during reload_as_needed so
3246    that the offset between fp and sp can be taken into consideration), zero
3247    is returned.  Otherwise, 1 is returned.  */
3248
3249 static int
3250 eliminate_regs_in_insn (rtx_insn *insn, int replace)
3251 {
3252   int icode = recog_memoized (insn);
3253   rtx old_body = PATTERN (insn);
3254   int insn_is_asm = asm_noperands (old_body) >= 0;
3255   rtx old_set = single_set (insn);
3256   rtx new_body;
3257   int val = 0;
3258   int i;
3259   rtx substed_operand[MAX_RECOG_OPERANDS];
3260   rtx orig_operand[MAX_RECOG_OPERANDS];
3261   struct elim_table *ep;
3262   rtx plus_src, plus_cst_src;
3263
3264   if (! insn_is_asm && icode < 0)
3265     {
3266       gcc_assert (DEBUG_INSN_P (insn)
3267                   || GET_CODE (PATTERN (insn)) == USE
3268                   || GET_CODE (PATTERN (insn)) == CLOBBER
3269                   || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3270       if (DEBUG_INSN_P (insn))
3271         INSN_VAR_LOCATION_LOC (insn)
3272           = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3273       return 0;
3274     }
3275
3276   if (old_set != 0 && REG_P (SET_DEST (old_set))
3277       && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3278     {
3279       /* Check for setting an eliminable register.  */
3280       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3281         if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3282           {
3283             /* If this is setting the frame pointer register to the
3284                hardware frame pointer register and this is an elimination
3285                that will be done (tested above), this insn is really
3286                adjusting the frame pointer downward to compensate for
3287                the adjustment done before a nonlocal goto.  */
3288             if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
3289                 && ep->from == FRAME_POINTER_REGNUM
3290                 && ep->to == HARD_FRAME_POINTER_REGNUM)
3291               {
3292                 rtx base = SET_SRC (old_set);
3293                 rtx_insn *base_insn = insn;
3294                 HOST_WIDE_INT offset = 0;
3295
3296                 while (base != ep->to_rtx)
3297                   {
3298                     rtx_insn *prev_insn;
3299                     rtx prev_set;
3300
3301                     if (GET_CODE (base) == PLUS
3302                         && CONST_INT_P (XEXP (base, 1)))
3303                       {
3304                         offset += INTVAL (XEXP (base, 1));
3305                         base = XEXP (base, 0);
3306                       }
3307                     else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3308                              && (prev_set = single_set (prev_insn)) != 0
3309                              && rtx_equal_p (SET_DEST (prev_set), base))
3310                       {
3311                         base = SET_SRC (prev_set);
3312                         base_insn = prev_insn;
3313                       }
3314                     else
3315                       break;
3316                   }
3317
3318                 if (base == ep->to_rtx)
3319                   {
3320                     rtx src = plus_constant (Pmode, ep->to_rtx,
3321                                              offset - ep->offset);
3322
3323                     new_body = old_body;
3324                     if (! replace)
3325                       {
3326                         new_body = copy_insn (old_body);
3327                         if (REG_NOTES (insn))
3328                           REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3329                       }
3330                     PATTERN (insn) = new_body;
3331                     old_set = single_set (insn);
3332
3333                     /* First see if this insn remains valid when we
3334                        make the change.  If not, keep the INSN_CODE
3335                        the same and let reload fit it up.  */
3336                     validate_change (insn, &SET_SRC (old_set), src, 1);
3337                     validate_change (insn, &SET_DEST (old_set),
3338                                      ep->to_rtx, 1);
3339                     if (! apply_change_group ())
3340                       {
3341                         SET_SRC (old_set) = src;
3342                         SET_DEST (old_set) = ep->to_rtx;
3343                       }
3344
3345                     val = 1;
3346                     goto done;
3347                   }
3348               }
3349
3350             /* In this case this insn isn't serving a useful purpose.  We
3351                will delete it in reload_as_needed once we know that this
3352                elimination is, in fact, being done.
3353
3354                If REPLACE isn't set, we can't delete this insn, but needn't
3355                process it since it won't be used unless something changes.  */
3356             if (replace)
3357               {
3358                 delete_dead_insn (insn);
3359                 return 1;
3360               }
3361             val = 1;
3362             goto done;
3363           }
3364     }
3365
3366   /* We allow one special case which happens to work on all machines we
3367      currently support: a single set with the source or a REG_EQUAL
3368      note being a PLUS of an eliminable register and a constant.  */
3369   plus_src = plus_cst_src = 0;
3370   if (old_set && REG_P (SET_DEST (old_set)))
3371     {
3372       if (GET_CODE (SET_SRC (old_set)) == PLUS)
3373         plus_src = SET_SRC (old_set);
3374       /* First see if the source is of the form (plus (...) CST).  */
3375       if (plus_src
3376           && CONST_INT_P (XEXP (plus_src, 1)))
3377         plus_cst_src = plus_src;
3378       else if (REG_P (SET_SRC (old_set))
3379                || plus_src)
3380         {
3381           /* Otherwise, see if we have a REG_EQUAL note of the form
3382              (plus (...) CST).  */
3383           rtx links;
3384           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3385             {
3386               if ((REG_NOTE_KIND (links) == REG_EQUAL
3387                    || REG_NOTE_KIND (links) == REG_EQUIV)
3388                   && GET_CODE (XEXP (links, 0)) == PLUS
3389                   && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3390                 {
3391                   plus_cst_src = XEXP (links, 0);
3392                   break;
3393                 }
3394             }
3395         }
3396
3397       /* Check that the first operand of the PLUS is a hard reg or
3398          the lowpart subreg of one.  */
3399       if (plus_cst_src)
3400         {
3401           rtx reg = XEXP (plus_cst_src, 0);
3402           if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3403             reg = SUBREG_REG (reg);
3404
3405           if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3406             plus_cst_src = 0;
3407         }
3408     }
3409   if (plus_cst_src)
3410     {
3411       rtx reg = XEXP (plus_cst_src, 0);
3412       HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3413
3414       if (GET_CODE (reg) == SUBREG)
3415         reg = SUBREG_REG (reg);
3416
3417       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3418         if (ep->from_rtx == reg && ep->can_eliminate)
3419           {
3420             rtx to_rtx = ep->to_rtx;
3421             offset += ep->offset;
3422             offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3423
3424             if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3425               to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3426                                     to_rtx);
3427             /* If we have a nonzero offset, and the source is already
3428                a simple REG, the following transformation would
3429                increase the cost of the insn by replacing a simple REG
3430                with (plus (reg sp) CST).  So try only when we already
3431                had a PLUS before.  */
3432             if (offset == 0 || plus_src)
3433               {
3434                 rtx new_src = plus_constant (GET_MODE (to_rtx),
3435                                              to_rtx, offset);
3436
3437                 new_body = old_body;
3438                 if (! replace)
3439                   {
3440                     new_body = copy_insn (old_body);
3441                     if (REG_NOTES (insn))
3442                       REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3443                   }
3444                 PATTERN (insn) = new_body;
3445                 old_set = single_set (insn);
3446
3447                 /* First see if this insn remains valid when we make the
3448                    change.  If not, try to replace the whole pattern with
3449                    a simple set (this may help if the original insn was a
3450                    PARALLEL that was only recognized as single_set due to
3451                    REG_UNUSED notes).  If this isn't valid either, keep
3452                    the INSN_CODE the same and let reload fix it up.  */
3453                 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3454                   {
3455                     rtx new_pat = gen_rtx_SET (VOIDmode,
3456                                                SET_DEST (old_set), new_src);
3457
3458                     if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3459                       SET_SRC (old_set) = new_src;
3460                   }
3461               }
3462             else
3463               break;
3464
3465             val = 1;
3466             /* This can't have an effect on elimination offsets, so skip right
3467                to the end.  */
3468             goto done;
3469           }
3470     }
3471
3472   /* Determine the effects of this insn on elimination offsets.  */
3473   elimination_effects (old_body, VOIDmode);
3474
3475   /* Eliminate all eliminable registers occurring in operands that
3476      can be handled by reload.  */
3477   extract_insn (insn);
3478   for (i = 0; i < recog_data.n_operands; i++)
3479     {
3480       orig_operand[i] = recog_data.operand[i];
3481       substed_operand[i] = recog_data.operand[i];
3482
3483       /* For an asm statement, every operand is eliminable.  */
3484       if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3485         {
3486           bool is_set_src, in_plus;
3487
3488           /* Check for setting a register that we know about.  */
3489           if (recog_data.operand_type[i] != OP_IN
3490               && REG_P (orig_operand[i]))
3491             {
3492               /* If we are assigning to a register that can be eliminated, it
3493                  must be as part of a PARALLEL, since the code above handles
3494                  single SETs.  We must indicate that we can no longer
3495                  eliminate this reg.  */
3496               for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3497                    ep++)
3498                 if (ep->from_rtx == orig_operand[i])
3499                   ep->can_eliminate = 0;
3500             }
3501
3502           /* Companion to the above plus substitution, we can allow
3503              invariants as the source of a plain move.  */
3504           is_set_src = false;
3505           if (old_set
3506               && recog_data.operand_loc[i] == &SET_SRC (old_set))
3507             is_set_src = true;
3508           in_plus = false;
3509           if (plus_src
3510               && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3511                   || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3512             in_plus = true;
3513
3514           substed_operand[i]
3515             = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3516                                 replace ? insn : NULL_RTX,
3517                                 is_set_src || in_plus, false);
3518           if (substed_operand[i] != orig_operand[i])
3519             val = 1;
3520           /* Terminate the search in check_eliminable_occurrences at
3521              this point.  */
3522           *recog_data.operand_loc[i] = 0;
3523
3524           /* If an output operand changed from a REG to a MEM and INSN is an
3525              insn, write a CLOBBER insn.  */
3526           if (recog_data.operand_type[i] != OP_IN
3527               && REG_P (orig_operand[i])
3528               && MEM_P (substed_operand[i])
3529               && replace)
3530             emit_insn_after (gen_clobber (orig_operand[i]), insn);
3531         }
3532     }
3533
3534   for (i = 0; i < recog_data.n_dups; i++)
3535     *recog_data.dup_loc[i]
3536       = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3537
3538   /* If any eliminable remain, they aren't eliminable anymore.  */
3539   check_eliminable_occurrences (old_body);
3540
3541   /* Substitute the operands; the new values are in the substed_operand
3542      array.  */
3543   for (i = 0; i < recog_data.n_operands; i++)
3544     *recog_data.operand_loc[i] = substed_operand[i];
3545   for (i = 0; i < recog_data.n_dups; i++)
3546     *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3547
3548   /* If we are replacing a body that was a (set X (plus Y Z)), try to
3549      re-recognize the insn.  We do this in case we had a simple addition
3550      but now can do this as a load-address.  This saves an insn in this
3551      common case.
3552      If re-recognition fails, the old insn code number will still be used,
3553      and some register operands may have changed into PLUS expressions.
3554      These will be handled by find_reloads by loading them into a register
3555      again.  */
3556
3557   if (val)
3558     {
3559       /* If we aren't replacing things permanently and we changed something,
3560          make another copy to ensure that all the RTL is new.  Otherwise
3561          things can go wrong if find_reload swaps commutative operands
3562          and one is inside RTL that has been copied while the other is not.  */
3563       new_body = old_body;
3564       if (! replace)
3565         {
3566           new_body = copy_insn (old_body);
3567           if (REG_NOTES (insn))
3568             REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3569         }
3570       PATTERN (insn) = new_body;
3571
3572       /* If we had a move insn but now we don't, rerecognize it.  This will
3573          cause spurious re-recognition if the old move had a PARALLEL since
3574          the new one still will, but we can't call single_set without
3575          having put NEW_BODY into the insn and the re-recognition won't
3576          hurt in this rare case.  */
3577       /* ??? Why this huge if statement - why don't we just rerecognize the
3578          thing always?  */
3579       if (! insn_is_asm
3580           && old_set != 0
3581           && ((REG_P (SET_SRC (old_set))
3582                && (GET_CODE (new_body) != SET
3583                    || !REG_P (SET_SRC (new_body))))
3584               /* If this was a load from or store to memory, compare
3585                  the MEM in recog_data.operand to the one in the insn.
3586                  If they are not equal, then rerecognize the insn.  */
3587               || (old_set != 0
3588                   && ((MEM_P (SET_SRC (old_set))
3589                        && SET_SRC (old_set) != recog_data.operand[1])
3590                       || (MEM_P (SET_DEST (old_set))
3591                           && SET_DEST (old_set) != recog_data.operand[0])))
3592               /* If this was an add insn before, rerecognize.  */
3593               || GET_CODE (SET_SRC (old_set)) == PLUS))
3594         {
3595           int new_icode = recog (PATTERN (insn), insn, 0);
3596           if (new_icode >= 0)
3597             INSN_CODE (insn) = new_icode;
3598         }
3599     }
3600
3601   /* Restore the old body.  If there were any changes to it, we made a copy
3602      of it while the changes were still in place, so we'll correctly return
3603      a modified insn below.  */
3604   if (! replace)
3605     {
3606       /* Restore the old body.  */
3607       for (i = 0; i < recog_data.n_operands; i++)
3608         /* Restoring a top-level match_parallel would clobber the new_body
3609            we installed in the insn.  */
3610         if (recog_data.operand_loc[i] != &PATTERN (insn))
3611           *recog_data.operand_loc[i] = orig_operand[i];
3612       for (i = 0; i < recog_data.n_dups; i++)
3613         *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3614     }
3615
3616   /* Update all elimination pairs to reflect the status after the current
3617      insn.  The changes we make were determined by the earlier call to
3618      elimination_effects.
3619
3620      We also detect cases where register elimination cannot be done,
3621      namely, if a register would be both changed and referenced outside a MEM
3622      in the resulting insn since such an insn is often undefined and, even if
3623      not, we cannot know what meaning will be given to it.  Note that it is
3624      valid to have a register used in an address in an insn that changes it
3625      (presumably with a pre- or post-increment or decrement).
3626
3627      If anything changes, return nonzero.  */
3628
3629   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3630     {
3631       if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3632         ep->can_eliminate = 0;
3633
3634       ep->ref_outside_mem = 0;
3635
3636       if (ep->previous_offset != ep->offset)
3637         val = 1;
3638     }
3639
3640  done:
3641   /* If we changed something, perform elimination in REG_NOTES.  This is
3642      needed even when REPLACE is zero because a REG_DEAD note might refer
3643      to a register that we eliminate and could cause a different number
3644      of spill registers to be needed in the final reload pass than in
3645      the pre-passes.  */
3646   if (val && REG_NOTES (insn) != 0)
3647     REG_NOTES (insn)
3648       = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3649                           false);
3650
3651   return val;
3652 }
3653
3654 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3655    register allocator.  INSN is the instruction we need to examine, we perform
3656    eliminations in its operands and record cases where eliminating a reg with
3657    an invariant equivalence would add extra cost.  */
3658
3659 static void
3660 elimination_costs_in_insn (rtx_insn *insn)
3661 {
3662   int icode = recog_memoized (insn);
3663   rtx old_body = PATTERN (insn);
3664   int insn_is_asm = asm_noperands (old_body) >= 0;
3665   rtx old_set = single_set (insn);
3666   int i;
3667   rtx orig_operand[MAX_RECOG_OPERANDS];
3668   rtx orig_dup[MAX_RECOG_OPERANDS];
3669   struct elim_table *ep;
3670   rtx plus_src, plus_cst_src;
3671   bool sets_reg_p;
3672
3673   if (! insn_is_asm && icode < 0)
3674     {
3675       gcc_assert (DEBUG_INSN_P (insn)
3676                   || GET_CODE (PATTERN (insn)) == USE
3677                   || GET_CODE (PATTERN (insn)) == CLOBBER
3678                   || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3679       return;
3680     }
3681
3682   if (old_set != 0 && REG_P (SET_DEST (old_set))
3683       && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3684     {
3685       /* Check for setting an eliminable register.  */
3686       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3687         if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3688           return;
3689     }
3690
3691   /* We allow one special case which happens to work on all machines we
3692      currently support: a single set with the source or a REG_EQUAL
3693      note being a PLUS of an eliminable register and a constant.  */
3694   plus_src = plus_cst_src = 0;
3695   sets_reg_p = false;
3696   if (old_set && REG_P (SET_DEST (old_set)))
3697     {
3698       sets_reg_p = true;
3699       if (GET_CODE (SET_SRC (old_set)) == PLUS)
3700         plus_src = SET_SRC (old_set);
3701       /* First see if the source is of the form (plus (...) CST).  */
3702       if (plus_src
3703           && CONST_INT_P (XEXP (plus_src, 1)))
3704         plus_cst_src = plus_src;
3705       else if (REG_P (SET_SRC (old_set))
3706                || plus_src)
3707         {
3708           /* Otherwise, see if we have a REG_EQUAL note of the form
3709              (plus (...) CST).  */
3710           rtx links;
3711           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3712             {
3713               if ((REG_NOTE_KIND (links) == REG_EQUAL
3714                    || REG_NOTE_KIND (links) == REG_EQUIV)
3715                   && GET_CODE (XEXP (links, 0)) == PLUS
3716                   && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3717                 {
3718                   plus_cst_src = XEXP (links, 0);
3719                   break;
3720                 }
3721             }
3722         }
3723     }
3724
3725   /* Determine the effects of this insn on elimination offsets.  */
3726   elimination_effects (old_body, VOIDmode);
3727
3728   /* Eliminate all eliminable registers occurring in operands that
3729      can be handled by reload.  */
3730   extract_insn (insn);
3731   for (i = 0; i < recog_data.n_dups; i++)
3732     orig_dup[i] = *recog_data.dup_loc[i];
3733
3734   for (i = 0; i < recog_data.n_operands; i++)
3735     {
3736       orig_operand[i] = recog_data.operand[i];
3737
3738       /* For an asm statement, every operand is eliminable.  */
3739       if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3740         {
3741           bool is_set_src, in_plus;
3742
3743           /* Check for setting a register that we know about.  */
3744           if (recog_data.operand_type[i] != OP_IN
3745               && REG_P (orig_operand[i]))
3746             {
3747               /* If we are assigning to a register that can be eliminated, it
3748                  must be as part of a PARALLEL, since the code above handles
3749                  single SETs.  We must indicate that we can no longer
3750                  eliminate this reg.  */
3751               for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3752                    ep++)
3753                 if (ep->from_rtx == orig_operand[i])
3754                   ep->can_eliminate = 0;
3755             }
3756
3757           /* Companion to the above plus substitution, we can allow
3758              invariants as the source of a plain move.  */
3759           is_set_src = false;
3760           if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3761             is_set_src = true;
3762           if (is_set_src && !sets_reg_p)
3763             note_reg_elim_costly (SET_SRC (old_set), insn);
3764           in_plus = false;
3765           if (plus_src && sets_reg_p
3766               && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3767                   || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3768             in_plus = true;
3769
3770           eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3771                             NULL_RTX,
3772                             is_set_src || in_plus, true);
3773           /* Terminate the search in check_eliminable_occurrences at
3774              this point.  */
3775           *recog_data.operand_loc[i] = 0;
3776         }
3777     }
3778
3779   for (i = 0; i < recog_data.n_dups; i++)
3780     *recog_data.dup_loc[i]
3781       = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3782
3783   /* If any eliminable remain, they aren't eliminable anymore.  */
3784   check_eliminable_occurrences (old_body);
3785
3786   /* Restore the old body.  */
3787   for (i = 0; i < recog_data.n_operands; i++)
3788     *recog_data.operand_loc[i] = orig_operand[i];
3789   for (i = 0; i < recog_data.n_dups; i++)
3790     *recog_data.dup_loc[i] = orig_dup[i];
3791
3792   /* Update all elimination pairs to reflect the status after the current
3793      insn.  The changes we make were determined by the earlier call to
3794      elimination_effects.  */
3795
3796   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3797     {
3798       if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3799         ep->can_eliminate = 0;
3800
3801       ep->ref_outside_mem = 0;
3802     }
3803
3804   return;
3805 }
3806
3807 /* Loop through all elimination pairs.
3808    Recalculate the number not at initial offset.
3809
3810    Compute the maximum offset (minimum offset if the stack does not
3811    grow downward) for each elimination pair.  */
3812
3813 static void
3814 update_eliminable_offsets (void)
3815 {
3816   struct elim_table *ep;
3817
3818   num_not_at_initial_offset = 0;
3819   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3820     {
3821       ep->previous_offset = ep->offset;
3822       if (ep->can_eliminate && ep->offset != ep->initial_offset)
3823         num_not_at_initial_offset++;
3824     }
3825 }
3826
3827 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3828    replacement we currently believe is valid, mark it as not eliminable if X
3829    modifies DEST in any way other than by adding a constant integer to it.
3830
3831    If DEST is the frame pointer, we do nothing because we assume that
3832    all assignments to the hard frame pointer are nonlocal gotos and are being
3833    done at a time when they are valid and do not disturb anything else.
3834    Some machines want to eliminate a fake argument pointer with either the
3835    frame or stack pointer.  Assignments to the hard frame pointer must not
3836    prevent this elimination.
3837
3838    Called via note_stores from reload before starting its passes to scan
3839    the insns of the function.  */
3840
3841 static void
3842 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3843 {
3844   unsigned int i;
3845
3846   /* A SUBREG of a hard register here is just changing its mode.  We should
3847      not see a SUBREG of an eliminable hard register, but check just in
3848      case.  */
3849   if (GET_CODE (dest) == SUBREG)
3850     dest = SUBREG_REG (dest);
3851
3852   if (dest == hard_frame_pointer_rtx)
3853     return;
3854
3855   for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3856     if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3857         && (GET_CODE (x) != SET
3858             || GET_CODE (SET_SRC (x)) != PLUS
3859             || XEXP (SET_SRC (x), 0) != dest
3860             || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3861       {
3862         reg_eliminate[i].can_eliminate_previous
3863           = reg_eliminate[i].can_eliminate = 0;
3864         num_eliminable--;
3865       }
3866 }
3867
3868 /* Verify that the initial elimination offsets did not change since the
3869    last call to set_initial_elim_offsets.  This is used to catch cases
3870    where something illegal happened during reload_as_needed that could
3871    cause incorrect code to be generated if we did not check for it.  */
3872
3873 static bool
3874 verify_initial_elim_offsets (void)
3875 {
3876   HOST_WIDE_INT t;
3877
3878   if (!num_eliminable)
3879     return true;
3880
3881 #ifdef ELIMINABLE_REGS
3882   {
3883    struct elim_table *ep;
3884
3885    for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3886      {
3887        INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3888        if (t != ep->initial_offset)
3889          return false;
3890      }
3891   }
3892 #else
3893   INITIAL_FRAME_POINTER_OFFSET (t);
3894   if (t != reg_eliminate[0].initial_offset)
3895     return false;
3896 #endif
3897
3898   return true;
3899 }
3900
3901 /* Reset all offsets on eliminable registers to their initial values.  */
3902
3903 static void
3904 set_initial_elim_offsets (void)
3905 {
3906   struct elim_table *ep = reg_eliminate;
3907
3908 #ifdef ELIMINABLE_REGS
3909   for (; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3910     {
3911       INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3912       ep->previous_offset = ep->offset = ep->initial_offset;
3913     }
3914 #else
3915   INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3916   ep->previous_offset = ep->offset = ep->initial_offset;
3917 #endif
3918
3919   num_not_at_initial_offset = 0;
3920 }
3921
3922 /* Subroutine of set_initial_label_offsets called via for_each_eh_label.  */
3923
3924 static void
3925 set_initial_eh_label_offset (rtx label)
3926 {
3927   set_label_offsets (label, NULL, 1);
3928 }
3929
3930 /* Initialize the known label offsets.
3931    Set a known offset for each forced label to be at the initial offset
3932    of each elimination.  We do this because we assume that all
3933    computed jumps occur from a location where each elimination is
3934    at its initial offset.
3935    For all other labels, show that we don't know the offsets.  */
3936
3937 static void
3938 set_initial_label_offsets (void)
3939 {
3940   memset (offsets_known_at, 0, num_labels);
3941
3942   for (rtx_insn_list *x = forced_labels; x; x = x->next ())
3943     if (x->insn ())
3944       set_label_offsets (x->insn (), NULL, 1);
3945
3946   for (rtx_insn_list *x = nonlocal_goto_handler_labels; x; x = x->next ())
3947     if (x->insn ())
3948       set_label_offsets (x->insn (), NULL, 1);
3949
3950   for_each_eh_label (set_initial_eh_label_offset);
3951 }
3952
3953 /* Set all elimination offsets to the known values for the code label given
3954    by INSN.  */
3955
3956 static void
3957 set_offsets_for_label (rtx_insn *insn)
3958 {
3959   unsigned int i;
3960   int label_nr = CODE_LABEL_NUMBER (insn);
3961   struct elim_table *ep;
3962
3963   num_not_at_initial_offset = 0;
3964   for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3965     {
3966       ep->offset = ep->previous_offset
3967                  = offsets_at[label_nr - first_label_num][i];
3968       if (ep->can_eliminate && ep->offset != ep->initial_offset)
3969         num_not_at_initial_offset++;
3970     }
3971 }
3972
3973 /* See if anything that happened changes which eliminations are valid.
3974    For example, on the SPARC, whether or not the frame pointer can
3975    be eliminated can depend on what registers have been used.  We need
3976    not check some conditions again (such as flag_omit_frame_pointer)
3977    since they can't have changed.  */
3978
3979 static void
3980 update_eliminables (HARD_REG_SET *pset)
3981 {
3982   int previous_frame_pointer_needed = frame_pointer_needed;
3983   struct elim_table *ep;
3984
3985   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3986     if ((ep->from == HARD_FRAME_POINTER_REGNUM
3987          && targetm.frame_pointer_required ())
3988 #ifdef ELIMINABLE_REGS
3989         || ! targetm.can_eliminate (ep->from, ep->to)
3990 #endif
3991         )
3992       ep->can_eliminate = 0;
3993
3994   /* Look for the case where we have discovered that we can't replace
3995      register A with register B and that means that we will now be
3996      trying to replace register A with register C.  This means we can
3997      no longer replace register C with register B and we need to disable
3998      such an elimination, if it exists.  This occurs often with A == ap,
3999      B == sp, and C == fp.  */
4000
4001   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4002     {
4003       struct elim_table *op;
4004       int new_to = -1;
4005
4006       if (! ep->can_eliminate && ep->can_eliminate_previous)
4007         {
4008           /* Find the current elimination for ep->from, if there is a
4009              new one.  */
4010           for (op = reg_eliminate;
4011                op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
4012             if (op->from == ep->from && op->can_eliminate)
4013               {
4014                 new_to = op->to;
4015                 break;
4016               }
4017
4018           /* See if there is an elimination of NEW_TO -> EP->TO.  If so,
4019              disable it.  */
4020           for (op = reg_eliminate;
4021                op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
4022             if (op->from == new_to && op->to == ep->to)
4023               op->can_eliminate = 0;
4024         }
4025     }
4026
4027   /* See if any registers that we thought we could eliminate the previous
4028      time are no longer eliminable.  If so, something has changed and we
4029      must spill the register.  Also, recompute the number of eliminable
4030      registers and see if the frame pointer is needed; it is if there is
4031      no elimination of the frame pointer that we can perform.  */
4032
4033   frame_pointer_needed = 1;
4034   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4035     {
4036       if (ep->can_eliminate
4037           && ep->from == FRAME_POINTER_REGNUM
4038           && ep->to != HARD_FRAME_POINTER_REGNUM
4039           && (! SUPPORTS_STACK_ALIGNMENT
4040               || ! crtl->stack_realign_needed))
4041         frame_pointer_needed = 0;
4042
4043       if (! ep->can_eliminate && ep->can_eliminate_previous)
4044         {
4045           ep->can_eliminate_previous = 0;
4046           SET_HARD_REG_BIT (*pset, ep->from);
4047           num_eliminable--;
4048         }
4049     }
4050
4051   /* If we didn't need a frame pointer last time, but we do now, spill
4052      the hard frame pointer.  */
4053   if (frame_pointer_needed && ! previous_frame_pointer_needed)
4054     SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4055 }
4056
4057 /* Call update_eliminables an spill any registers we can't eliminate anymore.
4058    Return true iff a register was spilled.  */
4059
4060 static bool
4061 update_eliminables_and_spill (void)
4062 {
4063   int i;
4064   bool did_spill = false;
4065   HARD_REG_SET to_spill;
4066   CLEAR_HARD_REG_SET (to_spill);
4067   update_eliminables (&to_spill);
4068   AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
4069
4070   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4071     if (TEST_HARD_REG_BIT (to_spill, i))
4072       {
4073         spill_hard_reg (i, 1);
4074         did_spill = true;
4075
4076         /* Regardless of the state of spills, if we previously had
4077            a register that we thought we could eliminate, but now can
4078            not eliminate, we must run another pass.
4079
4080            Consider pseudos which have an entry in reg_equiv_* which
4081            reference an eliminable register.  We must make another pass
4082            to update reg_equiv_* so that we do not substitute in the
4083            old value from when we thought the elimination could be
4084            performed.  */
4085       }
4086   return did_spill;
4087 }
4088
4089 /* Return true if X is used as the target register of an elimination.  */
4090
4091 bool
4092 elimination_target_reg_p (rtx x)
4093 {
4094   struct elim_table *ep;
4095
4096   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4097     if (ep->to_rtx == x && ep->can_eliminate)
4098       return true;
4099
4100   return false;
4101 }
4102
4103 /* Initialize the table of registers to eliminate.
4104    Pre-condition: global flag frame_pointer_needed has been set before
4105    calling this function.  */
4106
4107 static void
4108 init_elim_table (void)
4109 {
4110   struct elim_table *ep;
4111 #ifdef ELIMINABLE_REGS
4112   const struct elim_table_1 *ep1;
4113 #endif
4114
4115   if (!reg_eliminate)
4116     reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4117
4118   num_eliminable = 0;
4119
4120 #ifdef ELIMINABLE_REGS
4121   for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4122        ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4123     {
4124       ep->from = ep1->from;
4125       ep->to = ep1->to;
4126       ep->can_eliminate = ep->can_eliminate_previous
4127         = (targetm.can_eliminate (ep->from, ep->to)
4128            && ! (ep->to == STACK_POINTER_REGNUM
4129                  && frame_pointer_needed
4130                  && (! SUPPORTS_STACK_ALIGNMENT
4131                      || ! stack_realign_fp)));
4132     }
4133 #else
4134   reg_eliminate[0].from = reg_eliminate_1[0].from;
4135   reg_eliminate[0].to = reg_eliminate_1[0].to;
4136   reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4137     = ! frame_pointer_needed;
4138 #endif
4139
4140   /* Count the number of eliminable registers and build the FROM and TO
4141      REG rtx's.  Note that code in gen_rtx_REG will cause, e.g.,
4142      gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4143      We depend on this.  */
4144   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4145     {
4146       num_eliminable += ep->can_eliminate;
4147       ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4148       ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4149     }
4150 }
4151
4152 /* Find all the pseudo registers that didn't get hard regs
4153    but do have known equivalent constants or memory slots.
4154    These include parameters (known equivalent to parameter slots)
4155    and cse'd or loop-moved constant memory addresses.
4156
4157    Record constant equivalents in reg_equiv_constant
4158    so they will be substituted by find_reloads.
4159    Record memory equivalents in reg_mem_equiv so they can
4160    be substituted eventually by altering the REG-rtx's.  */
4161
4162 static void
4163 init_eliminable_invariants (rtx_insn *first, bool do_subregs)
4164 {
4165   int i;
4166   rtx_insn *insn;
4167
4168   grow_reg_equivs ();
4169   if (do_subregs)
4170     reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4171   else
4172     reg_max_ref_width = NULL;
4173
4174   num_eliminable_invariants = 0;
4175
4176   first_label_num = get_first_label_num ();
4177   num_labels = max_label_num () - first_label_num;
4178
4179   /* Allocate the tables used to store offset information at labels.  */
4180   offsets_known_at = XNEWVEC (char, num_labels);
4181   offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4182
4183 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4184    to.  If DO_SUBREGS is true, also find all paradoxical subregs and
4185    find largest such for each pseudo.  FIRST is the head of the insn
4186    list.  */
4187
4188   for (insn = first; insn; insn = NEXT_INSN (insn))
4189     {
4190       rtx set = single_set (insn);
4191
4192       /* We may introduce USEs that we want to remove at the end, so
4193          we'll mark them with QImode.  Make sure there are no
4194          previously-marked insns left by say regmove.  */
4195       if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4196           && GET_MODE (insn) != VOIDmode)
4197         PUT_MODE (insn, VOIDmode);
4198
4199       if (do_subregs && NONDEBUG_INSN_P (insn))
4200         scan_paradoxical_subregs (PATTERN (insn));
4201
4202       if (set != 0 && REG_P (SET_DEST (set)))
4203         {
4204           rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4205           rtx x;
4206
4207           if (! note)
4208             continue;
4209
4210           i = REGNO (SET_DEST (set));
4211           x = XEXP (note, 0);
4212
4213           if (i <= LAST_VIRTUAL_REGISTER)
4214             continue;
4215
4216           /* If flag_pic and we have constant, verify it's legitimate.  */
4217           if (!CONSTANT_P (x)
4218               || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4219             {
4220               /* It can happen that a REG_EQUIV note contains a MEM
4221                  that is not a legitimate memory operand.  As later
4222                  stages of reload assume that all addresses found
4223                  in the reg_equiv_* arrays were originally legitimate,
4224                  we ignore such REG_EQUIV notes.  */
4225               if (memory_operand (x, VOIDmode))
4226                 {
4227                   /* Always unshare the equivalence, so we can
4228                      substitute into this insn without touching the
4229                        equivalence.  */
4230                   reg_equiv_memory_loc (i) = copy_rtx (x);
4231                 }
4232               else if (function_invariant_p (x))
4233                 {
4234                   machine_mode mode;
4235
4236                   mode = GET_MODE (SET_DEST (set));
4237                   if (GET_CODE (x) == PLUS)
4238                     {
4239                       /* This is PLUS of frame pointer and a constant,
4240                          and might be shared.  Unshare it.  */
4241                       reg_equiv_invariant (i) = copy_rtx (x);
4242                       num_eliminable_invariants++;
4243                     }
4244                   else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4245                     {
4246                       reg_equiv_invariant (i) = x;
4247                       num_eliminable_invariants++;
4248                     }
4249                   else if (targetm.legitimate_constant_p (mode, x))
4250                     reg_equiv_constant (i) = x;
4251                   else
4252                     {
4253                       reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4254                       if (! reg_equiv_memory_loc (i))
4255                         reg_equiv_init (i) = NULL;
4256                     }
4257                 }
4258               else
4259                 {
4260                   reg_equiv_init (i) = NULL;
4261                   continue;
4262                 }
4263             }
4264           else
4265             reg_equiv_init (i) = NULL;
4266         }
4267     }
4268
4269   if (dump_file)
4270     for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4271       if (reg_equiv_init (i))
4272         {
4273           fprintf (dump_file, "init_insns for %u: ", i);
4274           print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4275           fprintf (dump_file, "\n");
4276         }
4277 }
4278
4279 /* Indicate that we no longer have known memory locations or constants.
4280    Free all data involved in tracking these.  */
4281
4282 static void
4283 free_reg_equiv (void)
4284 {
4285   int i;
4286
4287   free (offsets_known_at);
4288   free (offsets_at);
4289   offsets_at = 0;
4290   offsets_known_at = 0;
4291
4292   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4293     if (reg_equiv_alt_mem_list (i))
4294       free_EXPR_LIST_list (&reg_equiv_alt_mem_list (i));
4295   vec_free (reg_equivs);
4296 }
4297 \f
4298 /* Kick all pseudos out of hard register REGNO.
4299
4300    If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4301    because we found we can't eliminate some register.  In the case, no pseudos
4302    are allowed to be in the register, even if they are only in a block that
4303    doesn't require spill registers, unlike the case when we are spilling this
4304    hard reg to produce another spill register.
4305
4306    Return nonzero if any pseudos needed to be kicked out.  */
4307
4308 static void
4309 spill_hard_reg (unsigned int regno, int cant_eliminate)
4310 {
4311   int i;
4312
4313   if (cant_eliminate)
4314     {
4315       SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4316       df_set_regs_ever_live (regno, true);
4317     }
4318
4319   /* Spill every pseudo reg that was allocated to this reg
4320      or to something that overlaps this reg.  */
4321
4322   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4323     if (reg_renumber[i] >= 0
4324         && (unsigned int) reg_renumber[i] <= regno
4325         && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4326       SET_REGNO_REG_SET (&spilled_pseudos, i);
4327 }
4328
4329 /* After find_reload_regs has been run for all insn that need reloads,
4330    and/or spill_hard_regs was called, this function is used to actually
4331    spill pseudo registers and try to reallocate them.  It also sets up the
4332    spill_regs array for use by choose_reload_regs.  */
4333
4334 static int
4335 finish_spills (int global)
4336 {
4337   struct insn_chain *chain;
4338   int something_changed = 0;
4339   unsigned i;
4340   reg_set_iterator rsi;
4341
4342   /* Build the spill_regs array for the function.  */
4343   /* If there are some registers still to eliminate and one of the spill regs
4344      wasn't ever used before, additional stack space may have to be
4345      allocated to store this register.  Thus, we may have changed the offset
4346      between the stack and frame pointers, so mark that something has changed.
4347
4348      One might think that we need only set VAL to 1 if this is a call-used
4349      register.  However, the set of registers that must be saved by the
4350      prologue is not identical to the call-used set.  For example, the
4351      register used by the call insn for the return PC is a call-used register,
4352      but must be saved by the prologue.  */
4353
4354   n_spills = 0;
4355   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4356     if (TEST_HARD_REG_BIT (used_spill_regs, i))
4357       {
4358         spill_reg_order[i] = n_spills;
4359         spill_regs[n_spills++] = i;
4360         if (num_eliminable && ! df_regs_ever_live_p (i))
4361           something_changed = 1;
4362         df_set_regs_ever_live (i, true);
4363       }
4364     else
4365       spill_reg_order[i] = -1;
4366
4367   EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4368     if (! ira_conflicts_p || reg_renumber[i] >= 0)
4369       {
4370         /* Record the current hard register the pseudo is allocated to
4371            in pseudo_previous_regs so we avoid reallocating it to the
4372            same hard reg in a later pass.  */
4373         gcc_assert (reg_renumber[i] >= 0);
4374
4375         SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4376         /* Mark it as no longer having a hard register home.  */
4377         reg_renumber[i] = -1;
4378         if (ira_conflicts_p)
4379           /* Inform IRA about the change.  */
4380           ira_mark_allocation_change (i);
4381         /* We will need to scan everything again.  */
4382         something_changed = 1;
4383       }
4384
4385   /* Retry global register allocation if possible.  */
4386   if (global && ira_conflicts_p)
4387     {
4388       unsigned int n;
4389
4390       memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4391       /* For every insn that needs reloads, set the registers used as spill
4392          regs in pseudo_forbidden_regs for every pseudo live across the
4393          insn.  */
4394       for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4395         {
4396           EXECUTE_IF_SET_IN_REG_SET
4397             (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4398             {
4399               IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4400                                 chain->used_spill_regs);
4401             }
4402           EXECUTE_IF_SET_IN_REG_SET
4403             (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4404             {
4405               IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4406                                 chain->used_spill_regs);
4407             }
4408         }
4409
4410       /* Retry allocating the pseudos spilled in IRA and the
4411          reload.  For each reg, merge the various reg sets that
4412          indicate which hard regs can't be used, and call
4413          ira_reassign_pseudos.  */
4414       for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4415         if (reg_old_renumber[i] != reg_renumber[i])
4416           {
4417             if (reg_renumber[i] < 0)
4418               temp_pseudo_reg_arr[n++] = i;
4419             else
4420               CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4421           }
4422       if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4423                                 bad_spill_regs_global,
4424                                 pseudo_forbidden_regs, pseudo_previous_regs,
4425                                 &spilled_pseudos))
4426         something_changed = 1;
4427     }
4428   /* Fix up the register information in the insn chain.
4429      This involves deleting those of the spilled pseudos which did not get
4430      a new hard register home from the live_{before,after} sets.  */
4431   for (chain = reload_insn_chain; chain; chain = chain->next)
4432     {
4433       HARD_REG_SET used_by_pseudos;
4434       HARD_REG_SET used_by_pseudos2;
4435
4436       if (! ira_conflicts_p)
4437         {
4438           /* Don't do it for IRA because IRA and the reload still can
4439              assign hard registers to the spilled pseudos on next
4440              reload iterations.  */
4441           AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4442           AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4443         }
4444       /* Mark any unallocated hard regs as available for spills.  That
4445          makes inheritance work somewhat better.  */
4446       if (chain->need_reload)
4447         {
4448           REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4449           REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4450           IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4451
4452           compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4453           compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4454           /* Value of chain->used_spill_regs from previous iteration
4455              may be not included in the value calculated here because
4456              of possible removing caller-saves insns (see function
4457              delete_caller_save_insns.  */
4458           COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4459           AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4460         }
4461     }
4462
4463   CLEAR_REG_SET (&changed_allocation_pseudos);
4464   /* Let alter_reg modify the reg rtx's for the modified pseudos.  */
4465   for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4466     {
4467       int regno = reg_renumber[i];
4468       if (reg_old_renumber[i] == regno)
4469         continue;
4470
4471       SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4472
4473       alter_reg (i, reg_old_renumber[i], false);
4474       reg_old_renumber[i] = regno;
4475       if (dump_file)
4476         {
4477           if (regno == -1)
4478             fprintf (dump_file, " Register %d now on stack.\n\n", i);
4479           else
4480             fprintf (dump_file, " Register %d now in %d.\n\n",
4481                      i, reg_renumber[i]);
4482         }
4483     }
4484
4485   return something_changed;
4486 }
4487 \f
4488 /* Find all paradoxical subregs within X and update reg_max_ref_width.  */
4489
4490 static void
4491 scan_paradoxical_subregs (rtx x)
4492 {
4493   int i;
4494   const char *fmt;
4495   enum rtx_code code = GET_CODE (x);
4496
4497   switch (code)
4498     {
4499     case REG:
4500     case CONST:
4501     case SYMBOL_REF:
4502     case LABEL_REF:
4503     CASE_CONST_ANY:
4504     case CC0:
4505     case PC:
4506     case USE:
4507     case CLOBBER:
4508       return;
4509
4510     case SUBREG:
4511       if (REG_P (SUBREG_REG (x))
4512           && (GET_MODE_SIZE (GET_MODE (x))
4513               > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4514         {
4515           reg_max_ref_width[REGNO (SUBREG_REG (x))]
4516             = GET_MODE_SIZE (GET_MODE (x));
4517           mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4518         }
4519       return;
4520
4521     default:
4522       break;
4523     }
4524
4525   fmt = GET_RTX_FORMAT (code);
4526   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4527     {
4528       if (fmt[i] == 'e')
4529         scan_paradoxical_subregs (XEXP (x, i));
4530       else if (fmt[i] == 'E')
4531         {
4532           int j;
4533           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4534             scan_paradoxical_subregs (XVECEXP (x, i, j));
4535         }
4536     }
4537 }
4538
4539 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4540    If *OP_PTR is a paradoxical subreg, try to remove that subreg
4541    and apply the corresponding narrowing subreg to *OTHER_PTR.
4542    Return true if the operands were changed, false otherwise.  */
4543
4544 static bool
4545 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4546 {
4547   rtx op, inner, other, tem;
4548
4549   op = *op_ptr;
4550   if (!paradoxical_subreg_p (op))
4551     return false;
4552   inner = SUBREG_REG (op);
4553
4554   other = *other_ptr;
4555   tem = gen_lowpart_common (GET_MODE (inner), other);
4556   if (!tem)
4557     return false;
4558
4559   /* If the lowpart operation turned a hard register into a subreg,
4560      rather than simplifying it to another hard register, then the
4561      mode change cannot be properly represented.  For example, OTHER
4562      might be valid in its current mode, but not in the new one.  */
4563   if (GET_CODE (tem) == SUBREG
4564       && REG_P (other)
4565       && HARD_REGISTER_P (other))
4566     return false;
4567
4568   *op_ptr = inner;
4569   *other_ptr = tem;
4570   return true;
4571 }
4572 \f
4573 /* A subroutine of reload_as_needed.  If INSN has a REG_EH_REGION note,
4574    examine all of the reload insns between PREV and NEXT exclusive, and
4575    annotate all that may trap.  */
4576
4577 static void
4578 fixup_eh_region_note (rtx_insn *insn, rtx_insn *prev, rtx_insn *next)
4579 {
4580   rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4581   if (note == NULL)
4582     return;
4583   if (!insn_could_throw_p (insn))
4584     remove_note (insn, note);
4585   copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4586 }
4587
4588 /* Reload pseudo-registers into hard regs around each insn as needed.
4589    Additional register load insns are output before the insn that needs it
4590    and perhaps store insns after insns that modify the reloaded pseudo reg.
4591
4592    reg_last_reload_reg and reg_reloaded_contents keep track of
4593    which registers are already available in reload registers.
4594    We update these for the reloads that we perform,
4595    as the insns are scanned.  */
4596
4597 static void
4598 reload_as_needed (int live_known)
4599 {
4600   struct insn_chain *chain;
4601 #if defined (AUTO_INC_DEC)
4602   int i;
4603 #endif
4604   rtx_note *marker;
4605
4606   memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4607   memset (spill_reg_store, 0, sizeof spill_reg_store);
4608   reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4609   INIT_REG_SET (&reg_has_output_reload);
4610   CLEAR_HARD_REG_SET (reg_reloaded_valid);
4611   CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4612
4613   set_initial_elim_offsets ();
4614
4615   /* Generate a marker insn that we will move around.  */
4616   marker = emit_note (NOTE_INSN_DELETED);
4617   unlink_insn_chain (marker, marker);
4618
4619   for (chain = reload_insn_chain; chain; chain = chain->next)
4620     {
4621       rtx_insn *prev = 0;
4622       rtx_insn *insn = chain->insn;
4623       rtx_insn *old_next = NEXT_INSN (insn);
4624 #ifdef AUTO_INC_DEC
4625       rtx_insn *old_prev = PREV_INSN (insn);
4626 #endif
4627
4628       if (will_delete_init_insn_p (insn))
4629         continue;
4630
4631       /* If we pass a label, copy the offsets from the label information
4632          into the current offsets of each elimination.  */
4633       if (LABEL_P (insn))
4634         set_offsets_for_label (insn);
4635
4636       else if (INSN_P (insn))
4637         {
4638           regset_head regs_to_forget;
4639           INIT_REG_SET (&regs_to_forget);
4640           note_stores (PATTERN (insn), forget_old_reloads_1, &regs_to_forget);
4641
4642           /* If this is a USE and CLOBBER of a MEM, ensure that any
4643              references to eliminable registers have been removed.  */
4644
4645           if ((GET_CODE (PATTERN (insn)) == USE
4646                || GET_CODE (PATTERN (insn)) == CLOBBER)
4647               && MEM_P (XEXP (PATTERN (insn), 0)))
4648             XEXP (XEXP (PATTERN (insn), 0), 0)
4649               = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4650                                 GET_MODE (XEXP (PATTERN (insn), 0)),
4651                                 NULL_RTX);
4652
4653           /* If we need to do register elimination processing, do so.
4654              This might delete the insn, in which case we are done.  */
4655           if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4656             {
4657               eliminate_regs_in_insn (insn, 1);
4658               if (NOTE_P (insn))
4659                 {
4660                   update_eliminable_offsets ();
4661                   CLEAR_REG_SET (&regs_to_forget);
4662                   continue;
4663                 }
4664             }
4665
4666           /* If need_elim is nonzero but need_reload is zero, one might think
4667              that we could simply set n_reloads to 0.  However, find_reloads
4668              could have done some manipulation of the insn (such as swapping
4669              commutative operands), and these manipulations are lost during
4670              the first pass for every insn that needs register elimination.
4671              So the actions of find_reloads must be redone here.  */
4672
4673           if (! chain->need_elim && ! chain->need_reload
4674               && ! chain->need_operand_change)
4675             n_reloads = 0;
4676           /* First find the pseudo regs that must be reloaded for this insn.
4677              This info is returned in the tables reload_... (see reload.h).
4678              Also modify the body of INSN by substituting RELOAD
4679              rtx's for those pseudo regs.  */
4680           else
4681             {
4682               CLEAR_REG_SET (&reg_has_output_reload);
4683               CLEAR_HARD_REG_SET (reg_is_output_reload);
4684
4685               find_reloads (insn, 1, spill_indirect_levels, live_known,
4686                             spill_reg_order);
4687             }
4688
4689           if (n_reloads > 0)
4690             {
4691               rtx_insn *next = NEXT_INSN (insn);
4692
4693               /* ??? PREV can get deleted by reload inheritance.
4694                  Work around this by emitting a marker note.  */
4695               prev = PREV_INSN (insn);
4696               reorder_insns_nobb (marker, marker, prev);
4697
4698               /* Now compute which reload regs to reload them into.  Perhaps
4699                  reusing reload regs from previous insns, or else output
4700                  load insns to reload them.  Maybe output store insns too.
4701                  Record the choices of reload reg in reload_reg_rtx.  */
4702               choose_reload_regs (chain);
4703
4704               /* Generate the insns to reload operands into or out of
4705                  their reload regs.  */
4706               emit_reload_insns (chain);
4707
4708               /* Substitute the chosen reload regs from reload_reg_rtx
4709                  into the insn's body (or perhaps into the bodies of other
4710                  load and store insn that we just made for reloading
4711                  and that we moved the structure into).  */
4712               subst_reloads (insn);
4713
4714               prev = PREV_INSN (marker);
4715               unlink_insn_chain (marker, marker);
4716
4717               /* Adjust the exception region notes for loads and stores.  */
4718               if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4719                 fixup_eh_region_note (insn, prev, next);
4720
4721               /* Adjust the location of REG_ARGS_SIZE.  */
4722               rtx p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4723               if (p)
4724                 {
4725                   remove_note (insn, p);
4726                   fixup_args_size_notes (prev, PREV_INSN (next),
4727                                          INTVAL (XEXP (p, 0)));
4728                 }
4729
4730               /* If this was an ASM, make sure that all the reload insns
4731                  we have generated are valid.  If not, give an error
4732                  and delete them.  */
4733               if (asm_noperands (PATTERN (insn)) >= 0)
4734                 for (rtx_insn *p = NEXT_INSN (prev);
4735                      p != next;
4736                      p = NEXT_INSN (p))
4737                   if (p != insn && INSN_P (p)
4738                       && GET_CODE (PATTERN (p)) != USE
4739                       && (recog_memoized (p) < 0
4740                           || (extract_insn (p),
4741                               !(constrain_operands (1,
4742                                   get_enabled_alternatives (p))))))
4743                     {
4744                       error_for_asm (insn,
4745                                      "%<asm%> operand requires "
4746                                      "impossible reload");
4747                       delete_insn (p);
4748                     }
4749             }
4750
4751           if (num_eliminable && chain->need_elim)
4752             update_eliminable_offsets ();
4753
4754           /* Any previously reloaded spilled pseudo reg, stored in this insn,
4755              is no longer validly lying around to save a future reload.
4756              Note that this does not detect pseudos that were reloaded
4757              for this insn in order to be stored in
4758              (obeying register constraints).  That is correct; such reload
4759              registers ARE still valid.  */
4760           forget_marked_reloads (&regs_to_forget);
4761           CLEAR_REG_SET (&regs_to_forget);
4762
4763           /* There may have been CLOBBER insns placed after INSN.  So scan
4764              between INSN and NEXT and use them to forget old reloads.  */
4765           for (rtx_insn *x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4766             if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4767               note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4768
4769 #ifdef AUTO_INC_DEC
4770           /* Likewise for regs altered by auto-increment in this insn.
4771              REG_INC notes have been changed by reloading:
4772              find_reloads_address_1 records substitutions for them,
4773              which have been performed by subst_reloads above.  */
4774           for (i = n_reloads - 1; i >= 0; i--)
4775             {
4776               rtx in_reg = rld[i].in_reg;
4777               if (in_reg)
4778                 {
4779                   enum rtx_code code = GET_CODE (in_reg);
4780                   /* PRE_INC / PRE_DEC will have the reload register ending up
4781                      with the same value as the stack slot, but that doesn't
4782                      hold true for POST_INC / POST_DEC.  Either we have to
4783                      convert the memory access to a true POST_INC / POST_DEC,
4784                      or we can't use the reload register for inheritance.  */
4785                   if ((code == POST_INC || code == POST_DEC)
4786                       && TEST_HARD_REG_BIT (reg_reloaded_valid,
4787                                             REGNO (rld[i].reg_rtx))
4788                       /* Make sure it is the inc/dec pseudo, and not
4789                          some other (e.g. output operand) pseudo.  */
4790                       && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4791                           == REGNO (XEXP (in_reg, 0))))
4792
4793                     {
4794                       rtx reload_reg = rld[i].reg_rtx;
4795                       machine_mode mode = GET_MODE (reload_reg);
4796                       int n = 0;
4797                       rtx_insn *p;
4798
4799                       for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4800                         {
4801                           /* We really want to ignore REG_INC notes here, so
4802                              use PATTERN (p) as argument to reg_set_p .  */
4803                           if (reg_set_p (reload_reg, PATTERN (p)))
4804                             break;
4805                           n = count_occurrences (PATTERN (p), reload_reg, 0);
4806                           if (! n)
4807                             continue;
4808                           if (n == 1)
4809                             {
4810                               rtx replace_reg
4811                                 = gen_rtx_fmt_e (code, mode, reload_reg);
4812
4813                               validate_replace_rtx_group (reload_reg,
4814                                                           replace_reg, p);
4815                               n = verify_changes (0);
4816
4817                               /* We must also verify that the constraints
4818                                  are met after the replacement.  Make sure
4819                                  extract_insn is only called for an insn
4820                                  where the replacements were found to be
4821                                  valid so far. */
4822                               if (n)
4823                                 {
4824                                   extract_insn (p);
4825                                   n = constrain_operands (1,
4826                                     get_enabled_alternatives (p));
4827                                 }
4828
4829                               /* If the constraints were not met, then
4830                                  undo the replacement, else confirm it.  */
4831                               if (!n)
4832                                 cancel_changes (0);
4833                               else
4834                                 confirm_change_group ();
4835                             }
4836                           break;
4837                         }
4838                       if (n == 1)
4839                         {
4840                           add_reg_note (p, REG_INC, reload_reg);
4841                           /* Mark this as having an output reload so that the
4842                              REG_INC processing code below won't invalidate
4843                              the reload for inheritance.  */
4844                           SET_HARD_REG_BIT (reg_is_output_reload,
4845                                             REGNO (reload_reg));
4846                           SET_REGNO_REG_SET (&reg_has_output_reload,
4847                                              REGNO (XEXP (in_reg, 0)));
4848                         }
4849                       else
4850                         forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4851                                               NULL);
4852                     }
4853                   else if ((code == PRE_INC || code == PRE_DEC)
4854                            && TEST_HARD_REG_BIT (reg_reloaded_valid,
4855                                                  REGNO (rld[i].reg_rtx))
4856                            /* Make sure it is the inc/dec pseudo, and not
4857                               some other (e.g. output operand) pseudo.  */
4858                            && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4859                                == REGNO (XEXP (in_reg, 0))))
4860                     {
4861                       SET_HARD_REG_BIT (reg_is_output_reload,
4862                                         REGNO (rld[i].reg_rtx));
4863                       SET_REGNO_REG_SET (&reg_has_output_reload,
4864                                          REGNO (XEXP (in_reg, 0)));
4865                     }
4866                   else if (code == PRE_INC || code == PRE_DEC
4867                            || code == POST_INC || code == POST_DEC)
4868                     {
4869                       int in_regno = REGNO (XEXP (in_reg, 0));
4870
4871                       if (reg_last_reload_reg[in_regno] != NULL_RTX)
4872                         {
4873                           int in_hard_regno;
4874                           bool forget_p = true;
4875
4876                           in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4877                           if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4878                                                  in_hard_regno))
4879                             {
4880                               for (rtx_insn *x = (old_prev ?
4881                                                   NEXT_INSN (old_prev) : insn);
4882                                    x != old_next;
4883                                    x = NEXT_INSN (x))
4884                                 if (x == reg_reloaded_insn[in_hard_regno])
4885                                   {
4886                                     forget_p = false;
4887                                     break;
4888                                   }
4889                             }
4890                           /* If for some reasons, we didn't set up
4891                              reg_last_reload_reg in this insn,
4892                              invalidate inheritance from previous
4893                              insns for the incremented/decremented
4894                              register.  Such registers will be not in
4895                              reg_has_output_reload.  Invalidate it
4896                              also if the corresponding element in
4897                              reg_reloaded_insn is also
4898                              invalidated.  */
4899                           if (forget_p)
4900                             forget_old_reloads_1 (XEXP (in_reg, 0),
4901                                                   NULL_RTX, NULL);
4902                         }
4903                     }
4904                 }
4905             }
4906           /* If a pseudo that got a hard register is auto-incremented,
4907              we must purge records of copying it into pseudos without
4908              hard registers.  */
4909           for (rtx x = REG_NOTES (insn); x; x = XEXP (x, 1))
4910             if (REG_NOTE_KIND (x) == REG_INC)
4911               {
4912                 /* See if this pseudo reg was reloaded in this insn.
4913                    If so, its last-reload info is still valid
4914                    because it is based on this insn's reload.  */
4915                 for (i = 0; i < n_reloads; i++)
4916                   if (rld[i].out == XEXP (x, 0))
4917                     break;
4918
4919                 if (i == n_reloads)
4920                   forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4921               }
4922 #endif
4923         }
4924       /* A reload reg's contents are unknown after a label.  */
4925       if (LABEL_P (insn))
4926         CLEAR_HARD_REG_SET (reg_reloaded_valid);
4927
4928       /* Don't assume a reload reg is still good after a call insn
4929          if it is a call-used reg, or if it contains a value that will
4930          be partially clobbered by the call.  */
4931       else if (CALL_P (insn))
4932         {
4933           AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4934           AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4935
4936           /* If this is a call to a setjmp-type function, we must not
4937              reuse any reload reg contents across the call; that will
4938              just be clobbered by other uses of the register in later
4939              code, before the longjmp.  */
4940           if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4941             CLEAR_HARD_REG_SET (reg_reloaded_valid);
4942         }
4943     }
4944
4945   /* Clean up.  */
4946   free (reg_last_reload_reg);
4947   CLEAR_REG_SET (&reg_has_output_reload);
4948 }
4949
4950 /* Discard all record of any value reloaded from X,
4951    or reloaded in X from someplace else;
4952    unless X is an output reload reg of the current insn.
4953
4954    X may be a hard reg (the reload reg)
4955    or it may be a pseudo reg that was reloaded from.
4956
4957    When DATA is non-NULL just mark the registers in regset
4958    to be forgotten later.  */
4959
4960 static void
4961 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4962                       void *data)
4963 {
4964   unsigned int regno;
4965   unsigned int nr;
4966   regset regs = (regset) data;
4967
4968   /* note_stores does give us subregs of hard regs,
4969      subreg_regno_offset requires a hard reg.  */
4970   while (GET_CODE (x) == SUBREG)
4971     {
4972       /* We ignore the subreg offset when calculating the regno,
4973          because we are using the entire underlying hard register
4974          below.  */
4975       x = SUBREG_REG (x);
4976     }
4977
4978   if (!REG_P (x))
4979     return;
4980
4981   regno = REGNO (x);
4982
4983   if (regno >= FIRST_PSEUDO_REGISTER)
4984     nr = 1;
4985   else
4986     {
4987       unsigned int i;
4988
4989       nr = hard_regno_nregs[regno][GET_MODE (x)];
4990       /* Storing into a spilled-reg invalidates its contents.
4991          This can happen if a block-local pseudo is allocated to that reg
4992          and it wasn't spilled because this block's total need is 0.
4993          Then some insn might have an optional reload and use this reg.  */
4994       if (!regs)
4995         for (i = 0; i < nr; i++)
4996           /* But don't do this if the reg actually serves as an output
4997              reload reg in the current instruction.  */
4998           if (n_reloads == 0
4999               || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
5000             {
5001               CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
5002               spill_reg_store[regno + i] = 0;
5003             }
5004     }
5005
5006   if (regs)
5007     while (nr-- > 0)
5008       SET_REGNO_REG_SET (regs, regno + nr);
5009   else
5010     {
5011       /* Since value of X has changed,
5012          forget any value previously copied from it.  */
5013
5014       while (nr-- > 0)
5015         /* But don't forget a copy if this is the output reload
5016            that establishes the copy's validity.  */
5017         if (n_reloads == 0
5018             || !REGNO_REG_SET_P (&reg_has_output_reload, regno + nr))
5019           reg_last_reload_reg[regno + nr] = 0;
5020      }
5021 }
5022
5023 /* Forget the reloads marked in regset by previous function.  */
5024 static void
5025 forget_marked_reloads (regset regs)
5026 {
5027   unsigned int reg;
5028   reg_set_iterator rsi;
5029   EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
5030     {
5031       if (reg < FIRST_PSEUDO_REGISTER
5032           /* But don't do this if the reg actually serves as an output
5033              reload reg in the current instruction.  */
5034           && (n_reloads == 0
5035               || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
5036           {
5037             CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
5038             spill_reg_store[reg] = 0;
5039           }
5040       if (n_reloads == 0
5041           || !REGNO_REG_SET_P (&reg_has_output_reload, reg))
5042         reg_last_reload_reg[reg] = 0;
5043     }
5044 }
5045 \f
5046 /* The following HARD_REG_SETs indicate when each hard register is
5047    used for a reload of various parts of the current insn.  */
5048
5049 /* If reg is unavailable for all reloads.  */
5050 static HARD_REG_SET reload_reg_unavailable;
5051 /* If reg is in use as a reload reg for a RELOAD_OTHER reload.  */
5052 static HARD_REG_SET reload_reg_used;
5053 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I.  */
5054 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5055 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I.  */
5056 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5057 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I.  */
5058 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5059 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I.  */
5060 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5061 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I.  */
5062 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5063 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I.  */
5064 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5065 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload.  */
5066 static HARD_REG_SET reload_reg_used_in_op_addr;
5067 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload.  */
5068 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
5069 /* If reg is in use for a RELOAD_FOR_INSN reload.  */
5070 static HARD_REG_SET reload_reg_used_in_insn;
5071 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload.  */
5072 static HARD_REG_SET reload_reg_used_in_other_addr;
5073
5074 /* If reg is in use as a reload reg for any sort of reload.  */
5075 static HARD_REG_SET reload_reg_used_at_all;
5076
5077 /* If reg is use as an inherited reload.  We just mark the first register
5078    in the group.  */
5079 static HARD_REG_SET reload_reg_used_for_inherit;
5080
5081 /* Records which hard regs are used in any way, either as explicit use or
5082    by being allocated to a pseudo during any point of the current insn.  */
5083 static HARD_REG_SET reg_used_in_insn;
5084
5085 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5086    TYPE. MODE is used to indicate how many consecutive regs are
5087    actually used.  */
5088
5089 static void
5090 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5091                         machine_mode mode)
5092 {
5093   switch (type)
5094     {
5095     case RELOAD_OTHER:
5096       add_to_hard_reg_set (&reload_reg_used, mode, regno);
5097       break;
5098
5099     case RELOAD_FOR_INPUT_ADDRESS:
5100       add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5101       break;
5102
5103     case RELOAD_FOR_INPADDR_ADDRESS:
5104       add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5105       break;
5106
5107     case RELOAD_FOR_OUTPUT_ADDRESS:
5108       add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5109       break;
5110
5111     case RELOAD_FOR_OUTADDR_ADDRESS:
5112       add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5113       break;
5114
5115     case RELOAD_FOR_OPERAND_ADDRESS:
5116       add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5117       break;
5118
5119     case RELOAD_FOR_OPADDR_ADDR:
5120       add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5121       break;
5122
5123     case RELOAD_FOR_OTHER_ADDRESS:
5124       add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5125       break;
5126
5127     case RELOAD_FOR_INPUT:
5128       add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5129       break;
5130
5131     case RELOAD_FOR_OUTPUT:
5132       add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5133       break;
5134
5135     case RELOAD_FOR_INSN:
5136       add_to_hard_reg_set (&reload_reg_used_in_insn,  mode, regno);
5137       break;
5138     }
5139
5140   add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5141 }
5142
5143 /* Similarly, but show REGNO is no longer in use for a reload.  */
5144
5145 static void
5146 clear_reload_reg_in_use (unsigned int regno, int opnum,
5147                          enum reload_type type, machine_mode mode)
5148 {
5149   unsigned int nregs = hard_regno_nregs[regno][mode];
5150   unsigned int start_regno, end_regno, r;
5151   int i;
5152   /* A complication is that for some reload types, inheritance might
5153      allow multiple reloads of the same types to share a reload register.
5154      We set check_opnum if we have to check only reloads with the same
5155      operand number, and check_any if we have to check all reloads.  */
5156   int check_opnum = 0;
5157   int check_any = 0;
5158   HARD_REG_SET *used_in_set;
5159
5160   switch (type)
5161     {
5162     case RELOAD_OTHER:
5163       used_in_set = &reload_reg_used;
5164       break;
5165
5166     case RELOAD_FOR_INPUT_ADDRESS:
5167       used_in_set = &reload_reg_used_in_input_addr[opnum];
5168       break;
5169
5170     case RELOAD_FOR_INPADDR_ADDRESS:
5171       check_opnum = 1;
5172       used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5173       break;
5174
5175     case RELOAD_FOR_OUTPUT_ADDRESS:
5176       used_in_set = &reload_reg_used_in_output_addr[opnum];
5177       break;
5178
5179     case RELOAD_FOR_OUTADDR_ADDRESS:
5180       check_opnum = 1;
5181       used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5182       break;
5183
5184     case RELOAD_FOR_OPERAND_ADDRESS:
5185       used_in_set = &reload_reg_used_in_op_addr;
5186       break;
5187
5188     case RELOAD_FOR_OPADDR_ADDR:
5189       check_any = 1;
5190       used_in_set = &reload_reg_used_in_op_addr_reload;
5191       break;
5192
5193     case RELOAD_FOR_OTHER_ADDRESS:
5194       used_in_set = &reload_reg_used_in_other_addr;
5195       check_any = 1;
5196       break;
5197
5198     case RELOAD_FOR_INPUT:
5199       used_in_set = &reload_reg_used_in_input[opnum];
5200       break;
5201
5202     case RELOAD_FOR_OUTPUT:
5203       used_in_set = &reload_reg_used_in_output[opnum];
5204       break;
5205
5206     case RELOAD_FOR_INSN:
5207       used_in_set = &reload_reg_used_in_insn;
5208       break;
5209     default:
5210       gcc_unreachable ();
5211     }
5212   /* We resolve conflicts with remaining reloads of the same type by
5213      excluding the intervals of reload registers by them from the
5214      interval of freed reload registers.  Since we only keep track of
5215      one set of interval bounds, we might have to exclude somewhat
5216      more than what would be necessary if we used a HARD_REG_SET here.
5217      But this should only happen very infrequently, so there should
5218      be no reason to worry about it.  */
5219
5220   start_regno = regno;
5221   end_regno = regno + nregs;
5222   if (check_opnum || check_any)
5223     {
5224       for (i = n_reloads - 1; i >= 0; i--)
5225         {
5226           if (rld[i].when_needed == type
5227               && (check_any || rld[i].opnum == opnum)
5228               && rld[i].reg_rtx)
5229             {
5230               unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5231               unsigned int conflict_end
5232                 = end_hard_regno (rld[i].mode, conflict_start);
5233
5234               /* If there is an overlap with the first to-be-freed register,
5235                  adjust the interval start.  */
5236               if (conflict_start <= start_regno && conflict_end > start_regno)
5237                 start_regno = conflict_end;
5238               /* Otherwise, if there is a conflict with one of the other
5239                  to-be-freed registers, adjust the interval end.  */
5240               if (conflict_start > start_regno && conflict_start < end_regno)
5241                 end_regno = conflict_start;
5242             }
5243         }
5244     }
5245
5246   for (r = start_regno; r < end_regno; r++)
5247     CLEAR_HARD_REG_BIT (*used_in_set, r);
5248 }
5249
5250 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5251    specified by OPNUM and TYPE.  */
5252
5253 static int
5254 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5255 {
5256   int i;
5257
5258   /* In use for a RELOAD_OTHER means it's not available for anything.  */
5259   if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5260       || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5261     return 0;
5262
5263   switch (type)
5264     {
5265     case RELOAD_OTHER:
5266       /* In use for anything means we can't use it for RELOAD_OTHER.  */
5267       if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5268           || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5269           || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5270           || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5271         return 0;
5272
5273       for (i = 0; i < reload_n_operands; i++)
5274         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5275             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5276             || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5277             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5278             || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5279             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5280           return 0;
5281
5282       return 1;
5283
5284     case RELOAD_FOR_INPUT:
5285       if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5286           || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5287         return 0;
5288
5289       if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5290         return 0;
5291
5292       /* If it is used for some other input, can't use it.  */
5293       for (i = 0; i < reload_n_operands; i++)
5294         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5295           return 0;
5296
5297       /* If it is used in a later operand's address, can't use it.  */
5298       for (i = opnum + 1; i < reload_n_operands; i++)
5299         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5300             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5301           return 0;
5302
5303       return 1;
5304
5305     case RELOAD_FOR_INPUT_ADDRESS:
5306       /* Can't use a register if it is used for an input address for this
5307          operand or used as an input in an earlier one.  */
5308       if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5309           || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5310         return 0;
5311
5312       for (i = 0; i < opnum; i++)
5313         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5314           return 0;
5315
5316       return 1;
5317
5318     case RELOAD_FOR_INPADDR_ADDRESS:
5319       /* Can't use a register if it is used for an input address
5320          for this operand or used as an input in an earlier
5321          one.  */
5322       if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5323         return 0;
5324
5325       for (i = 0; i < opnum; i++)
5326         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5327           return 0;
5328
5329       return 1;
5330
5331     case RELOAD_FOR_OUTPUT_ADDRESS:
5332       /* Can't use a register if it is used for an output address for this
5333          operand or used as an output in this or a later operand.  Note
5334          that multiple output operands are emitted in reverse order, so
5335          the conflicting ones are those with lower indices.  */
5336       if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5337         return 0;
5338
5339       for (i = 0; i <= opnum; i++)
5340         if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5341           return 0;
5342
5343       return 1;
5344
5345     case RELOAD_FOR_OUTADDR_ADDRESS:
5346       /* Can't use a register if it is used for an output address
5347          for this operand or used as an output in this or a
5348          later operand.  Note that multiple output operands are
5349          emitted in reverse order, so the conflicting ones are
5350          those with lower indices.  */
5351       if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5352         return 0;
5353
5354       for (i = 0; i <= opnum; i++)
5355         if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5356           return 0;
5357
5358       return 1;
5359
5360     case RELOAD_FOR_OPERAND_ADDRESS:
5361       for (i = 0; i < reload_n_operands; i++)
5362         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5363           return 0;
5364
5365       return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5366               && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5367
5368     case RELOAD_FOR_OPADDR_ADDR:
5369       for (i = 0; i < reload_n_operands; i++)
5370         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5371           return 0;
5372
5373       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5374
5375     case RELOAD_FOR_OUTPUT:
5376       /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5377          outputs, or an operand address for this or an earlier output.
5378          Note that multiple output operands are emitted in reverse order,
5379          so the conflicting ones are those with higher indices.  */
5380       if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5381         return 0;
5382
5383       for (i = 0; i < reload_n_operands; i++)
5384         if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5385           return 0;
5386
5387       for (i = opnum; i < reload_n_operands; i++)
5388         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5389             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5390           return 0;
5391
5392       return 1;
5393
5394     case RELOAD_FOR_INSN:
5395       for (i = 0; i < reload_n_operands; i++)
5396         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5397             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5398           return 0;
5399
5400       return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5401               && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5402
5403     case RELOAD_FOR_OTHER_ADDRESS:
5404       return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5405
5406     default:
5407       gcc_unreachable ();
5408     }
5409 }
5410
5411 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5412    the number RELOADNUM, is still available in REGNO at the end of the insn.
5413
5414    We can assume that the reload reg was already tested for availability
5415    at the time it is needed, and we should not check this again,
5416    in case the reg has already been marked in use.  */
5417
5418 static int
5419 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5420 {
5421   int opnum = rld[reloadnum].opnum;
5422   enum reload_type type = rld[reloadnum].when_needed;
5423   int i;
5424
5425   /* See if there is a reload with the same type for this operand, using
5426      the same register. This case is not handled by the code below.  */
5427   for (i = reloadnum + 1; i < n_reloads; i++)
5428     {
5429       rtx reg;
5430       int nregs;
5431
5432       if (rld[i].opnum != opnum || rld[i].when_needed != type)
5433         continue;
5434       reg = rld[i].reg_rtx;
5435       if (reg == NULL_RTX)
5436         continue;
5437       nregs = hard_regno_nregs[REGNO (reg)][GET_MODE (reg)];
5438       if (regno >= REGNO (reg) && regno < REGNO (reg) + nregs)
5439         return 0;
5440     }
5441
5442   switch (type)
5443     {
5444     case RELOAD_OTHER:
5445       /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5446          its value must reach the end.  */
5447       return 1;
5448
5449       /* If this use is for part of the insn,
5450          its value reaches if no subsequent part uses the same register.
5451          Just like the above function, don't try to do this with lots
5452          of fallthroughs.  */
5453
5454     case RELOAD_FOR_OTHER_ADDRESS:
5455       /* Here we check for everything else, since these don't conflict
5456          with anything else and everything comes later.  */
5457
5458       for (i = 0; i < reload_n_operands; i++)
5459         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5460             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5461             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5462             || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5463             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5464             || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5465           return 0;
5466
5467       return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5468               && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5469               && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5470               && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5471
5472     case RELOAD_FOR_INPUT_ADDRESS:
5473     case RELOAD_FOR_INPADDR_ADDRESS:
5474       /* Similar, except that we check only for this and subsequent inputs
5475          and the address of only subsequent inputs and we do not need
5476          to check for RELOAD_OTHER objects since they are known not to
5477          conflict.  */
5478
5479       for (i = opnum; i < reload_n_operands; i++)
5480         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5481           return 0;
5482
5483       /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5484          could be killed if the register is also used by reload with type
5485          RELOAD_FOR_INPUT_ADDRESS, so check it.  */
5486       if (type == RELOAD_FOR_INPADDR_ADDRESS
5487           && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5488         return 0;
5489
5490       for (i = opnum + 1; i < reload_n_operands; i++)
5491         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5492             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5493           return 0;
5494
5495       for (i = 0; i < reload_n_operands; i++)
5496         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5497             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5498             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5499           return 0;
5500
5501       if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5502         return 0;
5503
5504       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5505               && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5506               && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5507
5508     case RELOAD_FOR_INPUT:
5509       /* Similar to input address, except we start at the next operand for
5510          both input and input address and we do not check for
5511          RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5512          would conflict.  */
5513
5514       for (i = opnum + 1; i < reload_n_operands; i++)
5515         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5516             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5517             || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5518           return 0;
5519
5520       /* ... fall through ...  */
5521
5522     case RELOAD_FOR_OPERAND_ADDRESS:
5523       /* Check outputs and their addresses.  */
5524
5525       for (i = 0; i < reload_n_operands; i++)
5526         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5527             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5528             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5529           return 0;
5530
5531       return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5532
5533     case RELOAD_FOR_OPADDR_ADDR:
5534       for (i = 0; i < reload_n_operands; i++)
5535         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5536             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5537             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5538           return 0;
5539
5540       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5541               && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5542               && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5543
5544     case RELOAD_FOR_INSN:
5545       /* These conflict with other outputs with RELOAD_OTHER.  So
5546          we need only check for output addresses.  */
5547
5548       opnum = reload_n_operands;
5549
5550       /* ... fall through ...  */
5551
5552     case RELOAD_FOR_OUTPUT:
5553     case RELOAD_FOR_OUTPUT_ADDRESS:
5554     case RELOAD_FOR_OUTADDR_ADDRESS:
5555       /* We already know these can't conflict with a later output.  So the
5556          only thing to check are later output addresses.
5557          Note that multiple output operands are emitted in reverse order,
5558          so the conflicting ones are those with lower indices.  */
5559       for (i = 0; i < opnum; i++)
5560         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5561             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5562           return 0;
5563
5564       /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5565          could be killed if the register is also used by reload with type
5566          RELOAD_FOR_OUTPUT_ADDRESS, so check it.  */
5567       if (type == RELOAD_FOR_OUTADDR_ADDRESS
5568           && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5569         return 0;
5570
5571       return 1;
5572
5573     default:
5574       gcc_unreachable ();
5575     }
5576 }
5577
5578 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5579    every register in REG.  */
5580
5581 static bool
5582 reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5583 {
5584   unsigned int i;
5585
5586   for (i = REGNO (reg); i < END_REGNO (reg); i++)
5587     if (!reload_reg_reaches_end_p (i, reloadnum))
5588       return false;
5589   return true;
5590 }
5591 \f
5592
5593 /*  Returns whether R1 and R2 are uniquely chained: the value of one
5594     is used by the other, and that value is not used by any other
5595     reload for this insn.  This is used to partially undo the decision
5596     made in find_reloads when in the case of multiple
5597     RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5598     RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5599     reloads.  This code tries to avoid the conflict created by that
5600     change.  It might be cleaner to explicitly keep track of which
5601     RELOAD_FOR_OPADDR_ADDR reload is associated with which
5602     RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5603     this after the fact. */
5604 static bool
5605 reloads_unique_chain_p (int r1, int r2)
5606 {
5607   int i;
5608
5609   /* We only check input reloads.  */
5610   if (! rld[r1].in || ! rld[r2].in)
5611     return false;
5612
5613   /* Avoid anything with output reloads.  */
5614   if (rld[r1].out || rld[r2].out)
5615     return false;
5616
5617   /* "chained" means one reload is a component of the other reload,
5618      not the same as the other reload.  */
5619   if (rld[r1].opnum != rld[r2].opnum
5620       || rtx_equal_p (rld[r1].in, rld[r2].in)
5621       || rld[r1].optional || rld[r2].optional
5622       || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5623             || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5624     return false;
5625
5626   /* The following loop assumes that r1 is the reload that feeds r2.  */
5627   if (r1 > r2)
5628     {
5629       int tmp = r2;
5630       r2 = r1;
5631       r1 = tmp;
5632     }
5633
5634   for (i = 0; i < n_reloads; i ++)
5635     /* Look for input reloads that aren't our two */
5636     if (i != r1 && i != r2 && rld[i].in)
5637       {
5638         /* If our reload is mentioned at all, it isn't a simple chain.  */
5639         if (reg_mentioned_p (rld[r1].in, rld[i].in))
5640           return false;
5641       }
5642   return true;
5643 }
5644
5645 /* The recursive function change all occurrences of WHAT in *WHERE
5646    to REPL.  */
5647 static void
5648 substitute (rtx *where, const_rtx what, rtx repl)
5649 {
5650   const char *fmt;
5651   int i;
5652   enum rtx_code code;
5653
5654   if (*where == 0)
5655     return;
5656
5657   if (*where == what || rtx_equal_p (*where, what))
5658     {
5659       /* Record the location of the changed rtx.  */
5660       substitute_stack.safe_push (where);
5661       *where = repl;
5662       return;
5663     }
5664
5665   code = GET_CODE (*where);
5666   fmt = GET_RTX_FORMAT (code);
5667   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5668     {
5669       if (fmt[i] == 'E')
5670         {
5671           int j;
5672
5673           for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5674             substitute (&XVECEXP (*where, i, j), what, repl);
5675         }
5676       else if (fmt[i] == 'e')
5677         substitute (&XEXP (*where, i), what, repl);
5678     }
5679 }
5680
5681 /* The function returns TRUE if chain of reload R1 and R2 (in any
5682    order) can be evaluated without usage of intermediate register for
5683    the reload containing another reload.  It is important to see
5684    gen_reload to understand what the function is trying to do.  As an
5685    example, let us have reload chain
5686
5687       r2: const
5688       r1: <something> + const
5689
5690    and reload R2 got reload reg HR.  The function returns true if
5691    there is a correct insn HR = HR + <something>.  Otherwise,
5692    gen_reload will use intermediate register (and this is the reload
5693    reg for R1) to reload <something>.
5694
5695    We need this function to find a conflict for chain reloads.  In our
5696    example, if HR = HR + <something> is incorrect insn, then we cannot
5697    use HR as a reload register for R2.  If we do use it then we get a
5698    wrong code:
5699
5700       HR = const
5701       HR = <something>
5702       HR = HR + HR
5703
5704 */
5705 static bool
5706 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5707 {
5708   /* Assume other cases in gen_reload are not possible for
5709      chain reloads or do need an intermediate hard registers.  */
5710   bool result = true;
5711   int regno, n, code;
5712   rtx out, in;
5713   rtx_insn *insn;
5714   rtx_insn *last = get_last_insn ();
5715
5716   /* Make r2 a component of r1.  */
5717   if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5718     {
5719       n = r1;
5720       r1 = r2;
5721       r2 = n;
5722     }
5723   gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5724   regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5725   gcc_assert (regno >= 0);
5726   out = gen_rtx_REG (rld[r1].mode, regno);
5727   in = rld[r1].in;
5728   substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5729
5730   /* If IN is a paradoxical SUBREG, remove it and try to put the
5731      opposite SUBREG on OUT.  Likewise for a paradoxical SUBREG on OUT.  */
5732   strip_paradoxical_subreg (&in, &out);
5733
5734   if (GET_CODE (in) == PLUS
5735       && (REG_P (XEXP (in, 0))
5736           || GET_CODE (XEXP (in, 0)) == SUBREG
5737           || MEM_P (XEXP (in, 0)))
5738       && (REG_P (XEXP (in, 1))
5739           || GET_CODE (XEXP (in, 1)) == SUBREG
5740           || CONSTANT_P (XEXP (in, 1))
5741           || MEM_P (XEXP (in, 1))))
5742     {
5743       insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5744       code = recog_memoized (insn);
5745       result = false;
5746
5747       if (code >= 0)
5748         {
5749           extract_insn (insn);
5750           /* We want constrain operands to treat this insn strictly in
5751              its validity determination, i.e., the way it would after
5752              reload has completed.  */
5753           result = constrain_operands (1, get_enabled_alternatives (insn));
5754         }
5755
5756       delete_insns_since (last);
5757     }
5758
5759   /* Restore the original value at each changed address within R1.  */
5760   while (!substitute_stack.is_empty ())
5761     {
5762       rtx *where = substitute_stack.pop ();
5763       *where = rld[r2].in;
5764     }
5765
5766   return result;
5767 }
5768
5769 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5770    Return 0 otherwise.
5771
5772    This function uses the same algorithm as reload_reg_free_p above.  */
5773
5774 static int
5775 reloads_conflict (int r1, int r2)
5776 {
5777   enum reload_type r1_type = rld[r1].when_needed;
5778   enum reload_type r2_type = rld[r2].when_needed;
5779   int r1_opnum = rld[r1].opnum;
5780   int r2_opnum = rld[r2].opnum;
5781
5782   /* RELOAD_OTHER conflicts with everything.  */
5783   if (r2_type == RELOAD_OTHER)
5784     return 1;
5785
5786   /* Otherwise, check conflicts differently for each type.  */
5787
5788   switch (r1_type)
5789     {
5790     case RELOAD_FOR_INPUT:
5791       return (r2_type == RELOAD_FOR_INSN
5792               || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5793               || r2_type == RELOAD_FOR_OPADDR_ADDR
5794               || r2_type == RELOAD_FOR_INPUT
5795               || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5796                    || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5797                   && r2_opnum > r1_opnum));
5798
5799     case RELOAD_FOR_INPUT_ADDRESS:
5800       return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5801               || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5802
5803     case RELOAD_FOR_INPADDR_ADDRESS:
5804       return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5805               || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5806
5807     case RELOAD_FOR_OUTPUT_ADDRESS:
5808       return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5809               || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5810
5811     case RELOAD_FOR_OUTADDR_ADDRESS:
5812       return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5813               || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5814
5815     case RELOAD_FOR_OPERAND_ADDRESS:
5816       return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5817               || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5818                   && (!reloads_unique_chain_p (r1, r2)
5819                       || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5820
5821     case RELOAD_FOR_OPADDR_ADDR:
5822       return (r2_type == RELOAD_FOR_INPUT
5823               || r2_type == RELOAD_FOR_OPADDR_ADDR);
5824
5825     case RELOAD_FOR_OUTPUT:
5826       return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5827               || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5828                    || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5829                   && r2_opnum >= r1_opnum));
5830
5831     case RELOAD_FOR_INSN:
5832       return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5833               || r2_type == RELOAD_FOR_INSN
5834               || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5835
5836     case RELOAD_FOR_OTHER_ADDRESS:
5837       return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5838
5839     case RELOAD_OTHER:
5840       return 1;
5841
5842     default:
5843       gcc_unreachable ();
5844     }
5845 }
5846 \f
5847 /* Indexed by reload number, 1 if incoming value
5848    inherited from previous insns.  */
5849 static char reload_inherited[MAX_RELOADS];
5850
5851 /* For an inherited reload, this is the insn the reload was inherited from,
5852    if we know it.  Otherwise, this is 0.  */
5853 static rtx_insn *reload_inheritance_insn[MAX_RELOADS];
5854
5855 /* If nonzero, this is a place to get the value of the reload,
5856    rather than using reload_in.  */
5857 static rtx reload_override_in[MAX_RELOADS];
5858
5859 /* For each reload, the hard register number of the register used,
5860    or -1 if we did not need a register for this reload.  */
5861 static int reload_spill_index[MAX_RELOADS];
5862
5863 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode.  */
5864 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5865
5866 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode.  */
5867 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5868
5869 /* Subroutine of free_for_value_p, used to check a single register.
5870    START_REGNO is the starting regno of the full reload register
5871    (possibly comprising multiple hard registers) that we are considering.  */
5872
5873 static int
5874 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5875                              enum reload_type type, rtx value, rtx out,
5876                              int reloadnum, int ignore_address_reloads)
5877 {
5878   int time1;
5879   /* Set if we see an input reload that must not share its reload register
5880      with any new earlyclobber, but might otherwise share the reload
5881      register with an output or input-output reload.  */
5882   int check_earlyclobber = 0;
5883   int i;
5884   int copy = 0;
5885
5886   if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5887     return 0;
5888
5889   if (out == const0_rtx)
5890     {
5891       copy = 1;
5892       out = NULL_RTX;
5893     }
5894
5895   /* We use some pseudo 'time' value to check if the lifetimes of the
5896      new register use would overlap with the one of a previous reload
5897      that is not read-only or uses a different value.
5898      The 'time' used doesn't have to be linear in any shape or form, just
5899      monotonic.
5900      Some reload types use different 'buckets' for each operand.
5901      So there are MAX_RECOG_OPERANDS different time values for each
5902      such reload type.
5903      We compute TIME1 as the time when the register for the prospective
5904      new reload ceases to be live, and TIME2 for each existing
5905      reload as the time when that the reload register of that reload
5906      becomes live.
5907      Where there is little to be gained by exact lifetime calculations,
5908      we just make conservative assumptions, i.e. a longer lifetime;
5909      this is done in the 'default:' cases.  */
5910   switch (type)
5911     {
5912     case RELOAD_FOR_OTHER_ADDRESS:
5913       /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads.  */
5914       time1 = copy ? 0 : 1;
5915       break;
5916     case RELOAD_OTHER:
5917       time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5918       break;
5919       /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5920          RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT.  By adding 0 / 1 / 2 ,
5921          respectively, to the time values for these, we get distinct time
5922          values.  To get distinct time values for each operand, we have to
5923          multiply opnum by at least three.  We round that up to four because
5924          multiply by four is often cheaper.  */
5925     case RELOAD_FOR_INPADDR_ADDRESS:
5926       time1 = opnum * 4 + 2;
5927       break;
5928     case RELOAD_FOR_INPUT_ADDRESS:
5929       time1 = opnum * 4 + 3;
5930       break;
5931     case RELOAD_FOR_INPUT:
5932       /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5933          executes (inclusive).  */
5934       time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5935       break;
5936     case RELOAD_FOR_OPADDR_ADDR:
5937       /* opnum * 4 + 4
5938          <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5939       time1 = MAX_RECOG_OPERANDS * 4 + 1;
5940       break;
5941     case RELOAD_FOR_OPERAND_ADDRESS:
5942       /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5943          is executed.  */
5944       time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5945       break;
5946     case RELOAD_FOR_OUTADDR_ADDRESS:
5947       time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5948       break;
5949     case RELOAD_FOR_OUTPUT_ADDRESS:
5950       time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5951       break;
5952     default:
5953       time1 = MAX_RECOG_OPERANDS * 5 + 5;
5954     }
5955
5956   for (i = 0; i < n_reloads; i++)
5957     {
5958       rtx reg = rld[i].reg_rtx;
5959       if (reg && REG_P (reg)
5960           && ((unsigned) regno - true_regnum (reg)
5961               <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5962           && i != reloadnum)
5963         {
5964           rtx other_input = rld[i].in;
5965
5966           /* If the other reload loads the same input value, that
5967              will not cause a conflict only if it's loading it into
5968              the same register.  */
5969           if (true_regnum (reg) != start_regno)
5970             other_input = NULL_RTX;
5971           if (! other_input || ! rtx_equal_p (other_input, value)
5972               || rld[i].out || out)
5973             {
5974               int time2;
5975               switch (rld[i].when_needed)
5976                 {
5977                 case RELOAD_FOR_OTHER_ADDRESS:
5978                   time2 = 0;
5979                   break;
5980                 case RELOAD_FOR_INPADDR_ADDRESS:
5981                   /* find_reloads makes sure that a
5982                      RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5983                      by at most one - the first -
5984                      RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS .  If the
5985                      address reload is inherited, the address address reload
5986                      goes away, so we can ignore this conflict.  */
5987                   if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5988                       && ignore_address_reloads
5989                       /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5990                          Then the address address is still needed to store
5991                          back the new address.  */
5992                       && ! rld[reloadnum].out)
5993                     continue;
5994                   /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5995                      RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5996                      reloads go away.  */
5997                   if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5998                       && ignore_address_reloads
5999                       /* Unless we are reloading an auto_inc expression.  */
6000                       && ! rld[reloadnum].out)
6001                     continue;
6002                   time2 = rld[i].opnum * 4 + 2;
6003                   break;
6004                 case RELOAD_FOR_INPUT_ADDRESS:
6005                   if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
6006                       && ignore_address_reloads
6007                       && ! rld[reloadnum].out)
6008                     continue;
6009                   time2 = rld[i].opnum * 4 + 3;
6010                   break;
6011                 case RELOAD_FOR_INPUT:
6012                   time2 = rld[i].opnum * 4 + 4;
6013                   check_earlyclobber = 1;
6014                   break;
6015                   /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
6016                      == MAX_RECOG_OPERAND * 4  */
6017                 case RELOAD_FOR_OPADDR_ADDR:
6018                   if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
6019                       && ignore_address_reloads
6020                       && ! rld[reloadnum].out)
6021                     continue;
6022                   time2 = MAX_RECOG_OPERANDS * 4 + 1;
6023                   break;
6024                 case RELOAD_FOR_OPERAND_ADDRESS:
6025                   time2 = MAX_RECOG_OPERANDS * 4 + 2;
6026                   check_earlyclobber = 1;
6027                   break;
6028                 case RELOAD_FOR_INSN:
6029                   time2 = MAX_RECOG_OPERANDS * 4 + 3;
6030                   break;
6031                 case RELOAD_FOR_OUTPUT:
6032                   /* All RELOAD_FOR_OUTPUT reloads become live just after the
6033                      instruction is executed.  */
6034                   time2 = MAX_RECOG_OPERANDS * 4 + 4;
6035                   break;
6036                   /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
6037                      the RELOAD_FOR_OUTPUT reloads, so assign it the same time
6038                      value.  */
6039                 case RELOAD_FOR_OUTADDR_ADDRESS:
6040                   if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
6041                       && ignore_address_reloads
6042                       && ! rld[reloadnum].out)
6043                     continue;
6044                   time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
6045                   break;
6046                 case RELOAD_FOR_OUTPUT_ADDRESS:
6047                   time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
6048                   break;
6049                 case RELOAD_OTHER:
6050                   /* If there is no conflict in the input part, handle this
6051                      like an output reload.  */
6052                   if (! rld[i].in || rtx_equal_p (other_input, value))
6053                     {
6054                       time2 = MAX_RECOG_OPERANDS * 4 + 4;
6055                       /* Earlyclobbered outputs must conflict with inputs.  */
6056                       if (earlyclobber_operand_p (rld[i].out))
6057                         time2 = MAX_RECOG_OPERANDS * 4 + 3;
6058
6059                       break;
6060                     }
6061                   time2 = 1;
6062                   /* RELOAD_OTHER might be live beyond instruction execution,
6063                      but this is not obvious when we set time2 = 1.  So check
6064                      here if there might be a problem with the new reload
6065                      clobbering the register used by the RELOAD_OTHER.  */
6066                   if (out)
6067                     return 0;
6068                   break;
6069                 default:
6070                   return 0;
6071                 }
6072               if ((time1 >= time2
6073                    && (! rld[i].in || rld[i].out
6074                        || ! rtx_equal_p (other_input, value)))
6075                   || (out && rld[reloadnum].out_reg
6076                       && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
6077                 return 0;
6078             }
6079         }
6080     }
6081
6082   /* Earlyclobbered outputs must conflict with inputs.  */
6083   if (check_earlyclobber && out && earlyclobber_operand_p (out))
6084     return 0;
6085
6086   return 1;
6087 }
6088
6089 /* Return 1 if the value in reload reg REGNO, as used by a reload
6090    needed for the part of the insn specified by OPNUM and TYPE,
6091    may be used to load VALUE into it.
6092
6093    MODE is the mode in which the register is used, this is needed to
6094    determine how many hard regs to test.
6095
6096    Other read-only reloads with the same value do not conflict
6097    unless OUT is nonzero and these other reloads have to live while
6098    output reloads live.
6099    If OUT is CONST0_RTX, this is a special case: it means that the
6100    test should not be for using register REGNO as reload register, but
6101    for copying from register REGNO into the reload register.
6102
6103    RELOADNUM is the number of the reload we want to load this value for;
6104    a reload does not conflict with itself.
6105
6106    When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6107    reloads that load an address for the very reload we are considering.
6108
6109    The caller has to make sure that there is no conflict with the return
6110    register.  */
6111
6112 static int
6113 free_for_value_p (int regno, machine_mode mode, int opnum,
6114                   enum reload_type type, rtx value, rtx out, int reloadnum,
6115                   int ignore_address_reloads)
6116 {
6117   int nregs = hard_regno_nregs[regno][mode];
6118   while (nregs-- > 0)
6119     if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6120                                        value, out, reloadnum,
6121                                        ignore_address_reloads))
6122       return 0;
6123   return 1;
6124 }
6125
6126 /* Return nonzero if the rtx X is invariant over the current function.  */
6127 /* ??? Actually, the places where we use this expect exactly what is
6128    tested here, and not everything that is function invariant.  In
6129    particular, the frame pointer and arg pointer are special cased;
6130    pic_offset_table_rtx is not, and we must not spill these things to
6131    memory.  */
6132
6133 int
6134 function_invariant_p (const_rtx x)
6135 {
6136   if (CONSTANT_P (x))
6137     return 1;
6138   if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6139     return 1;
6140   if (GET_CODE (x) == PLUS
6141       && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6142       && GET_CODE (XEXP (x, 1)) == CONST_INT)
6143     return 1;
6144   return 0;
6145 }
6146
6147 /* Determine whether the reload reg X overlaps any rtx'es used for
6148    overriding inheritance.  Return nonzero if so.  */
6149
6150 static int
6151 conflicts_with_override (rtx x)
6152 {
6153   int i;
6154   for (i = 0; i < n_reloads; i++)
6155     if (reload_override_in[i]
6156         && reg_overlap_mentioned_p (x, reload_override_in[i]))
6157       return 1;
6158   return 0;
6159 }
6160 \f
6161 /* Give an error message saying we failed to find a reload for INSN,
6162    and clear out reload R.  */
6163 static void
6164 failed_reload (rtx_insn *insn, int r)
6165 {
6166   if (asm_noperands (PATTERN (insn)) < 0)
6167     /* It's the compiler's fault.  */
6168     fatal_insn ("could not find a spill register", insn);
6169
6170   /* It's the user's fault; the operand's mode and constraint
6171      don't match.  Disable this reload so we don't crash in final.  */
6172   error_for_asm (insn,
6173                  "%<asm%> operand constraint incompatible with operand size");
6174   rld[r].in = 0;
6175   rld[r].out = 0;
6176   rld[r].reg_rtx = 0;
6177   rld[r].optional = 1;
6178   rld[r].secondary_p = 1;
6179 }
6180
6181 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6182    for reload R.  If it's valid, get an rtx for it.  Return nonzero if
6183    successful.  */
6184 static int
6185 set_reload_reg (int i, int r)
6186 {
6187   /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6188      parameter.  */
6189   int regno ATTRIBUTE_UNUSED;
6190   rtx reg = spill_reg_rtx[i];
6191
6192   if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6193     spill_reg_rtx[i] = reg
6194       = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6195
6196   regno = true_regnum (reg);
6197
6198   /* Detect when the reload reg can't hold the reload mode.
6199      This used to be one `if', but Sequent compiler can't handle that.  */
6200   if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6201     {
6202       machine_mode test_mode = VOIDmode;
6203       if (rld[r].in)
6204         test_mode = GET_MODE (rld[r].in);
6205       /* If rld[r].in has VOIDmode, it means we will load it
6206          in whatever mode the reload reg has: to wit, rld[r].mode.
6207          We have already tested that for validity.  */
6208       /* Aside from that, we need to test that the expressions
6209          to reload from or into have modes which are valid for this
6210          reload register.  Otherwise the reload insns would be invalid.  */
6211       if (! (rld[r].in != 0 && test_mode != VOIDmode
6212              && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6213         if (! (rld[r].out != 0
6214                && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6215           {
6216             /* The reg is OK.  */
6217             last_spill_reg = i;
6218
6219             /* Mark as in use for this insn the reload regs we use
6220                for this.  */
6221             mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6222                                     rld[r].when_needed, rld[r].mode);
6223
6224             rld[r].reg_rtx = reg;
6225             reload_spill_index[r] = spill_regs[i];
6226             return 1;
6227           }
6228     }
6229   return 0;
6230 }
6231
6232 /* Find a spill register to use as a reload register for reload R.
6233    LAST_RELOAD is nonzero if this is the last reload for the insn being
6234    processed.
6235
6236    Set rld[R].reg_rtx to the register allocated.
6237
6238    We return 1 if successful, or 0 if we couldn't find a spill reg and
6239    we didn't change anything.  */
6240
6241 static int
6242 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6243                      int last_reload)
6244 {
6245   int i, pass, count;
6246
6247   /* If we put this reload ahead, thinking it is a group,
6248      then insist on finding a group.  Otherwise we can grab a
6249      reg that some other reload needs.
6250      (That can happen when we have a 68000 DATA_OR_FP_REG
6251      which is a group of data regs or one fp reg.)
6252      We need not be so restrictive if there are no more reloads
6253      for this insn.
6254
6255      ??? Really it would be nicer to have smarter handling
6256      for that kind of reg class, where a problem like this is normal.
6257      Perhaps those classes should be avoided for reloading
6258      by use of more alternatives.  */
6259
6260   int force_group = rld[r].nregs > 1 && ! last_reload;
6261
6262   /* If we want a single register and haven't yet found one,
6263      take any reg in the right class and not in use.
6264      If we want a consecutive group, here is where we look for it.
6265
6266      We use three passes so we can first look for reload regs to
6267      reuse, which are already in use for other reloads in this insn,
6268      and only then use additional registers which are not "bad", then
6269      finally any register.
6270
6271      I think that maximizing reuse is needed to make sure we don't
6272      run out of reload regs.  Suppose we have three reloads, and
6273      reloads A and B can share regs.  These need two regs.
6274      Suppose A and B are given different regs.
6275      That leaves none for C.  */
6276   for (pass = 0; pass < 3; pass++)
6277     {
6278       /* I is the index in spill_regs.
6279          We advance it round-robin between insns to use all spill regs
6280          equally, so that inherited reloads have a chance
6281          of leapfrogging each other.  */
6282
6283       i = last_spill_reg;
6284
6285       for (count = 0; count < n_spills; count++)
6286         {
6287           int rclass = (int) rld[r].rclass;
6288           int regnum;
6289
6290           i++;
6291           if (i >= n_spills)
6292             i -= n_spills;
6293           regnum = spill_regs[i];
6294
6295           if ((reload_reg_free_p (regnum, rld[r].opnum,
6296                                   rld[r].when_needed)
6297                || (rld[r].in
6298                    /* We check reload_reg_used to make sure we
6299                       don't clobber the return register.  */
6300                    && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6301                    && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6302                                         rld[r].when_needed, rld[r].in,
6303                                         rld[r].out, r, 1)))
6304               && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6305               && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6306               /* Look first for regs to share, then for unshared.  But
6307                  don't share regs used for inherited reloads; they are
6308                  the ones we want to preserve.  */
6309               && (pass
6310                   || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6311                                          regnum)
6312                       && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6313                                               regnum))))
6314             {
6315               int nr = hard_regno_nregs[regnum][rld[r].mode];
6316
6317               /* During the second pass we want to avoid reload registers
6318                  which are "bad" for this reload.  */
6319               if (pass == 1
6320                   && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6321                 continue;
6322
6323               /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6324                  (on 68000) got us two FP regs.  If NR is 1,
6325                  we would reject both of them.  */
6326               if (force_group)
6327                 nr = rld[r].nregs;
6328               /* If we need only one reg, we have already won.  */
6329               if (nr == 1)
6330                 {
6331                   /* But reject a single reg if we demand a group.  */
6332                   if (force_group)
6333                     continue;
6334                   break;
6335                 }
6336               /* Otherwise check that as many consecutive regs as we need
6337                  are available here.  */
6338               while (nr > 1)
6339                 {
6340                   int regno = regnum + nr - 1;
6341                   if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6342                         && spill_reg_order[regno] >= 0
6343                         && reload_reg_free_p (regno, rld[r].opnum,
6344                                               rld[r].when_needed)))
6345                     break;
6346                   nr--;
6347                 }
6348               if (nr == 1)
6349                 break;
6350             }
6351         }
6352
6353       /* If we found something on the current pass, omit later passes.  */
6354       if (count < n_spills)
6355         break;
6356     }
6357
6358   /* We should have found a spill register by now.  */
6359   if (count >= n_spills)
6360     return 0;
6361
6362   /* I is the index in SPILL_REG_RTX of the reload register we are to
6363      allocate.  Get an rtx for it and find its register number.  */
6364
6365   return set_reload_reg (i, r);
6366 }
6367 \f
6368 /* Initialize all the tables needed to allocate reload registers.
6369    CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6370    is the array we use to restore the reg_rtx field for every reload.  */
6371
6372 static void
6373 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6374 {
6375   int i;
6376
6377   for (i = 0; i < n_reloads; i++)
6378     rld[i].reg_rtx = save_reload_reg_rtx[i];
6379
6380   memset (reload_inherited, 0, MAX_RELOADS);
6381   memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6382   memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6383
6384   CLEAR_HARD_REG_SET (reload_reg_used);
6385   CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6386   CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6387   CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6388   CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6389   CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6390
6391   CLEAR_HARD_REG_SET (reg_used_in_insn);
6392   {
6393     HARD_REG_SET tmp;
6394     REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6395     IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6396     REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6397     IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6398     compute_use_by_pseudos (&reg_used_in_insn, &chain->live_throughout);
6399     compute_use_by_pseudos (&reg_used_in_insn, &chain->dead_or_set);
6400   }
6401
6402   for (i = 0; i < reload_n_operands; i++)
6403     {
6404       CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6405       CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6406       CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6407       CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6408       CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6409       CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6410     }
6411
6412   COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6413
6414   CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6415
6416   for (i = 0; i < n_reloads; i++)
6417     /* If we have already decided to use a certain register,
6418        don't use it in another way.  */
6419     if (rld[i].reg_rtx)
6420       mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6421                               rld[i].when_needed, rld[i].mode);
6422 }
6423
6424 #ifdef SECONDARY_MEMORY_NEEDED
6425 /* If X is not a subreg, return it unmodified.  If it is a subreg,
6426    look up whether we made a replacement for the SUBREG_REG.  Return
6427    either the replacement or the SUBREG_REG.  */
6428
6429 static rtx
6430 replaced_subreg (rtx x)
6431 {
6432   if (GET_CODE (x) == SUBREG)
6433     return find_replacement (&SUBREG_REG (x));
6434   return x;
6435 }
6436 #endif
6437
6438 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6439    mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6440    SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6441    otherwise it is NULL.  */
6442
6443 static int
6444 compute_reload_subreg_offset (machine_mode outermode,
6445                               rtx subreg,
6446                               machine_mode innermode)
6447 {
6448   int outer_offset;
6449   machine_mode middlemode;
6450
6451   if (!subreg)
6452     return subreg_lowpart_offset (outermode, innermode);
6453
6454   outer_offset = SUBREG_BYTE (subreg);
6455   middlemode = GET_MODE (SUBREG_REG (subreg));
6456
6457   /* If SUBREG is paradoxical then return the normal lowpart offset
6458      for OUTERMODE and INNERMODE.  Our caller has already checked
6459      that OUTERMODE fits in INNERMODE.  */
6460   if (outer_offset == 0
6461       && GET_MODE_SIZE (outermode) > GET_MODE_SIZE (middlemode))
6462     return subreg_lowpart_offset (outermode, innermode);
6463
6464   /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6465      plus the normal lowpart offset for MIDDLEMODE and INNERMODE.  */
6466   return outer_offset + subreg_lowpart_offset (middlemode, innermode);
6467 }
6468
6469 /* Assign hard reg targets for the pseudo-registers we must reload
6470    into hard regs for this insn.
6471    Also output the instructions to copy them in and out of the hard regs.
6472
6473    For machines with register classes, we are responsible for
6474    finding a reload reg in the proper class.  */
6475
6476 static void
6477 choose_reload_regs (struct insn_chain *chain)
6478 {
6479   rtx_insn *insn = chain->insn;
6480   int i, j;
6481   unsigned int max_group_size = 1;
6482   enum reg_class group_class = NO_REGS;
6483   int pass, win, inheritance;
6484
6485   rtx save_reload_reg_rtx[MAX_RELOADS];
6486
6487   /* In order to be certain of getting the registers we need,
6488      we must sort the reloads into order of increasing register class.
6489      Then our grabbing of reload registers will parallel the process
6490      that provided the reload registers.
6491
6492      Also note whether any of the reloads wants a consecutive group of regs.
6493      If so, record the maximum size of the group desired and what
6494      register class contains all the groups needed by this insn.  */
6495
6496   for (j = 0; j < n_reloads; j++)
6497     {
6498       reload_order[j] = j;
6499       if (rld[j].reg_rtx != NULL_RTX)
6500         {
6501           gcc_assert (REG_P (rld[j].reg_rtx)
6502                       && HARD_REGISTER_P (rld[j].reg_rtx));
6503           reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6504         }
6505       else
6506         reload_spill_index[j] = -1;
6507
6508       if (rld[j].nregs > 1)
6509         {
6510           max_group_size = MAX (rld[j].nregs, max_group_size);
6511           group_class
6512             = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6513         }
6514
6515       save_reload_reg_rtx[j] = rld[j].reg_rtx;
6516     }
6517
6518   if (n_reloads > 1)
6519     qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6520
6521   /* If -O, try first with inheritance, then turning it off.
6522      If not -O, don't do inheritance.
6523      Using inheritance when not optimizing leads to paradoxes
6524      with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6525      because one side of the comparison might be inherited.  */
6526   win = 0;
6527   for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6528     {
6529       choose_reload_regs_init (chain, save_reload_reg_rtx);
6530
6531       /* Process the reloads in order of preference just found.
6532          Beyond this point, subregs can be found in reload_reg_rtx.
6533
6534          This used to look for an existing reloaded home for all of the
6535          reloads, and only then perform any new reloads.  But that could lose
6536          if the reloads were done out of reg-class order because a later
6537          reload with a looser constraint might have an old home in a register
6538          needed by an earlier reload with a tighter constraint.
6539
6540          To solve this, we make two passes over the reloads, in the order
6541          described above.  In the first pass we try to inherit a reload
6542          from a previous insn.  If there is a later reload that needs a
6543          class that is a proper subset of the class being processed, we must
6544          also allocate a spill register during the first pass.
6545
6546          Then make a second pass over the reloads to allocate any reloads
6547          that haven't been given registers yet.  */
6548
6549       for (j = 0; j < n_reloads; j++)
6550         {
6551           int r = reload_order[j];
6552           rtx search_equiv = NULL_RTX;
6553
6554           /* Ignore reloads that got marked inoperative.  */
6555           if (rld[r].out == 0 && rld[r].in == 0
6556               && ! rld[r].secondary_p)
6557             continue;
6558
6559           /* If find_reloads chose to use reload_in or reload_out as a reload
6560              register, we don't need to chose one.  Otherwise, try even if it
6561              found one since we might save an insn if we find the value lying
6562              around.
6563              Try also when reload_in is a pseudo without a hard reg.  */
6564           if (rld[r].in != 0 && rld[r].reg_rtx != 0
6565               && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6566                   || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6567                       && !MEM_P (rld[r].in)
6568                       && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6569             continue;
6570
6571 #if 0 /* No longer needed for correct operation.
6572          It might give better code, or might not; worth an experiment?  */
6573           /* If this is an optional reload, we can't inherit from earlier insns
6574              until we are sure that any non-optional reloads have been allocated.
6575              The following code takes advantage of the fact that optional reloads
6576              are at the end of reload_order.  */
6577           if (rld[r].optional != 0)
6578             for (i = 0; i < j; i++)
6579               if ((rld[reload_order[i]].out != 0
6580                    || rld[reload_order[i]].in != 0
6581                    || rld[reload_order[i]].secondary_p)
6582                   && ! rld[reload_order[i]].optional
6583                   && rld[reload_order[i]].reg_rtx == 0)
6584                 allocate_reload_reg (chain, reload_order[i], 0);
6585 #endif
6586
6587           /* First see if this pseudo is already available as reloaded
6588              for a previous insn.  We cannot try to inherit for reloads
6589              that are smaller than the maximum number of registers needed
6590              for groups unless the register we would allocate cannot be used
6591              for the groups.
6592
6593              We could check here to see if this is a secondary reload for
6594              an object that is already in a register of the desired class.
6595              This would avoid the need for the secondary reload register.
6596              But this is complex because we can't easily determine what
6597              objects might want to be loaded via this reload.  So let a
6598              register be allocated here.  In `emit_reload_insns' we suppress
6599              one of the loads in the case described above.  */
6600
6601           if (inheritance)
6602             {
6603               int byte = 0;
6604               int regno = -1;
6605               machine_mode mode = VOIDmode;
6606               rtx subreg = NULL_RTX;
6607
6608               if (rld[r].in == 0)
6609                 ;
6610               else if (REG_P (rld[r].in))
6611                 {
6612                   regno = REGNO (rld[r].in);
6613                   mode = GET_MODE (rld[r].in);
6614                 }
6615               else if (REG_P (rld[r].in_reg))
6616                 {
6617                   regno = REGNO (rld[r].in_reg);
6618                   mode = GET_MODE (rld[r].in_reg);
6619                 }
6620               else if (GET_CODE (rld[r].in_reg) == SUBREG
6621                        && REG_P (SUBREG_REG (rld[r].in_reg)))
6622                 {
6623                   regno = REGNO (SUBREG_REG (rld[r].in_reg));
6624                   if (regno < FIRST_PSEUDO_REGISTER)
6625                     regno = subreg_regno (rld[r].in_reg);
6626                   else
6627                     {
6628                       subreg = rld[r].in_reg;
6629                       byte = SUBREG_BYTE (subreg);
6630                     }
6631                   mode = GET_MODE (rld[r].in_reg);
6632                 }
6633 #ifdef AUTO_INC_DEC
6634               else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6635                        && REG_P (XEXP (rld[r].in_reg, 0)))
6636                 {
6637                   regno = REGNO (XEXP (rld[r].in_reg, 0));
6638                   mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6639                   rld[r].out = rld[r].in;
6640                 }
6641 #endif
6642 #if 0
6643               /* This won't work, since REGNO can be a pseudo reg number.
6644                  Also, it takes much more hair to keep track of all the things
6645                  that can invalidate an inherited reload of part of a pseudoreg.  */
6646               else if (GET_CODE (rld[r].in) == SUBREG
6647                        && REG_P (SUBREG_REG (rld[r].in)))
6648                 regno = subreg_regno (rld[r].in);
6649 #endif
6650
6651               if (regno >= 0
6652                   && reg_last_reload_reg[regno] != 0
6653                   && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
6654                       >= GET_MODE_SIZE (mode) + byte)
6655 #ifdef CANNOT_CHANGE_MODE_CLASS
6656                   /* Verify that the register it's in can be used in
6657                      mode MODE.  */
6658                   && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6659                                                 GET_MODE (reg_last_reload_reg[regno]),
6660                                                 mode)
6661 #endif
6662                   )
6663                 {
6664                   enum reg_class rclass = rld[r].rclass, last_class;
6665                   rtx last_reg = reg_last_reload_reg[regno];
6666
6667                   i = REGNO (last_reg);
6668                   byte = compute_reload_subreg_offset (mode,
6669                                                        subreg,
6670                                                        GET_MODE (last_reg));
6671                   i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6672                   last_class = REGNO_REG_CLASS (i);
6673
6674                   if (reg_reloaded_contents[i] == regno
6675                       && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6676                       && HARD_REGNO_MODE_OK (i, rld[r].mode)
6677                       && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6678                           /* Even if we can't use this register as a reload
6679                              register, we might use it for reload_override_in,
6680                              if copying it to the desired class is cheap
6681                              enough.  */
6682                           || ((register_move_cost (mode, last_class, rclass)
6683                                < memory_move_cost (mode, rclass, true))
6684                               && (secondary_reload_class (1, rclass, mode,
6685                                                           last_reg)
6686                                   == NO_REGS)
6687 #ifdef SECONDARY_MEMORY_NEEDED
6688                               && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6689                                                             mode)
6690 #endif
6691                               ))
6692
6693                       && (rld[r].nregs == max_group_size
6694                           || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6695                                                   i))
6696                       && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6697                                            rld[r].when_needed, rld[r].in,
6698                                            const0_rtx, r, 1))
6699                     {
6700                       /* If a group is needed, verify that all the subsequent
6701                          registers still have their values intact.  */
6702                       int nr = hard_regno_nregs[i][rld[r].mode];
6703                       int k;
6704
6705                       for (k = 1; k < nr; k++)
6706                         if (reg_reloaded_contents[i + k] != regno
6707                             || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6708                           break;
6709
6710                       if (k == nr)
6711                         {
6712                           int i1;
6713                           int bad_for_class;
6714
6715                           last_reg = (GET_MODE (last_reg) == mode
6716                                       ? last_reg : gen_rtx_REG (mode, i));
6717
6718                           bad_for_class = 0;
6719                           for (k = 0; k < nr; k++)
6720                             bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6721                                                                   i+k);
6722
6723                           /* We found a register that contains the
6724                              value we need.  If this register is the
6725                              same as an `earlyclobber' operand of the
6726                              current insn, just mark it as a place to
6727                              reload from since we can't use it as the
6728                              reload register itself.  */
6729
6730                           for (i1 = 0; i1 < n_earlyclobbers; i1++)
6731                             if (reg_overlap_mentioned_for_reload_p
6732                                 (reg_last_reload_reg[regno],
6733                                  reload_earlyclobbers[i1]))
6734                               break;
6735
6736                           if (i1 != n_earlyclobbers
6737                               || ! (free_for_value_p (i, rld[r].mode,
6738                                                       rld[r].opnum,
6739                                                       rld[r].when_needed, rld[r].in,
6740                                                       rld[r].out, r, 1))
6741                               /* Don't use it if we'd clobber a pseudo reg.  */
6742                               || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6743                                   && rld[r].out
6744                                   && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6745                               /* Don't clobber the frame pointer.  */
6746                               || (i == HARD_FRAME_POINTER_REGNUM
6747                                   && frame_pointer_needed
6748                                   && rld[r].out)
6749                               /* Don't really use the inherited spill reg
6750                                  if we need it wider than we've got it.  */
6751                               || (GET_MODE_SIZE (rld[r].mode)
6752                                   > GET_MODE_SIZE (mode))
6753                               || bad_for_class
6754
6755                               /* If find_reloads chose reload_out as reload
6756                                  register, stay with it - that leaves the
6757                                  inherited register for subsequent reloads.  */
6758                               || (rld[r].out && rld[r].reg_rtx
6759                                   && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6760                             {
6761                               if (! rld[r].optional)
6762                                 {
6763                                   reload_override_in[r] = last_reg;
6764                                   reload_inheritance_insn[r]
6765                                     = reg_reloaded_insn[i];
6766                                 }
6767                             }
6768                           else
6769                             {
6770                               int k;
6771                               /* We can use this as a reload reg.  */
6772                               /* Mark the register as in use for this part of
6773                                  the insn.  */
6774                               mark_reload_reg_in_use (i,
6775                                                       rld[r].opnum,
6776                                                       rld[r].when_needed,
6777                                                       rld[r].mode);
6778                               rld[r].reg_rtx = last_reg;
6779                               reload_inherited[r] = 1;
6780                               reload_inheritance_insn[r]
6781                                 = reg_reloaded_insn[i];
6782                               reload_spill_index[r] = i;
6783                               for (k = 0; k < nr; k++)
6784                                 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6785                                                   i + k);
6786                             }
6787                         }
6788                     }
6789                 }
6790             }
6791
6792           /* Here's another way to see if the value is already lying around.  */
6793           if (inheritance
6794               && rld[r].in != 0
6795               && ! reload_inherited[r]
6796               && rld[r].out == 0
6797               && (CONSTANT_P (rld[r].in)
6798                   || GET_CODE (rld[r].in) == PLUS
6799                   || REG_P (rld[r].in)
6800                   || MEM_P (rld[r].in))
6801               && (rld[r].nregs == max_group_size
6802                   || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6803             search_equiv = rld[r].in;
6804
6805           if (search_equiv)
6806             {
6807               rtx equiv
6808                 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6809                                   -1, NULL, 0, rld[r].mode);
6810               int regno = 0;
6811
6812               if (equiv != 0)
6813                 {
6814                   if (REG_P (equiv))
6815                     regno = REGNO (equiv);
6816                   else
6817                     {
6818                       /* This must be a SUBREG of a hard register.
6819                          Make a new REG since this might be used in an
6820                          address and not all machines support SUBREGs
6821                          there.  */
6822                       gcc_assert (GET_CODE (equiv) == SUBREG);
6823                       regno = subreg_regno (equiv);
6824                       equiv = gen_rtx_REG (rld[r].mode, regno);
6825                       /* If we choose EQUIV as the reload register, but the
6826                          loop below decides to cancel the inheritance, we'll
6827                          end up reloading EQUIV in rld[r].mode, not the mode
6828                          it had originally.  That isn't safe when EQUIV isn't
6829                          available as a spill register since its value might
6830                          still be live at this point.  */
6831                       for (i = regno; i < regno + (int) rld[r].nregs; i++)
6832                         if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6833                           equiv = 0;
6834                     }
6835                 }
6836
6837               /* If we found a spill reg, reject it unless it is free
6838                  and of the desired class.  */
6839               if (equiv != 0)
6840                 {
6841                   int regs_used = 0;
6842                   int bad_for_class = 0;
6843                   int max_regno = regno + rld[r].nregs;
6844
6845                   for (i = regno; i < max_regno; i++)
6846                     {
6847                       regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6848                                                       i);
6849                       bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6850                                                            i);
6851                     }
6852
6853                   if ((regs_used
6854                        && ! free_for_value_p (regno, rld[r].mode,
6855                                               rld[r].opnum, rld[r].when_needed,
6856                                               rld[r].in, rld[r].out, r, 1))
6857                       || bad_for_class)
6858                     equiv = 0;
6859                 }
6860
6861               if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6862                 equiv = 0;
6863
6864               /* We found a register that contains the value we need.
6865                  If this register is the same as an `earlyclobber' operand
6866                  of the current insn, just mark it as a place to reload from
6867                  since we can't use it as the reload register itself.  */
6868
6869               if (equiv != 0)
6870                 for (i = 0; i < n_earlyclobbers; i++)
6871                   if (reg_overlap_mentioned_for_reload_p (equiv,
6872                                                           reload_earlyclobbers[i]))
6873                     {
6874                       if (! rld[r].optional)
6875                         reload_override_in[r] = equiv;
6876                       equiv = 0;
6877                       break;
6878                     }
6879
6880               /* If the equiv register we have found is explicitly clobbered
6881                  in the current insn, it depends on the reload type if we
6882                  can use it, use it for reload_override_in, or not at all.
6883                  In particular, we then can't use EQUIV for a
6884                  RELOAD_FOR_OUTPUT_ADDRESS reload.  */
6885
6886               if (equiv != 0)
6887                 {
6888                   if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6889                     switch (rld[r].when_needed)
6890                       {
6891                       case RELOAD_FOR_OTHER_ADDRESS:
6892                       case RELOAD_FOR_INPADDR_ADDRESS:
6893                       case RELOAD_FOR_INPUT_ADDRESS:
6894                       case RELOAD_FOR_OPADDR_ADDR:
6895                         break;
6896                       case RELOAD_OTHER:
6897                       case RELOAD_FOR_INPUT:
6898                       case RELOAD_FOR_OPERAND_ADDRESS:
6899                         if (! rld[r].optional)
6900                           reload_override_in[r] = equiv;
6901                         /* Fall through.  */
6902                       default:
6903                         equiv = 0;
6904                         break;
6905                       }
6906                   else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6907                     switch (rld[r].when_needed)
6908                       {
6909                       case RELOAD_FOR_OTHER_ADDRESS:
6910                       case RELOAD_FOR_INPADDR_ADDRESS:
6911                       case RELOAD_FOR_INPUT_ADDRESS:
6912                       case RELOAD_FOR_OPADDR_ADDR:
6913                       case RELOAD_FOR_OPERAND_ADDRESS:
6914                       case RELOAD_FOR_INPUT:
6915                         break;
6916                       case RELOAD_OTHER:
6917                         if (! rld[r].optional)
6918                           reload_override_in[r] = equiv;
6919                         /* Fall through.  */
6920                       default:
6921                         equiv = 0;
6922                         break;
6923                       }
6924                 }
6925
6926               /* If we found an equivalent reg, say no code need be generated
6927                  to load it, and use it as our reload reg.  */
6928               if (equiv != 0
6929                   && (regno != HARD_FRAME_POINTER_REGNUM
6930                       || !frame_pointer_needed))
6931                 {
6932                   int nr = hard_regno_nregs[regno][rld[r].mode];
6933                   int k;
6934                   rld[r].reg_rtx = equiv;
6935                   reload_spill_index[r] = regno;
6936                   reload_inherited[r] = 1;
6937
6938                   /* If reg_reloaded_valid is not set for this register,
6939                      there might be a stale spill_reg_store lying around.
6940                      We must clear it, since otherwise emit_reload_insns
6941                      might delete the store.  */
6942                   if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6943                     spill_reg_store[regno] = NULL;
6944                   /* If any of the hard registers in EQUIV are spill
6945                      registers, mark them as in use for this insn.  */
6946                   for (k = 0; k < nr; k++)
6947                     {
6948                       i = spill_reg_order[regno + k];
6949                       if (i >= 0)
6950                         {
6951                           mark_reload_reg_in_use (regno, rld[r].opnum,
6952                                                   rld[r].when_needed,
6953                                                   rld[r].mode);
6954                           SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6955                                             regno + k);
6956                         }
6957                     }
6958                 }
6959             }
6960
6961           /* If we found a register to use already, or if this is an optional
6962              reload, we are done.  */
6963           if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6964             continue;
6965
6966 #if 0
6967           /* No longer needed for correct operation.  Might or might
6968              not give better code on the average.  Want to experiment?  */
6969
6970           /* See if there is a later reload that has a class different from our
6971              class that intersects our class or that requires less register
6972              than our reload.  If so, we must allocate a register to this
6973              reload now, since that reload might inherit a previous reload
6974              and take the only available register in our class.  Don't do this
6975              for optional reloads since they will force all previous reloads
6976              to be allocated.  Also don't do this for reloads that have been
6977              turned off.  */
6978
6979           for (i = j + 1; i < n_reloads; i++)
6980             {
6981               int s = reload_order[i];
6982
6983               if ((rld[s].in == 0 && rld[s].out == 0
6984                    && ! rld[s].secondary_p)
6985                   || rld[s].optional)
6986                 continue;
6987
6988               if ((rld[s].rclass != rld[r].rclass
6989                    && reg_classes_intersect_p (rld[r].rclass,
6990                                                rld[s].rclass))
6991                   || rld[s].nregs < rld[r].nregs)
6992                 break;
6993             }
6994
6995           if (i == n_reloads)
6996             continue;
6997
6998           allocate_reload_reg (chain, r, j == n_reloads - 1);
6999 #endif
7000         }
7001
7002       /* Now allocate reload registers for anything non-optional that
7003          didn't get one yet.  */
7004       for (j = 0; j < n_reloads; j++)
7005         {
7006           int r = reload_order[j];
7007
7008           /* Ignore reloads that got marked inoperative.  */
7009           if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
7010             continue;
7011
7012           /* Skip reloads that already have a register allocated or are
7013              optional.  */
7014           if (rld[r].reg_rtx != 0 || rld[r].optional)
7015             continue;
7016
7017           if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
7018             break;
7019         }
7020
7021       /* If that loop got all the way, we have won.  */
7022       if (j == n_reloads)
7023         {
7024           win = 1;
7025           break;
7026         }
7027
7028       /* Loop around and try without any inheritance.  */
7029     }
7030
7031   if (! win)
7032     {
7033       /* First undo everything done by the failed attempt
7034          to allocate with inheritance.  */
7035       choose_reload_regs_init (chain, save_reload_reg_rtx);
7036
7037       /* Some sanity tests to verify that the reloads found in the first
7038          pass are identical to the ones we have now.  */
7039       gcc_assert (chain->n_reloads == n_reloads);
7040
7041       for (i = 0; i < n_reloads; i++)
7042         {
7043           if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
7044             continue;
7045           gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
7046           for (j = 0; j < n_spills; j++)
7047             if (spill_regs[j] == chain->rld[i].regno)
7048               if (! set_reload_reg (j, i))
7049                 failed_reload (chain->insn, i);
7050         }
7051     }
7052
7053   /* If we thought we could inherit a reload, because it seemed that
7054      nothing else wanted the same reload register earlier in the insn,
7055      verify that assumption, now that all reloads have been assigned.
7056      Likewise for reloads where reload_override_in has been set.  */
7057
7058   /* If doing expensive optimizations, do one preliminary pass that doesn't
7059      cancel any inheritance, but removes reloads that have been needed only
7060      for reloads that we know can be inherited.  */
7061   for (pass = flag_expensive_optimizations; pass >= 0; pass--)
7062     {
7063       for (j = 0; j < n_reloads; j++)
7064         {
7065           int r = reload_order[j];
7066           rtx check_reg;
7067 #ifdef SECONDARY_MEMORY_NEEDED
7068           rtx tem;
7069 #endif
7070           if (reload_inherited[r] && rld[r].reg_rtx)
7071             check_reg = rld[r].reg_rtx;
7072           else if (reload_override_in[r]
7073                    && (REG_P (reload_override_in[r])
7074                        || GET_CODE (reload_override_in[r]) == SUBREG))
7075             check_reg = reload_override_in[r];
7076           else
7077             continue;
7078           if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
7079                                   rld[r].opnum, rld[r].when_needed, rld[r].in,
7080                                   (reload_inherited[r]
7081                                    ? rld[r].out : const0_rtx),
7082                                   r, 1))
7083             {
7084               if (pass)
7085                 continue;
7086               reload_inherited[r] = 0;
7087               reload_override_in[r] = 0;
7088             }
7089           /* If we can inherit a RELOAD_FOR_INPUT, or can use a
7090              reload_override_in, then we do not need its related
7091              RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
7092              likewise for other reload types.
7093              We handle this by removing a reload when its only replacement
7094              is mentioned in reload_in of the reload we are going to inherit.
7095              A special case are auto_inc expressions; even if the input is
7096              inherited, we still need the address for the output.  We can
7097              recognize them because they have RELOAD_OUT set to RELOAD_IN.
7098              If we succeeded removing some reload and we are doing a preliminary
7099              pass just to remove such reloads, make another pass, since the
7100              removal of one reload might allow us to inherit another one.  */
7101           else if (rld[r].in
7102                    && rld[r].out != rld[r].in
7103                    && remove_address_replacements (rld[r].in))
7104             {
7105               if (pass)
7106                 pass = 2;
7107             }
7108 #ifdef SECONDARY_MEMORY_NEEDED
7109           /* If we needed a memory location for the reload, we also have to
7110              remove its related reloads.  */
7111           else if (rld[r].in
7112                    && rld[r].out != rld[r].in
7113                    && (tem = replaced_subreg (rld[r].in), REG_P (tem))
7114                    && REGNO (tem) < FIRST_PSEUDO_REGISTER
7115                    && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem)),
7116                                                rld[r].rclass, rld[r].inmode)
7117                    && remove_address_replacements
7118                       (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum,
7119                                           rld[r].when_needed)))
7120             {
7121               if (pass)
7122                 pass = 2;
7123             }
7124 #endif
7125         }
7126     }
7127
7128   /* Now that reload_override_in is known valid,
7129      actually override reload_in.  */
7130   for (j = 0; j < n_reloads; j++)
7131     if (reload_override_in[j])
7132       rld[j].in = reload_override_in[j];
7133
7134   /* If this reload won't be done because it has been canceled or is
7135      optional and not inherited, clear reload_reg_rtx so other
7136      routines (such as subst_reloads) don't get confused.  */
7137   for (j = 0; j < n_reloads; j++)
7138     if (rld[j].reg_rtx != 0
7139         && ((rld[j].optional && ! reload_inherited[j])
7140             || (rld[j].in == 0 && rld[j].out == 0
7141                 && ! rld[j].secondary_p)))
7142       {
7143         int regno = true_regnum (rld[j].reg_rtx);
7144
7145         if (spill_reg_order[regno] >= 0)
7146           clear_reload_reg_in_use (regno, rld[j].opnum,
7147                                    rld[j].when_needed, rld[j].mode);
7148         rld[j].reg_rtx = 0;
7149         reload_spill_index[j] = -1;
7150       }
7151
7152   /* Record which pseudos and which spill regs have output reloads.  */
7153   for (j = 0; j < n_reloads; j++)
7154     {
7155       int r = reload_order[j];
7156
7157       i = reload_spill_index[r];
7158
7159       /* I is nonneg if this reload uses a register.
7160          If rld[r].reg_rtx is 0, this is an optional reload
7161          that we opted to ignore.  */
7162       if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
7163           && rld[r].reg_rtx != 0)
7164         {
7165           int nregno = REGNO (rld[r].out_reg);
7166           int nr = 1;
7167
7168           if (nregno < FIRST_PSEUDO_REGISTER)
7169             nr = hard_regno_nregs[nregno][rld[r].mode];
7170
7171           while (--nr >= 0)
7172             SET_REGNO_REG_SET (&reg_has_output_reload,
7173                                nregno + nr);
7174
7175           if (i >= 0)
7176             add_to_hard_reg_set (&reg_is_output_reload, rld[r].mode, i);
7177
7178           gcc_assert (rld[r].when_needed == RELOAD_OTHER
7179                       || rld[r].when_needed == RELOAD_FOR_OUTPUT
7180                       || rld[r].when_needed == RELOAD_FOR_INSN);
7181         }
7182     }
7183 }
7184
7185 /* Deallocate the reload register for reload R.  This is called from
7186    remove_address_replacements.  */
7187
7188 void
7189 deallocate_reload_reg (int r)
7190 {
7191   int regno;
7192
7193   if (! rld[r].reg_rtx)
7194     return;
7195   regno = true_regnum (rld[r].reg_rtx);
7196   rld[r].reg_rtx = 0;
7197   if (spill_reg_order[regno] >= 0)
7198     clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7199                              rld[r].mode);
7200   reload_spill_index[r] = -1;
7201 }
7202 \f
7203 /* These arrays are filled by emit_reload_insns and its subroutines.  */
7204 static rtx_insn *input_reload_insns[MAX_RECOG_OPERANDS];
7205 static rtx_insn *other_input_address_reload_insns = 0;
7206 static rtx_insn *other_input_reload_insns = 0;
7207 static rtx_insn *input_address_reload_insns[MAX_RECOG_OPERANDS];
7208 static rtx_insn *inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7209 static rtx_insn *output_reload_insns[MAX_RECOG_OPERANDS];
7210 static rtx_insn *output_address_reload_insns[MAX_RECOG_OPERANDS];
7211 static rtx_insn *outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7212 static rtx_insn *operand_reload_insns = 0;
7213 static rtx_insn *other_operand_reload_insns = 0;
7214 static rtx_insn *other_output_reload_insns[MAX_RECOG_OPERANDS];
7215
7216 /* Values to be put in spill_reg_store are put here first.  Instructions
7217    must only be placed here if the associated reload register reaches
7218    the end of the instruction's reload sequence.  */
7219 static rtx_insn *new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7220 static HARD_REG_SET reg_reloaded_died;
7221
7222 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7223    of class NEW_CLASS with mode NEW_MODE.  Or alternatively, if alt_reload_reg
7224    is nonzero, if that is suitable.  On success, change *RELOAD_REG to the
7225    adjusted register, and return true.  Otherwise, return false.  */
7226 static bool
7227 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7228                             enum reg_class new_class,
7229                             machine_mode new_mode)
7230
7231 {
7232   rtx reg;
7233
7234   for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7235     {
7236       unsigned regno = REGNO (reg);
7237
7238       if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7239         continue;
7240       if (GET_MODE (reg) != new_mode)
7241         {
7242           if (!HARD_REGNO_MODE_OK (regno, new_mode))
7243             continue;
7244           if (hard_regno_nregs[regno][new_mode]
7245               > hard_regno_nregs[regno][GET_MODE (reg)])
7246             continue;
7247           reg = reload_adjust_reg_for_mode (reg, new_mode);
7248         }
7249       *reload_reg = reg;
7250       return true;
7251     }
7252   return false;
7253 }
7254
7255 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7256    pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7257    nonzero, if that is suitable.  On success, change *RELOAD_REG to the
7258    adjusted register, and return true.  Otherwise, return false.  */
7259 static bool
7260 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7261                              enum insn_code icode)
7262
7263 {
7264   enum reg_class new_class = scratch_reload_class (icode);
7265   machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7266
7267   return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7268                                      new_class, new_mode);
7269 }
7270
7271 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7272    has the number J.  OLD contains the value to be used as input.  */
7273
7274 static void
7275 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7276                          rtx old, int j)
7277 {
7278   rtx_insn *insn = chain->insn;
7279   rtx reloadreg;
7280   rtx oldequiv_reg = 0;
7281   rtx oldequiv = 0;
7282   int special = 0;
7283   machine_mode mode;
7284   rtx_insn **where;
7285
7286   /* delete_output_reload is only invoked properly if old contains
7287      the original pseudo register.  Since this is replaced with a
7288      hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7289      find the pseudo in RELOAD_IN_REG.  This is also used to
7290      determine whether a secondary reload is needed.  */
7291   if (reload_override_in[j]
7292       && (REG_P (rl->in_reg)
7293           || (GET_CODE (rl->in_reg) == SUBREG
7294               && REG_P (SUBREG_REG (rl->in_reg)))))
7295     {
7296       oldequiv = old;
7297       old = rl->in_reg;
7298     }
7299   if (oldequiv == 0)
7300     oldequiv = old;
7301   else if (REG_P (oldequiv))
7302     oldequiv_reg = oldequiv;
7303   else if (GET_CODE (oldequiv) == SUBREG)
7304     oldequiv_reg = SUBREG_REG (oldequiv);
7305
7306   reloadreg = reload_reg_rtx_for_input[j];
7307   mode = GET_MODE (reloadreg);
7308
7309   /* If we are reloading from a register that was recently stored in
7310      with an output-reload, see if we can prove there was
7311      actually no need to store the old value in it.  */
7312
7313   if (optimize && REG_P (oldequiv)
7314       && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7315       && spill_reg_store[REGNO (oldequiv)]
7316       && REG_P (old)
7317       && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7318           || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7319                           rl->out_reg)))
7320     delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7321
7322   /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7323      OLDEQUIV.  */
7324
7325   while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7326     oldequiv = SUBREG_REG (oldequiv);
7327   if (GET_MODE (oldequiv) != VOIDmode
7328       && mode != GET_MODE (oldequiv))
7329     oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7330
7331   /* Switch to the right place to emit the reload insns.  */
7332   switch (rl->when_needed)
7333     {
7334     case RELOAD_OTHER:
7335       where = &other_input_reload_insns;
7336       break;
7337     case RELOAD_FOR_INPUT:
7338       where = &input_reload_insns[rl->opnum];
7339       break;
7340     case RELOAD_FOR_INPUT_ADDRESS:
7341       where = &input_address_reload_insns[rl->opnum];
7342       break;
7343     case RELOAD_FOR_INPADDR_ADDRESS:
7344       where = &inpaddr_address_reload_insns[rl->opnum];
7345       break;
7346     case RELOAD_FOR_OUTPUT_ADDRESS:
7347       where = &output_address_reload_insns[rl->opnum];
7348       break;
7349     case RELOAD_FOR_OUTADDR_ADDRESS:
7350       where = &outaddr_address_reload_insns[rl->opnum];
7351       break;
7352     case RELOAD_FOR_OPERAND_ADDRESS:
7353       where = &operand_reload_insns;
7354       break;
7355     case RELOAD_FOR_OPADDR_ADDR:
7356       where = &other_operand_reload_insns;
7357       break;
7358     case RELOAD_FOR_OTHER_ADDRESS:
7359       where = &other_input_address_reload_insns;
7360       break;
7361     default:
7362       gcc_unreachable ();
7363     }
7364
7365   push_to_sequence (*where);
7366
7367   /* Auto-increment addresses must be reloaded in a special way.  */
7368   if (rl->out && ! rl->out_reg)
7369     {
7370       /* We are not going to bother supporting the case where a
7371          incremented register can't be copied directly from
7372          OLDEQUIV since this seems highly unlikely.  */
7373       gcc_assert (rl->secondary_in_reload < 0);
7374
7375       if (reload_inherited[j])
7376         oldequiv = reloadreg;
7377
7378       old = XEXP (rl->in_reg, 0);
7379
7380       /* Prevent normal processing of this reload.  */
7381       special = 1;
7382       /* Output a special code sequence for this case.  */
7383       inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7384     }
7385
7386   /* If we are reloading a pseudo-register that was set by the previous
7387      insn, see if we can get rid of that pseudo-register entirely
7388      by redirecting the previous insn into our reload register.  */
7389
7390   else if (optimize && REG_P (old)
7391            && REGNO (old) >= FIRST_PSEUDO_REGISTER
7392            && dead_or_set_p (insn, old)
7393            /* This is unsafe if some other reload
7394               uses the same reg first.  */
7395            && ! conflicts_with_override (reloadreg)
7396            && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7397                                 rl->when_needed, old, rl->out, j, 0))
7398     {
7399       rtx_insn *temp = PREV_INSN (insn);
7400       while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7401         temp = PREV_INSN (temp);
7402       if (temp
7403           && NONJUMP_INSN_P (temp)
7404           && GET_CODE (PATTERN (temp)) == SET
7405           && SET_DEST (PATTERN (temp)) == old
7406           /* Make sure we can access insn_operand_constraint.  */
7407           && asm_noperands (PATTERN (temp)) < 0
7408           /* This is unsafe if operand occurs more than once in current
7409              insn.  Perhaps some occurrences aren't reloaded.  */
7410           && count_occurrences (PATTERN (insn), old, 0) == 1)
7411         {
7412           rtx old = SET_DEST (PATTERN (temp));
7413           /* Store into the reload register instead of the pseudo.  */
7414           SET_DEST (PATTERN (temp)) = reloadreg;
7415
7416           /* Verify that resulting insn is valid.
7417
7418              Note that we have replaced the destination of TEMP with
7419              RELOADREG.  If TEMP references RELOADREG within an
7420              autoincrement addressing mode, then the resulting insn
7421              is ill-formed and we must reject this optimization.  */
7422           extract_insn (temp);
7423           if (constrain_operands (1, get_enabled_alternatives (temp))
7424 #ifdef AUTO_INC_DEC
7425               && ! find_reg_note (temp, REG_INC, reloadreg)
7426 #endif
7427               )
7428             {
7429               /* If the previous insn is an output reload, the source is
7430                  a reload register, and its spill_reg_store entry will
7431                  contain the previous destination.  This is now
7432                  invalid.  */
7433               if (REG_P (SET_SRC (PATTERN (temp)))
7434                   && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7435                 {
7436                   spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7437                   spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7438                 }
7439
7440               /* If these are the only uses of the pseudo reg,
7441                  pretend for GDB it lives in the reload reg we used.  */
7442               if (REG_N_DEATHS (REGNO (old)) == 1
7443                   && REG_N_SETS (REGNO (old)) == 1)
7444                 {
7445                   reg_renumber[REGNO (old)] = REGNO (reloadreg);
7446                   if (ira_conflicts_p)
7447                     /* Inform IRA about the change.  */
7448                     ira_mark_allocation_change (REGNO (old));
7449                   alter_reg (REGNO (old), -1, false);
7450                 }
7451               special = 1;
7452
7453               /* Adjust any debug insns between temp and insn.  */
7454               while ((temp = NEXT_INSN (temp)) != insn)
7455                 if (DEBUG_INSN_P (temp))
7456                   replace_rtx (PATTERN (temp), old, reloadreg);
7457                 else
7458                   gcc_assert (NOTE_P (temp));
7459             }
7460           else
7461             {
7462               SET_DEST (PATTERN (temp)) = old;
7463             }
7464         }
7465     }
7466
7467   /* We can't do that, so output an insn to load RELOADREG.  */
7468
7469   /* If we have a secondary reload, pick up the secondary register
7470      and icode, if any.  If OLDEQUIV and OLD are different or
7471      if this is an in-out reload, recompute whether or not we
7472      still need a secondary register and what the icode should
7473      be.  If we still need a secondary register and the class or
7474      icode is different, go back to reloading from OLD if using
7475      OLDEQUIV means that we got the wrong type of register.  We
7476      cannot have different class or icode due to an in-out reload
7477      because we don't make such reloads when both the input and
7478      output need secondary reload registers.  */
7479
7480   if (! special && rl->secondary_in_reload >= 0)
7481     {
7482       rtx second_reload_reg = 0;
7483       rtx third_reload_reg = 0;
7484       int secondary_reload = rl->secondary_in_reload;
7485       rtx real_oldequiv = oldequiv;
7486       rtx real_old = old;
7487       rtx tmp;
7488       enum insn_code icode;
7489       enum insn_code tertiary_icode = CODE_FOR_nothing;
7490
7491       /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7492          and similarly for OLD.
7493          See comments in get_secondary_reload in reload.c.  */
7494       /* If it is a pseudo that cannot be replaced with its
7495          equivalent MEM, we must fall back to reload_in, which
7496          will have all the necessary substitutions registered.
7497          Likewise for a pseudo that can't be replaced with its
7498          equivalent constant.
7499
7500          Take extra care for subregs of such pseudos.  Note that
7501          we cannot use reg_equiv_mem in this case because it is
7502          not in the right mode.  */
7503
7504       tmp = oldequiv;
7505       if (GET_CODE (tmp) == SUBREG)
7506         tmp = SUBREG_REG (tmp);
7507       if (REG_P (tmp)
7508           && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7509           && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7510               || reg_equiv_constant (REGNO (tmp)) != 0))
7511         {
7512           if (! reg_equiv_mem (REGNO (tmp))
7513               || num_not_at_initial_offset
7514               || GET_CODE (oldequiv) == SUBREG)
7515             real_oldequiv = rl->in;
7516           else
7517             real_oldequiv = reg_equiv_mem (REGNO (tmp));
7518         }
7519
7520       tmp = old;
7521       if (GET_CODE (tmp) == SUBREG)
7522         tmp = SUBREG_REG (tmp);
7523       if (REG_P (tmp)
7524           && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7525           && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7526               || reg_equiv_constant (REGNO (tmp)) != 0))
7527         {
7528           if (! reg_equiv_mem (REGNO (tmp))
7529               || num_not_at_initial_offset
7530               || GET_CODE (old) == SUBREG)
7531             real_old = rl->in;
7532           else
7533             real_old = reg_equiv_mem (REGNO (tmp));
7534         }
7535
7536       second_reload_reg = rld[secondary_reload].reg_rtx;
7537       if (rld[secondary_reload].secondary_in_reload >= 0)
7538         {
7539           int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7540
7541           third_reload_reg = rld[tertiary_reload].reg_rtx;
7542           tertiary_icode = rld[secondary_reload].secondary_in_icode;
7543           /* We'd have to add more code for quartary reloads.  */
7544           gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7545         }
7546       icode = rl->secondary_in_icode;
7547
7548       if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7549           || (rl->in != 0 && rl->out != 0))
7550         {
7551           secondary_reload_info sri, sri2;
7552           enum reg_class new_class, new_t_class;
7553
7554           sri.icode = CODE_FOR_nothing;
7555           sri.prev_sri = NULL;
7556           new_class
7557             = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7558                                                          rl->rclass, mode,
7559                                                          &sri);
7560
7561           if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7562             second_reload_reg = 0;
7563           else if (new_class == NO_REGS)
7564             {
7565               if (reload_adjust_reg_for_icode (&second_reload_reg,
7566                                                third_reload_reg,
7567                                                (enum insn_code) sri.icode))
7568                 {
7569                   icode = (enum insn_code) sri.icode;
7570                   third_reload_reg = 0;
7571                 }
7572               else
7573                 {
7574                   oldequiv = old;
7575                   real_oldequiv = real_old;
7576                 }
7577             }
7578           else if (sri.icode != CODE_FOR_nothing)
7579             /* We currently lack a way to express this in reloads.  */
7580             gcc_unreachable ();
7581           else
7582             {
7583               sri2.icode = CODE_FOR_nothing;
7584               sri2.prev_sri = &sri;
7585               new_t_class
7586                 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7587                                                              new_class, mode,
7588                                                              &sri);
7589               if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7590                 {
7591                   if (reload_adjust_reg_for_temp (&second_reload_reg,
7592                                                   third_reload_reg,
7593                                                   new_class, mode))
7594                     {
7595                       third_reload_reg = 0;
7596                       tertiary_icode = (enum insn_code) sri2.icode;
7597                     }
7598                   else
7599                     {
7600                       oldequiv = old;
7601                       real_oldequiv = real_old;
7602                     }
7603                 }
7604               else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7605                 {
7606                   rtx intermediate = second_reload_reg;
7607
7608                   if (reload_adjust_reg_for_temp (&intermediate, NULL,
7609                                                   new_class, mode)
7610                       && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7611                                                       ((enum insn_code)
7612                                                        sri2.icode)))
7613                     {
7614                       second_reload_reg = intermediate;
7615                       tertiary_icode = (enum insn_code) sri2.icode;
7616                     }
7617                   else
7618                     {
7619                       oldequiv = old;
7620                       real_oldequiv = real_old;
7621                     }
7622                 }
7623               else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7624                 {
7625                   rtx intermediate = second_reload_reg;
7626
7627                   if (reload_adjust_reg_for_temp (&intermediate, NULL,
7628                                                   new_class, mode)
7629                       && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7630                                                       new_t_class, mode))
7631                     {
7632                       second_reload_reg = intermediate;
7633                       tertiary_icode = (enum insn_code) sri2.icode;
7634                     }
7635                   else
7636                     {
7637                       oldequiv = old;
7638                       real_oldequiv = real_old;
7639                     }
7640                 }
7641               else
7642                 {
7643                   /* This could be handled more intelligently too.  */
7644                   oldequiv = old;
7645                   real_oldequiv = real_old;
7646                 }
7647             }
7648         }
7649
7650       /* If we still need a secondary reload register, check
7651          to see if it is being used as a scratch or intermediate
7652          register and generate code appropriately.  If we need
7653          a scratch register, use REAL_OLDEQUIV since the form of
7654          the insn may depend on the actual address if it is
7655          a MEM.  */
7656
7657       if (second_reload_reg)
7658         {
7659           if (icode != CODE_FOR_nothing)
7660             {
7661               /* We'd have to add extra code to handle this case.  */
7662               gcc_assert (!third_reload_reg);
7663
7664               emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7665                                           second_reload_reg));
7666               special = 1;
7667             }
7668           else
7669             {
7670               /* See if we need a scratch register to load the
7671                  intermediate register (a tertiary reload).  */
7672               if (tertiary_icode != CODE_FOR_nothing)
7673                 {
7674                   emit_insn ((GEN_FCN (tertiary_icode)
7675                               (second_reload_reg, real_oldequiv,
7676                                third_reload_reg)));
7677                 }
7678               else if (third_reload_reg)
7679                 {
7680                   gen_reload (third_reload_reg, real_oldequiv,
7681                               rl->opnum,
7682                               rl->when_needed);
7683                   gen_reload (second_reload_reg, third_reload_reg,
7684                               rl->opnum,
7685                               rl->when_needed);
7686                 }
7687               else
7688                 gen_reload (second_reload_reg, real_oldequiv,
7689                             rl->opnum,
7690                             rl->when_needed);
7691
7692               oldequiv = second_reload_reg;
7693             }
7694         }
7695     }
7696
7697   if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7698     {
7699       rtx real_oldequiv = oldequiv;
7700
7701       if ((REG_P (oldequiv)
7702            && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7703            && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7704                || reg_equiv_constant (REGNO (oldequiv)) != 0))
7705           || (GET_CODE (oldequiv) == SUBREG
7706               && REG_P (SUBREG_REG (oldequiv))
7707               && (REGNO (SUBREG_REG (oldequiv))
7708                   >= FIRST_PSEUDO_REGISTER)
7709               && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7710                   || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7711           || (CONSTANT_P (oldequiv)
7712               && (targetm.preferred_reload_class (oldequiv,
7713                                                   REGNO_REG_CLASS (REGNO (reloadreg)))
7714                   == NO_REGS)))
7715         real_oldequiv = rl->in;
7716       gen_reload (reloadreg, real_oldequiv, rl->opnum,
7717                   rl->when_needed);
7718     }
7719
7720   if (cfun->can_throw_non_call_exceptions)
7721     copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7722
7723   /* End this sequence.  */
7724   *where = get_insns ();
7725   end_sequence ();
7726
7727   /* Update reload_override_in so that delete_address_reloads_1
7728      can see the actual register usage.  */
7729   if (oldequiv_reg)
7730     reload_override_in[j] = oldequiv;
7731 }
7732
7733 /* Generate insns to for the output reload RL, which is for the insn described
7734    by CHAIN and has the number J.  */
7735 static void
7736 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7737                           int j)
7738 {
7739   rtx reloadreg;
7740   rtx_insn *insn = chain->insn;
7741   int special = 0;
7742   rtx old = rl->out;
7743   machine_mode mode;
7744   rtx_insn *p;
7745   rtx rl_reg_rtx;
7746
7747   if (rl->when_needed == RELOAD_OTHER)
7748     start_sequence ();
7749   else
7750     push_to_sequence (output_reload_insns[rl->opnum]);
7751
7752   rl_reg_rtx = reload_reg_rtx_for_output[j];
7753   mode = GET_MODE (rl_reg_rtx);
7754
7755   reloadreg = rl_reg_rtx;
7756
7757   /* If we need two reload regs, set RELOADREG to the intermediate
7758      one, since it will be stored into OLD.  We might need a secondary
7759      register only for an input reload, so check again here.  */
7760
7761   if (rl->secondary_out_reload >= 0)
7762     {
7763       rtx real_old = old;
7764       int secondary_reload = rl->secondary_out_reload;
7765       int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7766
7767       if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7768           && reg_equiv_mem (REGNO (old)) != 0)
7769         real_old = reg_equiv_mem (REGNO (old));
7770
7771       if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7772         {
7773           rtx second_reloadreg = reloadreg;
7774           reloadreg = rld[secondary_reload].reg_rtx;
7775
7776           /* See if RELOADREG is to be used as a scratch register
7777              or as an intermediate register.  */
7778           if (rl->secondary_out_icode != CODE_FOR_nothing)
7779             {
7780               /* We'd have to add extra code to handle this case.  */
7781               gcc_assert (tertiary_reload < 0);
7782
7783               emit_insn ((GEN_FCN (rl->secondary_out_icode)
7784                           (real_old, second_reloadreg, reloadreg)));
7785               special = 1;
7786             }
7787           else
7788             {
7789               /* See if we need both a scratch and intermediate reload
7790                  register.  */
7791
7792               enum insn_code tertiary_icode
7793                 = rld[secondary_reload].secondary_out_icode;
7794
7795               /* We'd have to add more code for quartary reloads.  */
7796               gcc_assert (tertiary_reload < 0
7797                           || rld[tertiary_reload].secondary_out_reload < 0);
7798
7799               if (GET_MODE (reloadreg) != mode)
7800                 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7801
7802               if (tertiary_icode != CODE_FOR_nothing)
7803                 {
7804                   rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7805
7806                   /* Copy primary reload reg to secondary reload reg.
7807                      (Note that these have been swapped above, then
7808                      secondary reload reg to OLD using our insn.)  */
7809
7810                   /* If REAL_OLD is a paradoxical SUBREG, remove it
7811                      and try to put the opposite SUBREG on
7812                      RELOADREG.  */
7813                   strip_paradoxical_subreg (&real_old, &reloadreg);
7814
7815                   gen_reload (reloadreg, second_reloadreg,
7816                               rl->opnum, rl->when_needed);
7817                   emit_insn ((GEN_FCN (tertiary_icode)
7818                               (real_old, reloadreg, third_reloadreg)));
7819                   special = 1;
7820                 }
7821
7822               else
7823                 {
7824                   /* Copy between the reload regs here and then to
7825                      OUT later.  */
7826
7827                   gen_reload (reloadreg, second_reloadreg,
7828                               rl->opnum, rl->when_needed);
7829                   if (tertiary_reload >= 0)
7830                     {
7831                       rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7832
7833                       gen_reload (third_reloadreg, reloadreg,
7834                                   rl->opnum, rl->when_needed);
7835                       reloadreg = third_reloadreg;
7836                     }
7837                 }
7838             }
7839         }
7840     }
7841
7842   /* Output the last reload insn.  */
7843   if (! special)
7844     {
7845       rtx set;
7846
7847       /* Don't output the last reload if OLD is not the dest of
7848          INSN and is in the src and is clobbered by INSN.  */
7849       if (! flag_expensive_optimizations
7850           || !REG_P (old)
7851           || !(set = single_set (insn))
7852           || rtx_equal_p (old, SET_DEST (set))
7853           || !reg_mentioned_p (old, SET_SRC (set))
7854           || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7855                && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7856         gen_reload (old, reloadreg, rl->opnum,
7857                     rl->when_needed);
7858     }
7859
7860   /* Look at all insns we emitted, just to be safe.  */
7861   for (p = get_insns (); p; p = NEXT_INSN (p))
7862     if (INSN_P (p))
7863       {
7864         rtx pat = PATTERN (p);
7865
7866         /* If this output reload doesn't come from a spill reg,
7867            clear any memory of reloaded copies of the pseudo reg.
7868            If this output reload comes from a spill reg,
7869            reg_has_output_reload will make this do nothing.  */
7870         note_stores (pat, forget_old_reloads_1, NULL);
7871
7872         if (reg_mentioned_p (rl_reg_rtx, pat))
7873           {
7874             rtx set = single_set (insn);
7875             if (reload_spill_index[j] < 0
7876                 && set
7877                 && SET_SRC (set) == rl_reg_rtx)
7878               {
7879                 int src = REGNO (SET_SRC (set));
7880
7881                 reload_spill_index[j] = src;
7882                 SET_HARD_REG_BIT (reg_is_output_reload, src);
7883                 if (find_regno_note (insn, REG_DEAD, src))
7884                   SET_HARD_REG_BIT (reg_reloaded_died, src);
7885               }
7886             if (HARD_REGISTER_P (rl_reg_rtx))
7887               {
7888                 int s = rl->secondary_out_reload;
7889                 set = single_set (p);
7890                 /* If this reload copies only to the secondary reload
7891                    register, the secondary reload does the actual
7892                    store.  */
7893                 if (s >= 0 && set == NULL_RTX)
7894                   /* We can't tell what function the secondary reload
7895                      has and where the actual store to the pseudo is
7896                      made; leave new_spill_reg_store alone.  */
7897                   ;
7898                 else if (s >= 0
7899                          && SET_SRC (set) == rl_reg_rtx
7900                          && SET_DEST (set) == rld[s].reg_rtx)
7901                   {
7902                     /* Usually the next instruction will be the
7903                        secondary reload insn;  if we can confirm
7904                        that it is, setting new_spill_reg_store to
7905                        that insn will allow an extra optimization.  */
7906                     rtx s_reg = rld[s].reg_rtx;
7907                     rtx_insn *next = NEXT_INSN (p);
7908                     rld[s].out = rl->out;
7909                     rld[s].out_reg = rl->out_reg;
7910                     set = single_set (next);
7911                     if (set && SET_SRC (set) == s_reg
7912                         && reload_reg_rtx_reaches_end_p (s_reg, s))
7913                       {
7914                         SET_HARD_REG_BIT (reg_is_output_reload,
7915                                           REGNO (s_reg));
7916                         new_spill_reg_store[REGNO (s_reg)] = next;
7917                       }
7918                   }
7919                 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7920                   new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7921               }
7922           }
7923       }
7924
7925   if (rl->when_needed == RELOAD_OTHER)
7926     {
7927       emit_insn (other_output_reload_insns[rl->opnum]);
7928       other_output_reload_insns[rl->opnum] = get_insns ();
7929     }
7930   else
7931     output_reload_insns[rl->opnum] = get_insns ();
7932
7933   if (cfun->can_throw_non_call_exceptions)
7934     copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7935
7936   end_sequence ();
7937 }
7938
7939 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7940    and has the number J.  */
7941 static void
7942 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7943 {
7944   rtx_insn *insn = chain->insn;
7945   rtx old = (rl->in && MEM_P (rl->in)
7946              ? rl->in_reg : rl->in);
7947   rtx reg_rtx = rl->reg_rtx;
7948
7949   if (old && reg_rtx)
7950     {
7951       machine_mode mode;
7952
7953       /* Determine the mode to reload in.
7954          This is very tricky because we have three to choose from.
7955          There is the mode the insn operand wants (rl->inmode).
7956          There is the mode of the reload register RELOADREG.
7957          There is the intrinsic mode of the operand, which we could find
7958          by stripping some SUBREGs.
7959          It turns out that RELOADREG's mode is irrelevant:
7960          we can change that arbitrarily.
7961
7962          Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7963          then the reload reg may not support QImode moves, so use SImode.
7964          If foo is in memory due to spilling a pseudo reg, this is safe,
7965          because the QImode value is in the least significant part of a
7966          slot big enough for a SImode.  If foo is some other sort of
7967          memory reference, then it is impossible to reload this case,
7968          so previous passes had better make sure this never happens.
7969
7970          Then consider a one-word union which has SImode and one of its
7971          members is a float, being fetched as (SUBREG:SF union:SI).
7972          We must fetch that as SFmode because we could be loading into
7973          a float-only register.  In this case OLD's mode is correct.
7974
7975          Consider an immediate integer: it has VOIDmode.  Here we need
7976          to get a mode from something else.
7977
7978          In some cases, there is a fourth mode, the operand's
7979          containing mode.  If the insn specifies a containing mode for
7980          this operand, it overrides all others.
7981
7982          I am not sure whether the algorithm here is always right,
7983          but it does the right things in those cases.  */
7984
7985       mode = GET_MODE (old);
7986       if (mode == VOIDmode)
7987         mode = rl->inmode;
7988
7989       /* We cannot use gen_lowpart_common since it can do the wrong thing
7990          when REG_RTX has a multi-word mode.  Note that REG_RTX must
7991          always be a REG here.  */
7992       if (GET_MODE (reg_rtx) != mode)
7993         reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7994     }
7995   reload_reg_rtx_for_input[j] = reg_rtx;
7996
7997   if (old != 0
7998       /* AUTO_INC reloads need to be handled even if inherited.  We got an
7999          AUTO_INC reload if reload_out is set but reload_out_reg isn't.  */
8000       && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
8001       && ! rtx_equal_p (reg_rtx, old)
8002       && reg_rtx != 0)
8003     emit_input_reload_insns (chain, rld + j, old, j);
8004
8005   /* When inheriting a wider reload, we have a MEM in rl->in,
8006      e.g. inheriting a SImode output reload for
8007      (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10)))  */
8008   if (optimize && reload_inherited[j] && rl->in
8009       && MEM_P (rl->in)
8010       && MEM_P (rl->in_reg)
8011       && reload_spill_index[j] >= 0
8012       && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
8013     rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
8014
8015   /* If we are reloading a register that was recently stored in with an
8016      output-reload, see if we can prove there was
8017      actually no need to store the old value in it.  */
8018
8019   if (optimize
8020       && (reload_inherited[j] || reload_override_in[j])
8021       && reg_rtx
8022       && REG_P (reg_rtx)
8023       && spill_reg_store[REGNO (reg_rtx)] != 0
8024 #if 0
8025       /* There doesn't seem to be any reason to restrict this to pseudos
8026          and doing so loses in the case where we are copying from a
8027          register of the wrong class.  */
8028       && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
8029 #endif
8030       /* The insn might have already some references to stackslots
8031          replaced by MEMs, while reload_out_reg still names the
8032          original pseudo.  */
8033       && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
8034           || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
8035     delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
8036 }
8037
8038 /* Do output reloading for reload RL, which is for the insn described by
8039    CHAIN and has the number J.
8040    ??? At some point we need to support handling output reloads of
8041    JUMP_INSNs or insns that set cc0.  */
8042 static void
8043 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
8044 {
8045   rtx note, old;
8046   rtx_insn *insn = chain->insn;
8047   /* If this is an output reload that stores something that is
8048      not loaded in this same reload, see if we can eliminate a previous
8049      store.  */
8050   rtx pseudo = rl->out_reg;
8051   rtx reg_rtx = rl->reg_rtx;
8052
8053   if (rl->out && reg_rtx)
8054     {
8055       machine_mode mode;
8056
8057       /* Determine the mode to reload in.
8058          See comments above (for input reloading).  */
8059       mode = GET_MODE (rl->out);
8060       if (mode == VOIDmode)
8061         {
8062           /* VOIDmode should never happen for an output.  */
8063           if (asm_noperands (PATTERN (insn)) < 0)
8064             /* It's the compiler's fault.  */
8065             fatal_insn ("VOIDmode on an output", insn);
8066           error_for_asm (insn, "output operand is constant in %<asm%>");
8067           /* Prevent crash--use something we know is valid.  */
8068           mode = word_mode;
8069           rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
8070         }
8071       if (GET_MODE (reg_rtx) != mode)
8072         reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
8073     }
8074   reload_reg_rtx_for_output[j] = reg_rtx;
8075
8076   if (pseudo
8077       && optimize
8078       && REG_P (pseudo)
8079       && ! rtx_equal_p (rl->in_reg, pseudo)
8080       && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
8081       && reg_last_reload_reg[REGNO (pseudo)])
8082     {
8083       int pseudo_no = REGNO (pseudo);
8084       int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
8085
8086       /* We don't need to test full validity of last_regno for
8087          inherit here; we only want to know if the store actually
8088          matches the pseudo.  */
8089       if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
8090           && reg_reloaded_contents[last_regno] == pseudo_no
8091           && spill_reg_store[last_regno]
8092           && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
8093         delete_output_reload (insn, j, last_regno, reg_rtx);
8094     }
8095
8096   old = rl->out_reg;
8097   if (old == 0
8098       || reg_rtx == 0
8099       || rtx_equal_p (old, reg_rtx))
8100     return;
8101
8102   /* An output operand that dies right away does need a reload,
8103      but need not be copied from it.  Show the new location in the
8104      REG_UNUSED note.  */
8105   if ((REG_P (old) || GET_CODE (old) == SCRATCH)
8106       && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
8107     {
8108       XEXP (note, 0) = reg_rtx;
8109       return;
8110     }
8111   /* Likewise for a SUBREG of an operand that dies.  */
8112   else if (GET_CODE (old) == SUBREG
8113            && REG_P (SUBREG_REG (old))
8114            && 0 != (note = find_reg_note (insn, REG_UNUSED,
8115                                           SUBREG_REG (old))))
8116     {
8117       XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
8118       return;
8119     }
8120   else if (GET_CODE (old) == SCRATCH)
8121     /* If we aren't optimizing, there won't be a REG_UNUSED note,
8122        but we don't want to make an output reload.  */
8123     return;
8124
8125   /* If is a JUMP_INSN, we can't support output reloads yet.  */
8126   gcc_assert (NONJUMP_INSN_P (insn));
8127
8128   emit_output_reload_insns (chain, rld + j, j);
8129 }
8130
8131 /* A reload copies values of MODE from register SRC to register DEST.
8132    Return true if it can be treated for inheritance purposes like a
8133    group of reloads, each one reloading a single hard register.  The
8134    caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8135    occupy the same number of hard registers.  */
8136
8137 static bool
8138 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
8139                      int src ATTRIBUTE_UNUSED,
8140                      machine_mode mode ATTRIBUTE_UNUSED)
8141 {
8142 #ifdef CANNOT_CHANGE_MODE_CLASS
8143   return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
8144           && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
8145 #else
8146   return true;
8147 #endif
8148 }
8149
8150 /* Output insns to reload values in and out of the chosen reload regs.  */
8151
8152 static void
8153 emit_reload_insns (struct insn_chain *chain)
8154 {
8155   rtx_insn *insn = chain->insn;
8156
8157   int j;
8158
8159   CLEAR_HARD_REG_SET (reg_reloaded_died);
8160
8161   for (j = 0; j < reload_n_operands; j++)
8162     input_reload_insns[j] = input_address_reload_insns[j]
8163       = inpaddr_address_reload_insns[j]
8164       = output_reload_insns[j] = output_address_reload_insns[j]
8165       = outaddr_address_reload_insns[j]
8166       = other_output_reload_insns[j] = 0;
8167   other_input_address_reload_insns = 0;
8168   other_input_reload_insns = 0;
8169   operand_reload_insns = 0;
8170   other_operand_reload_insns = 0;
8171
8172   /* Dump reloads into the dump file.  */
8173   if (dump_file)
8174     {
8175       fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8176       debug_reload_to_stream (dump_file);
8177     }
8178
8179   for (j = 0; j < n_reloads; j++)
8180     if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8181       {
8182         unsigned int i;
8183
8184         for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8185           new_spill_reg_store[i] = 0;
8186       }
8187
8188   /* Now output the instructions to copy the data into and out of the
8189      reload registers.  Do these in the order that the reloads were reported,
8190      since reloads of base and index registers precede reloads of operands
8191      and the operands may need the base and index registers reloaded.  */
8192
8193   for (j = 0; j < n_reloads; j++)
8194     {
8195       do_input_reload (chain, rld + j, j);
8196       do_output_reload (chain, rld + j, j);
8197     }
8198
8199   /* Now write all the insns we made for reloads in the order expected by
8200      the allocation functions.  Prior to the insn being reloaded, we write
8201      the following reloads:
8202
8203      RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8204
8205      RELOAD_OTHER reloads.
8206
8207      For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8208      by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8209      RELOAD_FOR_INPUT reload for the operand.
8210
8211      RELOAD_FOR_OPADDR_ADDRS reloads.
8212
8213      RELOAD_FOR_OPERAND_ADDRESS reloads.
8214
8215      After the insn being reloaded, we write the following:
8216
8217      For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8218      by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8219      RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8220      reloads for the operand.  The RELOAD_OTHER output reloads are
8221      output in descending order by reload number.  */
8222
8223   emit_insn_before (other_input_address_reload_insns, insn);
8224   emit_insn_before (other_input_reload_insns, insn);
8225
8226   for (j = 0; j < reload_n_operands; j++)
8227     {
8228       emit_insn_before (inpaddr_address_reload_insns[j], insn);
8229       emit_insn_before (input_address_reload_insns[j], insn);
8230       emit_insn_before (input_reload_insns[j], insn);
8231     }
8232
8233   emit_insn_before (other_operand_reload_insns, insn);
8234   emit_insn_before (operand_reload_insns, insn);
8235
8236   for (j = 0; j < reload_n_operands; j++)
8237     {
8238       rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8239       x = emit_insn_after (output_address_reload_insns[j], x);
8240       x = emit_insn_after (output_reload_insns[j], x);
8241       emit_insn_after (other_output_reload_insns[j], x);
8242     }
8243
8244   /* For all the spill regs newly reloaded in this instruction,
8245      record what they were reloaded from, so subsequent instructions
8246      can inherit the reloads.
8247
8248      Update spill_reg_store for the reloads of this insn.
8249      Copy the elements that were updated in the loop above.  */
8250
8251   for (j = 0; j < n_reloads; j++)
8252     {
8253       int r = reload_order[j];
8254       int i = reload_spill_index[r];
8255
8256       /* If this is a non-inherited input reload from a pseudo, we must
8257          clear any memory of a previous store to the same pseudo.  Only do
8258          something if there will not be an output reload for the pseudo
8259          being reloaded.  */
8260       if (rld[r].in_reg != 0
8261           && ! (reload_inherited[r] || reload_override_in[r]))
8262         {
8263           rtx reg = rld[r].in_reg;
8264
8265           if (GET_CODE (reg) == SUBREG)
8266             reg = SUBREG_REG (reg);
8267
8268           if (REG_P (reg)
8269               && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8270               && !REGNO_REG_SET_P (&reg_has_output_reload, REGNO (reg)))
8271             {
8272               int nregno = REGNO (reg);
8273
8274               if (reg_last_reload_reg[nregno])
8275                 {
8276                   int last_regno = REGNO (reg_last_reload_reg[nregno]);
8277
8278                   if (reg_reloaded_contents[last_regno] == nregno)
8279                     spill_reg_store[last_regno] = 0;
8280                 }
8281             }
8282         }
8283
8284       /* I is nonneg if this reload used a register.
8285          If rld[r].reg_rtx is 0, this is an optional reload
8286          that we opted to ignore.  */
8287
8288       if (i >= 0 && rld[r].reg_rtx != 0)
8289         {
8290           int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8291           int k;
8292
8293           /* For a multi register reload, we need to check if all or part
8294              of the value lives to the end.  */
8295           for (k = 0; k < nr; k++)
8296             if (reload_reg_reaches_end_p (i + k, r))
8297               CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8298
8299           /* Maybe the spill reg contains a copy of reload_out.  */
8300           if (rld[r].out != 0
8301               && (REG_P (rld[r].out)
8302                   || (rld[r].out_reg
8303                       ? REG_P (rld[r].out_reg)
8304                       /* The reload value is an auto-modification of
8305                          some kind.  For PRE_INC, POST_INC, PRE_DEC
8306                          and POST_DEC, we record an equivalence
8307                          between the reload register and the operand
8308                          on the optimistic assumption that we can make
8309                          the equivalence hold.  reload_as_needed must
8310                          then either make it hold or invalidate the
8311                          equivalence.
8312
8313                          PRE_MODIFY and POST_MODIFY addresses are reloaded
8314                          somewhat differently, and allowing them here leads
8315                          to problems.  */
8316                       : (GET_CODE (rld[r].out) != POST_MODIFY
8317                          && GET_CODE (rld[r].out) != PRE_MODIFY))))
8318             {
8319               rtx reg;
8320
8321               reg = reload_reg_rtx_for_output[r];
8322               if (reload_reg_rtx_reaches_end_p (reg, r))
8323                 {
8324                   machine_mode mode = GET_MODE (reg);
8325                   int regno = REGNO (reg);
8326                   int nregs = hard_regno_nregs[regno][mode];
8327                   rtx out = (REG_P (rld[r].out)
8328                              ? rld[r].out
8329                              : rld[r].out_reg
8330                              ? rld[r].out_reg
8331 /* AUTO_INC */               : XEXP (rld[r].in_reg, 0));
8332                   int out_regno = REGNO (out);
8333                   int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8334                                    : hard_regno_nregs[out_regno][mode]);
8335                   bool piecemeal;
8336
8337                   spill_reg_store[regno] = new_spill_reg_store[regno];
8338                   spill_reg_stored_to[regno] = out;
8339                   reg_last_reload_reg[out_regno] = reg;
8340
8341                   piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8342                                && nregs == out_nregs
8343                                && inherit_piecemeal_p (out_regno, regno, mode));
8344
8345                   /* If OUT_REGNO is a hard register, it may occupy more than
8346                      one register.  If it does, say what is in the
8347                      rest of the registers assuming that both registers
8348                      agree on how many words the object takes.  If not,
8349                      invalidate the subsequent registers.  */
8350
8351                   if (HARD_REGISTER_NUM_P (out_regno))
8352                     for (k = 1; k < out_nregs; k++)
8353                       reg_last_reload_reg[out_regno + k]
8354                         = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8355
8356                   /* Now do the inverse operation.  */
8357                   for (k = 0; k < nregs; k++)
8358                     {
8359                       CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8360                       reg_reloaded_contents[regno + k]
8361                         = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8362                            ? out_regno
8363                            : out_regno + k);
8364                       reg_reloaded_insn[regno + k] = insn;
8365                       SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8366                       if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8367                         SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8368                                           regno + k);
8369                       else
8370                         CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8371                                             regno + k);
8372                     }
8373                 }
8374             }
8375           /* Maybe the spill reg contains a copy of reload_in.  Only do
8376              something if there will not be an output reload for
8377              the register being reloaded.  */
8378           else if (rld[r].out_reg == 0
8379                    && rld[r].in != 0
8380                    && ((REG_P (rld[r].in)
8381                         && !HARD_REGISTER_P (rld[r].in)
8382                         && !REGNO_REG_SET_P (&reg_has_output_reload,
8383                                              REGNO (rld[r].in)))
8384                        || (REG_P (rld[r].in_reg)
8385                            && !REGNO_REG_SET_P (&reg_has_output_reload,
8386                                                 REGNO (rld[r].in_reg))))
8387                    && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8388             {
8389               rtx reg;
8390
8391               reg = reload_reg_rtx_for_input[r];
8392               if (reload_reg_rtx_reaches_end_p (reg, r))
8393                 {
8394                   machine_mode mode;
8395                   int regno;
8396                   int nregs;
8397                   int in_regno;
8398                   int in_nregs;
8399                   rtx in;
8400                   bool piecemeal;
8401
8402                   mode = GET_MODE (reg);
8403                   regno = REGNO (reg);
8404                   nregs = hard_regno_nregs[regno][mode];
8405                   if (REG_P (rld[r].in)
8406                       && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8407                     in = rld[r].in;
8408                   else if (REG_P (rld[r].in_reg))
8409                     in = rld[r].in_reg;
8410                   else
8411                     in = XEXP (rld[r].in_reg, 0);
8412                   in_regno = REGNO (in);
8413
8414                   in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8415                               : hard_regno_nregs[in_regno][mode]);
8416
8417                   reg_last_reload_reg[in_regno] = reg;
8418
8419                   piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8420                                && nregs == in_nregs
8421                                && inherit_piecemeal_p (regno, in_regno, mode));
8422
8423                   if (HARD_REGISTER_NUM_P (in_regno))
8424                     for (k = 1; k < in_nregs; k++)
8425                       reg_last_reload_reg[in_regno + k]
8426                         = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8427
8428                   /* Unless we inherited this reload, show we haven't
8429                      recently done a store.
8430                      Previous stores of inherited auto_inc expressions
8431                      also have to be discarded.  */
8432                   if (! reload_inherited[r]
8433                       || (rld[r].out && ! rld[r].out_reg))
8434                     spill_reg_store[regno] = 0;
8435
8436                   for (k = 0; k < nregs; k++)
8437                     {
8438                       CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8439                       reg_reloaded_contents[regno + k]
8440                         = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8441                            ? in_regno
8442                            : in_regno + k);
8443                       reg_reloaded_insn[regno + k] = insn;
8444                       SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8445                       if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8446                         SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8447                                           regno + k);
8448                       else
8449                         CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8450                                             regno + k);
8451                     }
8452                 }
8453             }
8454         }
8455
8456       /* The following if-statement was #if 0'd in 1.34 (or before...).
8457          It's reenabled in 1.35 because supposedly nothing else
8458          deals with this problem.  */
8459
8460       /* If a register gets output-reloaded from a non-spill register,
8461          that invalidates any previous reloaded copy of it.
8462          But forget_old_reloads_1 won't get to see it, because
8463          it thinks only about the original insn.  So invalidate it here.
8464          Also do the same thing for RELOAD_OTHER constraints where the
8465          output is discarded.  */
8466       if (i < 0
8467           && ((rld[r].out != 0
8468                && (REG_P (rld[r].out)
8469                    || (MEM_P (rld[r].out)
8470                        && REG_P (rld[r].out_reg))))
8471               || (rld[r].out == 0 && rld[r].out_reg
8472                   && REG_P (rld[r].out_reg))))
8473         {
8474           rtx out = ((rld[r].out && REG_P (rld[r].out))
8475                      ? rld[r].out : rld[r].out_reg);
8476           int out_regno = REGNO (out);
8477           machine_mode mode = GET_MODE (out);
8478
8479           /* REG_RTX is now set or clobbered by the main instruction.
8480              As the comment above explains, forget_old_reloads_1 only
8481              sees the original instruction, and there is no guarantee
8482              that the original instruction also clobbered REG_RTX.
8483              For example, if find_reloads sees that the input side of
8484              a matched operand pair dies in this instruction, it may
8485              use the input register as the reload register.
8486
8487              Calling forget_old_reloads_1 is a waste of effort if
8488              REG_RTX is also the output register.
8489
8490              If we know that REG_RTX holds the value of a pseudo
8491              register, the code after the call will record that fact.  */
8492           if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8493             forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8494
8495           if (!HARD_REGISTER_NUM_P (out_regno))
8496             {
8497               rtx src_reg;
8498               rtx_insn *store_insn = NULL;
8499
8500               reg_last_reload_reg[out_regno] = 0;
8501
8502               /* If we can find a hard register that is stored, record
8503                  the storing insn so that we may delete this insn with
8504                  delete_output_reload.  */
8505               src_reg = reload_reg_rtx_for_output[r];
8506
8507               if (src_reg)
8508                 {
8509                   if (reload_reg_rtx_reaches_end_p (src_reg, r))
8510                     store_insn = new_spill_reg_store[REGNO (src_reg)];
8511                   else
8512                     src_reg = NULL_RTX;
8513                 }
8514               else
8515                 {
8516                   /* If this is an optional reload, try to find the
8517                      source reg from an input reload.  */
8518                   rtx set = single_set (insn);
8519                   if (set && SET_DEST (set) == rld[r].out)
8520                     {
8521                       int k;
8522
8523                       src_reg = SET_SRC (set);
8524                       store_insn = insn;
8525                       for (k = 0; k < n_reloads; k++)
8526                         {
8527                           if (rld[k].in == src_reg)
8528                             {
8529                               src_reg = reload_reg_rtx_for_input[k];
8530                               break;
8531                             }
8532                         }
8533                     }
8534                 }
8535               if (src_reg && REG_P (src_reg)
8536                   && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8537                 {
8538                   int src_regno, src_nregs, k;
8539                   rtx note;
8540
8541                   gcc_assert (GET_MODE (src_reg) == mode);
8542                   src_regno = REGNO (src_reg);
8543                   src_nregs = hard_regno_nregs[src_regno][mode];
8544                   /* The place where to find a death note varies with
8545                      PRESERVE_DEATH_INFO_REGNO_P .  The condition is not
8546                      necessarily checked exactly in the code that moves
8547                      notes, so just check both locations.  */
8548                   note = find_regno_note (insn, REG_DEAD, src_regno);
8549                   if (! note && store_insn)
8550                     note = find_regno_note (store_insn, REG_DEAD, src_regno);
8551                   for (k = 0; k < src_nregs; k++)
8552                     {
8553                       spill_reg_store[src_regno + k] = store_insn;
8554                       spill_reg_stored_to[src_regno + k] = out;
8555                       reg_reloaded_contents[src_regno + k] = out_regno;
8556                       reg_reloaded_insn[src_regno + k] = store_insn;
8557                       CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8558                       SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8559                       if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8560                                                           mode))
8561                         SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8562                                           src_regno + k);
8563                       else
8564                         CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8565                                             src_regno + k);
8566                       SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8567                       if (note)
8568                         SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8569                       else
8570                         CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8571                     }
8572                   reg_last_reload_reg[out_regno] = src_reg;
8573                   /* We have to set reg_has_output_reload here, or else
8574                      forget_old_reloads_1 will clear reg_last_reload_reg
8575                      right away.  */
8576                   SET_REGNO_REG_SET (&reg_has_output_reload,
8577                                      out_regno);
8578                 }
8579             }
8580           else
8581             {
8582               int k, out_nregs = hard_regno_nregs[out_regno][mode];
8583
8584               for (k = 0; k < out_nregs; k++)
8585                 reg_last_reload_reg[out_regno + k] = 0;
8586             }
8587         }
8588     }
8589   IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8590 }
8591 \f
8592 /* Go through the motions to emit INSN and test if it is strictly valid.
8593    Return the emitted insn if valid, else return NULL.  */
8594
8595 static rtx_insn *
8596 emit_insn_if_valid_for_reload (rtx pat)
8597 {
8598   rtx_insn *last = get_last_insn ();
8599   int code;
8600
8601   rtx_insn *insn = emit_insn (pat);
8602   code = recog_memoized (insn);
8603
8604   if (code >= 0)
8605     {
8606       extract_insn (insn);
8607       /* We want constrain operands to treat this insn strictly in its
8608          validity determination, i.e., the way it would after reload has
8609          completed.  */
8610       if (constrain_operands (1, get_enabled_alternatives (insn)))
8611         return insn;
8612     }
8613
8614   delete_insns_since (last);
8615   return NULL;
8616 }
8617
8618 /* Emit code to perform a reload from IN (which may be a reload register) to
8619    OUT (which may also be a reload register).  IN or OUT is from operand
8620    OPNUM with reload type TYPE.
8621
8622    Returns first insn emitted.  */
8623
8624 static rtx_insn *
8625 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8626 {
8627   rtx_insn *last = get_last_insn ();
8628   rtx_insn *tem;
8629 #ifdef SECONDARY_MEMORY_NEEDED
8630   rtx tem1, tem2;
8631 #endif
8632
8633   /* If IN is a paradoxical SUBREG, remove it and try to put the
8634      opposite SUBREG on OUT.  Likewise for a paradoxical SUBREG on OUT.  */
8635   if (!strip_paradoxical_subreg (&in, &out))
8636     strip_paradoxical_subreg (&out, &in);
8637
8638   /* How to do this reload can get quite tricky.  Normally, we are being
8639      asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8640      register that didn't get a hard register.  In that case we can just
8641      call emit_move_insn.
8642
8643      We can also be asked to reload a PLUS that adds a register or a MEM to
8644      another register, constant or MEM.  This can occur during frame pointer
8645      elimination and while reloading addresses.  This case is handled by
8646      trying to emit a single insn to perform the add.  If it is not valid,
8647      we use a two insn sequence.
8648
8649      Or we can be asked to reload an unary operand that was a fragment of
8650      an addressing mode, into a register.  If it isn't recognized as-is,
8651      we try making the unop operand and the reload-register the same:
8652      (set reg:X (unop:X expr:Y))
8653      -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8654
8655      Finally, we could be called to handle an 'o' constraint by putting
8656      an address into a register.  In that case, we first try to do this
8657      with a named pattern of "reload_load_address".  If no such pattern
8658      exists, we just emit a SET insn and hope for the best (it will normally
8659      be valid on machines that use 'o').
8660
8661      This entire process is made complex because reload will never
8662      process the insns we generate here and so we must ensure that
8663      they will fit their constraints and also by the fact that parts of
8664      IN might be being reloaded separately and replaced with spill registers.
8665      Because of this, we are, in some sense, just guessing the right approach
8666      here.  The one listed above seems to work.
8667
8668      ??? At some point, this whole thing needs to be rethought.  */
8669
8670   if (GET_CODE (in) == PLUS
8671       && (REG_P (XEXP (in, 0))
8672           || GET_CODE (XEXP (in, 0)) == SUBREG
8673           || MEM_P (XEXP (in, 0)))
8674       && (REG_P (XEXP (in, 1))
8675           || GET_CODE (XEXP (in, 1)) == SUBREG
8676           || CONSTANT_P (XEXP (in, 1))
8677           || MEM_P (XEXP (in, 1))))
8678     {
8679       /* We need to compute the sum of a register or a MEM and another
8680          register, constant, or MEM, and put it into the reload
8681          register.  The best possible way of doing this is if the machine
8682          has a three-operand ADD insn that accepts the required operands.
8683
8684          The simplest approach is to try to generate such an insn and see if it
8685          is recognized and matches its constraints.  If so, it can be used.
8686
8687          It might be better not to actually emit the insn unless it is valid,
8688          but we need to pass the insn as an operand to `recog' and
8689          `extract_insn' and it is simpler to emit and then delete the insn if
8690          not valid than to dummy things up.  */
8691
8692       rtx op0, op1, tem;
8693       rtx_insn *insn;
8694       enum insn_code code;
8695
8696       op0 = find_replacement (&XEXP (in, 0));
8697       op1 = find_replacement (&XEXP (in, 1));
8698
8699       /* Since constraint checking is strict, commutativity won't be
8700          checked, so we need to do that here to avoid spurious failure
8701          if the add instruction is two-address and the second operand
8702          of the add is the same as the reload reg, which is frequently
8703          the case.  If the insn would be A = B + A, rearrange it so
8704          it will be A = A + B as constrain_operands expects.  */
8705
8706       if (REG_P (XEXP (in, 1))
8707           && REGNO (out) == REGNO (XEXP (in, 1)))
8708         tem = op0, op0 = op1, op1 = tem;
8709
8710       if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8711         in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8712
8713       insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8714       if (insn)
8715         return insn;
8716
8717       /* If that failed, we must use a conservative two-insn sequence.
8718
8719          Use a move to copy one operand into the reload register.  Prefer
8720          to reload a constant, MEM or pseudo since the move patterns can
8721          handle an arbitrary operand.  If OP1 is not a constant, MEM or
8722          pseudo and OP1 is not a valid operand for an add instruction, then
8723          reload OP1.
8724
8725          After reloading one of the operands into the reload register, add
8726          the reload register to the output register.
8727
8728          If there is another way to do this for a specific machine, a
8729          DEFINE_PEEPHOLE should be specified that recognizes the sequence
8730          we emit below.  */
8731
8732       code = optab_handler (add_optab, GET_MODE (out));
8733
8734       if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8735           || (REG_P (op1)
8736               && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8737           || (code != CODE_FOR_nothing
8738               && !insn_operand_matches (code, 2, op1)))
8739         tem = op0, op0 = op1, op1 = tem;
8740
8741       gen_reload (out, op0, opnum, type);
8742
8743       /* If OP0 and OP1 are the same, we can use OUT for OP1.
8744          This fixes a problem on the 32K where the stack pointer cannot
8745          be used as an operand of an add insn.  */
8746
8747       if (rtx_equal_p (op0, op1))
8748         op1 = out;
8749
8750       insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8751       if (insn)
8752         {
8753           /* Add a REG_EQUIV note so that find_equiv_reg can find it.  */
8754           set_dst_reg_note (insn, REG_EQUIV, in, out);
8755           return insn;
8756         }
8757
8758       /* If that failed, copy the address register to the reload register.
8759          Then add the constant to the reload register.  */
8760
8761       gcc_assert (!reg_overlap_mentioned_p (out, op0));
8762       gen_reload (out, op1, opnum, type);
8763       insn = emit_insn (gen_add2_insn (out, op0));
8764       set_dst_reg_note (insn, REG_EQUIV, in, out);
8765     }
8766
8767 #ifdef SECONDARY_MEMORY_NEEDED
8768   /* If we need a memory location to do the move, do it that way.  */
8769   else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out),
8770             (REG_P (tem1) && REG_P (tem2)))
8771            && REGNO (tem1) < FIRST_PSEUDO_REGISTER
8772            && REGNO (tem2) < FIRST_PSEUDO_REGISTER
8773            && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1)),
8774                                        REGNO_REG_CLASS (REGNO (tem2)),
8775                                        GET_MODE (out)))
8776     {
8777       /* Get the memory to use and rewrite both registers to its mode.  */
8778       rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8779
8780       if (GET_MODE (loc) != GET_MODE (out))
8781         out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8782
8783       if (GET_MODE (loc) != GET_MODE (in))
8784         in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8785
8786       gen_reload (loc, in, opnum, type);
8787       gen_reload (out, loc, opnum, type);
8788     }
8789 #endif
8790   else if (REG_P (out) && UNARY_P (in))
8791     {
8792       rtx insn;
8793       rtx op1;
8794       rtx out_moded;
8795       rtx_insn *set;
8796
8797       op1 = find_replacement (&XEXP (in, 0));
8798       if (op1 != XEXP (in, 0))
8799         in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8800
8801       /* First, try a plain SET.  */
8802       set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8803       if (set)
8804         return set;
8805
8806       /* If that failed, move the inner operand to the reload
8807          register, and try the same unop with the inner expression
8808          replaced with the reload register.  */
8809
8810       if (GET_MODE (op1) != GET_MODE (out))
8811         out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8812       else
8813         out_moded = out;
8814
8815       gen_reload (out_moded, op1, opnum, type);
8816
8817       insn
8818         = gen_rtx_SET (VOIDmode, out,
8819                        gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8820                                       out_moded));
8821       insn = emit_insn_if_valid_for_reload (insn);
8822       if (insn)
8823         {
8824           set_unique_reg_note (insn, REG_EQUIV, in);
8825           return as_a <rtx_insn *> (insn);
8826         }
8827
8828       fatal_insn ("failure trying to reload:", set);
8829     }
8830   /* If IN is a simple operand, use gen_move_insn.  */
8831   else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8832     {
8833       tem = emit_insn (gen_move_insn (out, in));
8834       /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note.  */
8835       mark_jump_label (in, tem, 0);
8836     }
8837
8838 #ifdef HAVE_reload_load_address
8839   else if (HAVE_reload_load_address)
8840     emit_insn (gen_reload_load_address (out, in));
8841 #endif
8842
8843   /* Otherwise, just write (set OUT IN) and hope for the best.  */
8844   else
8845     emit_insn (gen_rtx_SET (VOIDmode, out, in));
8846
8847   /* Return the first insn emitted.
8848      We can not just return get_last_insn, because there may have
8849      been multiple instructions emitted.  Also note that gen_move_insn may
8850      emit more than one insn itself, so we can not assume that there is one
8851      insn emitted per emit_insn_before call.  */
8852
8853   return last ? NEXT_INSN (last) : get_insns ();
8854 }
8855 \f
8856 /* Delete a previously made output-reload whose result we now believe
8857    is not needed.  First we double-check.
8858
8859    INSN is the insn now being processed.
8860    LAST_RELOAD_REG is the hard register number for which we want to delete
8861    the last output reload.
8862    J is the reload-number that originally used REG.  The caller has made
8863    certain that reload J doesn't use REG any longer for input.
8864    NEW_RELOAD_REG is reload register that reload J is using for REG.  */
8865
8866 static void
8867 delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
8868                       rtx new_reload_reg)
8869 {
8870   rtx_insn *output_reload_insn = spill_reg_store[last_reload_reg];
8871   rtx reg = spill_reg_stored_to[last_reload_reg];
8872   int k;
8873   int n_occurrences;
8874   int n_inherited = 0;
8875   rtx substed;
8876   unsigned regno;
8877   int nregs;
8878
8879   /* It is possible that this reload has been only used to set another reload
8880      we eliminated earlier and thus deleted this instruction too.  */
8881   if (output_reload_insn->deleted ())
8882     return;
8883
8884   /* Get the raw pseudo-register referred to.  */
8885
8886   while (GET_CODE (reg) == SUBREG)
8887     reg = SUBREG_REG (reg);
8888   substed = reg_equiv_memory_loc (REGNO (reg));
8889
8890   /* This is unsafe if the operand occurs more often in the current
8891      insn than it is inherited.  */
8892   for (k = n_reloads - 1; k >= 0; k--)
8893     {
8894       rtx reg2 = rld[k].in;
8895       if (! reg2)
8896         continue;
8897       if (MEM_P (reg2) || reload_override_in[k])
8898         reg2 = rld[k].in_reg;
8899 #ifdef AUTO_INC_DEC
8900       if (rld[k].out && ! rld[k].out_reg)
8901         reg2 = XEXP (rld[k].in_reg, 0);
8902 #endif
8903       while (GET_CODE (reg2) == SUBREG)
8904         reg2 = SUBREG_REG (reg2);
8905       if (rtx_equal_p (reg2, reg))
8906         {
8907           if (reload_inherited[k] || reload_override_in[k] || k == j)
8908             n_inherited++;
8909           else
8910             return;
8911         }
8912     }
8913   n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8914   if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8915     n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8916                                         reg, 0);
8917   if (substed)
8918     n_occurrences += count_occurrences (PATTERN (insn),
8919                                         eliminate_regs (substed, VOIDmode,
8920                                                         NULL_RTX), 0);
8921   for (rtx i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8922     {
8923       gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8924       n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8925     }
8926   if (n_occurrences > n_inherited)
8927     return;
8928
8929   regno = REGNO (reg);
8930   if (regno >= FIRST_PSEUDO_REGISTER)
8931     nregs = 1;
8932   else
8933     nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8934
8935   /* If the pseudo-reg we are reloading is no longer referenced
8936      anywhere between the store into it and here,
8937      and we're within the same basic block, then the value can only
8938      pass through the reload reg and end up here.
8939      Otherwise, give up--return.  */
8940   for (rtx_insn *i1 = NEXT_INSN (output_reload_insn);
8941        i1 != insn; i1 = NEXT_INSN (i1))
8942     {
8943       if (NOTE_INSN_BASIC_BLOCK_P (i1))
8944         return;
8945       if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8946           && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8947         {
8948           /* If this is USE in front of INSN, we only have to check that
8949              there are no more references than accounted for by inheritance.  */
8950           while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8951             {
8952               n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8953               i1 = NEXT_INSN (i1);
8954             }
8955           if (n_occurrences <= n_inherited && i1 == insn)
8956             break;
8957           return;
8958         }
8959     }
8960
8961   /* We will be deleting the insn.  Remove the spill reg information.  */
8962   for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8963     {
8964       spill_reg_store[last_reload_reg + k] = 0;
8965       spill_reg_stored_to[last_reload_reg + k] = 0;
8966     }
8967
8968   /* The caller has already checked that REG dies or is set in INSN.
8969      It has also checked that we are optimizing, and thus some
8970      inaccuracies in the debugging information are acceptable.
8971      So we could just delete output_reload_insn.  But in some cases
8972      we can improve the debugging information without sacrificing
8973      optimization - maybe even improving the code: See if the pseudo
8974      reg has been completely replaced with reload regs.  If so, delete
8975      the store insn and forget we had a stack slot for the pseudo.  */
8976   if (rld[j].out != rld[j].in
8977       && REG_N_DEATHS (REGNO (reg)) == 1
8978       && REG_N_SETS (REGNO (reg)) == 1
8979       && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8980       && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8981     {
8982       rtx_insn *i2;
8983
8984       /* We know that it was used only between here and the beginning of
8985          the current basic block.  (We also know that the last use before
8986          INSN was the output reload we are thinking of deleting, but never
8987          mind that.)  Search that range; see if any ref remains.  */
8988       for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8989         {
8990           rtx set = single_set (i2);
8991
8992           /* Uses which just store in the pseudo don't count,
8993              since if they are the only uses, they are dead.  */
8994           if (set != 0 && SET_DEST (set) == reg)
8995             continue;
8996           if (LABEL_P (i2) || JUMP_P (i2))
8997             break;
8998           if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8999               && reg_mentioned_p (reg, PATTERN (i2)))
9000             {
9001               /* Some other ref remains; just delete the output reload we
9002                  know to be dead.  */
9003               delete_address_reloads (output_reload_insn, insn);
9004               delete_insn (output_reload_insn);
9005               return;
9006             }
9007         }
9008
9009       /* Delete the now-dead stores into this pseudo.  Note that this
9010          loop also takes care of deleting output_reload_insn.  */
9011       for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
9012         {
9013           rtx set = single_set (i2);
9014
9015           if (set != 0 && SET_DEST (set) == reg)
9016             {
9017               delete_address_reloads (i2, insn);
9018               delete_insn (i2);
9019             }
9020           if (LABEL_P (i2) || JUMP_P (i2))
9021             break;
9022         }
9023
9024       /* For the debugging info, say the pseudo lives in this reload reg.  */
9025       reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
9026       if (ira_conflicts_p)
9027         /* Inform IRA about the change.  */
9028         ira_mark_allocation_change (REGNO (reg));
9029       alter_reg (REGNO (reg), -1, false);
9030     }
9031   else
9032     {
9033       delete_address_reloads (output_reload_insn, insn);
9034       delete_insn (output_reload_insn);
9035     }
9036 }
9037
9038 /* We are going to delete DEAD_INSN.  Recursively delete loads of
9039    reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
9040    CURRENT_INSN is being reloaded, so we have to check its reloads too.  */
9041 static void
9042 delete_address_reloads (rtx_insn *dead_insn, rtx_insn *current_insn)
9043 {
9044   rtx set = single_set (dead_insn);
9045   rtx set2, dst;
9046   rtx_insn *prev, *next;
9047   if (set)
9048     {
9049       rtx dst = SET_DEST (set);
9050       if (MEM_P (dst))
9051         delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
9052     }
9053   /* If we deleted the store from a reloaded post_{in,de}c expression,
9054      we can delete the matching adds.  */
9055   prev = PREV_INSN (dead_insn);
9056   next = NEXT_INSN (dead_insn);
9057   if (! prev || ! next)
9058     return;
9059   set = single_set (next);
9060   set2 = single_set (prev);
9061   if (! set || ! set2
9062       || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
9063       || !CONST_INT_P (XEXP (SET_SRC (set), 1))
9064       || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
9065     return;
9066   dst = SET_DEST (set);
9067   if (! rtx_equal_p (dst, SET_DEST (set2))
9068       || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
9069       || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
9070       || (INTVAL (XEXP (SET_SRC (set), 1))
9071           != -INTVAL (XEXP (SET_SRC (set2), 1))))
9072     return;
9073   delete_related_insns (prev);
9074   delete_related_insns (next);
9075 }
9076
9077 /* Subfunction of delete_address_reloads: process registers found in X.  */
9078 static void
9079 delete_address_reloads_1 (rtx_insn *dead_insn, rtx x, rtx_insn *current_insn)
9080 {
9081   rtx_insn *prev, *i2;
9082   rtx set, dst;
9083   int i, j;
9084   enum rtx_code code = GET_CODE (x);
9085
9086   if (code != REG)
9087     {
9088       const char *fmt = GET_RTX_FORMAT (code);
9089       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9090         {
9091           if (fmt[i] == 'e')
9092             delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
9093           else if (fmt[i] == 'E')
9094             {
9095               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9096                 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
9097                                           current_insn);
9098             }
9099         }
9100       return;
9101     }
9102
9103   if (spill_reg_order[REGNO (x)] < 0)
9104     return;
9105
9106   /* Scan backwards for the insn that sets x.  This might be a way back due
9107      to inheritance.  */
9108   for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
9109     {
9110       code = GET_CODE (prev);
9111       if (code == CODE_LABEL || code == JUMP_INSN)
9112         return;
9113       if (!INSN_P (prev))
9114         continue;
9115       if (reg_set_p (x, PATTERN (prev)))
9116         break;
9117       if (reg_referenced_p (x, PATTERN (prev)))
9118         return;
9119     }
9120   if (! prev || INSN_UID (prev) < reload_first_uid)
9121     return;
9122   /* Check that PREV only sets the reload register.  */
9123   set = single_set (prev);
9124   if (! set)
9125     return;
9126   dst = SET_DEST (set);
9127   if (!REG_P (dst)
9128       || ! rtx_equal_p (dst, x))
9129     return;
9130   if (! reg_set_p (dst, PATTERN (dead_insn)))
9131     {
9132       /* Check if DST was used in a later insn -
9133          it might have been inherited.  */
9134       for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
9135         {
9136           if (LABEL_P (i2))
9137             break;
9138           if (! INSN_P (i2))
9139             continue;
9140           if (reg_referenced_p (dst, PATTERN (i2)))
9141             {
9142               /* If there is a reference to the register in the current insn,
9143                  it might be loaded in a non-inherited reload.  If no other
9144                  reload uses it, that means the register is set before
9145                  referenced.  */
9146               if (i2 == current_insn)
9147                 {
9148                   for (j = n_reloads - 1; j >= 0; j--)
9149                     if ((rld[j].reg_rtx == dst && reload_inherited[j])
9150                         || reload_override_in[j] == dst)
9151                       return;
9152                   for (j = n_reloads - 1; j >= 0; j--)
9153                     if (rld[j].in && rld[j].reg_rtx == dst)
9154                       break;
9155                   if (j >= 0)
9156                     break;
9157                 }
9158               return;
9159             }
9160           if (JUMP_P (i2))
9161             break;
9162           /* If DST is still live at CURRENT_INSN, check if it is used for
9163              any reload.  Note that even if CURRENT_INSN sets DST, we still
9164              have to check the reloads.  */
9165           if (i2 == current_insn)
9166             {
9167               for (j = n_reloads - 1; j >= 0; j--)
9168                 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9169                     || reload_override_in[j] == dst)
9170                   return;
9171               /* ??? We can't finish the loop here, because dst might be
9172                  allocated to a pseudo in this block if no reload in this
9173                  block needs any of the classes containing DST - see
9174                  spill_hard_reg.  There is no easy way to tell this, so we
9175                  have to scan till the end of the basic block.  */
9176             }
9177           if (reg_set_p (dst, PATTERN (i2)))
9178             break;
9179         }
9180     }
9181   delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9182   reg_reloaded_contents[REGNO (dst)] = -1;
9183   delete_insn (prev);
9184 }
9185 \f
9186 /* Output reload-insns to reload VALUE into RELOADREG.
9187    VALUE is an autoincrement or autodecrement RTX whose operand
9188    is a register or memory location;
9189    so reloading involves incrementing that location.
9190    IN is either identical to VALUE, or some cheaper place to reload from.
9191
9192    INC_AMOUNT is the number to increment or decrement by (always positive).
9193    This cannot be deduced from VALUE.  */
9194
9195 static void
9196 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9197 {
9198   /* REG or MEM to be copied and incremented.  */
9199   rtx incloc = find_replacement (&XEXP (value, 0));
9200   /* Nonzero if increment after copying.  */
9201   int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9202               || GET_CODE (value) == POST_MODIFY);
9203   rtx_insn *last;
9204   rtx inc;
9205   rtx_insn *add_insn;
9206   int code;
9207   rtx real_in = in == value ? incloc : in;
9208
9209   /* No hard register is equivalent to this register after
9210      inc/dec operation.  If REG_LAST_RELOAD_REG were nonzero,
9211      we could inc/dec that register as well (maybe even using it for
9212      the source), but I'm not sure it's worth worrying about.  */
9213   if (REG_P (incloc))
9214     reg_last_reload_reg[REGNO (incloc)] = 0;
9215
9216   if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9217     {
9218       gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9219       inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9220     }
9221   else
9222     {
9223       if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9224         inc_amount = -inc_amount;
9225
9226       inc = GEN_INT (inc_amount);
9227     }
9228
9229   /* If this is post-increment, first copy the location to the reload reg.  */
9230   if (post && real_in != reloadreg)
9231     emit_insn (gen_move_insn (reloadreg, real_in));
9232
9233   if (in == value)
9234     {
9235       /* See if we can directly increment INCLOC.  Use a method similar to
9236          that in gen_reload.  */
9237
9238       last = get_last_insn ();
9239       add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9240                                          gen_rtx_PLUS (GET_MODE (incloc),
9241                                                        incloc, inc)));
9242
9243       code = recog_memoized (add_insn);
9244       if (code >= 0)
9245         {
9246           extract_insn (add_insn);
9247           if (constrain_operands (1, get_enabled_alternatives (add_insn)))
9248             {
9249               /* If this is a pre-increment and we have incremented the value
9250                  where it lives, copy the incremented value to RELOADREG to
9251                  be used as an address.  */
9252
9253               if (! post)
9254                 emit_insn (gen_move_insn (reloadreg, incloc));
9255               return;
9256             }
9257         }
9258       delete_insns_since (last);
9259     }
9260
9261   /* If couldn't do the increment directly, must increment in RELOADREG.
9262      The way we do this depends on whether this is pre- or post-increment.
9263      For pre-increment, copy INCLOC to the reload register, increment it
9264      there, then save back.  */
9265
9266   if (! post)
9267     {
9268       if (in != reloadreg)
9269         emit_insn (gen_move_insn (reloadreg, real_in));
9270       emit_insn (gen_add2_insn (reloadreg, inc));
9271       emit_insn (gen_move_insn (incloc, reloadreg));
9272     }
9273   else
9274     {
9275       /* Postincrement.
9276          Because this might be a jump insn or a compare, and because RELOADREG
9277          may not be available after the insn in an input reload, we must do
9278          the incrementation before the insn being reloaded for.
9279
9280          We have already copied IN to RELOADREG.  Increment the copy in
9281          RELOADREG, save that back, then decrement RELOADREG so it has
9282          the original value.  */
9283
9284       emit_insn (gen_add2_insn (reloadreg, inc));
9285       emit_insn (gen_move_insn (incloc, reloadreg));
9286       if (CONST_INT_P (inc))
9287         emit_insn (gen_add2_insn (reloadreg,
9288                                   gen_int_mode (-INTVAL (inc),
9289                                                 GET_MODE (reloadreg))));
9290       else
9291         emit_insn (gen_sub2_insn (reloadreg, inc));
9292     }
9293 }
9294 \f
9295 #ifdef AUTO_INC_DEC
9296 static void
9297 add_auto_inc_notes (rtx_insn *insn, rtx x)
9298 {
9299   enum rtx_code code = GET_CODE (x);
9300   const char *fmt;
9301   int i, j;
9302
9303   if (code == MEM && auto_inc_p (XEXP (x, 0)))
9304     {
9305       add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9306       return;
9307     }
9308
9309   /* Scan all the operand sub-expressions.  */
9310   fmt = GET_RTX_FORMAT (code);
9311   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9312     {
9313       if (fmt[i] == 'e')
9314         add_auto_inc_notes (insn, XEXP (x, i));
9315       else if (fmt[i] == 'E')
9316         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9317           add_auto_inc_notes (insn, XVECEXP (x, i, j));
9318     }
9319 }
9320 #endif