| blob | 989a296eb335c6f28f317caaee67c2bdfd327438 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2014 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56 (TFHAR_REGNO 114)
57 (TFIAR_REGNO 115)
58 (TEXASR_REGNO 116)
59 (FIRST_SPE_HIGH_REGNO 117)
60 (LAST_SPE_HIGH_REGNO 148)
61 ])
63 ;;
64 ;; UNSPEC usage
65 ;;
67 (define_c_enum "unspec"
68 [UNSPEC_FRSP ; frsp for POWER machines
69 UNSPEC_PROBE_STACK ; probe stack memory reference
70 UNSPEC_TOCPTR ; address of a word pointing to the TOC
71 UNSPEC_TOC ; address of the TOC (more-or-less)
72 UNSPEC_MOVSI_GOT
73 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
74 UNSPEC_FCTIWZ
75 UNSPEC_FRIM
76 UNSPEC_FRIN
77 UNSPEC_FRIP
78 UNSPEC_FRIZ
79 UNSPEC_LD_MPIC ; load_macho_picbase
80 UNSPEC_RELD_MPIC ; re-load_macho_picbase
81 UNSPEC_MPIC_CORRECT ; macho_correct_pic
82 UNSPEC_TLSGD
83 UNSPEC_TLSLD
84 UNSPEC_MOVESI_FROM_CR
85 UNSPEC_MOVESI_TO_CR
86 UNSPEC_TLSDTPREL
87 UNSPEC_TLSDTPRELHA
88 UNSPEC_TLSDTPRELLO
89 UNSPEC_TLSGOTDTPREL
90 UNSPEC_TLSTPREL
91 UNSPEC_TLSTPRELHA
92 UNSPEC_TLSTPRELLO
93 UNSPEC_TLSGOTTPREL
94 UNSPEC_TLSTLS
95 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
96 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
97 UNSPEC_STFIWX
98 UNSPEC_POPCNTB
99 UNSPEC_FRES
100 UNSPEC_SP_SET
101 UNSPEC_SP_TEST
102 UNSPEC_SYNC
103 UNSPEC_LWSYNC
104 UNSPEC_SYNC_OP
105 UNSPEC_ATOMIC
106 UNSPEC_CMPXCHG
107 UNSPEC_XCHG
108 UNSPEC_AND
109 UNSPEC_DLMZB
110 UNSPEC_DLMZB_CR
111 UNSPEC_DLMZB_STRLEN
112 UNSPEC_RSQRT
113 UNSPEC_TOCREL
114 UNSPEC_MACHOPIC_OFFSET
115 UNSPEC_BPERM
116 UNSPEC_COPYSIGN
117 UNSPEC_PARITY
118 UNSPEC_FCTIW
119 UNSPEC_FCTID
120 UNSPEC_LFIWAX
121 UNSPEC_LFIWZX
122 UNSPEC_FCTIWUZ
123 UNSPEC_GRP_END_NOP
124 UNSPEC_P8V_FMRGOW
125 UNSPEC_P8V_MTVSRWZ
126 UNSPEC_P8V_RELOAD_FROM_GPR
127 UNSPEC_P8V_MTVSRD
128 UNSPEC_P8V_XXPERMDI
129 UNSPEC_P8V_RELOAD_FROM_VSX
130 UNSPEC_ADDG6S
131 UNSPEC_CDTBCD
132 UNSPEC_CBCDTD
133 UNSPEC_DIVE
134 UNSPEC_DIVEO
135 UNSPEC_DIVEU
136 UNSPEC_DIVEUO
137 UNSPEC_UNPACK_128BIT
138 UNSPEC_PACK_128BIT
139 UNSPEC_LSQ
140 UNSPEC_FUSION_GPR
141 ])
143 ;;
144 ;; UNSPEC_VOLATILE usage
145 ;;
147 (define_c_enum "unspecv"
148 [UNSPECV_BLOCK
149 UNSPECV_LL ; load-locked
150 UNSPECV_SC ; store-conditional
151 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
152 UNSPECV_EH_RR ; eh_reg_restore
153 UNSPECV_ISYNC ; isync instruction
154 UNSPECV_MFTB ; move from time base
155 UNSPECV_NLGR ; non-local goto receiver
156 UNSPECV_MFFS ; Move from FPSCR
157 UNSPECV_MTFSF ; Move to FPSCR Fields
158 ])
160 \f
161 ;; Define an insn type attribute. This is used in function unit delay
162 ;; computations.
163 (define_attr "type"
164 "integer,two,three,
165 add,logical,shift,insert,
166 mul,halfmul,div,
167 exts,cntlz,popcnt,isel,
168 load,store,fpload,fpstore,vecload,vecstore,
169 cmp,
170 branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
171 compare,
172 cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
173 fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
174 brinc,
175 vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
176 vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
177 htm"
178 (const_string "integer"))
180 ;; What data size does this instruction work on?
181 ;; This is used for insert, mul.
182 (define_attr "size" "8,16,32,64" (const_string "32"))
184 ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
185 ;; This is used for add, logical, shift, exts, mul.
186 (define_attr "dot" "no,yes" (const_string "no"))
188 ;; Does this instruction sign-extend its result?
189 ;; This is used for load insns.
190 (define_attr "sign_extend" "no,yes" (const_string "no"))
192 ;; Does this instruction use indexed (that is, reg+reg) addressing?
193 ;; This is used for load and store insns. If operand 0 or 1 is a MEM
194 ;; it is automatically set based on that. If a load or store instruction
195 ;; has fewer than two operands it needs to set this attribute manually
196 ;; or the compiler will crash.
197 (define_attr "indexed" "no,yes"
198 (if_then_else (ior (match_operand 0 "indexed_address_mem")
199 (match_operand 1 "indexed_address_mem"))
200 (const_string "yes")
201 (const_string "no")))
203 ;; Does this instruction use update addressing?
204 ;; This is used for load and store insns. See the comments for "indexed".
205 (define_attr "update" "no,yes"
206 (if_then_else (ior (match_operand 0 "update_address_mem")
207 (match_operand 1 "update_address_mem"))
208 (const_string "yes")
209 (const_string "no")))
211 ;; Is this instruction using operands[2] as shift amount, and can that be a
212 ;; register?
213 ;; This is used for shift insns.
214 (define_attr "maybe_var_shift" "no,yes" (const_string "no"))
216 ;; Is this instruction using a shift amount from a register?
217 ;; This is used for shift insns.
218 (define_attr "var_shift" "no,yes"
219 (if_then_else (and (eq_attr "type" "shift")
220 (eq_attr "maybe_var_shift" "yes"))
221 (if_then_else (match_operand 2 "gpc_reg_operand")
222 (const_string "yes")
223 (const_string "no"))
224 (const_string "no")))
226 ;; Define floating point instruction sub-types for use with Xfpu.md
227 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
229 ;; Length (in bytes).
230 ; '(pc)' in the following doesn't include the instruction itself; it is
231 ; calculated as if the instruction had zero size.
232 (define_attr "length" ""
233 (if_then_else (eq_attr "type" "branch")
234 (if_then_else (and (ge (minus (match_dup 0) (pc))
235 (const_int -32768))
236 (lt (minus (match_dup 0) (pc))
237 (const_int 32764)))
238 (const_int 4)
239 (const_int 8))
240 (const_int 4)))
242 ;; Processor type -- this attribute must exactly match the processor_type
243 ;; enumeration in rs6000-opts.h.
244 (define_attr "cpu"
245 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
246 ppc750,ppc7400,ppc7450,
247 ppc403,ppc405,ppc440,ppc476,
248 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
249 power4,power5,power6,power7,power8,
250 rs64a,mpccore,cell,ppca2,titan"
251 (const (symbol_ref "rs6000_cpu_attr")))
254 ;; If this instruction is microcoded on the CELL processor
255 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
256 (define_attr "cell_micro" "not,conditional,always"
257 (if_then_else (ior (eq_attr "type" "compare")
258 (and (eq_attr "type" "shift,exts,mul")
259 (eq_attr "dot" "yes"))
260 (and (eq_attr "type" "load")
261 (eq_attr "sign_extend" "yes"))
262 (and (eq_attr "type" "shift")
263 (eq_attr "var_shift" "yes")))
264 (const_string "always")
265 (const_string "not")))
267 (automata_option "ndfa")
269 (include "rs64.md")
270 (include "mpc.md")
271 (include "40x.md")
272 (include "440.md")
273 (include "476.md")
274 (include "601.md")
275 (include "603.md")
276 (include "6xx.md")
277 (include "7xx.md")
278 (include "7450.md")
279 (include "8540.md")
280 (include "e300c2c3.md")
281 (include "e500mc.md")
282 (include "e500mc64.md")
283 (include "e5500.md")
284 (include "e6500.md")
285 (include "power4.md")
286 (include "power5.md")
287 (include "power6.md")
288 (include "power7.md")
289 (include "power8.md")
290 (include "cell.md")
291 (include "xfpu.md")
292 (include "a2.md")
293 (include "titan.md")
295 (include "predicates.md")
296 (include "constraints.md")
298 (include "darwin.md")
300 \f
301 ;; Mode iterators
303 ; This mode iterator allows :GPR to be used to indicate the allowable size
304 ; of whole values in GPRs.
305 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
307 ; Any supported integer mode.
308 (define_mode_iterator INT [QI HI SI DI TI PTI])
310 ; Any supported integer mode that fits in one register.
311 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
313 ; Everything we can extend QImode to.
314 (define_mode_iterator EXTQI [HI SI (DI "TARGET_POWERPC64")])
316 ; Everything we can extend HImode to.
317 (define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")])
319 ; Everything we can extend SImode to.
320 (define_mode_iterator EXTSI [(DI "TARGET_POWERPC64")])
322 ; QImode or HImode for small atomic ops
323 (define_mode_iterator QHI [QI HI])
325 ; HImode or SImode for sign extended fusion ops
326 (define_mode_iterator HSI [HI SI])
328 ; SImode or DImode, even if DImode doesn't fit in GPRs.
329 (define_mode_iterator SDI [SI DI])
331 ; The size of a pointer. Also, the size of the value that a record-condition
332 ; (one with a '.') will compare; and the size used for arithmetic carries.
333 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
335 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
336 ; PTImode is GPR only)
337 (define_mode_iterator TI2 [TI PTI])
339 ; Any hardware-supported floating-point mode
340 (define_mode_iterator FP [
341 (SF "TARGET_HARD_FLOAT
342 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
343 (DF "TARGET_HARD_FLOAT
344 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
345 (TF "!TARGET_IEEEQUAD
346 && TARGET_HARD_FLOAT
347 && (TARGET_FPRS || TARGET_E500_DOUBLE)
348 && TARGET_LONG_DOUBLE_128")
349 (DD "TARGET_DFP")
350 (TD "TARGET_DFP")])
352 ; Any fma capable floating-point mode.
353 (define_mode_iterator FMA_F [
354 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
355 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
356 || VECTOR_UNIT_VSX_P (DFmode)")
357 (V2SF "TARGET_PAIRED_FLOAT")
358 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
359 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
360 ])
362 ; Floating point move iterators to combine binary and decimal moves
363 (define_mode_iterator FMOVE32 [SF SD])
364 (define_mode_iterator FMOVE64 [DF DD])
365 (define_mode_iterator FMOVE64X [DI DF DD])
366 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
367 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
369 ; Iterators for 128 bit types for direct move
370 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
371 (V16QI "")
372 (V8HI "")
373 (V4SI "")
374 (V4SF "")
375 (V2DI "")
376 (V2DF "")
377 (V1TI "")])
379 ; Whether a floating point move is ok, don't allow SD without hardware FP
380 (define_mode_attr fmove_ok [(SF "")
381 (DF "")
382 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
383 (DD "")])
385 ; Convert REAL_VALUE to the appropriate bits
386 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
387 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
388 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
389 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
391 ; Definitions for load to 32-bit fpr register
392 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
393 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
394 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
395 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
397 ; Definitions for store from 32-bit fpr register
398 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
399 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
400 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
401 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
403 ; Definitions for 32-bit fpr direct move
404 ; At present, the decimal modes are not allowed in the traditional altivec
405 ; registers, so restrict the constraints to just the traditional FPRs.
406 (define_mode_attr f32_dm [(SF "wn") (SD "wh")])
408 ; Definitions for 32-bit VSX
409 (define_mode_attr f32_vsx [(SF "ww") (SD "wn")])
411 ; Definitions for 32-bit use of altivec registers
412 (define_mode_attr f32_av [(SF "wu") (SD "wn")])
414 ; Definitions for 64-bit VSX
415 (define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
417 ; Definitions for 64-bit direct move
418 (define_mode_attr f64_dm [(DF "wk") (DD "wh")])
420 ; Definitions for 64-bit use of altivec registers
421 (define_mode_attr f64_av [(DF "wv") (DD "wn")])
423 ; These modes do not fit in integer registers in 32-bit mode.
424 ; but on e500v2, the gpr are 64 bit registers
425 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
427 ; Iterator for reciprocal estimate instructions
428 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
430 ; Iterator for just SF/DF
431 (define_mode_iterator SFDF [SF DF])
433 ; SF/DF suffix for traditional floating instructions
434 (define_mode_attr Ftrad [(SF "s") (DF "")])
436 ; SF/DF suffix for VSX instructions
437 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
439 ; SF/DF constraint for arithmetic on traditional floating point registers
440 (define_mode_attr Ff [(SF "f") (DF "d")])
442 ; SF/DF constraint for arithmetic on VSX registers
443 (define_mode_attr Fv [(SF "wy") (DF "ws")])
445 ; SF/DF constraint for arithmetic on altivec registers
446 (define_mode_attr Fa [(SF "wu") (DF "wv")])
448 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
449 (define_mode_attr Fs [(SF "s") (DF "d")])
451 ; FRE/FRES support
452 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
453 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
455 ; Conditional returns.
456 (define_code_iterator any_return [return simple_return])
457 (define_code_attr return_pred [(return "direct_return ()")
458 (simple_return "1")])
459 (define_code_attr return_str [(return "") (simple_return "simple_")])
461 ; Logical operators.
462 (define_code_iterator iorxor [ior xor])
464 ; Signed/unsigned variants of ops.
465 (define_code_iterator any_extend [sign_extend zero_extend])
466 (define_code_attr u [(sign_extend "") (zero_extend "u")])
467 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
469 ; Various instructions that come in SI and DI forms.
470 ; A generic w/d attribute, for things like cmpw/cmpd.
471 (define_mode_attr wd [(QI "b")
472 (HI "h")
473 (SI "w")
474 (DI "d")
475 (V16QI "b")
476 (V8HI "h")
477 (V4SI "w")
478 (V2DI "d")])
480 ;; How many bits in this mode?
481 (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
483 ; DImode bits
484 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
486 ;; ISEL/ISEL64 target selection
487 (define_mode_attr sel [(SI "") (DI "64")])
489 ;; Bitmask for shift instructions
490 (define_mode_attr hH [(SI "h") (DI "H")])
492 ;; A mode twice the size of the given mode
493 (define_mode_attr dmode [(SI "di") (DI "ti")])
494 (define_mode_attr DMODE [(SI "DI") (DI "TI")])
496 ;; Suffix for reload patterns
497 (define_mode_attr ptrsize [(SI "32bit")
498 (DI "64bit")])
500 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
501 (DI "TARGET_64BIT")])
503 (define_mode_attr mptrsize [(SI "si")
504 (DI "di")])
506 (define_mode_attr ptrload [(SI "lwz")
507 (DI "ld")])
509 (define_mode_attr ptrm [(SI "m")
510 (DI "Y")])
512 (define_mode_attr rreg [(SF "f")
513 (DF "ws")
514 (TF "f")
515 (TD "f")
516 (V4SF "wf")
517 (V2DF "wd")])
519 (define_mode_attr rreg2 [(SF "f")
520 (DF "d")])
522 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
523 (DF "TARGET_FCFID")])
525 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
526 (DF "TARGET_E500_DOUBLE")])
528 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
529 (DF "TARGET_DOUBLE_FLOAT")])
531 ;; Mode iterator for logical operations on 128-bit types
532 (define_mode_iterator BOOL_128 [TI
533 PTI
534 (V16QI "TARGET_ALTIVEC")
535 (V8HI "TARGET_ALTIVEC")
536 (V4SI "TARGET_ALTIVEC")
537 (V4SF "TARGET_ALTIVEC")
538 (V2DI "TARGET_ALTIVEC")
539 (V2DF "TARGET_ALTIVEC")
540 (V1TI "TARGET_ALTIVEC")])
542 ;; For the GPRs we use 3 constraints for register outputs, two that are the
543 ;; same as the output register, and a third where the output register is an
544 ;; early clobber, so we don't have to deal with register overlaps. For the
545 ;; vector types, we prefer to use the vector registers. For TI mode, allow
546 ;; either.
548 ;; Mode attribute for boolean operation register constraints for output
549 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wt,v")
550 (PTI "&r,r,r")
551 (V16QI "wa,v,&?r,?r,?r")
552 (V8HI "wa,v,&?r,?r,?r")
553 (V4SI "wa,v,&?r,?r,?r")
554 (V4SF "wa,v,&?r,?r,?r")
555 (V2DI "wa,v,&?r,?r,?r")
556 (V2DF "wa,v,&?r,?r,?r")
557 (V1TI "wa,v,&?r,?r,?r")])
559 ;; Mode attribute for boolean operation register constraints for operand1
560 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wt,v")
561 (PTI "r,0,r")
562 (V16QI "wa,v,r,0,r")
563 (V8HI "wa,v,r,0,r")
564 (V4SI "wa,v,r,0,r")
565 (V4SF "wa,v,r,0,r")
566 (V2DI "wa,v,r,0,r")
567 (V2DF "wa,v,r,0,r")
568 (V1TI "wa,v,r,0,r")])
570 ;; Mode attribute for boolean operation register constraints for operand2
571 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wt,v")
572 (PTI "r,r,0")
573 (V16QI "wa,v,r,r,0")
574 (V8HI "wa,v,r,r,0")
575 (V4SI "wa,v,r,r,0")
576 (V4SF "wa,v,r,r,0")
577 (V2DI "wa,v,r,r,0")
578 (V2DF "wa,v,r,r,0")
579 (V1TI "wa,v,r,r,0")])
581 ;; Mode attribute for boolean operation register constraints for operand1
582 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
583 ;; is used for operand1 or operand2
584 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wt,v")
585 (PTI "r,0,0")
586 (V16QI "wa,v,r,0,0")
587 (V8HI "wa,v,r,0,0")
588 (V4SI "wa,v,r,0,0")
589 (V4SF "wa,v,r,0,0")
590 (V2DI "wa,v,r,0,0")
591 (V2DF "wa,v,r,0,0")
592 (V1TI "wa,v,r,0,0")])
594 ;; Reload iterator for creating the function to allocate a base register to
595 ;; supplement addressing modes.
596 (define_mode_iterator RELOAD [V16QI V8HI V4SI V2DI V4SF V2DF V1TI
597 SF SD SI DF DD DI TI PTI])
599 \f
600 ;; Start with fixed-point load and store insns. Here we put only the more
601 ;; complex forms. Basic data transfer is done later.
603 (define_insn "zero_extendqi<mode>2"
604 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
605 (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
606 ""
607 "@
608 lbz%U1%X1 %0,%1
609 rlwinm %0,%1,0,0xff"
610 [(set_attr "type" "load,shift")])
612 (define_insn_and_split "*zero_extendqi<mode>2_dot"
613 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
614 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
615 (const_int 0)))
616 (clobber (match_scratch:EXTQI 0 "=r,r"))]
617 "rs6000_gen_cell_microcode"
618 "@
619 andi. %0,%1,0xff
620 #"
621 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
622 [(set (match_dup 0)
623 (zero_extend:EXTQI (match_dup 1)))
624 (set (match_dup 2)
625 (compare:CC (match_dup 0)
626 (const_int 0)))]
627 ""
628 [(set_attr "type" "logical")
629 (set_attr "dot" "yes")
630 (set_attr "length" "4,8")])
632 (define_insn_and_split "*zero_extendqi<mode>2_dot2"
633 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
634 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
635 (const_int 0)))
636 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
637 (zero_extend:EXTQI (match_dup 1)))]
638 "rs6000_gen_cell_microcode"
639 "@
640 andi. %0,%1,0xff
641 #"
642 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
643 [(set (match_dup 0)
644 (zero_extend:EXTQI (match_dup 1)))
645 (set (match_dup 2)
646 (compare:CC (match_dup 0)
647 (const_int 0)))]
648 ""
649 [(set_attr "type" "logical")
650 (set_attr "dot" "yes")
651 (set_attr "length" "4,8")])
654 (define_insn "zero_extendhi<mode>2"
655 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
656 (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
657 ""
658 "@
659 lhz%U1%X1 %0,%1
660 rlwinm %0,%1,0,0xffff"
661 [(set_attr "type" "load,shift")])
663 (define_insn_and_split "*zero_extendhi<mode>2_dot"
664 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
665 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
666 (const_int 0)))
667 (clobber (match_scratch:EXTHI 0 "=r,r"))]
668 "rs6000_gen_cell_microcode"
669 "@
670 andi. %0,%1,0xffff
671 #"
672 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
673 [(set (match_dup 0)
674 (zero_extend:EXTHI (match_dup 1)))
675 (set (match_dup 2)
676 (compare:CC (match_dup 0)
677 (const_int 0)))]
678 ""
679 [(set_attr "type" "logical")
680 (set_attr "dot" "yes")
681 (set_attr "length" "4,8")])
683 (define_insn_and_split "*zero_extendhi<mode>2_dot2"
684 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
685 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
686 (const_int 0)))
687 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
688 (zero_extend:EXTHI (match_dup 1)))]
689 "rs6000_gen_cell_microcode"
690 "@
691 andi. %0,%1,0xffff
692 #"
693 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
694 [(set (match_dup 0)
695 (zero_extend:EXTHI (match_dup 1)))
696 (set (match_dup 2)
697 (compare:CC (match_dup 0)
698 (const_int 0)))]
699 ""
700 [(set_attr "type" "logical")
701 (set_attr "dot" "yes")
702 (set_attr "length" "4,8")])
705 (define_insn "zero_extendsi<mode>2"
706 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
707 (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
708 ""
709 "@
710 lwz%U1%X1 %0,%1
711 rldicl %0,%1,0,32
712 mtvsrwz %x0,%1
713 lfiwzx %0,%y1
714 lxsiwzx %x0,%y1"
715 [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
717 (define_insn_and_split "*zero_extendsi<mode>2_dot"
718 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
719 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
720 (const_int 0)))
721 (clobber (match_scratch:EXTSI 0 "=r,r"))]
722 "rs6000_gen_cell_microcode"
723 "@
724 rldicl. %0,%1,0,32
725 #"
726 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
727 [(set (match_dup 0)
728 (zero_extend:DI (match_dup 1)))
729 (set (match_dup 2)
730 (compare:CC (match_dup 0)
731 (const_int 0)))]
732 ""
733 [(set_attr "type" "shift")
734 (set_attr "dot" "yes")
735 (set_attr "length" "4,8")])
737 (define_insn_and_split "*zero_extendsi<mode>2_dot2"
738 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
739 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
740 (const_int 0)))
741 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
742 (zero_extend:EXTSI (match_dup 1)))]
743 "rs6000_gen_cell_microcode"
744 "@
745 rldicl. %0,%1,0,32
746 #"
747 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
748 [(set (match_dup 0)
749 (zero_extend:EXTSI (match_dup 1)))
750 (set (match_dup 2)
751 (compare:CC (match_dup 0)
752 (const_int 0)))]
753 ""
754 [(set_attr "type" "shift")
755 (set_attr "dot" "yes")
756 (set_attr "length" "4,8")])
759 (define_insn "extendqi<mode>2"
760 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r")
761 (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r")))]
762 ""
763 "extsb %0,%1"
764 [(set_attr "type" "exts")])
766 (define_insn_and_split "*extendqi<mode>2_dot"
767 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
768 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
769 (const_int 0)))
770 (clobber (match_scratch:EXTQI 0 "=r,r"))]
771 "rs6000_gen_cell_microcode"
772 "@
773 extsb. %0,%1
774 #"
775 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
776 [(set (match_dup 0)
777 (sign_extend:EXTQI (match_dup 1)))
778 (set (match_dup 2)
779 (compare:CC (match_dup 0)
780 (const_int 0)))]
781 ""
782 [(set_attr "type" "exts")
783 (set_attr "dot" "yes")
784 (set_attr "length" "4,8")])
786 (define_insn_and_split "*extendqi<mode>2_dot2"
787 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
788 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
789 (const_int 0)))
790 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
791 (sign_extend:EXTQI (match_dup 1)))]
792 "rs6000_gen_cell_microcode"
793 "@
794 extsb. %0,%1
795 #"
796 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
797 [(set (match_dup 0)
798 (sign_extend:EXTQI (match_dup 1)))
799 (set (match_dup 2)
800 (compare:CC (match_dup 0)
801 (const_int 0)))]
802 ""
803 [(set_attr "type" "exts")
804 (set_attr "dot" "yes")
805 (set_attr "length" "4,8")])
808 (define_expand "extendhi<mode>2"
809 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "")
810 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "")))]
811 ""
812 "")
814 (define_insn "*extendhi<mode>2"
815 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
816 (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
817 "rs6000_gen_cell_microcode"
818 "@
819 lha%U1%X1 %0,%1
820 extsh %0,%1"
821 [(set_attr "type" "load,exts")
822 (set_attr "sign_extend" "yes")])
824 (define_insn "*extendhi<mode>2_noload"
825 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r")
826 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r")))]
827 "!rs6000_gen_cell_microcode"
828 "extsh %0,%1"
829 [(set_attr "type" "exts")])
831 (define_insn_and_split "*extendhi<mode>2_dot"
832 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
833 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
834 (const_int 0)))
835 (clobber (match_scratch:EXTHI 0 "=r,r"))]
836 "rs6000_gen_cell_microcode"
837 "@
838 extsh. %0,%1
839 #"
840 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
841 [(set (match_dup 0)
842 (sign_extend:EXTHI (match_dup 1)))
843 (set (match_dup 2)
844 (compare:CC (match_dup 0)
845 (const_int 0)))]
846 ""
847 [(set_attr "type" "exts")
848 (set_attr "dot" "yes")
849 (set_attr "length" "4,8")])
851 (define_insn_and_split "*extendhi<mode>2_dot2"
852 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
853 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
854 (const_int 0)))
855 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
856 (sign_extend:EXTHI (match_dup 1)))]
857 "rs6000_gen_cell_microcode"
858 "@
859 extsh. %0,%1
860 #"
861 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
862 [(set (match_dup 0)
863 (sign_extend:EXTHI (match_dup 1)))
864 (set (match_dup 2)
865 (compare:CC (match_dup 0)
866 (const_int 0)))]
867 ""
868 [(set_attr "type" "exts")
869 (set_attr "dot" "yes")
870 (set_attr "length" "4,8")])
873 (define_insn "extendsi<mode>2"
874 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
875 (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
876 ""
877 "@
878 lwa%U1%X1 %0,%1
879 extsw %0,%1
880 mtvsrwa %x0,%1
881 lfiwax %0,%y1
882 lxsiwax %x0,%y1"
883 [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
884 (set_attr "sign_extend" "yes")])
886 (define_insn_and_split "*extendsi<mode>2_dot"
887 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
888 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
889 (const_int 0)))
890 (clobber (match_scratch:EXTSI 0 "=r,r"))]
891 "rs6000_gen_cell_microcode"
892 "@
893 extsw. %0,%1
894 #"
895 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
896 [(set (match_dup 0)
897 (sign_extend:EXTSI (match_dup 1)))
898 (set (match_dup 2)
899 (compare:CC (match_dup 0)
900 (const_int 0)))]
901 ""
902 [(set_attr "type" "exts")
903 (set_attr "dot" "yes")
904 (set_attr "length" "4,8")])
906 (define_insn_and_split "*extendsi<mode>2_dot2"
907 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
908 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
909 (const_int 0)))
910 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
911 (sign_extend:EXTSI (match_dup 1)))]
912 "rs6000_gen_cell_microcode"
913 "@
914 extsw. %0,%1
915 #"
916 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
917 [(set (match_dup 0)
918 (sign_extend:EXTSI (match_dup 1)))
919 (set (match_dup 2)
920 (compare:CC (match_dup 0)
921 (const_int 0)))]
922 ""
923 [(set_attr "type" "exts")
924 (set_attr "dot" "yes")
925 (set_attr "length" "4,8")])
926 \f
927 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
929 (define_insn "*macchwc"
930 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
931 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
932 (match_operand:SI 2 "gpc_reg_operand" "r")
933 (const_int 16))
934 (sign_extend:SI
935 (match_operand:HI 1 "gpc_reg_operand" "r")))
936 (match_operand:SI 4 "gpc_reg_operand" "0"))
937 (const_int 0)))
938 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
939 (plus:SI (mult:SI (ashiftrt:SI
940 (match_dup 2)
941 (const_int 16))
942 (sign_extend:SI
943 (match_dup 1)))
944 (match_dup 4)))]
945 "TARGET_MULHW"
946 "macchw. %0,%1,%2"
947 [(set_attr "type" "halfmul")])
949 (define_insn "*macchw"
950 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
951 (plus:SI (mult:SI (ashiftrt:SI
952 (match_operand:SI 2 "gpc_reg_operand" "r")
953 (const_int 16))
954 (sign_extend:SI
955 (match_operand:HI 1 "gpc_reg_operand" "r")))
956 (match_operand:SI 3 "gpc_reg_operand" "0")))]
957 "TARGET_MULHW"
958 "macchw %0,%1,%2"
959 [(set_attr "type" "halfmul")])
961 (define_insn "*macchwuc"
962 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
963 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
964 (match_operand:SI 2 "gpc_reg_operand" "r")
965 (const_int 16))
966 (zero_extend:SI
967 (match_operand:HI 1 "gpc_reg_operand" "r")))
968 (match_operand:SI 4 "gpc_reg_operand" "0"))
969 (const_int 0)))
970 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
971 (plus:SI (mult:SI (lshiftrt:SI
972 (match_dup 2)
973 (const_int 16))
974 (zero_extend:SI
975 (match_dup 1)))
976 (match_dup 4)))]
977 "TARGET_MULHW"
978 "macchwu. %0,%1,%2"
979 [(set_attr "type" "halfmul")])
981 (define_insn "*macchwu"
982 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
983 (plus:SI (mult:SI (lshiftrt:SI
984 (match_operand:SI 2 "gpc_reg_operand" "r")
985 (const_int 16))
986 (zero_extend:SI
987 (match_operand:HI 1 "gpc_reg_operand" "r")))
988 (match_operand:SI 3 "gpc_reg_operand" "0")))]
989 "TARGET_MULHW"
990 "macchwu %0,%1,%2"
991 [(set_attr "type" "halfmul")])
993 (define_insn "*machhwc"
994 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
995 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
996 (match_operand:SI 1 "gpc_reg_operand" "%r")
997 (const_int 16))
998 (ashiftrt:SI
999 (match_operand:SI 2 "gpc_reg_operand" "r")
1000 (const_int 16)))
1001 (match_operand:SI 4 "gpc_reg_operand" "0"))
1002 (const_int 0)))
1003 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1004 (plus:SI (mult:SI (ashiftrt:SI
1005 (match_dup 1)
1006 (const_int 16))
1007 (ashiftrt:SI
1008 (match_dup 2)
1009 (const_int 16)))
1010 (match_dup 4)))]
1011 "TARGET_MULHW"
1012 "machhw. %0,%1,%2"
1013 [(set_attr "type" "halfmul")])
1015 (define_insn "*machhw"
1016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1017 (plus:SI (mult:SI (ashiftrt:SI
1018 (match_operand:SI 1 "gpc_reg_operand" "%r")
1019 (const_int 16))
1020 (ashiftrt:SI
1021 (match_operand:SI 2 "gpc_reg_operand" "r")
1022 (const_int 16)))
1023 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1024 "TARGET_MULHW"
1025 "machhw %0,%1,%2"
1026 [(set_attr "type" "halfmul")])
1028 (define_insn "*machhwuc"
1029 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1030 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1031 (match_operand:SI 1 "gpc_reg_operand" "%r")
1032 (const_int 16))
1033 (lshiftrt:SI
1034 (match_operand:SI 2 "gpc_reg_operand" "r")
1035 (const_int 16)))
1036 (match_operand:SI 4 "gpc_reg_operand" "0"))
1037 (const_int 0)))
1038 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1039 (plus:SI (mult:SI (lshiftrt:SI
1040 (match_dup 1)
1041 (const_int 16))
1042 (lshiftrt:SI
1043 (match_dup 2)
1044 (const_int 16)))
1045 (match_dup 4)))]
1046 "TARGET_MULHW"
1047 "machhwu. %0,%1,%2"
1048 [(set_attr "type" "halfmul")])
1050 (define_insn "*machhwu"
1051 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1052 (plus:SI (mult:SI (lshiftrt:SI
1053 (match_operand:SI 1 "gpc_reg_operand" "%r")
1054 (const_int 16))
1055 (lshiftrt:SI
1056 (match_operand:SI 2 "gpc_reg_operand" "r")
1057 (const_int 16)))
1058 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1059 "TARGET_MULHW"
1060 "machhwu %0,%1,%2"
1061 [(set_attr "type" "halfmul")])
1063 (define_insn "*maclhwc"
1064 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1065 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1066 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1067 (sign_extend:SI
1068 (match_operand:HI 2 "gpc_reg_operand" "r")))
1069 (match_operand:SI 4 "gpc_reg_operand" "0"))
1070 (const_int 0)))
1071 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1072 (plus:SI (mult:SI (sign_extend:SI
1073 (match_dup 1))
1074 (sign_extend:SI
1075 (match_dup 2)))
1076 (match_dup 4)))]
1077 "TARGET_MULHW"
1078 "maclhw. %0,%1,%2"
1079 [(set_attr "type" "halfmul")])
1081 (define_insn "*maclhw"
1082 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1083 (plus:SI (mult:SI (sign_extend:SI
1084 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1085 (sign_extend:SI
1086 (match_operand:HI 2 "gpc_reg_operand" "r")))
1087 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1088 "TARGET_MULHW"
1089 "maclhw %0,%1,%2"
1090 [(set_attr "type" "halfmul")])
1092 (define_insn "*maclhwuc"
1093 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1094 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1095 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1096 (zero_extend:SI
1097 (match_operand:HI 2 "gpc_reg_operand" "r")))
1098 (match_operand:SI 4 "gpc_reg_operand" "0"))
1099 (const_int 0)))
1100 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1101 (plus:SI (mult:SI (zero_extend:SI
1102 (match_dup 1))
1103 (zero_extend:SI
1104 (match_dup 2)))
1105 (match_dup 4)))]
1106 "TARGET_MULHW"
1107 "maclhwu. %0,%1,%2"
1108 [(set_attr "type" "halfmul")])
1110 (define_insn "*maclhwu"
1111 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1112 (plus:SI (mult:SI (zero_extend:SI
1113 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1114 (zero_extend:SI
1115 (match_operand:HI 2 "gpc_reg_operand" "r")))
1116 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1117 "TARGET_MULHW"
1118 "maclhwu %0,%1,%2"
1119 [(set_attr "type" "halfmul")])
1121 (define_insn "*nmacchwc"
1122 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1123 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1124 (mult:SI (ashiftrt:SI
1125 (match_operand:SI 2 "gpc_reg_operand" "r")
1126 (const_int 16))
1127 (sign_extend:SI
1128 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1129 (const_int 0)))
1130 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1131 (minus:SI (match_dup 4)
1132 (mult:SI (ashiftrt:SI
1133 (match_dup 2)
1134 (const_int 16))
1135 (sign_extend:SI
1136 (match_dup 1)))))]
1137 "TARGET_MULHW"
1138 "nmacchw. %0,%1,%2"
1139 [(set_attr "type" "halfmul")])
1141 (define_insn "*nmacchw"
1142 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1143 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1144 (mult:SI (ashiftrt:SI
1145 (match_operand:SI 2 "gpc_reg_operand" "r")
1146 (const_int 16))
1147 (sign_extend:SI
1148 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1149 "TARGET_MULHW"
1150 "nmacchw %0,%1,%2"
1151 [(set_attr "type" "halfmul")])
1153 (define_insn "*nmachhwc"
1154 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1155 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1156 (mult:SI (ashiftrt:SI
1157 (match_operand:SI 1 "gpc_reg_operand" "%r")
1158 (const_int 16))
1159 (ashiftrt:SI
1160 (match_operand:SI 2 "gpc_reg_operand" "r")
1161 (const_int 16))))
1162 (const_int 0)))
1163 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1164 (minus:SI (match_dup 4)
1165 (mult:SI (ashiftrt:SI
1166 (match_dup 1)
1167 (const_int 16))
1168 (ashiftrt:SI
1169 (match_dup 2)
1170 (const_int 16)))))]
1171 "TARGET_MULHW"
1172 "nmachhw. %0,%1,%2"
1173 [(set_attr "type" "halfmul")])
1175 (define_insn "*nmachhw"
1176 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1177 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1178 (mult:SI (ashiftrt:SI
1179 (match_operand:SI 1 "gpc_reg_operand" "%r")
1180 (const_int 16))
1181 (ashiftrt:SI
1182 (match_operand:SI 2 "gpc_reg_operand" "r")
1183 (const_int 16)))))]
1184 "TARGET_MULHW"
1185 "nmachhw %0,%1,%2"
1186 [(set_attr "type" "halfmul")])
1188 (define_insn "*nmaclhwc"
1189 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1190 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1191 (mult:SI (sign_extend:SI
1192 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1193 (sign_extend:SI
1194 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1195 (const_int 0)))
1196 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1197 (minus:SI (match_dup 4)
1198 (mult:SI (sign_extend:SI
1199 (match_dup 1))
1200 (sign_extend:SI
1201 (match_dup 2)))))]
1202 "TARGET_MULHW"
1203 "nmaclhw. %0,%1,%2"
1204 [(set_attr "type" "halfmul")])
1206 (define_insn "*nmaclhw"
1207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1208 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1209 (mult:SI (sign_extend:SI
1210 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1211 (sign_extend:SI
1212 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1213 "TARGET_MULHW"
1214 "nmaclhw %0,%1,%2"
1215 [(set_attr "type" "halfmul")])
1217 (define_insn "*mulchwc"
1218 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1219 (compare:CC (mult:SI (ashiftrt:SI
1220 (match_operand:SI 2 "gpc_reg_operand" "r")
1221 (const_int 16))
1222 (sign_extend:SI
1223 (match_operand:HI 1 "gpc_reg_operand" "r")))
1224 (const_int 0)))
1225 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1226 (mult:SI (ashiftrt:SI
1227 (match_dup 2)
1228 (const_int 16))
1229 (sign_extend:SI
1230 (match_dup 1))))]
1231 "TARGET_MULHW"
1232 "mulchw. %0,%1,%2"
1233 [(set_attr "type" "halfmul")])
1235 (define_insn "*mulchw"
1236 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1237 (mult:SI (ashiftrt:SI
1238 (match_operand:SI 2 "gpc_reg_operand" "r")
1239 (const_int 16))
1240 (sign_extend:SI
1241 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1242 "TARGET_MULHW"
1243 "mulchw %0,%1,%2"
1244 [(set_attr "type" "halfmul")])
1246 (define_insn "*mulchwuc"
1247 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1248 (compare:CC (mult:SI (lshiftrt:SI
1249 (match_operand:SI 2 "gpc_reg_operand" "r")
1250 (const_int 16))
1251 (zero_extend:SI
1252 (match_operand:HI 1 "gpc_reg_operand" "r")))
1253 (const_int 0)))
1254 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1255 (mult:SI (lshiftrt:SI
1256 (match_dup 2)
1257 (const_int 16))
1258 (zero_extend:SI
1259 (match_dup 1))))]
1260 "TARGET_MULHW"
1261 "mulchwu. %0,%1,%2"
1262 [(set_attr "type" "halfmul")])
1264 (define_insn "*mulchwu"
1265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1266 (mult:SI (lshiftrt:SI
1267 (match_operand:SI 2 "gpc_reg_operand" "r")
1268 (const_int 16))
1269 (zero_extend:SI
1270 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1271 "TARGET_MULHW"
1272 "mulchwu %0,%1,%2"
1273 [(set_attr "type" "halfmul")])
1275 (define_insn "*mulhhwc"
1276 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1277 (compare:CC (mult:SI (ashiftrt:SI
1278 (match_operand:SI 1 "gpc_reg_operand" "%r")
1279 (const_int 16))
1280 (ashiftrt:SI
1281 (match_operand:SI 2 "gpc_reg_operand" "r")
1282 (const_int 16)))
1283 (const_int 0)))
1284 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1285 (mult:SI (ashiftrt:SI
1286 (match_dup 1)
1287 (const_int 16))
1288 (ashiftrt:SI
1289 (match_dup 2)
1290 (const_int 16))))]
1291 "TARGET_MULHW"
1292 "mulhhw. %0,%1,%2"
1293 [(set_attr "type" "halfmul")])
1295 (define_insn "*mulhhw"
1296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1297 (mult:SI (ashiftrt:SI
1298 (match_operand:SI 1 "gpc_reg_operand" "%r")
1299 (const_int 16))
1300 (ashiftrt:SI
1301 (match_operand:SI 2 "gpc_reg_operand" "r")
1302 (const_int 16))))]
1303 "TARGET_MULHW"
1304 "mulhhw %0,%1,%2"
1305 [(set_attr "type" "halfmul")])
1307 (define_insn "*mulhhwuc"
1308 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1309 (compare:CC (mult:SI (lshiftrt:SI
1310 (match_operand:SI 1 "gpc_reg_operand" "%r")
1311 (const_int 16))
1312 (lshiftrt:SI
1313 (match_operand:SI 2 "gpc_reg_operand" "r")
1314 (const_int 16)))
1315 (const_int 0)))
1316 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1317 (mult:SI (lshiftrt:SI
1318 (match_dup 1)
1319 (const_int 16))
1320 (lshiftrt:SI
1321 (match_dup 2)
1322 (const_int 16))))]
1323 "TARGET_MULHW"
1324 "mulhhwu. %0,%1,%2"
1325 [(set_attr "type" "halfmul")])
1327 (define_insn "*mulhhwu"
1328 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1329 (mult:SI (lshiftrt:SI
1330 (match_operand:SI 1 "gpc_reg_operand" "%r")
1331 (const_int 16))
1332 (lshiftrt:SI
1333 (match_operand:SI 2 "gpc_reg_operand" "r")
1334 (const_int 16))))]
1335 "TARGET_MULHW"
1336 "mulhhwu %0,%1,%2"
1337 [(set_attr "type" "halfmul")])
1339 (define_insn "*mullhwc"
1340 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1341 (compare:CC (mult:SI (sign_extend:SI
1342 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1343 (sign_extend:SI
1344 (match_operand:HI 2 "gpc_reg_operand" "r")))
1345 (const_int 0)))
1346 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1347 (mult:SI (sign_extend:SI
1348 (match_dup 1))
1349 (sign_extend:SI
1350 (match_dup 2))))]
1351 "TARGET_MULHW"
1352 "mullhw. %0,%1,%2"
1353 [(set_attr "type" "halfmul")])
1355 (define_insn "*mullhw"
1356 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1357 (mult:SI (sign_extend:SI
1358 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1359 (sign_extend:SI
1360 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1361 "TARGET_MULHW"
1362 "mullhw %0,%1,%2"
1363 [(set_attr "type" "halfmul")])
1365 (define_insn "*mullhwuc"
1366 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1367 (compare:CC (mult:SI (zero_extend:SI
1368 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1369 (zero_extend:SI
1370 (match_operand:HI 2 "gpc_reg_operand" "r")))
1371 (const_int 0)))
1372 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1373 (mult:SI (zero_extend:SI
1374 (match_dup 1))
1375 (zero_extend:SI
1376 (match_dup 2))))]
1377 "TARGET_MULHW"
1378 "mullhwu. %0,%1,%2"
1379 [(set_attr "type" "halfmul")])
1381 (define_insn "*mullhwu"
1382 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1383 (mult:SI (zero_extend:SI
1384 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1385 (zero_extend:SI
1386 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1387 "TARGET_MULHW"
1388 "mullhwu %0,%1,%2"
1389 [(set_attr "type" "halfmul")])
1390 \f
1391 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1392 (define_insn "dlmzb"
1393 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1394 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1395 (match_operand:SI 2 "gpc_reg_operand" "r")]
1396 UNSPEC_DLMZB_CR))
1397 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1398 (unspec:SI [(match_dup 1)
1399 (match_dup 2)]
1400 UNSPEC_DLMZB))]
1401 "TARGET_DLMZB"
1402 "dlmzb. %0,%1,%2")
1404 (define_expand "strlensi"
1405 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1406 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1407 (match_operand:QI 2 "const_int_operand" "")
1408 (match_operand 3 "const_int_operand" "")]
1409 UNSPEC_DLMZB_STRLEN))
1410 (clobber (match_scratch:CC 4 "=x"))]
1411 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1412 {
1413 rtx result = operands[0];
1414 rtx src = operands[1];
1415 rtx search_char = operands[2];
1416 rtx align = operands[3];
1417 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1418 rtx loop_label, end_label, mem, cr0, cond;
1419 if (search_char != const0_rtx
1420 || GET_CODE (align) != CONST_INT
1421 || INTVAL (align) < 8)
1422 FAIL;
1423 word1 = gen_reg_rtx (SImode);
1424 word2 = gen_reg_rtx (SImode);
1425 scratch_dlmzb = gen_reg_rtx (SImode);
1426 scratch_string = gen_reg_rtx (Pmode);
1427 loop_label = gen_label_rtx ();
1428 end_label = gen_label_rtx ();
1429 addr = force_reg (Pmode, XEXP (src, 0));
1430 emit_move_insn (scratch_string, addr);
1431 emit_label (loop_label);
1432 mem = change_address (src, SImode, scratch_string);
1433 emit_move_insn (word1, mem);
1434 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1435 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1436 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1437 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1438 emit_jump_insn (gen_rtx_SET (VOIDmode,
1439 pc_rtx,
1440 gen_rtx_IF_THEN_ELSE (VOIDmode,
1441 cond,
1442 gen_rtx_LABEL_REF
1443 (VOIDmode,
1444 end_label),
1445 pc_rtx)));
1446 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1447 emit_jump_insn (gen_rtx_SET (VOIDmode,
1448 pc_rtx,
1449 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1450 emit_barrier ();
1451 emit_label (end_label);
1452 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1453 emit_insn (gen_subsi3 (result, scratch_string, addr));
1454 emit_insn (gen_addsi3 (result, result, constm1_rtx));
1455 DONE;
1456 })
1457 \f
1458 ;; Fixed-point arithmetic insns.
1460 (define_expand "add<mode>3"
1461 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1462 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1463 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1464 ""
1465 {
1466 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1467 {
1468 if (non_short_cint_operand (operands[2], DImode))
1469 FAIL;
1470 }
1471 else if (GET_CODE (operands[2]) == CONST_INT
1472 && ! add_operand (operands[2], <MODE>mode))
1473 {
1474 rtx tmp = ((!can_create_pseudo_p ()
1475 || rtx_equal_p (operands[0], operands[1]))
1476 ? operands[0] : gen_reg_rtx (<MODE>mode));
1478 HOST_WIDE_INT val = INTVAL (operands[2]);
1479 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1480 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1482 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1483 FAIL;
1485 /* The ordering here is important for the prolog expander.
1486 When space is allocated from the stack, adding 'low' first may
1487 produce a temporary deallocation (which would be bad). */
1488 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1489 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1490 DONE;
1491 }
1492 })
1494 ;; Discourage ai/addic because of carry but provide it in an alternative
1495 ;; allowing register zero as source.
1496 (define_insn "*add<mode>3_internal1"
1497 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1498 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1499 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1500 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1501 "@
1502 add %0,%1,%2
1503 addi %0,%1,%2
1504 addic %0,%1,%2
1505 addis %0,%1,%v2"
1506 [(set_attr "type" "add")])
1508 (define_insn "addsi3_high"
1509 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1510 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1511 (high:SI (match_operand 2 "" ""))))]
1512 "TARGET_MACHO && !TARGET_64BIT"
1513 "addis %0,%1,ha16(%2)"
1514 [(set_attr "type" "add")])
1516 (define_insn "*add<mode>3_internal2"
1517 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1518 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1519 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1520 (const_int 0)))
1521 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1522 ""
1523 "@
1524 add. %3,%1,%2
1525 addic. %3,%1,%2
1526 #
1527 #"
1528 [(set_attr "type" "add,compare,compare,compare")
1529 (set_attr "dot" "yes")
1530 (set_attr "length" "4,4,8,8")])
1532 (define_split
1533 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1534 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1535 (match_operand:GPR 2 "reg_or_short_operand" ""))
1536 (const_int 0)))
1537 (clobber (match_scratch:GPR 3 ""))]
1538 "reload_completed"
1539 [(set (match_dup 3)
1540 (plus:GPR (match_dup 1)
1541 (match_dup 2)))
1542 (set (match_dup 0)
1543 (compare:CC (match_dup 3)
1544 (const_int 0)))]
1545 "")
1547 (define_insn "*add<mode>3_internal3"
1548 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1549 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1550 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1551 (const_int 0)))
1552 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1553 (plus:P (match_dup 1)
1554 (match_dup 2)))]
1555 ""
1556 "@
1557 add. %0,%1,%2
1558 addic. %0,%1,%2
1559 #
1560 #"
1561 [(set_attr "type" "add,compare,compare,compare")
1562 (set_attr "dot" "yes")
1563 (set_attr "length" "4,4,8,8")])
1565 (define_split
1566 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1567 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1568 (match_operand:P 2 "reg_or_short_operand" ""))
1569 (const_int 0)))
1570 (set (match_operand:P 0 "gpc_reg_operand" "")
1571 (plus:P (match_dup 1) (match_dup 2)))]
1572 "reload_completed"
1573 [(set (match_dup 0)
1574 (plus:P (match_dup 1)
1575 (match_dup 2)))
1576 (set (match_dup 3)
1577 (compare:CC (match_dup 0)
1578 (const_int 0)))]
1579 "")
1581 ;; Split an add that we can't do in one insn into two insns, each of which
1582 ;; does one 16-bit part. This is used by combine. Note that the low-order
1583 ;; add should be last in case the result gets used in an address.
1585 (define_split
1586 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1587 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1588 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1589 ""
1590 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1591 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1592 {
1593 HOST_WIDE_INT val = INTVAL (operands[2]);
1594 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1595 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1597 operands[4] = GEN_INT (low);
1598 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1599 operands[3] = GEN_INT (rest);
1600 else if (can_create_pseudo_p ())
1601 {
1602 operands[3] = gen_reg_rtx (DImode);
1603 emit_move_insn (operands[3], operands[2]);
1604 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1605 DONE;
1606 }
1607 else
1608 FAIL;
1609 })
1611 (define_expand "one_cmpl<mode>2"
1612 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1613 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1614 ""
1615 {
1616 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1617 {
1618 rs6000_split_logical (operands, NOT, false, false, false);
1619 DONE;
1620 }
1621 })
1623 (define_insn "*one_cmpl<mode>2"
1624 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1625 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1626 ""
1627 "not %0,%1")
1629 (define_insn_and_split "*one_cmpl<mode>2_dot"
1630 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1631 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1632 (const_int 0)))
1633 (clobber (match_scratch:GPR 0 "=r,r"))]
1634 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1635 "@
1636 not. %0,%1
1637 #"
1638 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1639 [(set (match_dup 0)
1640 (not:GPR (match_dup 1)))
1641 (set (match_dup 2)
1642 (compare:CC (match_dup 0)
1643 (const_int 0)))]
1644 ""
1645 [(set_attr "type" "logical")
1646 (set_attr "dot" "yes")
1647 (set_attr "length" "4,8")])
1649 (define_insn_and_split "*one_cmpl<mode>2_dot2"
1650 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1651 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1652 (const_int 0)))
1653 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1654 (not:GPR (match_dup 1)))]
1655 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1656 "@
1657 not. %0,%1
1658 #"
1659 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1660 [(set (match_dup 0)
1661 (not:GPR (match_dup 1)))
1662 (set (match_dup 2)
1663 (compare:CC (match_dup 0)
1664 (const_int 0)))]
1665 ""
1666 [(set_attr "type" "logical")
1667 (set_attr "dot" "yes")
1668 (set_attr "length" "4,8")])
1671 (define_expand "sub<mode>3"
1672 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1673 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1674 (match_operand:SDI 2 "gpc_reg_operand" "")))]
1675 ""
1676 {
1677 if (short_cint_operand (operands[1], <MODE>mode)
1678 && !(<MODE>mode == DImode && !TARGET_POWERPC64))
1679 {
1680 emit_insn (gen_subf<mode>3_imm (operands[0], operands[2], operands[1]));
1681 DONE;
1682 }
1683 })
1685 (define_insn "*subf<mode>3"
1686 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1687 (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r")
1688 (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1689 ""
1690 "subf %0,%1,%2"
1691 [(set_attr "type" "add")])
1693 (define_insn_and_split "*subf<mode>3_dot"
1694 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1695 (compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
1696 (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1697 (const_int 0)))
1698 (clobber (match_scratch:GPR 0 "=r,r"))]
1699 "<MODE>mode == Pmode"
1700 "@
1701 subf. %0,%1,%2
1702 #"
1703 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1704 [(set (match_dup 0)
1705 (minus:GPR (match_dup 2)
1706 (match_dup 1)))
1707 (set (match_dup 3)
1708 (compare:CC (match_dup 0)
1709 (const_int 0)))]
1710 ""
1711 [(set_attr "type" "add")
1712 (set_attr "dot" "yes")
1713 (set_attr "length" "4,8")])
1715 (define_insn_and_split "*subf<mode>3_dot2"
1716 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1717 (compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
1718 (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1719 (const_int 0)))
1720 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1721 (minus:GPR (match_dup 2)
1722 (match_dup 1)))]
1723 "<MODE>mode == Pmode"
1724 "@
1725 subf. %0,%1,%2
1726 #"
1727 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1728 [(set (match_dup 0)
1729 (minus:GPR (match_dup 2)
1730 (match_dup 1)))
1731 (set (match_dup 3)
1732 (compare:CC (match_dup 0)
1733 (const_int 0)))]
1734 ""
1735 [(set_attr "type" "add")
1736 (set_attr "dot" "yes")
1737 (set_attr "length" "4,8")])
1739 (define_insn "subf<mode>3_imm"
1740 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1741 (minus:GPR (match_operand:GPR 2 "short_cint_operand" "I")
1742 (match_operand:GPR 1 "gpc_reg_operand" "r")))
1743 (clobber (reg:GPR CA_REGNO))]
1744 ""
1745 "subfic %0,%1,%2"
1746 [(set_attr "type" "add")])
1749 (define_expand "neg<mode>2"
1750 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1751 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1752 ""
1753 "")
1755 (define_insn "*neg<mode>2"
1756 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1757 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1758 ""
1759 "neg %0,%1"
1760 [(set_attr "type" "add")])
1762 (define_insn_and_split "*neg<mode>2_dot"
1763 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1764 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1765 (const_int 0)))
1766 (clobber (match_scratch:GPR 0 "=r,r"))]
1767 "<MODE>mode == Pmode"
1768 "@
1769 neg. %0,%1
1770 #"
1771 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1772 [(set (match_dup 0)
1773 (neg:GPR (match_dup 1)))
1774 (set (match_dup 2)
1775 (compare:CC (match_dup 0)
1776 (const_int 0)))]
1777 ""
1778 [(set_attr "type" "add")
1779 (set_attr "dot" "yes")
1780 (set_attr "length" "4,8")])
1782 (define_insn_and_split "*neg<mode>2_dot2"
1783 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1784 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1785 (const_int 0)))
1786 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1787 (neg:GPR (match_dup 1)))]
1788 "<MODE>mode == Pmode"
1789 "@
1790 neg. %0,%1
1791 #"
1792 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1793 [(set (match_dup 0)
1794 (neg:GPR (match_dup 1)))
1795 (set (match_dup 2)
1796 (compare:CC (match_dup 0)
1797 (const_int 0)))]
1798 ""
1799 [(set_attr "type" "add")
1800 (set_attr "dot" "yes")
1801 (set_attr "length" "4,8")])
1804 (define_insn "clz<mode>2"
1805 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1806 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1807 ""
1808 "cntlz<wd> %0,%1"
1809 [(set_attr "type" "cntlz")])
1811 (define_expand "ctz<mode>2"
1812 [(set (match_dup 2)
1813 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1814 (set (match_dup 3)
1815 (and:GPR (match_dup 1)
1816 (match_dup 2)))
1817 (set (match_dup 4)
1818 (clz:GPR (match_dup 3)))
1819 (parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1820 (minus:GPR (match_dup 5)
1821 (match_dup 4)))
1822 (clobber (reg:GPR CA_REGNO))])]
1823 ""
1824 {
1825 operands[2] = gen_reg_rtx (<MODE>mode);
1826 operands[3] = gen_reg_rtx (<MODE>mode);
1827 operands[4] = gen_reg_rtx (<MODE>mode);
1828 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1829 })
1831 (define_expand "ffs<mode>2"
1832 [(set (match_dup 2)
1833 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1834 (set (match_dup 3)
1835 (and:GPR (match_dup 1)
1836 (match_dup 2)))
1837 (set (match_dup 4)
1838 (clz:GPR (match_dup 3)))
1839 (parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1840 (minus:GPR (match_dup 5)
1841 (match_dup 4)))
1842 (clobber (reg:GPR CA_REGNO))])]
1843 ""
1844 {
1845 operands[2] = gen_reg_rtx (<MODE>mode);
1846 operands[3] = gen_reg_rtx (<MODE>mode);
1847 operands[4] = gen_reg_rtx (<MODE>mode);
1848 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1849 })
1852 (define_expand "popcount<mode>2"
1853 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1854 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1855 "TARGET_POPCNTB || TARGET_POPCNTD"
1856 {
1857 rs6000_emit_popcount (operands[0], operands[1]);
1858 DONE;
1859 })
1861 (define_insn "popcntb<mode>2"
1862 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1863 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1864 UNSPEC_POPCNTB))]
1865 "TARGET_POPCNTB"
1866 "popcntb %0,%1"
1867 [(set_attr "type" "popcnt")])
1869 (define_insn "popcntd<mode>2"
1870 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1871 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1872 "TARGET_POPCNTD"
1873 "popcnt<wd> %0,%1"
1874 [(set_attr "type" "popcnt")])
1877 (define_expand "parity<mode>2"
1878 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1879 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1880 "TARGET_POPCNTB"
1881 {
1882 rs6000_emit_parity (operands[0], operands[1]);
1883 DONE;
1884 })
1886 (define_insn "parity<mode>2_cmpb"
1887 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1888 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
1889 "TARGET_CMPB && TARGET_POPCNTB"
1890 "prty<wd> %0,%1"
1891 [(set_attr "type" "popcnt")])
1894 ;; Since the hardware zeros the upper part of the register, save generating the
1895 ;; AND immediate if we are converting to unsigned
1896 (define_insn "*bswaphi2_extenddi"
1897 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1898 (zero_extend:DI
1899 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1900 "TARGET_POWERPC64"
1901 "lhbrx %0,%y1"
1902 [(set_attr "length" "4")
1903 (set_attr "type" "load")])
1905 (define_insn "*bswaphi2_extendsi"
1906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1907 (zero_extend:SI
1908 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1909 ""
1910 "lhbrx %0,%y1"
1911 [(set_attr "length" "4")
1912 (set_attr "type" "load")])
1914 (define_expand "bswaphi2"
1915 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
1916 (bswap:HI
1917 (match_operand:HI 1 "reg_or_mem_operand" "")))
1918 (clobber (match_scratch:SI 2 ""))])]
1919 ""
1920 {
1921 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1922 operands[1] = force_reg (HImode, operands[1]);
1923 })
1925 (define_insn "bswaphi2_internal"
1926 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
1927 (bswap:HI
1928 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
1929 (clobber (match_scratch:SI 2 "=X,X,&r"))]
1930 ""
1931 "@
1932 lhbrx %0,%y1
1933 sthbrx %1,%y0
1934 #"
1935 [(set_attr "length" "4,4,12")
1936 (set_attr "type" "load,store,*")])
1938 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
1939 ;; correct for -mlittle as well as -mbig.
1940 (define_split
1941 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1942 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
1943 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
1944 "reload_completed"
1945 [(set (match_dup 3)
1946 (zero_extract:SI (match_dup 4)
1947 (const_int 8)
1948 (const_int 16)))
1949 (set (match_dup 2)
1950 (and:SI (ashift:SI (match_dup 4)
1951 (const_int 8))
1952 (const_int 65280))) ;; 0xff00
1953 (set (match_dup 3)
1954 (ior:SI (match_dup 3)
1955 (match_dup 2)))]
1956 "
1957 {
1958 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
1959 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
1960 }")
1962 (define_insn "*bswapsi2_extenddi"
1963 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1964 (zero_extend:DI
1965 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
1966 "TARGET_POWERPC64"
1967 "lwbrx %0,%y1"
1968 [(set_attr "length" "4")
1969 (set_attr "type" "load")])
1971 (define_expand "bswapsi2"
1972 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
1973 (bswap:SI
1974 (match_operand:SI 1 "reg_or_mem_operand" "")))]
1975 ""
1976 {
1977 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1978 operands[1] = force_reg (SImode, operands[1]);
1979 })
1981 (define_insn "*bswapsi2_internal"
1982 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
1983 (bswap:SI
1984 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
1985 ""
1986 "@
1987 lwbrx %0,%y1
1988 stwbrx %1,%y0
1989 #"
1990 [(set_attr "length" "4,4,12")
1991 (set_attr "type" "load,store,*")])
1993 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
1994 ;; zero_extract insns do not change for -mlittle.
1995 (define_split
1996 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1997 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1998 "reload_completed"
1999 [(set (match_dup 0)
2000 (rotate:SI (match_dup 1) (const_int 8)))
2001 (set (zero_extract:SI (match_dup 0)
2002 (const_int 8)
2003 (const_int 0))
2004 (match_dup 1))
2005 (set (zero_extract:SI (match_dup 0)
2006 (const_int 8)
2007 (const_int 16))
2008 (rotate:SI (match_dup 1)
2009 (const_int 16)))]
2010 "")
2012 (define_expand "bswapdi2"
2013 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2014 (bswap:DI
2015 (match_operand:DI 1 "reg_or_mem_operand" "")))
2016 (clobber (match_scratch:DI 2 ""))
2017 (clobber (match_scratch:DI 3 ""))
2018 (clobber (match_scratch:DI 4 ""))])]
2019 ""
2020 {
2021 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2022 operands[1] = force_reg (DImode, operands[1]);
2024 if (!TARGET_POWERPC64)
2025 {
2026 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2027 that uses 64-bit registers needs the same scratch registers as 64-bit
2028 mode. */
2029 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2030 DONE;
2031 }
2032 })
2034 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2035 (define_insn "*bswapdi2_ldbrx"
2036 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2037 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2038 (clobber (match_scratch:DI 2 "=X,X,&r"))
2039 (clobber (match_scratch:DI 3 "=X,X,&r"))
2040 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2041 "TARGET_POWERPC64 && TARGET_LDBRX
2042 && (REG_P (operands[0]) || REG_P (operands[1]))"
2043 "@
2044 ldbrx %0,%y1
2045 stdbrx %1,%y0
2046 #"
2047 [(set_attr "length" "4,4,36")
2048 (set_attr "type" "load,store,*")])
2050 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2051 (define_insn "*bswapdi2_64bit"
2052 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2053 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2054 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2055 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2056 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2057 "TARGET_POWERPC64 && !TARGET_LDBRX
2058 && (REG_P (operands[0]) || REG_P (operands[1]))
2059 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2060 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2061 "#"
2062 [(set_attr "length" "16,12,36")])
2064 (define_split
2065 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2066 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2067 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2068 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2069 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2070 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2071 [(const_int 0)]
2072 "
2073 {
2074 rtx dest = operands[0];
2075 rtx src = operands[1];
2076 rtx op2 = operands[2];
2077 rtx op3 = operands[3];
2078 rtx op4 = operands[4];
2079 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2080 BYTES_BIG_ENDIAN ? 4 : 0);
2081 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2082 BYTES_BIG_ENDIAN ? 4 : 0);
2083 rtx addr1;
2084 rtx addr2;
2085 rtx word_high;
2086 rtx word_low;
2088 addr1 = XEXP (src, 0);
2089 if (GET_CODE (addr1) == PLUS)
2090 {
2091 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2092 if (TARGET_AVOID_XFORM)
2093 {
2094 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2095 addr2 = op2;
2096 }
2097 else
2098 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2099 }
2100 else if (TARGET_AVOID_XFORM)
2101 {
2102 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2103 addr2 = op2;
2104 }
2105 else
2106 {
2107 emit_move_insn (op2, GEN_INT (4));
2108 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2109 }
2111 if (BYTES_BIG_ENDIAN)
2112 {
2113 word_high = change_address (src, SImode, addr1);
2114 word_low = change_address (src, SImode, addr2);
2115 }
2116 else
2117 {
2118 word_high = change_address (src, SImode, addr2);
2119 word_low = change_address (src, SImode, addr1);
2120 }
2122 emit_insn (gen_bswapsi2 (op3_32, word_low));
2123 emit_insn (gen_bswapsi2 (op4_32, word_high));
2124 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2125 emit_insn (gen_iordi3 (dest, dest, op4));
2126 DONE;
2127 }")
2129 (define_split
2130 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2131 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2132 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2133 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2134 (clobber (match_operand:DI 4 "" ""))]
2135 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2136 [(const_int 0)]
2137 "
2138 {
2139 rtx dest = operands[0];
2140 rtx src = operands[1];
2141 rtx op2 = operands[2];
2142 rtx op3 = operands[3];
2143 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2144 BYTES_BIG_ENDIAN ? 4 : 0);
2145 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2146 BYTES_BIG_ENDIAN ? 4 : 0);
2147 rtx addr1;
2148 rtx addr2;
2149 rtx word_high;
2150 rtx word_low;
2152 addr1 = XEXP (dest, 0);
2153 if (GET_CODE (addr1) == PLUS)
2154 {
2155 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2156 if (TARGET_AVOID_XFORM)
2157 {
2158 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2159 addr2 = op2;
2160 }
2161 else
2162 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2163 }
2164 else if (TARGET_AVOID_XFORM)
2165 {
2166 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2167 addr2 = op2;
2168 }
2169 else
2170 {
2171 emit_move_insn (op2, GEN_INT (4));
2172 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2173 }
2175 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2176 if (BYTES_BIG_ENDIAN)
2177 {
2178 word_high = change_address (dest, SImode, addr1);
2179 word_low = change_address (dest, SImode, addr2);
2180 }
2181 else
2182 {
2183 word_high = change_address (dest, SImode, addr2);
2184 word_low = change_address (dest, SImode, addr1);
2185 }
2186 emit_insn (gen_bswapsi2 (word_high, src_si));
2187 emit_insn (gen_bswapsi2 (word_low, op3_si));
2188 DONE;
2189 }")
2191 (define_split
2192 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2193 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2194 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2195 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2196 (clobber (match_operand:DI 4 "" ""))]
2197 "TARGET_POWERPC64 && reload_completed"
2198 [(const_int 0)]
2199 "
2200 {
2201 rtx dest = operands[0];
2202 rtx src = operands[1];
2203 rtx op2 = operands[2];
2204 rtx op3 = operands[3];
2205 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2206 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2207 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2208 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2209 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2211 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2212 emit_insn (gen_bswapsi2 (dest_si, src_si));
2213 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2214 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2215 emit_insn (gen_iordi3 (dest, dest, op3));
2216 DONE;
2217 }")
2219 (define_insn "bswapdi2_32bit"
2220 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2221 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2222 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2223 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2224 "#"
2225 [(set_attr "length" "16,12,36")])
2227 (define_split
2228 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2229 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2230 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2231 "!TARGET_POWERPC64 && reload_completed"
2232 [(const_int 0)]
2233 "
2234 {
2235 rtx dest = operands[0];
2236 rtx src = operands[1];
2237 rtx op2 = operands[2];
2238 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2239 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2240 rtx addr1;
2241 rtx addr2;
2242 rtx word1;
2243 rtx word2;
2245 addr1 = XEXP (src, 0);
2246 if (GET_CODE (addr1) == PLUS)
2247 {
2248 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2249 if (TARGET_AVOID_XFORM)
2250 {
2251 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2252 addr2 = op2;
2253 }
2254 else
2255 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2256 }
2257 else if (TARGET_AVOID_XFORM)
2258 {
2259 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2260 addr2 = op2;
2261 }
2262 else
2263 {
2264 emit_move_insn (op2, GEN_INT (4));
2265 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2266 }
2268 word1 = change_address (src, SImode, addr1);
2269 word2 = change_address (src, SImode, addr2);
2271 emit_insn (gen_bswapsi2 (dest2, word1));
2272 emit_insn (gen_bswapsi2 (dest1, word2));
2273 DONE;
2274 }")
2276 (define_split
2277 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2278 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2279 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2280 "!TARGET_POWERPC64 && reload_completed"
2281 [(const_int 0)]
2282 "
2283 {
2284 rtx dest = operands[0];
2285 rtx src = operands[1];
2286 rtx op2 = operands[2];
2287 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2288 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2289 rtx addr1;
2290 rtx addr2;
2291 rtx word1;
2292 rtx word2;
2294 addr1 = XEXP (dest, 0);
2295 if (GET_CODE (addr1) == PLUS)
2296 {
2297 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2298 if (TARGET_AVOID_XFORM)
2299 {
2300 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2301 addr2 = op2;
2302 }
2303 else
2304 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2305 }
2306 else if (TARGET_AVOID_XFORM)
2307 {
2308 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2309 addr2 = op2;
2310 }
2311 else
2312 {
2313 emit_move_insn (op2, GEN_INT (4));
2314 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2315 }
2317 word1 = change_address (dest, SImode, addr1);
2318 word2 = change_address (dest, SImode, addr2);
2320 emit_insn (gen_bswapsi2 (word2, src1));
2321 emit_insn (gen_bswapsi2 (word1, src2));
2322 DONE;
2323 }")
2325 (define_split
2326 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2327 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2328 (clobber (match_operand:SI 2 "" ""))]
2329 "!TARGET_POWERPC64 && reload_completed"
2330 [(const_int 0)]
2331 "
2332 {
2333 rtx dest = operands[0];
2334 rtx src = operands[1];
2335 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2336 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2337 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2338 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2340 emit_insn (gen_bswapsi2 (dest1, src2));
2341 emit_insn (gen_bswapsi2 (dest2, src1));
2342 DONE;
2343 }")
2346 (define_insn "mul<mode>3"
2347 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2348 (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2349 (match_operand:GPR 2 "reg_or_short_operand" "r,I")))]
2350 ""
2351 "@
2352 mull<wd> %0,%1,%2
2353 mulli %0,%1,%2"
2354 [(set_attr "type" "mul")
2355 (set (attr "size")
2356 (cond [(match_operand:GPR 2 "s8bit_cint_operand" "")
2357 (const_string "8")
2358 (match_operand:GPR 2 "short_cint_operand" "")
2359 (const_string "16")]
2360 (const_string "<bits>")))])
2362 (define_insn_and_split "*mul<mode>3_dot"
2363 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2364 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2365 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2366 (const_int 0)))
2367 (clobber (match_scratch:GPR 0 "=r,r"))]
2368 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2369 "@
2370 mull<wd>. %0,%1,%2
2371 #"
2372 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2373 [(set (match_dup 0)
2374 (mult:GPR (match_dup 1)
2375 (match_dup 2)))
2376 (set (match_dup 3)
2377 (compare:CC (match_dup 0)
2378 (const_int 0)))]
2379 ""
2380 [(set_attr "type" "mul")
2381 (set_attr "size" "<bits>")
2382 (set_attr "dot" "yes")
2383 (set_attr "length" "4,8")])
2385 (define_insn_and_split "*mul<mode>3_dot2"
2386 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2387 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2388 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2389 (const_int 0)))
2390 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2391 (mult:GPR (match_dup 1)
2392 (match_dup 2)))]
2393 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2394 "@
2395 mull<wd>. %0,%1,%2
2396 #"
2397 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2398 [(set (match_dup 0)
2399 (mult:GPR (match_dup 1)
2400 (match_dup 2)))
2401 (set (match_dup 3)
2402 (compare:CC (match_dup 0)
2403 (const_int 0)))]
2404 ""
2405 [(set_attr "type" "mul")
2406 (set_attr "size" "<bits>")
2407 (set_attr "dot" "yes")
2408 (set_attr "length" "4,8")])
2411 (define_expand "<su>mul<mode>3_highpart"
2412 [(set (match_operand:GPR 0 "gpc_reg_operand")
2413 (subreg:GPR
2414 (mult:<DMODE> (any_extend:<DMODE>
2415 (match_operand:GPR 1 "gpc_reg_operand"))
2416 (any_extend:<DMODE>
2417 (match_operand:GPR 2 "gpc_reg_operand")))
2418 0))]
2419 ""
2420 {
2421 if (<MODE>mode == SImode && TARGET_POWERPC64)
2422 {
2423 emit_insn (gen_<su>mulsi3_highpart_64 (operands[0], operands[1],
2424 operands[2]));
2425 DONE;
2426 }
2428 if (!WORDS_BIG_ENDIAN)
2429 {
2430 emit_insn (gen_<su>mul<mode>3_highpart_le (operands[0], operands[1],
2431 operands[2]));
2432 DONE;
2433 }
2434 })
2436 (define_insn "*<su>mul<mode>3_highpart"
2437 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2438 (subreg:GPR
2439 (mult:<DMODE> (any_extend:<DMODE>
2440 (match_operand:GPR 1 "gpc_reg_operand" "r"))
2441 (any_extend:<DMODE>
2442 (match_operand:GPR 2 "gpc_reg_operand" "r")))
2443 0))]
2444 "WORDS_BIG_ENDIAN && !(<MODE>mode == SImode && TARGET_POWERPC64)"
2445 "mulh<wd><u> %0,%1,%2"
2446 [(set_attr "type" "mul")
2447 (set_attr "size" "<bits>")])
2449 (define_insn "<su>mulsi3_highpart_le"
2450 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2451 (subreg:SI
2452 (mult:DI (any_extend:DI
2453 (match_operand:SI 1 "gpc_reg_operand" "r"))
2454 (any_extend:DI
2455 (match_operand:SI 2 "gpc_reg_operand" "r")))
2456 4))]
2457 "!WORDS_BIG_ENDIAN && !TARGET_POWERPC64"
2458 "mulhw<u> %0,%1,%2"
2459 [(set_attr "type" "mul")])
2461 (define_insn "<su>muldi3_highpart_le"
2462 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2463 (subreg:DI
2464 (mult:TI (any_extend:TI
2465 (match_operand:DI 1 "gpc_reg_operand" "r"))
2466 (any_extend:TI
2467 (match_operand:DI 2 "gpc_reg_operand" "r")))
2468 8))]
2469 "!WORDS_BIG_ENDIAN && TARGET_POWERPC64"
2470 "mulhd<u> %0,%1,%2"
2471 [(set_attr "type" "mul")
2472 (set_attr "size" "64")])
2474 (define_insn "<su>mulsi3_highpart_64"
2475 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2476 (truncate:SI
2477 (lshiftrt:DI
2478 (mult:DI (any_extend:DI
2479 (match_operand:SI 1 "gpc_reg_operand" "r"))
2480 (any_extend:DI
2481 (match_operand:SI 2 "gpc_reg_operand" "r")))
2482 (const_int 32))))]
2483 "TARGET_POWERPC64"
2484 "mulhw<u> %0,%1,%2"
2485 [(set_attr "type" "mul")])
2487 (define_expand "<u>mul<mode><dmode>3"
2488 [(set (match_operand:<DMODE> 0 "gpc_reg_operand")
2489 (mult:<DMODE> (any_extend:<DMODE>
2490 (match_operand:GPR 1 "gpc_reg_operand"))
2491 (any_extend:<DMODE>
2492 (match_operand:GPR 2 "gpc_reg_operand"))))]
2493 "!(<MODE>mode == SImode && TARGET_POWERPC64)"
2494 {
2495 rtx l = gen_reg_rtx (<MODE>mode);
2496 rtx h = gen_reg_rtx (<MODE>mode);
2497 emit_insn (gen_mul<mode>3 (l, operands[1], operands[2]));
2498 emit_insn (gen_<su>mul<mode>3_highpart (h, operands[1], operands[2]));
2499 emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l);
2500 emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h);
2501 DONE;
2502 })
2505 (define_insn "udiv<mode>3"
2506 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2507 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2508 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2509 ""
2510 "div<wd>u %0,%1,%2"
2511 [(set_attr "type" "div")
2512 (set_attr "size" "<bits>")])
2515 ;; For powers of two we can do sra[wd]i/addze for divide and then adjust for
2516 ;; modulus. If it isn't a power of two, force operands into register and do
2517 ;; a normal divide.
2518 (define_expand "div<mode>3"
2519 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2520 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2521 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2522 ""
2523 {
2524 if (CONST_INT_P (operands[2])
2525 && INTVAL (operands[2]) > 0
2526 && exact_log2 (INTVAL (operands[2])) >= 0)
2527 {
2528 emit_insn (gen_div<mode>3_sra (operands[0], operands[1], operands[2]));
2529 DONE;
2530 }
2532 operands[2] = force_reg (<MODE>mode, operands[2]);
2533 })
2535 (define_insn "*div<mode>3"
2536 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2537 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2538 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2539 ""
2540 "div<wd> %0,%1,%2"
2541 [(set_attr "type" "div")
2542 (set_attr "size" "<bits>")])
2544 (define_insn "div<mode>3_sra"
2545 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2546 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2547 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))
2548 (clobber (reg:GPR CA_REGNO))]
2549 ""
2550 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2551 [(set_attr "type" "two")
2552 (set_attr "length" "8")])
2554 (define_insn_and_split "*div<mode>3_sra_dot"
2555 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2556 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2557 (match_operand:GPR 2 "exact_log2_cint_operand" "N,N"))
2558 (const_int 0)))
2559 (clobber (match_scratch:GPR 0 "=r,r"))
2560 (clobber (reg:GPR CA_REGNO))]
2561 "<MODE>mode == Pmode"
2562 "@
2563 sra<wd>i %0,%1,%p2\;addze. %0,%0
2564 #"
2565 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2566 [(parallel [(set (match_dup 0)
2567 (div:GPR (match_dup 1)
2568 (match_dup 2)))
2569 (clobber (reg:GPR CA_REGNO))])
2570 (set (match_dup 3)
2571 (compare:CC (match_dup 0)
2572 (const_int 0)))]
2573 ""
2574 [(set_attr "type" "two")
2575 (set_attr "length" "8,12")
2576 (set_attr "cell_micro" "not")])
2578 (define_insn_and_split "*div<mode>3_sra_dot2"
2579 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2580 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2581 (match_operand:GPR 2 "exact_log2_cint_operand" "N,N"))
2582 (const_int 0)))
2583 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2584 (div:GPR (match_dup 1)
2585 (match_dup 2)))
2586 (clobber (reg:GPR CA_REGNO))]
2587 "<MODE>mode == Pmode"
2588 "@
2589 sra<wd>i %0,%1,%p2\;addze. %0,%0
2590 #"
2591 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2592 [(parallel [(set (match_dup 0)
2593 (div:GPR (match_dup 1)
2594 (match_dup 2)))
2595 (clobber (reg:GPR CA_REGNO))])
2596 (set (match_dup 3)
2597 (compare:CC (match_dup 0)
2598 (const_int 0)))]
2599 ""
2600 [(set_attr "type" "two")
2601 (set_attr "length" "8,12")
2602 (set_attr "cell_micro" "not")])
2604 (define_expand "mod<mode>3"
2605 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2606 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2607 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2608 ""
2609 {
2610 int i;
2611 rtx temp1;
2612 rtx temp2;
2614 if (GET_CODE (operands[2]) != CONST_INT
2615 || INTVAL (operands[2]) <= 0
2616 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2617 FAIL;
2619 temp1 = gen_reg_rtx (<MODE>mode);
2620 temp2 = gen_reg_rtx (<MODE>mode);
2622 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2623 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2624 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2625 DONE;
2626 })
2627 \f
2628 ;; Logical instructions
2629 ;; The logical instructions are mostly combined by using match_operator,
2630 ;; but the plain AND insns are somewhat different because there is no
2631 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2632 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2634 (define_expand "and<mode>3"
2635 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2636 (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2637 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2638 ""
2639 {
2640 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2641 {
2642 rs6000_split_logical (operands, AND, false, false, false);
2643 DONE;
2644 }
2646 if (logical_const_operand (operands[2], <MODE>mode)
2647 && !any_mask_operand (operands[2], <MODE>mode))
2648 {
2649 if (rs6000_gen_cell_microcode)
2650 {
2651 emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
2652 DONE;
2653 }
2654 else
2655 operands[2] = force_reg (<MODE>mode, operands[2]);
2656 }
2658 if ((<MODE>mode == DImode && !and64_2_operand (operands[2], <MODE>mode))
2659 || (<MODE>mode != DImode && !and_operand (operands[2], <MODE>mode)))
2660 operands[2] = force_reg (<MODE>mode, operands[2]);
2661 })
2664 (define_insn "and<mode>3_imm"
2665 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2666 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
2667 (match_operand:GPR 2 "logical_const_operand" "n")))
2668 (clobber (match_scratch:CC 3 "=x"))]
2669 "rs6000_gen_cell_microcode
2670 && !any_mask_operand (operands[2], <MODE>mode)"
2671 "andi%e2. %0,%1,%u2"
2672 [(set_attr "type" "logical")
2673 (set_attr "dot" "yes")])
2675 (define_insn_and_split "*and<mode>3_imm_dot"
2676 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2677 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2678 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2679 (const_int 0)))
2680 (clobber (match_scratch:GPR 0 "=r,r"))
2681 (clobber (match_scratch:CC 4 "=X,x"))]
2682 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2683 && rs6000_gen_cell_microcode
2684 && !any_mask_operand (operands[2], <MODE>mode)"
2685 "@
2686 andi%e2. %0,%1,%u2
2687 #"
2688 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2689 [(parallel [(set (match_dup 0)
2690 (and:GPR (match_dup 1)
2691 (match_dup 2)))
2692 (clobber (match_dup 4))])
2693 (set (match_dup 3)
2694 (compare:CC (match_dup 0)
2695 (const_int 0)))]
2696 ""
2697 [(set_attr "type" "logical")
2698 (set_attr "dot" "yes")
2699 (set_attr "length" "4,8")])
2701 (define_insn_and_split "*and<mode>3_imm_dot2"
2702 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2703 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2704 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2705 (const_int 0)))
2706 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2707 (and:GPR (match_dup 1)
2708 (match_dup 2)))
2709 (clobber (match_scratch:CC 4 "=X,x"))]
2710 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2711 && rs6000_gen_cell_microcode
2712 && !any_mask_operand (operands[2], <MODE>mode)"
2713 "@
2714 andi%e2. %0,%1,%u2
2715 #"
2716 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2717 [(parallel [(set (match_dup 0)
2718 (and:GPR (match_dup 1)
2719 (match_dup 2)))
2720 (clobber (match_dup 4))])
2721 (set (match_dup 3)
2722 (compare:CC (match_dup 0)
2723 (const_int 0)))]
2724 ""
2725 [(set_attr "type" "logical")
2726 (set_attr "dot" "yes")
2727 (set_attr "length" "4,8")])
2729 (define_insn_and_split "*and<mode>3_imm_mask_dot"
2730 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2731 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2732 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2733 (const_int 0)))
2734 (clobber (match_scratch:GPR 0 "=r,r"))]
2735 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2736 && rs6000_gen_cell_microcode
2737 && any_mask_operand (operands[2], <MODE>mode)"
2738 "@
2739 andi%e2. %0,%1,%u2
2740 #"
2741 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2742 [(set (match_dup 0)
2743 (and:GPR (match_dup 1)
2744 (match_dup 2)))
2745 (set (match_dup 3)
2746 (compare:CC (match_dup 0)
2747 (const_int 0)))]
2748 ""
2749 [(set_attr "type" "logical")
2750 (set_attr "dot" "yes")
2751 (set_attr "length" "4,8")])
2753 (define_insn_and_split "*and<mode>3_imm_mask_dot2"
2754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2755 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2756 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2757 (const_int 0)))
2758 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2759 (and:GPR (match_dup 1)
2760 (match_dup 2)))]
2761 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2762 && rs6000_gen_cell_microcode
2763 && any_mask_operand (operands[2], <MODE>mode)"
2764 "@
2765 andi%e2. %0,%1,%u2
2766 #"
2767 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2768 [(set (match_dup 0)
2769 (and:GPR (match_dup 1)
2770 (match_dup 2)))
2771 (set (match_dup 3)
2772 (compare:CC (match_dup 0)
2773 (const_int 0)))]
2774 ""
2775 [(set_attr "type" "logical")
2776 (set_attr "dot" "yes")
2777 (set_attr "length" "4,8")])
2780 (define_insn "*and<mode>3_mask"
2781 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2782 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2783 (match_operand:GPR 2 "any_mask_operand" "S,T")))]
2784 ""
2785 "@
2786 rldic%B2 %0,%1,0,%S2
2787 rlwinm %0,%1,0,%m2,%M2"
2788 [(set_attr "type" "shift")])
2790 (define_insn_and_split "*and<mode>3_mask_dot"
2791 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2792 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2793 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2794 (const_int 0)))
2795 (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
2796 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2797 && rs6000_gen_cell_microcode
2798 && !logical_const_operand (operands[2], <MODE>mode)"
2799 "@
2800 rldic%B2. %0,%1,0,%S2
2801 rlwinm. %0,%1,0,%m2,%M2
2802 #
2803 #"
2804 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2805 [(set (match_dup 0)
2806 (and:GPR (match_dup 1)
2807 (match_dup 2)))
2808 (set (match_dup 3)
2809 (compare:CC (match_dup 0)
2810 (const_int 0)))]
2811 ""
2812 [(set_attr "type" "shift")
2813 (set_attr "dot" "yes")
2814 (set_attr "length" "4,4,8,8")])
2816 (define_insn_and_split "*and<mode>3_mask_dot2"
2817 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2818 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2819 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2820 (const_int 0)))
2821 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
2822 (and:GPR (match_dup 1)
2823 (match_dup 2)))]
2824 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2825 && rs6000_gen_cell_microcode
2826 && !logical_const_operand (operands[2], <MODE>mode)"
2827 "@
2828 rldic%B2. %0,%1,0,%S2
2829 rlwinm. %0,%1,0,%m2,%M2
2830 #
2831 #"
2832 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2833 [(set (match_dup 0)
2834 (and:GPR (match_dup 1)
2835 (match_dup 2)))
2836 (set (match_dup 3)
2837 (compare:CC (match_dup 0)
2838 (const_int 0)))]
2839 ""
2840 [(set_attr "type" "shift")
2841 (set_attr "dot" "yes")
2842 (set_attr "length" "4,4,8,8")])
2846 (define_insn "andsi3_internal0_nomc"
2847 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2848 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2849 (match_operand:SI 2 "and_operand" "?r,T")))]
2850 "!rs6000_gen_cell_microcode"
2851 "@
2852 and %0,%1,%2
2853 rlwinm %0,%1,0,%m2,%M2"
2854 [(set_attr "type" "logical,shift")])
2857 ;; Handle the PowerPC64 rlwinm corner case
2859 (define_insn_and_split "*andsi3_internal6"
2860 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2861 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2862 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2863 "TARGET_POWERPC64"
2864 "#"
2865 "TARGET_POWERPC64"
2866 [(set (match_dup 0)
2867 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2868 (match_dup 4)))
2869 (set (match_dup 0)
2870 (rotate:SI (match_dup 0) (match_dup 5)))]
2871 "
2872 {
2873 int mb = extract_MB (operands[2]);
2874 int me = extract_ME (operands[2]);
2875 operands[3] = GEN_INT (me + 1);
2876 operands[5] = GEN_INT (32 - (me + 1));
2877 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2878 }"
2879 [(set_attr "length" "8")])
2882 (define_expand "<code><mode>3"
2883 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2884 (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2885 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2886 ""
2887 {
2888 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2889 {
2890 rs6000_split_logical (operands, <CODE>, false, false, false);
2891 DONE;
2892 }
2894 if (non_logical_cint_operand (operands[2], <MODE>mode))
2895 {
2896 rtx tmp = ((!can_create_pseudo_p ()
2897 || rtx_equal_p (operands[0], operands[1]))
2898 ? operands[0] : gen_reg_rtx (<MODE>mode));
2900 HOST_WIDE_INT value = INTVAL (operands[2]);
2901 HOST_WIDE_INT lo = value & 0xffff;
2902 HOST_WIDE_INT hi = value - lo;
2904 emit_insn (gen_<code><mode>3 (tmp, operands[1], GEN_INT (hi)));
2905 emit_insn (gen_<code><mode>3 (operands[0], tmp, GEN_INT (lo)));
2906 DONE;
2907 }
2909 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
2910 operands[2] = force_reg (<MODE>mode, operands[2]);
2911 })
2913 (define_split
2914 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2915 (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2916 (match_operand:GPR 2 "non_logical_cint_operand" "")))]
2917 ""
2918 [(set (match_dup 3)
2919 (iorxor:GPR (match_dup 1)
2920 (match_dup 4)))
2921 (set (match_dup 0)
2922 (iorxor:GPR (match_dup 3)
2923 (match_dup 5)))]
2924 {
2925 operands[3] = ((!can_create_pseudo_p ()
2926 || rtx_equal_p (operands[0], operands[1]))
2927 ? operands[0] : gen_reg_rtx (<MODE>mode));
2929 HOST_WIDE_INT value = INTVAL (operands[2]);
2930 HOST_WIDE_INT lo = value & 0xffff;
2931 HOST_WIDE_INT hi = value - lo;
2933 operands[4] = GEN_INT (hi);
2934 operands[5] = GEN_INT (lo);
2935 })
2937 (define_insn "*bool<mode>3_imm"
2938 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2939 (match_operator:GPR 3 "boolean_or_operator"
2940 [(match_operand:GPR 1 "gpc_reg_operand" "%r")
2941 (match_operand:GPR 2 "logical_const_operand" "n")]))]
2942 ""
2943 "%q3i%e2 %0,%1,%u2"
2944 [(set_attr "type" "logical")])
2946 (define_insn "*bool<mode>3"
2947 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2948 (match_operator:GPR 3 "boolean_operator"
2949 [(match_operand:GPR 1 "gpc_reg_operand" "r")
2950 (match_operand:GPR 2 "gpc_reg_operand" "r")]))]
2951 ""
2952 "%q3 %0,%1,%2"
2953 [(set_attr "type" "logical")])
2955 (define_insn_and_split "*bool<mode>3_dot"
2956 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2957 (compare:CC (match_operator:GPR 3 "boolean_operator"
2958 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
2959 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
2960 (const_int 0)))
2961 (clobber (match_scratch:GPR 0 "=r,r"))]
2962 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2963 "@
2964 %q3. %0,%1,%2
2965 #"
2966 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
2967 [(set (match_dup 0)
2968 (match_dup 3))
2969 (set (match_dup 4)
2970 (compare:CC (match_dup 0)
2971 (const_int 0)))]
2972 ""
2973 [(set_attr "type" "logical")
2974 (set_attr "dot" "yes")
2975 (set_attr "length" "4,8")])
2977 (define_insn_and_split "*bool<mode>3_dot2"
2978 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2979 (compare:CC (match_operator:GPR 3 "boolean_operator"
2980 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
2981 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
2982 (const_int 0)))
2983 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2984 (match_dup 3))]
2985 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2986 "@
2987 %q3. %0,%1,%2
2988 #"
2989 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
2990 [(set (match_dup 0)
2991 (match_dup 3))
2992 (set (match_dup 4)
2993 (compare:CC (match_dup 0)
2994 (const_int 0)))]
2995 ""
2996 [(set_attr "type" "logical")
2997 (set_attr "dot" "yes")
2998 (set_attr "length" "4,8")])
3001 (define_insn "*boolc<mode>3"
3002 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3003 (match_operator:GPR 3 "boolean_operator"
3004 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))
3005 (match_operand:GPR 1 "gpc_reg_operand" "r")]))]
3006 ""
3007 "%q3 %0,%1,%2"
3008 [(set_attr "type" "logical")])
3010 (define_insn_and_split "*boolc<mode>3_dot"
3011 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3012 (compare:CC (match_operator:GPR 3 "boolean_operator"
3013 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3014 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3015 (const_int 0)))
3016 (clobber (match_scratch:GPR 0 "=r,r"))]
3017 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3018 "@
3019 %q3. %0,%1,%2
3020 #"
3021 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3022 [(set (match_dup 0)
3023 (match_dup 3))
3024 (set (match_dup 4)
3025 (compare:CC (match_dup 0)
3026 (const_int 0)))]
3027 ""
3028 [(set_attr "type" "logical")
3029 (set_attr "dot" "yes")
3030 (set_attr "length" "4,8")])
3032 (define_insn_and_split "*boolc<mode>3_dot2"
3033 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3034 (compare:CC (match_operator:GPR 3 "boolean_operator"
3035 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3036 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3037 (const_int 0)))
3038 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3039 (match_dup 3))]
3040 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3041 "@
3042 %q3. %0,%1,%2
3043 #"
3044 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3045 [(set (match_dup 0)
3046 (match_dup 3))
3047 (set (match_dup 4)
3048 (compare:CC (match_dup 0)
3049 (const_int 0)))]
3050 ""
3051 [(set_attr "type" "logical")
3052 (set_attr "dot" "yes")
3053 (set_attr "length" "4,8")])
3056 (define_insn "*boolcc<mode>3"
3057 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3058 (match_operator:GPR 3 "boolean_operator"
3059 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
3060 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))]))]
3061 ""
3062 "%q3 %0,%1,%2"
3063 [(set_attr "type" "logical")])
3065 (define_insn_and_split "*boolcc<mode>3_dot"
3066 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3067 (compare:CC (match_operator:GPR 3 "boolean_operator"
3068 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3069 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3070 (const_int 0)))
3071 (clobber (match_scratch:GPR 0 "=r,r"))]
3072 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3073 "@
3074 %q3. %0,%1,%2
3075 #"
3076 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3077 [(set (match_dup 0)
3078 (match_dup 3))
3079 (set (match_dup 4)
3080 (compare:CC (match_dup 0)
3081 (const_int 0)))]
3082 ""
3083 [(set_attr "type" "logical")
3084 (set_attr "dot" "yes")
3085 (set_attr "length" "4,8")])
3087 (define_insn_and_split "*boolcc<mode>3_dot2"
3088 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3089 (compare:CC (match_operator:GPR 3 "boolean_operator"
3090 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3091 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3092 (const_int 0)))
3093 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3094 (match_dup 3))]
3095 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3096 "@
3097 %q3. %0,%1,%2
3098 #"
3099 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3100 [(set (match_dup 0)
3101 (match_dup 3))
3102 (set (match_dup 4)
3103 (compare:CC (match_dup 0)
3104 (const_int 0)))]
3105 ""
3106 [(set_attr "type" "logical")
3107 (set_attr "dot" "yes")
3108 (set_attr "length" "4,8")])
3111 ;; TODO: Should have dots of this as well.
3112 (define_insn "*eqv<mode>3"
3113 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3114 (not:GPR (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3115 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
3116 ""
3117 "eqv %0,%1,%2"
3118 [(set_attr "type" "logical")])
3119 \f
3120 ;; Rotate and shift insns, in all their variants. These support shifts,
3121 ;; field inserts and extracts, and various combinations thereof.
3122 (define_expand "insv"
3123 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3124 (match_operand:SI 1 "const_int_operand" "")
3125 (match_operand:SI 2 "const_int_operand" ""))
3126 (match_operand 3 "gpc_reg_operand" ""))]
3127 ""
3128 "
3129 {
3130 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3131 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3132 compiler if the address of the structure is taken later. Likewise, do
3133 not handle invalid E500 subregs. */
3134 if (GET_CODE (operands[0]) == SUBREG
3135 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3136 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3137 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3138 FAIL;
3140 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3141 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3142 operands[3]));
3143 else
3144 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3145 operands[3]));
3146 DONE;
3147 }")
3149 (define_insn "insvsi_internal"
3150 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3151 (match_operand:SI 1 "const_int_operand" "i")
3152 (match_operand:SI 2 "const_int_operand" "i"))
3153 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3154 ""
3155 "*
3156 {
3157 int start = INTVAL (operands[2]) & 31;
3158 int size = INTVAL (operands[1]) & 31;
3160 operands[4] = GEN_INT (32 - start - size);
3161 operands[1] = GEN_INT (start + size - 1);
3162 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3163 }"
3164 [(set_attr "type" "insert")])
3166 (define_insn "*insvsi_internal1"
3167 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3168 (match_operand:SI 1 "const_int_operand" "i")
3169 (match_operand:SI 2 "const_int_operand" "i"))
3170 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3171 (match_operand:SI 4 "const_int_operand" "i")))]
3172 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3173 "*
3174 {
3175 int shift = INTVAL (operands[4]) & 31;
3176 int start = INTVAL (operands[2]) & 31;
3177 int size = INTVAL (operands[1]) & 31;
3179 operands[4] = GEN_INT (shift - start - size);
3180 operands[1] = GEN_INT (start + size - 1);
3181 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3182 }"
3183 [(set_attr "type" "insert")])
3185 (define_insn "*insvsi_internal2"
3186 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3187 (match_operand:SI 1 "const_int_operand" "i")
3188 (match_operand:SI 2 "const_int_operand" "i"))
3189 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3190 (match_operand:SI 4 "const_int_operand" "i")))]
3191 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3192 "*
3193 {
3194 int shift = INTVAL (operands[4]) & 31;
3195 int start = INTVAL (operands[2]) & 31;
3196 int size = INTVAL (operands[1]) & 31;
3198 operands[4] = GEN_INT (32 - shift - start - size);
3199 operands[1] = GEN_INT (start + size - 1);
3200 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3201 }"
3202 [(set_attr "type" "insert")])
3204 (define_insn "*insvsi_internal3"
3205 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3206 (match_operand:SI 1 "const_int_operand" "i")
3207 (match_operand:SI 2 "const_int_operand" "i"))
3208 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3209 (match_operand:SI 4 "const_int_operand" "i")))]
3210 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3211 "*
3212 {
3213 int shift = INTVAL (operands[4]) & 31;
3214 int start = INTVAL (operands[2]) & 31;
3215 int size = INTVAL (operands[1]) & 31;
3217 operands[4] = GEN_INT (32 - shift - start - size);
3218 operands[1] = GEN_INT (start + size - 1);
3219 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3220 }"
3221 [(set_attr "type" "insert")])
3223 (define_insn "*insvsi_internal4"
3224 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3225 (match_operand:SI 1 "const_int_operand" "i")
3226 (match_operand:SI 2 "const_int_operand" "i"))
3227 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3228 (match_operand:SI 4 "const_int_operand" "i")
3229 (match_operand:SI 5 "const_int_operand" "i")))]
3230 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3231 "*
3232 {
3233 int extract_start = INTVAL (operands[5]) & 31;
3234 int extract_size = INTVAL (operands[4]) & 31;
3235 int insert_start = INTVAL (operands[2]) & 31;
3236 int insert_size = INTVAL (operands[1]) & 31;
3238 /* Align extract field with insert field */
3239 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3240 operands[1] = GEN_INT (insert_start + insert_size - 1);
3241 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3242 }"
3243 [(set_attr "type" "insert")])
3245 ;; combine patterns for rlwimi
3246 (define_insn "*insvsi_internal5"
3247 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3248 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3249 (match_operand:SI 1 "mask_operand" "i"))
3250 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3251 (match_operand:SI 2 "const_int_operand" "i"))
3252 (match_operand:SI 5 "mask_operand" "i"))))]
3253 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3254 "*
3255 {
3256 int me = extract_ME(operands[5]);
3257 int mb = extract_MB(operands[5]);
3258 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3259 operands[2] = GEN_INT(mb);
3260 operands[1] = GEN_INT(me);
3261 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3262 }"
3263 [(set_attr "type" "insert")])
3265 (define_insn "*insvsi_internal6"
3266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3267 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3268 (match_operand:SI 2 "const_int_operand" "i"))
3269 (match_operand:SI 5 "mask_operand" "i"))
3270 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3271 (match_operand:SI 1 "mask_operand" "i"))))]
3272 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3273 "*
3274 {
3275 int me = extract_ME(operands[5]);
3276 int mb = extract_MB(operands[5]);
3277 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3278 operands[2] = GEN_INT(mb);
3279 operands[1] = GEN_INT(me);
3280 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3281 }"
3282 [(set_attr "type" "insert")])
3284 (define_insn "insvdi_internal"
3285 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3286 (match_operand:SI 1 "const_int_operand" "i")
3287 (match_operand:SI 2 "const_int_operand" "i"))
3288 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3289 "TARGET_POWERPC64"
3290 "*
3291 {
3292 int start = INTVAL (operands[2]) & 63;
3293 int size = INTVAL (operands[1]) & 63;
3295 operands[1] = GEN_INT (64 - start - size);
3296 return \"rldimi %0,%3,%H1,%H2\";
3297 }"
3298 [(set_attr "type" "insert")
3299 (set_attr "size" "64")])
3301 (define_insn "*insvdi_internal2"
3302 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3303 (match_operand:SI 1 "const_int_operand" "i")
3304 (match_operand:SI 2 "const_int_operand" "i"))
3305 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3306 (match_operand:SI 4 "const_int_operand" "i")))]
3307 "TARGET_POWERPC64
3308 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3309 "*
3310 {
3311 int shift = INTVAL (operands[4]) & 63;
3312 int start = (INTVAL (operands[2]) & 63) - 32;
3313 int size = INTVAL (operands[1]) & 63;
3315 operands[4] = GEN_INT (64 - shift - start - size);
3316 operands[2] = GEN_INT (start);
3317 operands[1] = GEN_INT (start + size - 1);
3318 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3319 }")
3321 (define_insn "*insvdi_internal3"
3322 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3323 (match_operand:SI 1 "const_int_operand" "i")
3324 (match_operand:SI 2 "const_int_operand" "i"))
3325 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3326 (match_operand:SI 4 "const_int_operand" "i")))]
3327 "TARGET_POWERPC64
3328 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3329 "*
3330 {
3331 int shift = INTVAL (operands[4]) & 63;
3332 int start = (INTVAL (operands[2]) & 63) - 32;
3333 int size = INTVAL (operands[1]) & 63;
3335 operands[4] = GEN_INT (64 - shift - start - size);
3336 operands[2] = GEN_INT (start);
3337 operands[1] = GEN_INT (start + size - 1);
3338 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3339 }")
3341 (define_expand "extzv"
3342 [(set (match_operand 0 "gpc_reg_operand" "")
3343 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3344 (match_operand:SI 2 "const_int_operand" "")
3345 (match_operand:SI 3 "const_int_operand" "")))]
3346 ""
3347 "
3348 {
3349 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3350 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3351 compiler if the address of the structure is taken later. */
3352 if (GET_CODE (operands[0]) == SUBREG
3353 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3354 FAIL;
3356 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3357 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3358 operands[3]));
3359 else
3360 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3361 operands[3]));
3362 DONE;
3363 }")
3365 (define_insn "extzvsi_internal"
3366 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3367 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3368 (match_operand:SI 2 "const_int_operand" "i")
3369 (match_operand:SI 3 "const_int_operand" "i")))]
3370 ""
3371 "*
3372 {
3373 int start = INTVAL (operands[3]) & 31;
3374 int size = INTVAL (operands[2]) & 31;
3376 if (start + size >= 32)
3377 operands[3] = const0_rtx;
3378 else
3379 operands[3] = GEN_INT (start + size);
3380 return \"rlwinm %0,%1,%3,%s2,31\";
3381 }"
3382 [(set_attr "type" "shift")])
3384 (define_insn "*extzvsi_internal1"
3385 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3386 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3387 (match_operand:SI 2 "const_int_operand" "i,i")
3388 (match_operand:SI 3 "const_int_operand" "i,i"))
3389 (const_int 0)))
3390 (clobber (match_scratch:SI 4 "=r,r"))]
3391 ""
3392 "*
3393 {
3394 int start = INTVAL (operands[3]) & 31;
3395 int size = INTVAL (operands[2]) & 31;
3397 /* Force split for non-cc0 compare. */
3398 if (which_alternative == 1)
3399 return \"#\";
3401 /* If the bit-field being tested fits in the upper or lower half of a
3402 word, it is possible to use andiu. or andil. to test it. This is
3403 useful because the condition register set-use delay is smaller for
3404 andi[ul]. than for rlinm. This doesn't work when the starting bit
3405 position is 0 because the LT and GT bits may be set wrong. */
3407 if ((start > 0 && start + size <= 16) || start >= 16)
3408 {
3409 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3410 - (1 << (16 - (start & 15) - size))));
3411 if (start < 16)
3412 return \"andis. %4,%1,%3\";
3413 else
3414 return \"andi. %4,%1,%3\";
3415 }
3417 if (start + size >= 32)
3418 operands[3] = const0_rtx;
3419 else
3420 operands[3] = GEN_INT (start + size);
3421 return \"rlwinm. %4,%1,%3,%s2,31\";
3422 }"
3423 [(set_attr "type" "shift")
3424 (set_attr "dot" "yes")
3425 (set_attr "length" "4,8")])
3427 (define_split
3428 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3429 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3430 (match_operand:SI 2 "const_int_operand" "")
3431 (match_operand:SI 3 "const_int_operand" ""))
3432 (const_int 0)))
3433 (clobber (match_scratch:SI 4 ""))]
3434 "reload_completed"
3435 [(set (match_dup 4)
3436 (zero_extract:SI (match_dup 1) (match_dup 2)
3437 (match_dup 3)))
3438 (set (match_dup 0)
3439 (compare:CC (match_dup 4)
3440 (const_int 0)))]
3441 "")
3443 (define_insn "*extzvsi_internal2"
3444 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3445 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3446 (match_operand:SI 2 "const_int_operand" "i,i")
3447 (match_operand:SI 3 "const_int_operand" "i,i"))
3448 (const_int 0)))
3449 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3450 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3451 ""
3452 "*
3453 {
3454 int start = INTVAL (operands[3]) & 31;
3455 int size = INTVAL (operands[2]) & 31;
3457 /* Force split for non-cc0 compare. */
3458 if (which_alternative == 1)
3459 return \"#\";
3461 /* Since we are using the output value, we can't ignore any need for
3462 a shift. The bit-field must end at the LSB. */
3463 if (start >= 16 && start + size == 32)
3464 {
3465 operands[3] = GEN_INT ((1 << size) - 1);
3466 return \"andi. %0,%1,%3\";
3467 }
3469 if (start + size >= 32)
3470 operands[3] = const0_rtx;
3471 else
3472 operands[3] = GEN_INT (start + size);
3473 return \"rlwinm. %0,%1,%3,%s2,31\";
3474 }"
3475 [(set_attr "type" "shift")
3476 (set_attr "dot" "yes")
3477 (set_attr "length" "4,8")])
3479 (define_split
3480 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3481 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3482 (match_operand:SI 2 "const_int_operand" "")
3483 (match_operand:SI 3 "const_int_operand" ""))
3484 (const_int 0)))
3485 (set (match_operand:SI 0 "gpc_reg_operand" "")
3486 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3487 "reload_completed"
3488 [(set (match_dup 0)
3489 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3490 (set (match_dup 4)
3491 (compare:CC (match_dup 0)
3492 (const_int 0)))]
3493 "")
3495 (define_insn "extzvdi_internal"
3496 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3497 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3498 (match_operand:SI 2 "const_int_operand" "i")
3499 (match_operand:SI 3 "const_int_operand" "i")))]
3500 "TARGET_POWERPC64"
3501 "*
3502 {
3503 int start = INTVAL (operands[3]) & 63;
3504 int size = INTVAL (operands[2]) & 63;
3506 if (start + size >= 64)
3507 operands[3] = const0_rtx;
3508 else
3509 operands[3] = GEN_INT (start + size);
3510 operands[2] = GEN_INT (64 - size);
3511 return \"rldicl %0,%1,%3,%2\";
3512 }"
3513 [(set_attr "type" "shift")])
3515 (define_insn "*extzvdi_internal1"
3516 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3517 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3518 (match_operand:SI 2 "const_int_operand" "i")
3519 (match_operand:SI 3 "const_int_operand" "i"))
3520 (const_int 0)))
3521 (clobber (match_scratch:DI 4 "=r"))]
3522 "TARGET_64BIT && rs6000_gen_cell_microcode"
3523 "*
3524 {
3525 int start = INTVAL (operands[3]) & 63;
3526 int size = INTVAL (operands[2]) & 63;
3528 if (start + size >= 64)
3529 operands[3] = const0_rtx;
3530 else
3531 operands[3] = GEN_INT (start + size);
3532 operands[2] = GEN_INT (64 - size);
3533 return \"rldicl. %4,%1,%3,%2\";
3534 }"
3535 [(set_attr "type" "shift")
3536 (set_attr "dot" "yes")])
3538 (define_insn "*extzvdi_internal2"
3539 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3540 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3541 (match_operand:SI 2 "const_int_operand" "i")
3542 (match_operand:SI 3 "const_int_operand" "i"))
3543 (const_int 0)))
3544 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3545 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3546 "TARGET_64BIT && rs6000_gen_cell_microcode"
3547 "*
3548 {
3549 int start = INTVAL (operands[3]) & 63;
3550 int size = INTVAL (operands[2]) & 63;
3552 if (start + size >= 64)
3553 operands[3] = const0_rtx;
3554 else
3555 operands[3] = GEN_INT (start + size);
3556 operands[2] = GEN_INT (64 - size);
3557 return \"rldicl. %0,%1,%3,%2\";
3558 }"
3559 [(set_attr "type" "shift")
3560 (set_attr "dot" "yes")])
3563 (define_insn "rotl<mode>3"
3564 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3565 (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3566 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
3567 ""
3568 "rotl<wd>%I2 %0,%1,%<hH>2"
3569 [(set_attr "type" "shift")
3570 (set_attr "maybe_var_shift" "yes")])
3572 (define_insn "*rotlsi3_64"
3573 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3574 (zero_extend:DI
3575 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3576 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
3577 "TARGET_POWERPC64"
3578 "rotlw%I2 %0,%1,%h2"
3579 [(set_attr "type" "shift")
3580 (set_attr "maybe_var_shift" "yes")])
3582 (define_insn_and_split "*rotl<mode>3_dot"
3583 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3584 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3585 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3586 (const_int 0)))
3587 (clobber (match_scratch:GPR 0 "=r,r"))]
3588 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3589 "@
3590 rotl<wd>%I2. %0,%1,%<hH>2
3591 #"
3592 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3593 [(set (match_dup 0)
3594 (rotate:GPR (match_dup 1)
3595 (match_dup 2)))
3596 (set (match_dup 3)
3597 (compare:CC (match_dup 0)
3598 (const_int 0)))]
3599 ""
3600 [(set_attr "type" "shift")
3601 (set_attr "maybe_var_shift" "yes")
3602 (set_attr "dot" "yes")
3603 (set_attr "length" "4,8")])
3605 (define_insn_and_split "*rotl<mode>3_dot2"
3606 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3607 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3608 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3609 (const_int 0)))
3610 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3611 (rotate:GPR (match_dup 1)
3612 (match_dup 2)))]
3613 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3614 "@
3615 rotl<wd>%I2. %0,%1,%<hH>2
3616 #"
3617 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3618 [(set (match_dup 0)
3619 (rotate:GPR (match_dup 1)
3620 (match_dup 2)))
3621 (set (match_dup 3)
3622 (compare:CC (match_dup 0)
3623 (const_int 0)))]
3624 ""
3625 [(set_attr "type" "shift")
3626 (set_attr "maybe_var_shift" "yes")
3627 (set_attr "dot" "yes")
3628 (set_attr "length" "4,8")])
3631 (define_insn "*rotlsi3_internal4"
3632 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3633 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3634 (match_operand:SI 2 "reg_or_cint_operand" "rn"))
3635 (match_operand:SI 3 "mask_operand" "n")))]
3636 ""
3637 "rlw%I2nm %0,%1,%h2,%m3,%M3"
3638 [(set_attr "type" "shift")
3639 (set_attr "maybe_var_shift" "yes")])
3641 (define_insn "*rotlsi3_internal5"
3642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3643 (compare:CC (and:SI
3644 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3645 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3646 (match_operand:SI 3 "mask_operand" "n,n"))
3647 (const_int 0)))
3648 (clobber (match_scratch:SI 4 "=r,r"))]
3649 ""
3650 "@
3651 rlw%I2nm. %4,%1,%h2,%m3,%M3
3652 #"
3653 [(set_attr "type" "shift")
3654 (set_attr "maybe_var_shift" "yes")
3655 (set_attr "dot" "yes")
3656 (set_attr "length" "4,8")])
3658 (define_split
3659 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3660 (compare:CC (and:SI
3661 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3662 (match_operand:SI 2 "reg_or_cint_operand" ""))
3663 (match_operand:SI 3 "mask_operand" ""))
3664 (const_int 0)))
3665 (clobber (match_scratch:SI 4 ""))]
3666 "reload_completed"
3667 [(set (match_dup 4)
3668 (and:SI (rotate:SI (match_dup 1)
3669 (match_dup 2))
3670 (match_dup 3)))
3671 (set (match_dup 0)
3672 (compare:CC (match_dup 4)
3673 (const_int 0)))]
3674 "")
3676 (define_insn "*rotlsi3_internal6"
3677 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3678 (compare:CC (and:SI
3679 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3680 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3681 (match_operand:SI 3 "mask_operand" "n,n"))
3682 (const_int 0)))
3683 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3684 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3685 ""
3686 "@
3687 rlw%I2nm. %0,%1,%h2,%m3,%M3
3688 #"
3689 [(set_attr "type" "shift")
3690 (set_attr "maybe_var_shift" "yes")
3691 (set_attr "dot" "yes")
3692 (set_attr "length" "4,8")])
3694 (define_split
3695 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3696 (compare:CC (and:SI
3697 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3698 (match_operand:SI 2 "reg_or_cint_operand" ""))
3699 (match_operand:SI 3 "mask_operand" ""))
3700 (const_int 0)))
3701 (set (match_operand:SI 0 "gpc_reg_operand" "")
3702 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3703 "reload_completed"
3704 [(set (match_dup 0)
3705 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3706 (set (match_dup 4)
3707 (compare:CC (match_dup 0)
3708 (const_int 0)))]
3709 "")
3711 (define_insn "*rotlsi3_internal7le"
3712 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3713 (zero_extend:SI
3714 (subreg:QI
3715 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3716 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3717 "!BYTES_BIG_ENDIAN"
3718 "rlw%I2nm %0,%1,%h2,0xff"
3719 [(set (attr "cell_micro")
3720 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3721 (const_string "not")
3722 (const_string "always")))
3723 (set_attr "type" "shift")])
3725 (define_insn "*rotlsi3_internal7be"
3726 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3727 (zero_extend:SI
3728 (subreg:QI
3729 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3730 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3731 "BYTES_BIG_ENDIAN"
3732 "rlw%I2nm %0,%1,%h2,0xff"
3733 [(set (attr "cell_micro")
3734 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3735 (const_string "not")
3736 (const_string "always")))
3737 (set_attr "type" "shift")])
3739 (define_insn "*rotlsi3_internal8le"
3740 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3741 (compare:CC (zero_extend:SI
3742 (subreg:QI
3743 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3744 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3745 (const_int 0)))
3746 (clobber (match_scratch:SI 3 "=r,r"))]
3747 "!BYTES_BIG_ENDIAN"
3748 "@
3749 rlw%I2nm. %3,%1,%h2,0xff
3750 #"
3751 [(set_attr "type" "shift")
3752 (set_attr "maybe_var_shift" "yes")
3753 (set_attr "dot" "yes")
3754 (set_attr "length" "4,8")])
3756 (define_insn "*rotlsi3_internal8be"
3757 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3758 (compare:CC (zero_extend:SI
3759 (subreg:QI
3760 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3761 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3762 (const_int 0)))
3763 (clobber (match_scratch:SI 3 "=r,r"))]
3764 "BYTES_BIG_ENDIAN"
3765 "@
3766 rlw%I2nm. %3,%1,%h2,0xff
3767 #"
3768 [(set_attr "type" "shift")
3769 (set_attr "maybe_var_shift" "yes")
3770 (set_attr "dot" "yes")
3771 (set_attr "length" "4,8")])
3773 (define_split
3774 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3775 (compare:CC (zero_extend:SI
3776 (subreg:QI
3777 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3778 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3779 (const_int 0)))
3780 (clobber (match_scratch:SI 3 ""))]
3781 "!BYTES_BIG_ENDIAN && reload_completed"
3782 [(set (match_dup 3)
3783 (zero_extend:SI (subreg:QI
3784 (rotate:SI (match_dup 1)
3785 (match_dup 2)) 0)))
3786 (set (match_dup 0)
3787 (compare:CC (match_dup 3)
3788 (const_int 0)))]
3789 "")
3791 (define_split
3792 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3793 (compare:CC (zero_extend:SI
3794 (subreg:QI
3795 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3796 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3797 (const_int 0)))
3798 (clobber (match_scratch:SI 3 ""))]
3799 "BYTES_BIG_ENDIAN && reload_completed"
3800 [(set (match_dup 3)
3801 (zero_extend:SI (subreg:QI
3802 (rotate:SI (match_dup 1)
3803 (match_dup 2)) 3)))
3804 (set (match_dup 0)
3805 (compare:CC (match_dup 3)
3806 (const_int 0)))]
3807 "")
3809 (define_insn "*rotlsi3_internal9le"
3810 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3811 (compare:CC (zero_extend:SI
3812 (subreg:QI
3813 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3814 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3815 (const_int 0)))
3816 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3817 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3818 "!BYTES_BIG_ENDIAN"
3819 "@
3820 rlw%I2nm. %0,%1,%h2,0xff
3821 #"
3822 [(set_attr "type" "shift")
3823 (set_attr "maybe_var_shift" "yes")
3824 (set_attr "dot" "yes")
3825 (set_attr "length" "4,8")])
3827 (define_insn "*rotlsi3_internal9be"
3828 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3829 (compare:CC (zero_extend:SI
3830 (subreg:QI
3831 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3832 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3833 (const_int 0)))
3834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3835 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3836 "BYTES_BIG_ENDIAN"
3837 "@
3838 rlw%I2nm. %0,%1,%h2,0xff
3839 #"
3840 [(set_attr "type" "shift")
3841 (set_attr "maybe_var_shift" "yes")
3842 (set_attr "dot" "yes")
3843 (set_attr "length" "4,8")])
3845 (define_split
3846 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3847 (compare:CC (zero_extend:SI
3848 (subreg:QI
3849 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3850 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3851 (const_int 0)))
3852 (set (match_operand:SI 0 "gpc_reg_operand" "")
3853 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3854 "!BYTES_BIG_ENDIAN && reload_completed"
3855 [(set (match_dup 0)
3856 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3857 (set (match_dup 3)
3858 (compare:CC (match_dup 0)
3859 (const_int 0)))]
3860 "")
3862 (define_split
3863 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3864 (compare:CC (zero_extend:SI
3865 (subreg:QI
3866 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3867 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3868 (const_int 0)))
3869 (set (match_operand:SI 0 "gpc_reg_operand" "")
3870 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3871 "BYTES_BIG_ENDIAN && reload_completed"
3872 [(set (match_dup 0)
3873 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
3874 (set (match_dup 3)
3875 (compare:CC (match_dup 0)
3876 (const_int 0)))]
3877 "")
3879 (define_insn "*rotlsi3_internal10le"
3880 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3881 (zero_extend:SI
3882 (subreg:HI
3883 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3884 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 0)))]
3885 "!BYTES_BIG_ENDIAN"
3886 "rlw%I2nm %0,%1,%h2,0xffff"
3887 [(set_attr "type" "shift")
3888 (set_attr "maybe_var_shift" "yes")])
3890 (define_insn "*rotlsi3_internal10be"
3891 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3892 (zero_extend:SI
3893 (subreg:HI
3894 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3895 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 2)))]
3896 "BYTES_BIG_ENDIAN"
3897 "rlw%I2nm %0,%1,%h2,0xffff"
3898 [(set_attr "type" "shift")
3899 (set_attr "maybe_var_shift" "yes")])
3901 (define_insn "*rotlsi3_internal11le"
3902 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3903 (compare:CC (zero_extend:SI
3904 (subreg:HI
3905 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3906 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3907 (const_int 0)))
3908 (clobber (match_scratch:SI 3 "=r,r"))]
3909 "!BYTES_BIG_ENDIAN"
3910 "@
3911 rlw%I2nm. %3,%1,%h2,0xffff
3912 #"
3913 [(set_attr "type" "shift")
3914 (set_attr "maybe_var_shift" "yes")
3915 (set_attr "dot" "yes")
3916 (set_attr "length" "4,8")])
3918 (define_insn "*rotlsi3_internal11be"
3919 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3920 (compare:CC (zero_extend:SI
3921 (subreg:HI
3922 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3923 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
3924 (const_int 0)))
3925 (clobber (match_scratch:SI 3 "=r,r"))]
3926 "BYTES_BIG_ENDIAN"
3927 "@
3928 rlw%I2nm. %3,%1,%h2,0xffff
3929 #"
3930 [(set_attr "type" "shift")
3931 (set_attr "maybe_var_shift" "yes")
3932 (set_attr "dot" "yes")
3933 (set_attr "length" "4,8")])
3935 (define_split
3936 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3937 (compare:CC (zero_extend:SI
3938 (subreg:HI
3939 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3940 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3941 (const_int 0)))
3942 (clobber (match_scratch:SI 3 ""))]
3943 "!BYTES_BIG_ENDIAN && reload_completed"
3944 [(set (match_dup 3)
3945 (zero_extend:SI (subreg:HI
3946 (rotate:SI (match_dup 1)
3947 (match_dup 2)) 0)))
3948 (set (match_dup 0)
3949 (compare:CC (match_dup 3)
3950 (const_int 0)))]
3951 "")
3953 (define_split
3954 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3955 (compare:CC (zero_extend:SI
3956 (subreg:HI
3957 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3958 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
3959 (const_int 0)))
3960 (clobber (match_scratch:SI 3 ""))]
3961 "BYTES_BIG_ENDIAN && reload_completed"
3962 [(set (match_dup 3)
3963 (zero_extend:SI (subreg:HI
3964 (rotate:SI (match_dup 1)
3965 (match_dup 2)) 2)))
3966 (set (match_dup 0)
3967 (compare:CC (match_dup 3)
3968 (const_int 0)))]
3969 "")
3971 (define_insn "*rotlsi3_internal12le"
3972 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3973 (compare:CC (zero_extend:SI
3974 (subreg:HI
3975 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3976 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3977 (const_int 0)))
3978 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3979 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3980 "!BYTES_BIG_ENDIAN"
3981 "@
3982 rlw%I2nm. %0,%1,%h2,0xffff
3983 #"
3984 [(set_attr "type" "shift")
3985 (set_attr "maybe_var_shift" "yes")
3986 (set_attr "dot" "yes")
3987 (set_attr "length" "4,8")])
3989 (define_insn "*rotlsi3_internal12be"
3990 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3991 (compare:CC (zero_extend:SI
3992 (subreg:HI
3993 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3994 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
3995 (const_int 0)))
3996 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3997 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
3998 "BYTES_BIG_ENDIAN"
3999 "@
4000 rlw%I2nm. %0,%1,%h2,0xffff
4001 #"
4002 [(set_attr "type" "shift")
4003 (set_attr "maybe_var_shift" "yes")
4004 (set_attr "dot" "yes")
4005 (set_attr "length" "4,8")])
4007 (define_split
4008 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4009 (compare:CC (zero_extend:SI
4010 (subreg:HI
4011 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4012 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4013 (const_int 0)))
4014 (set (match_operand:SI 0 "gpc_reg_operand" "")
4015 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4016 "!BYTES_BIG_ENDIAN && reload_completed"
4017 [(set (match_dup 0)
4018 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4019 (set (match_dup 3)
4020 (compare:CC (match_dup 0)
4021 (const_int 0)))]
4022 "")
4024 (define_split
4025 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4026 (compare:CC (zero_extend:SI
4027 (subreg:HI
4028 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4029 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4030 (const_int 0)))
4031 (set (match_operand:SI 0 "gpc_reg_operand" "")
4032 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4033 "BYTES_BIG_ENDIAN && reload_completed"
4034 [(set (match_dup 0)
4035 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4036 (set (match_dup 3)
4037 (compare:CC (match_dup 0)
4038 (const_int 0)))]
4039 "")
4042 (define_insn "ashl<mode>3"
4043 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4044 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4045 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4046 ""
4047 "sl<wd>%I2 %0,%1,%<hH>2"
4048 [(set_attr "type" "shift")
4049 (set_attr "maybe_var_shift" "yes")])
4051 (define_insn "*ashlsi3_64"
4052 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4053 (zero_extend:DI
4054 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4055 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4056 "TARGET_POWERPC64"
4057 "slw%I2 %0,%1,%h2"
4058 [(set_attr "type" "shift")
4059 (set_attr "maybe_var_shift" "yes")])
4061 (define_insn_and_split "*ashl<mode>3_dot"
4062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4063 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4064 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4065 (const_int 0)))
4066 (clobber (match_scratch:GPR 0 "=r,r"))]
4067 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4068 "@
4069 sl<wd>%I2. %0,%1,%<hH>2
4070 #"
4071 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4072 [(set (match_dup 0)
4073 (ashift:GPR (match_dup 1)
4074 (match_dup 2)))
4075 (set (match_dup 3)
4076 (compare:CC (match_dup 0)
4077 (const_int 0)))]
4078 ""
4079 [(set_attr "type" "shift")
4080 (set_attr "maybe_var_shift" "yes")
4081 (set_attr "dot" "yes")
4082 (set_attr "length" "4,8")])
4084 (define_insn_and_split "*ashl<mode>3_dot2"
4085 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4086 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4087 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4088 (const_int 0)))
4089 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4090 (ashift:GPR (match_dup 1)
4091 (match_dup 2)))]
4092 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4093 "@
4094 sl<wd>%I2. %0,%1,%<hH>2
4095 #"
4096 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4097 [(set (match_dup 0)
4098 (ashift:GPR (match_dup 1)
4099 (match_dup 2)))
4100 (set (match_dup 3)
4101 (compare:CC (match_dup 0)
4102 (const_int 0)))]
4103 ""
4104 [(set_attr "type" "shift")
4105 (set_attr "maybe_var_shift" "yes")
4106 (set_attr "dot" "yes")
4107 (set_attr "length" "4,8")])
4110 (define_insn "rlwinm"
4111 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4112 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4113 (match_operand:SI 2 "const_int_operand" "i"))
4114 (match_operand:SI 3 "mask_operand" "n")))]
4115 "includes_lshift_p (operands[2], operands[3])"
4116 "rlwinm %0,%1,%h2,%m3,%M3"
4117 [(set_attr "type" "shift")])
4119 (define_insn ""
4120 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4121 (compare:CC
4122 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4123 (match_operand:SI 2 "const_int_operand" "i,i"))
4124 (match_operand:SI 3 "mask_operand" "n,n"))
4125 (const_int 0)))
4126 (clobber (match_scratch:SI 4 "=r,r"))]
4127 "includes_lshift_p (operands[2], operands[3])"
4128 "@
4129 rlwinm. %4,%1,%h2,%m3,%M3
4130 #"
4131 [(set_attr "type" "shift")
4132 (set_attr "dot" "yes")
4133 (set_attr "length" "4,8")])
4135 (define_split
4136 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4137 (compare:CC
4138 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4139 (match_operand:SI 2 "const_int_operand" ""))
4140 (match_operand:SI 3 "mask_operand" ""))
4141 (const_int 0)))
4142 (clobber (match_scratch:SI 4 ""))]
4143 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4144 [(set (match_dup 4)
4145 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4146 (match_dup 3)))
4147 (set (match_dup 0)
4148 (compare:CC (match_dup 4)
4149 (const_int 0)))]
4150 "")
4152 (define_insn ""
4153 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4154 (compare:CC
4155 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4156 (match_operand:SI 2 "const_int_operand" "i,i"))
4157 (match_operand:SI 3 "mask_operand" "n,n"))
4158 (const_int 0)))
4159 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4160 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4161 "includes_lshift_p (operands[2], operands[3])"
4162 "@
4163 rlwinm. %0,%1,%h2,%m3,%M3
4164 #"
4165 [(set_attr "type" "shift")
4166 (set_attr "dot" "yes")
4167 (set_attr "length" "4,8")])
4169 (define_split
4170 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4171 (compare:CC
4172 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4173 (match_operand:SI 2 "const_int_operand" ""))
4174 (match_operand:SI 3 "mask_operand" ""))
4175 (const_int 0)))
4176 (set (match_operand:SI 0 "gpc_reg_operand" "")
4177 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4178 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4179 [(set (match_dup 0)
4180 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4181 (set (match_dup 4)
4182 (compare:CC (match_dup 0)
4183 (const_int 0)))]
4184 "")
4187 (define_insn "lshr<mode>3"
4188 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4189 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4190 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4191 ""
4192 "sr<wd>%I2 %0,%1,%<hH>2"
4193 [(set_attr "type" "shift")
4194 (set_attr "maybe_var_shift" "yes")])
4196 (define_insn "*lshrsi3_64"
4197 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4198 (zero_extend:DI
4199 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4200 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4201 "TARGET_POWERPC64"
4202 "srw%I2 %0,%1,%h2"
4203 [(set_attr "type" "shift")
4204 (set_attr "maybe_var_shift" "yes")])
4206 (define_insn_and_split "*lshr<mode>3_dot"
4207 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4208 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4209 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4210 (const_int 0)))
4211 (clobber (match_scratch:GPR 0 "=r,r"))]
4212 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4213 "@
4214 sr<wd>%I2. %0,%1,%<hH>2
4215 #"
4216 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4217 [(set (match_dup 0)
4218 (lshiftrt:GPR (match_dup 1)
4219 (match_dup 2)))
4220 (set (match_dup 3)
4221 (compare:CC (match_dup 0)
4222 (const_int 0)))]
4223 ""
4224 [(set_attr "type" "shift")
4225 (set_attr "maybe_var_shift" "yes")
4226 (set_attr "dot" "yes")
4227 (set_attr "length" "4,8")])
4229 (define_insn_and_split "*lshr<mode>3_dot2"
4230 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4231 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4232 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4233 (const_int 0)))
4234 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4235 (lshiftrt:GPR (match_dup 1)
4236 (match_dup 2)))]
4237 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4238 "@
4239 sr<wd>%I2. %0,%1,%<hH>2
4240 #"
4241 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4242 [(set (match_dup 0)
4243 (lshiftrt:GPR (match_dup 1)
4244 (match_dup 2)))
4245 (set (match_dup 3)
4246 (compare:CC (match_dup 0)
4247 (const_int 0)))]
4248 ""
4249 [(set_attr "type" "shift")
4250 (set_attr "maybe_var_shift" "yes")
4251 (set_attr "dot" "yes")
4252 (set_attr "length" "4,8")])
4255 (define_insn ""
4256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4257 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4258 (match_operand:SI 2 "const_int_operand" "i"))
4259 (match_operand:SI 3 "mask_operand" "n")))]
4260 "includes_rshift_p (operands[2], operands[3])"
4261 "rlwinm %0,%1,%s2,%m3,%M3"
4262 [(set_attr "type" "shift")])
4264 (define_insn ""
4265 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4266 (compare:CC
4267 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4268 (match_operand:SI 2 "const_int_operand" "i,i"))
4269 (match_operand:SI 3 "mask_operand" "n,n"))
4270 (const_int 0)))
4271 (clobber (match_scratch:SI 4 "=r,r"))]
4272 "includes_rshift_p (operands[2], operands[3])"
4273 "@
4274 rlwinm. %4,%1,%s2,%m3,%M3
4275 #"
4276 [(set_attr "type" "shift")
4277 (set_attr "dot" "yes")
4278 (set_attr "length" "4,8")])
4280 (define_split
4281 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4282 (compare:CC
4283 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4284 (match_operand:SI 2 "const_int_operand" ""))
4285 (match_operand:SI 3 "mask_operand" ""))
4286 (const_int 0)))
4287 (clobber (match_scratch:SI 4 ""))]
4288 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4289 [(set (match_dup 4)
4290 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4291 (match_dup 3)))
4292 (set (match_dup 0)
4293 (compare:CC (match_dup 4)
4294 (const_int 0)))]
4295 "")
4297 (define_insn ""
4298 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4299 (compare:CC
4300 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4301 (match_operand:SI 2 "const_int_operand" "i,i"))
4302 (match_operand:SI 3 "mask_operand" "n,n"))
4303 (const_int 0)))
4304 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4305 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4306 "includes_rshift_p (operands[2], operands[3])"
4307 "@
4308 rlwinm. %0,%1,%s2,%m3,%M3
4309 #"
4310 [(set_attr "type" "shift")
4311 (set_attr "dot" "yes")
4312 (set_attr "length" "4,8")])
4314 (define_split
4315 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4316 (compare:CC
4317 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4318 (match_operand:SI 2 "const_int_operand" ""))
4319 (match_operand:SI 3 "mask_operand" ""))
4320 (const_int 0)))
4321 (set (match_operand:SI 0 "gpc_reg_operand" "")
4322 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4323 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4324 [(set (match_dup 0)
4325 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4326 (set (match_dup 4)
4327 (compare:CC (match_dup 0)
4328 (const_int 0)))]
4329 "")
4331 (define_insn "*lshiftrt_internal1le"
4332 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4333 (zero_extend:SI
4334 (subreg:QI
4335 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4336 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4337 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4338 "rlwinm %0,%1,%s2,0xff"
4339 [(set_attr "type" "shift")])
4341 (define_insn "*lshiftrt_internal1be"
4342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4343 (zero_extend:SI
4344 (subreg:QI
4345 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4346 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4347 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4348 "rlwinm %0,%1,%s2,0xff"
4349 [(set_attr "type" "shift")])
4351 (define_insn "*lshiftrt_internal2le"
4352 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4353 (compare:CC
4354 (zero_extend:SI
4355 (subreg:QI
4356 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4357 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4358 (const_int 0)))
4359 (clobber (match_scratch:SI 3 "=r,r"))]
4360 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4361 "@
4362 rlwinm. %3,%1,%s2,0xff
4363 #"
4364 [(set_attr "type" "shift")
4365 (set_attr "dot" "yes")
4366 (set_attr "length" "4,8")])
4368 (define_insn "*lshiftrt_internal2be"
4369 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4370 (compare:CC
4371 (zero_extend:SI
4372 (subreg:QI
4373 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4374 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4375 (const_int 0)))
4376 (clobber (match_scratch:SI 3 "=r,r"))]
4377 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4378 "@
4379 rlwinm. %3,%1,%s2,0xff
4380 #"
4381 [(set_attr "type" "shift")
4382 (set_attr "dot" "yes")
4383 (set_attr "length" "4,8")])
4385 (define_split
4386 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4387 (compare:CC
4388 (zero_extend:SI
4389 (subreg:QI
4390 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4391 (match_operand:SI 2 "const_int_operand" "")) 0))
4392 (const_int 0)))
4393 (clobber (match_scratch:SI 3 ""))]
4394 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4395 [(set (match_dup 3)
4396 (zero_extend:SI (subreg:QI
4397 (lshiftrt:SI (match_dup 1)
4398 (match_dup 2)) 0)))
4399 (set (match_dup 0)
4400 (compare:CC (match_dup 3)
4401 (const_int 0)))]
4402 "")
4404 (define_split
4405 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4406 (compare:CC
4407 (zero_extend:SI
4408 (subreg:QI
4409 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4410 (match_operand:SI 2 "const_int_operand" "")) 3))
4411 (const_int 0)))
4412 (clobber (match_scratch:SI 3 ""))]
4413 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4414 [(set (match_dup 3)
4415 (zero_extend:SI (subreg:QI
4416 (lshiftrt:SI (match_dup 1)
4417 (match_dup 2)) 3)))
4418 (set (match_dup 0)
4419 (compare:CC (match_dup 3)
4420 (const_int 0)))]
4421 "")
4423 (define_insn "*lshiftrt_internal3le"
4424 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4425 (compare:CC
4426 (zero_extend:SI
4427 (subreg:QI
4428 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4429 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4430 (const_int 0)))
4431 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4432 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4433 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4434 "@
4435 rlwinm. %0,%1,%s2,0xff
4436 #"
4437 [(set_attr "type" "shift")
4438 (set_attr "dot" "yes")
4439 (set_attr "length" "4,8")])
4441 (define_insn "*lshiftrt_internal3be"
4442 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4443 (compare:CC
4444 (zero_extend:SI
4445 (subreg:QI
4446 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4447 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4448 (const_int 0)))
4449 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4450 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4451 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4452 "@
4453 rlwinm. %0,%1,%s2,0xff
4454 #"
4455 [(set_attr "type" "shift")
4456 (set_attr "dot" "yes")
4457 (set_attr "length" "4,8")])
4459 (define_split
4460 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4461 (compare:CC
4462 (zero_extend:SI
4463 (subreg:QI
4464 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4465 (match_operand:SI 2 "const_int_operand" "")) 0))
4466 (const_int 0)))
4467 (set (match_operand:SI 0 "gpc_reg_operand" "")
4468 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4469 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4470 [(set (match_dup 0)
4471 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4472 (set (match_dup 3)
4473 (compare:CC (match_dup 0)
4474 (const_int 0)))]
4475 "")
4477 (define_split
4478 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4479 (compare:CC
4480 (zero_extend:SI
4481 (subreg:QI
4482 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4483 (match_operand:SI 2 "const_int_operand" "")) 3))
4484 (const_int 0)))
4485 (set (match_operand:SI 0 "gpc_reg_operand" "")
4486 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4487 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4488 [(set (match_dup 0)
4489 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4490 (set (match_dup 3)
4491 (compare:CC (match_dup 0)
4492 (const_int 0)))]
4493 "")
4495 (define_insn "*lshiftrt_internal4le"
4496 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4497 (zero_extend:SI
4498 (subreg:HI
4499 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4500 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4501 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4502 "rlwinm %0,%1,%s2,0xffff"
4503 [(set_attr "type" "shift")])
4505 (define_insn "*lshiftrt_internal4be"
4506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4507 (zero_extend:SI
4508 (subreg:HI
4509 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4510 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4511 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4512 "rlwinm %0,%1,%s2,0xffff"
4513 [(set_attr "type" "shift")])
4515 (define_insn "*lshiftrt_internal5le"
4516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4517 (compare:CC
4518 (zero_extend:SI
4519 (subreg:HI
4520 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4521 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4522 (const_int 0)))
4523 (clobber (match_scratch:SI 3 "=r,r"))]
4524 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4525 "@
4526 rlwinm. %3,%1,%s2,0xffff
4527 #"
4528 [(set_attr "type" "shift")
4529 (set_attr "dot" "yes")
4530 (set_attr "length" "4,8")])
4532 (define_insn "*lshiftrt_internal5be"
4533 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4534 (compare:CC
4535 (zero_extend:SI
4536 (subreg:HI
4537 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4538 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4539 (const_int 0)))
4540 (clobber (match_scratch:SI 3 "=r,r"))]
4541 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4542 "@
4543 rlwinm. %3,%1,%s2,0xffff
4544 #"
4545 [(set_attr "type" "shift")
4546 (set_attr "dot" "yes")
4547 (set_attr "length" "4,8")])
4549 (define_split
4550 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4551 (compare:CC
4552 (zero_extend:SI
4553 (subreg:HI
4554 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4555 (match_operand:SI 2 "const_int_operand" "")) 0))
4556 (const_int 0)))
4557 (clobber (match_scratch:SI 3 ""))]
4558 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4559 [(set (match_dup 3)
4560 (zero_extend:SI (subreg:HI
4561 (lshiftrt:SI (match_dup 1)
4562 (match_dup 2)) 0)))
4563 (set (match_dup 0)
4564 (compare:CC (match_dup 3)
4565 (const_int 0)))]
4566 "")
4568 (define_split
4569 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4570 (compare:CC
4571 (zero_extend:SI
4572 (subreg:HI
4573 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4574 (match_operand:SI 2 "const_int_operand" "")) 2))
4575 (const_int 0)))
4576 (clobber (match_scratch:SI 3 ""))]
4577 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4578 [(set (match_dup 3)
4579 (zero_extend:SI (subreg:HI
4580 (lshiftrt:SI (match_dup 1)
4581 (match_dup 2)) 2)))
4582 (set (match_dup 0)
4583 (compare:CC (match_dup 3)
4584 (const_int 0)))]
4585 "")
4587 (define_insn "*lshiftrt_internal5le"
4588 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4589 (compare:CC
4590 (zero_extend:SI
4591 (subreg:HI
4592 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4593 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4594 (const_int 0)))
4595 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4596 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4597 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4598 "@
4599 rlwinm. %0,%1,%s2,0xffff
4600 #"
4601 [(set_attr "type" "shift")
4602 (set_attr "dot" "yes")
4603 (set_attr "length" "4,8")])
4605 (define_insn "*lshiftrt_internal5be"
4606 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4607 (compare:CC
4608 (zero_extend:SI
4609 (subreg:HI
4610 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4611 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4612 (const_int 0)))
4613 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4614 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4615 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4616 "@
4617 rlwinm. %0,%1,%s2,0xffff
4618 #"
4619 [(set_attr "type" "shift")
4620 (set_attr "dot" "yes")
4621 (set_attr "length" "4,8")])
4623 (define_split
4624 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4625 (compare:CC
4626 (zero_extend:SI
4627 (subreg:HI
4628 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4629 (match_operand:SI 2 "const_int_operand" "")) 0))
4630 (const_int 0)))
4631 (set (match_operand:SI 0 "gpc_reg_operand" "")
4632 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4633 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4634 [(set (match_dup 0)
4635 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4636 (set (match_dup 3)
4637 (compare:CC (match_dup 0)
4638 (const_int 0)))]
4639 "")
4641 (define_split
4642 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4643 (compare:CC
4644 (zero_extend:SI
4645 (subreg:HI
4646 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4647 (match_operand:SI 2 "const_int_operand" "")) 2))
4648 (const_int 0)))
4649 (set (match_operand:SI 0 "gpc_reg_operand" "")
4650 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4651 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4652 [(set (match_dup 0)
4653 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4654 (set (match_dup 3)
4655 (compare:CC (match_dup 0)
4656 (const_int 0)))]
4657 "")
4660 (define_expand "ashr<mode>3"
4661 [(parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4662 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
4663 (match_operand:SI 2 "reg_or_cint_operand" "")))
4664 (clobber (reg:GPR CA_REGNO))])]
4665 ""
4666 {
4667 /* The generic code does not generate optimal code for the low word
4668 (it should be a rlwimi and a rot). Until we have target code to
4669 solve this generically, keep this expander. */
4671 if (<MODE>mode == DImode && !TARGET_POWERPC64)
4672 {
4673 if (CONST_INT_P (operands[2]))
4674 {
4675 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
4676 DONE;
4677 }
4678 else
4679 FAIL;
4680 }
4681 })
4683 (define_insn "*ashr<mode>3"
4684 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4685 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4686 (match_operand:SI 2 "reg_or_cint_operand" "rn")))
4687 (clobber (reg:GPR CA_REGNO))]
4688 ""
4689 "sra<wd>%I2 %0,%1,%<hH>2"
4690 [(set_attr "type" "shift")
4691 (set_attr "maybe_var_shift" "yes")])
4693 (define_insn "*ashrsi3_64"
4694 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4695 (sign_extend:DI
4696 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4697 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))
4698 (clobber (reg:SI CA_REGNO))]
4699 "TARGET_POWERPC64"
4700 "sraw%I2 %0,%1,%h2"
4701 [(set_attr "type" "shift")
4702 (set_attr "maybe_var_shift" "yes")])
4704 (define_insn_and_split "*ashr<mode>3_dot"
4705 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4706 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4707 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4708 (const_int 0)))
4709 (clobber (match_scratch:GPR 0 "=r,r"))
4710 (clobber (reg:GPR CA_REGNO))]
4711 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4712 "@
4713 sra<wd>%I2. %0,%1,%<hH>2
4714 #"
4715 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4716 [(parallel [(set (match_dup 0)
4717 (ashiftrt:GPR (match_dup 1)
4718 (match_dup 2)))
4719 (clobber (reg:GPR CA_REGNO))])
4720 (set (match_dup 3)
4721 (compare:CC (match_dup 0)
4722 (const_int 0)))]
4723 ""
4724 [(set_attr "type" "shift")
4725 (set_attr "maybe_var_shift" "yes")
4726 (set_attr "dot" "yes")
4727 (set_attr "length" "4,8")])
4729 (define_insn_and_split "*ashr<mode>3_dot2"
4730 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4731 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4732 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4733 (const_int 0)))
4734 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4735 (ashiftrt:GPR (match_dup 1)
4736 (match_dup 2)))
4737 (clobber (reg:GPR CA_REGNO))]
4738 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4739 "@
4740 sra<wd>%I2. %0,%1,%<hH>2
4741 #"
4742 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4743 [(parallel [(set (match_dup 0)
4744 (ashiftrt:GPR (match_dup 1)
4745 (match_dup 2)))
4746 (clobber (reg:GPR CA_REGNO))])
4747 (set (match_dup 3)
4748 (compare:CC (match_dup 0)
4749 (const_int 0)))]
4750 ""
4751 [(set_attr "type" "shift")
4752 (set_attr "maybe_var_shift" "yes")
4753 (set_attr "dot" "yes")
4754 (set_attr "length" "4,8")])
4755 \f
4756 ;; Builtins to replace a division to generate FRE reciprocal estimate
4757 ;; instructions and the necessary fixup instructions
4758 (define_expand "recip<mode>3"
4759 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4760 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4761 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4762 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4763 {
4764 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4765 DONE;
4766 })
4768 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4769 ;; hardware division. This is only done before register allocation and with
4770 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4771 (define_split
4772 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4773 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4774 (match_operand 2 "gpc_reg_operand" "")))]
4775 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4776 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4777 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4778 [(const_int 0)]
4779 {
4780 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4781 DONE;
4782 })
4784 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4785 ;; appropriate fixup.
4786 (define_expand "rsqrt<mode>2"
4787 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4788 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4789 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4790 {
4791 rs6000_emit_swrsqrt (operands[0], operands[1]);
4792 DONE;
4793 })
4794 \f
4795 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
4796 ;; modes here, and also add in conditional vsx/power8-vector support to access
4797 ;; values in the traditional Altivec registers if the appropriate
4798 ;; -mupper-regs-{df,sf} option is enabled.
4800 (define_expand "abs<mode>2"
4801 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4802 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4803 "TARGET_<MODE>_INSN"
4804 "")
4806 (define_insn "*abs<mode>2_fpr"
4807 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4808 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4809 "TARGET_<MODE>_FPR"
4810 "@
4811 fabs %0,%1
4812 xsabsdp %x0,%x1"
4813 [(set_attr "type" "fp")
4814 (set_attr "fp_type" "fp_addsub_<Fs>")])
4816 (define_insn "*nabs<mode>2_fpr"
4817 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4818 (neg:SFDF
4819 (abs:SFDF
4820 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
4821 "TARGET_<MODE>_FPR"
4822 "@
4823 fnabs %0,%1
4824 xsnabsdp %x0,%x1"
4825 [(set_attr "type" "fp")
4826 (set_attr "fp_type" "fp_addsub_<Fs>")])
4828 (define_expand "neg<mode>2"
4829 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4830 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4831 "TARGET_<MODE>_INSN"
4832 "")
4834 (define_insn "*neg<mode>2_fpr"
4835 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4836 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4837 "TARGET_<MODE>_FPR"
4838 "@
4839 fneg %0,%1
4840 xsnegdp %x0,%x1"
4841 [(set_attr "type" "fp")
4842 (set_attr "fp_type" "fp_addsub_<Fs>")])
4844 (define_expand "add<mode>3"
4845 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4846 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4847 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4848 "TARGET_<MODE>_INSN"
4849 "")
4851 (define_insn "*add<mode>3_fpr"
4852 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4853 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4854 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4855 "TARGET_<MODE>_FPR"
4856 "@
4857 fadd<Ftrad> %0,%1,%2
4858 xsadd<Fvsx> %x0,%x1,%x2"
4859 [(set_attr "type" "fp")
4860 (set_attr "fp_type" "fp_addsub_<Fs>")])
4862 (define_expand "sub<mode>3"
4863 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4864 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4865 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4866 "TARGET_<MODE>_INSN"
4867 "")
4869 (define_insn "*sub<mode>3_fpr"
4870 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4871 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4872 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4873 "TARGET_<MODE>_FPR"
4874 "@
4875 fsub<Ftrad> %0,%1,%2
4876 xssub<Fvsx> %x0,%x1,%x2"
4877 [(set_attr "type" "fp")
4878 (set_attr "fp_type" "fp_addsub_<Fs>")])
4880 (define_expand "mul<mode>3"
4881 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4882 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4883 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4884 "TARGET_<MODE>_INSN"
4885 "")
4887 (define_insn "*mul<mode>3_fpr"
4888 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4889 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4890 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4891 "TARGET_<MODE>_FPR"
4892 "@
4893 fmul<Ftrad> %0,%1,%2
4894 xsmul<Fvsx> %x0,%x1,%x2"
4895 [(set_attr "type" "dmul")
4896 (set_attr "fp_type" "fp_mul_<Fs>")])
4898 (define_expand "div<mode>3"
4899 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4900 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4901 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4902 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
4903 "")
4905 (define_insn "*div<mode>3_fpr"
4906 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4907 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4908 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4909 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
4910 "@
4911 fdiv<Ftrad> %0,%1,%2
4912 xsdiv<Fvsx> %x0,%x1,%x2"
4913 [(set_attr "type" "<Fs>div")
4914 (set_attr "fp_type" "fp_div_<Fs>")])
4916 (define_insn "sqrt<mode>2"
4917 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4918 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4919 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
4920 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
4921 "@
4922 fsqrt<Ftrad> %0,%1
4923 xssqrt<Fvsx> %x0,%x1"
4924 [(set_attr "type" "<Fs>sqrt")
4925 (set_attr "fp_type" "fp_sqrt_<Fs>")])
4927 ;; Floating point reciprocal approximation
4928 (define_insn "fre<Fs>"
4929 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4930 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
4931 UNSPEC_FRES))]
4932 "TARGET_<FFRE>"
4933 "@
4934 fre<Ftrad> %0,%1
4935 xsre<Fvsx> %x0,%x1"
4936 [(set_attr "type" "fp")])
4938 (define_insn "*rsqrt<mode>2"
4939 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4940 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
4941 UNSPEC_RSQRT))]
4942 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4943 "@
4944 frsqrte<Ftrad> %0,%1
4945 xsrsqrte<Fvsx> %x0,%x1"
4946 [(set_attr "type" "fp")])
4948 ;; Floating point comparisons
4949 (define_insn "*cmp<mode>_fpr"
4950 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
4951 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4952 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4953 "TARGET_<MODE>_FPR"
4954 "@
4955 fcmpu %0,%1,%2
4956 xscmpudp %0,%x1,%x2"
4957 [(set_attr "type" "fpcompare")])
4959 ;; Floating point conversions
4960 (define_expand "extendsfdf2"
4961 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4962 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4963 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4964 "")
4966 (define_insn_and_split "*extendsfdf2_fpr"
4967 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wu")
4968 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
4969 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4970 "@
4971 #
4972 fmr %0,%1
4973 lfs%U1%X1 %0,%1
4974 #
4975 xxlor %x0,%x1,%x1
4976 lxsspx %x0,%y1"
4977 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4978 [(const_int 0)]
4979 {
4980 emit_note (NOTE_INSN_DELETED);
4981 DONE;
4982 }
4983 [(set_attr "type" "fp,fp,fpload,fp,vecsimple,fpload")])
4985 (define_expand "truncdfsf2"
4986 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4987 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4988 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4989 "")
4991 (define_insn "*truncdfsf2_fpr"
4992 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4993 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4994 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4995 "frsp %0,%1"
4996 [(set_attr "type" "fp")])
4998 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
4999 ;; builtins.c and optabs.c that are not correct for IBM long double
5000 ;; when little-endian.
5001 (define_expand "signbittf2"
5002 [(set (match_dup 2)
5003 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
5004 (set (match_dup 3)
5005 (subreg:DI (match_dup 2) 0))
5006 (set (match_dup 4)
5007 (match_dup 5))
5008 (set (match_operand:SI 0 "gpc_reg_operand" "")
5009 (match_dup 6))]
5010 "!TARGET_IEEEQUAD
5011 && TARGET_HARD_FLOAT
5012 && (TARGET_FPRS || TARGET_E500_DOUBLE)
5013 && TARGET_LONG_DOUBLE_128"
5014 {
5015 operands[2] = gen_reg_rtx (DFmode);
5016 operands[3] = gen_reg_rtx (DImode);
5017 if (TARGET_POWERPC64)
5018 {
5019 operands[4] = gen_reg_rtx (DImode);
5020 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
5021 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
5022 WORDS_BIG_ENDIAN ? 4 : 0);
5023 }
5024 else
5025 {
5026 operands[4] = gen_reg_rtx (SImode);
5027 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
5028 WORDS_BIG_ENDIAN ? 0 : 4);
5029 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
5030 }
5031 })
5033 (define_expand "copysign<mode>3"
5034 [(set (match_dup 3)
5035 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5036 (set (match_dup 4)
5037 (neg:SFDF (abs:SFDF (match_dup 1))))
5038 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5039 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5040 (match_dup 5))
5041 (match_dup 3)
5042 (match_dup 4)))]
5043 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5044 && ((TARGET_PPC_GFXOPT
5045 && !HONOR_NANS (<MODE>mode)
5046 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5047 || TARGET_CMPB
5048 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5049 {
5050 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5051 {
5052 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5053 operands[2]));
5054 DONE;
5055 }
5057 operands[3] = gen_reg_rtx (<MODE>mode);
5058 operands[4] = gen_reg_rtx (<MODE>mode);
5059 operands[5] = CONST0_RTX (<MODE>mode);
5060 })
5062 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5063 ;; compiler from optimizing -0.0
5064 (define_insn "copysign<mode>3_fcpsgn"
5065 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5066 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5067 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
5068 UNSPEC_COPYSIGN))]
5069 "TARGET_<MODE>_FPR && TARGET_CMPB"
5070 "@
5071 fcpsgn %0,%2,%1
5072 xscpsgndp %x0,%x2,%x1"
5073 [(set_attr "type" "fp")])
5075 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5076 ;; fsel instruction and some auxiliary computations. Then we just have a
5077 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5078 ;; combine.
5079 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5080 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5081 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5082 ;; define_splits to make them if made by combine. On VSX machines we have the
5083 ;; min/max instructions.
5084 ;;
5085 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5086 ;; to allow either DF/SF to use only traditional registers.
5088 (define_expand "smax<mode>3"
5089 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5090 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5091 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5092 (match_dup 1)
5093 (match_dup 2)))]
5094 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5095 {
5096 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
5097 DONE;
5098 })
5100 (define_insn "*smax<mode>3_vsx"
5101 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5102 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5103 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5104 "TARGET_<MODE>_FPR && TARGET_VSX"
5105 "xsmaxdp %x0,%x1,%x2"
5106 [(set_attr "type" "fp")])
5108 (define_expand "smin<mode>3"
5109 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5110 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5111 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5112 (match_dup 2)
5113 (match_dup 1)))]
5114 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5115 {
5116 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
5117 DONE;
5118 })
5120 (define_insn "*smin<mode>3_vsx"
5121 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5122 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5123 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5124 "TARGET_<MODE>_FPR && TARGET_VSX"
5125 "xsmindp %x0,%x1,%x2"
5126 [(set_attr "type" "fp")])
5128 (define_split
5129 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5130 (match_operator:SFDF 3 "min_max_operator"
5131 [(match_operand:SFDF 1 "gpc_reg_operand" "")
5132 (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
5133 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
5134 && !TARGET_VSX"
5135 [(const_int 0)]
5136 {
5137 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
5138 operands[2]);
5139 DONE;
5140 })
5142 (define_split
5143 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5144 (match_operator:SF 3 "min_max_operator"
5145 [(match_operand:SF 1 "gpc_reg_operand" "")
5146 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5147 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5148 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5149 [(const_int 0)]
5150 "
5151 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5152 operands[1], operands[2]);
5153 DONE;
5154 }")
5156 (define_expand "mov<mode>cc"
5157 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5158 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5159 (match_operand:GPR 2 "gpc_reg_operand" "")
5160 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5161 "TARGET_ISEL<sel>"
5162 "
5163 {
5164 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5165 DONE;
5166 else
5167 FAIL;
5168 }")
5170 ;; We use the BASE_REGS for the isel input operands because, if rA is
5171 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5172 ;; because we may switch the operands and rB may end up being rA.
5173 ;;
5174 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5175 ;; leave out the mode in operand 4 and use one pattern, but reload can
5176 ;; change the mode underneath our feet and then gets confused trying
5177 ;; to reload the value.
5178 (define_insn "isel_signed_<mode>"
5179 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5180 (if_then_else:GPR
5181 (match_operator 1 "scc_comparison_operator"
5182 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5183 (const_int 0)])
5184 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5185 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5186 "TARGET_ISEL<sel>"
5187 "*
5188 { return output_isel (operands); }"
5189 [(set_attr "type" "isel")
5190 (set_attr "length" "4")])
5192 (define_insn "isel_unsigned_<mode>"
5193 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5194 (if_then_else:GPR
5195 (match_operator 1 "scc_comparison_operator"
5196 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5197 (const_int 0)])
5198 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5199 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5200 "TARGET_ISEL<sel>"
5201 "*
5202 { return output_isel (operands); }"
5203 [(set_attr "type" "isel")
5204 (set_attr "length" "4")])
5206 ;; These patterns can be useful for combine; they let combine know that
5207 ;; isel can handle reversed comparisons so long as the operands are
5208 ;; registers.
5210 (define_insn "*isel_reversed_signed_<mode>"
5211 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5212 (if_then_else:GPR
5213 (match_operator 1 "scc_rev_comparison_operator"
5214 [(match_operand:CC 4 "cc_reg_operand" "y")
5215 (const_int 0)])
5216 (match_operand:GPR 2 "gpc_reg_operand" "b")
5217 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5218 "TARGET_ISEL<sel>"
5219 "*
5220 { return output_isel (operands); }"
5221 [(set_attr "type" "isel")
5222 (set_attr "length" "4")])
5224 (define_insn "*isel_reversed_unsigned_<mode>"
5225 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5226 (if_then_else:GPR
5227 (match_operator 1 "scc_rev_comparison_operator"
5228 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5229 (const_int 0)])
5230 (match_operand:GPR 2 "gpc_reg_operand" "b")
5231 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5232 "TARGET_ISEL<sel>"
5233 "*
5234 { return output_isel (operands); }"
5235 [(set_attr "type" "isel")
5236 (set_attr "length" "4")])
5238 (define_expand "movsfcc"
5239 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5240 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5241 (match_operand:SF 2 "gpc_reg_operand" "")
5242 (match_operand:SF 3 "gpc_reg_operand" "")))]
5243 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5244 "
5245 {
5246 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5247 DONE;
5248 else
5249 FAIL;
5250 }")
5252 (define_insn "*fselsfsf4"
5253 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5254 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5255 (match_operand:SF 4 "zero_fp_constant" "F"))
5256 (match_operand:SF 2 "gpc_reg_operand" "f")
5257 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5258 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5259 "fsel %0,%1,%2,%3"
5260 [(set_attr "type" "fp")])
5262 (define_insn "*fseldfsf4"
5263 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5264 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5265 (match_operand:DF 4 "zero_fp_constant" "F"))
5266 (match_operand:SF 2 "gpc_reg_operand" "f")
5267 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5268 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5269 "fsel %0,%1,%2,%3"
5270 [(set_attr "type" "fp")])
5272 ;; The conditional move instructions allow us to perform max and min
5273 ;; operations even when
5275 (define_split
5276 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5277 (match_operator:DF 3 "min_max_operator"
5278 [(match_operand:DF 1 "gpc_reg_operand" "")
5279 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5280 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5281 && !flag_trapping_math"
5282 [(const_int 0)]
5283 "
5284 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5285 operands[1], operands[2]);
5286 DONE;
5287 }")
5289 (define_expand "movdfcc"
5290 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5291 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5292 (match_operand:DF 2 "gpc_reg_operand" "")
5293 (match_operand:DF 3 "gpc_reg_operand" "")))]
5294 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5295 "
5296 {
5297 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5298 DONE;
5299 else
5300 FAIL;
5301 }")
5303 (define_insn "*fseldfdf4"
5304 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5305 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5306 (match_operand:DF 4 "zero_fp_constant" "F"))
5307 (match_operand:DF 2 "gpc_reg_operand" "d")
5308 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5309 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5310 "fsel %0,%1,%2,%3"
5311 [(set_attr "type" "fp")])
5313 (define_insn "*fselsfdf4"
5314 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5315 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5316 (match_operand:SF 4 "zero_fp_constant" "F"))
5317 (match_operand:DF 2 "gpc_reg_operand" "d")
5318 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5319 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5320 "fsel %0,%1,%2,%3"
5321 [(set_attr "type" "fp")])
5322 \f
5323 ;; Conversions to and from floating-point.
5325 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5326 ; don't want to support putting SImode in FPR registers.
5327 (define_insn "lfiwax"
5328 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5329 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5330 UNSPEC_LFIWAX))]
5331 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5332 "@
5333 lfiwax %0,%y1
5334 lxsiwax %x0,%y1
5335 mtvsrwa %x0,%1"
5336 [(set_attr "type" "fpload,fpload,mffgpr")])
5338 ; This split must be run before register allocation because it allocates the
5339 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5340 ; it earlier to allow for the combiner to merge insns together where it might
5341 ; not be needed and also in case the insns are deleted as dead code.
5343 (define_insn_and_split "floatsi<mode>2_lfiwax"
5344 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
5345 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5346 (clobber (match_scratch:DI 2 "=wj"))]
5347 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5348 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5349 "#"
5350 ""
5351 [(pc)]
5352 "
5353 {
5354 rtx dest = operands[0];
5355 rtx src = operands[1];
5356 rtx tmp;
5358 if (!MEM_P (src) && TARGET_POWERPC64
5359 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5360 tmp = convert_to_mode (DImode, src, false);
5361 else
5362 {
5363 tmp = operands[2];
5364 if (GET_CODE (tmp) == SCRATCH)
5365 tmp = gen_reg_rtx (DImode);
5366 if (MEM_P (src))
5367 {
5368 src = rs6000_address_for_fpconvert (src);
5369 emit_insn (gen_lfiwax (tmp, src));
5370 }
5371 else
5372 {
5373 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5374 emit_move_insn (stack, src);
5375 emit_insn (gen_lfiwax (tmp, stack));
5376 }
5377 }
5378 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5379 DONE;
5380 }"
5381 [(set_attr "length" "12")
5382 (set_attr "type" "fpload")])
5384 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5385 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fa>")
5386 (float:SFDF
5387 (sign_extend:DI
5388 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5389 (clobber (match_scratch:DI 2 "=0,d"))]
5390 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5391 && <SI_CONVERT_FP>"
5392 "#"
5393 ""
5394 [(pc)]
5395 "
5396 {
5397 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5398 if (GET_CODE (operands[2]) == SCRATCH)
5399 operands[2] = gen_reg_rtx (DImode);
5400 emit_insn (gen_lfiwax (operands[2], operands[1]));
5401 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5402 DONE;
5403 }"
5404 [(set_attr "length" "8")
5405 (set_attr "type" "fpload")])
5407 (define_insn "lfiwzx"
5408 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5409 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5410 UNSPEC_LFIWZX))]
5411 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5412 "@
5413 lfiwzx %0,%y1
5414 lxsiwzx %x0,%y1
5415 mtvsrwz %x0,%1"
5416 [(set_attr "type" "fpload,fpload,mftgpr")])
5418 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5419 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
5420 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5421 (clobber (match_scratch:DI 2 "=wj"))]
5422 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5423 && <SI_CONVERT_FP>"
5424 "#"
5425 ""
5426 [(pc)]
5427 "
5428 {
5429 rtx dest = operands[0];
5430 rtx src = operands[1];
5431 rtx tmp;
5433 if (!MEM_P (src) && TARGET_POWERPC64
5434 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5435 tmp = convert_to_mode (DImode, src, true);
5436 else
5437 {
5438 tmp = operands[2];
5439 if (GET_CODE (tmp) == SCRATCH)
5440 tmp = gen_reg_rtx (DImode);
5441 if (MEM_P (src))
5442 {
5443 src = rs6000_address_for_fpconvert (src);
5444 emit_insn (gen_lfiwzx (tmp, src));
5445 }
5446 else
5447 {
5448 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5449 emit_move_insn (stack, src);
5450 emit_insn (gen_lfiwzx (tmp, stack));
5451 }
5452 }
5453 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5454 DONE;
5455 }"
5456 [(set_attr "length" "12")
5457 (set_attr "type" "fpload")])
5459 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5460 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fa>")
5461 (unsigned_float:SFDF
5462 (zero_extend:DI
5463 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5464 (clobber (match_scratch:DI 2 "=0,d"))]
5465 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5466 && <SI_CONVERT_FP>"
5467 "#"
5468 ""
5469 [(pc)]
5470 "
5471 {
5472 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5473 if (GET_CODE (operands[2]) == SCRATCH)
5474 operands[2] = gen_reg_rtx (DImode);
5475 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5476 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5477 DONE;
5478 }"
5479 [(set_attr "length" "8")
5480 (set_attr "type" "fpload")])
5482 ; For each of these conversions, there is a define_expand, a define_insn
5483 ; with a '#' template, and a define_split (with C code). The idea is
5484 ; to allow constant folding with the template of the define_insn,
5485 ; then to have the insns split later (between sched1 and final).
5487 (define_expand "floatsidf2"
5488 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5489 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5490 (use (match_dup 2))
5491 (use (match_dup 3))
5492 (clobber (match_dup 4))
5493 (clobber (match_dup 5))
5494 (clobber (match_dup 6))])]
5495 "TARGET_HARD_FLOAT
5496 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5497 "
5498 {
5499 if (TARGET_E500_DOUBLE)
5500 {
5501 if (!REG_P (operands[1]))
5502 operands[1] = force_reg (SImode, operands[1]);
5503 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5504 DONE;
5505 }
5506 else if (TARGET_LFIWAX && TARGET_FCFID)
5507 {
5508 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5509 DONE;
5510 }
5511 else if (TARGET_FCFID)
5512 {
5513 rtx dreg = operands[1];
5514 if (!REG_P (dreg))
5515 dreg = force_reg (SImode, dreg);
5516 dreg = convert_to_mode (DImode, dreg, false);
5517 emit_insn (gen_floatdidf2 (operands[0], dreg));
5518 DONE;
5519 }
5521 if (!REG_P (operands[1]))
5522 operands[1] = force_reg (SImode, operands[1]);
5523 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5524 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5525 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5526 operands[5] = gen_reg_rtx (DFmode);
5527 operands[6] = gen_reg_rtx (SImode);
5528 }")
5530 (define_insn_and_split "*floatsidf2_internal"
5531 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5532 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5533 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5534 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5535 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5536 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5537 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5538 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5539 "#"
5540 ""
5541 [(pc)]
5542 "
5543 {
5544 rtx lowword, highword;
5545 gcc_assert (MEM_P (operands[4]));
5546 highword = adjust_address (operands[4], SImode, 0);
5547 lowword = adjust_address (operands[4], SImode, 4);
5548 if (! WORDS_BIG_ENDIAN)
5549 std::swap (lowword, highword);
5551 emit_insn (gen_xorsi3 (operands[6], operands[1],
5552 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5553 emit_move_insn (lowword, operands[6]);
5554 emit_move_insn (highword, operands[2]);
5555 emit_move_insn (operands[5], operands[4]);
5556 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5557 DONE;
5558 }"
5559 [(set_attr "length" "24")
5560 (set_attr "type" "fp")])
5562 ;; If we don't have a direct conversion to single precision, don't enable this
5563 ;; conversion for 32-bit without fast math, because we don't have the insn to
5564 ;; generate the fixup swizzle to avoid double rounding problems.
5565 (define_expand "floatunssisf2"
5566 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5567 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5568 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5569 && (!TARGET_FPRS
5570 || (TARGET_FPRS
5571 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5572 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5573 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5574 "
5575 {
5576 if (!TARGET_FPRS)
5577 {
5578 if (!REG_P (operands[1]))
5579 operands[1] = force_reg (SImode, operands[1]);
5580 }
5581 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5582 {
5583 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5584 DONE;
5585 }
5586 else
5587 {
5588 rtx dreg = operands[1];
5589 if (!REG_P (dreg))
5590 dreg = force_reg (SImode, dreg);
5591 dreg = convert_to_mode (DImode, dreg, true);
5592 emit_insn (gen_floatdisf2 (operands[0], dreg));
5593 DONE;
5594 }
5595 }")
5597 (define_expand "floatunssidf2"
5598 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5599 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5600 (use (match_dup 2))
5601 (use (match_dup 3))
5602 (clobber (match_dup 4))
5603 (clobber (match_dup 5))])]
5604 "TARGET_HARD_FLOAT
5605 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5606 "
5607 {
5608 if (TARGET_E500_DOUBLE)
5609 {
5610 if (!REG_P (operands[1]))
5611 operands[1] = force_reg (SImode, operands[1]);
5612 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5613 DONE;
5614 }
5615 else if (TARGET_LFIWZX && TARGET_FCFID)
5616 {
5617 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5618 DONE;
5619 }
5620 else if (TARGET_FCFID)
5621 {
5622 rtx dreg = operands[1];
5623 if (!REG_P (dreg))
5624 dreg = force_reg (SImode, dreg);
5625 dreg = convert_to_mode (DImode, dreg, true);
5626 emit_insn (gen_floatdidf2 (operands[0], dreg));
5627 DONE;
5628 }
5630 if (!REG_P (operands[1]))
5631 operands[1] = force_reg (SImode, operands[1]);
5632 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5633 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5634 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5635 operands[5] = gen_reg_rtx (DFmode);
5636 }")
5638 (define_insn_and_split "*floatunssidf2_internal"
5639 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5640 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5641 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5642 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5643 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5644 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5645 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5646 && !(TARGET_FCFID && TARGET_POWERPC64)"
5647 "#"
5648 ""
5649 [(pc)]
5650 "
5651 {
5652 rtx lowword, highword;
5653 gcc_assert (MEM_P (operands[4]));
5654 highword = adjust_address (operands[4], SImode, 0);
5655 lowword = adjust_address (operands[4], SImode, 4);
5656 if (! WORDS_BIG_ENDIAN)
5657 std::swap (lowword, highword);
5659 emit_move_insn (lowword, operands[1]);
5660 emit_move_insn (highword, operands[2]);
5661 emit_move_insn (operands[5], operands[4]);
5662 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5663 DONE;
5664 }"
5665 [(set_attr "length" "20")
5666 (set_attr "type" "fp")])
5668 (define_expand "fix_trunc<mode>si2"
5669 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5670 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5671 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5672 "
5673 {
5674 if (!<E500_CONVERT>)
5675 {
5676 rtx tmp, stack;
5678 if (TARGET_STFIWX)
5679 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5680 else
5681 {
5682 tmp = gen_reg_rtx (DImode);
5683 stack = rs6000_allocate_stack_temp (DImode, true, false);
5684 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5685 tmp, stack));
5686 }
5687 DONE;
5688 }
5689 }")
5691 ; Like the convert to float patterns, this insn must be split before
5692 ; register allocation so that it can allocate the memory slot if it
5693 ; needed
5694 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5695 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5696 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5697 (clobber (match_scratch:DI 2 "=d"))]
5698 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5699 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5700 && TARGET_STFIWX && can_create_pseudo_p ()"
5701 "#"
5702 ""
5703 [(pc)]
5704 {
5705 rtx dest = operands[0];
5706 rtx src = operands[1];
5707 rtx tmp = operands[2];
5709 if (GET_CODE (tmp) == SCRATCH)
5710 tmp = gen_reg_rtx (DImode);
5712 emit_insn (gen_fctiwz_<mode> (tmp, src));
5713 if (MEM_P (dest))
5714 {
5715 dest = rs6000_address_for_fpconvert (dest);
5716 emit_insn (gen_stfiwx (dest, tmp));
5717 DONE;
5718 }
5719 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5720 {
5721 dest = gen_lowpart (DImode, dest);
5722 emit_move_insn (dest, tmp);
5723 DONE;
5724 }
5725 else
5726 {
5727 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5728 emit_insn (gen_stfiwx (stack, tmp));
5729 emit_move_insn (dest, stack);
5730 DONE;
5731 }
5732 }
5733 [(set_attr "length" "12")
5734 (set_attr "type" "fp")])
5736 (define_insn_and_split "fix_trunc<mode>si2_internal"
5737 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5738 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5739 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5740 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5741 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5742 "#"
5743 ""
5744 [(pc)]
5745 "
5746 {
5747 rtx lowword;
5748 gcc_assert (MEM_P (operands[3]));
5749 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5751 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5752 emit_move_insn (operands[3], operands[2]);
5753 emit_move_insn (operands[0], lowword);
5754 DONE;
5755 }"
5756 [(set_attr "length" "16")
5757 (set_attr "type" "fp")])
5759 (define_expand "fix_trunc<mode>di2"
5760 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5761 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5762 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5763 && TARGET_FCFID"
5764 "")
5766 (define_insn "*fix_trunc<mode>di2_fctidz"
5767 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5768 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fa>")))]
5769 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5770 && TARGET_FCFID"
5771 "@
5772 fctidz %0,%1
5773 xscvdpsxds %x0,%x1"
5774 [(set_attr "type" "fp")])
5776 (define_expand "fixuns_trunc<mode>si2"
5777 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5778 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5779 "TARGET_HARD_FLOAT
5780 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
5781 || <E500_CONVERT>)"
5782 "
5783 {
5784 if (!<E500_CONVERT>)
5785 {
5786 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5787 DONE;
5788 }
5789 }")
5791 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
5792 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5793 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5794 (clobber (match_scratch:DI 2 "=d"))]
5795 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
5796 && TARGET_STFIWX && can_create_pseudo_p ()"
5797 "#"
5798 ""
5799 [(pc)]
5800 {
5801 rtx dest = operands[0];
5802 rtx src = operands[1];
5803 rtx tmp = operands[2];
5805 if (GET_CODE (tmp) == SCRATCH)
5806 tmp = gen_reg_rtx (DImode);
5808 emit_insn (gen_fctiwuz_<mode> (tmp, src));
5809 if (MEM_P (dest))
5810 {
5811 dest = rs6000_address_for_fpconvert (dest);
5812 emit_insn (gen_stfiwx (dest, tmp));
5813 DONE;
5814 }
5815 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5816 {
5817 dest = gen_lowpart (DImode, dest);
5818 emit_move_insn (dest, tmp);
5819 DONE;
5820 }
5821 else
5822 {
5823 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5824 emit_insn (gen_stfiwx (stack, tmp));
5825 emit_move_insn (dest, stack);
5826 DONE;
5827 }
5828 }
5829 [(set_attr "length" "12")
5830 (set_attr "type" "fp")])
5832 (define_expand "fixuns_trunc<mode>di2"
5833 [(set (match_operand:DI 0 "register_operand" "")
5834 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
5835 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
5836 "")
5838 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
5839 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5840 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fa>")))]
5841 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5842 && TARGET_FCTIDUZ"
5843 "@
5844 fctiduz %0,%1
5845 xscvdpuxds %x0,%x1"
5846 [(set_attr "type" "fp")])
5848 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5849 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5850 ; because the first makes it clear that operand 0 is not live
5851 ; before the instruction.
5852 (define_insn "fctiwz_<mode>"
5853 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5854 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
5855 UNSPEC_FCTIWZ))]
5856 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5857 "@
5858 fctiwz %0,%1
5859 xscvdpsxws %x0,%x1"
5860 [(set_attr "type" "fp")])
5862 (define_insn "fctiwuz_<mode>"
5863 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5864 (unspec:DI [(unsigned_fix:SI
5865 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
5866 UNSPEC_FCTIWUZ))]
5867 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
5868 "@
5869 fctiwuz %0,%1
5870 xscvdpuxws %x0,%x1"
5871 [(set_attr "type" "fp")])
5873 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
5874 ;; since the friz instruction does not truncate the value if the floating
5875 ;; point value is < LONG_MIN or > LONG_MAX.
5876 (define_insn "*friz"
5877 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
5878 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,ws"))))]
5879 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
5880 && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
5881 "@
5882 friz %0,%1
5883 xsrdpiz %x0,%x1"
5884 [(set_attr "type" "fp")])
5886 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
5887 ;; load to properly sign extend the value, but at least doing a store, load
5888 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
5889 ;; if we have 32-bit memory ops
5890 (define_insn_and_split "*round32<mode>2_fprs"
5891 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5892 (float:SFDF
5893 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5894 (clobber (match_scratch:DI 2 "=d"))
5895 (clobber (match_scratch:DI 3 "=d"))]
5896 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5897 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
5898 && can_create_pseudo_p ()"
5899 "#"
5900 ""
5901 [(pc)]
5902 {
5903 rtx dest = operands[0];
5904 rtx src = operands[1];
5905 rtx tmp1 = operands[2];
5906 rtx tmp2 = operands[3];
5907 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5909 if (GET_CODE (tmp1) == SCRATCH)
5910 tmp1 = gen_reg_rtx (DImode);
5911 if (GET_CODE (tmp2) == SCRATCH)
5912 tmp2 = gen_reg_rtx (DImode);
5914 emit_insn (gen_fctiwz_<mode> (tmp1, src));
5915 emit_insn (gen_stfiwx (stack, tmp1));
5916 emit_insn (gen_lfiwax (tmp2, stack));
5917 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5918 DONE;
5919 }
5920 [(set_attr "type" "fpload")
5921 (set_attr "length" "16")])
5923 (define_insn_and_split "*roundu32<mode>2_fprs"
5924 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5925 (unsigned_float:SFDF
5926 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5927 (clobber (match_scratch:DI 2 "=d"))
5928 (clobber (match_scratch:DI 3 "=d"))]
5929 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5930 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
5931 && can_create_pseudo_p ()"
5932 "#"
5933 ""
5934 [(pc)]
5935 {
5936 rtx dest = operands[0];
5937 rtx src = operands[1];
5938 rtx tmp1 = operands[2];
5939 rtx tmp2 = operands[3];
5940 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5942 if (GET_CODE (tmp1) == SCRATCH)
5943 tmp1 = gen_reg_rtx (DImode);
5944 if (GET_CODE (tmp2) == SCRATCH)
5945 tmp2 = gen_reg_rtx (DImode);
5947 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
5948 emit_insn (gen_stfiwx (stack, tmp1));
5949 emit_insn (gen_lfiwzx (tmp2, stack));
5950 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5951 DONE;
5952 }
5953 [(set_attr "type" "fpload")
5954 (set_attr "length" "16")])
5956 ;; No VSX equivalent to fctid
5957 (define_insn "lrint<mode>di2"
5958 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5959 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5960 UNSPEC_FCTID))]
5961 "TARGET_<MODE>_FPR && TARGET_FPRND"
5962 "fctid %0,%1"
5963 [(set_attr "type" "fp")])
5965 (define_insn "btrunc<mode>2"
5966 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5967 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5968 UNSPEC_FRIZ))]
5969 "TARGET_<MODE>_FPR && TARGET_FPRND"
5970 "@
5971 friz %0,%1
5972 xsrdpiz %x0,%x1"
5973 [(set_attr "type" "fp")
5974 (set_attr "fp_type" "fp_addsub_<Fs>")])
5976 (define_insn "ceil<mode>2"
5977 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5978 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5979 UNSPEC_FRIP))]
5980 "TARGET_<MODE>_FPR && TARGET_FPRND"
5981 "@
5982 frip %0,%1
5983 xsrdpip %x0,%x1"
5984 [(set_attr "type" "fp")
5985 (set_attr "fp_type" "fp_addsub_<Fs>")])
5987 (define_insn "floor<mode>2"
5988 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5989 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5990 UNSPEC_FRIM))]
5991 "TARGET_<MODE>_FPR && TARGET_FPRND"
5992 "@
5993 frim %0,%1
5994 xsrdpim %x0,%x1"
5995 [(set_attr "type" "fp")
5996 (set_attr "fp_type" "fp_addsub_<Fs>")])
5998 ;; No VSX equivalent to frin
5999 (define_insn "round<mode>2"
6000 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6001 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6002 UNSPEC_FRIN))]
6003 "TARGET_<MODE>_FPR && TARGET_FPRND"
6004 "frin %0,%1"
6005 [(set_attr "type" "fp")
6006 (set_attr "fp_type" "fp_addsub_<Fs>")])
6008 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6009 (define_insn "stfiwx"
6010 [(set (match_operand:SI 0 "memory_operand" "=Z")
6011 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6012 UNSPEC_STFIWX))]
6013 "TARGET_PPC_GFXOPT"
6014 "stfiwx %1,%y0"
6015 [(set_attr "type" "fpstore")])
6017 ;; If we don't have a direct conversion to single precision, don't enable this
6018 ;; conversion for 32-bit without fast math, because we don't have the insn to
6019 ;; generate the fixup swizzle to avoid double rounding problems.
6020 (define_expand "floatsisf2"
6021 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6022 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6023 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6024 && (!TARGET_FPRS
6025 || (TARGET_FPRS
6026 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6027 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6028 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6029 "
6030 {
6031 if (!TARGET_FPRS)
6032 {
6033 if (!REG_P (operands[1]))
6034 operands[1] = force_reg (SImode, operands[1]);
6035 }
6036 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6037 {
6038 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6039 DONE;
6040 }
6041 else if (TARGET_FCFID && TARGET_LFIWAX)
6042 {
6043 rtx dfreg = gen_reg_rtx (DFmode);
6044 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6045 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6046 DONE;
6047 }
6048 else
6049 {
6050 rtx dreg = operands[1];
6051 if (!REG_P (dreg))
6052 dreg = force_reg (SImode, dreg);
6053 dreg = convert_to_mode (DImode, dreg, false);
6054 emit_insn (gen_floatdisf2 (operands[0], dreg));
6055 DONE;
6056 }
6057 }")
6059 (define_expand "floatdidf2"
6060 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6061 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6062 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6063 "")
6065 (define_insn "*floatdidf2_fpr"
6066 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6067 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6068 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6069 "@
6070 fcfid %0,%1
6071 xscvsxddp %x0,%x1"
6072 [(set_attr "type" "fp")])
6074 ; Allow the combiner to merge source memory operands to the conversion so that
6075 ; the optimizer/register allocator doesn't try to load the value too early in a
6076 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6077 ; hit. We will split after reload to avoid the trip through the GPRs
6079 (define_insn_and_split "*floatdidf2_mem"
6080 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6081 (float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
6082 (clobber (match_scratch:DI 2 "=d,wi"))]
6083 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6084 "#"
6085 "&& reload_completed"
6086 [(set (match_dup 2) (match_dup 1))
6087 (set (match_dup 0) (float:DF (match_dup 2)))]
6088 ""
6089 [(set_attr "length" "8")
6090 (set_attr "type" "fpload")])
6092 (define_expand "floatunsdidf2"
6093 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6094 (unsigned_float:DF
6095 (match_operand:DI 1 "gpc_reg_operand" "")))]
6096 "TARGET_HARD_FLOAT && TARGET_FCFIDU"
6097 "")
6099 (define_insn "*floatunsdidf2_fcfidu"
6100 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6101 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6102 "TARGET_HARD_FLOAT && TARGET_FCFIDU"
6103 "@
6104 fcfidu %0,%1
6105 xscvuxddp %x0,%x1"
6106 [(set_attr "type" "fp")
6107 (set_attr "length" "4")])
6109 (define_insn_and_split "*floatunsdidf2_mem"
6110 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6111 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
6112 (clobber (match_scratch:DI 2 "=d,wi"))]
6113 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6114 "#"
6115 "&& reload_completed"
6116 [(set (match_dup 2) (match_dup 1))
6117 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6118 ""
6119 [(set_attr "length" "8")
6120 (set_attr "type" "fpload")])
6122 (define_expand "floatdisf2"
6123 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6124 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6125 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6126 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6127 "
6128 {
6129 if (!TARGET_FCFIDS)
6130 {
6131 rtx val = operands[1];
6132 if (!flag_unsafe_math_optimizations)
6133 {
6134 rtx label = gen_label_rtx ();
6135 val = gen_reg_rtx (DImode);
6136 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6137 emit_label (label);
6138 }
6139 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6140 DONE;
6141 }
6142 }")
6144 (define_insn "floatdisf2_fcfids"
6145 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
6146 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6147 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6148 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6149 "@
6150 fcfids %0,%1
6151 xscvsxdsp %x0,%x1"
6152 [(set_attr "type" "fp")])
6154 (define_insn_and_split "*floatdisf2_mem"
6155 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
6156 (float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
6157 (clobber (match_scratch:DI 2 "=d,d,wi"))]
6158 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6159 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6160 "#"
6161 "&& reload_completed"
6162 [(pc)]
6163 "
6164 {
6165 emit_move_insn (operands[2], operands[1]);
6166 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6167 DONE;
6168 }"
6169 [(set_attr "length" "8")])
6171 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6172 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6173 ;; from double rounding.
6174 ;; Instead of creating a new cpu type for two FP operations, just use fp
6175 (define_insn_and_split "floatdisf2_internal1"
6176 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6177 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6178 (clobber (match_scratch:DF 2 "=d"))]
6179 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6180 && !TARGET_FCFIDS"
6181 "#"
6182 "&& reload_completed"
6183 [(set (match_dup 2)
6184 (float:DF (match_dup 1)))
6185 (set (match_dup 0)
6186 (float_truncate:SF (match_dup 2)))]
6187 ""
6188 [(set_attr "length" "8")
6189 (set_attr "type" "fp")])
6191 ;; Twiddles bits to avoid double rounding.
6192 ;; Bits that might be truncated when converting to DFmode are replaced
6193 ;; by a bit that won't be lost at that stage, but is below the SFmode
6194 ;; rounding position.
6195 (define_expand "floatdisf2_internal2"
6196 [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6197 (const_int 53)))
6198 (clobber (reg:DI CA_REGNO))])
6199 (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6200 (const_int 2047)))
6201 (set (match_dup 3) (plus:DI (match_dup 3)
6202 (const_int 1)))
6203 (set (match_dup 0) (plus:DI (match_dup 0)
6204 (const_int 2047)))
6205 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6206 (const_int 2)))
6207 (set (match_dup 0) (ior:DI (match_dup 0)
6208 (match_dup 1)))
6209 (set (match_dup 0) (and:DI (match_dup 0)
6210 (const_int -2048)))
6211 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6212 (label_ref (match_operand:DI 2 "" ""))
6213 (pc)))
6214 (set (match_dup 0) (match_dup 1))]
6215 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6216 && !TARGET_FCFIDS"
6217 "
6218 {
6219 operands[3] = gen_reg_rtx (DImode);
6220 operands[4] = gen_reg_rtx (CCUNSmode);
6221 }")
6223 (define_expand "floatunsdisf2"
6224 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6225 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6226 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6227 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6228 "")
6230 (define_insn "floatunsdisf2_fcfidus"
6231 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wu")
6232 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6233 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6234 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6235 "@
6236 fcfidus %0,%1
6237 xscvuxdsp %x0,%x1"
6238 [(set_attr "type" "fp")])
6240 (define_insn_and_split "*floatunsdisf2_mem"
6241 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
6242 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
6243 (clobber (match_scratch:DI 2 "=d,d,wi"))]
6244 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6245 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6246 "#"
6247 "&& reload_completed"
6248 [(pc)]
6249 "
6250 {
6251 emit_move_insn (operands[2], operands[1]);
6252 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6253 DONE;
6254 }"
6255 [(set_attr "length" "8")
6256 (set_attr "type" "fpload")])
6257 \f
6258 ;; Define the TImode operations that can be done in a small number
6259 ;; of instructions. The & constraints are to prevent the register
6260 ;; allocator from allocating registers that overlap with the inputs
6261 ;; (for example, having an input in 7,8 and an output in 6,7). We
6262 ;; also allow for the output being the same as one of the inputs.
6264 (define_insn "addti3"
6265 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")
6266 (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")
6267 (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]
6268 "TARGET_64BIT"
6269 {
6270 if (WORDS_BIG_ENDIAN)
6271 return (GET_CODE (operands[2])) != CONST_INT
6272 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6273 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6274 else
6275 return (GET_CODE (operands[2])) != CONST_INT
6276 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6277 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6278 }
6279 [(set_attr "type" "two")
6280 (set_attr "length" "8")])
6282 (define_insn "subti3"
6283 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6284 (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")
6285 (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6286 "TARGET_64BIT"
6287 {
6288 if (WORDS_BIG_ENDIAN)
6289 return (GET_CODE (operands[1]) != CONST_INT)
6290 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6291 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6292 else
6293 return (GET_CODE (operands[1]) != CONST_INT)
6294 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6295 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6296 }
6297 [(set_attr "type" "two")
6298 (set_attr "length" "8")])
6301 ;; Define the DImode operations that can be done in a small number
6302 ;; of instructions. The & constraints are to prevent the register
6303 ;; allocator from allocating registers that overlap with the inputs
6304 ;; (for example, having an input in 7,8 and an output in 6,7). We
6305 ;; also allow for the output being the same as one of the inputs.
6307 (define_insn "*adddi3_noppc64"
6308 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6309 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6310 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6311 "! TARGET_POWERPC64"
6312 "*
6313 {
6314 if (WORDS_BIG_ENDIAN)
6315 return (GET_CODE (operands[2])) != CONST_INT
6316 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6317 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6318 else
6319 return (GET_CODE (operands[2])) != CONST_INT
6320 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6321 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6322 }"
6323 [(set_attr "type" "two")
6324 (set_attr "length" "8")])
6326 (define_insn "*subdi3_noppc64"
6327 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6328 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6329 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6330 "! TARGET_POWERPC64"
6331 "*
6332 {
6333 if (WORDS_BIG_ENDIAN)
6334 return (GET_CODE (operands[1]) != CONST_INT)
6335 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6336 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6337 else
6338 return (GET_CODE (operands[1]) != CONST_INT)
6339 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6340 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6341 }"
6342 [(set_attr "type" "two")
6343 (set_attr "length" "8")])
6345 (define_insn "*negdi2_noppc64"
6346 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6347 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6348 "! TARGET_POWERPC64"
6349 "*
6350 {
6351 return (WORDS_BIG_ENDIAN)
6352 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6353 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6354 }"
6355 [(set_attr "type" "two")
6356 (set_attr "length" "8")])
6359 ;; Shift by a variable amount is too complex to be worth open-coding. We
6360 ;; just handle shifts by constants.
6361 (define_insn "ashrdi3_no_power"
6362 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6363 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6364 (match_operand:SI 2 "const_int_operand" "M,i")))
6365 (clobber (reg:SI CA_REGNO))]
6366 "!TARGET_POWERPC64"
6367 {
6368 switch (which_alternative)
6369 {
6370 default:
6371 gcc_unreachable ();
6372 case 0:
6373 if (WORDS_BIG_ENDIAN)
6374 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6375 else
6376 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6377 case 1:
6378 if (WORDS_BIG_ENDIAN)
6379 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6380 else
6381 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6382 }
6383 }
6384 [(set_attr "type" "two,three")
6385 (set_attr "length" "8,12")])
6387 (define_insn "*ashrdisi3_noppc64be"
6388 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6389 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6390 (const_int 32)) 4))]
6391 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6392 "*
6393 {
6394 if (REGNO (operands[0]) == REGNO (operands[1]))
6395 return \"\";
6396 else
6397 return \"mr %0,%1\";
6398 }"
6399 [(set_attr "length" "4")])
6401 \f
6402 ;; PowerPC64 DImode operations.
6404 (define_insn "*rotldi3_internal4"
6405 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6406 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6407 (match_operand:DI 2 "reg_or_cint_operand" "rn"))
6408 (match_operand:DI 3 "mask64_operand" "n")))]
6409 "TARGET_POWERPC64"
6410 "rld%I2c%B3 %0,%1,%H2,%S3"
6411 [(set_attr "type" "shift")
6412 (set_attr "maybe_var_shift" "yes")])
6414 (define_insn "*rotldi3_internal5"
6415 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6416 (compare:CC (and:DI
6417 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6418 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6419 (match_operand:DI 3 "mask64_operand" "n,n"))
6420 (const_int 0)))
6421 (clobber (match_scratch:DI 4 "=r,r"))]
6422 "TARGET_64BIT"
6423 "@
6424 rld%I2c%B3. %4,%1,%H2,%S3
6425 #"
6426 [(set_attr "type" "shift")
6427 (set_attr "maybe_var_shift" "yes")
6428 (set_attr "dot" "yes")
6429 (set_attr "length" "4,8")])
6431 (define_split
6432 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6433 (compare:CC (and:DI
6434 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6435 (match_operand:DI 2 "reg_or_cint_operand" ""))
6436 (match_operand:DI 3 "mask64_operand" ""))
6437 (const_int 0)))
6438 (clobber (match_scratch:DI 4 ""))]
6439 "TARGET_POWERPC64 && reload_completed"
6440 [(set (match_dup 4)
6441 (and:DI (rotate:DI (match_dup 1)
6442 (match_dup 2))
6443 (match_dup 3)))
6444 (set (match_dup 0)
6445 (compare:CC (match_dup 4)
6446 (const_int 0)))]
6447 "")
6449 (define_insn "*rotldi3_internal6"
6450 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6451 (compare:CC (and:DI
6452 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6453 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6454 (match_operand:DI 3 "mask64_operand" "n,n"))
6455 (const_int 0)))
6456 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6457 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6458 "TARGET_64BIT"
6459 "@
6460 rld%I2c%B3. %0,%1,%H2,%S3
6461 #"
6462 [(set_attr "type" "shift")
6463 (set_attr "maybe_var_shift" "yes")
6464 (set_attr "dot" "yes")
6465 (set_attr "length" "4,8")])
6467 (define_split
6468 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6469 (compare:CC (and:DI
6470 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6471 (match_operand:DI 2 "reg_or_cint_operand" ""))
6472 (match_operand:DI 3 "mask64_operand" ""))
6473 (const_int 0)))
6474 (set (match_operand:DI 0 "gpc_reg_operand" "")
6475 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6476 "TARGET_POWERPC64 && reload_completed"
6477 [(set (match_dup 0)
6478 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6479 (set (match_dup 4)
6480 (compare:CC (match_dup 0)
6481 (const_int 0)))]
6482 "")
6484 (define_insn "*rotldi3_internal7le"
6485 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6486 (zero_extend:DI
6487 (subreg:QI
6488 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6489 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6490 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6491 "rld%I2cl %0,%1,%H2,56"
6492 [(set_attr "type" "shift")
6493 (set_attr "maybe_var_shift" "yes")])
6495 (define_insn "*rotldi3_internal7be"
6496 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6497 (zero_extend:DI
6498 (subreg:QI
6499 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6500 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))]
6501 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6502 "rld%I2cl %0,%1,%H2,56"
6503 [(set_attr "type" "shift")
6504 (set_attr "maybe_var_shift" "yes")])
6506 (define_insn "*rotldi3_internal8le"
6507 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6508 (compare:CC (zero_extend:DI
6509 (subreg:QI
6510 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6511 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6512 (const_int 0)))
6513 (clobber (match_scratch:DI 3 "=r,r"))]
6514 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6515 "@
6516 rld%I2cl. %3,%1,%H2,56
6517 #"
6518 [(set_attr "type" "shift")
6519 (set_attr "maybe_var_shift" "yes")
6520 (set_attr "dot" "yes")
6521 (set_attr "length" "4,8")])
6523 (define_insn "*rotldi3_internal8be"
6524 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6525 (compare:CC (zero_extend:DI
6526 (subreg:QI
6527 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6528 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6529 (const_int 0)))
6530 (clobber (match_scratch:DI 3 "=r,r"))]
6531 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6532 "@
6533 rld%I2cl. %3,%1,%H2,56
6534 #"
6535 [(set_attr "type" "shift")
6536 (set_attr "maybe_var_shift" "yes")
6537 (set_attr "dot" "yes")
6538 (set_attr "length" "4,8")])
6540 (define_split
6541 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6542 (compare:CC (zero_extend:DI
6543 (subreg:QI
6544 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6545 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6546 (const_int 0)))
6547 (clobber (match_scratch:DI 3 ""))]
6548 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6549 [(set (match_dup 3)
6550 (zero_extend:DI (subreg:QI
6551 (rotate:DI (match_dup 1)
6552 (match_dup 2)) 0)))
6553 (set (match_dup 0)
6554 (compare:CC (match_dup 3)
6555 (const_int 0)))]
6556 "")
6558 (define_split
6559 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6560 (compare:CC (zero_extend:DI
6561 (subreg:QI
6562 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6563 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6564 (const_int 0)))
6565 (clobber (match_scratch:DI 3 ""))]
6566 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6567 [(set (match_dup 3)
6568 (zero_extend:DI (subreg:QI
6569 (rotate:DI (match_dup 1)
6570 (match_dup 2)) 7)))
6571 (set (match_dup 0)
6572 (compare:CC (match_dup 3)
6573 (const_int 0)))]
6574 "")
6576 (define_insn "*rotldi3_internal9le"
6577 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6578 (compare:CC (zero_extend:DI
6579 (subreg:QI
6580 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6581 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6582 (const_int 0)))
6583 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6584 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6585 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6586 "@
6587 rld%I2cl. %0,%1,%H2,56
6588 #"
6589 [(set_attr "type" "shift")
6590 (set_attr "maybe_var_shift" "yes")
6591 (set_attr "dot" "yes")
6592 (set_attr "length" "4,8")])
6594 (define_insn "*rotldi3_internal9be"
6595 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6596 (compare:CC (zero_extend:DI
6597 (subreg:QI
6598 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6599 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6600 (const_int 0)))
6601 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6602 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6603 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6604 "@
6605 rld%I2cl. %0,%1,%H2,56
6606 #"
6607 [(set_attr "type" "shift")
6608 (set_attr "maybe_var_shift" "yes")
6609 (set_attr "dot" "yes")
6610 (set_attr "length" "4,8")])
6612 (define_split
6613 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6614 (compare:CC (zero_extend:DI
6615 (subreg:QI
6616 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6617 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6618 (const_int 0)))
6619 (set (match_operand:DI 0 "gpc_reg_operand" "")
6620 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6621 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6622 [(set (match_dup 0)
6623 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6624 (set (match_dup 3)
6625 (compare:CC (match_dup 0)
6626 (const_int 0)))]
6627 "")
6629 (define_split
6630 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6631 (compare:CC (zero_extend:DI
6632 (subreg:QI
6633 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6634 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6635 (const_int 0)))
6636 (set (match_operand:DI 0 "gpc_reg_operand" "")
6637 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6638 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6639 [(set (match_dup 0)
6640 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
6641 (set (match_dup 3)
6642 (compare:CC (match_dup 0)
6643 (const_int 0)))]
6644 "")
6646 (define_insn "*rotldi3_internal10le"
6647 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6648 (zero_extend:DI
6649 (subreg:HI
6650 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6651 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6652 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6653 "rld%I2cl %0,%1,%H2,48"
6654 [(set_attr "type" "shift")
6655 (set_attr "maybe_var_shift" "yes")])
6657 (define_insn "*rotldi3_internal10be"
6658 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6659 (zero_extend:DI
6660 (subreg:HI
6661 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6662 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))]
6663 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6664 "rld%I2cl %0,%1,%H2,48"
6665 [(set_attr "type" "shift")
6666 (set_attr "maybe_var_shift" "yes")])
6668 (define_insn "*rotldi3_internal11le"
6669 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6670 (compare:CC (zero_extend:DI
6671 (subreg:HI
6672 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6673 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6674 (const_int 0)))
6675 (clobber (match_scratch:DI 3 "=r,r"))]
6676 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6677 "@
6678 rld%I2cl. %3,%1,%H2,48
6679 #"
6680 [(set_attr "type" "shift")
6681 (set_attr "maybe_var_shift" "yes")
6682 (set_attr "dot" "yes")
6683 (set_attr "length" "4,8")])
6685 (define_insn "*rotldi3_internal11be"
6686 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6687 (compare:CC (zero_extend:DI
6688 (subreg:HI
6689 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6690 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6691 (const_int 0)))
6692 (clobber (match_scratch:DI 3 "=r,r"))]
6693 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6694 "@
6695 rld%I2cl. %3,%1,%H2,48
6696 #"
6697 [(set_attr "type" "shift")
6698 (set_attr "maybe_var_shift" "yes")
6699 (set_attr "dot" "yes")
6700 (set_attr "length" "4,8")])
6702 (define_split
6703 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6704 (compare:CC (zero_extend:DI
6705 (subreg:HI
6706 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6707 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6708 (const_int 0)))
6709 (clobber (match_scratch:DI 3 ""))]
6710 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6711 [(set (match_dup 3)
6712 (zero_extend:DI (subreg:HI
6713 (rotate:DI (match_dup 1)
6714 (match_dup 2)) 0)))
6715 (set (match_dup 0)
6716 (compare:CC (match_dup 3)
6717 (const_int 0)))]
6718 "")
6720 (define_split
6721 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6722 (compare:CC (zero_extend:DI
6723 (subreg:HI
6724 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6725 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6726 (const_int 0)))
6727 (clobber (match_scratch:DI 3 ""))]
6728 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6729 [(set (match_dup 3)
6730 (zero_extend:DI (subreg:HI
6731 (rotate:DI (match_dup 1)
6732 (match_dup 2)) 6)))
6733 (set (match_dup 0)
6734 (compare:CC (match_dup 3)
6735 (const_int 0)))]
6736 "")
6738 (define_insn "*rotldi3_internal12le"
6739 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6740 (compare:CC (zero_extend:DI
6741 (subreg:HI
6742 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6743 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6744 (const_int 0)))
6745 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6746 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6747 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6748 "@
6749 rld%I2cl. %0,%1,%H2,48
6750 #"
6751 [(set_attr "type" "shift")
6752 (set_attr "maybe_var_shift" "yes")
6753 (set_attr "dot" "yes")
6754 (set_attr "length" "4,8")])
6756 (define_insn "*rotldi3_internal12be"
6757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6758 (compare:CC (zero_extend:DI
6759 (subreg:HI
6760 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6761 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6762 (const_int 0)))
6763 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6764 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6765 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6766 "@
6767 rld%I2cl. %0,%1,%H2,48
6768 #"
6769 [(set_attr "type" "shift")
6770 (set_attr "maybe_var_shift" "yes")
6771 (set_attr "dot" "yes")
6772 (set_attr "length" "4,8")])
6774 (define_split
6775 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6776 (compare:CC (zero_extend:DI
6777 (subreg:HI
6778 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6779 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6780 (const_int 0)))
6781 (set (match_operand:DI 0 "gpc_reg_operand" "")
6782 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6783 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6784 [(set (match_dup 0)
6785 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6786 (set (match_dup 3)
6787 (compare:CC (match_dup 0)
6788 (const_int 0)))]
6789 "")
6791 (define_split
6792 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6793 (compare:CC (zero_extend:DI
6794 (subreg:HI
6795 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6796 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6797 (const_int 0)))
6798 (set (match_operand:DI 0 "gpc_reg_operand" "")
6799 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6800 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6801 [(set (match_dup 0)
6802 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
6803 (set (match_dup 3)
6804 (compare:CC (match_dup 0)
6805 (const_int 0)))]
6806 "")
6808 (define_insn "*rotldi3_internal13le"
6809 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6810 (zero_extend:DI
6811 (subreg:SI
6812 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6813 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6814 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6815 "rld%I2cl %0,%1,%H2,32"
6816 [(set_attr "type" "shift")
6817 (set_attr "maybe_var_shift" "yes")])
6819 (define_insn "*rotldi3_internal13be"
6820 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6821 (zero_extend:DI
6822 (subreg:SI
6823 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6824 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))]
6825 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6826 "rld%I2cl %0,%1,%H2,32"
6827 [(set_attr "type" "shift")
6828 (set_attr "maybe_var_shift" "yes")])
6830 (define_insn "*rotldi3_internal14le"
6831 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6832 (compare:CC (zero_extend:DI
6833 (subreg:SI
6834 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6835 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6836 (const_int 0)))
6837 (clobber (match_scratch:DI 3 "=r,r"))]
6838 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6839 "@
6840 rld%I2cl. %3,%1,%H2,32
6841 #"
6842 [(set_attr "type" "shift")
6843 (set_attr "maybe_var_shift" "yes")
6844 (set_attr "dot" "yes")
6845 (set_attr "length" "4,8")])
6847 (define_insn "*rotldi3_internal14be"
6848 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6849 (compare:CC (zero_extend:DI
6850 (subreg:SI
6851 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6852 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6853 (const_int 0)))
6854 (clobber (match_scratch:DI 3 "=r,r"))]
6855 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6856 "@
6857 rld%I2cl. %3,%1,%H2,32
6858 #"
6859 [(set_attr "type" "shift")
6860 (set_attr "maybe_var_shift" "yes")
6861 (set_attr "dot" "yes")
6862 (set_attr "length" "4,8")])
6864 (define_split
6865 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6866 (compare:CC (zero_extend:DI
6867 (subreg:SI
6868 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6869 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6870 (const_int 0)))
6871 (clobber (match_scratch:DI 3 ""))]
6872 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6873 [(set (match_dup 3)
6874 (zero_extend:DI (subreg:SI
6875 (rotate:DI (match_dup 1)
6876 (match_dup 2)) 0)))
6877 (set (match_dup 0)
6878 (compare:CC (match_dup 3)
6879 (const_int 0)))]
6880 "")
6882 (define_split
6883 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6884 (compare:CC (zero_extend:DI
6885 (subreg:SI
6886 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6887 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
6888 (const_int 0)))
6889 (clobber (match_scratch:DI 3 ""))]
6890 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6891 [(set (match_dup 3)
6892 (zero_extend:DI (subreg:SI
6893 (rotate:DI (match_dup 1)
6894 (match_dup 2)) 4)))
6895 (set (match_dup 0)
6896 (compare:CC (match_dup 3)
6897 (const_int 0)))]
6898 "")
6900 (define_insn "*rotldi3_internal15le"
6901 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6902 (compare:CC (zero_extend:DI
6903 (subreg:SI
6904 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6905 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6906 (const_int 0)))
6907 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6908 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6909 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6910 "@
6911 rld%I2cl. %0,%1,%H2,32
6912 #"
6913 [(set_attr "type" "shift")
6914 (set_attr "maybe_var_shift" "yes")
6915 (set_attr "dot" "yes")
6916 (set_attr "length" "4,8")])
6918 (define_insn "*rotldi3_internal15be"
6919 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6920 (compare:CC (zero_extend:DI
6921 (subreg:SI
6922 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6923 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6924 (const_int 0)))
6925 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6926 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
6927 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6928 "@
6929 rld%I2cl. %0,%1,%H2,32
6930 #"
6931 [(set_attr "type" "shift")
6932 (set_attr "maybe_var_shift" "yes")
6933 (set_attr "dot" "yes")
6934 (set_attr "length" "4,8")])
6936 (define_split
6937 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6938 (compare:CC (zero_extend:DI
6939 (subreg:SI
6940 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6941 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6942 (const_int 0)))
6943 (set (match_operand:DI 0 "gpc_reg_operand" "")
6944 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6945 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6946 [(set (match_dup 0)
6947 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6948 (set (match_dup 3)
6949 (compare:CC (match_dup 0)
6950 (const_int 0)))]
6951 "")
6953 (define_split
6954 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6955 (compare:CC (zero_extend:DI
6956 (subreg:SI
6957 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6958 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
6959 (const_int 0)))
6960 (set (match_operand:DI 0 "gpc_reg_operand" "")
6961 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
6962 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6963 [(set (match_dup 0)
6964 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
6965 (set (match_dup 3)
6966 (compare:CC (match_dup 0)
6967 (const_int 0)))]
6968 "")
6970 (define_insn "*ashldi3_internal4"
6971 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6972 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6973 (match_operand:SI 2 "const_int_operand" "i"))
6974 (match_operand:DI 3 "const_int_operand" "n")))]
6975 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6976 "rldic %0,%1,%H2,%W3"
6977 [(set_attr "type" "shift")])
6979 (define_insn "ashldi3_internal5"
6980 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6981 (compare:CC
6982 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6983 (match_operand:SI 2 "const_int_operand" "i,i"))
6984 (match_operand:DI 3 "const_int_operand" "n,n"))
6985 (const_int 0)))
6986 (clobber (match_scratch:DI 4 "=r,r"))]
6987 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6988 "@
6989 rldic. %4,%1,%H2,%W3
6990 #"
6991 [(set_attr "type" "shift")
6992 (set_attr "dot" "yes")
6993 (set_attr "length" "4,8")])
6995 (define_split
6996 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6997 (compare:CC
6998 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6999 (match_operand:SI 2 "const_int_operand" ""))
7000 (match_operand:DI 3 "const_int_operand" ""))
7001 (const_int 0)))
7002 (clobber (match_scratch:DI 4 ""))]
7003 "TARGET_POWERPC64 && reload_completed
7004 && includes_rldic_lshift_p (operands[2], operands[3])"
7005 [(set (match_dup 4)
7006 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7007 (match_dup 3)))
7008 (set (match_dup 0)
7009 (compare:CC (match_dup 4)
7010 (const_int 0)))]
7011 "")
7013 (define_insn "*ashldi3_internal6"
7014 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7015 (compare:CC
7016 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7017 (match_operand:SI 2 "const_int_operand" "i,i"))
7018 (match_operand:DI 3 "const_int_operand" "n,n"))
7019 (const_int 0)))
7020 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7021 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7022 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7023 "@
7024 rldic. %0,%1,%H2,%W3
7025 #"
7026 [(set_attr "type" "shift")
7027 (set_attr "dot" "yes")
7028 (set_attr "length" "4,8")])
7030 (define_split
7031 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7032 (compare:CC
7033 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7034 (match_operand:SI 2 "const_int_operand" ""))
7035 (match_operand:DI 3 "const_int_operand" ""))
7036 (const_int 0)))
7037 (set (match_operand:DI 0 "gpc_reg_operand" "")
7038 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7039 "TARGET_POWERPC64 && reload_completed
7040 && includes_rldic_lshift_p (operands[2], operands[3])"
7041 [(set (match_dup 0)
7042 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7043 (match_dup 3)))
7044 (set (match_dup 4)
7045 (compare:CC (match_dup 0)
7046 (const_int 0)))]
7047 "")
7049 (define_insn "*ashldi3_internal7"
7050 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7051 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7052 (match_operand:SI 2 "const_int_operand" "i"))
7053 (match_operand:DI 3 "mask64_operand" "n")))]
7054 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7055 "rldicr %0,%1,%H2,%S3"
7056 [(set_attr "type" "shift")])
7058 (define_insn "ashldi3_internal8"
7059 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7060 (compare:CC
7061 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7062 (match_operand:SI 2 "const_int_operand" "i,i"))
7063 (match_operand:DI 3 "mask64_operand" "n,n"))
7064 (const_int 0)))
7065 (clobber (match_scratch:DI 4 "=r,r"))]
7066 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7067 "@
7068 rldicr. %4,%1,%H2,%S3
7069 #"
7070 [(set_attr "type" "shift")
7071 (set_attr "dot" "yes")
7072 (set_attr "length" "4,8")])
7074 (define_split
7075 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7076 (compare:CC
7077 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7078 (match_operand:SI 2 "const_int_operand" ""))
7079 (match_operand:DI 3 "mask64_operand" ""))
7080 (const_int 0)))
7081 (clobber (match_scratch:DI 4 ""))]
7082 "TARGET_POWERPC64 && reload_completed
7083 && includes_rldicr_lshift_p (operands[2], operands[3])"
7084 [(set (match_dup 4)
7085 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7086 (match_dup 3)))
7087 (set (match_dup 0)
7088 (compare:CC (match_dup 4)
7089 (const_int 0)))]
7090 "")
7092 (define_insn "*ashldi3_internal9"
7093 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7094 (compare:CC
7095 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7096 (match_operand:SI 2 "const_int_operand" "i,i"))
7097 (match_operand:DI 3 "mask64_operand" "n,n"))
7098 (const_int 0)))
7099 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7100 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7101 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7102 "@
7103 rldicr. %0,%1,%H2,%S3
7104 #"
7105 [(set_attr "type" "shift")
7106 (set_attr "dot" "yes")
7107 (set_attr "length" "4,8")])
7109 (define_split
7110 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7111 (compare:CC
7112 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7113 (match_operand:SI 2 "const_int_operand" ""))
7114 (match_operand:DI 3 "mask64_operand" ""))
7115 (const_int 0)))
7116 (set (match_operand:DI 0 "gpc_reg_operand" "")
7117 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7118 "TARGET_POWERPC64 && reload_completed
7119 && includes_rldicr_lshift_p (operands[2], operands[3])"
7120 [(set (match_dup 0)
7121 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7122 (match_dup 3)))
7123 (set (match_dup 4)
7124 (compare:CC (match_dup 0)
7125 (const_int 0)))]
7126 "")
7129 (define_insn_and_split "*anddi3_2rld"
7130 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7131 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
7132 (match_operand:DI 2 "and_2rld_operand" "n")))]
7133 "TARGET_POWERPC64"
7134 "#"
7135 ""
7136 [(set (match_dup 0)
7137 (and:DI (rotate:DI (match_dup 1)
7138 (match_dup 4))
7139 (match_dup 5)))
7140 (set (match_dup 0)
7141 (and:DI (rotate:DI (match_dup 0)
7142 (match_dup 6))
7143 (match_dup 7)))]
7144 {
7145 build_mask64_2_operands (operands[2], &operands[4]);
7146 }
7147 [(set_attr "length" "8")])
7149 (define_insn_and_split "*anddi3_2rld_dot"
7150 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7151 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7152 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7153 (const_int 0)))
7154 (clobber (match_scratch:DI 0 "=r,r"))]
7155 "TARGET_64BIT && rs6000_gen_cell_microcode"
7156 "@
7157 #
7158 #"
7159 "&& reload_completed"
7160 [(set (match_dup 0)
7161 (and:DI (rotate:DI (match_dup 1)
7162 (match_dup 4))
7163 (match_dup 5)))
7164 (parallel [(set (match_dup 3)
7165 (compare:CC (and:DI (rotate:DI (match_dup 0)
7166 (match_dup 6))
7167 (match_dup 7))
7168 (const_int 0)))
7169 (clobber (match_dup 0))])]
7170 {
7171 build_mask64_2_operands (operands[2], &operands[4]);
7172 }
7173 [(set_attr "type" "compare")
7174 (set_attr "dot" "yes")
7175 (set_attr "length" "8,12")])
7177 (define_insn_and_split "*anddi3_2rld_dot2"
7178 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7179 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7180 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7181 (const_int 0)))
7182 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7183 (and:DI (match_dup 1)
7184 (match_dup 2)))]
7185 "TARGET_64BIT && rs6000_gen_cell_microcode"
7186 "@
7187 #
7188 #"
7189 "&& reload_completed"
7190 [(set (match_dup 0)
7191 (and:DI (rotate:DI (match_dup 1)
7192 (match_dup 4))
7193 (match_dup 5)))
7194 (parallel [(set (match_dup 3)
7195 (compare:CC (and:DI (rotate:DI (match_dup 0)
7196 (match_dup 6))
7197 (match_dup 7))
7198 (const_int 0)))
7199 (set (match_dup 0)
7200 (and:DI (rotate:DI (match_dup 0)
7201 (match_dup 6))
7202 (match_dup 7)))])]
7203 {
7204 build_mask64_2_operands (operands[2], &operands[4]);
7205 }
7206 [(set_attr "type" "compare")
7207 (set_attr "dot" "yes")
7208 (set_attr "length" "8,12")])
7209 \f
7210 ;; 128-bit logical operations expanders
7212 (define_expand "and<mode>3"
7213 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7214 (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7215 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7216 ""
7217 "")
7219 (define_expand "ior<mode>3"
7220 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7221 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7222 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7223 ""
7224 "")
7226 (define_expand "xor<mode>3"
7227 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7228 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7229 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7230 ""
7231 "")
7233 (define_expand "one_cmpl<mode>2"
7234 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7235 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7236 ""
7237 "")
7239 (define_expand "nor<mode>3"
7240 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7241 (and:BOOL_128
7242 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7243 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7244 ""
7245 "")
7247 (define_expand "andc<mode>3"
7248 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7249 (and:BOOL_128
7250 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7251 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7252 ""
7253 "")
7255 ;; Power8 vector logical instructions.
7256 (define_expand "eqv<mode>3"
7257 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7258 (not:BOOL_128
7259 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7260 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7261 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7262 "")
7264 ;; Rewrite nand into canonical form
7265 (define_expand "nand<mode>3"
7266 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7267 (ior:BOOL_128
7268 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7269 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7270 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7271 "")
7273 ;; The canonical form is to have the negated element first, so we need to
7274 ;; reverse arguments.
7275 (define_expand "orc<mode>3"
7276 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7277 (ior:BOOL_128
7278 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7279 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7280 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7281 "")
7283 ;; 128-bit logical operations insns and split operations
7284 (define_insn_and_split "*and<mode>3_internal"
7285 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7286 (and:BOOL_128
7287 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7288 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))]
7289 ""
7290 {
7291 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7292 return "xxland %x0,%x1,%x2";
7294 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7295 return "vand %0,%1,%2";
7297 return "#";
7298 }
7299 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7300 [(const_int 0)]
7301 {
7302 rs6000_split_logical (operands, AND, false, false, false);
7303 DONE;
7304 }
7305 [(set (attr "type")
7306 (if_then_else
7307 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7308 (const_string "vecsimple")
7309 (const_string "integer")))
7310 (set (attr "length")
7311 (if_then_else
7312 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7313 (const_string "4")
7314 (if_then_else
7315 (match_test "TARGET_POWERPC64")
7316 (const_string "8")
7317 (const_string "16"))))])
7319 ;; 128-bit IOR/XOR
7320 (define_insn_and_split "*bool<mode>3_internal"
7321 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7322 (match_operator:BOOL_128 3 "boolean_or_operator"
7323 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7324 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7325 ""
7326 {
7327 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7328 return "xxl%q3 %x0,%x1,%x2";
7330 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7331 return "v%q3 %0,%1,%2";
7333 return "#";
7334 }
7335 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7336 [(const_int 0)]
7337 {
7338 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false);
7339 DONE;
7340 }
7341 [(set (attr "type")
7342 (if_then_else
7343 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7344 (const_string "vecsimple")
7345 (const_string "integer")))
7346 (set (attr "length")
7347 (if_then_else
7348 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7349 (const_string "4")
7350 (if_then_else
7351 (match_test "TARGET_POWERPC64")
7352 (const_string "8")
7353 (const_string "16"))))])
7355 ;; 128-bit ANDC/ORC
7356 (define_insn_and_split "*boolc<mode>3_internal1"
7357 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7358 (match_operator:BOOL_128 3 "boolean_operator"
7359 [(not:BOOL_128
7360 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
7361 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7362 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7363 {
7364 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7365 return "xxl%q3 %x0,%x1,%x2";
7367 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7368 return "v%q3 %0,%1,%2";
7370 return "#";
7371 }
7372 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7373 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7374 [(const_int 0)]
7375 {
7376 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7377 DONE;
7378 }
7379 [(set (attr "type")
7380 (if_then_else
7381 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7382 (const_string "vecsimple")
7383 (const_string "integer")))
7384 (set (attr "length")
7385 (if_then_else
7386 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7387 (const_string "4")
7388 (if_then_else
7389 (match_test "TARGET_POWERPC64")
7390 (const_string "8")
7391 (const_string "16"))))])
7393 (define_insn_and_split "*boolc<mode>3_internal2"
7394 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7395 (match_operator:TI2 3 "boolean_operator"
7396 [(not:TI2
7397 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7398 (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
7399 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7400 "#"
7401 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7402 [(const_int 0)]
7403 {
7404 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7405 DONE;
7406 }
7407 [(set_attr "type" "integer")
7408 (set (attr "length")
7409 (if_then_else
7410 (match_test "TARGET_POWERPC64")
7411 (const_string "8")
7412 (const_string "16")))])
7414 ;; 128-bit NAND/NOR
7415 (define_insn_and_split "*boolcc<mode>3_internal1"
7416 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7417 (match_operator:BOOL_128 3 "boolean_operator"
7418 [(not:BOOL_128
7419 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
7420 (not:BOOL_128
7421 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
7422 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7423 {
7424 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7425 return "xxl%q3 %x0,%x1,%x2";
7427 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7428 return "v%q3 %0,%1,%2";
7430 return "#";
7431 }
7432 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7433 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7434 [(const_int 0)]
7435 {
7436 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7437 DONE;
7438 }
7439 [(set (attr "type")
7440 (if_then_else
7441 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7442 (const_string "vecsimple")
7443 (const_string "integer")))
7444 (set (attr "length")
7445 (if_then_else
7446 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7447 (const_string "4")
7448 (if_then_else
7449 (match_test "TARGET_POWERPC64")
7450 (const_string "8")
7451 (const_string "16"))))])
7453 (define_insn_and_split "*boolcc<mode>3_internal2"
7454 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7455 (match_operator:TI2 3 "boolean_operator"
7456 [(not:TI2
7457 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7458 (not:TI2
7459 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
7460 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7461 "#"
7462 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7463 [(const_int 0)]
7464 {
7465 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7466 DONE;
7467 }
7468 [(set_attr "type" "integer")
7469 (set (attr "length")
7470 (if_then_else
7471 (match_test "TARGET_POWERPC64")
7472 (const_string "8")
7473 (const_string "16")))])
7476 ;; 128-bit EQV
7477 (define_insn_and_split "*eqv<mode>3_internal1"
7478 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7479 (not:BOOL_128
7480 (xor:BOOL_128
7481 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
7482 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
7483 "TARGET_P8_VECTOR"
7484 {
7485 if (vsx_register_operand (operands[0], <MODE>mode))
7486 return "xxleqv %x0,%x1,%x2";
7488 return "#";
7489 }
7490 "TARGET_P8_VECTOR && reload_completed
7491 && int_reg_operand (operands[0], <MODE>mode)"
7492 [(const_int 0)]
7493 {
7494 rs6000_split_logical (operands, XOR, true, false, false);
7495 DONE;
7496 }
7497 [(set (attr "type")
7498 (if_then_else
7499 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7500 (const_string "vecsimple")
7501 (const_string "integer")))
7502 (set (attr "length")
7503 (if_then_else
7504 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7505 (const_string "4")
7506 (if_then_else
7507 (match_test "TARGET_POWERPC64")
7508 (const_string "8")
7509 (const_string "16"))))])
7511 (define_insn_and_split "*eqv<mode>3_internal2"
7512 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7513 (not:TI2
7514 (xor:TI2
7515 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
7516 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
7517 "!TARGET_P8_VECTOR"
7518 "#"
7519 "reload_completed && !TARGET_P8_VECTOR"
7520 [(const_int 0)]
7521 {
7522 rs6000_split_logical (operands, XOR, true, false, false);
7523 DONE;
7524 }
7525 [(set_attr "type" "integer")
7526 (set (attr "length")
7527 (if_then_else
7528 (match_test "TARGET_POWERPC64")
7529 (const_string "8")
7530 (const_string "16")))])
7532 ;; 128-bit one's complement
7533 (define_insn_and_split "*one_cmpl<mode>3_internal"
7534 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7535 (not:BOOL_128
7536 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
7537 ""
7538 {
7539 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7540 return "xxlnor %x0,%x1,%x1";
7542 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7543 return "vnor %0,%1,%1";
7545 return "#";
7546 }
7547 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7548 [(const_int 0)]
7549 {
7550 rs6000_split_logical (operands, NOT, false, false, false);
7551 DONE;
7552 }
7553 [(set (attr "type")
7554 (if_then_else
7555 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7556 (const_string "vecsimple")
7557 (const_string "integer")))
7558 (set (attr "length")
7559 (if_then_else
7560 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7561 (const_string "4")
7562 (if_then_else
7563 (match_test "TARGET_POWERPC64")
7564 (const_string "8")
7565 (const_string "16"))))])
7567 \f
7568 ;; Now define ways of moving data around.
7570 ;; Set up a register with a value from the GOT table
7572 (define_expand "movsi_got"
7573 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7574 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7575 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7576 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7577 "
7578 {
7579 if (GET_CODE (operands[1]) == CONST)
7580 {
7581 rtx offset = const0_rtx;
7582 HOST_WIDE_INT value;
7584 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7585 value = INTVAL (offset);
7586 if (value != 0)
7587 {
7588 rtx tmp = (!can_create_pseudo_p ()
7589 ? operands[0]
7590 : gen_reg_rtx (Pmode));
7591 emit_insn (gen_movsi_got (tmp, operands[1]));
7592 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7593 DONE;
7594 }
7595 }
7597 operands[2] = rs6000_got_register (operands[1]);
7598 }")
7600 (define_insn "*movsi_got_internal"
7601 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7602 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7603 (match_operand:SI 2 "gpc_reg_operand" "b")]
7604 UNSPEC_MOVSI_GOT))]
7605 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7606 "lwz %0,%a1@got(%2)"
7607 [(set_attr "type" "load")])
7609 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7610 ;; didn't get allocated to a hard register.
7611 (define_split
7612 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7613 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7614 (match_operand:SI 2 "memory_operand" "")]
7615 UNSPEC_MOVSI_GOT))]
7616 "DEFAULT_ABI == ABI_V4
7617 && flag_pic == 1
7618 && (reload_in_progress || reload_completed)"
7619 [(set (match_dup 0) (match_dup 2))
7620 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7621 UNSPEC_MOVSI_GOT))]
7622 "")
7624 ;; For SI, we special-case integers that can't be loaded in one insn. We
7625 ;; do the load 16-bits at a time. We could do this by loading from memory,
7626 ;; and this is even supposed to be faster, but it is simpler not to get
7627 ;; integers in the TOC.
7628 (define_insn "movsi_low"
7629 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7630 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7631 (match_operand 2 "" ""))))]
7632 "TARGET_MACHO && ! TARGET_64BIT"
7633 "lwz %0,lo16(%2)(%1)"
7634 [(set_attr "type" "load")
7635 (set_attr "length" "4")])
7637 (define_insn "*movsi_internal1"
7638 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
7639 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
7640 "!TARGET_SINGLE_FPU &&
7641 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7642 "@
7643 mr %0,%1
7644 la %0,%a1
7645 lwz%U1%X1 %0,%1
7646 stw%U0%X0 %1,%0
7647 li %0,%1
7648 lis %0,%v1
7649 #
7650 mf%1 %0
7651 mt%0 %1
7652 mt%0 %1
7653 nop"
7654 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
7655 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
7657 (define_insn "*movsi_internal1_single"
7658 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
7659 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
7660 "TARGET_SINGLE_FPU &&
7661 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7662 "@
7663 mr %0,%1
7664 la %0,%a1
7665 lwz%U1%X1 %0,%1
7666 stw%U0%X0 %1,%0
7667 li %0,%1
7668 lis %0,%v1
7669 #
7670 mf%1 %0
7671 mt%0 %1
7672 mt%0 %1
7673 nop
7674 stfs%U0%X0 %1,%0
7675 lfs%U1%X1 %0,%1"
7676 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
7677 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7679 ;; Split a load of a large constant into the appropriate two-insn
7680 ;; sequence.
7682 (define_split
7683 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7684 (match_operand:SI 1 "const_int_operand" ""))]
7685 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7686 && (INTVAL (operands[1]) & 0xffff) != 0"
7687 [(set (match_dup 0)
7688 (match_dup 2))
7689 (set (match_dup 0)
7690 (ior:SI (match_dup 0)
7691 (match_dup 3)))]
7692 "
7693 {
7694 if (rs6000_emit_set_const (operands[0], operands[1]))
7695 DONE;
7696 else
7697 FAIL;
7698 }")
7700 (define_insn "*mov<mode>_internal2"
7701 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7702 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7703 (const_int 0)))
7704 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7705 ""
7706 "@
7707 cmp<wd>i %2,%0,0
7708 mr. %0,%1
7709 #"
7710 [(set_attr "type" "cmp,logical,cmp")
7711 (set_attr "dot" "yes")
7712 (set_attr "length" "4,4,8")])
7714 (define_split
7715 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
7716 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7717 (const_int 0)))
7718 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7719 "reload_completed"
7720 [(set (match_dup 0) (match_dup 1))
7721 (set (match_dup 2)
7722 (compare:CC (match_dup 0)
7723 (const_int 0)))]
7724 "")
7725 \f
7726 (define_insn "*movhi_internal"
7727 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7728 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7729 "gpc_reg_operand (operands[0], HImode)
7730 || gpc_reg_operand (operands[1], HImode)"
7731 "@
7732 mr %0,%1
7733 lhz%U1%X1 %0,%1
7734 sth%U0%X0 %1,%0
7735 li %0,%w1
7736 mf%1 %0
7737 mt%0 %1
7738 nop"
7739 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7741 (define_expand "mov<mode>"
7742 [(set (match_operand:INT 0 "general_operand" "")
7743 (match_operand:INT 1 "any_operand" ""))]
7744 ""
7745 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7747 (define_insn "*movqi_internal"
7748 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7749 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7750 "gpc_reg_operand (operands[0], QImode)
7751 || gpc_reg_operand (operands[1], QImode)"
7752 "@
7753 mr %0,%1
7754 lbz%U1%X1 %0,%1
7755 stb%U0%X0 %1,%0
7756 li %0,%1
7757 mf%1 %0
7758 mt%0 %1
7759 nop"
7760 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7761 \f
7762 ;; Here is how to move condition codes around. When we store CC data in
7763 ;; an integer register or memory, we store just the high-order 4 bits.
7764 ;; This lets us not shift in the most common case of CR0.
7765 (define_expand "movcc"
7766 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7767 (match_operand:CC 1 "nonimmediate_operand" ""))]
7768 ""
7769 "")
7771 (define_insn "*movcc_internal1"
7772 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
7773 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
7774 "register_operand (operands[0], CCmode)
7775 || register_operand (operands[1], CCmode)"
7776 "@
7777 mcrf %0,%1
7778 mtcrf 128,%1
7779 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
7780 crxor %0,%0,%0
7781 mfcr %0%Q1
7782 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
7783 mr %0,%1
7784 li %0,%1
7785 mf%1 %0
7786 mt%0 %1
7787 lwz%U1%X1 %0,%1
7788 stw%U0%X0 %1,%0"
7789 [(set (attr "type")
7790 (cond [(eq_attr "alternative" "0,3")
7791 (const_string "cr_logical")
7792 (eq_attr "alternative" "1,2")
7793 (const_string "mtcr")
7794 (eq_attr "alternative" "6,7")
7795 (const_string "integer")
7796 (eq_attr "alternative" "8")
7797 (const_string "mfjmpr")
7798 (eq_attr "alternative" "9")
7799 (const_string "mtjmpr")
7800 (eq_attr "alternative" "10")
7801 (const_string "load")
7802 (eq_attr "alternative" "11")
7803 (const_string "store")
7804 (match_test "TARGET_MFCRF")
7805 (const_string "mfcrf")
7806 ]
7807 (const_string "mfcr")))
7808 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
7809 \f
7810 ;; For floating-point, we normally deal with the floating-point registers
7811 ;; unless -msoft-float is used. The sole exception is that parameter passing
7812 ;; can produce floating-point values in fixed-point registers. Unless the
7813 ;; value is a simple constant or already in memory, we deal with this by
7814 ;; allocating memory and copying the value explicitly via that memory location.
7816 ;; Move 32-bit binary/decimal floating point
7817 (define_expand "mov<mode>"
7818 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
7819 (match_operand:FMOVE32 1 "any_operand" ""))]
7820 "<fmove_ok>"
7821 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7823 (define_split
7824 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
7825 (match_operand:FMOVE32 1 "const_double_operand" ""))]
7826 "reload_completed
7827 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7828 || (GET_CODE (operands[0]) == SUBREG
7829 && GET_CODE (SUBREG_REG (operands[0])) == REG
7830 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7831 [(set (match_dup 2) (match_dup 3))]
7832 "
7833 {
7834 long l;
7835 REAL_VALUE_TYPE rv;
7837 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7838 <real_value_to_target> (rv, l);
7840 if (! TARGET_POWERPC64)
7841 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
7842 else
7843 operands[2] = gen_lowpart (SImode, operands[0]);
7845 operands[3] = gen_int_mode (l, SImode);
7846 }")
7848 (define_insn "mov<mode>_hardfloat"
7849 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,<f32_lr>,<f32_sm>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
7850 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r,h,0,G,Fn"))]
7851 "(gpc_reg_operand (operands[0], <MODE>mode)
7852 || gpc_reg_operand (operands[1], <MODE>mode))
7853 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
7854 "@
7855 mr %0,%1
7856 lwz%U1%X1 %0,%1
7857 stw%U0%X0 %1,%0
7858 fmr %0,%1
7859 xxlor %x0,%x1,%x1
7860 xxlxor %x0,%x0,%x0
7861 <f32_li>
7862 <f32_si>
7863 <f32_lv>
7864 <f32_sv>
7865 mtvsrwz %x0,%1
7866 mfvsrwz %0,%x1
7867 mt%0 %1
7868 mf%1 %0
7869 nop
7870 #
7871 #"
7872 [(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*,*,*")
7873 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
7875 (define_insn "*mov<mode>_softfloat"
7876 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
7877 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
7878 "(gpc_reg_operand (operands[0], <MODE>mode)
7879 || gpc_reg_operand (operands[1], <MODE>mode))
7880 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7881 "@
7882 mr %0,%1
7883 mt%0 %1
7884 mf%1 %0
7885 lwz%U1%X1 %0,%1
7886 stw%U0%X0 %1,%0
7887 li %0,%1
7888 lis %0,%v1
7889 #
7890 #
7891 nop"
7892 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
7893 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
7895 \f
7896 ;; Move 64-bit binary/decimal floating point
7897 (define_expand "mov<mode>"
7898 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
7899 (match_operand:FMOVE64 1 "any_operand" ""))]
7900 ""
7901 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7903 (define_split
7904 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7905 (match_operand:FMOVE64 1 "const_int_operand" ""))]
7906 "! TARGET_POWERPC64 && reload_completed
7907 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7908 || (GET_CODE (operands[0]) == SUBREG
7909 && GET_CODE (SUBREG_REG (operands[0])) == REG
7910 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7911 [(set (match_dup 2) (match_dup 4))
7912 (set (match_dup 3) (match_dup 1))]
7913 "
7914 {
7915 int endian = (WORDS_BIG_ENDIAN == 0);
7916 HOST_WIDE_INT value = INTVAL (operands[1]);
7918 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
7919 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
7920 operands[4] = GEN_INT (value >> 32);
7921 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7922 }")
7924 (define_split
7925 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7926 (match_operand:FMOVE64 1 "const_double_operand" ""))]
7927 "! TARGET_POWERPC64 && reload_completed
7928 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7929 || (GET_CODE (operands[0]) == SUBREG
7930 && GET_CODE (SUBREG_REG (operands[0])) == REG
7931 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7932 [(set (match_dup 2) (match_dup 4))
7933 (set (match_dup 3) (match_dup 5))]
7934 "
7935 {
7936 int endian = (WORDS_BIG_ENDIAN == 0);
7937 long l[2];
7938 REAL_VALUE_TYPE rv;
7940 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7941 <real_value_to_target> (rv, l);
7943 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
7944 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
7945 operands[4] = gen_int_mode (l[endian], SImode);
7946 operands[5] = gen_int_mode (l[1 - endian], SImode);
7947 }")
7949 (define_split
7950 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7951 (match_operand:FMOVE64 1 "const_double_operand" ""))]
7952 "TARGET_POWERPC64 && reload_completed
7953 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7954 || (GET_CODE (operands[0]) == SUBREG
7955 && GET_CODE (SUBREG_REG (operands[0])) == REG
7956 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7957 [(set (match_dup 2) (match_dup 3))]
7958 "
7959 {
7960 int endian = (WORDS_BIG_ENDIAN == 0);
7961 long l[2];
7962 REAL_VALUE_TYPE rv;
7963 HOST_WIDE_INT val;
7965 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7966 <real_value_to_target> (rv, l);
7968 operands[2] = gen_lowpart (DImode, operands[0]);
7969 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7970 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7971 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7973 operands[3] = gen_int_mode (val, DImode);
7974 }")
7976 ;; Don't have reload use general registers to load a constant. It is
7977 ;; less efficient than loading the constant into an FP register, since
7978 ;; it will probably be used there.
7980 ;; The move constraints are ordered to prefer floating point registers before
7981 ;; general purpose registers to avoid doing a store and a load to get the value
7982 ;; into a floating point register when it is needed for a floating point
7983 ;; operation. Prefer traditional floating point registers over VSX registers,
7984 ;; since the D-form version of the memory instructions does not need a GPR for
7985 ;; reloading.
7987 (define_insn "*mov<mode>_hardfloat32"
7988 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,!r,!r,!r")
7989 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,G,H,F"))]
7990 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
7991 && (gpc_reg_operand (operands[0], <MODE>mode)
7992 || gpc_reg_operand (operands[1], <MODE>mode))"
7993 "@
7994 stfd%U0%X0 %1,%0
7995 lfd%U1%X1 %0,%1
7996 fmr %0,%1
7997 lxsd%U1x %x0,%y1
7998 stxsd%U0x %x1,%y0
7999 xxlor %x0,%x1,%x1
8000 xxlxor %x0,%x0,%x0
8001 #
8002 #
8003 #
8004 #
8005 #
8006 #"
8007 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,two,fp,fp,*")
8008 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
8010 (define_insn "*mov<mode>_softfloat32"
8011 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8012 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
8013 "! TARGET_POWERPC64
8014 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8015 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
8016 || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
8017 && (gpc_reg_operand (operands[0], <MODE>mode)
8018 || gpc_reg_operand (operands[1], <MODE>mode))"
8019 "#"
8020 [(set_attr "type" "store,load,two,*,*,*")
8021 (set_attr "length" "8,8,8,8,12,16")])
8023 ; ld/std require word-aligned displacements -> 'Y' constraint.
8024 ; List Y->r and r->Y before r->r for reload.
8025 (define_insn "*mov<mode>_hardfloat64"
8026 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,<f64_dm>")
8027 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,r,h,0,G,H,F,wg,r,<f64_dm>,r"))]
8028 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8029 && (gpc_reg_operand (operands[0], <MODE>mode)
8030 || gpc_reg_operand (operands[1], <MODE>mode))"
8031 "@
8032 stfd%U0%X0 %1,%0
8033 lfd%U1%X1 %0,%1
8034 fmr %0,%1
8035 lxsd%U1x %x0,%y1
8036 stxsd%U0x %x1,%y0
8037 xxlor %x0,%x1,%x1
8038 xxlxor %x0,%x0,%x0
8039 std%U0%X0 %1,%0
8040 ld%U1%X1 %0,%1
8041 mr %0,%1
8042 mt%0 %1
8043 mf%1 %0
8044 nop
8045 #
8046 #
8047 #
8048 mftgpr %0,%1
8049 mffgpr %0,%1
8050 mfvsrd %0,%x1
8051 mtvsrd %x0,%1"
8052 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,*,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr,mftgpr,mffgpr")
8053 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
8055 (define_insn "*mov<mode>_softfloat64"
8056 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8057 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8058 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8059 && (gpc_reg_operand (operands[0], <MODE>mode)
8060 || gpc_reg_operand (operands[1], <MODE>mode))"
8061 "@
8062 std%U0%X0 %1,%0
8063 ld%U1%X1 %0,%1
8064 mr %0,%1
8065 mt%0 %1
8066 mf%1 %0
8067 #
8068 #
8069 #
8070 nop"
8071 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8072 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8073 \f
8074 (define_expand "mov<mode>"
8075 [(set (match_operand:FMOVE128 0 "general_operand" "")
8076 (match_operand:FMOVE128 1 "any_operand" ""))]
8077 ""
8078 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8080 ;; It's important to list Y->r and r->Y before r->r because otherwise
8081 ;; reload, given m->r, will try to pick r->r and reload it, which
8082 ;; doesn't make progress.
8084 ;; We can't split little endian direct moves of TDmode, because the words are
8085 ;; not swapped like they are for TImode or TFmode. Subregs therefore are
8086 ;; problematical. Don't allow direct move for this case.
8088 (define_insn_and_split "*mov<mode>_64bit_dm"
8089 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r,r,wm")
8090 (match_operand:FMOVE128 1 "input_operand" "d,m,d,j,r,jYGHF,r,wm,r"))]
8091 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8092 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
8093 && (gpc_reg_operand (operands[0], <MODE>mode)
8094 || gpc_reg_operand (operands[1], <MODE>mode))"
8095 "#"
8096 "&& reload_completed"
8097 [(pc)]
8098 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8099 [(set_attr "length" "8,8,8,8,12,12,8,8,8")])
8101 (define_insn_and_split "*movtd_64bit_nodm"
8102 [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r")
8103 (match_operand:TD 1 "input_operand" "d,m,d,j,r,jYGHF,r"))]
8104 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
8105 && (gpc_reg_operand (operands[0], TDmode)
8106 || gpc_reg_operand (operands[1], TDmode))"
8107 "#"
8108 "&& reload_completed"
8109 [(pc)]
8110 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8111 [(set_attr "length" "8,8,8,8,12,12,8")])
8113 (define_insn_and_split "*mov<mode>_32bit"
8114 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r")
8115 (match_operand:FMOVE128 1 "input_operand" "d,m,d,j,r,jYGHF,r"))]
8116 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
8117 && (gpc_reg_operand (operands[0], <MODE>mode)
8118 || gpc_reg_operand (operands[1], <MODE>mode))"
8119 "#"
8120 "&& reload_completed"
8121 [(pc)]
8122 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8123 [(set_attr "length" "8,8,8,8,20,20,16")])
8125 (define_insn_and_split "*mov<mode>_softfloat"
8126 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8127 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
8128 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
8129 && (gpc_reg_operand (operands[0], <MODE>mode)
8130 || gpc_reg_operand (operands[1], <MODE>mode))"
8131 "#"
8132 "&& reload_completed"
8133 [(pc)]
8134 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8135 [(set_attr "length" "20,20,16")])
8137 ;; If we are using -ffast-math, easy_fp_constant assumes all constants are
8138 ;; 'easy' in order to allow for reciprocal estimation. Make sure the constant
8139 ;; is in the constant pool before reload occurs. This simplifies accessing
8140 ;; scalars in the traditional Altivec registers.
8142 (define_split
8143 [(set (match_operand:SFDF 0 "register_operand" "")
8144 (match_operand:SFDF 1 "memory_fp_constant" ""))]
8145 "TARGET_<MODE>_FPR && flag_unsafe_math_optimizations
8146 && !reload_in_progress && !reload_completed && !lra_in_progress"
8147 [(set (match_dup 0) (match_dup 2))]
8148 {
8149 operands[2] = validize_mem (force_const_mem (<MODE>mode, operands[1]));
8150 })
8152 (define_expand "extenddftf2"
8153 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8154 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8155 "!TARGET_IEEEQUAD
8156 && TARGET_HARD_FLOAT
8157 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8158 && TARGET_LONG_DOUBLE_128"
8159 {
8160 if (TARGET_E500_DOUBLE)
8161 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8162 else
8163 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8164 DONE;
8165 })
8167 (define_expand "extenddftf2_fprs"
8168 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8169 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8170 (use (match_dup 2))])]
8171 "!TARGET_IEEEQUAD
8172 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8173 && TARGET_LONG_DOUBLE_128"
8174 {
8175 operands[2] = CONST0_RTX (DFmode);
8176 /* Generate GOT reference early for SVR4 PIC. */
8177 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8178 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8179 })
8181 (define_insn_and_split "*extenddftf2_internal"
8182 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8183 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8184 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8185 "!TARGET_IEEEQUAD
8186 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8187 && TARGET_LONG_DOUBLE_128"
8188 "#"
8189 "&& reload_completed"
8190 [(pc)]
8191 {
8192 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8193 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8194 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8195 operands[1]);
8196 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8197 operands[2]);
8198 DONE;
8199 })
8201 (define_expand "extendsftf2"
8202 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8203 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8204 "!TARGET_IEEEQUAD
8205 && TARGET_HARD_FLOAT
8206 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8207 && TARGET_LONG_DOUBLE_128"
8208 {
8209 rtx tmp = gen_reg_rtx (DFmode);
8210 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8211 emit_insn (gen_extenddftf2 (operands[0], tmp));
8212 DONE;
8213 })
8215 (define_expand "trunctfdf2"
8216 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8217 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8218 "!TARGET_IEEEQUAD
8219 && TARGET_HARD_FLOAT
8220 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8221 && TARGET_LONG_DOUBLE_128"
8222 "")
8224 (define_insn_and_split "trunctfdf2_internal1"
8225 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8226 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8227 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8228 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8229 "@
8230 #
8231 fmr %0,%1"
8232 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8233 [(const_int 0)]
8234 {
8235 emit_note (NOTE_INSN_DELETED);
8236 DONE;
8237 }
8238 [(set_attr "type" "fp")])
8240 (define_insn "trunctfdf2_internal2"
8241 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8242 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8243 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8244 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8245 && TARGET_LONG_DOUBLE_128"
8246 "fadd %0,%1,%L1"
8247 [(set_attr "type" "fp")
8248 (set_attr "fp_type" "fp_addsub_d")])
8250 (define_expand "trunctfsf2"
8251 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8252 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8253 "!TARGET_IEEEQUAD
8254 && TARGET_HARD_FLOAT
8255 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8256 && TARGET_LONG_DOUBLE_128"
8257 {
8258 if (TARGET_E500_DOUBLE)
8259 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8260 else
8261 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8262 DONE;
8263 })
8265 (define_insn_and_split "trunctfsf2_fprs"
8266 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8267 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8268 (clobber (match_scratch:DF 2 "=d"))]
8269 "!TARGET_IEEEQUAD
8270 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8271 && TARGET_LONG_DOUBLE_128"
8272 "#"
8273 "&& reload_completed"
8274 [(set (match_dup 2)
8275 (float_truncate:DF (match_dup 1)))
8276 (set (match_dup 0)
8277 (float_truncate:SF (match_dup 2)))]
8278 "")
8280 (define_expand "floatsitf2"
8281 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8282 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8283 "!TARGET_IEEEQUAD
8284 && TARGET_HARD_FLOAT
8285 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8286 && TARGET_LONG_DOUBLE_128"
8287 {
8288 rtx tmp = gen_reg_rtx (DFmode);
8289 expand_float (tmp, operands[1], false);
8290 emit_insn (gen_extenddftf2 (operands[0], tmp));
8291 DONE;
8292 })
8294 ; fadd, but rounding towards zero.
8295 ; This is probably not the optimal code sequence.
8296 (define_insn "fix_trunc_helper"
8297 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8298 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8299 UNSPEC_FIX_TRUNC_TF))
8300 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8301 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8302 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8303 [(set_attr "type" "fp")
8304 (set_attr "length" "20")])
8306 (define_expand "fix_trunctfsi2"
8307 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8308 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8309 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
8310 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
8311 {
8312 if (TARGET_E500_DOUBLE)
8313 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8314 else
8315 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8316 DONE;
8317 })
8319 (define_expand "fix_trunctfsi2_fprs"
8320 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8321 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8322 (clobber (match_dup 2))
8323 (clobber (match_dup 3))
8324 (clobber (match_dup 4))
8325 (clobber (match_dup 5))])]
8326 "!TARGET_IEEEQUAD
8327 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8328 {
8329 operands[2] = gen_reg_rtx (DFmode);
8330 operands[3] = gen_reg_rtx (DFmode);
8331 operands[4] = gen_reg_rtx (DImode);
8332 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
8333 })
8335 (define_insn_and_split "*fix_trunctfsi2_internal"
8336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8337 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8338 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8339 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8340 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8341 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8342 "!TARGET_IEEEQUAD
8343 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8344 "#"
8345 ""
8346 [(pc)]
8347 {
8348 rtx lowword;
8349 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8351 gcc_assert (MEM_P (operands[5]));
8352 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8354 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
8355 emit_move_insn (operands[5], operands[4]);
8356 emit_move_insn (operands[0], lowword);
8357 DONE;
8358 })
8360 (define_expand "negtf2"
8361 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8362 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8363 "!TARGET_IEEEQUAD
8364 && TARGET_HARD_FLOAT
8365 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8366 && TARGET_LONG_DOUBLE_128"
8367 "")
8369 (define_insn "negtf2_internal"
8370 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
8371 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8372 "!TARGET_IEEEQUAD
8373 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8374 "*
8375 {
8376 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8377 return \"fneg %L0,%L1\;fneg %0,%1\";
8378 else
8379 return \"fneg %0,%1\;fneg %L0,%L1\";
8380 }"
8381 [(set_attr "type" "fp")
8382 (set_attr "length" "8")])
8384 (define_expand "abstf2"
8385 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8386 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8387 "!TARGET_IEEEQUAD
8388 && TARGET_HARD_FLOAT
8389 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8390 && TARGET_LONG_DOUBLE_128"
8391 "
8392 {
8393 rtx label = gen_label_rtx ();
8394 if (TARGET_E500_DOUBLE)
8395 {
8396 if (flag_finite_math_only && !flag_trapping_math)
8397 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8398 else
8399 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8400 }
8401 else
8402 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8403 emit_label (label);
8404 DONE;
8405 }")
8407 (define_expand "abstf2_internal"
8408 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8409 (match_operand:TF 1 "gpc_reg_operand" ""))
8410 (set (match_dup 3) (match_dup 5))
8411 (set (match_dup 5) (abs:DF (match_dup 5)))
8412 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8413 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8414 (label_ref (match_operand 2 "" ""))
8415 (pc)))
8416 (set (match_dup 6) (neg:DF (match_dup 6)))]
8417 "!TARGET_IEEEQUAD
8418 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8419 && TARGET_LONG_DOUBLE_128"
8420 "
8421 {
8422 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8423 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8424 operands[3] = gen_reg_rtx (DFmode);
8425 operands[4] = gen_reg_rtx (CCFPmode);
8426 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8427 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8428 }")
8429 \f
8430 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
8431 ;; must have 3 arguments, and scratch register constraint must be a single
8432 ;; constraint.
8434 ;; Reload patterns to support gpr load/store with misaligned mem.
8435 ;; and multiple gpr load/store at offset >= 0xfffc
8436 (define_expand "reload_<mode>_store"
8437 [(parallel [(match_operand 0 "memory_operand" "=m")
8438 (match_operand 1 "gpc_reg_operand" "r")
8439 (match_operand:GPR 2 "register_operand" "=&b")])]
8440 ""
8441 {
8442 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
8443 DONE;
8444 })
8446 (define_expand "reload_<mode>_load"
8447 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
8448 (match_operand 1 "memory_operand" "m")
8449 (match_operand:GPR 2 "register_operand" "=b")])]
8450 ""
8451 {
8452 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
8453 DONE;
8454 })
8456 \f
8457 ;; Reload patterns for various types using the vector registers. We may need
8458 ;; an additional base register to convert the reg+offset addressing to reg+reg
8459 ;; for vector registers and reg+reg or (reg+reg)&(-16) addressing to just an
8460 ;; index register for gpr registers.
8461 (define_expand "reload_<RELOAD:mode>_<P:mptrsize>_store"
8462 [(parallel [(match_operand:RELOAD 0 "memory_operand" "m")
8463 (match_operand:RELOAD 1 "gpc_reg_operand" "wa")
8464 (match_operand:P 2 "register_operand" "=b")])]
8465 "<P:tptrsize>"
8466 {
8467 rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true);
8468 DONE;
8469 })
8471 (define_expand "reload_<RELOAD:mode>_<P:mptrsize>_load"
8472 [(parallel [(match_operand:RELOAD 0 "gpc_reg_operand" "wa")
8473 (match_operand:RELOAD 1 "memory_operand" "m")
8474 (match_operand:P 2 "register_operand" "=b")])]
8475 "<P:tptrsize>"
8476 {
8477 rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false);
8478 DONE;
8479 })
8482 ;; Reload sometimes tries to move the address to a GPR, and can generate
8483 ;; invalid RTL for addresses involving AND -16. Allow addresses involving
8484 ;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16.
8486 (define_insn_and_split "*vec_reload_and_plus_<mptrsize>"
8487 [(set (match_operand:P 0 "gpc_reg_operand" "=b")
8488 (and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
8489 (match_operand:P 2 "reg_or_cint_operand" "rI"))
8490 (const_int -16)))]
8491 "TARGET_ALTIVEC && (reload_in_progress || reload_completed)"
8492 "#"
8493 "&& reload_completed"
8494 [(set (match_dup 0)
8495 (plus:P (match_dup 1)
8496 (match_dup 2)))
8497 (set (match_dup 0)
8498 (and:P (match_dup 0)
8499 (const_int -16)))])
8500 \f
8501 ;; Power8 merge instructions to allow direct move to/from floating point
8502 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
8503 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
8504 ;; value, since it is allocated in reload and not all of the flow information
8505 ;; is setup for it. We have two patterns to do the two moves between gprs and
8506 ;; fprs. There isn't a dependancy between the two, but we could potentially
8507 ;; schedule other instructions between the two instructions. TFmode is
8508 ;; currently limited to traditional FPR registers. If/when this is changed, we
8509 ;; will need to revist %L to make sure it works with VSX registers, or add an
8510 ;; %x version of %L.
8512 (define_insn "p8_fmrgow_<mode>"
8513 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
8514 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
8515 UNSPEC_P8V_FMRGOW))]
8516 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8517 "fmrgow %0,%1,%L1"
8518 [(set_attr "type" "vecperm")])
8520 (define_insn "p8_mtvsrwz_1"
8521 [(set (match_operand:TF 0 "register_operand" "=d")
8522 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
8523 UNSPEC_P8V_MTVSRWZ))]
8524 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8525 "mtvsrwz %x0,%1"
8526 [(set_attr "type" "mftgpr")])
8528 (define_insn "p8_mtvsrwz_2"
8529 [(set (match_operand:TF 0 "register_operand" "+d")
8530 (unspec:TF [(match_dup 0)
8531 (match_operand:SI 1 "register_operand" "r")]
8532 UNSPEC_P8V_MTVSRWZ))]
8533 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8534 "mtvsrwz %L0,%1"
8535 [(set_attr "type" "mftgpr")])
8537 (define_insn_and_split "reload_fpr_from_gpr<mode>"
8538 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
8539 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
8540 UNSPEC_P8V_RELOAD_FROM_GPR))
8541 (clobber (match_operand:TF 2 "register_operand" "=d"))]
8542 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8543 "#"
8544 "&& reload_completed"
8545 [(const_int 0)]
8546 {
8547 rtx dest = operands[0];
8548 rtx src = operands[1];
8549 rtx tmp = operands[2];
8550 rtx gpr_hi_reg = gen_highpart (SImode, src);
8551 rtx gpr_lo_reg = gen_lowpart (SImode, src);
8553 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
8554 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
8555 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
8556 DONE;
8557 }
8558 [(set_attr "length" "12")
8559 (set_attr "type" "three")])
8561 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
8562 (define_insn "p8_mtvsrd_1"
8563 [(set (match_operand:TF 0 "register_operand" "=ws")
8564 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
8565 UNSPEC_P8V_MTVSRD))]
8566 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8567 "mtvsrd %0,%1"
8568 [(set_attr "type" "mftgpr")])
8570 (define_insn "p8_mtvsrd_2"
8571 [(set (match_operand:TF 0 "register_operand" "+ws")
8572 (unspec:TF [(match_dup 0)
8573 (match_operand:DI 1 "register_operand" "r")]
8574 UNSPEC_P8V_MTVSRD))]
8575 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8576 "mtvsrd %L0,%1"
8577 [(set_attr "type" "mftgpr")])
8579 (define_insn "p8_xxpermdi_<mode>"
8580 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8581 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
8582 UNSPEC_P8V_XXPERMDI))]
8583 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8584 "xxpermdi %x0,%1,%L1,0"
8585 [(set_attr "type" "vecperm")])
8587 (define_insn_and_split "reload_vsx_from_gpr<mode>"
8588 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8589 (unspec:FMOVE128_GPR
8590 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
8591 UNSPEC_P8V_RELOAD_FROM_GPR))
8592 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
8593 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8594 "#"
8595 "&& reload_completed"
8596 [(const_int 0)]
8597 {
8598 rtx dest = operands[0];
8599 rtx src = operands[1];
8600 rtx tmp = operands[2];
8601 rtx gpr_hi_reg = gen_highpart (DImode, src);
8602 rtx gpr_lo_reg = gen_lowpart (DImode, src);
8604 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
8605 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
8606 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
8607 }
8608 [(set_attr "length" "12")
8609 (set_attr "type" "three")])
8611 (define_split
8612 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
8613 (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
8614 "reload_completed
8615 && (int_reg_operand (operands[0], <MODE>mode)
8616 || int_reg_operand (operands[1], <MODE>mode))"
8617 [(pc)]
8618 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8620 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
8621 ;; type is stored internally as double precision in the VSX registers, we have
8622 ;; to convert it from the vector format.
8624 (define_insn_and_split "reload_vsx_from_gprsf"
8625 [(set (match_operand:SF 0 "register_operand" "=wa")
8626 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
8627 UNSPEC_P8V_RELOAD_FROM_GPR))
8628 (clobber (match_operand:DI 2 "register_operand" "=r"))]
8629 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8630 "#"
8631 "&& reload_completed"
8632 [(const_int 0)]
8633 {
8634 rtx op0 = operands[0];
8635 rtx op1 = operands[1];
8636 rtx op2 = operands[2];
8637 /* Also use the destination register to hold the unconverted DImode value.
8638 This is conceptually a separate value from OP0, so we use gen_rtx_REG
8639 rather than simplify_gen_subreg. */
8640 rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
8641 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
8643 /* Move SF value to upper 32-bits for xscvspdpn. */
8644 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
8645 emit_move_insn (op0_di, op2);
8646 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
8647 DONE;
8648 }
8649 [(set_attr "length" "8")
8650 (set_attr "type" "two")])
8652 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
8653 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
8654 ;; and then doing a move of that.
8655 (define_insn "p8_mfvsrd_3_<mode>"
8656 [(set (match_operand:DF 0 "register_operand" "=r")
8657 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8658 UNSPEC_P8V_RELOAD_FROM_VSX))]
8659 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8660 "mfvsrd %0,%x1"
8661 [(set_attr "type" "mftgpr")])
8663 (define_insn_and_split "reload_gpr_from_vsx<mode>"
8664 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
8665 (unspec:FMOVE128_GPR
8666 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8667 UNSPEC_P8V_RELOAD_FROM_VSX))
8668 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
8669 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8670 "#"
8671 "&& reload_completed"
8672 [(const_int 0)]
8673 {
8674 rtx dest = operands[0];
8675 rtx src = operands[1];
8676 rtx tmp = operands[2];
8677 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
8678 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
8680 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
8681 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
8682 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
8683 }
8684 [(set_attr "length" "12")
8685 (set_attr "type" "three")])
8687 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
8688 ;; type is stored internally as double precision, we have to convert it to the
8689 ;; vector format.
8691 (define_insn_and_split "reload_gpr_from_vsxsf"
8692 [(set (match_operand:SF 0 "register_operand" "=r")
8693 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
8694 UNSPEC_P8V_RELOAD_FROM_VSX))
8695 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
8696 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8697 "#"
8698 "&& reload_completed"
8699 [(const_int 0)]
8700 {
8701 rtx op0 = operands[0];
8702 rtx op1 = operands[1];
8703 rtx op2 = operands[2];
8704 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
8706 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
8707 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
8708 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
8709 DONE;
8710 }
8711 [(set_attr "length" "12")
8712 (set_attr "type" "three")])
8714 (define_insn "p8_mfvsrd_4_disf"
8715 [(set (match_operand:DI 0 "register_operand" "=r")
8716 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
8717 UNSPEC_P8V_RELOAD_FROM_VSX))]
8718 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8719 "mfvsrd %0,%x1"
8720 [(set_attr "type" "mftgpr")])
8722 \f
8723 ;; Next come the multi-word integer load and store and the load and store
8724 ;; multiple insns.
8726 ;; List r->r after r->Y, otherwise reload will try to reload a
8727 ;; non-offsettable address by using r->r which won't make progress.
8728 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
8729 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
8730 (define_insn "*movdi_internal32"
8731 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
8732 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
8733 "! TARGET_POWERPC64
8734 && (gpc_reg_operand (operands[0], DImode)
8735 || gpc_reg_operand (operands[1], DImode))"
8736 "@
8737 #
8738 #
8739 #
8740 stfd%U0%X0 %1,%0
8741 lfd%U1%X1 %0,%1
8742 fmr %0,%1
8743 #"
8744 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")])
8746 (define_split
8747 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8748 (match_operand:DI 1 "const_int_operand" ""))]
8749 "! TARGET_POWERPC64 && reload_completed
8750 && gpr_or_gpr_p (operands[0], operands[1])
8751 && !direct_move_p (operands[0], operands[1])"
8752 [(set (match_dup 2) (match_dup 4))
8753 (set (match_dup 3) (match_dup 1))]
8754 "
8755 {
8756 HOST_WIDE_INT value = INTVAL (operands[1]);
8757 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8758 DImode);
8759 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8760 DImode);
8761 operands[4] = GEN_INT (value >> 32);
8762 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8763 }")
8765 (define_split
8766 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
8767 (match_operand:DIFD 1 "input_operand" ""))]
8768 "reload_completed && !TARGET_POWERPC64
8769 && gpr_or_gpr_p (operands[0], operands[1])
8770 && !direct_move_p (operands[0], operands[1])"
8771 [(pc)]
8772 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8774 (define_insn "*movdi_internal64"
8775 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi")
8776 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))]
8777 "TARGET_POWERPC64
8778 && (gpc_reg_operand (operands[0], DImode)
8779 || gpc_reg_operand (operands[1], DImode))"
8780 "@
8781 std%U0%X0 %1,%0
8782 ld%U1%X1 %0,%1
8783 mr %0,%1
8784 li %0,%1
8785 lis %0,%v1
8786 #
8787 stfd%U0%X0 %1,%0
8788 lfd%U1%X1 %0,%1
8789 fmr %0,%1
8790 mf%1 %0
8791 mt%0 %1
8792 nop
8793 mftgpr %0,%1
8794 mffgpr %0,%1
8795 mfvsrd %0,%x1
8796 mtvsrd %x0,%1
8797 xxlxor %x0,%x0,%x0"
8798 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,vecsimple")
8799 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")])
8801 ;; Generate all one-bits and clear left or right.
8802 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8803 (define_split
8804 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8805 (match_operand:DI 1 "mask64_operand" ""))]
8806 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8807 [(set (match_dup 0) (const_int -1))
8808 (set (match_dup 0)
8809 (and:DI (rotate:DI (match_dup 0)
8810 (const_int 0))
8811 (match_dup 1)))]
8812 "")
8814 ;; Split a load of a large constant into the appropriate five-instruction
8815 ;; sequence. Handle anything in a constant number of insns.
8816 ;; When non-easy constants can go in the TOC, this should use
8817 ;; easy_fp_constant predicate.
8818 (define_split
8819 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8820 (match_operand:DI 1 "const_int_operand" ""))]
8821 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8822 [(set (match_dup 0) (match_dup 2))
8823 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8824 "
8825 {
8826 if (rs6000_emit_set_const (operands[0], operands[1]))
8827 DONE;
8828 else
8829 FAIL;
8830 }")
8832 (define_split
8833 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8834 (match_operand:DI 1 "const_scalar_int_operand" ""))]
8835 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8836 [(set (match_dup 0) (match_dup 2))
8837 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8838 "
8839 {
8840 if (rs6000_emit_set_const (operands[0], operands[1]))
8841 DONE;
8842 else
8843 FAIL;
8844 }")
8845 \f
8846 ;; TImode/PTImode is similar, except that we usually want to compute the
8847 ;; address into a register and use lsi/stsi (the exception is during reload).
8849 (define_insn "*mov<mode>_string"
8850 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
8851 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
8852 "! TARGET_POWERPC64
8853 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
8854 && (gpc_reg_operand (operands[0], <MODE>mode)
8855 || gpc_reg_operand (operands[1], <MODE>mode))"
8856 "*
8857 {
8858 switch (which_alternative)
8859 {
8860 default:
8861 gcc_unreachable ();
8862 case 0:
8863 if (TARGET_STRING)
8864 return \"stswi %1,%P0,16\";
8865 case 1:
8866 return \"#\";
8867 case 2:
8868 /* If the address is not used in the output, we can use lsi. Otherwise,
8869 fall through to generating four loads. */
8870 if (TARGET_STRING
8871 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8872 return \"lswi %0,%P1,16\";
8873 /* ... fall through ... */
8874 case 3:
8875 case 4:
8876 case 5:
8877 return \"#\";
8878 }
8879 }"
8880 [(set_attr "type" "store,store,load,load,*,*")
8881 (set_attr "update" "yes")
8882 (set_attr "indexed" "yes")
8883 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
8884 (const_string "always")
8885 (const_string "conditional")))])
8887 (define_insn "*mov<mode>_ppc64"
8888 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
8889 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
8890 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
8891 && (gpc_reg_operand (operands[0], <MODE>mode)
8892 || gpc_reg_operand (operands[1], <MODE>mode)))"
8893 {
8894 return rs6000_output_move_128bit (operands);
8895 }
8896 [(set_attr "type" "store,store,load,load,*,*")
8897 (set_attr "length" "8")])
8899 (define_split
8900 [(set (match_operand:TI2 0 "int_reg_operand" "")
8901 (match_operand:TI2 1 "const_scalar_int_operand" ""))]
8902 "TARGET_POWERPC64
8903 && (VECTOR_MEM_NONE_P (<MODE>mode)
8904 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
8905 [(set (match_dup 2) (match_dup 4))
8906 (set (match_dup 3) (match_dup 5))]
8907 "
8908 {
8909 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8910 <MODE>mode);
8911 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8912 <MODE>mode);
8913 if (CONST_WIDE_INT_P (operands[1]))
8914 {
8915 operands[4] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 1));
8916 operands[5] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 0));
8917 }
8918 else if (CONST_INT_P (operands[1]))
8919 {
8920 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8921 operands[5] = operands[1];
8922 }
8923 else
8924 FAIL;
8925 }")
8927 (define_split
8928 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
8929 (match_operand:TI2 1 "input_operand" ""))]
8930 "reload_completed
8931 && gpr_or_gpr_p (operands[0], operands[1])
8932 && !direct_move_p (operands[0], operands[1])
8933 && !quad_load_store_p (operands[0], operands[1])"
8934 [(pc)]
8935 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8936 \f
8937 (define_expand "load_multiple"
8938 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8939 (match_operand:SI 1 "" ""))
8940 (use (match_operand:SI 2 "" ""))])]
8941 "TARGET_STRING && !TARGET_POWERPC64"
8942 "
8943 {
8944 int regno;
8945 int count;
8946 rtx op1;
8947 int i;
8949 /* Support only loading a constant number of fixed-point registers from
8950 memory and only bother with this if more than two; the machine
8951 doesn't support more than eight. */
8952 if (GET_CODE (operands[2]) != CONST_INT
8953 || INTVAL (operands[2]) <= 2
8954 || INTVAL (operands[2]) > 8
8955 || GET_CODE (operands[1]) != MEM
8956 || GET_CODE (operands[0]) != REG
8957 || REGNO (operands[0]) >= 32)
8958 FAIL;
8960 count = INTVAL (operands[2]);
8961 regno = REGNO (operands[0]);
8963 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8964 op1 = replace_equiv_address (operands[1],
8965 force_reg (SImode, XEXP (operands[1], 0)));
8967 for (i = 0; i < count; i++)
8968 XVECEXP (operands[3], 0, i)
8969 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8970 adjust_address_nv (op1, SImode, i * 4));
8971 }")
8973 (define_insn "*ldmsi8"
8974 [(match_parallel 0 "load_multiple_operation"
8975 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8976 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8977 (set (match_operand:SI 3 "gpc_reg_operand" "")
8978 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8979 (set (match_operand:SI 4 "gpc_reg_operand" "")
8980 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8981 (set (match_operand:SI 5 "gpc_reg_operand" "")
8982 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8983 (set (match_operand:SI 6 "gpc_reg_operand" "")
8984 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8985 (set (match_operand:SI 7 "gpc_reg_operand" "")
8986 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8987 (set (match_operand:SI 8 "gpc_reg_operand" "")
8988 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8989 (set (match_operand:SI 9 "gpc_reg_operand" "")
8990 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8991 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8992 "*
8993 { return rs6000_output_load_multiple (operands); }"
8994 [(set_attr "type" "load")
8995 (set_attr "update" "yes")
8996 (set_attr "indexed" "yes")
8997 (set_attr "length" "32")])
8999 (define_insn "*ldmsi7"
9000 [(match_parallel 0 "load_multiple_operation"
9001 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9002 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9003 (set (match_operand:SI 3 "gpc_reg_operand" "")
9004 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9005 (set (match_operand:SI 4 "gpc_reg_operand" "")
9006 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9007 (set (match_operand:SI 5 "gpc_reg_operand" "")
9008 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9009 (set (match_operand:SI 6 "gpc_reg_operand" "")
9010 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9011 (set (match_operand:SI 7 "gpc_reg_operand" "")
9012 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9013 (set (match_operand:SI 8 "gpc_reg_operand" "")
9014 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9015 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9016 "*
9017 { return rs6000_output_load_multiple (operands); }"
9018 [(set_attr "type" "load")
9019 (set_attr "update" "yes")
9020 (set_attr "indexed" "yes")
9021 (set_attr "length" "32")])
9023 (define_insn "*ldmsi6"
9024 [(match_parallel 0 "load_multiple_operation"
9025 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9026 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9027 (set (match_operand:SI 3 "gpc_reg_operand" "")
9028 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9029 (set (match_operand:SI 4 "gpc_reg_operand" "")
9030 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9031 (set (match_operand:SI 5 "gpc_reg_operand" "")
9032 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9033 (set (match_operand:SI 6 "gpc_reg_operand" "")
9034 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9035 (set (match_operand:SI 7 "gpc_reg_operand" "")
9036 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9037 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9038 "*
9039 { return rs6000_output_load_multiple (operands); }"
9040 [(set_attr "type" "load")
9041 (set_attr "update" "yes")
9042 (set_attr "indexed" "yes")
9043 (set_attr "length" "32")])
9045 (define_insn "*ldmsi5"
9046 [(match_parallel 0 "load_multiple_operation"
9047 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9048 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9049 (set (match_operand:SI 3 "gpc_reg_operand" "")
9050 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9051 (set (match_operand:SI 4 "gpc_reg_operand" "")
9052 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9053 (set (match_operand:SI 5 "gpc_reg_operand" "")
9054 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9055 (set (match_operand:SI 6 "gpc_reg_operand" "")
9056 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9057 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9058 "*
9059 { return rs6000_output_load_multiple (operands); }"
9060 [(set_attr "type" "load")
9061 (set_attr "update" "yes")
9062 (set_attr "indexed" "yes")
9063 (set_attr "length" "32")])
9065 (define_insn "*ldmsi4"
9066 [(match_parallel 0 "load_multiple_operation"
9067 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9068 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9069 (set (match_operand:SI 3 "gpc_reg_operand" "")
9070 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9071 (set (match_operand:SI 4 "gpc_reg_operand" "")
9072 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9073 (set (match_operand:SI 5 "gpc_reg_operand" "")
9074 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9075 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9076 "*
9077 { return rs6000_output_load_multiple (operands); }"
9078 [(set_attr "type" "load")
9079 (set_attr "update" "yes")
9080 (set_attr "indexed" "yes")
9081 (set_attr "length" "32")])
9083 (define_insn "*ldmsi3"
9084 [(match_parallel 0 "load_multiple_operation"
9085 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9086 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9087 (set (match_operand:SI 3 "gpc_reg_operand" "")
9088 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9089 (set (match_operand:SI 4 "gpc_reg_operand" "")
9090 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9091 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9092 "*
9093 { return rs6000_output_load_multiple (operands); }"
9094 [(set_attr "type" "load")
9095 (set_attr "update" "yes")
9096 (set_attr "indexed" "yes")
9097 (set_attr "length" "32")])
9099 (define_expand "store_multiple"
9100 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9101 (match_operand:SI 1 "" ""))
9102 (clobber (scratch:SI))
9103 (use (match_operand:SI 2 "" ""))])]
9104 "TARGET_STRING && !TARGET_POWERPC64"
9105 "
9106 {
9107 int regno;
9108 int count;
9109 rtx to;
9110 rtx op0;
9111 int i;
9113 /* Support only storing a constant number of fixed-point registers to
9114 memory and only bother with this if more than two; the machine
9115 doesn't support more than eight. */
9116 if (GET_CODE (operands[2]) != CONST_INT
9117 || INTVAL (operands[2]) <= 2
9118 || INTVAL (operands[2]) > 8
9119 || GET_CODE (operands[0]) != MEM
9120 || GET_CODE (operands[1]) != REG
9121 || REGNO (operands[1]) >= 32)
9122 FAIL;
9124 count = INTVAL (operands[2]);
9125 regno = REGNO (operands[1]);
9127 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9128 to = force_reg (SImode, XEXP (operands[0], 0));
9129 op0 = replace_equiv_address (operands[0], to);
9131 XVECEXP (operands[3], 0, 0)
9132 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9133 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9134 gen_rtx_SCRATCH (SImode));
9136 for (i = 1; i < count; i++)
9137 XVECEXP (operands[3], 0, i + 1)
9138 = gen_rtx_SET (VOIDmode,
9139 adjust_address_nv (op0, SImode, i * 4),
9140 gen_rtx_REG (SImode, regno + i));
9141 }")
9143 (define_insn "*stmsi8"
9144 [(match_parallel 0 "store_multiple_operation"
9145 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9146 (match_operand:SI 2 "gpc_reg_operand" "r"))
9147 (clobber (match_scratch:SI 3 "=X"))
9148 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9149 (match_operand:SI 4 "gpc_reg_operand" "r"))
9150 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9151 (match_operand:SI 5 "gpc_reg_operand" "r"))
9152 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9153 (match_operand:SI 6 "gpc_reg_operand" "r"))
9154 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9155 (match_operand:SI 7 "gpc_reg_operand" "r"))
9156 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9157 (match_operand:SI 8 "gpc_reg_operand" "r"))
9158 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9159 (match_operand:SI 9 "gpc_reg_operand" "r"))
9160 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9161 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9162 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
9163 "stswi %2,%1,%O0"
9164 [(set_attr "type" "store")
9165 (set_attr "update" "yes")
9166 (set_attr "indexed" "yes")
9167 (set_attr "cell_micro" "always")])
9169 (define_insn "*stmsi7"
9170 [(match_parallel 0 "store_multiple_operation"
9171 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9172 (match_operand:SI 2 "gpc_reg_operand" "r"))
9173 (clobber (match_scratch:SI 3 "=X"))
9174 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9175 (match_operand:SI 4 "gpc_reg_operand" "r"))
9176 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9177 (match_operand:SI 5 "gpc_reg_operand" "r"))
9178 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9179 (match_operand:SI 6 "gpc_reg_operand" "r"))
9180 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9181 (match_operand:SI 7 "gpc_reg_operand" "r"))
9182 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9183 (match_operand:SI 8 "gpc_reg_operand" "r"))
9184 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9185 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9186 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9187 "stswi %2,%1,%O0"
9188 [(set_attr "type" "store")
9189 (set_attr "update" "yes")
9190 (set_attr "indexed" "yes")
9191 (set_attr "cell_micro" "always")])
9193 (define_insn "*stmsi6"
9194 [(match_parallel 0 "store_multiple_operation"
9195 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9196 (match_operand:SI 2 "gpc_reg_operand" "r"))
9197 (clobber (match_scratch:SI 3 "=X"))
9198 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9199 (match_operand:SI 4 "gpc_reg_operand" "r"))
9200 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9201 (match_operand:SI 5 "gpc_reg_operand" "r"))
9202 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9203 (match_operand:SI 6 "gpc_reg_operand" "r"))
9204 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9205 (match_operand:SI 7 "gpc_reg_operand" "r"))
9206 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9207 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9208 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9209 "stswi %2,%1,%O0"
9210 [(set_attr "type" "store")
9211 (set_attr "update" "yes")
9212 (set_attr "indexed" "yes")
9213 (set_attr "cell_micro" "always")])
9215 (define_insn "*stmsi5"
9216 [(match_parallel 0 "store_multiple_operation"
9217 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9218 (match_operand:SI 2 "gpc_reg_operand" "r"))
9219 (clobber (match_scratch:SI 3 "=X"))
9220 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9221 (match_operand:SI 4 "gpc_reg_operand" "r"))
9222 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9223 (match_operand:SI 5 "gpc_reg_operand" "r"))
9224 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9225 (match_operand:SI 6 "gpc_reg_operand" "r"))
9226 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9227 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9228 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9229 "stswi %2,%1,%O0"
9230 [(set_attr "type" "store")
9231 (set_attr "update" "yes")
9232 (set_attr "indexed" "yes")
9233 (set_attr "cell_micro" "always")])
9235 (define_insn "*stmsi4"
9236 [(match_parallel 0 "store_multiple_operation"
9237 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9238 (match_operand:SI 2 "gpc_reg_operand" "r"))
9239 (clobber (match_scratch:SI 3 "=X"))
9240 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9241 (match_operand:SI 4 "gpc_reg_operand" "r"))
9242 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9243 (match_operand:SI 5 "gpc_reg_operand" "r"))
9244 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9245 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9246 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9247 "stswi %2,%1,%O0"
9248 [(set_attr "type" "store")
9249 (set_attr "update" "yes")
9250 (set_attr "indexed" "yes")
9251 (set_attr "cell_micro" "always")])
9253 (define_insn "*stmsi3"
9254 [(match_parallel 0 "store_multiple_operation"
9255 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9256 (match_operand:SI 2 "gpc_reg_operand" "r"))
9257 (clobber (match_scratch:SI 3 "=X"))
9258 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9259 (match_operand:SI 4 "gpc_reg_operand" "r"))
9260 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9261 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9262 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9263 "stswi %2,%1,%O0"
9264 [(set_attr "type" "store")
9265 (set_attr "update" "yes")
9266 (set_attr "indexed" "yes")
9267 (set_attr "cell_micro" "always")])
9268 \f
9269 (define_expand "setmemsi"
9270 [(parallel [(set (match_operand:BLK 0 "" "")
9271 (match_operand 2 "const_int_operand" ""))
9272 (use (match_operand:SI 1 "" ""))
9273 (use (match_operand:SI 3 "" ""))])]
9274 ""
9275 "
9276 {
9277 /* If value to set is not zero, use the library routine. */
9278 if (operands[2] != const0_rtx)
9279 FAIL;
9281 if (expand_block_clear (operands))
9282 DONE;
9283 else
9284 FAIL;
9285 }")
9287 ;; String/block move insn.
9288 ;; Argument 0 is the destination
9289 ;; Argument 1 is the source
9290 ;; Argument 2 is the length
9291 ;; Argument 3 is the alignment
9293 (define_expand "movmemsi"
9294 [(parallel [(set (match_operand:BLK 0 "" "")
9295 (match_operand:BLK 1 "" ""))
9296 (use (match_operand:SI 2 "" ""))
9297 (use (match_operand:SI 3 "" ""))])]
9298 ""
9299 "
9300 {
9301 if (expand_block_move (operands))
9302 DONE;
9303 else
9304 FAIL;
9305 }")
9307 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9308 ;; register allocator doesn't have a clue about allocating 8 word registers.
9309 ;; rD/rS = r5 is preferred, efficient form.
9310 (define_expand "movmemsi_8reg"
9311 [(parallel [(set (match_operand 0 "" "")
9312 (match_operand 1 "" ""))
9313 (use (match_operand 2 "" ""))
9314 (use (match_operand 3 "" ""))
9315 (clobber (reg:SI 5))
9316 (clobber (reg:SI 6))
9317 (clobber (reg:SI 7))
9318 (clobber (reg:SI 8))
9319 (clobber (reg:SI 9))
9320 (clobber (reg:SI 10))
9321 (clobber (reg:SI 11))
9322 (clobber (reg:SI 12))
9323 (clobber (match_scratch:SI 4 ""))])]
9324 "TARGET_STRING"
9325 "")
9327 (define_insn ""
9328 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9329 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9330 (use (match_operand:SI 2 "immediate_operand" "i"))
9331 (use (match_operand:SI 3 "immediate_operand" "i"))
9332 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9333 (clobber (reg:SI 6))
9334 (clobber (reg:SI 7))
9335 (clobber (reg:SI 8))
9336 (clobber (reg:SI 9))
9337 (clobber (reg:SI 10))
9338 (clobber (reg:SI 11))
9339 (clobber (reg:SI 12))
9340 (clobber (match_scratch:SI 5 "=X"))]
9341 "TARGET_STRING
9342 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9343 || INTVAL (operands[2]) == 0)
9344 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9345 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9346 && REGNO (operands[4]) == 5"
9347 "lswi %4,%1,%2\;stswi %4,%0,%2"
9348 [(set_attr "type" "store")
9349 (set_attr "update" "yes")
9350 (set_attr "indexed" "yes")
9351 (set_attr "cell_micro" "always")
9352 (set_attr "length" "8")])
9354 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9355 ;; register allocator doesn't have a clue about allocating 6 word registers.
9356 ;; rD/rS = r5 is preferred, efficient form.
9357 (define_expand "movmemsi_6reg"
9358 [(parallel [(set (match_operand 0 "" "")
9359 (match_operand 1 "" ""))
9360 (use (match_operand 2 "" ""))
9361 (use (match_operand 3 "" ""))
9362 (clobber (reg:SI 5))
9363 (clobber (reg:SI 6))
9364 (clobber (reg:SI 7))
9365 (clobber (reg:SI 8))
9366 (clobber (reg:SI 9))
9367 (clobber (reg:SI 10))
9368 (clobber (match_scratch:SI 4 ""))])]
9369 "TARGET_STRING"
9370 "")
9372 (define_insn ""
9373 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9374 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9375 (use (match_operand:SI 2 "immediate_operand" "i"))
9376 (use (match_operand:SI 3 "immediate_operand" "i"))
9377 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9378 (clobber (reg:SI 6))
9379 (clobber (reg:SI 7))
9380 (clobber (reg:SI 8))
9381 (clobber (reg:SI 9))
9382 (clobber (reg:SI 10))
9383 (clobber (match_scratch:SI 5 "=X"))]
9384 "TARGET_STRING
9385 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9386 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9387 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9388 && REGNO (operands[4]) == 5"
9389 "lswi %4,%1,%2\;stswi %4,%0,%2"
9390 [(set_attr "type" "store")
9391 (set_attr "update" "yes")
9392 (set_attr "indexed" "yes")
9393 (set_attr "cell_micro" "always")
9394 (set_attr "length" "8")])
9396 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9397 ;; problems with TImode.
9398 ;; rD/rS = r5 is preferred, efficient form.
9399 (define_expand "movmemsi_4reg"
9400 [(parallel [(set (match_operand 0 "" "")
9401 (match_operand 1 "" ""))
9402 (use (match_operand 2 "" ""))
9403 (use (match_operand 3 "" ""))
9404 (clobber (reg:SI 5))
9405 (clobber (reg:SI 6))
9406 (clobber (reg:SI 7))
9407 (clobber (reg:SI 8))
9408 (clobber (match_scratch:SI 4 ""))])]
9409 "TARGET_STRING"
9410 "")
9412 (define_insn ""
9413 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9414 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9415 (use (match_operand:SI 2 "immediate_operand" "i"))
9416 (use (match_operand:SI 3 "immediate_operand" "i"))
9417 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9418 (clobber (reg:SI 6))
9419 (clobber (reg:SI 7))
9420 (clobber (reg:SI 8))
9421 (clobber (match_scratch:SI 5 "=X"))]
9422 "TARGET_STRING
9423 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9424 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9425 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9426 && REGNO (operands[4]) == 5"
9427 "lswi %4,%1,%2\;stswi %4,%0,%2"
9428 [(set_attr "type" "store")
9429 (set_attr "update" "yes")
9430 (set_attr "indexed" "yes")
9431 (set_attr "cell_micro" "always")
9432 (set_attr "length" "8")])
9434 ;; Move up to 8 bytes at a time.
9435 (define_expand "movmemsi_2reg"
9436 [(parallel [(set (match_operand 0 "" "")
9437 (match_operand 1 "" ""))
9438 (use (match_operand 2 "" ""))
9439 (use (match_operand 3 "" ""))
9440 (clobber (match_scratch:DI 4 ""))
9441 (clobber (match_scratch:SI 5 ""))])]
9442 "TARGET_STRING && ! TARGET_POWERPC64"
9443 "")
9445 (define_insn ""
9446 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9447 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9448 (use (match_operand:SI 2 "immediate_operand" "i"))
9449 (use (match_operand:SI 3 "immediate_operand" "i"))
9450 (clobber (match_scratch:DI 4 "=&r"))
9451 (clobber (match_scratch:SI 5 "=X"))]
9452 "TARGET_STRING && ! TARGET_POWERPC64
9453 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9454 "lswi %4,%1,%2\;stswi %4,%0,%2"
9455 [(set_attr "type" "store")
9456 (set_attr "update" "yes")
9457 (set_attr "indexed" "yes")
9458 (set_attr "cell_micro" "always")
9459 (set_attr "length" "8")])
9461 ;; Move up to 4 bytes at a time.
9462 (define_expand "movmemsi_1reg"
9463 [(parallel [(set (match_operand 0 "" "")
9464 (match_operand 1 "" ""))
9465 (use (match_operand 2 "" ""))
9466 (use (match_operand 3 "" ""))
9467 (clobber (match_scratch:SI 4 ""))
9468 (clobber (match_scratch:SI 5 ""))])]
9469 "TARGET_STRING"
9470 "")
9472 (define_insn ""
9473 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9474 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9475 (use (match_operand:SI 2 "immediate_operand" "i"))
9476 (use (match_operand:SI 3 "immediate_operand" "i"))
9477 (clobber (match_scratch:SI 4 "=&r"))
9478 (clobber (match_scratch:SI 5 "=X"))]
9479 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9480 "lswi %4,%1,%2\;stswi %4,%0,%2"
9481 [(set_attr "type" "store")
9482 (set_attr "update" "yes")
9483 (set_attr "indexed" "yes")
9484 (set_attr "cell_micro" "always")
9485 (set_attr "length" "8")])
9486 \f
9487 ;; Define insns that do load or store with update. Some of these we can
9488 ;; get by using pre-decrement or pre-increment, but the hardware can also
9489 ;; do cases where the increment is not the size of the object.
9490 ;;
9491 ;; In all these cases, we use operands 0 and 1 for the register being
9492 ;; incremented because those are the operands that local-alloc will
9493 ;; tie and these are the pair most likely to be tieable (and the ones
9494 ;; that will benefit the most).
9496 (define_insn "*movdi_update1"
9497 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9498 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9499 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9500 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9501 (plus:DI (match_dup 1) (match_dup 2)))]
9502 "TARGET_POWERPC64 && TARGET_UPDATE
9503 && (!avoiding_indexed_address_p (DImode)
9504 || !gpc_reg_operand (operands[2], DImode))"
9505 "@
9506 ldux %3,%0,%2
9507 ldu %3,%2(%0)"
9508 [(set_attr "type" "load")
9509 (set_attr "update" "yes")
9510 (set_attr "indexed" "yes,no")])
9512 (define_insn "movdi_<mode>_update"
9513 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9514 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9515 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9516 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9517 (plus:P (match_dup 1) (match_dup 2)))]
9518 "TARGET_POWERPC64 && TARGET_UPDATE
9519 && (!avoiding_indexed_address_p (Pmode)
9520 || !gpc_reg_operand (operands[2], Pmode)
9521 || (REG_P (operands[0])
9522 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9523 "@
9524 stdux %3,%0,%2
9525 stdu %3,%2(%0)"
9526 [(set_attr "type" "store")
9527 (set_attr "update" "yes")
9528 (set_attr "indexed" "yes,no")])
9530 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
9531 ;; needed for stack allocation, even if the user passes -mno-update.
9532 (define_insn "movdi_<mode>_update_stack"
9533 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9534 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9535 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9536 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9537 (plus:P (match_dup 1) (match_dup 2)))]
9538 "TARGET_POWERPC64"
9539 "@
9540 stdux %3,%0,%2
9541 stdu %3,%2(%0)"
9542 [(set_attr "type" "store")
9543 (set_attr "update" "yes")
9544 (set_attr "indexed" "yes,no")])
9546 (define_insn "*movsi_update1"
9547 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9548 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9549 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9550 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9551 (plus:SI (match_dup 1) (match_dup 2)))]
9552 "TARGET_UPDATE
9553 && (!avoiding_indexed_address_p (SImode)
9554 || !gpc_reg_operand (operands[2], SImode))"
9555 "@
9556 lwzux %3,%0,%2
9557 lwzu %3,%2(%0)"
9558 [(set_attr "type" "load")
9559 (set_attr "update" "yes")
9560 (set_attr "indexed" "yes,no")])
9562 (define_insn "*movsi_update2"
9563 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9564 (sign_extend:DI
9565 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9566 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9567 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9568 (plus:DI (match_dup 1) (match_dup 2)))]
9569 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
9570 && !avoiding_indexed_address_p (DImode)"
9571 "lwaux %3,%0,%2"
9572 [(set_attr "type" "load")
9573 (set_attr "sign_extend" "yes")
9574 (set_attr "update" "yes")
9575 (set_attr "indexed" "yes")])
9577 (define_insn "movsi_update"
9578 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9579 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9580 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9581 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9582 (plus:SI (match_dup 1) (match_dup 2)))]
9583 "TARGET_UPDATE
9584 && (!avoiding_indexed_address_p (SImode)
9585 || !gpc_reg_operand (operands[2], SImode)
9586 || (REG_P (operands[0])
9587 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9588 "@
9589 stwux %3,%0,%2
9590 stwu %3,%2(%0)"
9591 [(set_attr "type" "store")
9592 (set_attr "update" "yes")
9593 (set_attr "indexed" "yes,no")])
9595 ;; This is an unconditional pattern; needed for stack allocation, even
9596 ;; if the user passes -mno-update.
9597 (define_insn "movsi_update_stack"
9598 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9599 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9600 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9601 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9602 (plus:SI (match_dup 1) (match_dup 2)))]
9603 ""
9604 "@
9605 stwux %3,%0,%2
9606 stwu %3,%2(%0)"
9607 [(set_attr "type" "store")
9608 (set_attr "update" "yes")
9609 (set_attr "indexed" "yes,no")])
9611 (define_insn "*movhi_update1"
9612 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9613 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9614 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9615 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9616 (plus:SI (match_dup 1) (match_dup 2)))]
9617 "TARGET_UPDATE
9618 && (!avoiding_indexed_address_p (SImode)
9619 || !gpc_reg_operand (operands[2], SImode))"
9620 "@
9621 lhzux %3,%0,%2
9622 lhzu %3,%2(%0)"
9623 [(set_attr "type" "load")
9624 (set_attr "update" "yes")
9625 (set_attr "indexed" "yes,no")])
9627 (define_insn "*movhi_update2"
9628 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9629 (zero_extend:SI
9630 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9631 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9632 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9633 (plus:SI (match_dup 1) (match_dup 2)))]
9634 "TARGET_UPDATE
9635 && (!avoiding_indexed_address_p (SImode)
9636 || !gpc_reg_operand (operands[2], SImode))"
9637 "@
9638 lhzux %3,%0,%2
9639 lhzu %3,%2(%0)"
9640 [(set_attr "type" "load")
9641 (set_attr "update" "yes")
9642 (set_attr "indexed" "yes,no")])
9644 (define_insn "*movhi_update3"
9645 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9646 (sign_extend:SI
9647 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9648 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9649 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9650 (plus:SI (match_dup 1) (match_dup 2)))]
9651 "TARGET_UPDATE && rs6000_gen_cell_microcode
9652 && (!avoiding_indexed_address_p (SImode)
9653 || !gpc_reg_operand (operands[2], SImode))"
9654 "@
9655 lhaux %3,%0,%2
9656 lhau %3,%2(%0)"
9657 [(set_attr "type" "load")
9658 (set_attr "sign_extend" "yes")
9659 (set_attr "update" "yes")
9660 (set_attr "indexed" "yes,no")])
9662 (define_insn "*movhi_update4"
9663 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9664 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9665 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9666 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9667 (plus:SI (match_dup 1) (match_dup 2)))]
9668 "TARGET_UPDATE
9669 && (!avoiding_indexed_address_p (SImode)
9670 || !gpc_reg_operand (operands[2], SImode))"
9671 "@
9672 sthux %3,%0,%2
9673 sthu %3,%2(%0)"
9674 [(set_attr "type" "store")
9675 (set_attr "update" "yes")
9676 (set_attr "indexed" "yes,no")])
9678 (define_insn "*movqi_update1"
9679 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9680 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9681 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9682 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9683 (plus:SI (match_dup 1) (match_dup 2)))]
9684 "TARGET_UPDATE
9685 && (!avoiding_indexed_address_p (SImode)
9686 || !gpc_reg_operand (operands[2], SImode))"
9687 "@
9688 lbzux %3,%0,%2
9689 lbzu %3,%2(%0)"
9690 [(set_attr "type" "load")
9691 (set_attr "update" "yes")
9692 (set_attr "indexed" "yes,no")])
9694 (define_insn "*movqi_update2"
9695 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9696 (zero_extend:SI
9697 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9698 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9699 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9700 (plus:SI (match_dup 1) (match_dup 2)))]
9701 "TARGET_UPDATE
9702 && (!avoiding_indexed_address_p (SImode)
9703 || !gpc_reg_operand (operands[2], SImode))"
9704 "@
9705 lbzux %3,%0,%2
9706 lbzu %3,%2(%0)"
9707 [(set_attr "type" "load")
9708 (set_attr "update" "yes")
9709 (set_attr "indexed" "yes,no")])
9711 (define_insn "*movqi_update3"
9712 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9713 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9714 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9715 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9716 (plus:SI (match_dup 1) (match_dup 2)))]
9717 "TARGET_UPDATE
9718 && (!avoiding_indexed_address_p (SImode)
9719 || !gpc_reg_operand (operands[2], SImode))"
9720 "@
9721 stbux %3,%0,%2
9722 stbu %3,%2(%0)"
9723 [(set_attr "type" "store")
9724 (set_attr "update" "yes")
9725 (set_attr "indexed" "yes,no")])
9727 (define_insn "*movsf_update1"
9728 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9729 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9730 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9731 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9732 (plus:SI (match_dup 1) (match_dup 2)))]
9733 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9734 && (!avoiding_indexed_address_p (SImode)
9735 || !gpc_reg_operand (operands[2], SImode))"
9736 "@
9737 lfsux %3,%0,%2
9738 lfsu %3,%2(%0)"
9739 [(set_attr "type" "fpload")
9740 (set_attr "update" "yes")
9741 (set_attr "indexed" "yes,no")])
9743 (define_insn "*movsf_update2"
9744 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9745 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9746 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9747 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9748 (plus:SI (match_dup 1) (match_dup 2)))]
9749 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9750 && (!avoiding_indexed_address_p (SImode)
9751 || !gpc_reg_operand (operands[2], SImode))"
9752 "@
9753 stfsux %3,%0,%2
9754 stfsu %3,%2(%0)"
9755 [(set_attr "type" "fpstore")
9756 (set_attr "update" "yes")
9757 (set_attr "indexed" "yes,no")])
9759 (define_insn "*movsf_update3"
9760 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9761 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9762 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9763 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9764 (plus:SI (match_dup 1) (match_dup 2)))]
9765 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9766 && (!avoiding_indexed_address_p (SImode)
9767 || !gpc_reg_operand (operands[2], SImode))"
9768 "@
9769 lwzux %3,%0,%2
9770 lwzu %3,%2(%0)"
9771 [(set_attr "type" "load")
9772 (set_attr "update" "yes")
9773 (set_attr "indexed" "yes,no")])
9775 (define_insn "*movsf_update4"
9776 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9777 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9778 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9779 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9780 (plus:SI (match_dup 1) (match_dup 2)))]
9781 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9782 && (!avoiding_indexed_address_p (SImode)
9783 || !gpc_reg_operand (operands[2], SImode))"
9784 "@
9785 stwux %3,%0,%2
9786 stwu %3,%2(%0)"
9787 [(set_attr "type" "store")
9788 (set_attr "update" "yes")
9789 (set_attr "indexed" "yes,no")])
9791 (define_insn "*movdf_update1"
9792 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
9793 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9794 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9795 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9796 (plus:SI (match_dup 1) (match_dup 2)))]
9797 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9798 && (!avoiding_indexed_address_p (SImode)
9799 || !gpc_reg_operand (operands[2], SImode))"
9800 "@
9801 lfdux %3,%0,%2
9802 lfdu %3,%2(%0)"
9803 [(set_attr "type" "fpload")
9804 (set_attr "update" "yes")
9805 (set_attr "indexed" "yes,no")])
9807 (define_insn "*movdf_update2"
9808 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9809 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9810 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
9811 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9812 (plus:SI (match_dup 1) (match_dup 2)))]
9813 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9814 && (!avoiding_indexed_address_p (SImode)
9815 || !gpc_reg_operand (operands[2], SImode))"
9816 "@
9817 stfdux %3,%0,%2
9818 stfdu %3,%2(%0)"
9819 [(set_attr "type" "fpstore")
9820 (set_attr "update" "yes")
9821 (set_attr "indexed" "yes,no")])
9824 ;; After inserting conditional returns we can sometimes have
9825 ;; unnecessary register moves. Unfortunately we cannot have a
9826 ;; modeless peephole here, because some single SImode sets have early
9827 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9828 ;; sequences, using get_attr_length here will smash the operands
9829 ;; array. Neither is there an early_cobbler_p predicate.
9830 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9831 ;; Also this optimization interferes with scalars going into
9832 ;; altivec registers (the code does reloading through the FPRs).
9833 (define_peephole2
9834 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9835 (match_operand:DF 1 "any_operand" ""))
9836 (set (match_operand:DF 2 "gpc_reg_operand" "")
9837 (match_dup 0))]
9838 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9839 && !TARGET_UPPER_REGS_DF
9840 && peep2_reg_dead_p (2, operands[0])"
9841 [(set (match_dup 2) (match_dup 1))])
9843 (define_peephole2
9844 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9845 (match_operand:SF 1 "any_operand" ""))
9846 (set (match_operand:SF 2 "gpc_reg_operand" "")
9847 (match_dup 0))]
9848 "!TARGET_UPPER_REGS_SF
9849 && peep2_reg_dead_p (2, operands[0])"
9850 [(set (match_dup 2) (match_dup 1))])
9852 \f
9853 ;; TLS support.
9855 ;; Mode attributes for different ABIs.
9856 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
9857 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
9858 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
9859 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
9861 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
9862 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9863 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9864 (match_operand 4 "" "g")))
9865 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9866 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9867 UNSPEC_TLSGD)
9868 (clobber (reg:SI LR_REGNO))]
9869 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9870 {
9871 if (TARGET_CMODEL != CMODEL_SMALL)
9872 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
9873 "bl %z3\;nop";
9874 else
9875 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
9876 }
9877 "&& TARGET_TLS_MARKERS"
9878 [(set (match_dup 0)
9879 (unspec:TLSmode [(match_dup 1)
9880 (match_dup 2)]
9881 UNSPEC_TLSGD))
9882 (parallel [(set (match_dup 0)
9883 (call (mem:TLSmode (match_dup 3))
9884 (match_dup 4)))
9885 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9886 (clobber (reg:SI LR_REGNO))])]
9887 ""
9888 [(set_attr "type" "two")
9889 (set (attr "length")
9890 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9891 (const_int 16)
9892 (const_int 12)))])
9894 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
9895 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9896 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9897 (match_operand 4 "" "g")))
9898 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9899 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9900 UNSPEC_TLSGD)
9901 (clobber (reg:SI LR_REGNO))]
9902 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9903 {
9904 if (flag_pic)
9905 {
9906 if (TARGET_SECURE_PLT && flag_pic == 2)
9907 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
9908 else
9909 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
9910 }
9911 else
9912 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
9913 }
9914 "&& TARGET_TLS_MARKERS"
9915 [(set (match_dup 0)
9916 (unspec:TLSmode [(match_dup 1)
9917 (match_dup 2)]
9918 UNSPEC_TLSGD))
9919 (parallel [(set (match_dup 0)
9920 (call (mem:TLSmode (match_dup 3))
9921 (match_dup 4)))
9922 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9923 (clobber (reg:SI LR_REGNO))])]
9924 ""
9925 [(set_attr "type" "two")
9926 (set_attr "length" "8")])
9928 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
9929 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9930 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9931 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9932 UNSPEC_TLSGD))]
9933 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9934 "addi %0,%1,%2@got@tlsgd"
9935 "&& TARGET_CMODEL != CMODEL_SMALL"
9936 [(set (match_dup 3)
9937 (high:TLSmode
9938 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
9939 (set (match_dup 0)
9940 (lo_sum:TLSmode (match_dup 3)
9941 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
9942 "
9943 {
9944 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9945 }"
9946 [(set (attr "length")
9947 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9948 (const_int 8)
9949 (const_int 4)))])
9951 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
9952 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9953 (high:TLSmode
9954 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9955 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9956 UNSPEC_TLSGD)))]
9957 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9958 "addis %0,%1,%2@got@tlsgd@ha"
9959 [(set_attr "length" "4")])
9961 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
9962 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9963 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9964 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
9965 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9966 UNSPEC_TLSGD)))]
9967 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9968 "addi %0,%1,%2@got@tlsgd@l"
9969 [(set_attr "length" "4")])
9971 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
9972 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9973 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9974 (match_operand 2 "" "g")))
9975 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9976 UNSPEC_TLSGD)
9977 (clobber (reg:SI LR_REGNO))]
9978 "HAVE_AS_TLS && TARGET_TLS_MARKERS
9979 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9980 "bl %z1(%3@tlsgd)\;nop"
9981 [(set_attr "type" "branch")
9982 (set_attr "length" "8")])
9984 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
9985 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9986 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9987 (match_operand 2 "" "g")))
9988 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9989 UNSPEC_TLSGD)
9990 (clobber (reg:SI LR_REGNO))]
9991 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9992 {
9993 if (flag_pic)
9994 {
9995 if (TARGET_SECURE_PLT && flag_pic == 2)
9996 return "bl %z1+32768(%3@tlsgd)@plt";
9997 return "bl %z1(%3@tlsgd)@plt";
9998 }
9999 return "bl %z1(%3@tlsgd)";
10000 }
10001 [(set_attr "type" "branch")
10002 (set_attr "length" "4")])
10004 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10005 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10006 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10007 (match_operand 3 "" "g")))
10008 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10009 UNSPEC_TLSLD)
10010 (clobber (reg:SI LR_REGNO))]
10011 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10012 {
10013 if (TARGET_CMODEL != CMODEL_SMALL)
10014 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
10015 "bl %z2\;nop";
10016 else
10017 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
10018 }
10019 "&& TARGET_TLS_MARKERS"
10020 [(set (match_dup 0)
10021 (unspec:TLSmode [(match_dup 1)]
10022 UNSPEC_TLSLD))
10023 (parallel [(set (match_dup 0)
10024 (call (mem:TLSmode (match_dup 2))
10025 (match_dup 3)))
10026 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10027 (clobber (reg:SI LR_REGNO))])]
10028 ""
10029 [(set_attr "type" "two")
10030 (set (attr "length")
10031 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10032 (const_int 16)
10033 (const_int 12)))])
10035 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10036 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10037 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10038 (match_operand 3 "" "g")))
10039 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10040 UNSPEC_TLSLD)
10041 (clobber (reg:SI LR_REGNO))]
10042 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10043 {
10044 if (flag_pic)
10045 {
10046 if (TARGET_SECURE_PLT && flag_pic == 2)
10047 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10048 else
10049 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10050 }
10051 else
10052 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10053 }
10054 "&& TARGET_TLS_MARKERS"
10055 [(set (match_dup 0)
10056 (unspec:TLSmode [(match_dup 1)]
10057 UNSPEC_TLSLD))
10058 (parallel [(set (match_dup 0)
10059 (call (mem:TLSmode (match_dup 2))
10060 (match_dup 3)))
10061 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10062 (clobber (reg:SI LR_REGNO))])]
10063 ""
10064 [(set_attr "length" "8")])
10066 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
10067 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10068 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10069 UNSPEC_TLSLD))]
10070 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10071 "addi %0,%1,%&@got@tlsld"
10072 "&& TARGET_CMODEL != CMODEL_SMALL"
10073 [(set (match_dup 2)
10074 (high:TLSmode
10075 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
10076 (set (match_dup 0)
10077 (lo_sum:TLSmode (match_dup 2)
10078 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
10079 "
10080 {
10081 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10082 }"
10083 [(set (attr "length")
10084 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10085 (const_int 8)
10086 (const_int 4)))])
10088 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
10089 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10090 (high:TLSmode
10091 (unspec:TLSmode [(const_int 0)
10092 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10093 UNSPEC_TLSLD)))]
10094 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10095 "addis %0,%1,%&@got@tlsld@ha"
10096 [(set_attr "length" "4")])
10098 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
10099 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10100 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10101 (unspec:TLSmode [(const_int 0)
10102 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
10103 UNSPEC_TLSLD)))]
10104 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10105 "addi %0,%1,%&@got@tlsld@l"
10106 [(set_attr "length" "4")])
10108 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10109 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10110 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10111 (match_operand 2 "" "g")))
10112 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10113 (clobber (reg:SI LR_REGNO))]
10114 "HAVE_AS_TLS && TARGET_TLS_MARKERS
10115 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10116 "bl %z1(%&@tlsld)\;nop"
10117 [(set_attr "type" "branch")
10118 (set_attr "length" "8")])
10120 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10121 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10122 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10123 (match_operand 2 "" "g")))
10124 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10125 (clobber (reg:SI LR_REGNO))]
10126 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10127 {
10128 if (flag_pic)
10129 {
10130 if (TARGET_SECURE_PLT && flag_pic == 2)
10131 return "bl %z1+32768(%&@tlsld)@plt";
10132 return "bl %z1(%&@tlsld)@plt";
10133 }
10134 return "bl %z1(%&@tlsld)";
10135 }
10136 [(set_attr "type" "branch")
10137 (set_attr "length" "4")])
10139 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10140 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10141 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10142 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10143 UNSPEC_TLSDTPREL))]
10144 "HAVE_AS_TLS"
10145 "addi %0,%1,%2@dtprel")
10147 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10148 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10149 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10150 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10151 UNSPEC_TLSDTPRELHA))]
10152 "HAVE_AS_TLS"
10153 "addis %0,%1,%2@dtprel@ha")
10155 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10156 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10157 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10158 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10159 UNSPEC_TLSDTPRELLO))]
10160 "HAVE_AS_TLS"
10161 "addi %0,%1,%2@dtprel@l")
10163 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10164 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10165 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10166 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10167 UNSPEC_TLSGOTDTPREL))]
10168 "HAVE_AS_TLS"
10169 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
10170 "&& TARGET_CMODEL != CMODEL_SMALL"
10171 [(set (match_dup 3)
10172 (high:TLSmode
10173 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
10174 (set (match_dup 0)
10175 (lo_sum:TLSmode (match_dup 3)
10176 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
10177 "
10178 {
10179 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10180 }"
10181 [(set (attr "length")
10182 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10183 (const_int 8)
10184 (const_int 4)))])
10186 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
10187 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10188 (high:TLSmode
10189 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10190 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10191 UNSPEC_TLSGOTDTPREL)))]
10192 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10193 "addis %0,%1,%2@got@dtprel@ha"
10194 [(set_attr "length" "4")])
10196 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
10197 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10198 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10199 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10200 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10201 UNSPEC_TLSGOTDTPREL)))]
10202 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10203 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
10204 [(set_attr "length" "4")])
10206 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10207 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10208 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10209 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10210 UNSPEC_TLSTPREL))]
10211 "HAVE_AS_TLS"
10212 "addi %0,%1,%2@tprel")
10214 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10215 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10216 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10217 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10218 UNSPEC_TLSTPRELHA))]
10219 "HAVE_AS_TLS"
10220 "addis %0,%1,%2@tprel@ha")
10222 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10223 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10224 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10225 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10226 UNSPEC_TLSTPRELLO))]
10227 "HAVE_AS_TLS"
10228 "addi %0,%1,%2@tprel@l")
10230 ;; "b" output constraint here and on tls_tls input to support linker tls
10231 ;; optimization. The linker may edit the instructions emitted by a
10232 ;; tls_got_tprel/tls_tls pair to addis,addi.
10233 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10234 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10235 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10236 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10237 UNSPEC_TLSGOTTPREL))]
10238 "HAVE_AS_TLS"
10239 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
10240 "&& TARGET_CMODEL != CMODEL_SMALL"
10241 [(set (match_dup 3)
10242 (high:TLSmode
10243 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
10244 (set (match_dup 0)
10245 (lo_sum:TLSmode (match_dup 3)
10246 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
10247 "
10248 {
10249 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10250 }"
10251 [(set (attr "length")
10252 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10253 (const_int 8)
10254 (const_int 4)))])
10256 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
10257 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10258 (high:TLSmode
10259 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10260 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10261 UNSPEC_TLSGOTTPREL)))]
10262 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10263 "addis %0,%1,%2@got@tprel@ha"
10264 [(set_attr "length" "4")])
10266 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
10267 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10268 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10269 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10270 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10271 UNSPEC_TLSGOTTPREL)))]
10272 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10273 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
10274 [(set_attr "length" "4")])
10276 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10277 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10278 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10279 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10280 UNSPEC_TLSTLS))]
10281 "TARGET_ELF && HAVE_AS_TLS"
10282 "add %0,%1,%2@tls")
10284 (define_expand "tls_get_tpointer"
10285 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10286 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
10287 "TARGET_XCOFF && HAVE_AS_TLS"
10288 "
10289 {
10290 emit_insn (gen_tls_get_tpointer_internal ());
10291 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
10292 DONE;
10293 }")
10295 (define_insn "tls_get_tpointer_internal"
10296 [(set (reg:SI 3)
10297 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
10298 (clobber (reg:SI LR_REGNO))]
10299 "TARGET_XCOFF && HAVE_AS_TLS"
10300 "bla __get_tpointer")
10302 (define_expand "tls_get_addr<mode>"
10303 [(set (match_operand:P 0 "gpc_reg_operand" "")
10304 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
10305 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
10306 "TARGET_XCOFF && HAVE_AS_TLS"
10307 "
10308 {
10309 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
10310 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
10311 emit_insn (gen_tls_get_addr_internal<mode> ());
10312 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
10313 DONE;
10314 }")
10316 (define_insn "tls_get_addr_internal<mode>"
10317 [(set (reg:P 3)
10318 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
10319 (clobber (reg:P 0))
10320 (clobber (reg:P 4))
10321 (clobber (reg:P 5))
10322 (clobber (reg:P 11))
10323 (clobber (reg:CC CR0_REGNO))
10324 (clobber (reg:P LR_REGNO))]
10325 "TARGET_XCOFF && HAVE_AS_TLS"
10326 "bla __tls_get_addr")
10327 \f
10328 ;; Next come insns related to the calling sequence.
10329 ;;
10330 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10331 ;; We move the back-chain and decrement the stack pointer.
10333 (define_expand "allocate_stack"
10334 [(set (match_operand 0 "gpc_reg_operand" "")
10335 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10336 (set (reg 1)
10337 (minus (reg 1) (match_dup 1)))]
10338 ""
10339 "
10340 { rtx chain = gen_reg_rtx (Pmode);
10341 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10342 rtx neg_op0;
10343 rtx insn, par, set, mem;
10345 emit_move_insn (chain, stack_bot);
10347 /* Check stack bounds if necessary. */
10348 if (crtl->limit_stack)
10349 {
10350 rtx available;
10351 available = expand_binop (Pmode, sub_optab,
10352 stack_pointer_rtx, stack_limit_rtx,
10353 NULL_RTX, 1, OPTAB_WIDEN);
10354 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10355 }
10357 if (GET_CODE (operands[1]) != CONST_INT
10358 || INTVAL (operands[1]) < -32767
10359 || INTVAL (operands[1]) > 32768)
10360 {
10361 neg_op0 = gen_reg_rtx (Pmode);
10362 if (TARGET_32BIT)
10363 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10364 else
10365 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10366 }
10367 else
10368 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10370 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10371 : gen_movdi_di_update_stack))
10372 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10373 chain));
10374 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10375 it now and set the alias set/attributes. The above gen_*_update
10376 calls will generate a PARALLEL with the MEM set being the first
10377 operation. */
10378 par = PATTERN (insn);
10379 gcc_assert (GET_CODE (par) == PARALLEL);
10380 set = XVECEXP (par, 0, 0);
10381 gcc_assert (GET_CODE (set) == SET);
10382 mem = SET_DEST (set);
10383 gcc_assert (MEM_P (mem));
10384 MEM_NOTRAP_P (mem) = 1;
10385 set_mem_alias_set (mem, get_frame_alias_set ());
10387 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10388 DONE;
10389 }")
10391 ;; These patterns say how to save and restore the stack pointer. We need not
10392 ;; save the stack pointer at function level since we are careful to
10393 ;; preserve the backchain. At block level, we have to restore the backchain
10394 ;; when we restore the stack pointer.
10395 ;;
10396 ;; For nonlocal gotos, we must save both the stack pointer and its
10397 ;; backchain and restore both. Note that in the nonlocal case, the
10398 ;; save area is a memory location.
10400 (define_expand "save_stack_function"
10401 [(match_operand 0 "any_operand" "")
10402 (match_operand 1 "any_operand" "")]
10403 ""
10404 "DONE;")
10406 (define_expand "restore_stack_function"
10407 [(match_operand 0 "any_operand" "")
10408 (match_operand 1 "any_operand" "")]
10409 ""
10410 "DONE;")
10412 ;; Adjust stack pointer (op0) to a new value (op1).
10413 ;; First copy old stack backchain to new location, and ensure that the
10414 ;; scheduler won't reorder the sp assignment before the backchain write.
10415 (define_expand "restore_stack_block"
10416 [(set (match_dup 2) (match_dup 3))
10417 (set (match_dup 4) (match_dup 2))
10418 (match_dup 5)
10419 (set (match_operand 0 "register_operand" "")
10420 (match_operand 1 "register_operand" ""))]
10421 ""
10422 "
10423 {
10424 rtvec p;
10426 operands[1] = force_reg (Pmode, operands[1]);
10427 operands[2] = gen_reg_rtx (Pmode);
10428 operands[3] = gen_frame_mem (Pmode, operands[0]);
10429 operands[4] = gen_frame_mem (Pmode, operands[1]);
10430 p = rtvec_alloc (1);
10431 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10432 gen_frame_mem (BLKmode, operands[0]),
10433 const0_rtx);
10434 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
10435 }")
10437 (define_expand "save_stack_nonlocal"
10438 [(set (match_dup 3) (match_dup 4))
10439 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10440 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10441 ""
10442 "
10443 {
10444 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10446 /* Copy the backchain to the first word, sp to the second. */
10447 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10448 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10449 operands[3] = gen_reg_rtx (Pmode);
10450 operands[4] = gen_frame_mem (Pmode, operands[1]);
10451 }")
10453 (define_expand "restore_stack_nonlocal"
10454 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10455 (set (match_dup 3) (match_dup 4))
10456 (set (match_dup 5) (match_dup 2))
10457 (match_dup 6)
10458 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10459 ""
10460 "
10461 {
10462 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10463 rtvec p;
10465 /* Restore the backchain from the first word, sp from the second. */
10466 operands[2] = gen_reg_rtx (Pmode);
10467 operands[3] = gen_reg_rtx (Pmode);
10468 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10469 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10470 operands[5] = gen_frame_mem (Pmode, operands[3]);
10471 p = rtvec_alloc (1);
10472 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10473 gen_frame_mem (BLKmode, operands[0]),
10474 const0_rtx);
10475 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
10476 }")
10477 \f
10478 ;; TOC register handling.
10480 ;; Code to initialize the TOC register...
10482 (define_insn "load_toc_aix_si"
10483 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10484 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10485 (use (reg:SI 2))])]
10486 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
10487 "*
10488 {
10489 char buf[30];
10490 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10491 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10492 operands[2] = gen_rtx_REG (Pmode, 2);
10493 return \"lwz %0,%1(%2)\";
10494 }"
10495 [(set_attr "type" "load")
10496 (set_attr "update" "no")
10497 (set_attr "indexed" "no")])
10499 (define_insn "load_toc_aix_di"
10500 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10501 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10502 (use (reg:DI 2))])]
10503 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
10504 "*
10505 {
10506 char buf[30];
10507 #ifdef TARGET_RELOCATABLE
10508 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10509 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10510 #else
10511 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10512 #endif
10513 if (TARGET_ELF)
10514 strcat (buf, \"@toc\");
10515 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10516 operands[2] = gen_rtx_REG (Pmode, 2);
10517 return \"ld %0,%1(%2)\";
10518 }"
10519 [(set_attr "type" "load")
10520 (set_attr "update" "no")
10521 (set_attr "indexed" "no")])
10523 (define_insn "load_toc_v4_pic_si"
10524 [(set (reg:SI LR_REGNO)
10525 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10526 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10527 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10528 [(set_attr "type" "branch")
10529 (set_attr "length" "4")])
10531 (define_expand "load_toc_v4_PIC_1"
10532 [(parallel [(set (reg:SI LR_REGNO)
10533 (match_operand:SI 0 "immediate_operand" "s"))
10534 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
10535 "TARGET_ELF && DEFAULT_ABI == ABI_V4
10536 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10537 "")
10539 (define_insn "load_toc_v4_PIC_1_normal"
10540 [(set (reg:SI LR_REGNO)
10541 (match_operand:SI 0 "immediate_operand" "s"))
10542 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10543 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10544 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10545 "bcl 20,31,%0\\n%0:"
10546 [(set_attr "type" "branch")
10547 (set_attr "length" "4")])
10549 (define_insn "load_toc_v4_PIC_1_476"
10550 [(set (reg:SI LR_REGNO)
10551 (match_operand:SI 0 "immediate_operand" "s"))
10552 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10553 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10554 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10555 "*
10556 {
10557 char name[32];
10558 static char templ[32];
10560 get_ppc476_thunk_name (name);
10561 sprintf (templ, \"bl %s\\n%%0:\", name);
10562 return templ;
10563 }"
10564 [(set_attr "type" "branch")
10565 (set_attr "length" "4")])
10567 (define_expand "load_toc_v4_PIC_1b"
10568 [(parallel [(set (reg:SI LR_REGNO)
10569 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10570 (label_ref (match_operand 1 "" ""))]
10571 UNSPEC_TOCPTR))
10572 (match_dup 1)])]
10573 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10574 "")
10576 (define_insn "load_toc_v4_PIC_1b_normal"
10577 [(set (reg:SI LR_REGNO)
10578 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10579 (label_ref (match_operand 1 "" ""))]
10580 UNSPEC_TOCPTR))
10581 (match_dup 1)]
10582 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10583 "bcl 20,31,$+8\;.long %0-$"
10584 [(set_attr "type" "branch")
10585 (set_attr "length" "8")])
10587 (define_insn "load_toc_v4_PIC_1b_476"
10588 [(set (reg:SI LR_REGNO)
10589 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10590 (label_ref (match_operand 1 "" ""))]
10591 UNSPEC_TOCPTR))
10592 (match_dup 1)]
10593 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10594 "*
10595 {
10596 char name[32];
10597 static char templ[32];
10599 get_ppc476_thunk_name (name);
10600 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
10601 return templ;
10602 }"
10603 [(set_attr "type" "branch")
10604 (set_attr "length" "16")])
10606 (define_insn "load_toc_v4_PIC_2"
10607 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10608 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10609 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10610 (match_operand:SI 3 "immediate_operand" "s")))))]
10611 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10612 "lwz %0,%2-%3(%1)"
10613 [(set_attr "type" "load")])
10615 (define_insn "load_toc_v4_PIC_3b"
10616 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10617 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10618 (high:SI
10619 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10620 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10621 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10622 "addis %0,%1,%2-%3@ha")
10624 (define_insn "load_toc_v4_PIC_3c"
10625 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10626 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10627 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10628 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10629 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10630 "addi %0,%1,%2-%3@l")
10632 ;; If the TOC is shared over a translation unit, as happens with all
10633 ;; the kinds of PIC that we support, we need to restore the TOC
10634 ;; pointer only when jumping over units of translation.
10635 ;; On Darwin, we need to reload the picbase.
10637 (define_expand "builtin_setjmp_receiver"
10638 [(use (label_ref (match_operand 0 "" "")))]
10639 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10640 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10641 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10642 "
10643 {
10644 #if TARGET_MACHO
10645 if (DEFAULT_ABI == ABI_DARWIN)
10646 {
10647 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10648 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10649 rtx tmplabrtx;
10650 char tmplab[20];
10652 crtl->uses_pic_offset_table = 1;
10653 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10654 CODE_LABEL_NUMBER (operands[0]));
10655 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10657 emit_insn (gen_load_macho_picbase (tmplabrtx));
10658 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10659 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10660 }
10661 else
10662 #endif
10663 rs6000_emit_load_toc_table (FALSE);
10664 DONE;
10665 }")
10667 ;; Largetoc support
10668 (define_insn "*largetoc_high"
10669 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10670 (high:DI
10671 (unspec [(match_operand:DI 1 "" "")
10672 (match_operand:DI 2 "gpc_reg_operand" "b")]
10673 UNSPEC_TOCREL)))]
10674 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10675 "addis %0,%2,%1@toc@ha")
10677 (define_insn "*largetoc_high_aix<mode>"
10678 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10679 (high:P
10680 (unspec [(match_operand:P 1 "" "")
10681 (match_operand:P 2 "gpc_reg_operand" "b")]
10682 UNSPEC_TOCREL)))]
10683 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10684 "addis %0,%1@u(%2)")
10686 (define_insn "*largetoc_high_plus"
10687 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10688 (high:DI
10689 (plus:DI
10690 (unspec [(match_operand:DI 1 "" "")
10691 (match_operand:DI 2 "gpc_reg_operand" "b")]
10692 UNSPEC_TOCREL)
10693 (match_operand:DI 3 "add_cint_operand" "n"))))]
10694 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10695 "addis %0,%2,%1+%3@toc@ha")
10697 (define_insn "*largetoc_high_plus_aix<mode>"
10698 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10699 (high:P
10700 (plus:P
10701 (unspec [(match_operand:P 1 "" "")
10702 (match_operand:P 2 "gpc_reg_operand" "b")]
10703 UNSPEC_TOCREL)
10704 (match_operand:P 3 "add_cint_operand" "n"))))]
10705 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10706 "addis %0,%1+%3@u(%2)")
10708 (define_insn "*largetoc_low"
10709 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10710 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
10711 (match_operand:DI 2 "" "")))]
10712 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10713 "addi %0,%1,%2@l")
10715 (define_insn "*largetoc_low_aix<mode>"
10716 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
10717 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
10718 (match_operand:P 2 "" "")))]
10719 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10720 "la %0,%2@l(%1)")
10722 (define_insn_and_split "*tocref<mode>"
10723 [(set (match_operand:P 0 "gpc_reg_operand" "=b")
10724 (match_operand:P 1 "small_toc_ref" "R"))]
10725 "TARGET_TOC"
10726 "la %0,%a1"
10727 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10728 [(set (match_dup 0) (high:P (match_dup 1)))
10729 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10731 ;; Elf specific ways of loading addresses for non-PIC code.
10732 ;; The output of this could be r0, but we make a very strong
10733 ;; preference for a base register because it will usually
10734 ;; be needed there.
10735 (define_insn "elf_high"
10736 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10737 (high:SI (match_operand 1 "" "")))]
10738 "TARGET_ELF && ! TARGET_64BIT"
10739 "lis %0,%1@ha")
10741 (define_insn "elf_low"
10742 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10743 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10744 (match_operand 2 "" "")))]
10745 "TARGET_ELF && ! TARGET_64BIT"
10746 "la %0,%2@l(%1)")
10747 \f
10748 ;; Call and call_value insns
10749 (define_expand "call"
10750 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10751 (match_operand 1 "" ""))
10752 (use (match_operand 2 "" ""))
10753 (clobber (reg:SI LR_REGNO))])]
10754 ""
10755 "
10756 {
10757 #if TARGET_MACHO
10758 if (MACHOPIC_INDIRECT)
10759 operands[0] = machopic_indirect_call_target (operands[0]);
10760 #endif
10762 gcc_assert (GET_CODE (operands[0]) == MEM);
10763 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10765 operands[0] = XEXP (operands[0], 0);
10767 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10768 {
10769 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
10770 DONE;
10771 }
10773 if (GET_CODE (operands[0]) != SYMBOL_REF
10774 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10775 {
10776 if (INTVAL (operands[2]) & CALL_LONG)
10777 operands[0] = rs6000_longcall_ref (operands[0]);
10779 switch (DEFAULT_ABI)
10780 {
10781 case ABI_V4:
10782 case ABI_DARWIN:
10783 operands[0] = force_reg (Pmode, operands[0]);
10784 break;
10786 default:
10787 gcc_unreachable ();
10788 }
10789 }
10790 }")
10792 (define_expand "call_value"
10793 [(parallel [(set (match_operand 0 "" "")
10794 (call (mem:SI (match_operand 1 "address_operand" ""))
10795 (match_operand 2 "" "")))
10796 (use (match_operand 3 "" ""))
10797 (clobber (reg:SI LR_REGNO))])]
10798 ""
10799 "
10800 {
10801 #if TARGET_MACHO
10802 if (MACHOPIC_INDIRECT)
10803 operands[1] = machopic_indirect_call_target (operands[1]);
10804 #endif
10806 gcc_assert (GET_CODE (operands[1]) == MEM);
10807 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10809 operands[1] = XEXP (operands[1], 0);
10811 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10812 {
10813 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
10814 DONE;
10815 }
10817 if (GET_CODE (operands[1]) != SYMBOL_REF
10818 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10819 {
10820 if (INTVAL (operands[3]) & CALL_LONG)
10821 operands[1] = rs6000_longcall_ref (operands[1]);
10823 switch (DEFAULT_ABI)
10824 {
10825 case ABI_V4:
10826 case ABI_DARWIN:
10827 operands[1] = force_reg (Pmode, operands[1]);
10828 break;
10830 default:
10831 gcc_unreachable ();
10832 }
10833 }
10834 }")
10836 ;; Call to function in current module. No TOC pointer reload needed.
10837 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10838 ;; either the function was not prototyped, or it was prototyped as a
10839 ;; variable argument function. It is > 0 if FP registers were passed
10840 ;; and < 0 if they were not.
10842 (define_insn "*call_local32"
10843 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10844 (match_operand 1 "" "g,g"))
10845 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10846 (clobber (reg:SI LR_REGNO))]
10847 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10848 "*
10849 {
10850 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10851 output_asm_insn (\"crxor 6,6,6\", operands);
10853 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10854 output_asm_insn (\"creqv 6,6,6\", operands);
10856 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10857 }"
10858 [(set_attr "type" "branch")
10859 (set_attr "length" "4,8")])
10861 (define_insn "*call_local64"
10862 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10863 (match_operand 1 "" "g,g"))
10864 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10865 (clobber (reg:SI LR_REGNO))]
10866 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10867 "*
10868 {
10869 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10870 output_asm_insn (\"crxor 6,6,6\", operands);
10872 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10873 output_asm_insn (\"creqv 6,6,6\", operands);
10875 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10876 }"
10877 [(set_attr "type" "branch")
10878 (set_attr "length" "4,8")])
10880 (define_insn "*call_value_local32"
10881 [(set (match_operand 0 "" "")
10882 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10883 (match_operand 2 "" "g,g")))
10884 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10885 (clobber (reg:SI LR_REGNO))]
10886 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10887 "*
10888 {
10889 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10890 output_asm_insn (\"crxor 6,6,6\", operands);
10892 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10893 output_asm_insn (\"creqv 6,6,6\", operands);
10895 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10896 }"
10897 [(set_attr "type" "branch")
10898 (set_attr "length" "4,8")])
10901 (define_insn "*call_value_local64"
10902 [(set (match_operand 0 "" "")
10903 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10904 (match_operand 2 "" "g,g")))
10905 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10906 (clobber (reg:SI LR_REGNO))]
10907 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10908 "*
10909 {
10910 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10911 output_asm_insn (\"crxor 6,6,6\", operands);
10913 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10914 output_asm_insn (\"creqv 6,6,6\", operands);
10916 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10917 }"
10918 [(set_attr "type" "branch")
10919 (set_attr "length" "4,8")])
10922 ;; A function pointer under System V is just a normal pointer
10923 ;; operands[0] is the function pointer
10924 ;; operands[1] is the stack size to clean up
10925 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10926 ;; which indicates how to set cr1
10928 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10929 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10930 (match_operand 1 "" "g,g,g,g"))
10931 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10932 (clobber (reg:SI LR_REGNO))]
10933 "DEFAULT_ABI == ABI_V4
10934 || DEFAULT_ABI == ABI_DARWIN"
10935 {
10936 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10937 output_asm_insn ("crxor 6,6,6", operands);
10939 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10940 output_asm_insn ("creqv 6,6,6", operands);
10942 return "b%T0l";
10943 }
10944 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10945 (set_attr "length" "4,4,8,8")])
10947 (define_insn_and_split "*call_nonlocal_sysv<mode>"
10948 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10949 (match_operand 1 "" "g,g"))
10950 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10951 (clobber (reg:SI LR_REGNO))]
10952 "(DEFAULT_ABI == ABI_DARWIN
10953 || (DEFAULT_ABI == ABI_V4
10954 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10955 {
10956 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10957 output_asm_insn ("crxor 6,6,6", operands);
10959 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10960 output_asm_insn ("creqv 6,6,6", operands);
10962 #if TARGET_MACHO
10963 return output_call(insn, operands, 0, 2);
10964 #else
10965 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10966 {
10967 gcc_assert (!TARGET_SECURE_PLT);
10968 return "bl %z0@plt";
10969 }
10970 else
10971 return "bl %z0";
10972 #endif
10973 }
10974 "DEFAULT_ABI == ABI_V4
10975 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10976 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10977 [(parallel [(call (mem:SI (match_dup 0))
10978 (match_dup 1))
10979 (use (match_dup 2))
10980 (use (match_dup 3))
10981 (clobber (reg:SI LR_REGNO))])]
10982 {
10983 operands[3] = pic_offset_table_rtx;
10984 }
10985 [(set_attr "type" "branch,branch")
10986 (set_attr "length" "4,8")])
10988 (define_insn "*call_nonlocal_sysv_secure<mode>"
10989 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10990 (match_operand 1 "" "g,g"))
10991 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10992 (use (match_operand:SI 3 "register_operand" "r,r"))
10993 (clobber (reg:SI LR_REGNO))]
10994 "(DEFAULT_ABI == ABI_V4
10995 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10996 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
10997 {
10998 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10999 output_asm_insn ("crxor 6,6,6", operands);
11001 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11002 output_asm_insn ("creqv 6,6,6", operands);
11004 if (flag_pic == 2)
11005 /* The magic 32768 offset here and in the other sysv call insns
11006 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11007 See sysv4.h:toc_section. */
11008 return "bl %z0+32768@plt";
11009 else
11010 return "bl %z0@plt";
11011 }
11012 [(set_attr "type" "branch,branch")
11013 (set_attr "length" "4,8")])
11015 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11016 [(set (match_operand 0 "" "")
11017 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11018 (match_operand 2 "" "g,g,g,g")))
11019 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11020 (clobber (reg:SI LR_REGNO))]
11021 "DEFAULT_ABI == ABI_V4
11022 || DEFAULT_ABI == ABI_DARWIN"
11023 {
11024 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11025 output_asm_insn ("crxor 6,6,6", operands);
11027 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11028 output_asm_insn ("creqv 6,6,6", operands);
11030 return "b%T1l";
11031 }
11032 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11033 (set_attr "length" "4,4,8,8")])
11035 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11036 [(set (match_operand 0 "" "")
11037 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11038 (match_operand 2 "" "g,g")))
11039 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11040 (clobber (reg:SI LR_REGNO))]
11041 "(DEFAULT_ABI == ABI_DARWIN
11042 || (DEFAULT_ABI == ABI_V4
11043 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11044 {
11045 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11046 output_asm_insn ("crxor 6,6,6", operands);
11048 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11049 output_asm_insn ("creqv 6,6,6", operands);
11051 #if TARGET_MACHO
11052 return output_call(insn, operands, 1, 3);
11053 #else
11054 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11055 {
11056 gcc_assert (!TARGET_SECURE_PLT);
11057 return "bl %z1@plt";
11058 }
11059 else
11060 return "bl %z1";
11061 #endif
11062 }
11063 "DEFAULT_ABI == ABI_V4
11064 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11065 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11066 [(parallel [(set (match_dup 0)
11067 (call (mem:SI (match_dup 1))
11068 (match_dup 2)))
11069 (use (match_dup 3))
11070 (use (match_dup 4))
11071 (clobber (reg:SI LR_REGNO))])]
11072 {
11073 operands[4] = pic_offset_table_rtx;
11074 }
11075 [(set_attr "type" "branch,branch")
11076 (set_attr "length" "4,8")])
11078 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11079 [(set (match_operand 0 "" "")
11080 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11081 (match_operand 2 "" "g,g")))
11082 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11083 (use (match_operand:SI 4 "register_operand" "r,r"))
11084 (clobber (reg:SI LR_REGNO))]
11085 "(DEFAULT_ABI == ABI_V4
11086 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11087 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11088 {
11089 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11090 output_asm_insn ("crxor 6,6,6", operands);
11092 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11093 output_asm_insn ("creqv 6,6,6", operands);
11095 if (flag_pic == 2)
11096 return "bl %z1+32768@plt";
11097 else
11098 return "bl %z1@plt";
11099 }
11100 [(set_attr "type" "branch,branch")
11101 (set_attr "length" "4,8")])
11104 ;; Call to AIX abi function in the same module.
11106 (define_insn "*call_local_aix<mode>"
11107 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
11108 (match_operand 1 "" "g"))
11109 (clobber (reg:P LR_REGNO))]
11110 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11111 "bl %z0"
11112 [(set_attr "type" "branch")
11113 (set_attr "length" "4")])
11115 (define_insn "*call_value_local_aix<mode>"
11116 [(set (match_operand 0 "" "")
11117 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
11118 (match_operand 2 "" "g")))
11119 (clobber (reg:P LR_REGNO))]
11120 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11121 "bl %z1"
11122 [(set_attr "type" "branch")
11123 (set_attr "length" "4")])
11125 ;; Call to AIX abi function which may be in another module.
11126 ;; Restore the TOC pointer (r2) after the call.
11128 (define_insn "*call_nonlocal_aix<mode>"
11129 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
11130 (match_operand 1 "" "g"))
11131 (clobber (reg:P LR_REGNO))]
11132 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11133 "bl %z0\;nop"
11134 [(set_attr "type" "branch")
11135 (set_attr "length" "8")])
11137 (define_insn "*call_value_nonlocal_aix<mode>"
11138 [(set (match_operand 0 "" "")
11139 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
11140 (match_operand 2 "" "g")))
11141 (clobber (reg:P LR_REGNO))]
11142 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11143 "bl %z1\;nop"
11144 [(set_attr "type" "branch")
11145 (set_attr "length" "8")])
11147 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
11148 ;; Operand0 is the addresss of the function to call
11149 ;; Operand2 is the location in the function descriptor to load r2 from
11150 ;; Operand3 is the stack location to hold the current TOC pointer
11152 (define_insn "*call_indirect_aix<mode>"
11153 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11154 (match_operand 1 "" "g,g"))
11155 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11156 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11157 (clobber (reg:P LR_REGNO))]
11158 "DEFAULT_ABI == ABI_AIX"
11159 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11160 [(set_attr "type" "jmpreg")
11161 (set_attr "length" "12")])
11163 (define_insn "*call_value_indirect_aix<mode>"
11164 [(set (match_operand 0 "" "")
11165 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11166 (match_operand 2 "" "g,g")))
11167 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11168 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11169 (clobber (reg:P LR_REGNO))]
11170 "DEFAULT_ABI == ABI_AIX"
11171 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11172 [(set_attr "type" "jmpreg")
11173 (set_attr "length" "12")])
11175 ;; Call to indirect functions with the ELFv2 ABI.
11176 ;; Operand0 is the addresss of the function to call
11177 ;; Operand2 is the stack location to hold the current TOC pointer
11179 (define_insn "*call_indirect_elfv2<mode>"
11180 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11181 (match_operand 1 "" "g,g"))
11182 (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11183 (clobber (reg:P LR_REGNO))]
11184 "DEFAULT_ABI == ABI_ELFv2"
11185 "b%T0l\;<ptrload> 2,%2"
11186 [(set_attr "type" "jmpreg")
11187 (set_attr "length" "8")])
11189 (define_insn "*call_value_indirect_elfv2<mode>"
11190 [(set (match_operand 0 "" "")
11191 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11192 (match_operand 2 "" "g,g")))
11193 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11194 (clobber (reg:P LR_REGNO))]
11195 "DEFAULT_ABI == ABI_ELFv2"
11196 "b%T1l\;<ptrload> 2,%3"
11197 [(set_attr "type" "jmpreg")
11198 (set_attr "length" "8")])
11201 ;; Call subroutine returning any type.
11202 (define_expand "untyped_call"
11203 [(parallel [(call (match_operand 0 "" "")
11204 (const_int 0))
11205 (match_operand 1 "" "")
11206 (match_operand 2 "" "")])]
11207 ""
11208 "
11209 {
11210 int i;
11212 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11214 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11215 {
11216 rtx set = XVECEXP (operands[2], 0, i);
11217 emit_move_insn (SET_DEST (set), SET_SRC (set));
11218 }
11220 /* The optimizer does not know that the call sets the function value
11221 registers we stored in the result block. We avoid problems by
11222 claiming that all hard registers are used and clobbered at this
11223 point. */
11224 emit_insn (gen_blockage ());
11226 DONE;
11227 }")
11229 ;; sibling call patterns
11230 (define_expand "sibcall"
11231 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11232 (match_operand 1 "" ""))
11233 (use (match_operand 2 "" ""))
11234 (use (reg:SI LR_REGNO))
11235 (simple_return)])]
11236 ""
11237 "
11238 {
11239 #if TARGET_MACHO
11240 if (MACHOPIC_INDIRECT)
11241 operands[0] = machopic_indirect_call_target (operands[0]);
11242 #endif
11244 gcc_assert (GET_CODE (operands[0]) == MEM);
11245 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11247 operands[0] = XEXP (operands[0], 0);
11249 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11250 {
11251 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
11252 DONE;
11253 }
11254 }")
11256 (define_expand "sibcall_value"
11257 [(parallel [(set (match_operand 0 "register_operand" "")
11258 (call (mem:SI (match_operand 1 "address_operand" ""))
11259 (match_operand 2 "" "")))
11260 (use (match_operand 3 "" ""))
11261 (use (reg:SI LR_REGNO))
11262 (simple_return)])]
11263 ""
11264 "
11265 {
11266 #if TARGET_MACHO
11267 if (MACHOPIC_INDIRECT)
11268 operands[1] = machopic_indirect_call_target (operands[1]);
11269 #endif
11271 gcc_assert (GET_CODE (operands[1]) == MEM);
11272 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11274 operands[1] = XEXP (operands[1], 0);
11276 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11277 {
11278 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
11279 DONE;
11280 }
11281 }")
11283 ;; this and similar patterns must be marked as using LR, otherwise
11284 ;; dataflow will try to delete the store into it. This is true
11285 ;; even when the actual reg to jump to is in CTR, when LR was
11286 ;; saved and restored around the PIC-setting BCL.
11287 (define_insn "*sibcall_local32"
11288 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11289 (match_operand 1 "" "g,g"))
11290 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11291 (use (reg:SI LR_REGNO))
11292 (simple_return)]
11293 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11294 "*
11295 {
11296 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11297 output_asm_insn (\"crxor 6,6,6\", operands);
11299 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11300 output_asm_insn (\"creqv 6,6,6\", operands);
11302 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11303 }"
11304 [(set_attr "type" "branch")
11305 (set_attr "length" "4,8")])
11307 (define_insn "*sibcall_local64"
11308 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11309 (match_operand 1 "" "g,g"))
11310 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11311 (use (reg:SI LR_REGNO))
11312 (simple_return)]
11313 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11314 "*
11315 {
11316 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11317 output_asm_insn (\"crxor 6,6,6\", operands);
11319 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11320 output_asm_insn (\"creqv 6,6,6\", operands);
11322 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11323 }"
11324 [(set_attr "type" "branch")
11325 (set_attr "length" "4,8")])
11327 (define_insn "*sibcall_value_local32"
11328 [(set (match_operand 0 "" "")
11329 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11330 (match_operand 2 "" "g,g")))
11331 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11332 (use (reg:SI LR_REGNO))
11333 (simple_return)]
11334 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11335 "*
11336 {
11337 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11338 output_asm_insn (\"crxor 6,6,6\", operands);
11340 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11341 output_asm_insn (\"creqv 6,6,6\", operands);
11343 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11344 }"
11345 [(set_attr "type" "branch")
11346 (set_attr "length" "4,8")])
11348 (define_insn "*sibcall_value_local64"
11349 [(set (match_operand 0 "" "")
11350 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11351 (match_operand 2 "" "g,g")))
11352 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11353 (use (reg:SI LR_REGNO))
11354 (simple_return)]
11355 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11356 "*
11357 {
11358 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11359 output_asm_insn (\"crxor 6,6,6\", operands);
11361 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11362 output_asm_insn (\"creqv 6,6,6\", operands);
11364 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11365 }"
11366 [(set_attr "type" "branch")
11367 (set_attr "length" "4,8")])
11369 (define_insn "*sibcall_nonlocal_sysv<mode>"
11370 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
11371 (match_operand 1 "" ""))
11372 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
11373 (use (reg:SI LR_REGNO))
11374 (simple_return)]
11375 "(DEFAULT_ABI == ABI_DARWIN
11376 || DEFAULT_ABI == ABI_V4)
11377 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11378 "*
11379 {
11380 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11381 output_asm_insn (\"crxor 6,6,6\", operands);
11383 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11384 output_asm_insn (\"creqv 6,6,6\", operands);
11386 if (which_alternative >= 2)
11387 return \"b%T0\";
11388 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11389 {
11390 gcc_assert (!TARGET_SECURE_PLT);
11391 return \"b %z0@plt\";
11392 }
11393 else
11394 return \"b %z0\";
11395 }"
11396 [(set_attr "type" "branch")
11397 (set_attr "length" "4,8,4,8")])
11399 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11400 [(set (match_operand 0 "" "")
11401 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
11402 (match_operand 2 "" "")))
11403 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
11404 (use (reg:SI LR_REGNO))
11405 (simple_return)]
11406 "(DEFAULT_ABI == ABI_DARWIN
11407 || DEFAULT_ABI == ABI_V4)
11408 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11409 "*
11410 {
11411 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11412 output_asm_insn (\"crxor 6,6,6\", operands);
11414 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11415 output_asm_insn (\"creqv 6,6,6\", operands);
11417 if (which_alternative >= 2)
11418 return \"b%T1\";
11419 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11420 {
11421 gcc_assert (!TARGET_SECURE_PLT);
11422 return \"b %z1@plt\";
11423 }
11424 else
11425 return \"b %z1\";
11426 }"
11427 [(set_attr "type" "branch")
11428 (set_attr "length" "4,8,4,8")])
11430 ;; AIX ABI sibling call patterns.
11432 (define_insn "*sibcall_aix<mode>"
11433 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
11434 (match_operand 1 "" "g,g"))
11435 (simple_return)]
11436 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11437 "@
11438 b %z0
11439 b%T0"
11440 [(set_attr "type" "branch")
11441 (set_attr "length" "4")])
11443 (define_insn "*sibcall_value_aix<mode>"
11444 [(set (match_operand 0 "" "")
11445 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
11446 (match_operand 2 "" "g,g")))
11447 (simple_return)]
11448 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11449 "@
11450 b %z1
11451 b%T1"
11452 [(set_attr "type" "branch")
11453 (set_attr "length" "4")])
11455 (define_expand "sibcall_epilogue"
11456 [(use (const_int 0))]
11457 ""
11458 {
11459 if (!TARGET_SCHED_PROLOG)
11460 emit_insn (gen_blockage ());
11461 rs6000_emit_epilogue (TRUE);
11462 DONE;
11463 })
11465 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11466 ;; all of memory. This blocks insns from being moved across this point.
11468 (define_insn "blockage"
11469 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11470 ""
11471 "")
11473 (define_expand "probe_stack"
11474 [(set (match_operand 0 "memory_operand" "=m")
11475 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
11476 ""
11477 {
11478 if (TARGET_64BIT)
11479 emit_insn (gen_probe_stack_di (operands[0]));
11480 else
11481 emit_insn (gen_probe_stack_si (operands[0]));
11482 DONE;
11483 })
11485 (define_insn "probe_stack_<mode>"
11486 [(set (match_operand:P 0 "memory_operand" "=m")
11487 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
11488 ""
11489 {
11490 operands[1] = gen_rtx_REG (Pmode, 0);
11491 return "st<wd>%U0%X0 %1,%0";
11492 }
11493 [(set_attr "type" "store")
11494 (set (attr "update")
11495 (if_then_else (match_operand 0 "update_address_mem")
11496 (const_string "yes")
11497 (const_string "no")))
11498 (set (attr "indexed")
11499 (if_then_else (match_operand 0 "indexed_address_mem")
11500 (const_string "yes")
11501 (const_string "no")))
11502 (set_attr "length" "4")])
11504 (define_insn "probe_stack_range<P:mode>"
11505 [(set (match_operand:P 0 "register_operand" "=r")
11506 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
11507 (match_operand:P 2 "register_operand" "r")]
11508 UNSPECV_PROBE_STACK_RANGE))]
11509 ""
11510 "* return output_probe_stack_range (operands[0], operands[2]);"
11511 [(set_attr "type" "three")])
11512 \f
11513 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11514 ;; signed & unsigned, and one type of branch.
11515 ;;
11516 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11517 ;; insns, and branches.
11519 (define_expand "cbranch<mode>4"
11520 [(use (match_operator 0 "rs6000_cbranch_operator"
11521 [(match_operand:GPR 1 "gpc_reg_operand" "")
11522 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11523 (use (match_operand 3 ""))]
11524 ""
11525 "
11526 {
11527 /* Take care of the possibility that operands[2] might be negative but
11528 this might be a logical operation. That insn doesn't exist. */
11529 if (GET_CODE (operands[2]) == CONST_INT
11530 && INTVAL (operands[2]) < 0)
11531 {
11532 operands[2] = force_reg (<MODE>mode, operands[2]);
11533 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11534 GET_MODE (operands[0]),
11535 operands[1], operands[2]);
11536 }
11538 rs6000_emit_cbranch (<MODE>mode, operands);
11539 DONE;
11540 }")
11542 (define_expand "cbranch<mode>4"
11543 [(use (match_operator 0 "rs6000_cbranch_operator"
11544 [(match_operand:FP 1 "gpc_reg_operand" "")
11545 (match_operand:FP 2 "gpc_reg_operand" "")]))
11546 (use (match_operand 3 ""))]
11547 ""
11548 "
11549 {
11550 rs6000_emit_cbranch (<MODE>mode, operands);
11551 DONE;
11552 }")
11554 (define_expand "cstore<mode>4"
11555 [(use (match_operator 1 "rs6000_cbranch_operator"
11556 [(match_operand:GPR 2 "gpc_reg_operand" "")
11557 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11558 (clobber (match_operand:SI 0 "register_operand"))]
11559 ""
11560 "
11561 {
11562 /* Take care of the possibility that operands[3] might be negative but
11563 this might be a logical operation. That insn doesn't exist. */
11564 if (GET_CODE (operands[3]) == CONST_INT
11565 && INTVAL (operands[3]) < 0)
11566 {
11567 operands[3] = force_reg (<MODE>mode, operands[3]);
11568 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
11569 GET_MODE (operands[1]),
11570 operands[2], operands[3]);
11571 }
11573 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
11574 For SEQ, likewise, except that comparisons with zero should be done
11575 with an scc insns. However, due to the order that combine see the
11576 resulting insns, we must, in fact, allow SEQ for integers. Fail in
11577 the cases we don't want to handle or are best handled by portable
11578 code. */
11579 if (GET_CODE (operands[1]) == NE)
11580 FAIL;
11581 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11582 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
11583 && operands[3] == const0_rtx)
11584 FAIL;
11585 rs6000_emit_sCOND (<MODE>mode, operands);
11586 DONE;
11587 }")
11589 (define_expand "cstore<mode>4"
11590 [(use (match_operator 1 "rs6000_cbranch_operator"
11591 [(match_operand:FP 2 "gpc_reg_operand" "")
11592 (match_operand:FP 3 "gpc_reg_operand" "")]))
11593 (clobber (match_operand:SI 0 "register_operand"))]
11594 ""
11595 "
11596 {
11597 rs6000_emit_sCOND (<MODE>mode, operands);
11598 DONE;
11599 }")
11602 (define_expand "stack_protect_set"
11603 [(match_operand 0 "memory_operand" "")
11604 (match_operand 1 "memory_operand" "")]
11605 ""
11606 {
11607 #ifdef TARGET_THREAD_SSP_OFFSET
11608 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11609 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11610 operands[1] = gen_rtx_MEM (Pmode, addr);
11611 #endif
11612 if (TARGET_64BIT)
11613 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11614 else
11615 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11616 DONE;
11617 })
11619 (define_insn "stack_protect_setsi"
11620 [(set (match_operand:SI 0 "memory_operand" "=m")
11621 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11622 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11623 "TARGET_32BIT"
11624 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
11625 [(set_attr "type" "three")
11626 (set_attr "length" "12")])
11628 (define_insn "stack_protect_setdi"
11629 [(set (match_operand:DI 0 "memory_operand" "=Y")
11630 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11631 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11632 "TARGET_64BIT"
11633 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
11634 [(set_attr "type" "three")
11635 (set_attr "length" "12")])
11637 (define_expand "stack_protect_test"
11638 [(match_operand 0 "memory_operand" "")
11639 (match_operand 1 "memory_operand" "")
11640 (match_operand 2 "" "")]
11641 ""
11642 {
11643 rtx test, op0, op1;
11644 #ifdef TARGET_THREAD_SSP_OFFSET
11645 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11646 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11647 operands[1] = gen_rtx_MEM (Pmode, addr);
11648 #endif
11649 op0 = operands[0];
11650 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11651 test = gen_rtx_EQ (VOIDmode, op0, op1);
11652 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11653 DONE;
11654 })
11656 (define_insn "stack_protect_testsi"
11657 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11658 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11659 (match_operand:SI 2 "memory_operand" "m,m")]
11660 UNSPEC_SP_TEST))
11661 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11662 (clobber (match_scratch:SI 3 "=&r,&r"))]
11663 "TARGET_32BIT"
11664 "@
11665 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11666 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
11667 [(set_attr "length" "16,20")])
11669 (define_insn "stack_protect_testdi"
11670 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11671 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11672 (match_operand:DI 2 "memory_operand" "Y,Y")]
11673 UNSPEC_SP_TEST))
11674 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11675 (clobber (match_scratch:DI 3 "=&r,&r"))]
11676 "TARGET_64BIT"
11677 "@
11678 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11679 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
11680 [(set_attr "length" "16,20")])
11682 \f
11683 ;; Here are the actual compare insns.
11684 (define_insn "*cmp<mode>_internal1"
11685 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11686 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11687 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11688 ""
11689 "cmp<wd>%I2 %0,%1,%2"
11690 [(set_attr "type" "cmp")])
11692 ;; If we are comparing a register for equality with a large constant,
11693 ;; we can do this with an XOR followed by a compare. But this is profitable
11694 ;; only if the large constant is only used for the comparison (and in this
11695 ;; case we already have a register to reuse as scratch).
11696 ;;
11697 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11698 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11700 (define_peephole2
11701 [(set (match_operand:SI 0 "register_operand")
11702 (match_operand:SI 1 "logical_const_operand" ""))
11703 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11704 [(match_dup 0)
11705 (match_operand:SI 2 "logical_const_operand" "")]))
11706 (set (match_operand:CC 4 "cc_reg_operand" "")
11707 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11708 (match_dup 0)))
11709 (set (pc)
11710 (if_then_else (match_operator 6 "equality_operator"
11711 [(match_dup 4) (const_int 0)])
11712 (match_operand 7 "" "")
11713 (match_operand 8 "" "")))]
11714 "peep2_reg_dead_p (3, operands[0])
11715 && peep2_reg_dead_p (4, operands[4])"
11716 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11717 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11718 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11720 {
11721 /* Get the constant we are comparing against, and see what it looks like
11722 when sign-extended from 16 to 32 bits. Then see what constant we could
11723 XOR with SEXTC to get the sign-extended value. */
11724 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11725 SImode,
11726 operands[1], operands[2]);
11727 HOST_WIDE_INT c = INTVAL (cnst);
11728 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11729 HOST_WIDE_INT xorv = c ^ sextc;
11731 operands[9] = GEN_INT (xorv);
11732 operands[10] = GEN_INT (sextc);
11733 })
11735 (define_insn "*cmpsi_internal2"
11736 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11737 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11738 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11739 ""
11740 "cmplw%I2 %0,%1,%b2"
11741 [(set_attr "type" "cmp")])
11743 (define_insn "*cmpdi_internal2"
11744 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11745 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11746 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11747 ""
11748 "cmpld%I2 %0,%1,%b2"
11749 [(set_attr "type" "cmp")])
11751 ;; The following two insns don't exist as single insns, but if we provide
11752 ;; them, we can swap an add and compare, which will enable us to overlap more
11753 ;; of the required delay between a compare and branch. We generate code for
11754 ;; them by splitting.
11756 (define_insn ""
11757 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11758 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11759 (match_operand:SI 2 "short_cint_operand" "i")))
11760 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11761 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11762 ""
11763 "#"
11764 [(set_attr "length" "8")])
11766 (define_insn ""
11767 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11768 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11769 (match_operand:SI 2 "u_short_cint_operand" "i")))
11770 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11771 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11772 ""
11773 "#"
11774 [(set_attr "length" "8")])
11776 (define_split
11777 [(set (match_operand:CC 3 "cc_reg_operand" "")
11778 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11779 (match_operand:SI 2 "short_cint_operand" "")))
11780 (set (match_operand:SI 0 "gpc_reg_operand" "")
11781 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11782 ""
11783 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11784 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11786 (define_split
11787 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11788 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11789 (match_operand:SI 2 "u_short_cint_operand" "")))
11790 (set (match_operand:SI 0 "gpc_reg_operand" "")
11791 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11792 ""
11793 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11794 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11796 ;; Only need to compare second words if first words equal
11797 (define_insn "*cmptf_internal1"
11798 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11799 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11800 (match_operand:TF 2 "gpc_reg_operand" "d")))]
11801 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11802 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11803 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11804 [(set_attr "type" "fpcompare")
11805 (set_attr "length" "12")])
11807 (define_insn_and_split "*cmptf_internal2"
11808 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11809 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11810 (match_operand:TF 2 "gpc_reg_operand" "d")))
11811 (clobber (match_scratch:DF 3 "=d"))
11812 (clobber (match_scratch:DF 4 "=d"))
11813 (clobber (match_scratch:DF 5 "=d"))
11814 (clobber (match_scratch:DF 6 "=d"))
11815 (clobber (match_scratch:DF 7 "=d"))
11816 (clobber (match_scratch:DF 8 "=d"))
11817 (clobber (match_scratch:DF 9 "=d"))
11818 (clobber (match_scratch:DF 10 "=d"))
11819 (clobber (match_scratch:GPR 11 "=b"))]
11820 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11821 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11822 "#"
11823 "&& reload_completed"
11824 [(set (match_dup 3) (match_dup 14))
11825 (set (match_dup 4) (match_dup 15))
11826 (set (match_dup 9) (abs:DF (match_dup 5)))
11827 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11828 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11829 (label_ref (match_dup 12))
11830 (pc)))
11831 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11832 (set (pc) (label_ref (match_dup 13)))
11833 (match_dup 12)
11834 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11835 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11836 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11837 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
11838 (match_dup 13)]
11839 {
11840 REAL_VALUE_TYPE rv;
11841 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
11842 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
11844 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11845 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11846 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11847 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11848 operands[12] = gen_label_rtx ();
11849 operands[13] = gen_label_rtx ();
11850 real_inf (&rv);
11851 operands[14] = force_const_mem (DFmode,
11852 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11853 operands[15] = force_const_mem (DFmode,
11854 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11855 DFmode));
11856 if (TARGET_TOC)
11857 {
11858 rtx tocref;
11859 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
11860 operands[14] = gen_const_mem (DFmode, tocref);
11861 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
11862 operands[15] = gen_const_mem (DFmode, tocref);
11863 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11864 set_mem_alias_set (operands[15], get_TOC_alias_set ());
11865 }
11866 })
11867 \f
11868 ;; Now we have the scc insns. We can do some combinations because of the
11869 ;; way the machine works.
11870 ;;
11871 ;; Note that this is probably faster if we can put an insn between the
11872 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11873 ;; cases the insns below which don't use an intermediate CR field will
11874 ;; be used instead.
11875 (define_insn ""
11876 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11877 (match_operator:SI 1 "scc_comparison_operator"
11878 [(match_operand 2 "cc_reg_operand" "y")
11879 (const_int 0)]))]
11880 ""
11881 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11882 [(set (attr "type")
11883 (cond [(match_test "TARGET_MFCRF")
11884 (const_string "mfcrf")
11885 ]
11886 (const_string "mfcr")))
11887 (set_attr "length" "8")])
11889 ;; Same as above, but get the GT bit.
11890 (define_insn "move_from_CR_gt_bit"
11891 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11892 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11893 "TARGET_HARD_FLOAT && !TARGET_FPRS"
11894 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
11895 [(set_attr "type" "mfcr")
11896 (set_attr "length" "8")])
11898 ;; Same as above, but get the OV/ORDERED bit.
11899 (define_insn "move_from_CR_ov_bit"
11900 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11901 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
11902 UNSPEC_MV_CR_OV))]
11903 "TARGET_ISEL"
11904 "mfcr %0\;rlwinm %0,%0,%t1,1"
11905 [(set_attr "type" "mfcr")
11906 (set_attr "length" "8")])
11908 (define_insn ""
11909 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11910 (match_operator:DI 1 "scc_comparison_operator"
11911 [(match_operand 2 "cc_reg_operand" "y")
11912 (const_int 0)]))]
11913 "TARGET_POWERPC64"
11914 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11915 [(set (attr "type")
11916 (cond [(match_test "TARGET_MFCRF")
11917 (const_string "mfcrf")
11918 ]
11919 (const_string "mfcr")))
11920 (set_attr "length" "8")])
11922 (define_insn ""
11923 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11924 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11925 [(match_operand 2 "cc_reg_operand" "y,y")
11926 (const_int 0)])
11927 (const_int 0)))
11928 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11929 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11930 "TARGET_32BIT"
11931 "@
11932 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
11933 #"
11934 [(set_attr "type" "shift")
11935 (set_attr "dot" "yes")
11936 (set_attr "length" "8,16")])
11938 (define_split
11939 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11940 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11941 [(match_operand 2 "cc_reg_operand" "")
11942 (const_int 0)])
11943 (const_int 0)))
11944 (set (match_operand:SI 3 "gpc_reg_operand" "")
11945 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11946 "TARGET_32BIT && reload_completed"
11947 [(set (match_dup 3)
11948 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11949 (set (match_dup 0)
11950 (compare:CC (match_dup 3)
11951 (const_int 0)))]
11952 "")
11954 (define_insn ""
11955 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11956 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11957 [(match_operand 2 "cc_reg_operand" "y")
11958 (const_int 0)])
11959 (match_operand:SI 3 "const_int_operand" "n")))]
11960 ""
11961 "*
11962 {
11963 int is_bit = ccr_bit (operands[1], 1);
11964 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11965 int count;
11967 if (is_bit >= put_bit)
11968 count = is_bit - put_bit;
11969 else
11970 count = 32 - (put_bit - is_bit);
11972 operands[4] = GEN_INT (count);
11973 operands[5] = GEN_INT (put_bit);
11975 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
11976 }"
11977 [(set (attr "type")
11978 (cond [(match_test "TARGET_MFCRF")
11979 (const_string "mfcrf")
11980 ]
11981 (const_string "mfcr")))
11982 (set_attr "length" "8")])
11984 (define_insn ""
11985 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11986 (compare:CC
11987 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11988 [(match_operand 2 "cc_reg_operand" "y,y")
11989 (const_int 0)])
11990 (match_operand:SI 3 "const_int_operand" "n,n"))
11991 (const_int 0)))
11992 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11993 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11994 (match_dup 3)))]
11995 ""
11996 "*
11997 {
11998 int is_bit = ccr_bit (operands[1], 1);
11999 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12000 int count;
12002 /* Force split for non-cc0 compare. */
12003 if (which_alternative == 1)
12004 return \"#\";
12006 if (is_bit >= put_bit)
12007 count = is_bit - put_bit;
12008 else
12009 count = 32 - (put_bit - is_bit);
12011 operands[5] = GEN_INT (count);
12012 operands[6] = GEN_INT (put_bit);
12014 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
12015 }"
12016 [(set_attr "type" "shift")
12017 (set_attr "dot" "yes")
12018 (set_attr "length" "8,16")])
12020 (define_split
12021 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12022 (compare:CC
12023 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12024 [(match_operand 2 "cc_reg_operand" "")
12025 (const_int 0)])
12026 (match_operand:SI 3 "const_int_operand" ""))
12027 (const_int 0)))
12028 (set (match_operand:SI 4 "gpc_reg_operand" "")
12029 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12030 (match_dup 3)))]
12031 "reload_completed"
12032 [(set (match_dup 4)
12033 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12034 (match_dup 3)))
12035 (set (match_dup 0)
12036 (compare:CC (match_dup 4)
12037 (const_int 0)))]
12038 "")
12040 ;; There is a 3 cycle delay between consecutive mfcr instructions
12041 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12043 (define_peephole
12044 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12045 (match_operator:SI 1 "scc_comparison_operator"
12046 [(match_operand 2 "cc_reg_operand" "y")
12047 (const_int 0)]))
12048 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12049 (match_operator:SI 4 "scc_comparison_operator"
12050 [(match_operand 5 "cc_reg_operand" "y")
12051 (const_int 0)]))]
12052 "REGNO (operands[2]) != REGNO (operands[5])"
12053 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12054 [(set_attr "type" "mfcr")
12055 (set_attr "length" "12")])
12057 (define_peephole
12058 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12059 (match_operator:DI 1 "scc_comparison_operator"
12060 [(match_operand 2 "cc_reg_operand" "y")
12061 (const_int 0)]))
12062 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12063 (match_operator:DI 4 "scc_comparison_operator"
12064 [(match_operand 5 "cc_reg_operand" "y")
12065 (const_int 0)]))]
12066 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12067 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12068 [(set_attr "type" "mfcr")
12069 (set_attr "length" "12")])
12071 ;; There are some scc insns that can be done directly, without a compare.
12072 ;; These are faster because they don't involve the communications between
12073 ;; the FXU and branch units. In fact, we will be replacing all of the
12074 ;; integer scc insns here or in the portable methods in emit_store_flag.
12075 ;;
12076 ;; Also support (neg (scc ..)) since that construct is used to replace
12077 ;; branches, (plus (scc ..) ..) since that construct is common and
12078 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12079 ;; cases where it is no more expensive than (neg (scc ..)).
12081 ;; Have reload force a constant into a register for the simple insns that
12082 ;; otherwise won't accept constants. We do this because it is faster than
12083 ;; the cmp/mfcr sequence we would otherwise generate.
12085 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12086 (DI "rKJI")])
12088 (define_insn_and_split "*eq<mode>"
12089 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12090 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12091 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12092 ""
12093 "#"
12094 ""
12095 [(set (match_dup 0)
12096 (clz:GPR (match_dup 3)))
12097 (set (match_dup 0)
12098 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12099 {
12100 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12101 {
12102 /* Use output operand as intermediate. */
12103 operands[3] = operands[0];
12105 if (logical_operand (operands[2], <MODE>mode))
12106 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12107 gen_rtx_XOR (<MODE>mode,
12108 operands[1], operands[2])));
12109 else
12110 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12111 gen_rtx_PLUS (<MODE>mode, operands[1],
12112 negate_rtx (<MODE>mode,
12113 operands[2]))));
12114 }
12115 else
12116 operands[3] = operands[1];
12118 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12119 })
12121 (define_insn_and_split "*eq<mode>_compare"
12122 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12123 (compare:CC
12124 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12125 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12126 (const_int 0)))
12127 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12128 (eq:P (match_dup 1) (match_dup 2)))]
12129 "optimize_size"
12130 "#"
12131 "optimize_size"
12132 [(set (match_dup 0)
12133 (clz:P (match_dup 4)))
12134 (parallel [(set (match_dup 3)
12135 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12136 (const_int 0)))
12137 (set (match_dup 0)
12138 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12139 {
12140 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12141 {
12142 /* Use output operand as intermediate. */
12143 operands[4] = operands[0];
12145 if (logical_operand (operands[2], <MODE>mode))
12146 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12147 gen_rtx_XOR (<MODE>mode,
12148 operands[1], operands[2])));
12149 else
12150 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12151 gen_rtx_PLUS (<MODE>mode, operands[1],
12152 negate_rtx (<MODE>mode,
12153 operands[2]))));
12154 }
12155 else
12156 operands[4] = operands[1];
12158 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12159 })
12161 ;; We have insns of the form shown by the first define_insn below. If
12162 ;; there is something inside the comparison operation, we must split it.
12163 (define_split
12164 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12165 (plus:SI (match_operator 1 "comparison_operator"
12166 [(match_operand:SI 2 "" "")
12167 (match_operand:SI 3
12168 "reg_or_cint_operand" "")])
12169 (match_operand:SI 4 "gpc_reg_operand" "")))
12170 (clobber (match_operand:SI 5 "register_operand" ""))]
12171 "! gpc_reg_operand (operands[2], SImode)"
12172 [(set (match_dup 5) (match_dup 2))
12173 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
12174 (match_dup 4)))])
12176 (define_insn "*plus_eqsi"
12177 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12178 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12179 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12180 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12181 "TARGET_32BIT"
12182 "@
12183 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
12184 subfic %0,%1,0\;addze %0,%3
12185 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
12186 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
12187 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
12188 [(set_attr "type" "three,two,three,three,three")
12189 (set_attr "length" "12,8,12,12,12")])
12191 (define_insn "*compare_plus_eqsi"
12192 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12193 (compare:CC
12194 (plus:SI
12195 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12196 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12197 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12198 (const_int 0)))
12199 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12200 "TARGET_32BIT && optimize_size"
12201 "@
12202 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12203 subfic %4,%1,0\;addze. %4,%3
12204 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
12205 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
12206 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12207 #
12208 #
12209 #
12210 #
12211 #"
12212 [(set_attr "type" "compare")
12213 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12215 (define_split
12216 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12217 (compare:CC
12218 (plus:SI
12219 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12220 (match_operand:SI 2 "scc_eq_operand" ""))
12221 (match_operand:SI 3 "gpc_reg_operand" ""))
12222 (const_int 0)))
12223 (clobber (match_scratch:SI 4 ""))]
12224 "TARGET_32BIT && optimize_size && reload_completed"
12225 [(set (match_dup 4)
12226 (plus:SI (eq:SI (match_dup 1)
12227 (match_dup 2))
12228 (match_dup 3)))
12229 (set (match_dup 0)
12230 (compare:CC (match_dup 4)
12231 (const_int 0)))]
12232 "")
12234 (define_insn "*plus_eqsi_compare"
12235 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12236 (compare:CC
12237 (plus:SI
12238 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12239 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12240 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12241 (const_int 0)))
12242 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12243 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12244 "TARGET_32BIT && optimize_size"
12245 "@
12246 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12247 subfic %0,%1,0\;addze. %0,%3
12248 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
12249 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
12250 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12251 #
12252 #
12253 #
12254 #
12255 #"
12256 [(set_attr "type" "compare")
12257 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12259 (define_split
12260 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12261 (compare:CC
12262 (plus:SI
12263 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12264 (match_operand:SI 2 "scc_eq_operand" ""))
12265 (match_operand:SI 3 "gpc_reg_operand" ""))
12266 (const_int 0)))
12267 (set (match_operand:SI 0 "gpc_reg_operand" "")
12268 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12269 "TARGET_32BIT && optimize_size && reload_completed"
12270 [(set (match_dup 0)
12271 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12272 (set (match_dup 4)
12273 (compare:CC (match_dup 0)
12274 (const_int 0)))]
12275 "")
12277 (define_insn "*neg_eq0<mode>"
12278 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12279 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12280 (const_int 0))))]
12281 ""
12282 "addic %0,%1,-1\;subfe %0,%0,%0"
12283 [(set_attr "type" "two")
12284 (set_attr "length" "8")])
12286 (define_insn_and_split "*neg_eq<mode>"
12287 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12288 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12289 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12290 ""
12291 "#"
12292 ""
12293 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12294 {
12295 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12296 {
12297 /* Use output operand as intermediate. */
12298 operands[3] = operands[0];
12300 if (logical_operand (operands[2], <MODE>mode))
12301 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12302 gen_rtx_XOR (<MODE>mode,
12303 operands[1], operands[2])));
12304 else
12305 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12306 gen_rtx_PLUS (<MODE>mode, operands[1],
12307 negate_rtx (<MODE>mode,
12308 operands[2]))));
12309 }
12310 else
12311 operands[3] = operands[1];
12312 })
12314 (define_insn "*ne0_<mode>"
12315 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12316 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12317 (const_int 0)))
12318 (clobber (match_scratch:P 2 "=&r"))]
12319 "!(TARGET_32BIT && TARGET_ISEL)"
12320 "addic %2,%1,-1\;subfe %0,%2,%1"
12321 [(set_attr "type" "two")
12322 (set_attr "length" "8")])
12324 (define_insn "*plus_ne0_<mode>"
12325 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12326 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12327 (const_int 0))
12328 (match_operand:P 2 "gpc_reg_operand" "r")))
12329 (clobber (match_scratch:P 3 "=&r"))]
12330 ""
12331 "addic %3,%1,-1\;addze %0,%2"
12332 [(set_attr "type" "two")
12333 (set_attr "length" "8")])
12335 (define_insn "*compare_plus_ne0_<mode>"
12336 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12337 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12338 (const_int 0))
12339 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12340 (const_int 0)))
12341 (clobber (match_scratch:P 3 "=&r,&r"))
12342 (clobber (match_scratch:P 4 "=X,&r"))]
12343 ""
12344 "@
12345 addic %3,%1,-1\;addze. %3,%2
12346 #"
12347 [(set_attr "type" "compare")
12348 (set_attr "length" "8,12")])
12350 (define_split
12351 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12352 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12353 (const_int 0))
12354 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12355 (clobber (match_scratch:P 3 ""))
12356 (clobber (match_scratch:P 4 ""))]
12357 "reload_completed"
12358 [(parallel [(set (match_dup 3)
12359 (plus:P (ne:P (match_dup 1)
12360 (const_int 0))
12361 (match_dup 2)))
12362 (clobber (match_dup 4))])
12363 (set (match_dup 0)
12364 (compare:CC (match_dup 3)
12365 (const_int 0)))]
12366 "")
12368 ; For combine.
12369 (define_insn "*compare_plus_ne0_<mode>_1"
12370 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12371 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12372 (const_int 0))
12373 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
12374 (clobber (match_scratch:P 3 "=&r,&r"))
12375 (clobber (match_scratch:P 4 "=X,&r"))]
12376 ""
12377 "@
12378 addic %3,%1,-1\;addze. %3,%2
12379 #"
12380 [(set_attr "type" "compare")
12381 (set_attr "length" "8,12")])
12383 (define_split
12384 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
12385 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12386 (const_int 0))
12387 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12388 (clobber (match_scratch:P 3 ""))
12389 (clobber (match_scratch:P 4 ""))]
12390 "reload_completed"
12391 [(parallel [(set (match_dup 3)
12392 (plus:P (ne:P (match_dup 1)
12393 (const_int 0))
12394 (match_dup 2)))
12395 (clobber (match_dup 4))])
12396 (set (match_dup 0)
12397 (compare:CC (match_dup 3)
12398 (const_int 0)))]
12399 "")
12401 (define_insn "*plus_ne0_<mode>_compare"
12402 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12403 (compare:CC
12404 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12405 (const_int 0))
12406 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12407 (const_int 0)))
12408 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12409 (plus:P (ne:P (match_dup 1)
12410 (const_int 0))
12411 (match_dup 2)))
12412 (clobber (match_scratch:P 3 "=&r,&r"))]
12413 ""
12414 "@
12415 addic %3,%1,-1\;addze. %0,%2
12416 #"
12417 [(set_attr "type" "compare")
12418 (set_attr "length" "8,12")])
12420 (define_split
12421 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12422 (compare:CC
12423 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
12424 (const_int 0))
12425 (match_operand:P 2 "gpc_reg_operand" ""))
12426 (const_int 0)))
12427 (set (match_operand:P 0 "gpc_reg_operand" "")
12428 (plus:P (ne:P (match_dup 1)
12429 (const_int 0))
12430 (match_dup 2)))
12431 (clobber (match_scratch:P 3 ""))]
12432 "reload_completed"
12433 [(parallel [(set (match_dup 0)
12434 (plus:P (ne:P (match_dup 1)
12435 (const_int 0))
12436 (match_dup 2)))
12437 (clobber (match_dup 3))])
12438 (set (match_dup 4)
12439 (compare:CC (match_dup 0)
12440 (const_int 0)))]
12441 "")
12443 (define_insn "*leu<mode>"
12444 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12445 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12446 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12447 ""
12448 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12449 [(set_attr "type" "three")
12450 (set_attr "length" "12")])
12452 (define_insn "*leu<mode>_compare"
12453 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12454 (compare:CC
12455 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12456 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12457 (const_int 0)))
12458 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12459 (leu:P (match_dup 1) (match_dup 2)))]
12460 ""
12461 "@
12462 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12463 #"
12464 [(set_attr "type" "compare")
12465 (set_attr "length" "12,16")])
12467 (define_split
12468 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12469 (compare:CC
12470 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12471 (match_operand:P 2 "reg_or_short_operand" ""))
12472 (const_int 0)))
12473 (set (match_operand:P 0 "gpc_reg_operand" "")
12474 (leu:P (match_dup 1) (match_dup 2)))]
12475 "reload_completed"
12476 [(set (match_dup 0)
12477 (leu:P (match_dup 1) (match_dup 2)))
12478 (set (match_dup 3)
12479 (compare:CC (match_dup 0)
12480 (const_int 0)))]
12481 "")
12483 (define_insn "*plus_leu<mode>"
12484 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12485 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12486 (match_operand:P 2 "reg_or_short_operand" "rI"))
12487 (match_operand:P 3 "gpc_reg_operand" "r")))]
12488 ""
12489 "subf%I2c %0,%1,%2\;addze %0,%3"
12490 [(set_attr "type" "two")
12491 (set_attr "length" "8")])
12493 (define_insn ""
12494 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12495 (compare:CC
12496 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12497 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12498 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12499 (const_int 0)))
12500 (clobber (match_scratch:SI 4 "=&r,&r"))]
12501 "TARGET_32BIT"
12502 "@
12503 subf%I2c %4,%1,%2\;addze. %4,%3
12504 #"
12505 [(set_attr "type" "compare")
12506 (set_attr "length" "8,12")])
12508 (define_split
12509 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12510 (compare:CC
12511 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12512 (match_operand:SI 2 "reg_or_short_operand" ""))
12513 (match_operand:SI 3 "gpc_reg_operand" ""))
12514 (const_int 0)))
12515 (clobber (match_scratch:SI 4 ""))]
12516 "TARGET_32BIT && reload_completed"
12517 [(set (match_dup 4)
12518 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12519 (match_dup 3)))
12520 (set (match_dup 0)
12521 (compare:CC (match_dup 4)
12522 (const_int 0)))]
12523 "")
12525 (define_insn ""
12526 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12527 (compare:CC
12528 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12529 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12530 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12531 (const_int 0)))
12532 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12533 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12534 "TARGET_32BIT"
12535 "@
12536 subf%I2c %0,%1,%2\;addze. %0,%3
12537 #"
12538 [(set_attr "type" "compare")
12539 (set_attr "length" "8,12")])
12541 (define_split
12542 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12543 (compare:CC
12544 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12545 (match_operand:SI 2 "reg_or_short_operand" ""))
12546 (match_operand:SI 3 "gpc_reg_operand" ""))
12547 (const_int 0)))
12548 (set (match_operand:SI 0 "gpc_reg_operand" "")
12549 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12550 "TARGET_32BIT && reload_completed"
12551 [(set (match_dup 0)
12552 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12553 (set (match_dup 4)
12554 (compare:CC (match_dup 0)
12555 (const_int 0)))]
12556 "")
12558 (define_insn "*neg_leu<mode>"
12559 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12560 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12561 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12562 ""
12563 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
12564 [(set_attr "type" "three")
12565 (set_attr "length" "12")])
12567 (define_insn "*and_neg_leu<mode>"
12568 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12569 (and:P (neg:P
12570 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12571 (match_operand:P 2 "reg_or_short_operand" "rI")))
12572 (match_operand:P 3 "gpc_reg_operand" "r")))]
12573 ""
12574 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
12575 [(set_attr "type" "three")
12576 (set_attr "length" "12")])
12578 (define_insn ""
12579 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12580 (compare:CC
12581 (and:SI (neg:SI
12582 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12583 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12584 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12585 (const_int 0)))
12586 (clobber (match_scratch:SI 4 "=&r,&r"))]
12587 "TARGET_32BIT"
12588 "@
12589 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
12590 #"
12591 [(set_attr "type" "compare")
12592 (set_attr "length" "12,16")])
12594 (define_split
12595 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12596 (compare:CC
12597 (and:SI (neg:SI
12598 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12599 (match_operand:SI 2 "reg_or_short_operand" "")))
12600 (match_operand:SI 3 "gpc_reg_operand" ""))
12601 (const_int 0)))
12602 (clobber (match_scratch:SI 4 ""))]
12603 "TARGET_32BIT && reload_completed"
12604 [(set (match_dup 4)
12605 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12606 (match_dup 3)))
12607 (set (match_dup 0)
12608 (compare:CC (match_dup 4)
12609 (const_int 0)))]
12610 "")
12612 (define_insn ""
12613 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12614 (compare:CC
12615 (and:SI (neg:SI
12616 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12617 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12618 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12619 (const_int 0)))
12620 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12621 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12622 "TARGET_32BIT"
12623 "@
12624 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
12625 #"
12626 [(set_attr "type" "compare")
12627 (set_attr "length" "12,16")])
12629 (define_split
12630 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12631 (compare:CC
12632 (and:SI (neg:SI
12633 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12634 (match_operand:SI 2 "reg_or_short_operand" "")))
12635 (match_operand:SI 3 "gpc_reg_operand" ""))
12636 (const_int 0)))
12637 (set (match_operand:SI 0 "gpc_reg_operand" "")
12638 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12639 "TARGET_32BIT && reload_completed"
12640 [(set (match_dup 0)
12641 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12642 (match_dup 3)))
12643 (set (match_dup 4)
12644 (compare:CC (match_dup 0)
12645 (const_int 0)))]
12646 "")
12648 (define_insn_and_split "*ltu<mode>"
12649 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12650 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12651 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12652 ""
12653 "#"
12654 ""
12655 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12656 (set (match_dup 0) (neg:P (match_dup 0)))]
12657 "")
12659 (define_insn_and_split "*ltu<mode>_compare"
12660 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12661 (compare:CC
12662 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12663 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12664 (const_int 0)))
12665 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12666 (ltu:P (match_dup 1) (match_dup 2)))]
12667 ""
12668 "#"
12669 ""
12670 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12671 (parallel [(set (match_dup 3)
12672 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12673 (set (match_dup 0) (neg:P (match_dup 0)))])]
12674 "")
12676 (define_insn_and_split "*plus_ltu<mode>"
12677 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12678 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12679 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12680 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12681 ""
12682 "#"
12683 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12684 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12685 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12686 "")
12688 (define_insn_and_split "*plus_ltu<mode>_1"
12689 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12690 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12691 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12692 (match_operand:P 3 "short_cint_operand" "I,I")))]
12693 ""
12694 "#"
12695 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12696 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12697 (parallel [(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))
12698 (clobber (reg:P CA_REGNO))])]
12699 "")
12701 (define_insn_and_split "*plus_ltu<mode>_compare"
12702 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12703 (compare:CC
12704 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12705 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12706 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12707 (const_int 0)))
12708 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12709 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12710 ""
12711 "#"
12712 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12713 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12714 (parallel [(set (match_dup 4)
12715 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12716 (const_int 0)))
12717 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12718 "")
12720 (define_insn "*neg_ltu<mode>"
12721 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12722 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12723 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12724 ""
12725 "@
12726 subfc %0,%2,%1\;subfe %0,%0,%0
12727 addic %0,%1,%n2\;subfe %0,%0,%0"
12728 [(set_attr "type" "two")
12729 (set_attr "length" "8")])
12731 (define_insn "*geu<mode>"
12732 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12733 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12734 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12735 ""
12736 "@
12737 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12738 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12739 [(set_attr "type" "three")
12740 (set_attr "length" "12")])
12742 (define_insn "*geu<mode>_compare"
12743 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12744 (compare:CC
12745 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12746 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12747 (const_int 0)))
12748 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12749 (geu:P (match_dup 1) (match_dup 2)))]
12750 ""
12751 "@
12752 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12753 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12754 #
12755 #"
12756 [(set_attr "type" "compare")
12757 (set_attr "length" "12,12,16,16")])
12759 (define_split
12760 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12761 (compare:CC
12762 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12763 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12764 (const_int 0)))
12765 (set (match_operand:P 0 "gpc_reg_operand" "")
12766 (geu:P (match_dup 1) (match_dup 2)))]
12767 "reload_completed"
12768 [(set (match_dup 0)
12769 (geu:P (match_dup 1) (match_dup 2)))
12770 (set (match_dup 3)
12771 (compare:CC (match_dup 0)
12772 (const_int 0)))]
12773 "")
12775 (define_insn "*plus_geu<mode>"
12776 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12777 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12778 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12779 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12780 ""
12781 "@
12782 subfc %0,%2,%1\;addze %0,%3
12783 addic %0,%1,%n2\;addze %0,%3"
12784 [(set_attr "type" "two")
12785 (set_attr "length" "8")])
12787 (define_insn ""
12788 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12789 (compare:CC
12790 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12791 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12792 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12793 (const_int 0)))
12794 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12795 "TARGET_32BIT"
12796 "@
12797 subfc %4,%2,%1\;addze. %4,%3
12798 addic %4,%1,%n2\;addze. %4,%3
12799 #
12800 #"
12801 [(set_attr "type" "compare")
12802 (set_attr "length" "8,8,12,12")])
12804 (define_split
12805 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12806 (compare:CC
12807 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12808 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12809 (match_operand:SI 3 "gpc_reg_operand" ""))
12810 (const_int 0)))
12811 (clobber (match_scratch:SI 4 ""))]
12812 "TARGET_32BIT && reload_completed"
12813 [(set (match_dup 4)
12814 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12815 (match_dup 3)))
12816 (set (match_dup 0)
12817 (compare:CC (match_dup 4)
12818 (const_int 0)))]
12819 "")
12821 (define_insn ""
12822 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12823 (compare:CC
12824 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12825 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12826 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12827 (const_int 0)))
12828 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12829 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12830 "TARGET_32BIT"
12831 "@
12832 subfc %0,%2,%1\;addze. %0,%3
12833 addic %0,%1,%n2\;addze. %0,%3
12834 #
12835 #"
12836 [(set_attr "type" "compare")
12837 (set_attr "length" "8,8,12,12")])
12839 (define_split
12840 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12841 (compare:CC
12842 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12843 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12844 (match_operand:SI 3 "gpc_reg_operand" ""))
12845 (const_int 0)))
12846 (set (match_operand:SI 0 "gpc_reg_operand" "")
12847 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12848 "TARGET_32BIT && reload_completed"
12849 [(set (match_dup 0)
12850 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12851 (set (match_dup 4)
12852 (compare:CC (match_dup 0)
12853 (const_int 0)))]
12854 "")
12856 (define_insn "*neg_geu<mode>"
12857 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12858 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12859 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12860 ""
12861 "@
12862 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
12863 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
12864 [(set_attr "type" "three")
12865 (set_attr "length" "12")])
12867 (define_insn "*and_neg_geu<mode>"
12868 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12869 (and:P (neg:P
12870 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12871 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12872 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12873 ""
12874 "@
12875 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
12876 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
12877 [(set_attr "type" "three")
12878 (set_attr "length" "12")])
12880 (define_insn ""
12881 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12882 (compare:CC
12883 (and:SI (neg:SI
12884 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12885 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12886 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12887 (const_int 0)))
12888 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12889 "TARGET_32BIT"
12890 "@
12891 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
12892 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
12893 #
12894 #"
12895 [(set_attr "type" "compare")
12896 (set_attr "length" "12,12,16,16")])
12898 (define_split
12899 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12900 (compare:CC
12901 (and:SI (neg:SI
12902 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12903 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12904 (match_operand:SI 3 "gpc_reg_operand" ""))
12905 (const_int 0)))
12906 (clobber (match_scratch:SI 4 ""))]
12907 "TARGET_32BIT && reload_completed"
12908 [(set (match_dup 4)
12909 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12910 (match_dup 3)))
12911 (set (match_dup 0)
12912 (compare:CC (match_dup 4)
12913 (const_int 0)))]
12914 "")
12916 (define_insn ""
12917 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12918 (compare:CC
12919 (and:SI (neg:SI
12920 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12921 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12922 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12923 (const_int 0)))
12924 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12925 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12926 "TARGET_32BIT"
12927 "@
12928 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
12929 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
12930 #
12931 #"
12932 [(set_attr "type" "compare")
12933 (set_attr "length" "12,12,16,16")])
12935 (define_split
12936 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12937 (compare:CC
12938 (and:SI (neg:SI
12939 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12940 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12941 (match_operand:SI 3 "gpc_reg_operand" ""))
12942 (const_int 0)))
12943 (set (match_operand:SI 0 "gpc_reg_operand" "")
12944 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12945 "TARGET_32BIT && reload_completed"
12946 [(set (match_dup 0)
12947 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12948 (set (match_dup 4)
12949 (compare:CC (match_dup 0)
12950 (const_int 0)))]
12951 "")
12953 (define_insn "*plus_gt0<mode>"
12954 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12955 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12956 (const_int 0))
12957 (match_operand:P 2 "gpc_reg_operand" "r")))]
12958 ""
12959 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12960 [(set_attr "type" "three")
12961 (set_attr "length" "12")])
12963 (define_insn ""
12964 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12965 (compare:CC
12966 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12967 (const_int 0))
12968 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12969 (const_int 0)))
12970 (clobber (match_scratch:SI 3 "=&r,&r"))]
12971 "TARGET_32BIT"
12972 "@
12973 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12974 #"
12975 [(set_attr "type" "compare")
12976 (set_attr "length" "12,16")])
12978 (define_split
12979 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12980 (compare:CC
12981 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12982 (const_int 0))
12983 (match_operand:SI 2 "gpc_reg_operand" ""))
12984 (const_int 0)))
12985 (clobber (match_scratch:SI 3 ""))]
12986 "TARGET_32BIT && reload_completed"
12987 [(set (match_dup 3)
12988 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12989 (match_dup 2)))
12990 (set (match_dup 0)
12991 (compare:CC (match_dup 3)
12992 (const_int 0)))]
12993 "")
12995 (define_insn ""
12996 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12997 (compare:CC
12998 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12999 (const_int 0))
13000 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13001 (const_int 0)))
13002 (clobber (match_scratch:DI 3 "=&r,&r"))]
13003 "TARGET_64BIT"
13004 "@
13005 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13006 #"
13007 [(set_attr "type" "compare")
13008 (set_attr "length" "12,16")])
13010 (define_split
13011 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13012 (compare:CC
13013 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13014 (const_int 0))
13015 (match_operand:DI 2 "gpc_reg_operand" ""))
13016 (const_int 0)))
13017 (clobber (match_scratch:DI 3 ""))]
13018 "TARGET_64BIT && reload_completed"
13019 [(set (match_dup 3)
13020 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13021 (match_dup 2)))
13022 (set (match_dup 0)
13023 (compare:CC (match_dup 3)
13024 (const_int 0)))]
13025 "")
13027 (define_insn ""
13028 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13029 (compare:CC
13030 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13031 (const_int 0))
13032 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13033 (const_int 0)))
13034 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13035 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13036 "TARGET_32BIT"
13037 "@
13038 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13039 #"
13040 [(set_attr "type" "compare")
13041 (set_attr "length" "12,16")])
13043 (define_split
13044 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13045 (compare:CC
13046 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13047 (const_int 0))
13048 (match_operand:SI 2 "gpc_reg_operand" ""))
13049 (const_int 0)))
13050 (set (match_operand:SI 0 "gpc_reg_operand" "")
13051 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13052 "TARGET_32BIT && reload_completed"
13053 [(set (match_dup 0)
13054 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13055 (set (match_dup 3)
13056 (compare:CC (match_dup 0)
13057 (const_int 0)))]
13058 "")
13060 (define_insn ""
13061 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13062 (compare:CC
13063 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13064 (const_int 0))
13065 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13066 (const_int 0)))
13067 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13068 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13069 "TARGET_64BIT"
13070 "@
13071 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13072 #"
13073 [(set_attr "type" "compare")
13074 (set_attr "length" "12,16")])
13076 (define_split
13077 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13078 (compare:CC
13079 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13080 (const_int 0))
13081 (match_operand:DI 2 "gpc_reg_operand" ""))
13082 (const_int 0)))
13083 (set (match_operand:DI 0 "gpc_reg_operand" "")
13084 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13085 "TARGET_64BIT && reload_completed"
13086 [(set (match_dup 0)
13087 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13088 (set (match_dup 3)
13089 (compare:CC (match_dup 0)
13090 (const_int 0)))]
13091 "")
13093 (define_insn_and_split "*gtu<mode>"
13094 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13095 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13096 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13097 ""
13098 "#"
13099 ""
13100 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13101 (set (match_dup 0) (neg:P (match_dup 0)))]
13102 "")
13104 (define_insn_and_split "*gtu<mode>_compare"
13105 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13106 (compare:CC
13107 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13108 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13109 (const_int 0)))
13110 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13111 (gtu:P (match_dup 1) (match_dup 2)))]
13112 ""
13113 "#"
13114 ""
13115 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13116 (parallel [(set (match_dup 3)
13117 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13118 (set (match_dup 0) (neg:P (match_dup 0)))])]
13119 "")
13121 (define_insn_and_split "*plus_gtu<mode>"
13122 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13123 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13124 (match_operand:P 2 "reg_or_short_operand" "rI"))
13125 (match_operand:P 3 "gpc_reg_operand" "r")))]
13126 ""
13127 "#"
13128 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13129 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13130 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13131 "")
13133 (define_insn_and_split "*plus_gtu<mode>_1"
13134 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13135 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13136 (match_operand:P 2 "reg_or_short_operand" "rI"))
13137 (match_operand:P 3 "short_cint_operand" "I")))]
13138 ""
13139 "#"
13140 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13141 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13142 (parallel [(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))
13143 (clobber (reg:P CA_REGNO))])]
13144 "")
13146 (define_insn_and_split "*plus_gtu<mode>_compare"
13147 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13148 (compare:CC
13149 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13150 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13151 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13152 (const_int 0)))
13153 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13154 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13155 ""
13156 "#"
13157 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13158 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13159 (parallel [(set (match_dup 4)
13160 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13161 (const_int 0)))
13162 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13163 "")
13165 (define_insn "*neg_gtu<mode>"
13166 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13167 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13168 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13169 ""
13170 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13171 [(set_attr "type" "two")
13172 (set_attr "length" "8")])
13174 \f
13175 ;; Define both directions of branch and return. If we need a reload
13176 ;; register, we'd rather use CR0 since it is much easier to copy a
13177 ;; register CC value to there.
13179 (define_insn ""
13180 [(set (pc)
13181 (if_then_else (match_operator 1 "branch_comparison_operator"
13182 [(match_operand 2
13183 "cc_reg_operand" "y")
13184 (const_int 0)])
13185 (label_ref (match_operand 0 "" ""))
13186 (pc)))]
13187 ""
13188 "*
13189 {
13190 return output_cbranch (operands[1], \"%l0\", 0, insn);
13191 }"
13192 [(set_attr "type" "branch")])
13194 (define_insn ""
13195 [(set (pc)
13196 (if_then_else (match_operator 0 "branch_comparison_operator"
13197 [(match_operand 1
13198 "cc_reg_operand" "y")
13199 (const_int 0)])
13200 (any_return)
13201 (pc)))]
13202 "<return_pred>"
13203 "*
13204 {
13205 return output_cbranch (operands[0], NULL, 0, insn);
13206 }"
13207 [(set_attr "type" "jmpreg")
13208 (set_attr "length" "4")])
13210 (define_insn ""
13211 [(set (pc)
13212 (if_then_else (match_operator 1 "branch_comparison_operator"
13213 [(match_operand 2
13214 "cc_reg_operand" "y")
13215 (const_int 0)])
13216 (pc)
13217 (label_ref (match_operand 0 "" ""))))]
13218 ""
13219 "*
13220 {
13221 return output_cbranch (operands[1], \"%l0\", 1, insn);
13222 }"
13223 [(set_attr "type" "branch")])
13225 (define_insn ""
13226 [(set (pc)
13227 (if_then_else (match_operator 0 "branch_comparison_operator"
13228 [(match_operand 1
13229 "cc_reg_operand" "y")
13230 (const_int 0)])
13231 (pc)
13232 (any_return)))]
13233 "<return_pred>"
13234 "*
13235 {
13236 return output_cbranch (operands[0], NULL, 1, insn);
13237 }"
13238 [(set_attr "type" "jmpreg")
13239 (set_attr "length" "4")])
13241 ;; Logic on condition register values.
13243 ; This pattern matches things like
13244 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13245 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13246 ; (const_int 1)))
13247 ; which are generated by the branch logic.
13248 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13250 (define_insn "*cceq_ior_compare"
13251 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13252 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13253 [(match_operator:SI 2
13254 "branch_positive_comparison_operator"
13255 [(match_operand 3
13256 "cc_reg_operand" "y,y")
13257 (const_int 0)])
13258 (match_operator:SI 4
13259 "branch_positive_comparison_operator"
13260 [(match_operand 5
13261 "cc_reg_operand" "0,y")
13262 (const_int 0)])])
13263 (const_int 1)))]
13264 ""
13265 "cr%q1 %E0,%j2,%j4"
13266 [(set_attr "type" "cr_logical,delayed_cr")])
13268 ; Why is the constant -1 here, but 1 in the previous pattern?
13269 ; Because ~1 has all but the low bit set.
13270 (define_insn ""
13271 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13272 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13273 [(not:SI (match_operator:SI 2
13274 "branch_positive_comparison_operator"
13275 [(match_operand 3
13276 "cc_reg_operand" "y,y")
13277 (const_int 0)]))
13278 (match_operator:SI 4
13279 "branch_positive_comparison_operator"
13280 [(match_operand 5
13281 "cc_reg_operand" "0,y")
13282 (const_int 0)])])
13283 (const_int -1)))]
13284 ""
13285 "cr%q1 %E0,%j2,%j4"
13286 [(set_attr "type" "cr_logical,delayed_cr")])
13288 (define_insn "*cceq_rev_compare"
13289 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13290 (compare:CCEQ (match_operator:SI 1
13291 "branch_positive_comparison_operator"
13292 [(match_operand 2
13293 "cc_reg_operand" "0,y")
13294 (const_int 0)])
13295 (const_int 0)))]
13296 ""
13297 "crnot %E0,%j1"
13298 [(set_attr "type" "cr_logical,delayed_cr")])
13300 ;; If we are comparing the result of two comparisons, this can be done
13301 ;; using creqv or crxor.
13303 (define_insn_and_split ""
13304 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13305 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13306 [(match_operand 2 "cc_reg_operand" "y")
13307 (const_int 0)])
13308 (match_operator 3 "branch_comparison_operator"
13309 [(match_operand 4 "cc_reg_operand" "y")
13310 (const_int 0)])))]
13311 ""
13312 "#"
13313 ""
13314 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13315 (match_dup 5)))]
13316 "
13317 {
13318 int positive_1, positive_2;
13320 positive_1 = branch_positive_comparison_operator (operands[1],
13321 GET_MODE (operands[1]));
13322 positive_2 = branch_positive_comparison_operator (operands[3],
13323 GET_MODE (operands[3]));
13325 if (! positive_1)
13326 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13327 GET_CODE (operands[1])),
13328 SImode,
13329 operands[2], const0_rtx);
13330 else if (GET_MODE (operands[1]) != SImode)
13331 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13332 operands[2], const0_rtx);
13334 if (! positive_2)
13335 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13336 GET_CODE (operands[3])),
13337 SImode,
13338 operands[4], const0_rtx);
13339 else if (GET_MODE (operands[3]) != SImode)
13340 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13341 operands[4], const0_rtx);
13343 if (positive_1 == positive_2)
13344 {
13345 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13346 operands[5] = constm1_rtx;
13347 }
13348 else
13349 {
13350 operands[5] = const1_rtx;
13351 }
13352 }")
13354 ;; Unconditional branch and return.
13356 (define_insn "jump"
13357 [(set (pc)
13358 (label_ref (match_operand 0 "" "")))]
13359 ""
13360 "b %l0"
13361 [(set_attr "type" "branch")])
13363 (define_insn "<return_str>return"
13364 [(any_return)]
13365 "<return_pred>"
13366 "blr"
13367 [(set_attr "type" "jmpreg")])
13369 (define_expand "indirect_jump"
13370 [(set (pc) (match_operand 0 "register_operand" ""))])
13372 (define_insn "*indirect_jump<mode>"
13373 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13374 ""
13375 "@
13376 bctr
13377 blr"
13378 [(set_attr "type" "jmpreg")])
13380 ;; Table jump for switch statements:
13381 (define_expand "tablejump"
13382 [(use (match_operand 0 "" ""))
13383 (use (label_ref (match_operand 1 "" "")))]
13384 ""
13385 "
13386 {
13387 if (TARGET_32BIT)
13388 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13389 else
13390 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13391 DONE;
13392 }")
13394 (define_expand "tablejumpsi"
13395 [(set (match_dup 3)
13396 (plus:SI (match_operand:SI 0 "" "")
13397 (match_dup 2)))
13398 (parallel [(set (pc) (match_dup 3))
13399 (use (label_ref (match_operand 1 "" "")))])]
13400 "TARGET_32BIT"
13401 "
13402 { operands[0] = force_reg (SImode, operands[0]);
13403 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13404 operands[3] = gen_reg_rtx (SImode);
13405 }")
13407 (define_expand "tablejumpdi"
13408 [(set (match_dup 4)
13409 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
13410 (set (match_dup 3)
13411 (plus:DI (match_dup 4)
13412 (match_dup 2)))
13413 (parallel [(set (pc) (match_dup 3))
13414 (use (label_ref (match_operand 1 "" "")))])]
13415 "TARGET_64BIT"
13416 "
13417 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13418 operands[3] = gen_reg_rtx (DImode);
13419 operands[4] = gen_reg_rtx (DImode);
13420 }")
13422 (define_insn "*tablejump<mode>_internal1"
13423 [(set (pc)
13424 (match_operand:P 0 "register_operand" "c,*l"))
13425 (use (label_ref (match_operand 1 "" "")))]
13426 ""
13427 "@
13428 bctr
13429 blr"
13430 [(set_attr "type" "jmpreg")])
13432 (define_insn "nop"
13433 [(const_int 0)]
13434 ""
13435 "nop")
13437 (define_insn "group_ending_nop"
13438 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
13439 ""
13440 "*
13441 {
13442 if (rs6000_cpu_attr == CPU_POWER6)
13443 return \"ori 1,1,0\";
13444 return \"ori 2,2,0\";
13445 }")
13446 \f
13447 ;; Define the subtract-one-and-jump insns, starting with the template
13448 ;; so loop.c knows what to generate.
13450 (define_expand "doloop_end"
13451 [(use (match_operand 0 "" "")) ; loop pseudo
13452 (use (match_operand 1 "" ""))] ; label
13453 ""
13454 "
13455 {
13456 if (TARGET_64BIT)
13457 {
13458 if (GET_MODE (operands[0]) != DImode)
13459 FAIL;
13460 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
13461 }
13462 else
13463 {
13464 if (GET_MODE (operands[0]) != SImode)
13465 FAIL;
13466 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
13467 }
13468 DONE;
13469 }")
13471 (define_expand "ctr<mode>"
13472 [(parallel [(set (pc)
13473 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13474 (const_int 1))
13475 (label_ref (match_operand 1 "" ""))
13476 (pc)))
13477 (set (match_dup 0)
13478 (plus:P (match_dup 0)
13479 (const_int -1)))
13480 (clobber (match_scratch:CC 2 ""))
13481 (clobber (match_scratch:P 3 ""))])]
13482 ""
13483 "")
13485 ;; We need to be able to do this for any operand, including MEM, or we
13486 ;; will cause reload to blow up since we don't allow output reloads on
13487 ;; JUMP_INSNs.
13488 ;; For the length attribute to be calculated correctly, the
13489 ;; label MUST be operand 0.
13491 (define_insn "*ctr<mode>_internal1"
13492 [(set (pc)
13493 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13494 (const_int 1))
13495 (label_ref (match_operand 0 "" ""))
13496 (pc)))
13497 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13498 (plus:P (match_dup 1)
13499 (const_int -1)))
13500 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13501 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13502 ""
13503 "*
13504 {
13505 if (which_alternative != 0)
13506 return \"#\";
13507 else if (get_attr_length (insn) == 4)
13508 return \"bdnz %l0\";
13509 else
13510 return \"bdz $+8\;b %l0\";
13511 }"
13512 [(set_attr "type" "branch")
13513 (set_attr "length" "*,12,16,16")])
13515 (define_insn "*ctr<mode>_internal2"
13516 [(set (pc)
13517 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13518 (const_int 1))
13519 (pc)
13520 (label_ref (match_operand 0 "" ""))))
13521 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13522 (plus:P (match_dup 1)
13523 (const_int -1)))
13524 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13525 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13526 ""
13527 "*
13528 {
13529 if (which_alternative != 0)
13530 return \"#\";
13531 else if (get_attr_length (insn) == 4)
13532 return \"bdz %l0\";
13533 else
13534 return \"bdnz $+8\;b %l0\";
13535 }"
13536 [(set_attr "type" "branch")
13537 (set_attr "length" "*,12,16,16")])
13539 ;; Similar but use EQ
13541 (define_insn "*ctr<mode>_internal5"
13542 [(set (pc)
13543 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13544 (const_int 1))
13545 (label_ref (match_operand 0 "" ""))
13546 (pc)))
13547 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13548 (plus:P (match_dup 1)
13549 (const_int -1)))
13550 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13551 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13552 ""
13553 "*
13554 {
13555 if (which_alternative != 0)
13556 return \"#\";
13557 else if (get_attr_length (insn) == 4)
13558 return \"bdz %l0\";
13559 else
13560 return \"bdnz $+8\;b %l0\";
13561 }"
13562 [(set_attr "type" "branch")
13563 (set_attr "length" "*,12,16,16")])
13565 (define_insn "*ctr<mode>_internal6"
13566 [(set (pc)
13567 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13568 (const_int 1))
13569 (pc)
13570 (label_ref (match_operand 0 "" ""))))
13571 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13572 (plus:P (match_dup 1)
13573 (const_int -1)))
13574 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13575 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13576 ""
13577 "*
13578 {
13579 if (which_alternative != 0)
13580 return \"#\";
13581 else if (get_attr_length (insn) == 4)
13582 return \"bdnz %l0\";
13583 else
13584 return \"bdz $+8\;b %l0\";
13585 }"
13586 [(set_attr "type" "branch")
13587 (set_attr "length" "*,12,16,16")])
13589 ;; Now the splitters if we could not allocate the CTR register
13591 (define_split
13592 [(set (pc)
13593 (if_then_else (match_operator 2 "comparison_operator"
13594 [(match_operand:P 1 "gpc_reg_operand" "")
13595 (const_int 1)])
13596 (match_operand 5 "" "")
13597 (match_operand 6 "" "")))
13598 (set (match_operand:P 0 "gpc_reg_operand" "")
13599 (plus:P (match_dup 1) (const_int -1)))
13600 (clobber (match_scratch:CC 3 ""))
13601 (clobber (match_scratch:P 4 ""))]
13602 "reload_completed"
13603 [(parallel [(set (match_dup 3)
13604 (compare:CC (plus:P (match_dup 1)
13605 (const_int -1))
13606 (const_int 0)))
13607 (set (match_dup 0)
13608 (plus:P (match_dup 1)
13609 (const_int -1)))])
13610 (set (pc) (if_then_else (match_dup 7)
13611 (match_dup 5)
13612 (match_dup 6)))]
13613 "
13614 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13615 operands[3], const0_rtx); }")
13617 (define_split
13618 [(set (pc)
13619 (if_then_else (match_operator 2 "comparison_operator"
13620 [(match_operand:P 1 "gpc_reg_operand" "")
13621 (const_int 1)])
13622 (match_operand 5 "" "")
13623 (match_operand 6 "" "")))
13624 (set (match_operand:P 0 "nonimmediate_operand" "")
13625 (plus:P (match_dup 1) (const_int -1)))
13626 (clobber (match_scratch:CC 3 ""))
13627 (clobber (match_scratch:P 4 ""))]
13628 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13629 [(parallel [(set (match_dup 3)
13630 (compare:CC (plus:P (match_dup 1)
13631 (const_int -1))
13632 (const_int 0)))
13633 (set (match_dup 4)
13634 (plus:P (match_dup 1)
13635 (const_int -1)))])
13636 (set (match_dup 0)
13637 (match_dup 4))
13638 (set (pc) (if_then_else (match_dup 7)
13639 (match_dup 5)
13640 (match_dup 6)))]
13641 "
13642 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13643 operands[3], const0_rtx); }")
13644 \f
13645 (define_insn "trap"
13646 [(trap_if (const_int 1) (const_int 0))]
13647 ""
13648 "trap"
13649 [(set_attr "type" "trap")])
13651 (define_expand "ctrap<mode>4"
13652 [(trap_if (match_operator 0 "ordered_comparison_operator"
13653 [(match_operand:GPR 1 "register_operand")
13654 (match_operand:GPR 2 "reg_or_short_operand")])
13655 (match_operand 3 "zero_constant" ""))]
13656 ""
13657 "")
13659 (define_insn ""
13660 [(trap_if (match_operator 0 "ordered_comparison_operator"
13661 [(match_operand:GPR 1 "register_operand" "r")
13662 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13663 (const_int 0))]
13664 ""
13665 "t<wd>%V0%I2 %1,%2"
13666 [(set_attr "type" "trap")])
13667 \f
13668 ;; Insns related to generating the function prologue and epilogue.
13670 (define_expand "prologue"
13671 [(use (const_int 0))]
13672 ""
13673 {
13674 rs6000_emit_prologue ();
13675 if (!TARGET_SCHED_PROLOG)
13676 emit_insn (gen_blockage ());
13677 DONE;
13678 })
13680 (define_insn "*movesi_from_cr_one"
13681 [(match_parallel 0 "mfcr_operation"
13682 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13683 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13684 (match_operand 3 "immediate_operand" "n")]
13685 UNSPEC_MOVESI_FROM_CR))])]
13686 "TARGET_MFCRF"
13687 "*
13688 {
13689 int mask = 0;
13690 int i;
13691 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13692 {
13693 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13694 operands[4] = GEN_INT (mask);
13695 output_asm_insn (\"mfcr %1,%4\", operands);
13696 }
13697 return \"\";
13698 }"
13699 [(set_attr "type" "mfcrf")])
13701 (define_insn "movesi_from_cr"
13702 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13703 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
13704 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13705 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
13706 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
13707 UNSPEC_MOVESI_FROM_CR))]
13708 ""
13709 "mfcr %0"
13710 [(set_attr "type" "mfcr")])
13712 (define_insn "*crsave"
13713 [(match_parallel 0 "crsave_operation"
13714 [(set (match_operand:SI 1 "memory_operand" "=m")
13715 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13716 ""
13717 "stw %2,%1"
13718 [(set_attr "type" "store")])
13720 (define_insn "*stmw"
13721 [(match_parallel 0 "stmw_operation"
13722 [(set (match_operand:SI 1 "memory_operand" "=m")
13723 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13724 "TARGET_MULTIPLE"
13725 "stmw %2,%1"
13726 [(set_attr "type" "store")
13727 (set_attr "update" "yes")
13728 (set_attr "indexed" "yes")])
13730 ; The following comment applies to:
13731 ; save_gpregs_*
13732 ; save_fpregs_*
13733 ; restore_gpregs*
13734 ; return_and_restore_gpregs*
13735 ; return_and_restore_fpregs*
13736 ; return_and_restore_fpregs_aix*
13737 ;
13738 ; The out-of-line save / restore functions expects one input argument.
13739 ; Since those are not standard call_insn's, we must avoid using
13740 ; MATCH_OPERAND for that argument. That way the register rename
13741 ; optimization will not try to rename this register.
13742 ; Each pattern is repeated for each possible register number used in
13743 ; various ABIs (r11, r1, and for some functions r12)
13745 (define_insn "*save_gpregs_<mode>_r11"
13746 [(match_parallel 0 "any_parallel_operand"
13747 [(clobber (reg:P 65))
13748 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13749 (use (reg:P 11))
13750 (set (match_operand:P 2 "memory_operand" "=m")
13751 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13752 ""
13753 "bl %1"
13754 [(set_attr "type" "branch")
13755 (set_attr "length" "4")])
13757 (define_insn "*save_gpregs_<mode>_r12"
13758 [(match_parallel 0 "any_parallel_operand"
13759 [(clobber (reg:P 65))
13760 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13761 (use (reg:P 12))
13762 (set (match_operand:P 2 "memory_operand" "=m")
13763 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13764 ""
13765 "bl %1"
13766 [(set_attr "type" "branch")
13767 (set_attr "length" "4")])
13769 (define_insn "*save_gpregs_<mode>_r1"
13770 [(match_parallel 0 "any_parallel_operand"
13771 [(clobber (reg:P 65))
13772 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13773 (use (reg:P 1))
13774 (set (match_operand:P 2 "memory_operand" "=m")
13775 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13776 ""
13777 "bl %1"
13778 [(set_attr "type" "branch")
13779 (set_attr "length" "4")])
13781 (define_insn "*save_fpregs_<mode>_r11"
13782 [(match_parallel 0 "any_parallel_operand"
13783 [(clobber (reg:P 65))
13784 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13785 (use (reg:P 11))
13786 (set (match_operand:DF 2 "memory_operand" "=m")
13787 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13788 ""
13789 "bl %1"
13790 [(set_attr "type" "branch")
13791 (set_attr "length" "4")])
13793 (define_insn "*save_fpregs_<mode>_r12"
13794 [(match_parallel 0 "any_parallel_operand"
13795 [(clobber (reg:P 65))
13796 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13797 (use (reg:P 12))
13798 (set (match_operand:DF 2 "memory_operand" "=m")
13799 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13800 ""
13801 "bl %1"
13802 [(set_attr "type" "branch")
13803 (set_attr "length" "4")])
13805 (define_insn "*save_fpregs_<mode>_r1"
13806 [(match_parallel 0 "any_parallel_operand"
13807 [(clobber (reg:P 65))
13808 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13809 (use (reg:P 1))
13810 (set (match_operand:DF 2 "memory_operand" "=m")
13811 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13812 ""
13813 "bl %1"
13814 [(set_attr "type" "branch")
13815 (set_attr "length" "4")])
13817 ; This is to explain that changes to the stack pointer should
13818 ; not be moved over loads from or stores to stack memory.
13819 (define_insn "stack_tie"
13820 [(match_parallel 0 "tie_operand"
13821 [(set (mem:BLK (reg 1)) (const_int 0))])]
13822 ""
13823 ""
13824 [(set_attr "length" "0")])
13826 (define_expand "epilogue"
13827 [(use (const_int 0))]
13828 ""
13829 {
13830 if (!TARGET_SCHED_PROLOG)
13831 emit_insn (gen_blockage ());
13832 rs6000_emit_epilogue (FALSE);
13833 DONE;
13834 })
13836 ; On some processors, doing the mtcrf one CC register at a time is
13837 ; faster (like on the 604e). On others, doing them all at once is
13838 ; faster; for instance, on the 601 and 750.
13840 (define_expand "movsi_to_cr_one"
13841 [(set (match_operand:CC 0 "cc_reg_operand" "")
13842 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
13843 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13844 ""
13845 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13847 (define_insn "*movsi_to_cr"
13848 [(match_parallel 0 "mtcrf_operation"
13849 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13850 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13851 (match_operand 3 "immediate_operand" "n")]
13852 UNSPEC_MOVESI_TO_CR))])]
13853 ""
13854 "*
13855 {
13856 int mask = 0;
13857 int i;
13858 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13859 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13860 operands[4] = GEN_INT (mask);
13861 return \"mtcrf %4,%2\";
13862 }"
13863 [(set_attr "type" "mtcr")])
13865 (define_insn "*mtcrfsi"
13866 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13867 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13868 (match_operand 2 "immediate_operand" "n")]
13869 UNSPEC_MOVESI_TO_CR))]
13870 "GET_CODE (operands[0]) == REG
13871 && CR_REGNO_P (REGNO (operands[0]))
13872 && GET_CODE (operands[2]) == CONST_INT
13873 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13874 "mtcrf %R0,%1"
13875 [(set_attr "type" "mtcr")])
13877 ; The load-multiple instructions have similar properties.
13878 ; Note that "load_multiple" is a name known to the machine-independent
13879 ; code that actually corresponds to the PowerPC load-string.
13881 (define_insn "*lmw"
13882 [(match_parallel 0 "lmw_operation"
13883 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13884 (match_operand:SI 2 "memory_operand" "m"))])]
13885 "TARGET_MULTIPLE"
13886 "lmw %1,%2"
13887 [(set_attr "type" "load")
13888 (set_attr "update" "yes")
13889 (set_attr "indexed" "yes")
13890 (set_attr "cell_micro" "always")])
13892 (define_insn "*return_internal_<mode>"
13893 [(simple_return)
13894 (use (match_operand:P 0 "register_operand" "lc"))]
13895 ""
13896 "b%T0"
13897 [(set_attr "type" "jmpreg")])
13899 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13900 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13902 ; The following comment applies to:
13903 ; save_gpregs_*
13904 ; save_fpregs_*
13905 ; restore_gpregs*
13906 ; return_and_restore_gpregs*
13907 ; return_and_restore_fpregs*
13908 ; return_and_restore_fpregs_aix*
13909 ;
13910 ; The out-of-line save / restore functions expects one input argument.
13911 ; Since those are not standard call_insn's, we must avoid using
13912 ; MATCH_OPERAND for that argument. That way the register rename
13913 ; optimization will not try to rename this register.
13914 ; Each pattern is repeated for each possible register number used in
13915 ; various ABIs (r11, r1, and for some functions r12)
13917 (define_insn "*restore_gpregs_<mode>_r11"
13918 [(match_parallel 0 "any_parallel_operand"
13919 [(clobber (match_operand:P 1 "register_operand" "=l"))
13920 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13921 (use (reg:P 11))
13922 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13923 (match_operand:P 4 "memory_operand" "m"))])]
13924 ""
13925 "bl %2"
13926 [(set_attr "type" "branch")
13927 (set_attr "length" "4")])
13929 (define_insn "*restore_gpregs_<mode>_r12"
13930 [(match_parallel 0 "any_parallel_operand"
13931 [(clobber (match_operand:P 1 "register_operand" "=l"))
13932 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13933 (use (reg:P 12))
13934 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13935 (match_operand:P 4 "memory_operand" "m"))])]
13936 ""
13937 "bl %2"
13938 [(set_attr "type" "branch")
13939 (set_attr "length" "4")])
13941 (define_insn "*restore_gpregs_<mode>_r1"
13942 [(match_parallel 0 "any_parallel_operand"
13943 [(clobber (match_operand:P 1 "register_operand" "=l"))
13944 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13945 (use (reg:P 1))
13946 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13947 (match_operand:P 4 "memory_operand" "m"))])]
13948 ""
13949 "bl %2"
13950 [(set_attr "type" "branch")
13951 (set_attr "length" "4")])
13953 (define_insn "*return_and_restore_gpregs_<mode>_r11"
13954 [(match_parallel 0 "any_parallel_operand"
13955 [(return)
13956 (clobber (match_operand:P 1 "register_operand" "=l"))
13957 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13958 (use (reg:P 11))
13959 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13960 (match_operand:P 4 "memory_operand" "m"))])]
13961 ""
13962 "b %2"
13963 [(set_attr "type" "branch")
13964 (set_attr "length" "4")])
13966 (define_insn "*return_and_restore_gpregs_<mode>_r12"
13967 [(match_parallel 0 "any_parallel_operand"
13968 [(return)
13969 (clobber (match_operand:P 1 "register_operand" "=l"))
13970 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13971 (use (reg:P 12))
13972 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13973 (match_operand:P 4 "memory_operand" "m"))])]
13974 ""
13975 "b %2"
13976 [(set_attr "type" "branch")
13977 (set_attr "length" "4")])
13979 (define_insn "*return_and_restore_gpregs_<mode>_r1"
13980 [(match_parallel 0 "any_parallel_operand"
13981 [(return)
13982 (clobber (match_operand:P 1 "register_operand" "=l"))
13983 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13984 (use (reg:P 1))
13985 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13986 (match_operand:P 4 "memory_operand" "m"))])]
13987 ""
13988 "b %2"
13989 [(set_attr "type" "branch")
13990 (set_attr "length" "4")])
13992 (define_insn "*return_and_restore_fpregs_<mode>_r11"
13993 [(match_parallel 0 "any_parallel_operand"
13994 [(return)
13995 (clobber (match_operand:P 1 "register_operand" "=l"))
13996 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13997 (use (reg:P 11))
13998 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13999 (match_operand:DF 4 "memory_operand" "m"))])]
14000 ""
14001 "b %2"
14002 [(set_attr "type" "branch")
14003 (set_attr "length" "4")])
14005 (define_insn "*return_and_restore_fpregs_<mode>_r12"
14006 [(match_parallel 0 "any_parallel_operand"
14007 [(return)
14008 (clobber (match_operand:P 1 "register_operand" "=l"))
14009 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14010 (use (reg:P 12))
14011 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14012 (match_operand:DF 4 "memory_operand" "m"))])]
14013 ""
14014 "b %2"
14015 [(set_attr "type" "branch")
14016 (set_attr "length" "4")])
14018 (define_insn "*return_and_restore_fpregs_<mode>_r1"
14019 [(match_parallel 0 "any_parallel_operand"
14020 [(return)
14021 (clobber (match_operand:P 1 "register_operand" "=l"))
14022 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14023 (use (reg:P 1))
14024 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14025 (match_operand:DF 4 "memory_operand" "m"))])]
14026 ""
14027 "b %2"
14028 [(set_attr "type" "branch")
14029 (set_attr "length" "4")])
14031 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
14032 [(match_parallel 0 "any_parallel_operand"
14033 [(return)
14034 (use (match_operand:P 1 "register_operand" "l"))
14035 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14036 (use (reg:P 11))
14037 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14038 (match_operand:DF 4 "memory_operand" "m"))])]
14039 ""
14040 "b %2"
14041 [(set_attr "type" "branch")
14042 (set_attr "length" "4")])
14044 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
14045 [(match_parallel 0 "any_parallel_operand"
14046 [(return)
14047 (use (match_operand:P 1 "register_operand" "l"))
14048 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14049 (use (reg:P 1))
14050 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14051 (match_operand:DF 4 "memory_operand" "m"))])]
14052 ""
14053 "b %2"
14054 [(set_attr "type" "branch")
14055 (set_attr "length" "4")])
14057 ; This is used in compiling the unwind routines.
14058 (define_expand "eh_return"
14059 [(use (match_operand 0 "general_operand" ""))]
14060 ""
14061 "
14062 {
14063 if (TARGET_32BIT)
14064 emit_insn (gen_eh_set_lr_si (operands[0]));
14065 else
14066 emit_insn (gen_eh_set_lr_di (operands[0]));
14067 DONE;
14068 }")
14070 ; We can't expand this before we know where the link register is stored.
14071 (define_insn "eh_set_lr_<mode>"
14072 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14073 UNSPECV_EH_RR)
14074 (clobber (match_scratch:P 1 "=&b"))]
14075 ""
14076 "#")
14078 (define_split
14079 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14080 (clobber (match_scratch 1 ""))]
14081 "reload_completed"
14082 [(const_int 0)]
14083 "
14084 {
14085 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14086 DONE;
14087 }")
14089 (define_insn "prefetch"
14090 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14091 (match_operand:SI 1 "const_int_operand" "n")
14092 (match_operand:SI 2 "const_int_operand" "n"))]
14093 ""
14094 "*
14095 {
14096 if (GET_CODE (operands[0]) == REG)
14097 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14098 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14099 }"
14100 [(set_attr "type" "load")])
14101 \f
14102 (define_insn "bpermd_<mode>"
14103 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14104 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
14105 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
14106 "TARGET_POPCNTD"
14107 "bpermd %0,%1,%2"
14108 [(set_attr "type" "popcnt")])
14110 \f
14111 ;; Builtin fma support. Handle
14112 ;; Note that the conditions for expansion are in the FMA_F iterator.
14114 (define_expand "fma<mode>4"
14115 [(set (match_operand:FMA_F 0 "register_operand" "")
14116 (fma:FMA_F
14117 (match_operand:FMA_F 1 "register_operand" "")
14118 (match_operand:FMA_F 2 "register_operand" "")
14119 (match_operand:FMA_F 3 "register_operand" "")))]
14120 ""
14121 "")
14123 (define_insn "*fma<mode>4_fpr"
14124 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14125 (fma:SFDF
14126 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
14127 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14128 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
14129 "TARGET_<MODE>_FPR"
14130 "@
14131 fmadd<Ftrad> %0,%1,%2,%3
14132 xsmadda<Fvsx> %x0,%x1,%x2
14133 xsmaddm<Fvsx> %x0,%x1,%x3"
14134 [(set_attr "type" "fp")
14135 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14137 ; Altivec only has fma and nfms.
14138 (define_expand "fms<mode>4"
14139 [(set (match_operand:FMA_F 0 "register_operand" "")
14140 (fma:FMA_F
14141 (match_operand:FMA_F 1 "register_operand" "")
14142 (match_operand:FMA_F 2 "register_operand" "")
14143 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
14144 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14145 "")
14147 (define_insn "*fms<mode>4_fpr"
14148 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14149 (fma:SFDF
14150 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14151 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14152 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14153 "TARGET_<MODE>_FPR"
14154 "@
14155 fmsub<Ftrad> %0,%1,%2,%3
14156 xsmsuba<Fvsx> %x0,%x1,%x2
14157 xsmsubm<Fvsx> %x0,%x1,%x3"
14158 [(set_attr "type" "fp")
14159 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14161 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
14162 (define_expand "fnma<mode>4"
14163 [(set (match_operand:FMA_F 0 "register_operand" "")
14164 (neg:FMA_F
14165 (fma:FMA_F
14166 (match_operand:FMA_F 1 "register_operand" "")
14167 (match_operand:FMA_F 2 "register_operand" "")
14168 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14169 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
14170 "")
14172 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
14173 (define_expand "fnms<mode>4"
14174 [(set (match_operand:FMA_F 0 "register_operand" "")
14175 (neg:FMA_F
14176 (fma:FMA_F
14177 (match_operand:FMA_F 1 "register_operand" "")
14178 (match_operand:FMA_F 2 "register_operand" "")
14179 (match_operand:FMA_F 3 "register_operand" ""))))]
14180 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14181 "")
14183 ; Not an official optab name, but used from builtins.
14184 (define_expand "nfma<mode>4"
14185 [(set (match_operand:FMA_F 0 "register_operand" "")
14186 (neg:FMA_F
14187 (fma:FMA_F
14188 (match_operand:FMA_F 1 "register_operand" "")
14189 (match_operand:FMA_F 2 "register_operand" "")
14190 (match_operand:FMA_F 3 "register_operand" ""))))]
14191 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14192 "")
14194 (define_insn "*nfma<mode>4_fpr"
14195 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14196 (neg:SFDF
14197 (fma:SFDF
14198 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14199 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14200 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14201 "TARGET_<MODE>_FPR"
14202 "@
14203 fnmadd<Ftrad> %0,%1,%2,%3
14204 xsnmadda<Fvsx> %x0,%x1,%x2
14205 xsnmaddm<Fvsx> %x0,%x1,%x3"
14206 [(set_attr "type" "fp")
14207 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14209 ; Not an official optab name, but used from builtins.
14210 (define_expand "nfms<mode>4"
14211 [(set (match_operand:FMA_F 0 "register_operand" "")
14212 (neg:FMA_F
14213 (fma:FMA_F
14214 (match_operand:FMA_F 1 "register_operand" "")
14215 (match_operand:FMA_F 2 "register_operand" "")
14216 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14217 ""
14218 "")
14220 (define_insn "*nfmssf4_fpr"
14221 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14222 (neg:SFDF
14223 (fma:SFDF
14224 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14225 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14226 (neg:SFDF
14227 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
14228 "TARGET_<MODE>_FPR"
14229 "@
14230 fnmsub<Ftrad> %0,%1,%2,%3
14231 xsnmsuba<Fvsx> %x0,%x1,%x2
14232 xsnmsubm<Fvsx> %x0,%x1,%x3"
14233 [(set_attr "type" "fp")
14234 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14236 \f
14237 (define_expand "rs6000_get_timebase"
14238 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
14239 ""
14240 {
14241 if (TARGET_POWERPC64)
14242 emit_insn (gen_rs6000_mftb_di (operands[0]));
14243 else
14244 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
14245 DONE;
14246 })
14248 (define_insn "rs6000_get_timebase_ppc32"
14249 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
14250 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
14251 (clobber (match_scratch:SI 1 "=r"))
14252 (clobber (match_scratch:CC 2 "=y"))]
14253 "!TARGET_POWERPC64"
14254 {
14255 if (WORDS_BIG_ENDIAN)
14256 if (TARGET_MFCRF)
14257 {
14258 return "mfspr %0,269\;"
14259 "mfspr %L0,268\;"
14260 "mfspr %1,269\;"
14261 "cmpw %2,%0,%1\;"
14262 "bne- %2,$-16";
14263 }
14264 else
14265 {
14266 return "mftbu %0\;"
14267 "mftb %L0\;"
14268 "mftbu %1\;"
14269 "cmpw %2,%0,%1\;"
14270 "bne- %2,$-16";
14271 }
14272 else
14273 if (TARGET_MFCRF)
14274 {
14275 return "mfspr %L0,269\;"
14276 "mfspr %0,268\;"
14277 "mfspr %1,269\;"
14278 "cmpw %2,%L0,%1\;"
14279 "bne- %2,$-16";
14280 }
14281 else
14282 {
14283 return "mftbu %L0\;"
14284 "mftb %0\;"
14285 "mftbu %1\;"
14286 "cmpw %2,%L0,%1\;"
14287 "bne- %2,$-16";
14288 }
14289 }
14290 [(set_attr "length" "20")])
14292 (define_insn "rs6000_mftb_<mode>"
14293 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
14294 (unspec_volatile:GPR [(const_int 0)] UNSPECV_MFTB))]
14295 ""
14296 {
14297 if (TARGET_MFCRF)
14298 return "mfspr %0,268";
14299 else
14300 return "mftb %0";
14301 })
14303 \f
14304 (define_insn "rs6000_mffs"
14305 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
14306 (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
14307 "TARGET_HARD_FLOAT && TARGET_FPRS"
14308 "mffs %0")
14310 (define_insn "rs6000_mtfsf"
14311 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
14312 (match_operand:DF 1 "gpc_reg_operand" "d")]
14313 UNSPECV_MTFSF)]
14314 "TARGET_HARD_FLOAT && TARGET_FPRS"
14315 "mtfsf %0,%1")
14317 \f
14318 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
14319 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
14320 ;; register that is being loaded. The fused ops must be physically adjacent.
14322 ;; Find cases where the addis that feeds into a load instruction is either used
14323 ;; once or is the same as the target register, and replace it with the fusion
14324 ;; insn
14326 (define_peephole2
14327 [(set (match_operand:P 0 "base_reg_operand" "")
14328 (match_operand:P 1 "fusion_gpr_addis" ""))
14329 (set (match_operand:INT1 2 "base_reg_operand" "")
14330 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
14331 "TARGET_P8_FUSION
14332 && fusion_gpr_load_p (operands[0], operands[1], operands[2],
14333 operands[3])"
14334 [(const_int 0)]
14335 {
14336 expand_fusion_gpr_load (operands);
14337 DONE;
14338 })
14340 ;; Fusion insn, created by the define_peephole2 above (and eventually by
14341 ;; reload)
14343 (define_insn "fusion_gpr_load_<mode>"
14344 [(set (match_operand:INT1 0 "base_reg_operand" "=&b")
14345 (unspec:INT1 [(match_operand:INT1 1 "fusion_gpr_mem_combo" "")]
14346 UNSPEC_FUSION_GPR))]
14347 "TARGET_P8_FUSION"
14348 {
14349 return emit_fusion_gpr_load (operands[0], operands[1]);
14350 }
14351 [(set_attr "type" "load")
14352 (set_attr "length" "8")])
14354 \f
14355 ;; Miscellaneous ISA 2.06 (power7) instructions
14356 (define_insn "addg6s"
14357 [(set (match_operand:SI 0 "register_operand" "=r")
14358 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
14359 (match_operand:SI 2 "register_operand" "r")]
14360 UNSPEC_ADDG6S))]
14361 "TARGET_POPCNTD"
14362 "addg6s %0,%1,%2"
14363 [(set_attr "type" "integer")
14364 (set_attr "length" "4")])
14366 (define_insn "cdtbcd"
14367 [(set (match_operand:SI 0 "register_operand" "=r")
14368 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14369 UNSPEC_CDTBCD))]
14370 "TARGET_POPCNTD"
14371 "cdtbcd %0,%1"
14372 [(set_attr "type" "integer")
14373 (set_attr "length" "4")])
14375 (define_insn "cbcdtd"
14376 [(set (match_operand:SI 0 "register_operand" "=r")
14377 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14378 UNSPEC_CBCDTD))]
14379 "TARGET_POPCNTD"
14380 "cbcdtd %0,%1"
14381 [(set_attr "type" "integer")
14382 (set_attr "length" "4")])
14384 (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
14385 UNSPEC_DIVEO
14386 UNSPEC_DIVEU
14387 UNSPEC_DIVEUO])
14389 (define_int_attr div_extend [(UNSPEC_DIVE "e")
14390 (UNSPEC_DIVEO "eo")
14391 (UNSPEC_DIVEU "eu")
14392 (UNSPEC_DIVEUO "euo")])
14394 (define_insn "div<div_extend>_<mode>"
14395 [(set (match_operand:GPR 0 "register_operand" "=r")
14396 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
14397 (match_operand:GPR 2 "register_operand" "r")]
14398 UNSPEC_DIV_EXTEND))]
14399 "TARGET_POPCNTD"
14400 "div<wd><div_extend> %0,%1,%2"
14401 [(set_attr "type" "div")
14402 (set_attr "size" "<bits>")])
14404 \f
14405 ;; Pack/unpack 128-bit floating point types that take 2 scalar registers
14407 ; Type of the 64-bit part when packing/unpacking 128-bit floating point types
14408 (define_mode_attr FP128_64 [(TF "DF") (TD "DI")])
14410 (define_expand "unpack<mode>"
14411 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
14412 (unspec:<FP128_64>
14413 [(match_operand:FMOVE128 1 "register_operand" "")
14414 (match_operand:QI 2 "const_0_to_1_operand" "")]
14415 UNSPEC_UNPACK_128BIT))]
14416 ""
14417 "")
14419 (define_insn_and_split "unpack<mode>_dm"
14420 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
14421 (unspec:<FP128_64>
14422 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
14423 (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
14424 UNSPEC_UNPACK_128BIT))]
14425 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
14426 "#"
14427 "&& reload_completed"
14428 [(set (match_dup 0) (match_dup 3))]
14429 {
14430 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14432 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14433 {
14434 emit_note (NOTE_INSN_DELETED);
14435 DONE;
14436 }
14438 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14439 }
14440 [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
14441 (set_attr "length" "4")])
14443 (define_insn_and_split "unpack<mode>_nodm"
14444 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
14445 (unspec:<FP128_64>
14446 [(match_operand:FMOVE128 1 "register_operand" "d,d")
14447 (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
14448 UNSPEC_UNPACK_128BIT))]
14449 "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"
14450 "#"
14451 "&& reload_completed"
14452 [(set (match_dup 0) (match_dup 3))]
14453 {
14454 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14456 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14457 {
14458 emit_note (NOTE_INSN_DELETED);
14459 DONE;
14460 }
14462 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14463 }
14464 [(set_attr "type" "fp,fpstore")
14465 (set_attr "length" "4")])
14467 (define_insn_and_split "pack<mode>"
14468 [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
14469 (unspec:FMOVE128
14470 [(match_operand:<FP128_64> 1 "register_operand" "0,d")
14471 (match_operand:<FP128_64> 2 "register_operand" "d,d")]
14472 UNSPEC_PACK_128BIT))]
14473 ""
14474 "@
14475 fmr %L0,%2
14476 #"
14477 "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
14478 [(set (match_dup 3) (match_dup 1))
14479 (set (match_dup 4) (match_dup 2))]
14480 {
14481 unsigned dest_hi = REGNO (operands[0]);
14482 unsigned dest_lo = dest_hi + 1;
14484 gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
14485 gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
14487 operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
14488 operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
14489 }
14490 [(set_attr "type" "fp,fp")
14491 (set_attr "length" "4,8")])
14493 (define_insn "unpackv1ti"
14494 [(set (match_operand:DI 0 "register_operand" "=d,d")
14495 (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")
14496 (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
14497 UNSPEC_UNPACK_128BIT))]
14498 "TARGET_VSX"
14499 {
14500 if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
14501 return ASM_COMMENT_START " xxpermdi to same register";
14503 operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
14504 return "xxpermdi %x0,%x1,%x1,%3";
14505 }
14506 [(set_attr "type" "vecperm")
14507 (set_attr "length" "4")])
14509 (define_insn "packv1ti"
14510 [(set (match_operand:V1TI 0 "register_operand" "=wa")
14511 (unspec:V1TI
14512 [(match_operand:DI 1 "register_operand" "d")
14513 (match_operand:DI 2 "register_operand" "d")]
14514 UNSPEC_PACK_128BIT))]
14515 "TARGET_VSX"
14516 "xxpermdi %x0,%x1,%x2,0"
14517 [(set_attr "type" "vecperm")
14518 (set_attr "length" "4")])
14520 \f
14522 (include "sync.md")
14523 (include "vector.md")
14524 (include "vsx.md")
14525 (include "altivec.md")
14526 (include "spe.md")
14527 (include "dfp.md")
14528 (include "paired.md")
14529 (include "crypto.md")
14530 (include "htm.md")