| blob | 0c095f95c2c4c33057e4ac4dcf5d7e25cd017cd4 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 91-96, 1997, 1998 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 \f
24 ;; Define an insn type attribute. This is used in function unit delay
25 ;; computations.
26 (define_attr "type" "integer,load,store,fpload,fpstore,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
27 (const_string "integer"))
29 ;; Length (in bytes).
30 (define_attr "length" ""
31 (if_then_else (eq_attr "type" "branch")
32 (if_then_else (and (ge (minus (pc) (match_dup 0))
33 (const_int -32768))
34 (lt (minus (pc) (match_dup 0))
35 (const_int 32767)))
36 (const_int 8)
37 (const_int 12))
38 (const_int 4)))
40 ;; Processor type -- this attribute must exactly match the processor_type
41 ;; enumeration in rs6000.h.
43 (define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"
44 (const (symbol_ref "rs6000_cpu_attr")))
46 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
47 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
49 ; Load/Store Unit -- pure PowerPC only
50 ; (POWER and 601 use Integer Unit)
51 (define_function_unit "lsu" 1 0
52 (and (eq_attr "type" "load")
53 (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
54 2 1)
56 (define_function_unit "lsu" 1 0
57 (and (eq_attr "type" "store,fpstore")
58 (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
59 1 1)
61 (define_function_unit "lsu" 1 0
62 (and (eq_attr "type" "fpload")
63 (eq_attr "cpu" "mpccore,ppc603"))
64 2 1)
66 (define_function_unit "lsu" 1 0
67 (and (eq_attr "type" "fpload")
68 (eq_attr "cpu" "ppc604,ppc620"))
69 3 1)
71 (define_function_unit "iu" 1 0
72 (and (eq_attr "type" "load")
73 (eq_attr "cpu" "rios1,ppc403,ppc601"))
74 2 1)
76 (define_function_unit "iu" 1 0
77 (and (eq_attr "type" "store,fpstore")
78 (eq_attr "cpu" "rios1,ppc403,ppc601"))
79 1 1)
81 (define_function_unit "fpu" 1 0
82 (and (eq_attr "type" "fpstore")
83 (eq_attr "cpu" "rios1,ppc601"))
84 0 1)
86 (define_function_unit "iu" 1 0
87 (and (eq_attr "type" "fpload")
88 (eq_attr "cpu" "rios1"))
89 2 1)
91 (define_function_unit "iu" 1 0
92 (and (eq_attr "type" "fpload")
93 (eq_attr "cpu" "ppc601"))
94 3 1)
96 (define_function_unit "iu2" 2 0
97 (and (eq_attr "type" "load,fpload")
98 (eq_attr "cpu" "rios2"))
99 2 1)
101 (define_function_unit "iu2" 2 0
102 (and (eq_attr "type" "store,fpstore")
103 (eq_attr "cpu" "rios2"))
104 1 1)
106 ; Integer Unit (RIOS1, PPC601, PPC603)
107 (define_function_unit "iu" 1 0
108 (and (eq_attr "type" "integer")
109 (eq_attr "cpu" "rios1,mpccore,ppc403,ppc601,ppc603"))
110 1 1)
112 (define_function_unit "iu" 1 0
113 (and (eq_attr "type" "imul")
114 (eq_attr "cpu" "ppc403"))
115 4 4)
117 (define_function_unit "iu" 1 0
118 (and (eq_attr "type" "imul")
119 (eq_attr "cpu" "rios1,ppc601,ppc603"))
120 5 5)
122 (define_function_unit "iu" 1 0
123 (and (eq_attr "type" "idiv")
124 (eq_attr "cpu" "rios1"))
125 19 19)
127 (define_function_unit "iu" 1 0
128 (and (eq_attr "type" "idiv")
129 (eq_attr "cpu" "ppc403"))
130 33 33)
132 (define_function_unit "iu" 1 0
133 (and (eq_attr "type" "idiv")
134 (eq_attr "cpu" "ppc601"))
135 36 36)
137 (define_function_unit "iu" 1 0
138 (and (eq_attr "type" "idiv")
139 (eq_attr "cpu" "ppc603"))
140 37 36)
142 ; RIOS2 has two integer units: a primary one which can perform all
143 ; operations and a secondary one which is fed in lock step with the first
144 ; and can perform "simple" integer operations.
145 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
146 ; for the complex insns.
147 (define_function_unit "iu2" 2 0
148 (and (eq_attr "type" "integer")
149 (eq_attr "cpu" "rios2"))
150 1 1)
152 (define_function_unit "iu2" 2 0
153 (and (eq_attr "type" "imul")
154 (eq_attr "cpu" "rios2"))
155 2 2)
157 (define_function_unit "iu2" 2 0
158 (and (eq_attr "type" "idiv")
159 (eq_attr "cpu" "rios2"))
160 13 13)
162 (define_function_unit "imuldiv" 1 0
163 (and (eq_attr "type" "imul")
164 (eq_attr "cpu" "rios2"))
165 2 2)
167 (define_function_unit "imuldiv" 1 0
168 (and (eq_attr "type" "idiv")
169 (eq_attr "cpu" "rios2"))
170 13 13)
172 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
173 ; Divide latency varies greatly from 2-11, use 6 as average
174 (define_function_unit "imuldiv" 1 0
175 (and (eq_attr "type" "imul")
176 (eq_attr "cpu" "mpccore"))
177 2 1)
179 (define_function_unit "imuldiv" 1 0
180 (and (eq_attr "type" "idiv")
181 (eq_attr "cpu" "mpccore"))
182 6 6)
184 ; PPC604 has two units that perform integer operations
185 ; and one unit for divide/multiply operations (and move
186 ; from/to spr).
187 (define_function_unit "iu2" 2 0
188 (and (eq_attr "type" "integer")
189 (eq_attr "cpu" "ppc604,ppc620"))
190 1 1)
192 (define_function_unit "imuldiv" 1 0
193 (and (eq_attr "type" "imul")
194 (eq_attr "cpu" "ppc604,ppc620"))
195 4 2)
197 (define_function_unit "imuldiv" 1 0
198 (and (eq_attr "type" "idiv")
199 (eq_attr "cpu" "ppc604,ppc620"))
200 20 19)
202 ; compare is done on integer unit, but feeds insns which
203 ; execute on the branch unit.
204 (define_function_unit "iu" 1 0
205 (and (eq_attr "type" "compare")
206 (eq_attr "cpu" "rios1"))
207 4 1)
209 (define_function_unit "iu" 1 0
210 (and (eq_attr "type" "delayed_compare")
211 (eq_attr "cpu" "rios1"))
212 5 1)
214 (define_function_unit "iu" 1 0
215 (and (eq_attr "type" "compare,delayed_compare")
216 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
217 3 1)
219 (define_function_unit "iu2" 2 0
220 (and (eq_attr "type" "compare,delayed_compare")
221 (eq_attr "cpu" "rios2"))
222 3 1)
224 (define_function_unit "iu2" 2 0
225 (and (eq_attr "type" "compare,delayed_compare")
226 (eq_attr "cpu" "ppc604,ppc620"))
227 1 1)
229 ; fp compare uses fp unit
230 (define_function_unit "fpu" 1 0
231 (and (eq_attr "type" "fpcompare")
232 (eq_attr "cpu" "rios1"))
233 9 1)
235 ; rios1 and rios2 have different fpcompare delays
236 (define_function_unit "fpu2" 2 0
237 (and (eq_attr "type" "fpcompare")
238 (eq_attr "cpu" "rios2"))
239 5 1)
241 ; on ppc601 and ppc603, fpcompare takes also 2 cycles from
242 ; the integer unit
243 ; here we do not define delays, just occupy the unit. The dependencies
244 ; will be assigned by the fpcompare definition in the fpu.
245 (define_function_unit "iu" 1 0
246 (and (eq_attr "type" "fpcompare")
247 (eq_attr "cpu" "ppc601,ppc603"))
248 0 2)
250 ; fp compare uses fp unit
251 (define_function_unit "fpu" 1 0
252 (and (eq_attr "type" "fpcompare")
253 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
254 5 1)
256 (define_function_unit "fpu" 1 0
257 (and (eq_attr "type" "fpcompare")
258 (eq_attr "cpu" "mpccore"))
259 1 1)
261 (define_function_unit "bpu" 1 0
262 (and (eq_attr "type" "mtjmpr")
263 (eq_attr "cpu" "rios1,rios2"))
264 5 1)
266 (define_function_unit "bpu" 1 0
267 (and (eq_attr "type" "mtjmpr")
268 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
269 4 1)
271 ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
272 (define_function_unit "bpu" 1 0
273 (eq_attr "type" "jmpreg")
274 1 1)
276 (define_function_unit "bpu" 1 0
277 (eq_attr "type" "branch")
278 1 1)
280 ; Floating Point Unit
281 (define_function_unit "fpu" 1 0
282 (and (eq_attr "type" "fp,dmul")
283 (eq_attr "cpu" "rios1"))
284 2 1)
286 (define_function_unit "fpu" 1 0
287 (and (eq_attr "type" "fp")
288 (eq_attr "cpu" "mpccore"))
289 4 4)
291 (define_function_unit "fpu" 1 0
292 (and (eq_attr "type" "fp")
293 (eq_attr "cpu" "ppc601"))
294 4 1)
296 (define_function_unit "fpu" 1 0
297 (and (eq_attr "type" "fp")
298 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
299 3 1)
301 (define_function_unit "fpu" 1 0
302 (and (eq_attr "type" "dmul")
303 (eq_attr "cpu" "mpccore"))
304 5 5)
306 (define_function_unit "fpu" 1 0
307 (and (eq_attr "type" "dmul")
308 (eq_attr "cpu" "ppc601"))
309 5 2)
311 ; is this true?
312 (define_function_unit "fpu" 1 0
313 (and (eq_attr "type" "dmul")
314 (eq_attr "cpu" "ppc603"))
315 4 2)
317 (define_function_unit "fpu" 1 0
318 (and (eq_attr "type" "dmul")
319 (eq_attr "cpu" "ppc604,ppc620"))
320 3 1)
322 (define_function_unit "fpu" 1 0
323 (and (eq_attr "type" "sdiv,ddiv")
324 (eq_attr "cpu" "rios1"))
325 19 19)
327 (define_function_unit "fpu" 1 0
328 (and (eq_attr "type" "sdiv")
329 (eq_attr "cpu" "ppc601"))
330 17 17)
332 (define_function_unit "fpu" 1 0
333 (and (eq_attr "type" "sdiv")
334 (eq_attr "cpu" "mpccore"))
335 10 10)
337 (define_function_unit "fpu" 1 0
338 (and (eq_attr "type" "sdiv")
339 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
340 18 18)
342 (define_function_unit "fpu" 1 0
343 (and (eq_attr "type" "ddiv")
344 (eq_attr "cpu" "mpccore"))
345 17 17)
347 (define_function_unit "fpu" 1 0
348 (and (eq_attr "type" "ddiv")
349 (eq_attr "cpu" "ppc601,ppc604,ppc620"))
350 31 31)
352 (define_function_unit "fpu" 1 0
353 (and (eq_attr "type" "ddiv")
354 (eq_attr "cpu" "ppc603"))
355 33 33)
357 (define_function_unit "fpu" 1 0
358 (and (eq_attr "type" "ssqrt")
359 (eq_attr "cpu" "ppc620"))
360 31 31)
362 (define_function_unit "fpu" 1 0
363 (and (eq_attr "type" "dsqrt")
364 (eq_attr "cpu" "ppc620"))
365 31 31)
367 ; RIOS2 has two symmetric FPUs.
368 (define_function_unit "fpu2" 2 0
369 (and (eq_attr "type" "fp")
370 (eq_attr "cpu" "rios2"))
371 2 1)
373 (define_function_unit "fpu2" 2 0
374 (and (eq_attr "type" "dmul")
375 (eq_attr "cpu" "rios2"))
376 2 1)
378 (define_function_unit "fpu2" 2 0
379 (and (eq_attr "type" "sdiv,ddiv")
380 (eq_attr "cpu" "rios2"))
381 17 17)
383 (define_function_unit "fpu2" 2 0
384 (and (eq_attr "type" "ssqrt,dsqrt")
385 (eq_attr "cpu" "rios2"))
386 26 26)
388 \f
389 ;; Start with fixed-point load and store insns. Here we put only the more
390 ;; complex forms. Basic data transfer is done later.
392 (define_expand "zero_extendqidi2"
393 [(set (match_operand:DI 0 "gpc_reg_operand" "")
394 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
395 "TARGET_POWERPC64"
396 "")
398 (define_insn ""
399 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
400 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
401 "TARGET_POWERPC64"
402 "@
403 lbz%U1%X1 %0,%1
404 rldicl %0,%1,0,56"
405 [(set_attr "type" "load,*")])
407 (define_insn ""
408 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
409 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
410 (const_int 0)))
411 (clobber (match_scratch:DI 2 "=r"))]
412 "TARGET_POWERPC64"
413 "rldicl. %2,%1,0,56"
414 [(set_attr "type" "compare")])
416 (define_insn ""
417 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
418 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
419 (const_int 0)))
420 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
421 (zero_extend:DI (match_dup 1)))]
422 "TARGET_POWERPC64"
423 "rldicl. %0,%1,0,56"
424 [(set_attr "type" "compare")])
426 (define_insn "extendqidi2"
427 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
428 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
429 "TARGET_POWERPC64"
430 "extsb %0,%1")
432 (define_insn ""
433 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
434 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
435 (const_int 0)))
436 (clobber (match_scratch:DI 2 "=r"))]
437 "TARGET_POWERPC64"
438 "extsb. %2,%1"
439 [(set_attr "type" "compare")])
441 (define_insn ""
442 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
443 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
444 (const_int 0)))
445 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
446 (sign_extend:DI (match_dup 1)))]
447 "TARGET_POWERPC64"
448 "extsb. %0,%1"
449 [(set_attr "type" "compare")])
451 (define_expand "zero_extendhidi2"
452 [(set (match_operand:DI 0 "gpc_reg_operand" "")
453 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
454 "TARGET_POWERPC64"
455 "")
457 (define_insn ""
458 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
459 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
460 "TARGET_POWERPC64"
461 "@
462 lhz%U1%X1 %0,%1
463 rldicl %0,%1,0,48"
464 [(set_attr "type" "load,*")])
466 (define_insn ""
467 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
468 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
469 (const_int 0)))
470 (clobber (match_scratch:DI 2 "=r"))]
471 "TARGET_POWERPC64"
472 "rldicl. %2,%1,0,48"
473 [(set_attr "type" "compare")])
475 (define_insn ""
476 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
477 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
478 (const_int 0)))
479 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
480 (zero_extend:DI (match_dup 1)))]
481 "TARGET_POWERPC64"
482 "rldicl. %0,%1,0,48"
483 [(set_attr "type" "compare")])
485 (define_expand "extendhidi2"
486 [(set (match_operand:DI 0 "gpc_reg_operand" "")
487 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
488 "TARGET_POWERPC64"
489 "")
491 (define_insn ""
492 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
493 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
494 "TARGET_POWERPC64"
495 "@
496 lha%U1%X1 %0,%1
497 extsh %0,%1"
498 [(set_attr "type" "load,*")])
500 (define_insn ""
501 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
502 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
503 (const_int 0)))
504 (clobber (match_scratch:DI 2 "=r"))]
505 "TARGET_POWERPC64"
506 "extsh. %2,%1"
507 [(set_attr "type" "compare")])
509 (define_insn ""
510 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
511 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
512 (const_int 0)))
513 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
514 (sign_extend:DI (match_dup 1)))]
515 "TARGET_POWERPC64"
516 "extsh. %0,%1"
517 [(set_attr "type" "compare")])
519 (define_expand "zero_extendsidi2"
520 [(set (match_operand:DI 0 "gpc_reg_operand" "")
521 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
522 "TARGET_POWERPC64"
523 "")
525 (define_insn ""
526 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
527 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
528 "TARGET_POWERPC64"
529 "@
530 lwz%U1%X1 %0,%1
531 rldicl %0,%1,0,32"
532 [(set_attr "type" "load,*")])
534 (define_insn ""
535 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
536 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
537 (const_int 0)))
538 (clobber (match_scratch:DI 2 "=r"))]
539 "TARGET_POWERPC64"
540 "rldicl. %2,%1,0,32"
541 [(set_attr "type" "compare")])
543 (define_insn ""
544 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
545 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
546 (const_int 0)))
547 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
548 (zero_extend:DI (match_dup 1)))]
549 "TARGET_POWERPC64"
550 "rldicl. %0,%1,0,32"
551 [(set_attr "type" "compare")])
553 (define_expand "extendsidi2"
554 [(set (match_operand:DI 0 "gpc_reg_operand" "")
555 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
556 "TARGET_POWERPC64"
557 "")
559 (define_insn ""
560 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
561 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
562 "TARGET_POWERPC64"
563 "@
564 lwa%U1%X1 %0,%1
565 extsw %0,%1"
566 [(set_attr "type" "load,*")])
568 (define_insn ""
569 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
570 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
571 (const_int 0)))
572 (clobber (match_scratch:DI 2 "=r"))]
573 "TARGET_POWERPC64"
574 "extsw. %2,%1"
575 [(set_attr "type" "compare")])
577 (define_insn ""
578 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
579 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
580 (const_int 0)))
581 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
582 (sign_extend:DI (match_dup 1)))]
583 "TARGET_POWERPC64"
584 "extsw. %0,%1"
585 [(set_attr "type" "compare")])
587 (define_expand "zero_extendqisi2"
588 [(set (match_operand:SI 0 "gpc_reg_operand" "")
589 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
590 ""
591 "")
593 (define_insn ""
594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
595 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
596 ""
597 "@
598 lbz%U1%X1 %0,%1
599 {rlinm|rlwinm} %0,%1,0,0xff"
600 [(set_attr "type" "load,*")])
602 (define_insn ""
603 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
604 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
605 (const_int 0)))
606 (clobber (match_scratch:SI 2 "=r"))]
607 ""
608 "{andil.|andi.} %2,%1,0xff"
609 [(set_attr "type" "compare")])
611 (define_insn ""
612 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
613 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
614 (const_int 0)))
615 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
616 (zero_extend:SI (match_dup 1)))]
617 ""
618 "{andil.|andi.} %0,%1,0xff"
619 [(set_attr "type" "compare")])
621 (define_expand "extendqisi2"
622 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
623 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
624 ""
625 "
626 {
627 if (TARGET_POWERPC)
628 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
629 else if (TARGET_POWER)
630 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
631 else
632 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
633 DONE;
634 }")
636 (define_insn "extendqisi2_ppc"
637 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
638 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
639 "TARGET_POWERPC"
640 "extsb %0,%1")
642 (define_insn ""
643 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
644 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
645 (const_int 0)))
646 (clobber (match_scratch:SI 2 "=r"))]
647 "TARGET_POWERPC"
648 "extsb. %2,%1"
649 [(set_attr "type" "compare")])
651 (define_insn ""
652 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
653 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
654 (const_int 0)))
655 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
656 (sign_extend:SI (match_dup 1)))]
657 "TARGET_POWERPC"
658 "extsb. %0,%1"
659 [(set_attr "type" "compare")])
661 (define_expand "extendqisi2_power"
662 [(parallel [(set (match_dup 2)
663 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
664 (const_int 24)))
665 (clobber (scratch:SI))])
666 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
667 (ashiftrt:SI (match_dup 2)
668 (const_int 24)))
669 (clobber (scratch:SI))])]
670 "TARGET_POWER"
671 "
672 { operands[1] = gen_lowpart (SImode, operands[1]);
673 operands[2] = gen_reg_rtx (SImode); }")
675 (define_expand "extendqisi2_no_power"
676 [(set (match_dup 2)
677 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
678 (const_int 24)))
679 (set (match_operand:SI 0 "gpc_reg_operand" "")
680 (ashiftrt:SI (match_dup 2)
681 (const_int 24)))]
682 "! TARGET_POWER && ! TARGET_POWERPC"
683 "
684 { operands[1] = gen_lowpart (SImode, operands[1]);
685 operands[2] = gen_reg_rtx (SImode); }")
687 (define_expand "zero_extendqihi2"
688 [(set (match_operand:HI 0 "gpc_reg_operand" "")
689 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
690 ""
691 "")
693 (define_insn ""
694 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
695 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
696 ""
697 "@
698 lbz%U1%X1 %0,%1
699 {rlinm|rlwinm} %0,%1,0,0xff"
700 [(set_attr "type" "load,*")])
702 (define_insn ""
703 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
704 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
705 (const_int 0)))
706 (clobber (match_scratch:HI 2 "=r"))]
707 ""
708 "{andil.|andi.} %2,%1,0xff"
709 [(set_attr "type" "compare")])
711 (define_insn ""
712 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
713 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
714 (const_int 0)))
715 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
716 (zero_extend:HI (match_dup 1)))]
717 ""
718 "{andil.|andi.} %0,%1,0xff"
719 [(set_attr "type" "compare")])
721 (define_expand "extendqihi2"
722 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
723 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
724 ""
725 "
726 {
727 if (TARGET_POWERPC)
728 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
729 else if (TARGET_POWER)
730 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
731 else
732 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
733 DONE;
734 }")
736 (define_insn "extendqihi2_ppc"
737 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
738 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
739 "TARGET_POWERPC"
740 "extsb %0,%1")
742 (define_insn ""
743 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
744 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
745 (const_int 0)))
746 (clobber (match_scratch:HI 2 "=r"))]
747 "TARGET_POWERPC"
748 "extsb. %2,%1"
749 [(set_attr "type" "compare")])
751 (define_insn ""
752 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
753 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
754 (const_int 0)))
755 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
756 (sign_extend:HI (match_dup 1)))]
757 "TARGET_POWERPC"
758 "extsb. %0,%1"
759 [(set_attr "type" "compare")])
761 (define_expand "extendqihi2_power"
762 [(parallel [(set (match_dup 2)
763 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
764 (const_int 24)))
765 (clobber (scratch:SI))])
766 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
767 (ashiftrt:SI (match_dup 2)
768 (const_int 24)))
769 (clobber (scratch:SI))])]
770 "TARGET_POWER"
771 "
772 { operands[0] = gen_lowpart (SImode, operands[0]);
773 operands[1] = gen_lowpart (SImode, operands[1]);
774 operands[2] = gen_reg_rtx (SImode); }")
776 (define_expand "extendqihi2_no_power"
777 [(set (match_dup 2)
778 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
779 (const_int 24)))
780 (set (match_operand:HI 0 "gpc_reg_operand" "")
781 (ashiftrt:SI (match_dup 2)
782 (const_int 24)))]
783 "! TARGET_POWER && ! TARGET_POWERPC"
784 "
785 { operands[0] = gen_lowpart (SImode, operands[0]);
786 operands[1] = gen_lowpart (SImode, operands[1]);
787 operands[2] = gen_reg_rtx (SImode); }")
789 (define_expand "zero_extendhisi2"
790 [(set (match_operand:SI 0 "gpc_reg_operand" "")
791 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
792 ""
793 "")
795 (define_insn ""
796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
797 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
798 ""
799 "@
800 lhz%U1%X1 %0,%1
801 {rlinm|rlwinm} %0,%1,0,0xffff"
802 [(set_attr "type" "load,*")])
804 (define_insn ""
805 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
806 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
807 (const_int 0)))
808 (clobber (match_scratch:SI 2 "=r"))]
809 ""
810 "{andil.|andi.} %2,%1,0xffff"
811 [(set_attr "type" "compare")])
813 (define_insn ""
814 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
815 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
816 (const_int 0)))
817 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
818 (zero_extend:SI (match_dup 1)))]
819 ""
820 "{andil.|andi.} %0,%1,0xffff"
821 [(set_attr "type" "compare")])
823 (define_expand "extendhisi2"
824 [(set (match_operand:SI 0 "gpc_reg_operand" "")
825 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
826 ""
827 "")
829 (define_insn ""
830 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
831 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
832 ""
833 "@
834 lha%U1%X1 %0,%1
835 {exts|extsh} %0,%1"
836 [(set_attr "type" "load,*")])
838 (define_insn ""
839 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
840 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
841 (const_int 0)))
842 (clobber (match_scratch:SI 2 "=r"))]
843 ""
844 "{exts.|extsh.} %2,%1"
845 [(set_attr "type" "compare")])
847 (define_insn ""
848 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
849 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
850 (const_int 0)))
851 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
852 (sign_extend:SI (match_dup 1)))]
853 ""
854 "{exts.|extsh.} %0,%1"
855 [(set_attr "type" "compare")])
856 \f
857 ;; Fixed-point arithmetic insns.
859 ;; Discourage ai/addic because of carry but provide it in an alternative
860 ;; allowing register zero as source.
861 (define_expand "addsi3"
862 [(set (match_operand:SI 0 "gpc_reg_operand" "")
863 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
864 (match_operand:SI 2 "reg_or_cint_operand" "")))]
865 ""
866 "
867 {
868 if (GET_CODE (operands[2]) == CONST_INT
869 && !add_operand (operands[2], SImode))
870 {
871 rtx tmp = ((reload_in_progress || reload_completed
872 || rtx_equal_p (operands[0], operands[1]))
873 ? operands[0] : gen_reg_rtx (SImode));
875 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
876 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
878 if (low & 0x8000)
879 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
881 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high)));
882 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
883 DONE;
884 }
885 }")
887 (define_insn "*addsi3_internal1"
888 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
889 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
890 (match_operand:SI 2 "add_operand" "r,I,I,J")))]
891 ""
892 "@
893 {cax|add} %0,%1,%2
894 {cal %0,%2(%1)|addi %0,%1,%2}
895 {ai|addic} %0,%1,%2
896 {cau|addis} %0,%1,%v2"
897 [(set_attr "length" "4,4,4,4")])
899 (define_insn "*addsi3_internal2"
900 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
901 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
902 (match_operand:SI 2 "reg_or_short_operand" "r,I"))
903 (const_int 0)))
904 (clobber (match_scratch:SI 3 "=r,r"))]
905 ""
906 "@
907 {cax.|add.} %3,%1,%2
908 {ai.|addic.} %3,%1,%2"
909 [(set_attr "type" "compare")])
911 (define_insn "*addsi3_internal3"
912 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
913 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
914 (match_operand:SI 2 "reg_or_short_operand" "r,I"))
915 (const_int 0)))
916 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
917 (plus:SI (match_dup 1) (match_dup 2)))]
918 ""
919 "@
920 {cax.|add.} %0,%1,%2
921 {ai.|addic.} %0,%1,%2"
922 [(set_attr "type" "compare")])
924 ;; Split an add that we can't do in one insn into two insns, each of which
925 ;; does one 16-bit part. This is used by combine. Note that the low-order
926 ;; add should be last in case the result gets used in an address.
928 (define_split
929 [(set (match_operand:SI 0 "gpc_reg_operand" "")
930 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
931 (match_operand:SI 2 "non_add_cint_operand" "")))]
932 ""
933 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
934 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
935 "
936 {
937 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
938 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
940 if (low & 0x8000)
941 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
943 operands[3] = GEN_INT (high);
944 operands[4] = GEN_INT (low);
945 }")
947 (define_insn "one_cmplsi2"
948 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
949 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
950 ""
951 "nor %0,%1,%1")
953 (define_insn ""
954 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
955 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
956 (const_int 0)))
957 (clobber (match_scratch:SI 2 "=r"))]
958 ""
959 "nor. %2,%1,%1"
960 [(set_attr "type" "compare")])
962 (define_insn ""
963 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
964 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
965 (const_int 0)))
966 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
967 (not:SI (match_dup 1)))]
968 ""
969 "nor. %0,%1,%1"
970 [(set_attr "type" "compare")])
972 (define_insn ""
973 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
974 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
975 (match_operand:SI 2 "gpc_reg_operand" "r")))]
976 "! TARGET_POWERPC"
977 "{sf%I1|subf%I1c} %0,%2,%1")
979 (define_insn ""
980 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
981 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
982 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
983 "TARGET_POWERPC"
984 "@
985 subf %0,%2,%1
986 subfic %0,%2,%1")
988 (define_insn ""
989 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
990 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
991 (match_operand:SI 2 "gpc_reg_operand" "r"))
992 (const_int 0)))
993 (clobber (match_scratch:SI 3 "=r"))]
994 "! TARGET_POWERPC"
995 "{sf.|subfc.} %3,%2,%1"
996 [(set_attr "type" "compare")])
998 (define_insn ""
999 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1000 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1001 (match_operand:SI 2 "gpc_reg_operand" "r"))
1002 (const_int 0)))
1003 (clobber (match_scratch:SI 3 "=r"))]
1004 "TARGET_POWERPC"
1005 "subf. %3,%2,%1"
1006 [(set_attr "type" "compare")])
1008 (define_insn ""
1009 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1010 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1011 (match_operand:SI 2 "gpc_reg_operand" "r"))
1012 (const_int 0)))
1013 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1014 (minus:SI (match_dup 1) (match_dup 2)))]
1015 "! TARGET_POWERPC"
1016 "{sf.|subfc.} %0,%2,%1"
1017 [(set_attr "type" "compare")])
1019 (define_insn ""
1020 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1021 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1022 (match_operand:SI 2 "gpc_reg_operand" "r"))
1023 (const_int 0)))
1024 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1025 (minus:SI (match_dup 1) (match_dup 2)))]
1026 "TARGET_POWERPC"
1027 "subf. %0,%2,%1"
1028 [(set_attr "type" "compare")])
1030 (define_expand "subsi3"
1031 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1032 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1033 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1034 ""
1035 "
1036 {
1037 if (GET_CODE (operands[2]) == CONST_INT)
1038 {
1039 emit_insn (gen_addsi3 (operands[0], operands[1],
1040 negate_rtx (SImode, operands[2])));
1041 DONE;
1042 }
1043 }")
1045 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1046 ;; instruction and some auxiliary computations. Then we just have a single
1047 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1048 ;; combine.
1050 (define_expand "sminsi3"
1051 [(set (match_dup 3)
1052 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1053 (match_operand:SI 2 "reg_or_short_operand" ""))
1054 (const_int 0)
1055 (minus:SI (match_dup 2) (match_dup 1))))
1056 (set (match_operand:SI 0 "gpc_reg_operand" "")
1057 (minus:SI (match_dup 2) (match_dup 3)))]
1058 "TARGET_POWER"
1059 "
1060 { operands[3] = gen_reg_rtx (SImode); }")
1062 (define_split
1063 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1064 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1065 (match_operand:SI 2 "reg_or_short_operand" "")))
1066 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1067 "TARGET_POWER"
1068 [(set (match_dup 3)
1069 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1070 (const_int 0)
1071 (minus:SI (match_dup 2) (match_dup 1))))
1072 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1073 "")
1075 (define_expand "smaxsi3"
1076 [(set (match_dup 3)
1077 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1078 (match_operand:SI 2 "reg_or_short_operand" ""))
1079 (const_int 0)
1080 (minus:SI (match_dup 2) (match_dup 1))))
1081 (set (match_operand:SI 0 "gpc_reg_operand" "")
1082 (plus:SI (match_dup 3) (match_dup 1)))]
1083 "TARGET_POWER"
1084 "
1085 { operands[3] = gen_reg_rtx (SImode); }")
1087 (define_split
1088 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1089 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1090 (match_operand:SI 2 "reg_or_short_operand" "")))
1091 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1092 "TARGET_POWER"
1093 [(set (match_dup 3)
1094 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1095 (const_int 0)
1096 (minus:SI (match_dup 2) (match_dup 1))))
1097 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1098 "")
1100 (define_expand "uminsi3"
1101 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1102 (match_dup 5)))
1103 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1104 (match_dup 5)))
1105 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1106 (const_int 0)
1107 (minus:SI (match_dup 4) (match_dup 3))))
1108 (set (match_operand:SI 0 "gpc_reg_operand" "")
1109 (minus:SI (match_dup 2) (match_dup 3)))]
1110 "TARGET_POWER"
1111 "
1112 {
1113 operands[3] = gen_reg_rtx (SImode);
1114 operands[4] = gen_reg_rtx (SImode);
1115 operands[5] = GEN_INT (-2147483647 - 1);
1116 }")
1118 (define_expand "umaxsi3"
1119 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1120 (match_dup 5)))
1121 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1122 (match_dup 5)))
1123 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1124 (const_int 0)
1125 (minus:SI (match_dup 4) (match_dup 3))))
1126 (set (match_operand:SI 0 "gpc_reg_operand" "")
1127 (plus:SI (match_dup 3) (match_dup 1)))]
1128 "TARGET_POWER"
1129 "
1130 {
1131 operands[3] = gen_reg_rtx (SImode);
1132 operands[4] = gen_reg_rtx (SImode);
1133 operands[5] = GEN_INT (-2147483647 - 1);
1134 }")
1136 (define_insn ""
1137 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1138 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1139 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1140 (const_int 0)
1141 (minus:SI (match_dup 2) (match_dup 1))))]
1142 "TARGET_POWER"
1143 "doz%I2 %0,%1,%2")
1145 (define_insn ""
1146 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1147 (compare:CC
1148 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1149 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1150 (const_int 0)
1151 (minus:SI (match_dup 2) (match_dup 1)))
1152 (const_int 0)))
1153 (clobber (match_scratch:SI 3 "=r"))]
1154 "TARGET_POWER"
1155 "doz%I2. %3,%1,%2"
1156 [(set_attr "type" "delayed_compare")])
1158 (define_insn ""
1159 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1160 (compare:CC
1161 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1162 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1163 (const_int 0)
1164 (minus:SI (match_dup 2) (match_dup 1)))
1165 (const_int 0)))
1166 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1167 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1168 (const_int 0)
1169 (minus:SI (match_dup 2) (match_dup 1))))]
1170 "TARGET_POWER"
1171 "doz%I2. %0,%1,%2"
1172 [(set_attr "type" "delayed_compare")])
1174 ;; We don't need abs with condition code because such comparisons should
1175 ;; never be done.
1176 (define_expand "abssi2"
1177 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1178 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1179 ""
1180 "
1181 {
1182 if (!TARGET_POWER)
1183 {
1184 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1185 DONE;
1186 }
1187 }")
1189 (define_insn "abssi2_power"
1190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1191 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1192 "TARGET_POWER"
1193 "abs %0,%1")
1195 (define_insn "abssi2_nopower"
1196 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1197 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1198 (clobber (match_scratch:SI 2 "=&r,&r"))]
1199 "!TARGET_POWER"
1200 "*
1201 {
1202 return (TARGET_POWERPC)
1203 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
1204 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
1205 }"
1206 [(set_attr "length" "12")])
1208 (define_split
1209 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1210 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1211 (clobber (match_scratch:SI 2 "=&r,&r"))]
1212 "!TARGET_POWER && reload_completed"
1213 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1214 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1215 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1216 "")
1218 (define_insn ""
1219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1220 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1221 "TARGET_POWER"
1222 "nabs %0,%1")
1224 (define_insn ""
1225 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1226 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1227 (clobber (match_scratch:SI 2 "=&r,&r"))]
1228 "!TARGET_POWER"
1229 "*
1230 {
1231 return (TARGET_POWERPC)
1232 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
1233 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
1234 }"
1235 [(set_attr "length" "12")])
1237 (define_split
1238 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1239 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1240 (clobber (match_scratch:SI 2 "=&r,&r"))]
1241 "!TARGET_POWER && reload_completed"
1242 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1243 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1244 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1245 "")
1247 (define_insn "negsi2"
1248 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1249 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1250 ""
1251 "neg %0,%1")
1253 (define_insn ""
1254 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1255 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1256 (const_int 0)))
1257 (clobber (match_scratch:SI 2 "=r"))]
1258 ""
1259 "neg. %2,%1"
1260 [(set_attr "type" "compare")])
1262 (define_insn ""
1263 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1264 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1265 (const_int 0)))
1266 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1267 (neg:SI (match_dup 1)))]
1268 ""
1269 "neg. %0,%1"
1270 [(set_attr "type" "compare")])
1272 (define_insn "ffssi2"
1273 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
1274 (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1275 ""
1276 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
1277 [(set_attr "length" "16")])
1279 (define_expand "mulsi3"
1280 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1281 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1282 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1283 ""
1284 "
1285 {
1286 if (TARGET_POWER)
1287 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1288 else
1289 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1290 DONE;
1291 }")
1293 (define_insn "mulsi3_mq"
1294 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1295 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1296 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1297 (clobber (match_scratch:SI 3 "=q,q"))]
1298 "TARGET_POWER"
1299 "@
1300 {muls|mullw} %0,%1,%2
1301 {muli|mulli} %0,%1,%2"
1302 [(set_attr "type" "imul")])
1304 (define_insn "mulsi3_no_mq"
1305 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1306 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1307 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1308 "! TARGET_POWER"
1309 "@
1310 {muls|mullw} %0,%1,%2
1311 {muli|mulli} %0,%1,%2"
1312 [(set_attr "type" "imul")])
1314 (define_insn ""
1315 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1316 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1317 (match_operand:SI 2 "gpc_reg_operand" "r"))
1318 (const_int 0)))
1319 (clobber (match_scratch:SI 3 "=r"))
1320 (clobber (match_scratch:SI 4 "=q"))]
1321 "TARGET_POWER"
1322 "{muls.|mullw.} %3,%1,%2"
1323 [(set_attr "type" "delayed_compare")])
1325 (define_insn ""
1326 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1327 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1328 (match_operand:SI 2 "gpc_reg_operand" "r"))
1329 (const_int 0)))
1330 (clobber (match_scratch:SI 3 "=r"))]
1331 "! TARGET_POWER"
1332 "{muls.|mullw.} %3,%1,%2"
1333 [(set_attr "type" "delayed_compare")])
1335 (define_insn ""
1336 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1337 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1338 (match_operand:SI 2 "gpc_reg_operand" "r"))
1339 (const_int 0)))
1340 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1341 (mult:SI (match_dup 1) (match_dup 2)))
1342 (clobber (match_scratch:SI 4 "=q"))]
1343 "TARGET_POWER"
1344 "{muls.|mullw.} %0,%1,%2"
1345 [(set_attr "type" "delayed_compare")])
1347 (define_insn ""
1348 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1349 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1350 (match_operand:SI 2 "gpc_reg_operand" "r"))
1351 (const_int 0)))
1352 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1353 (mult:SI (match_dup 1) (match_dup 2)))]
1354 "! TARGET_POWER"
1355 "{muls.|mullw.} %0,%1,%2"
1356 [(set_attr "type" "delayed_compare")])
1358 ;; Operand 1 is divided by operand 2; quotient goes to operand
1359 ;; 0 and remainder to operand 3.
1360 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1362 (define_expand "divmodsi4"
1363 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1364 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1365 (match_operand:SI 2 "gpc_reg_operand" "")))
1366 (set (match_operand:SI 3 "gpc_reg_operand" "")
1367 (mod:SI (match_dup 1) (match_dup 2)))])]
1368 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1369 "
1370 {
1371 if (! TARGET_POWER && ! TARGET_POWERPC)
1372 {
1373 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1374 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1375 emit_insn (gen_divss_call ());
1376 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1377 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1378 DONE;
1379 }
1380 }")
1382 (define_insn ""
1383 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1384 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1385 (match_operand:SI 2 "gpc_reg_operand" "r")))
1386 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
1387 (mod:SI (match_dup 1) (match_dup 2)))]
1388 "TARGET_POWER"
1389 "divs %0,%1,%2"
1390 [(set_attr "type" "idiv")])
1392 (define_expand "udivsi3"
1393 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1394 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1395 (match_operand:SI 2 "gpc_reg_operand" "")))]
1396 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1397 "
1398 {
1399 if (! TARGET_POWER && ! TARGET_POWERPC)
1400 {
1401 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1402 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1403 emit_insn (gen_quous_call ());
1404 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1405 DONE;
1406 }
1407 else if (TARGET_POWER)
1408 {
1409 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1410 DONE;
1411 }
1412 }")
1414 (define_insn "udivsi3_mq"
1415 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1416 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1417 (match_operand:SI 2 "gpc_reg_operand" "r")))
1418 (clobber (match_scratch:SI 3 "=q"))]
1419 "TARGET_POWERPC && TARGET_POWER"
1420 "divwu %0,%1,%2"
1421 [(set_attr "type" "idiv")])
1423 (define_insn "*udivsi3_no_mq"
1424 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1425 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1426 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1427 "TARGET_POWERPC && ! TARGET_POWER"
1428 "divwu %0,%1,%2"
1429 [(set_attr "type" "idiv")])
1431 ;; For powers of two we can do srai/aze for divide and then adjust for
1432 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1433 ;; used; for PowerPC, force operands into register and do a normal divide;
1434 ;; for AIX common-mode, use quoss call on register operands.
1435 (define_expand "divsi3"
1436 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1437 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1438 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1439 ""
1440 "
1441 {
1442 if (GET_CODE (operands[2]) == CONST_INT
1443 && exact_log2 (INTVAL (operands[2])) >= 0)
1444 ;
1445 else if (TARGET_POWERPC)
1446 {
1447 operands[2] = force_reg (SImode, operands[2]);
1448 if (TARGET_POWER)
1449 {
1450 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1451 DONE;
1452 }
1453 }
1454 else if (TARGET_POWER)
1455 FAIL;
1456 else
1457 {
1458 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1459 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1460 emit_insn (gen_quoss_call ());
1461 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1462 DONE;
1463 }
1464 }")
1466 (define_insn "divsi3_mq"
1467 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1468 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1469 (match_operand:SI 2 "gpc_reg_operand" "r")))
1470 (clobber (match_scratch:SI 3 "=q"))]
1471 "TARGET_POWERPC && TARGET_POWER"
1472 "divw %0,%1,%2"
1473 [(set_attr "type" "idiv")])
1475 (define_insn "*divsi3_no_mq"
1476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1477 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1478 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1479 "TARGET_POWERPC && ! TARGET_POWER"
1480 "divw %0,%1,%2"
1481 [(set_attr "type" "idiv")])
1483 (define_expand "modsi3"
1484 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1485 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1486 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1487 ""
1488 "
1489 {
1490 int i = exact_log2 (INTVAL (operands[2]));
1491 rtx temp1;
1492 rtx temp2;
1494 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
1495 FAIL;
1497 temp1 = gen_reg_rtx (SImode);
1498 temp2 = gen_reg_rtx (SImode);
1500 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1501 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1502 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1503 DONE;
1504 }")
1506 (define_insn ""
1507 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1508 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1509 (match_operand:SI 2 "const_int_operand" "N")))]
1510 "exact_log2 (INTVAL (operands[2])) >= 0"
1511 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1512 [(set_attr "length" "8")])
1514 (define_insn ""
1515 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1516 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1517 (match_operand:SI 2 "const_int_operand" "N"))
1518 (const_int 0)))
1519 (clobber (match_scratch:SI 3 "=r"))]
1520 "exact_log2 (INTVAL (operands[2])) >= 0"
1521 "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3"
1522 [(set_attr "type" "compare")
1523 (set_attr "length" "8")])
1525 (define_insn ""
1526 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1527 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1528 (match_operand:SI 2 "const_int_operand" "N"))
1529 (const_int 0)))
1530 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1531 (div:SI (match_dup 1) (match_dup 2)))]
1532 "exact_log2 (INTVAL (operands[2])) >= 0"
1533 "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0"
1534 [(set_attr "type" "compare")
1535 (set_attr "length" "8")])
1537 (define_insn ""
1538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1539 (udiv:SI
1540 (plus:DI (ashift:DI
1541 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1542 (const_int 32))
1543 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
1544 (match_operand:SI 3 "gpc_reg_operand" "r")))
1545 (set (match_operand:SI 2 "register_operand" "=*q")
1546 (umod:SI
1547 (plus:DI (ashift:DI
1548 (zero_extend:DI (match_dup 1)) (const_int 32))
1549 (zero_extend:DI (match_dup 4)))
1550 (match_dup 3)))]
1551 "TARGET_POWER"
1552 "div %0,%1,%3"
1553 [(set_attr "type" "idiv")])
1555 ;; To do unsigned divide we handle the cases of the divisor looking like a
1556 ;; negative number. If it is a constant that is less than 2**31, we don't
1557 ;; have to worry about the branches. So make a few subroutines here.
1558 ;;
1559 ;; First comes the normal case.
1560 (define_expand "udivmodsi4_normal"
1561 [(set (match_dup 4) (const_int 0))
1562 (parallel [(set (match_operand:SI 0 "" "")
1563 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1564 (const_int 32))
1565 (zero_extend:DI
1566 (match_operand:SI 1 "" "")))
1567 (match_operand:SI 2 "" "")))
1568 (set (match_operand:SI 3 "" "")
1569 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1570 (const_int 32))
1571 (zero_extend:DI (match_dup 1)))
1572 (match_dup 2)))])]
1573 "TARGET_POWER"
1574 "
1575 { operands[4] = gen_reg_rtx (SImode); }")
1577 ;; This handles the branches.
1578 (define_expand "udivmodsi4_tests"
1579 [(set (match_operand:SI 0 "" "") (const_int 0))
1580 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
1581 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
1582 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
1583 (label_ref (match_operand:SI 4 "" "")) (pc)))
1584 (set (match_dup 0) (const_int 1))
1585 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
1586 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
1587 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
1588 (label_ref (match_dup 4)) (pc)))]
1589 "TARGET_POWER"
1590 "
1591 { operands[5] = gen_reg_rtx (CCUNSmode);
1592 operands[6] = gen_reg_rtx (CCmode);
1593 }")
1595 (define_expand "udivmodsi4"
1596 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1597 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1598 (match_operand:SI 2 "reg_or_cint_operand" "")))
1599 (set (match_operand:SI 3 "gpc_reg_operand" "")
1600 (umod:SI (match_dup 1) (match_dup 2)))])]
1601 ""
1602 "
1603 {
1604 rtx label = 0;
1606 if (! TARGET_POWER)
1607 {
1608 if (! TARGET_POWERPC)
1609 {
1610 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1611 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1612 emit_insn (gen_divus_call ());
1613 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1614 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1615 DONE;
1616 }
1617 else
1618 FAIL;
1619 }
1621 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
1622 {
1623 operands[2] = force_reg (SImode, operands[2]);
1624 label = gen_label_rtx ();
1625 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
1626 operands[3], label));
1627 }
1628 else
1629 operands[2] = force_reg (SImode, operands[2]);
1631 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
1632 operands[3]));
1633 if (label)
1634 emit_label (label);
1636 DONE;
1637 }")
1639 ;; AIX architecture-independent common-mode multiply (DImode),
1640 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
1641 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
1642 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
1643 ;; assumed unused if generating common-mode, so ignore.
1644 (define_insn "mulh_call"
1645 [(set (reg:SI 3)
1646 (truncate:SI
1647 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
1648 (sign_extend:DI (reg:SI 4)))
1649 (const_int 32))))
1650 (clobber (match_scratch:SI 0 "=l"))]
1651 "! TARGET_POWER && ! TARGET_POWERPC"
1652 "bla __mulh"
1653 [(set_attr "type" "imul")])
1655 (define_insn "mull_call"
1656 [(set (reg:DI 3)
1657 (mult:DI (sign_extend:DI (reg:SI 3))
1658 (sign_extend:DI (reg:SI 4))))
1659 (clobber (match_scratch:SI 0 "=l"))
1660 (clobber (reg:SI 0))]
1661 "! TARGET_POWER && ! TARGET_POWERPC"
1662 "bla __mull"
1663 [(set_attr "type" "imul")])
1665 (define_insn "divss_call"
1666 [(set (reg:SI 3)
1667 (div:SI (reg:SI 3) (reg:SI 4)))
1668 (set (reg:SI 4)
1669 (mod:SI (reg:SI 3) (reg:SI 4)))
1670 (clobber (match_scratch:SI 0 "=l"))
1671 (clobber (reg:SI 0))]
1672 "! TARGET_POWER && ! TARGET_POWERPC"
1673 "bla __divss"
1674 [(set_attr "type" "idiv")])
1676 (define_insn "divus_call"
1677 [(set (reg:SI 3)
1678 (udiv:SI (reg:SI 3) (reg:SI 4)))
1679 (set (reg:SI 4)
1680 (umod:SI (reg:SI 3) (reg:SI 4)))
1681 (clobber (match_scratch:SI 0 "=l"))
1682 (clobber (reg:SI 0))
1683 (clobber (match_scratch:CC 1 "=x"))
1684 (clobber (reg:CC 69))]
1685 "! TARGET_POWER && ! TARGET_POWERPC"
1686 "bla __divus"
1687 [(set_attr "type" "idiv")])
1689 (define_insn "quoss_call"
1690 [(set (reg:SI 3)
1691 (div:SI (reg:SI 3) (reg:SI 4)))
1692 (clobber (match_scratch:SI 0 "=l"))]
1693 "! TARGET_POWER && ! TARGET_POWERPC"
1694 "bla __quoss"
1695 [(set_attr "type" "idiv")])
1697 (define_insn "quous_call"
1698 [(set (reg:SI 3)
1699 (udiv:SI (reg:SI 3) (reg:SI 4)))
1700 (clobber (match_scratch:SI 0 "=l"))
1701 (clobber (reg:SI 0))
1702 (clobber (match_scratch:CC 1 "=x"))
1703 (clobber (reg:CC 69))]
1704 "! TARGET_POWER && ! TARGET_POWERPC"
1705 "bla __quous"
1706 [(set_attr "type" "idiv")])
1707 \f
1708 ;; Logical instructions
1709 (define_insn "andsi3"
1710 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1711 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1712 (match_operand:SI 2 "and_operand" "?r,L,K,J")))
1713 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1714 ""
1715 "@
1716 and %0,%1,%2
1717 {rlinm|rlwinm} %0,%1,0,%m2,%M2
1718 {andil.|andi.} %0,%1,%b2
1719 {andiu.|andis.} %0,%1,%u2"
1720 [(set_attr "length" "4,4,4,4")])
1722 (define_insn "*andsi3_internal2"
1723 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
1724 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1725 (match_operand:SI 2 "and_operand" "r,K,J,L"))
1726 (const_int 0)))
1727 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1728 ""
1729 "@
1730 and. %3,%1,%2
1731 {andil.|andi.} %3,%1,%b2
1732 {andiu.|andis.} %3,%1,%u2
1733 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2"
1734 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1736 (define_insn "*andsi3_internal3"
1737 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
1738 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1739 (match_operand:SI 2 "and_operand" "r,K,J,L"))
1740 (const_int 0)))
1741 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1742 (and:SI (match_dup 1) (match_dup 2)))]
1743 ""
1744 "@
1745 and. %0,%1,%2
1746 {andil.|andi.} %0,%1,%b2
1747 {andiu.|andis.} %0,%1,%u2
1748 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2"
1749 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1751 (define_expand "iorsi3"
1752 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1753 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1754 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1755 ""
1756 "
1757 {
1758 if (GET_CODE (operands[2]) == CONST_INT
1759 && !logical_operand (operands[2], SImode))
1760 {
1761 HOST_WIDE_INT value = INTVAL (operands[2]);
1762 rtx tmp = ((reload_in_progress || reload_completed
1763 || rtx_equal_p (operands[0], operands[1]))
1764 ? operands[0] : gen_reg_rtx (SImode));
1766 emit_insn (gen_iorsi3 (tmp, operands[1],
1767 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
1768 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
1769 DONE;
1770 }
1771 }")
1773 (define_insn "*iorsi3_internal1"
1774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1775 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1776 (match_operand:SI 2 "logical_operand" "r,K,J")))]
1777 ""
1778 "@
1779 or %0,%1,%2
1780 {oril|ori} %0,%1,%b2
1781 {oriu|oris} %0,%1,%u2"
1782 [(set_attr "length" "4,4,4")])
1784 (define_insn "*iorsi3_internal2"
1785 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1786 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1787 (match_operand:SI 2 "gpc_reg_operand" "r"))
1788 (const_int 0)))
1789 (clobber (match_scratch:SI 3 "=r"))]
1790 ""
1791 "or. %3,%1,%2"
1792 [(set_attr "type" "compare")])
1794 (define_insn "*iorsi3_internal3"
1795 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1796 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1797 (match_operand:SI 2 "gpc_reg_operand" "r"))
1798 (const_int 0)))
1799 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1800 (ior:SI (match_dup 1) (match_dup 2)))]
1801 ""
1802 "or. %0,%1,%2"
1803 [(set_attr "type" "compare")])
1805 ;; Split an IOR that we can't do in one insn into two insns, each of which
1806 ;; does one 16-bit part. This is used by combine.
1808 (define_split
1809 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1810 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1811 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1812 ""
1813 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
1814 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
1815 "
1816 {
1817 operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
1818 operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
1819 }")
1821 (define_expand "xorsi3"
1822 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1823 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1824 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1825 ""
1826 "
1827 {
1828 if (GET_CODE (operands[2]) == CONST_INT
1829 && !logical_operand (operands[2], SImode))
1830 {
1831 HOST_WIDE_INT value = INTVAL (operands[2]);
1832 rtx tmp = ((reload_in_progress || reload_completed
1833 || rtx_equal_p (operands[0], operands[1]))
1834 ? operands[0] : gen_reg_rtx (SImode));
1836 emit_insn (gen_xorsi3 (tmp, operands[1],
1837 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
1838 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
1839 DONE;
1840 }
1841 }")
1843 (define_insn "*xorsi3_internal1"
1844 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1845 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1846 (match_operand:SI 2 "logical_operand" "r,K,J")))]
1847 ""
1848 "@
1849 xor %0,%1,%2
1850 {xoril|xori} %0,%1,%b2
1851 {xoriu|xoris} %0,%1,%u2"
1852 [(set_attr "length" "4,4,4")])
1854 (define_insn "*xorsi3_internal2"
1855 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1856 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1857 (match_operand:SI 2 "gpc_reg_operand" "r"))
1858 (const_int 0)))
1859 (clobber (match_scratch:SI 3 "=r"))]
1860 ""
1861 "xor. %3,%1,%2"
1862 [(set_attr "type" "compare")])
1864 (define_insn "*xorsi3_internal3"
1865 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1866 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1867 (match_operand:SI 2 "gpc_reg_operand" "r"))
1868 (const_int 0)))
1869 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1870 (xor:SI (match_dup 1) (match_dup 2)))]
1871 ""
1872 "xor. %0,%1,%2"
1873 [(set_attr "type" "compare")])
1875 ;; Split an XOR that we can't do in one insn into two insns, each of which
1876 ;; does one 16-bit part. This is used by combine.
1878 (define_split
1879 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1880 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1881 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1882 ""
1883 [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
1884 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
1885 "
1886 {
1887 operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
1888 operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
1889 }")
1891 (define_insn "*eqvsi3_internal1"
1892 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1893 (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1894 (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1895 ""
1896 "eqv %0,%1,%2")
1898 (define_insn "*eqvsi3_internal2"
1899 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1900 (compare:CC (not:SI
1901 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1902 (match_operand:SI 2 "gpc_reg_operand" "r")))
1903 (const_int 0)))
1904 (clobber (match_scratch:SI 3 "=r"))]
1905 ""
1906 "eqv. %3,%1,%2"
1907 [(set_attr "type" "compare")])
1909 (define_insn "*eqvsi3_internal3"
1910 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1911 (compare:CC (not:SI
1912 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1913 (match_operand:SI 2 "gpc_reg_operand" "r")))
1914 (const_int 0)))
1915 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1916 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
1917 ""
1918 "eqv. %0,%1,%2"
1919 [(set_attr "type" "compare")])
1921 (define_insn "*andcsi3_internal1"
1922 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1923 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1924 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1925 ""
1926 "andc %0,%2,%1")
1928 (define_insn "*andcsi3_internal2"
1929 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1930 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1931 (match_operand:SI 2 "gpc_reg_operand" "r"))
1932 (const_int 0)))
1933 (clobber (match_scratch:SI 3 "=r"))]
1934 ""
1935 "andc. %3,%2,%1"
1936 [(set_attr "type" "compare")])
1938 (define_insn "*andcsi3_internal3"
1939 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1940 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1941 (match_operand:SI 2 "gpc_reg_operand" "r"))
1942 (const_int 0)))
1943 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1944 (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
1945 ""
1946 "andc. %0,%2,%1"
1947 [(set_attr "type" "compare")])
1949 (define_insn "*iorcsi3_internal1"
1950 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1951 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1952 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1953 ""
1954 "orc %0,%2,%1")
1956 (define_insn "*iorcsi3_internal2"
1957 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1958 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1959 (match_operand:SI 2 "gpc_reg_operand" "r"))
1960 (const_int 0)))
1961 (clobber (match_scratch:SI 3 "=r"))]
1962 ""
1963 "orc. %3,%2,%1"
1964 [(set_attr "type" "compare")])
1966 (define_insn "*iorcsi3_internal3"
1967 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1968 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1969 (match_operand:SI 2 "gpc_reg_operand" "r"))
1970 (const_int 0)))
1971 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1972 (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
1973 ""
1974 "orc. %0,%2,%1"
1975 [(set_attr "type" "compare")])
1977 (define_insn "*nandsi3_internal1"
1978 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1979 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1980 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1981 ""
1982 "nand %0,%1,%2")
1984 (define_insn "*nandsi3_internal2"
1985 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1986 (compare:CC
1987 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1988 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1989 (const_int 0)))
1990 (clobber (match_scratch:SI 3 "=r"))]
1991 ""
1992 "nand. %3,%1,%2"
1993 [(set_attr "type" "compare")])
1995 (define_insn "*nandsi3_internal3"
1996 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1997 (compare:CC
1998 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1999 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
2000 (const_int 0)))
2001 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2002 (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
2003 ""
2004 "nand. %0,%1,%2"
2005 [(set_attr "type" "compare")])
2007 (define_insn "*norsi3_internal1"
2008 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2009 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
2010 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
2011 ""
2012 "nor %0,%1,%2")
2014 (define_insn "*norsi3_internal2"
2015 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2016 (compare:CC
2017 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
2018 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
2019 (const_int 0)))
2020 (clobber (match_scratch:SI 3 "=r"))]
2021 ""
2022 "nor. %3,%1,%2"
2023 [(set_attr "type" "compare")])
2025 (define_insn "*norsi3_internal3"
2026 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2027 (compare:CC
2028 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
2029 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
2030 (const_int 0)))
2031 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2032 (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
2033 ""
2034 "nor. %0,%1,%2"
2035 [(set_attr "type" "compare")])
2037 ;; maskir insn. We need four forms because things might be in arbitrary
2038 ;; orders. Don't define forms that only set CR fields because these
2039 ;; would modify an input register.
2041 (define_insn "*maskir_internal1"
2042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2043 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2044 (match_operand:SI 1 "gpc_reg_operand" "0"))
2045 (and:SI (match_dup 2)
2046 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2047 "TARGET_POWER"
2048 "maskir %0,%3,%2")
2050 (define_insn "*maskir_internal2"
2051 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2052 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2053 (match_operand:SI 1 "gpc_reg_operand" "0"))
2054 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2055 (match_dup 2))))]
2056 "TARGET_POWER"
2057 "maskir %0,%3,%2")
2059 (define_insn "*maskir_internal3"
2060 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2061 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2062 (match_operand:SI 3 "gpc_reg_operand" "r"))
2063 (and:SI (not:SI (match_dup 2))
2064 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2065 "TARGET_POWER"
2066 "maskir %0,%3,%2")
2068 (define_insn "*maskir_internal4"
2069 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2070 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2071 (match_operand:SI 2 "gpc_reg_operand" "r"))
2072 (and:SI (not:SI (match_dup 2))
2073 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2074 "TARGET_POWER"
2075 "maskir %0,%3,%2")
2077 (define_insn "*maskir_internal5"
2078 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2079 (compare:CC
2080 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2081 (match_operand:SI 1 "gpc_reg_operand" "0"))
2082 (and:SI (match_dup 2)
2083 (match_operand:SI 3 "gpc_reg_operand" "r")))
2084 (const_int 0)))
2085 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2086 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2087 (and:SI (match_dup 2) (match_dup 3))))]
2088 "TARGET_POWER"
2089 "maskir. %0,%3,%2"
2090 [(set_attr "type" "compare")])
2092 (define_insn "*maskir_internal6"
2093 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2094 (compare:CC
2095 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2096 (match_operand:SI 1 "gpc_reg_operand" "0"))
2097 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2098 (match_dup 2)))
2099 (const_int 0)))
2100 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2101 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2102 (and:SI (match_dup 3) (match_dup 2))))]
2103 "TARGET_POWER"
2104 "maskir. %0,%3,%2"
2105 [(set_attr "type" "compare")])
2107 (define_insn "*maskir_internal7"
2108 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2109 (compare:CC
2110 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2111 (match_operand:SI 3 "gpc_reg_operand" "r"))
2112 (and:SI (not:SI (match_dup 2))
2113 (match_operand:SI 1 "gpc_reg_operand" "0")))
2114 (const_int 0)))
2115 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2116 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2117 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2118 "TARGET_POWER"
2119 "maskir. %0,%3,%2"
2120 [(set_attr "type" "compare")])
2122 (define_insn "*maskir_internal8"
2123 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2124 (compare:CC
2125 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2126 (match_operand:SI 2 "gpc_reg_operand" "r"))
2127 (and:SI (not:SI (match_dup 2))
2128 (match_operand:SI 1 "gpc_reg_operand" "0")))
2129 (const_int 0)))
2130 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2131 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2132 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2133 "TARGET_POWER"
2134 "maskir. %0,%3,%2"
2135 [(set_attr "type" "compare")])
2136 \f
2137 ;; Rotate and shift insns, in all their variants. These support shifts,
2138 ;; field inserts and extracts, and various combinations thereof.
2139 (define_expand "insv"
2140 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2141 (match_operand:SI 1 "const_int_operand" "i")
2142 (match_operand:SI 2 "const_int_operand" "i"))
2143 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2144 ""
2145 "
2146 {
2147 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2148 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2149 compiler if the address of the structure is taken later. */
2150 if (GET_CODE (operands[0]) == SUBREG
2151 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
2152 < UNITS_PER_WORD))
2153 FAIL;
2154 }")
2156 (define_insn ""
2157 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2158 (match_operand:SI 1 "const_int_operand" "i")
2159 (match_operand:SI 2 "const_int_operand" "i"))
2160 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2161 ""
2162 "*
2163 {
2164 int start = INTVAL (operands[2]) & 31;
2165 int size = INTVAL (operands[1]) & 31;
2167 operands[4] = GEN_INT (32 - start - size);
2168 operands[1] = GEN_INT (start + size - 1);
2169 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2170 }")
2172 (define_insn ""
2173 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2174 (match_operand:SI 1 "const_int_operand" "i")
2175 (match_operand:SI 2 "const_int_operand" "i"))
2176 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2177 (match_operand:SI 4 "const_int_operand" "i")))]
2178 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2179 "*
2180 {
2181 int shift = INTVAL (operands[4]) & 31;
2182 int start = INTVAL (operands[2]) & 31;
2183 int size = INTVAL (operands[1]) & 31;
2185 operands[4] = GEN_INT (shift - start - size);
2186 operands[1] = GEN_INT (start + size - 1);
2187 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2188 }")
2190 (define_insn ""
2191 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2192 (match_operand:SI 1 "const_int_operand" "i")
2193 (match_operand:SI 2 "const_int_operand" "i"))
2194 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2195 (match_operand:SI 4 "const_int_operand" "i")))]
2196 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2197 "*
2198 {
2199 int shift = INTVAL (operands[4]) & 31;
2200 int start = INTVAL (operands[2]) & 31;
2201 int size = INTVAL (operands[1]) & 31;
2203 operands[4] = GEN_INT (32 - shift - start - size);
2204 operands[1] = GEN_INT (start + size - 1);
2205 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2206 }")
2208 (define_insn ""
2209 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2210 (match_operand:SI 1 "const_int_operand" "i")
2211 (match_operand:SI 2 "const_int_operand" "i"))
2212 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2213 (match_operand:SI 4 "const_int_operand" "i")))]
2214 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2215 "*
2216 {
2217 int shift = INTVAL (operands[4]) & 31;
2218 int start = INTVAL (operands[2]) & 31;
2219 int size = INTVAL (operands[1]) & 31;
2221 operands[4] = GEN_INT (32 - shift - start - size);
2222 operands[1] = GEN_INT (start + size - 1);
2223 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2224 }")
2226 (define_insn ""
2227 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2228 (match_operand:SI 1 "const_int_operand" "i")
2229 (match_operand:SI 2 "const_int_operand" "i"))
2230 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2231 (match_operand:SI 4 "const_int_operand" "i")
2232 (match_operand:SI 5 "const_int_operand" "i")))]
2233 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2234 "*
2235 {
2236 int extract_start = INTVAL (operands[5]) & 31;
2237 int extract_size = INTVAL (operands[4]) & 31;
2238 int insert_start = INTVAL (operands[2]) & 31;
2239 int insert_size = INTVAL (operands[1]) & 31;
2241 /* Align extract field with insert field */
2242 operands[5] = GEN_INT (extract_start + extract_size
2243 - insert_start - insert_size);
2244 operands[1] = GEN_INT (insert_start + insert_size - 1);
2245 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
2246 }")
2248 (define_insn ""
2249 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
2250 (match_operand:DI 1 "const_int_operand" "i")
2251 (match_operand:DI 2 "const_int_operand" "i"))
2252 (match_operand:DI 3 "gpc_reg_operand" "r"))]
2253 "TARGET_POWERPC64"
2254 "*
2255 {
2256 int start = INTVAL (operands[2]) & 63;
2257 int size = INTVAL (operands[1]) & 63;
2259 operands[2] = GEN_INT (64 - start - size);
2260 return \"rldimi %0,%3,%H2,%H1\";
2261 }")
2263 (define_expand "extzv"
2264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2265 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2266 (match_operand:SI 2 "const_int_operand" "i")
2267 (match_operand:SI 3 "const_int_operand" "i")))]
2268 ""
2269 "
2270 {
2271 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2272 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2273 compiler if the address of the structure is taken later. */
2274 if (GET_CODE (operands[0]) == SUBREG
2275 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
2276 < UNITS_PER_WORD))
2277 FAIL;
2278 }")
2280 (define_insn ""
2281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2282 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2283 (match_operand:SI 2 "const_int_operand" "i")
2284 (match_operand:SI 3 "const_int_operand" "i")))]
2285 ""
2286 "*
2287 {
2288 int start = INTVAL (operands[3]) & 31;
2289 int size = INTVAL (operands[2]) & 31;
2291 if (start + size >= 32)
2292 operands[3] = const0_rtx;
2293 else
2294 operands[3] = GEN_INT (start + size);
2295 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
2296 }")
2298 (define_insn ""
2299 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2300 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2301 (match_operand:SI 2 "const_int_operand" "i")
2302 (match_operand:SI 3 "const_int_operand" "i"))
2303 (const_int 0)))
2304 (clobber (match_scratch:SI 4 "=r"))]
2305 ""
2306 "*
2307 {
2308 int start = INTVAL (operands[3]) & 31;
2309 int size = INTVAL (operands[2]) & 31;
2311 /* If the bitfield being tested fits in the upper or lower half of a
2312 word, it is possible to use andiu. or andil. to test it. This is
2313 useful because the condition register set-use delay is smaller for
2314 andi[ul]. than for rlinm. This doesn't work when the starting bit
2315 position is 0 because the LT and GT bits may be set wrong. */
2317 if ((start > 0 && start + size <= 16) || start >= 16)
2318 {
2319 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
2320 - (1 << (16 - (start & 15) - size))));
2321 if (start < 16)
2322 return \"{andiu.|andis.} %4,%1,%3\";
2323 else
2324 return \"{andil.|andi.} %4,%1,%3\";
2325 }
2327 if (start + size >= 32)
2328 operands[3] = const0_rtx;
2329 else
2330 operands[3] = GEN_INT (start + size);
2331 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
2332 }"
2333 [(set_attr "type" "compare")])
2335 (define_insn ""
2336 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2337 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2338 (match_operand:SI 2 "const_int_operand" "i")
2339 (match_operand:SI 3 "const_int_operand" "i"))
2340 (const_int 0)))
2341 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2342 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
2343 ""
2344 "*
2345 {
2346 int start = INTVAL (operands[3]) & 31;
2347 int size = INTVAL (operands[2]) & 31;
2349 if (start >= 16 && start + size == 32)
2350 {
2351 operands[3] = GEN_INT ((1 << (32 - start)) - 1);
2352 return \"{andil.|andi.} %0,%1,%3\";
2353 }
2355 if (start + size >= 32)
2356 operands[3] = const0_rtx;
2357 else
2358 operands[3] = GEN_INT (start + size);
2359 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
2360 }"
2361 [(set_attr "type" "delayed_compare")])
2363 (define_insn ""
2364 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2365 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2366 (match_operand:DI 2 "const_int_operand" "i")
2367 (match_operand:DI 3 "const_int_operand" "i")))]
2368 "TARGET_POWERPC64"
2369 "*
2370 {
2371 int start = INTVAL (operands[3]) & 63;
2372 int size = INTVAL (operands[2]) & 63;
2374 if (start + size >= 64)
2375 operands[3] = const0_rtx;
2376 else
2377 operands[3] = GEN_INT (start + size);
2378 operands[2] = GEN_INT (64 - size);
2379 return \"rldicl %0,%1,%3,%2\";
2380 }")
2382 (define_insn ""
2383 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
2384 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2385 (match_operand:DI 2 "const_int_operand" "i")
2386 (match_operand:DI 3 "const_int_operand" "i"))
2387 (const_int 0)))
2388 (clobber (match_scratch:DI 4 "=r"))]
2389 "TARGET_POWERPC64"
2390 "*
2391 {
2392 int start = INTVAL (operands[3]) & 63;
2393 int size = INTVAL (operands[2]) & 63;
2395 if (start + size >= 64)
2396 operands[3] = const0_rtx;
2397 else
2398 operands[3] = GEN_INT (start + size);
2399 operands[2] = GEN_INT (64 - size);
2400 return \"rldicl. %4,%1,%3,%2\";
2401 }")
2403 (define_insn ""
2404 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
2405 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2406 (match_operand:DI 2 "const_int_operand" "i")
2407 (match_operand:DI 3 "const_int_operand" "i"))
2408 (const_int 0)))
2409 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
2410 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
2411 "TARGET_POWERPC64"
2412 "*
2413 {
2414 int start = INTVAL (operands[3]) & 63;
2415 int size = INTVAL (operands[2]) & 63;
2417 if (start + size >= 64)
2418 operands[3] = const0_rtx;
2419 else
2420 operands[3] = GEN_INT (start + size);
2421 operands[2] = GEN_INT (64 - size);
2422 return \"rldicl. %0,%1,%3,%2\";
2423 }")
2425 (define_insn "rotlsi3"
2426 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2427 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2428 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2429 ""
2430 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
2432 (define_insn "*rotlsi3_internal2"
2433 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2434 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2435 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2436 (const_int 0)))
2437 (clobber (match_scratch:SI 3 "=r"))]
2438 ""
2439 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff"
2440 [(set_attr "type" "delayed_compare")])
2442 (define_insn "*rotlsi3_internal3"
2443 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2444 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2445 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2446 (const_int 0)))
2447 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2448 (rotate:SI (match_dup 1) (match_dup 2)))]
2449 ""
2450 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff"
2451 [(set_attr "type" "delayed_compare")])
2453 (define_insn "*rotlsi3_internal4"
2454 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2455 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2456 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2457 (match_operand:SI 3 "mask_operand" "L")))]
2458 ""
2459 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
2461 (define_insn "*rotlsi3_internal5"
2462 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2463 (compare:CC
2464 (and:SI
2465 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2466 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2467 (match_operand:SI 3 "mask_operand" "L"))
2468 (const_int 0)))
2469 (clobber (match_scratch:SI 4 "=r"))]
2470 ""
2471 "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3"
2472 [(set_attr "type" "delayed_compare")])
2474 (define_insn "*rotlsi3_internal6"
2475 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2476 (compare:CC
2477 (and:SI
2478 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2479 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2480 (match_operand:SI 3 "mask_operand" "L"))
2481 (const_int 0)))
2482 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2483 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2484 ""
2485 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3"
2486 [(set_attr "type" "delayed_compare")])
2488 (define_insn "*rotlsi3_internal7"
2489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2490 (zero_extend:SI
2491 (subreg:QI
2492 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2493 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
2494 ""
2495 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
2497 (define_insn "*rotlsi3_internal8"
2498 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2499 (compare:CC
2500 (zero_extend:SI
2501 (subreg:QI
2502 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2503 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2504 (const_int 0)))
2505 (clobber (match_scratch:SI 3 "=r"))]
2506 ""
2507 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff"
2508 [(set_attr "type" "delayed_compare")])
2510 (define_insn "*rotlsi3_internal9"
2511 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2512 (compare:CC
2513 (zero_extend:SI
2514 (subreg:QI
2515 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2516 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2517 (const_int 0)))
2518 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2519 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1)
2520 (match_dup 2)) 0)))]
2521 ""
2522 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff"
2523 [(set_attr "type" "delayed_compare")])
2525 (define_insn "*rotlsi3_internal10"
2526 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2527 (zero_extend:SI
2528 (subreg:HI
2529 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2530 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
2531 ""
2532 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
2534 (define_insn "*rotlsi3_internal11"
2535 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2536 (compare:CC
2537 (zero_extend:SI
2538 (subreg:HI
2539 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2540 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2541 (const_int 0)))
2542 (clobber (match_scratch:SI 3 "=r"))]
2543 ""
2544 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff"
2545 [(set_attr "type" "delayed_compare")])
2547 (define_insn "*rotlsi3_internal12"
2548 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2549 (compare:CC
2550 (zero_extend:SI
2551 (subreg:HI
2552 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2553 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2554 (const_int 0)))
2555 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2556 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1)
2557 (match_dup 2)) 0)))]
2558 ""
2559 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff"
2560 [(set_attr "type" "delayed_compare")])
2562 ;; Note that we use "sle." instead of "sl." so that we can set
2563 ;; SHIFT_COUNT_TRUNCATED.
2565 (define_expand "ashlsi3"
2566 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2567 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2568 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2569 ""
2570 "
2571 {
2572 if (TARGET_POWER)
2573 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
2574 else
2575 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
2576 DONE;
2577 }")
2579 (define_insn "ashlsi3_power"
2580 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2581 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2582 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2583 (clobber (match_scratch:SI 3 "=q,X"))]
2584 "TARGET_POWER"
2585 "@
2586 sle %0,%1,%2
2587 {sli|slwi} %0,%1,%h2"
2588 [(set_attr "length" "8")])
2590 (define_insn "ashlsi3_no_power"
2591 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2592 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2593 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2594 "! TARGET_POWER"
2595 "{sl|slw}%I2 %0,%1,%h2"
2596 [(set_attr "length" "8")])
2598 (define_insn ""
2599 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2600 (compare:CC
2601 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2602 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2603 (const_int 0)))
2604 (clobber (match_scratch:SI 3 "=r,r"))
2605 (clobber (match_scratch:SI 4 "=q,X"))]
2606 "TARGET_POWER"
2607 "@
2608 sle. %3,%1,%2
2609 {sli.|slwi.} %3,%1,%h2"
2610 [(set_attr "type" "delayed_compare")])
2612 (define_insn ""
2613 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2614 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2615 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2616 (const_int 0)))
2617 (clobber (match_scratch:SI 3 "=r"))]
2618 "! TARGET_POWER"
2619 "{sl|slw}%I2. %3,%1,%h2"
2620 [(set_attr "type" "delayed_compare")])
2622 (define_insn ""
2623 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2624 (compare:CC
2625 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2626 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2627 (const_int 0)))
2628 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2629 (ashift:SI (match_dup 1) (match_dup 2)))
2630 (clobber (match_scratch:SI 4 "=q,X"))]
2631 "TARGET_POWER"
2632 "@
2633 sle. %0,%1,%2
2634 {sli.|slwi.} %0,%1,%h2"
2635 [(set_attr "type" "delayed_compare")])
2637 (define_insn ""
2638 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2639 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2640 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2641 (const_int 0)))
2642 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2643 (ashift:SI (match_dup 1) (match_dup 2)))]
2644 "! TARGET_POWER"
2645 "{sl|slw}%I2. %0,%1,%h2"
2646 [(set_attr "type" "delayed_compare")])
2648 (define_insn ""
2649 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2650 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2651 (match_operand:SI 2 "const_int_operand" "i"))
2652 (match_operand:SI 3 "mask_operand" "L")))]
2653 "includes_lshift_p (operands[2], operands[3])"
2654 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
2656 (define_insn ""
2657 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2658 (compare:CC
2659 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2660 (match_operand:SI 2 "const_int_operand" "i"))
2661 (match_operand:SI 3 "mask_operand" "L"))
2662 (const_int 0)))
2663 (clobber (match_scratch:SI 4 "=r"))]
2664 "includes_lshift_p (operands[2], operands[3])"
2665 "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3"
2666 [(set_attr "type" "delayed_compare")])
2668 (define_insn ""
2669 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2670 (compare:CC
2671 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2672 (match_operand:SI 2 "const_int_operand" "i"))
2673 (match_operand:SI 3 "mask_operand" "L"))
2674 (const_int 0)))
2675 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2676 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2677 "includes_lshift_p (operands[2], operands[3])"
2678 "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3"
2679 [(set_attr "type" "delayed_compare")])
2681 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
2682 ;; "sli x,x,0".
2683 (define_expand "lshrsi3"
2684 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2685 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2686 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2687 ""
2688 "
2689 {
2690 if (TARGET_POWER)
2691 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
2692 else
2693 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
2694 DONE;
2695 }")
2697 (define_insn "lshrsi3_power"
2698 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2699 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
2700 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
2701 (clobber (match_scratch:SI 3 "=q,X,X"))]
2702 "TARGET_POWER"
2703 "@
2704 sre %0,%1,%2
2705 mr %0,%1
2706 {s%A2i|s%A2wi} %0,%1,%h2")
2708 (define_insn "lshrsi3_no_power"
2709 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2710 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2711 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
2712 "! TARGET_POWER"
2713 "@
2714 mr %0,%1
2715 {sr|srw}%I2 %0,%1,%h2")
2717 (define_insn ""
2718 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x")
2719 (compare:CC
2720 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
2721 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))
2722 (const_int 0)))
2723 (clobber (match_scratch:SI 3 "=r,X,r"))
2724 (clobber (match_scratch:SI 4 "=q,X,X"))]
2725 "TARGET_POWER"
2726 "@
2727 sre. %3,%1,%2
2728 mr. %1,%1
2729 {s%A2i.|s%A2wi.} %3,%1,%h2"
2730 [(set_attr "type" "delayed_compare")])
2732 (define_insn ""
2733 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2734 (compare:CC
2735 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2736 (match_operand:SI 2 "reg_or_cint_operand" "O,ri"))
2737 (const_int 0)))
2738 (clobber (match_scratch:SI 3 "=X,r"))]
2739 "! TARGET_POWER"
2740 "@
2741 mr. %1,%1
2742 {sr|srw}%I2. %3,%1,%h2"
2743 [(set_attr "type" "delayed_compare")])
2745 (define_insn ""
2746 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x")
2747 (compare:CC
2748 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
2749 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))
2750 (const_int 0)))
2751 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2752 (lshiftrt:SI (match_dup 1) (match_dup 2)))
2753 (clobber (match_scratch:SI 4 "=q,X,X"))]
2754 "TARGET_POWER"
2755 "@
2756 sre. %0,%1,%2
2757 mr. %0,%1
2758 {s%A2i.|s%A2wi.} %0,%1,%h2"
2759 [(set_attr "type" "delayed_compare")])
2761 (define_insn ""
2762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2763 (compare:CC
2764 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2765 (match_operand:SI 2 "reg_or_cint_operand" "O,ri"))
2766 (const_int 0)))
2767 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2768 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
2769 "! TARGET_POWER"
2770 "@
2771 mr. %0,%1
2772 {sr|srw}%I2. %0,%1,%h2"
2773 [(set_attr "type" "delayed_compare")])
2775 (define_insn ""
2776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2777 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2778 (match_operand:SI 2 "const_int_operand" "i"))
2779 (match_operand:SI 3 "mask_operand" "L")))]
2780 "includes_rshift_p (operands[2], operands[3])"
2781 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
2783 (define_insn ""
2784 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2785 (compare:CC
2786 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2787 (match_operand:SI 2 "const_int_operand" "i"))
2788 (match_operand:SI 3 "mask_operand" "L"))
2789 (const_int 0)))
2790 (clobber (match_scratch:SI 4 "=r"))]
2791 "includes_rshift_p (operands[2], operands[3])"
2792 "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3"
2793 [(set_attr "type" "delayed_compare")])
2795 (define_insn ""
2796 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2797 (compare:CC
2798 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2799 (match_operand:SI 2 "const_int_operand" "i"))
2800 (match_operand:SI 3 "mask_operand" "L"))
2801 (const_int 0)))
2802 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2803 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2804 "includes_rshift_p (operands[2], operands[3])"
2805 "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3"
2806 [(set_attr "type" "delayed_compare")])
2808 (define_insn ""
2809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2810 (zero_extend:SI
2811 (subreg:QI
2812 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2813 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
2814 "includes_rshift_p (operands[2], GEN_INT (255))"
2815 "{rlinm|rlwinm} %0,%1,%s2,0xff")
2817 (define_insn ""
2818 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2819 (compare:CC
2820 (zero_extend:SI
2821 (subreg:QI
2822 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2823 (match_operand:SI 2 "const_int_operand" "i")) 0))
2824 (const_int 0)))
2825 (clobber (match_scratch:SI 3 "=r"))]
2826 "includes_rshift_p (operands[2], GEN_INT (255))"
2827 "{rlinm.|rlwinm.} %3,%1,%s2,0xff"
2828 [(set_attr "type" "delayed_compare")])
2830 (define_insn ""
2831 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2832 (compare:CC
2833 (zero_extend:SI
2834 (subreg:QI
2835 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2836 (match_operand:SI 2 "const_int_operand" "i")) 0))
2837 (const_int 0)))
2838 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2839 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1)
2840 (match_dup 2)) 0)))]
2841 "includes_rshift_p (operands[2], GEN_INT (255))"
2842 "{rlinm.|rlwinm.} %0,%1,%s2,0xff"
2843 [(set_attr "type" "delayed_compare")])
2845 (define_insn ""
2846 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2847 (zero_extend:SI
2848 (subreg:HI
2849 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2850 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
2851 "includes_rshift_p (operands[2], GEN_INT (65535))"
2852 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
2854 (define_insn ""
2855 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2856 (compare:CC
2857 (zero_extend:SI
2858 (subreg:HI
2859 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2860 (match_operand:SI 2 "const_int_operand" "i")) 0))
2861 (const_int 0)))
2862 (clobber (match_scratch:SI 3 "=r"))]
2863 "includes_rshift_p (operands[2], GEN_INT (65535))"
2864 "{rlinm.|rlwinm.} %3,%1,%s2,0xffff"
2865 [(set_attr "type" "delayed_compare")])
2867 (define_insn ""
2868 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2869 (compare:CC
2870 (zero_extend:SI
2871 (subreg:HI
2872 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2873 (match_operand:SI 2 "const_int_operand" "i")) 0))
2874 (const_int 0)))
2875 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2876 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1)
2877 (match_dup 2)) 0)))]
2878 "includes_rshift_p (operands[2], GEN_INT (65535))"
2879 "{rlinm.|rlwinm.} %0,%1,%s2,0xffff"
2880 [(set_attr "type" "delayed_compare")])
2882 (define_insn ""
2883 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2884 (const_int 1)
2885 (match_operand:SI 1 "gpc_reg_operand" "r"))
2886 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2887 (const_int 31)))]
2888 "TARGET_POWER"
2889 "rrib %0,%1,%2")
2891 (define_insn ""
2892 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2893 (const_int 1)
2894 (match_operand:SI 1 "gpc_reg_operand" "r"))
2895 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2896 (const_int 31)))]
2897 "TARGET_POWER"
2898 "rrib %0,%1,%2")
2900 (define_insn ""
2901 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2902 (const_int 1)
2903 (match_operand:SI 1 "gpc_reg_operand" "r"))
2904 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2905 (const_int 1)
2906 (const_int 0)))]
2907 "TARGET_POWER"
2908 "rrib %0,%1,%2")
2910 (define_expand "ashrsi3"
2911 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2912 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
2913 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2914 ""
2915 "
2916 {
2917 if (TARGET_POWER)
2918 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
2919 else
2920 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
2921 DONE;
2922 }")
2924 (define_insn "ashrsi3_power"
2925 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2926 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2927 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2928 (clobber (match_scratch:SI 3 "=q,X"))]
2929 "TARGET_POWER"
2930 "@
2931 srea %0,%1,%2
2932 {srai|srawi} %0,%1,%h2")
2934 (define_insn "ashrsi3_no_power"
2935 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2936 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2937 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2938 "! TARGET_POWER"
2939 "{sra|sraw}%I2 %0,%1,%h2")
2941 (define_insn ""
2942 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2943 (compare:CC
2944 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2945 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2946 (const_int 0)))
2947 (clobber (match_scratch:SI 3 "=r,r"))
2948 (clobber (match_scratch:SI 4 "=q,X"))]
2949 "TARGET_POWER"
2950 "@
2951 srea. %3,%1,%2
2952 {srai.|srawi.} %3,%1,%h2"
2953 [(set_attr "type" "delayed_compare")])
2955 (define_insn ""
2956 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2957 (compare:CC
2958 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2959 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2960 (const_int 0)))
2961 (clobber (match_scratch:SI 3 "=r"))]
2962 "! TARGET_POWER"
2963 "{sra|sraw}%I2. %3,%1,%h2"
2964 [(set_attr "type" "delayed_compare")])
2966 (define_insn ""
2967 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2968 (compare:CC
2969 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2970 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2971 (const_int 0)))
2972 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2973 (ashiftrt:SI (match_dup 1) (match_dup 2)))
2974 (clobber (match_scratch:SI 4 "=q,X"))]
2975 "TARGET_POWER"
2976 "@
2977 srea. %0,%1,%2
2978 {srai.|srawi.} %0,%1,%h2"
2979 [(set_attr "type" "delayed_compare")])
2981 (define_insn ""
2982 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2983 (compare:CC
2984 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2985 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2986 (const_int 0)))
2987 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2988 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
2989 "! TARGET_POWER"
2990 "{sra|sraw}%I2. %0,%1,%h2"
2991 [(set_attr "type" "delayed_compare")])
2992 \f
2993 ;; Floating-point insns, excluding normal data motion.
2994 ;;
2995 ;; PowerPC has a full set of single-precision floating point instructions.
2996 ;;
2997 ;; For the POWER architecture, we pretend that we have both SFmode and
2998 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
2999 ;; The only conversions we will do will be when storing to memory. In that
3000 ;; case, we will use the "frsp" instruction before storing.
3001 ;;
3002 ;; Note that when we store into a single-precision memory location, we need to
3003 ;; use the frsp insn first. If the register being stored isn't dead, we
3004 ;; need a scratch register for the frsp. But this is difficult when the store
3005 ;; is done by reload. It is not incorrect to do the frsp on the register in
3006 ;; this case, we just lose precision that we would have otherwise gotten but
3007 ;; is not guaranteed. Perhaps this should be tightened up at some point.
3009 (define_insn "extendsfdf2"
3010 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3011 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3012 "TARGET_HARD_FLOAT"
3013 "*
3014 {
3015 if (REGNO (operands[0]) == REGNO (operands[1]))
3016 return \"\";
3017 else
3018 return \"fmr %0,%1\";
3019 }"
3020 [(set_attr "type" "fp")])
3022 (define_insn "truncdfsf2"
3023 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3024 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3025 "TARGET_HARD_FLOAT"
3026 "frsp %0,%1"
3027 [(set_attr "type" "fp")])
3029 (define_insn "aux_truncdfsf2"
3030 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3031 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
3032 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3033 "frsp %0,%1"
3034 [(set_attr "type" "fp")])
3036 (define_insn "negsf2"
3037 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3038 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3039 "TARGET_HARD_FLOAT"
3040 "fneg %0,%1"
3041 [(set_attr "type" "fp")])
3043 (define_insn "abssf2"
3044 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3045 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3046 "TARGET_HARD_FLOAT"
3047 "fabs %0,%1"
3048 [(set_attr "type" "fp")])
3050 (define_insn ""
3051 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3052 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
3053 "TARGET_HARD_FLOAT"
3054 "fnabs %0,%1"
3055 [(set_attr "type" "fp")])
3057 (define_expand "addsf3"
3058 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3059 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
3060 (match_operand:SF 2 "gpc_reg_operand" "")))]
3061 "TARGET_HARD_FLOAT"
3062 "")
3064 (define_insn ""
3065 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3066 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3067 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3068 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3069 "fadds %0,%1,%2"
3070 [(set_attr "type" "fp")])
3072 (define_insn ""
3073 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3074 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3075 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3076 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3077 "{fa|fadd} %0,%1,%2"
3078 [(set_attr "type" "fp")])
3080 (define_expand "subsf3"
3081 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3082 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
3083 (match_operand:SF 2 "gpc_reg_operand" "")))]
3084 "TARGET_HARD_FLOAT"
3085 "")
3087 (define_insn ""
3088 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3089 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3090 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3091 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3092 "fsubs %0,%1,%2"
3093 [(set_attr "type" "fp")])
3095 (define_insn ""
3096 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3097 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3098 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3099 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3100 "{fs|fsub} %0,%1,%2"
3101 [(set_attr "type" "fp")])
3103 (define_expand "mulsf3"
3104 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3105 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
3106 (match_operand:SF 2 "gpc_reg_operand" "")))]
3107 "TARGET_HARD_FLOAT"
3108 "")
3110 (define_insn ""
3111 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3112 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3113 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3114 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3115 "fmuls %0,%1,%2"
3116 [(set_attr "type" "fp")])
3118 (define_insn ""
3119 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3120 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3121 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3122 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3123 "{fm|fmul} %0,%1,%2"
3124 [(set_attr "type" "dmul")])
3126 (define_expand "divsf3"
3127 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3128 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
3129 (match_operand:SF 2 "gpc_reg_operand" "")))]
3130 "TARGET_HARD_FLOAT"
3131 "")
3133 (define_insn ""
3134 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3135 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3136 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3137 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3138 "fdivs %0,%1,%2"
3139 [(set_attr "type" "sdiv")])
3141 (define_insn ""
3142 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3143 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3144 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3145 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3146 "{fd|fdiv} %0,%1,%2"
3147 [(set_attr "type" "ddiv")])
3149 (define_insn ""
3150 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3151 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3152 (match_operand:SF 2 "gpc_reg_operand" "f"))
3153 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3154 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3155 "fmadds %0,%1,%2,%3"
3156 [(set_attr "type" "fp")])
3158 (define_insn ""
3159 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3160 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3161 (match_operand:SF 2 "gpc_reg_operand" "f"))
3162 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3163 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3164 "{fma|fmadd} %0,%1,%2,%3"
3165 [(set_attr "type" "dmul")])
3167 (define_insn ""
3168 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3169 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3170 (match_operand:SF 2 "gpc_reg_operand" "f"))
3171 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3172 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3173 "fmsubs %0,%1,%2,%3"
3174 [(set_attr "type" "fp")])
3176 (define_insn ""
3177 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3178 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3179 (match_operand:SF 2 "gpc_reg_operand" "f"))
3180 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3181 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3182 "{fms|fmsub} %0,%1,%2,%3"
3183 [(set_attr "type" "dmul")])
3185 (define_insn ""
3186 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3187 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3188 (match_operand:SF 2 "gpc_reg_operand" "f"))
3189 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3190 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3191 "fnmadds %0,%1,%2,%3"
3192 [(set_attr "type" "fp")])
3194 (define_insn ""
3195 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3196 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3197 (match_operand:SF 2 "gpc_reg_operand" "f"))
3198 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3199 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3200 "{fnma|fnmadd} %0,%1,%2,%3"
3201 [(set_attr "type" "dmul")])
3203 (define_insn ""
3204 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3205 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3206 (match_operand:SF 2 "gpc_reg_operand" "f"))
3207 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3208 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3209 "fnmsubs %0,%1,%2,%3"
3210 [(set_attr "type" "fp")])
3212 (define_insn ""
3213 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3214 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3215 (match_operand:SF 2 "gpc_reg_operand" "f"))
3216 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3217 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3218 "{fnms|fnmsub} %0,%1,%2,%3"
3219 [(set_attr "type" "dmul")])
3221 (define_expand "sqrtsf2"
3222 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3223 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
3224 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3225 "")
3227 (define_insn ""
3228 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3229 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3230 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
3231 "fsqrts %0,%1"
3232 [(set_attr "type" "ssqrt")])
3234 (define_insn ""
3235 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3236 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3237 "TARGET_POWER2 && TARGET_HARD_FLOAT"
3238 "fsqrt %0,%1"
3239 [(set_attr "type" "dsqrt")])
3241 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3242 ;; fsel instruction and some auxiliary computations. Then we just have a
3243 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3244 ;; combine.
3245 (define_expand "maxsf3"
3246 [(set (match_dup 3)
3247 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
3248 (match_operand:SF 2 "gpc_reg_operand" "")))
3249 (set (match_operand:SF 0 "gpc_reg_operand" "")
3250 (if_then_else:SF (ge (match_dup 3)
3251 (const_int 0))
3252 (match_dup 1)
3253 (match_dup 2)))]
3254 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3255 "
3256 { operands[3] = gen_reg_rtx (SFmode); }")
3258 (define_split
3259 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3260 (smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
3261 (match_operand:SF 2 "gpc_reg_operand" "")))
3262 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
3263 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3264 [(set (match_dup 3)
3265 (minus:SF (match_dup 1) (match_dup 2)))
3266 (set (match_dup 0)
3267 (if_then_else:SF (ge (match_dup 3)
3268 (const_int 0))
3269 (match_dup 1)
3270 (match_dup 2)))]
3271 "")
3273 (define_expand "minsf3"
3274 [(set (match_dup 3)
3275 (minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
3276 (match_operand:SF 1 "gpc_reg_operand" "")))
3277 (set (match_operand:SF 0 "gpc_reg_operand" "")
3278 (if_then_else:SF (ge (match_dup 3)
3279 (const_int 0))
3280 (match_dup 1)
3281 (match_dup 2)))]
3282 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3283 "
3284 { operands[3] = gen_reg_rtx (SFmode); }")
3286 (define_split
3287 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3288 (smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
3289 (match_operand:SF 2 "gpc_reg_operand" "")))
3290 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
3291 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3292 [(set (match_dup 3)
3293 (minus:SF (match_dup 2) (match_dup 1)))
3294 (set (match_dup 0)
3295 (if_then_else:SF (ge (match_dup 3)
3296 (const_int 0))
3297 (match_dup 1)
3298 (match_dup 2)))]
3299 "")
3301 (define_expand "movsfcc"
3302 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3303 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3304 (match_operand:SF 2 "gpc_reg_operand" "f")
3305 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3306 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3307 "
3308 {
3309 rtx temp, op0, op1;
3310 enum rtx_code code = GET_CODE (operands[1]);
3311 if (! rs6000_compare_fp_p)
3312 FAIL;
3313 switch (code)
3314 {
3315 case GE: case EQ: case NE:
3316 op0 = rs6000_compare_op0;
3317 op1 = rs6000_compare_op1;
3318 break;
3319 case GT:
3320 op0 = rs6000_compare_op1;
3321 op1 = rs6000_compare_op0;
3322 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3323 break;
3324 case LE:
3325 op0 = rs6000_compare_op1;
3326 op1 = rs6000_compare_op0;
3327 break;
3328 case LT:
3329 op0 = rs6000_compare_op0;
3330 op1 = rs6000_compare_op1;
3331 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3332 break;
3333 default:
3334 FAIL;
3335 }
3336 if (GET_MODE (rs6000_compare_op0) == DFmode)
3337 {
3338 temp = gen_reg_rtx (DFmode);
3339 emit_insn (gen_subdf3 (temp, op0, op1));
3340 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3]));
3341 if (code == EQ)
3342 {
3343 emit_insn (gen_negdf2 (temp, temp));
3344 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0],
3345 operands[3]));
3346 }
3347 else if (code == NE)
3348 {
3349 emit_insn (gen_negdf2 (temp, temp));
3350 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3],
3351 operands[0]));
3352 }
3353 }
3354 else
3355 {
3356 temp = gen_reg_rtx (SFmode);
3357 emit_insn (gen_subsf3 (temp, op0, op1));
3358 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3]));
3359 if (code == EQ)
3360 {
3361 emit_insn (gen_negsf2 (temp, temp));
3362 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0],
3363 operands[3]));
3364 }
3365 else if (code == NE)
3366 {
3367 emit_insn (gen_negsf2 (temp, temp));
3368 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3],
3369 operands[0]));
3370 }
3371 }
3372 DONE;
3373 }")
3375 (define_insn "fselsfsf4"
3376 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3377 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
3378 (const_int 0))
3379 (match_operand:SF 2 "gpc_reg_operand" "f")
3380 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3381 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3382 "fsel %0,%1,%2,%3"
3383 [(set_attr "type" "fp")])
3385 (define_insn "fseldfsf4"
3386 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3387 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
3388 (const_int 0))
3389 (match_operand:SF 2 "gpc_reg_operand" "f")
3390 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3391 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3392 "fsel %0,%1,%2,%3"
3393 [(set_attr "type" "fp")])
3395 (define_insn "negdf2"
3396 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3397 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3398 "TARGET_HARD_FLOAT"
3399 "fneg %0,%1"
3400 [(set_attr "type" "fp")])
3402 (define_insn "absdf2"
3403 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3404 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3405 "TARGET_HARD_FLOAT"
3406 "fabs %0,%1"
3407 [(set_attr "type" "fp")])
3409 (define_insn ""
3410 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3411 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
3412 "TARGET_HARD_FLOAT"
3413 "fnabs %0,%1"
3414 [(set_attr "type" "fp")])
3416 (define_insn "adddf3"
3417 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3418 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3419 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3420 "TARGET_HARD_FLOAT"
3421 "{fa|fadd} %0,%1,%2"
3422 [(set_attr "type" "fp")])
3424 (define_insn "subdf3"
3425 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3426 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3427 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3428 "TARGET_HARD_FLOAT"
3429 "{fs|fsub} %0,%1,%2"
3430 [(set_attr "type" "fp")])
3432 (define_insn "muldf3"
3433 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3434 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3435 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3436 "TARGET_HARD_FLOAT"
3437 "{fm|fmul} %0,%1,%2"
3438 [(set_attr "type" "dmul")])
3440 (define_insn "divdf3"
3441 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3442 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3443 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3444 "TARGET_HARD_FLOAT"
3445 "{fd|fdiv} %0,%1,%2"
3446 [(set_attr "type" "ddiv")])
3448 (define_insn ""
3449 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3450 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3451 (match_operand:DF 2 "gpc_reg_operand" "f"))
3452 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3453 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3454 "{fma|fmadd} %0,%1,%2,%3"
3455 [(set_attr "type" "dmul")])
3457 (define_insn ""
3458 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3459 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3460 (match_operand:DF 2 "gpc_reg_operand" "f"))
3461 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3462 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3463 "{fms|fmsub} %0,%1,%2,%3"
3464 [(set_attr "type" "dmul")])
3466 (define_insn ""
3467 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3468 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3469 (match_operand:DF 2 "gpc_reg_operand" "f"))
3470 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
3471 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3472 "{fnma|fnmadd} %0,%1,%2,%3"
3473 [(set_attr "type" "dmul")])
3475 (define_insn ""
3476 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3477 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3478 (match_operand:DF 2 "gpc_reg_operand" "f"))
3479 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
3480 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
3481 "{fnms|fnmsub} %0,%1,%2,%3"
3482 [(set_attr "type" "dmul")])
3484 (define_insn "sqrtdf2"
3485 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3486 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3487 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3488 "fsqrt %0,%1"
3489 [(set_attr "type" "dsqrt")])
3491 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3492 ;; fsel instruction and some auxiliary computations. Then we just have a
3493 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3494 ;; combine.
3496 (define_expand "maxdf3"
3497 [(set (match_dup 3)
3498 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
3499 (match_operand:DF 2 "gpc_reg_operand" "")))
3500 (set (match_operand:DF 0 "gpc_reg_operand" "")
3501 (if_then_else:DF (ge (match_dup 3)
3502 (const_int 0))
3503 (match_dup 1)
3504 (match_dup 2)))]
3505 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3506 "
3507 { operands[3] = gen_reg_rtx (DFmode); }")
3509 (define_split
3510 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3511 (smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
3512 (match_operand:DF 2 "gpc_reg_operand" "")))
3513 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
3514 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3515 [(set (match_dup 3)
3516 (minus:DF (match_dup 1) (match_dup 2)))
3517 (set (match_dup 0)
3518 (if_then_else:DF (ge (match_dup 3)
3519 (const_int 0))
3520 (match_dup 1)
3521 (match_dup 2)))]
3522 "")
3524 (define_expand "mindf3"
3525 [(set (match_dup 3)
3526 (minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
3527 (match_operand:DF 1 "gpc_reg_operand" "")))
3528 (set (match_operand:DF 0 "gpc_reg_operand" "")
3529 (if_then_else:DF (ge (match_dup 3)
3530 (const_int 0))
3531 (match_dup 1)
3532 (match_dup 2)))]
3533 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3534 "
3535 { operands[3] = gen_reg_rtx (DFmode); }")
3537 (define_split
3538 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3539 (smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
3540 (match_operand:DF 2 "gpc_reg_operand" "")))
3541 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
3542 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3543 [(set (match_dup 3)
3544 (minus:DF (match_dup 2) (match_dup 1)))
3545 (set (match_dup 0)
3546 (if_then_else:DF (ge (match_dup 3)
3547 (const_int 0))
3548 (match_dup 1)
3549 (match_dup 2)))]
3550 "")
3552 (define_expand "movdfcc"
3553 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3554 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3555 (match_operand:DF 2 "gpc_reg_operand" "f")
3556 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3557 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3558 "
3559 {
3560 rtx temp, op0, op1;
3561 enum rtx_code code = GET_CODE (operands[1]);
3562 if (! rs6000_compare_fp_p)
3563 FAIL;
3564 switch (code)
3565 {
3566 case GE: case EQ: case NE:
3567 op0 = rs6000_compare_op0;
3568 op1 = rs6000_compare_op1;
3569 break;
3570 case GT:
3571 op0 = rs6000_compare_op1;
3572 op1 = rs6000_compare_op0;
3573 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3574 break;
3575 case LE:
3576 op0 = rs6000_compare_op1;
3577 op1 = rs6000_compare_op0;
3578 break;
3579 case LT:
3580 op0 = rs6000_compare_op0;
3581 op1 = rs6000_compare_op1;
3582 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3583 break;
3584 default:
3585 FAIL;
3586 }
3587 if (GET_MODE (rs6000_compare_op0) == DFmode)
3588 {
3589 temp = gen_reg_rtx (DFmode);
3590 emit_insn (gen_subdf3 (temp, op0, op1));
3591 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3]));
3592 if (code == EQ)
3593 {
3594 emit_insn (gen_negdf2 (temp, temp));
3595 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0],
3596 operands[3]));
3597 }
3598 else if (code == NE)
3599 {
3600 emit_insn (gen_negdf2 (temp, temp));
3601 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3],
3602 operands[0]));
3603 }
3604 }
3605 else
3606 {
3607 temp = gen_reg_rtx (SFmode);
3608 emit_insn (gen_subsf3 (temp, op0, op1));
3609 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3]));
3610 if (code == EQ)
3611 {
3612 emit_insn (gen_negsf2 (temp, temp));
3613 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0],
3614 operands[3]));
3615 }
3616 else if (code == NE)
3617 {
3618 emit_insn (gen_negsf2 (temp, temp));
3619 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3],
3620 operands[0]));
3621 }
3622 }
3623 DONE;
3624 }")
3626 (define_insn "fseldfdf4"
3627 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3628 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
3629 (const_int 0))
3630 (match_operand:DF 2 "gpc_reg_operand" "f")
3631 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3632 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3633 "fsel %0,%1,%2,%3"
3634 [(set_attr "type" "fp")])
3636 (define_insn "fselsfdf4"
3637 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3638 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
3639 (const_int 0))
3640 (match_operand:DF 2 "gpc_reg_operand" "f")
3641 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3642 "TARGET_PPC_GFXOPT"
3643 "fsel %0,%1,%2,%3"
3644 [(set_attr "type" "fp")])
3645 \f
3646 ;; Conversions to and from floating-point.
3648 (define_expand "floatsidf2"
3649 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
3650 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
3651 (use (match_dup 2))
3652 (use (match_dup 3))
3653 (clobber (match_dup 4))
3654 (clobber (match_dup 5))
3655 (clobber (reg:DF 76))])]
3656 "TARGET_HARD_FLOAT"
3657 "
3658 {
3659 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
3660 operands[3] = force_reg (DFmode,
3661 rs6000_float_const (\"4503601774854144\", DFmode));
3662 operands[4] = gen_reg_rtx (SImode);
3663 operands[5] = gen_reg_rtx (Pmode);
3664 }")
3666 (define_insn "*floatsidf2_internal"
3667 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
3668 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
3669 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
3670 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
3671 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
3672 (clobber (match_operand 5 "gpc_reg_operand" "=b"))
3673 (clobber (reg:DF 76))]
3674 "TARGET_HARD_FLOAT"
3675 "#"
3676 [(set_attr "length" "24")])
3678 (define_split
3679 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3680 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
3681 (use (match_operand:SI 2 "gpc_reg_operand" ""))
3682 (use (match_operand:DF 3 "gpc_reg_operand" ""))
3683 (clobber (match_operand:SI 4 "gpc_reg_operand" ""))
3684 (clobber (match_operand 5 "gpc_reg_operand" ""))
3685 (clobber (reg:DF 76))]
3686 "TARGET_HARD_FLOAT"
3687 [(set (match_dup 4)
3688 (xor:SI (match_dup 1)
3689 (match_dup 6)))
3690 (set (match_dup 5)
3691 (unspec [(const_int 0)] 11))
3692 (set (match_dup 7)
3693 (unspec [(match_dup 4)
3694 (match_dup 5)] 12)) ;; low word
3695 (set (match_dup 7)
3696 (unspec [(match_dup 2)
3697 (match_dup 5)
3698 (match_dup 7)] 13)) ;; high word
3699 (set (match_dup 0)
3700 (unspec [(match_dup 7)
3701 (match_dup 5)] 14))
3702 (set (match_dup 0)
3703 (minus:DF (match_dup 0)
3704 (match_dup 3)))]
3705 "
3706 {
3707 operands[6] = GEN_INT (0x80000000);
3708 operands[7] = gen_rtx_REG (DFmode, FPMEM_REGNUM);
3709 }")
3711 (define_expand "floatunssidf2"
3712 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
3713 (unsigned_float:DF
3714 (match_operand:SI 1 "gpc_reg_operand" "")))
3715 (use (match_dup 2))
3716 (use (match_dup 3))
3717 (clobber (match_dup 4))
3718 (clobber (reg:DF 76))])]
3719 "TARGET_HARD_FLOAT"
3720 "
3721 {
3722 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
3723 operands[3] = force_reg (DFmode,
3724 rs6000_float_const (\"4503599627370496\", DFmode));
3725 operands[4] = gen_reg_rtx (Pmode);
3726 }")
3728 (define_insn "*floatunssidf2_internal"
3729 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
3730 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
3731 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
3732 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
3733 (clobber (match_operand 4 "gpc_reg_operand" "=b"))
3734 (clobber (reg:DF 76))]
3735 "TARGET_HARD_FLOAT"
3736 "#"
3737 [(set_attr "length" "20")])
3739 (define_split
3740 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3741 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
3742 (use (match_operand:SI 2 "gpc_reg_operand" ""))
3743 (use (match_operand:DF 3 "gpc_reg_operand" ""))
3744 (clobber (match_operand 4 "gpc_reg_operand" "=b"))
3745 (clobber (reg:DF 76))]
3746 "TARGET_HARD_FLOAT"
3747 [(set (match_dup 4)
3748 (unspec [(const_int 0)] 11))
3749 (set (match_dup 5)
3750 (unspec [(match_dup 1)
3751 (match_dup 4)] 12)) ;; low word
3752 (set (match_dup 5)
3753 (unspec [(match_dup 2)
3754 (match_dup 4)
3755 (match_dup 5)] 13)) ;; high word
3756 (set (match_dup 0)
3757 (unspec [(match_dup 5)
3758 (reg:SI 1)] 14))
3759 (set (match_dup 0)
3760 (minus:DF (match_dup 0)
3761 (match_dup 3)))]
3762 "operands[5] = gen_rtx_REG (DFmode, FPMEM_REGNUM);")
3764 ;; Load up scratch register with base address + offset if needed
3765 (define_insn "*floatsidf2_loadaddr"
3766 [(set (match_operand 0 "gpc_reg_operand" "=b")
3767 (unspec [(const_int 0)] 11))]
3768 "TARGET_HARD_FLOAT"
3769 "*
3770 {
3771 if (rs6000_fpmem_offset > 32760)
3772 {
3773 rtx xop[3];
3775 xop[0] = operands[0];
3776 xop[1] = (frame_pointer_needed) ? frame_pointer_rtx : stack_pointer_rtx;
3777 xop[2] = GEN_INT ((rs6000_fpmem_offset >> 16)
3778 + ((rs6000_fpmem_offset & 0x8000) >> 15));
3779 output_asm_insn (\"{cau|addis} %0,%1,%2\", xop);
3780 }
3782 return \"\";
3783 }"
3784 [(set_attr "length" "4")])
3786 (define_insn "*floatsidf2_store1"
3787 [(set (reg:DF 76)
3788 (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
3789 (match_operand 1 "gpc_reg_operand" "b")] 12))]
3790 "TARGET_HARD_FLOAT"
3791 "*
3792 {
3793 rtx indx;
3795 if (rs6000_fpmem_offset > 32760)
3796 indx = operands[1];
3797 else if (frame_pointer_needed)
3798 indx = frame_pointer_rtx;
3799 else
3800 indx = stack_pointer_rtx;
3802 operands[2]
3803 = gen_rtx_MEM (SImode,
3804 plus_constant (indx,
3805 (((rs6000_fpmem_offset & 0xffff) ^ 0x8000)
3806 - 0x8000)
3807 + ((WORDS_BIG_ENDIAN != 0) * 4)));
3809 return \"{st|stw} %0,%2\";
3810 }"
3811 [(set_attr "type" "store")])
3813 (define_insn "*floatsidf2_store2"
3814 [(set (reg:DF 76)
3815 (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
3816 (match_operand 1 "gpc_reg_operand" "b")
3817 (reg:DF 76)] 13))]
3818 "TARGET_HARD_FLOAT"
3819 "*
3820 {
3821 rtx indx;
3823 if (rs6000_fpmem_offset > 32760)
3824 indx = operands[1];
3825 else if (frame_pointer_needed)
3826 indx = frame_pointer_rtx;
3827 else
3828 indx = stack_pointer_rtx;
3830 operands[2]
3831 = gen_rtx_MEM (SImode,
3832 plus_constant (indx,
3833 (((rs6000_fpmem_offset & 0xffff) ^ 0x8000)
3834 - 0x8000)
3835 + ((WORDS_BIG_ENDIAN == 0) * 4)));
3837 return \"{st|stw} %0,%2\";
3838 }"
3839 [(set_attr "type" "store")])
3841 (define_insn "*floatsidf2_load"
3842 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3843 (unspec [(reg:DF 76)
3844 (match_operand 1 "gpc_reg_operand" "b")] 14))]
3845 "TARGET_HARD_FLOAT"
3846 "*
3847 {
3848 rtx indx;
3849 HOST_WIDE_INT offset = rs6000_fpmem_offset;
3851 if (rs6000_fpmem_offset > 32760)
3852 {
3853 indx = operands[1];
3854 offset = (((offset & 0xffff) ^ 0x8000) - 0x8000);
3855 }
3856 else if (frame_pointer_needed)
3857 indx = frame_pointer_rtx;
3858 else
3859 indx = stack_pointer_rtx;
3861 operands[2] = gen_rtx_MEM (SImode, plus_constant (indx, offset));
3863 return \"lfd %0,%2\";
3864 }"
3865 [(set_attr "type" "fpload")])
3867 (define_expand "fix_truncdfsi2"
3868 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3869 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
3870 (clobber (match_dup 2))
3871 (clobber (match_dup 3))
3872 (clobber (match_dup 4))])]
3873 "TARGET_HARD_FLOAT"
3874 "
3875 {
3876 if (!TARGET_POWER2 && !TARGET_POWERPC)
3877 {
3878 emit_insn (gen_trunc_call (operands[0], operands[1],
3879 gen_rtx_SYMBOL_REF (Pmode, RS6000_ITRUNC)));
3880 DONE;
3881 }
3883 operands[2] = gen_reg_rtx (DImode);
3884 operands[3] = gen_reg_rtx (Pmode);
3885 operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM);
3886 }")
3888 (define_insn "*fix_truncdfsi2_internal"
3889 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3890 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
3891 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
3892 (clobber (match_operand 3 "gpc_reg_operand" "=b"))
3893 (clobber (reg:DI 76))]
3894 "TARGET_HARD_FLOAT"
3895 "#"
3896 [(set_attr "length" "12")])
3898 (define_split
3899 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3900 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
3901 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
3902 (clobber (match_operand 3 "gpc_reg_operand" ""))
3903 (clobber (reg:DI 76))]
3904 "TARGET_HARD_FLOAT"
3905 [(set (match_dup 2)
3906 (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))))
3907 (set (match_dup 3)
3908 (unspec [(const_int 0)] 11))
3909 (set (match_dup 4)
3910 (unspec [(match_dup 2)
3911 (match_dup 3)] 15))
3912 (set (match_operand:SI 0 "gpc_reg_operand" "")
3913 (unspec [(match_dup 4)
3914 (match_dup 3)] 16))]
3915 "operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM);")
3917 (define_insn "*fix_truncdfsi2_store"
3918 [(set (reg:DI 76)
3919 (unspec [(match_operand:DI 0 "gpc_reg_operand" "f")
3920 (match_operand 1 "gpc_reg_operand" "b")] 15))]
3921 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3922 "*
3923 {
3924 rtx indx;
3926 if (rs6000_fpmem_offset > 32760)
3927 indx = operands[1];
3928 else if (frame_pointer_needed)
3929 indx = frame_pointer_rtx;
3930 else
3931 indx = stack_pointer_rtx;
3933 operands[2] = gen_rtx_MEM (DFmode,
3934 plus_constant (indx,
3935 (((rs6000_fpmem_offset & 0xffff)
3936 ^ 0x8000) - 0x8000)));
3938 return \"stfd %0,%w2\";
3939 }"
3940 [(set_attr "type" "fpstore")])
3942 (define_insn "*fix_truncdfsi2_load"
3943 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3944 (unspec [(reg:DI 76)
3945 (match_operand 1 "gpc_reg_operand" "b")] 16))]
3946 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3947 "*
3948 {
3949 rtx indx;
3951 if (rs6000_fpmem_offset > 32760)
3952 indx = operands[1];
3953 else if (frame_pointer_needed)
3954 indx = frame_pointer_rtx;
3955 else
3956 indx = stack_pointer_rtx;
3958 operands[2]
3959 = gen_rtx_MEM (DFmode,
3960 plus_constant (indx,
3961 (((rs6000_fpmem_offset & 0xffff) ^ 0x8000)
3962 - 0x8000)
3963 + ((WORDS_BIG_ENDIAN) ? 4 : 0)));
3965 return \"{l|lwz} %0,%2\";
3966 }"
3967 [(set_attr "type" "load")])
3969 (define_expand "fixuns_truncdfsi2"
3970 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3971 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
3972 "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT"
3973 "
3974 {
3975 emit_insn (gen_trunc_call (operands[0], operands[1],
3976 gen_rtx_SYMBOL_REF (Pmode, RS6000_UITRUNC)));
3977 DONE;
3978 }")
3980 (define_expand "trunc_call"
3981 [(parallel [(set (match_operand:SI 0 "" "")
3982 (fix:SI (match_operand:DF 1 "" "")))
3983 (use (match_operand:SI 2 "" ""))])]
3984 "TARGET_HARD_FLOAT"
3985 "
3986 {
3987 rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
3988 rtx first = XVECEXP (insns, 0, 0);
3989 rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
3991 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3992 REG_NOTES (first));
3993 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
3995 emit_insn (insns);
3996 DONE;
3997 }")
3999 (define_expand "trunc_call_rtl"
4000 [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
4001 (use (reg:DF 33))
4002 (parallel [(set (reg:SI 3)
4003 (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
4004 (use (const_int 0))
4005 (clobber (scratch:SI))])
4006 (set (match_operand:SI 0 "gpc_reg_operand" "")
4007 (reg:SI 3))]
4008 "TARGET_HARD_FLOAT"
4009 "
4010 {
4011 rs6000_trunc_used = 1;
4012 }")
4014 (define_insn "*fctiwz"
4015 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
4016 (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4017 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
4018 "{fcirz|fctiwz} %0,%1"
4019 [(set_attr "type" "fp")])
4021 (define_insn "floatdidf2"
4022 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4023 (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
4024 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
4025 "fcfid %0,%1"
4026 [(set_attr "type" "fp")])
4028 (define_insn "fix_truncdfdi2"
4029 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
4030 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
4031 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
4032 "fctidz %0,%1"
4033 [(set_attr "type" "fp")])
4034 \f
4035 ;; Define the DImode operations that can be done in a small number
4036 ;; of instructions. The & constraints are to prevent the register
4037 ;; allocator from allocating registers that overlap with the inputs
4038 ;; (for example, having an input in 7,8 and an output in 6,7). We
4039 ;; also allow for the output being the same as one of the inputs.
4041 (define_insn "*adddi3_noppc64"
4042 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
4043 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
4044 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
4045 "! TARGET_POWERPC64"
4046 "*
4047 {
4048 if (WORDS_BIG_ENDIAN)
4049 return (GET_CODE (operands[2])) != CONST_INT
4050 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
4051 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
4052 else
4053 return (GET_CODE (operands[2])) != CONST_INT
4054 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
4055 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
4056 }"
4057 [(set_attr "length" "8")])
4059 (define_insn "*subdi3_noppc64"
4060 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
4061 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
4062 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
4063 "! TARGET_POWERPC64"
4064 "*
4065 {
4066 if (WORDS_BIG_ENDIAN)
4067 return (GET_CODE (operands[1]) != CONST_INT)
4068 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
4069 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
4070 else
4071 return (GET_CODE (operands[1]) != CONST_INT)
4072 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
4073 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
4074 }"
4075 [(set_attr "length" "8")])
4077 (define_insn "*negdi2_noppc64"
4078 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4079 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
4080 "! TARGET_POWERPC64"
4081 "*
4082 {
4083 return (WORDS_BIG_ENDIAN)
4084 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
4085 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
4086 }"
4087 [(set_attr "length" "8")])
4089 (define_expand "mulsidi3"
4090 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4091 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4092 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4093 "! TARGET_POWERPC64"
4094 "
4095 {
4096 if (! TARGET_POWER && ! TARGET_POWERPC)
4097 {
4098 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
4099 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
4100 emit_insn (gen_mull_call ());
4101 if (WORDS_BIG_ENDIAN)
4102 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
4103 else
4104 {
4105 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
4106 gen_rtx_REG (SImode, 3));
4107 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
4108 gen_rtx_REG (SImode, 4));
4109 }
4110 DONE;
4111 }
4112 else if (TARGET_POWER)
4113 {
4114 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
4115 DONE;
4116 }
4117 }")
4119 (define_insn "mulsidi3_mq"
4120 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4121 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4122 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
4123 (clobber (match_scratch:SI 3 "=q"))]
4124 "TARGET_POWER"
4125 "mul %0,%1,%2\;mfmq %L0"
4126 [(set_attr "type" "imul")
4127 (set_attr "length" "8")])
4129 (define_insn "*mulsidi3_no_mq"
4130 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4131 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4132 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
4133 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
4134 "*
4135 {
4136 return (WORDS_BIG_ENDIAN)
4137 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
4138 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
4139 }"
4140 [(set_attr "type" "imul")
4141 (set_attr "length" "8")])
4143 (define_split
4144 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4145 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4146 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4147 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
4148 [(set (match_dup 3)
4149 (truncate:SI
4150 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
4151 (sign_extend:DI (match_dup 2)))
4152 (const_int 32))))
4153 (set (match_dup 4)
4154 (mult:SI (match_dup 1)
4155 (match_dup 2)))]
4156 "
4157 {
4158 int endian = (WORDS_BIG_ENDIAN == 0);
4159 operands[3] = operand_subword (operands[0], endian, 0, DImode);
4160 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
4161 }")
4163 (define_expand "umulsidi3"
4164 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4165 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4166 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4167 "TARGET_POWERPC && ! TARGET_POWERPC64"
4168 "
4169 {
4170 if (TARGET_POWER)
4171 {
4172 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
4173 DONE;
4174 }
4175 }")
4177 (define_insn "umulsidi3_mq"
4178 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4179 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4180 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
4181 (clobber (match_scratch:SI 3 "=q"))]
4182 "TARGET_POWERPC && TARGET_POWER"
4183 "*
4184 {
4185 return (WORDS_BIG_ENDIAN)
4186 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
4187 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
4188 }"
4189 [(set_attr "type" "imul")
4190 (set_attr "length" "8")])
4192 (define_insn "*umulsidi3_no_mq"
4193 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4194 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4195 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
4196 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
4197 "*
4198 {
4199 return (WORDS_BIG_ENDIAN)
4200 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
4201 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
4202 }"
4203 [(set_attr "type" "imul")
4204 (set_attr "length" "8")])
4206 (define_split
4207 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4208 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4209 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4210 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
4211 [(set (match_dup 3)
4212 (truncate:SI
4213 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
4214 (zero_extend:DI (match_dup 2)))
4215 (const_int 32))))
4216 (set (match_dup 4)
4217 (mult:SI (match_dup 1)
4218 (match_dup 2)))]
4219 "
4220 {
4221 int endian = (WORDS_BIG_ENDIAN == 0);
4222 operands[3] = operand_subword (operands[0], endian, 0, DImode);
4223 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
4224 }")
4226 (define_expand "smulsi3_highpart"
4227 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4228 (truncate:SI
4229 (lshiftrt:DI (mult:DI (sign_extend:DI
4230 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4231 (sign_extend:DI
4232 (match_operand:SI 2 "gpc_reg_operand" "r")))
4233 (const_int 32))))]
4234 ""
4235 "
4236 {
4237 if (! TARGET_POWER && ! TARGET_POWERPC)
4238 {
4239 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
4240 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
4241 emit_insn (gen_mulh_call ());
4242 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
4243 DONE;
4244 }
4245 else if (TARGET_POWER)
4246 {
4247 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1],
4248 operands[2]));
4249 DONE;
4250 }
4251 }")
4253 (define_insn "smulsi3_highpart_mq"
4254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4255 (truncate:SI
4256 (lshiftrt:DI (mult:DI (sign_extend:DI
4257 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4258 (sign_extend:DI
4259 (match_operand:SI 2 "gpc_reg_operand" "r")))
4260 (const_int 32))))
4261 (clobber (match_scratch:SI 3 "=q"))]
4262 "TARGET_POWER"
4263 "mul %0,%1,%2"
4264 [(set_attr "type" "imul")])
4266 (define_insn "*smulsi3_highpart_no_mq"
4267 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4268 (truncate:SI
4269 (lshiftrt:DI (mult:DI (sign_extend:DI
4270 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4271 (sign_extend:DI
4272 (match_operand:SI 2 "gpc_reg_operand" "r")))
4273 (const_int 32))))]
4274 "TARGET_POWERPC && ! TARGET_POWER"
4275 "mulhw %0,%1,%2"
4276 [(set_attr "type" "imul")])
4278 (define_expand "umulsi3_highpart"
4279 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4280 (truncate:SI
4281 (lshiftrt:DI (mult:DI (zero_extend:DI
4282 (match_operand:SI 1 "gpc_reg_operand" ""))
4283 (zero_extend:DI
4284 (match_operand:SI 2 "gpc_reg_operand" "")))
4285 (const_int 32))))]
4286 "TARGET_POWERPC"
4287 "
4288 {
4289 if (TARGET_POWER)
4290 {
4291 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
4292 DONE;
4293 }
4294 }")
4296 (define_insn "umulsi3_highpart_mq"
4297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4298 (truncate:SI
4299 (lshiftrt:DI (mult:DI (zero_extend:DI
4300 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4301 (zero_extend:DI
4302 (match_operand:SI 2 "gpc_reg_operand" "r")))
4303 (const_int 32))))
4304 (clobber (match_scratch:SI 3 "=q"))]
4305 "TARGET_POWERPC && TARGET_POWER"
4306 "mulhwu %0,%1,%2"
4307 [(set_attr "type" "imul")])
4309 (define_insn "*umulsi3_highpart_no_mq"
4310 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4311 (truncate:SI
4312 (lshiftrt:DI (mult:DI (zero_extend:DI
4313 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4314 (zero_extend:DI
4315 (match_operand:SI 2 "gpc_reg_operand" "r")))
4316 (const_int 32))))]
4317 "TARGET_POWERPC && ! TARGET_POWER"
4318 "mulhwu %0,%1,%2"
4319 [(set_attr "type" "imul")])
4321 ;; If operands 0 and 2 are in the same register, we have a problem. But
4322 ;; operands 0 and 1 (the usual case) can be in the same register. That's
4323 ;; why we have the strange constraints below.
4324 (define_insn "ashldi3_power"
4325 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
4326 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
4327 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
4328 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
4329 "TARGET_POWER"
4330 "@
4331 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
4332 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
4333 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
4334 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
4335 [(set_attr "length" "8")])
4337 (define_insn "lshrdi3_power"
4338 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
4339 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
4340 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
4341 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
4342 "TARGET_POWER"
4343 "@
4344 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
4345 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
4346 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
4347 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
4348 [(set_attr "length" "8")])
4350 ;; Shift by a variable amount is too complex to be worth open-coding. We
4351 ;; just handle shifts by constants.
4352 (define_insn "ashrdi3_power"
4353 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4354 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
4355 (match_operand:SI 2 "const_int_operand" "M,i")))
4356 (clobber (match_scratch:SI 3 "=X,q"))]
4357 "TARGET_POWER"
4358 "@
4359 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
4360 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
4361 [(set_attr "length" "8")])
4362 \f
4363 ;; PowerPC64 DImode operations.
4365 (define_expand "adddi3"
4366 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4367 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
4368 (match_operand:DI 2 "reg_or_cint_operand" "")))]
4369 ""
4370 "
4371 {
4372 if (! TARGET_POWERPC64)
4373 {
4374 if (non_short_cint_operand (operands[2], DImode))
4375 FAIL;
4376 }
4377 else
4378 if (GET_CODE (operands[2]) == CONST_INT
4379 && !add_operand (operands[2], DImode))
4380 {
4381 rtx tmp = ((reload_in_progress || reload_completed
4382 || rtx_equal_p (operands[0], operands[1]))
4383 ? operands[0] : gen_reg_rtx (DImode));
4385 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
4386 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
4388 if (low & 0x8000)
4389 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
4391 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (high)));
4392 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
4393 DONE;
4394 }
4395 }")
4397 ;; Discourage ai/addic because of carry but provide it in an alternative
4398 ;; allowing register zero as source.
4400 (define_insn "*adddi3_internal1"
4401 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
4402 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
4403 (match_operand:DI 2 "add_operand" "r,I,I,J")))]
4404 "TARGET_POWERPC64"
4405 "@
4406 add %0,%1,%2
4407 addi %0,%1,%2
4408 addic %0,%1,%2
4409 addis %0,%1,%v2")
4411 (define_insn "*adddi3_internal2"
4412 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4413 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
4414 (match_operand:DI 2 "reg_or_short_operand" "r,I"))
4415 (const_int 0)))
4416 (clobber (match_scratch:DI 3 "=r,r"))]
4417 "TARGET_POWERPC64"
4418 "@
4419 add. %3,%1,%2
4420 addic. %3,%1,%2"
4421 [(set_attr "type" "compare")])
4423 (define_insn "*adddi3_internal3"
4424 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
4425 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
4426 (match_operand:DI 2 "reg_or_short_operand" "r,I"))
4427 (const_int 0)))
4428 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4429 (plus:DI (match_dup 1) (match_dup 2)))]
4430 "TARGET_POWERPC64"
4431 "@
4432 add. %0,%1,%2
4433 addic. %0,%1,%2"
4434 [(set_attr "type" "compare")])
4436 ;; Split an add that we can't do in one insn into two insns, each of which
4437 ;; does one 16-bit part. This is used by combine. Note that the low-order
4438 ;; add should be last in case the result gets used in an address.
4440 (define_split
4441 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4442 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
4443 (match_operand:DI 2 "non_add_cint_operand" "")))]
4444 "TARGET_POWERPC64"
4445 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
4446 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
4447 "
4448 {
4449 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
4450 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
4452 if (low & 0x8000)
4453 high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
4455 operands[3] = GEN_INT (high);
4456 operands[4] = GEN_INT (low);
4457 }")
4459 (define_insn "one_cmpldi2"
4460 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4461 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
4462 "TARGET_POWERPC64"
4463 "nor %0,%1,%1")
4465 (define_insn ""
4466 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4467 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4468 (const_int 0)))
4469 (clobber (match_scratch:DI 2 "=r"))]
4470 "TARGET_POWERPC64"
4471 "nor. %2,%1,%1"
4472 [(set_attr "type" "compare")])
4474 (define_insn ""
4475 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4476 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4477 (const_int 0)))
4478 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4479 (not:DI (match_dup 1)))]
4480 "TARGET_POWERPC64"
4481 "nor. %0,%1,%1"
4482 [(set_attr "type" "compare")])
4484 (define_insn ""
4485 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4486 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
4487 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
4488 "TARGET_POWERPC64"
4489 "@
4490 subf %0,%2,%1
4491 subfic %0,%2,%1")
4493 (define_insn ""
4494 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4495 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4496 (match_operand:DI 2 "gpc_reg_operand" "r"))
4497 (const_int 0)))
4498 (clobber (match_scratch:DI 3 "=r"))]
4499 "TARGET_POWERPC64"
4500 "subf. %3,%2,%1"
4501 [(set_attr "type" "compare")])
4503 (define_insn ""
4504 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4505 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4506 (match_operand:DI 2 "gpc_reg_operand" "r"))
4507 (const_int 0)))
4508 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4509 (minus:DI (match_dup 1) (match_dup 2)))]
4510 "TARGET_POWERPC64"
4511 "subf. %0,%2,%1"
4512 [(set_attr "type" "compare")])
4514 (define_expand "subdi3"
4515 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4516 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
4517 (match_operand:DI 2 "reg_or_cint_operand" "")))]
4518 ""
4519 "
4520 {
4521 if (GET_CODE (operands[2]) == CONST_INT)
4522 {
4523 emit_insn (gen_adddi3 (operands[0], operands[1],
4524 negate_rtx (DImode, operands[2])));
4525 DONE;
4526 }
4527 }")
4529 (define_insn "absdi2"
4530 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4531 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
4532 (clobber (match_scratch:DI 2 "=&r,&r"))]
4533 "TARGET_POWERPC64"
4534 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0"
4535 [(set_attr "length" "12")])
4537 (define_split
4538 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4539 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
4540 (clobber (match_scratch:DI 2 "=&r,&r"))]
4541 "TARGET_POWERPC64 && reload_completed"
4542 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
4543 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
4544 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
4545 "")
4547 (define_insn ""
4548 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4549 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
4550 (clobber (match_scratch:DI 2 "=&r,&r"))]
4551 "TARGET_POWERPC64"
4552 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2"
4553 [(set_attr "length" "12")])
4555 (define_split
4556 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4557 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
4558 (clobber (match_scratch:DI 2 "=&r,&r"))]
4559 "TARGET_POWERPC64 && reload_completed"
4560 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
4561 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
4562 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
4563 "")
4565 (define_expand "negdi2"
4566 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4567 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
4568 ""
4569 "")
4571 (define_insn ""
4572 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4573 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
4574 "TARGET_POWERPC64"
4575 "neg %0,%1")
4577 (define_insn ""
4578 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4579 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4580 (const_int 0)))
4581 (clobber (match_scratch:DI 2 "=r"))]
4582 "TARGET_POWERPC64"
4583 "neg. %2,%1"
4584 [(set_attr "type" "compare")])
4586 (define_insn ""
4587 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4588 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4589 (const_int 0)))
4590 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4591 (neg:DI (match_dup 1)))]
4592 "TARGET_POWERPC64"
4593 "neg. %0,%1"
4594 [(set_attr "type" "compare")])
4596 (define_insn "ffsdi2"
4597 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4598 (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
4599 "TARGET_POWERPC64"
4600 "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
4601 [(set_attr "length" "16")])
4603 (define_insn "muldi3"
4604 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4605 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4606 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4607 "TARGET_POWERPC64"
4608 "mulld %0,%1,%2"
4609 [(set_attr "type" "imul")])
4611 (define_insn "smuldi3_highpart"
4612 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4613 (truncate:DI
4614 (lshiftrt:TI (mult:TI (sign_extend:TI
4615 (match_operand:DI 1 "gpc_reg_operand" "%r"))
4616 (sign_extend:TI
4617 (match_operand:DI 2 "gpc_reg_operand" "r")))
4618 (const_int 64))))]
4619 "TARGET_POWERPC64"
4620 "mulhd %0,%1,%2"
4621 [(set_attr "type" "imul")])
4623 (define_insn "umuldi3_highpart"
4624 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4625 (truncate:DI
4626 (lshiftrt:TI (mult:TI (zero_extend:TI
4627 (match_operand:DI 1 "gpc_reg_operand" "%r"))
4628 (zero_extend:TI
4629 (match_operand:DI 2 "gpc_reg_operand" "r")))
4630 (const_int 64))))]
4631 "TARGET_POWERPC64"
4632 "mulhdu %0,%1,%2"
4633 [(set_attr "type" "imul")])
4635 (define_expand "divdi3"
4636 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4637 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
4638 (match_operand:DI 2 "reg_or_cint_operand" "")))]
4639 "TARGET_POWERPC64"
4640 "
4641 {
4642 if (GET_CODE (operands[2]) == CONST_INT
4643 && exact_log2 (INTVAL (operands[2])) >= 0)
4644 ;
4645 else
4646 operands[2] = force_reg (DImode, operands[2]);
4647 }")
4649 (define_expand "moddi3"
4650 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
4651 (use (match_operand:DI 1 "gpc_reg_operand" ""))
4652 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
4653 "TARGET_POWERPC64"
4654 "
4655 {
4656 int i = exact_log2 (INTVAL (operands[2]));
4657 rtx temp1;
4658 rtx temp2;
4660 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
4661 FAIL;
4663 temp1 = gen_reg_rtx (DImode);
4664 temp2 = gen_reg_rtx (DImode);
4666 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
4667 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
4668 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
4669 DONE;
4670 }")
4672 (define_insn ""
4673 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4674 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4675 (match_operand:DI 2 "const_int_operand" "N")))]
4676 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
4677 "sradi %0,%1,%p2\;addze %0,%0"
4678 [(set_attr "length" "8")])
4680 (define_insn ""
4681 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4682 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4683 (match_operand:DI 2 "const_int_operand" "N"))
4684 (const_int 0)))
4685 (clobber (match_scratch:DI 3 "=r"))]
4686 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
4687 "sradi %3,%1,%p2\;addze. %3,%3"
4688 [(set_attr "type" "compare")
4689 (set_attr "length" "8")])
4691 (define_insn ""
4692 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4693 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4694 (match_operand:DI 2 "const_int_operand" "N"))
4695 (const_int 0)))
4696 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4697 (div:DI (match_dup 1) (match_dup 2)))]
4698 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
4699 "sradi %0,%1,%p2\;addze. %0,%0"
4700 [(set_attr "type" "compare")
4701 (set_attr "length" "8")])
4703 (define_insn ""
4704 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4705 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4706 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4707 "TARGET_POWERPC64"
4708 "divd %0,%1,%2"
4709 [(set_attr "type" "idiv")])
4711 (define_insn "udivdi3"
4712 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4713 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4714 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4715 "TARGET_POWERPC64"
4716 "divdu %0,%1,%2"
4717 [(set_attr "type" "idiv")])
4719 (define_insn "rotldi3"
4720 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4721 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4722 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
4723 "TARGET_POWERPC64"
4724 "rld%I2cl %0,%1,%H2,0")
4726 (define_insn "*rotldi3_internal2"
4727 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4728 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4729 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
4730 (const_int 0)))
4731 (clobber (match_scratch:DI 3 "=r"))]
4732 "TARGET_POWERPC64"
4733 "rld%I2cl. %3,%1,%H2,0"
4734 [(set_attr "type" "delayed_compare")])
4736 (define_insn "*rotldi3_internal3"
4737 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4738 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4739 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
4740 (const_int 0)))
4741 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4742 (rotate:DI (match_dup 1) (match_dup 2)))]
4743 "TARGET_POWERPC64"
4744 "rld%I2cl. %0,%1,%H2,0"
4745 [(set_attr "type" "delayed_compare")])
4747 (define_insn "*rotldi3_internal4"
4748 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4749 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4750 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
4751 (match_operand:DI 3 "mask64_operand" "S")))]
4752 "TARGET_POWERPC64"
4753 "rld%I2c%B3 %0,%1,%H2,%S3")
4755 (define_insn "*rotldi3_internal5"
4756 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4757 (compare:CC (and:DI (rotate:DI
4758 (match_operand:DI 1 "gpc_reg_operand" "r")
4759 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
4760 (match_operand:DI 3 "mask64_operand" "S"))
4761 (const_int 0)))
4762 (clobber (match_scratch:DI 4 "=r"))]
4763 "TARGET_POWERPC64"
4764 "rld%I2c%B3. %4,%1,%H2,%S3"
4765 [(set_attr "type" "delayed_compare")])
4767 (define_insn "*rotldi3_internal6"
4768 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4769 (compare:CC (and:DI (rotate:DI
4770 (match_operand:DI 1 "gpc_reg_operand" "r")
4771 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
4772 (match_operand:DI 3 "mask64_operand" "S"))
4773 (const_int 0)))
4774 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4775 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4776 "TARGET_POWERPC64"
4777 "rld%I2c%B3. %0,%1,%H2,%S3"
4778 [(set_attr "type" "delayed_compare")])
4780 (define_insn "*rotldi3_internal7"
4781 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4782 (zero_extend:DI
4783 (subreg:QI
4784 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4785 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
4786 "TARGET_POWERPC64"
4787 "rld%I2cl %0,%1,%H2,56")
4789 (define_insn "*rotldi3_internal8"
4790 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4791 (compare:CC (zero_extend:DI
4792 (subreg:QI
4793 (rotate:DI
4794 (match_operand:DI 1 "gpc_reg_operand" "r")
4795 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0))
4796 (const_int 0)))
4797 (clobber (match_scratch:DI 3 "=r"))]
4798 "TARGET_POWERPC64"
4799 "rld%I2cl. %3,%1,%H2,56"
4800 [(set_attr "type" "delayed_compare")])
4802 (define_insn "*rotldi3_internal9"
4803 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4804 (compare:CC (zero_extend:DI
4805 (subreg:QI
4806 (rotate:DI
4807 (match_operand:DI 1 "gpc_reg_operand" "r")
4808 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0))
4809 (const_int 0)))
4810 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4811 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1)
4812 (match_dup 2)) 0)))]
4813 "TARGET_POWERPC64"
4814 "rld%I2cl. %0,%1,%H2,56"
4815 [(set_attr "type" "delayed_compare")])
4817 (define_insn "*rotldi3_internal10"
4818 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4819 (zero_extend:DI
4820 (subreg:HI
4821 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4822 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
4823 "TARGET_POWERPC64"
4824 "rld%I2cl %0,%1,%H2,48")
4826 (define_insn "*rotldi3_internal11"
4827 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4828 (compare:CC (zero_extend:DI
4829 (subreg:HI
4830 (rotate:DI
4831 (match_operand:DI 1 "gpc_reg_operand" "r")
4832 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0))
4833 (const_int 0)))
4834 (clobber (match_scratch:DI 3 "=r"))]
4835 "TARGET_POWERPC64"
4836 "rld%I2cl. %3,%1,%H2,48"
4837 [(set_attr "type" "delayed_compare")])
4839 (define_insn "*rotldi3_internal12"
4840 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4841 (compare:CC (zero_extend:DI
4842 (subreg:HI
4843 (rotate:DI
4844 (match_operand:DI 1 "gpc_reg_operand" "r")
4845 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0))
4846 (const_int 0)))
4847 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4848 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1)
4849 (match_dup 2)) 0)))]
4850 "TARGET_POWERPC64"
4851 "rld%I2cl. %0,%1,%H2,48"
4852 [(set_attr "type" "delayed_compare")])
4854 (define_insn "*rotldi3_internal13"
4855 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4856 (zero_extend:DI
4857 (subreg:SI
4858 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4859 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
4860 "TARGET_POWERPC64"
4861 "rld%I2cl %0,%1,%H2,32")
4863 (define_insn "*rotldi3_internal14"
4864 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4865 (compare:CC (zero_extend:DI
4866 (subreg:SI
4867 (rotate:DI
4868 (match_operand:DI 1 "gpc_reg_operand" "r")
4869 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0))
4870 (const_int 0)))
4871 (clobber (match_scratch:DI 3 "=r"))]
4872 "TARGET_POWERPC64"
4873 "rld%I2cl. %3,%1,%H2,32"
4874 [(set_attr "type" "delayed_compare")])
4876 (define_insn "*rotldi3_internal15"
4877 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4878 (compare:CC (zero_extend:DI
4879 (subreg:SI
4880 (rotate:DI
4881 (match_operand:DI 1 "gpc_reg_operand" "r")
4882 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0))
4883 (const_int 0)))
4884 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4885 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1)
4886 (match_dup 2)) 0)))]
4887 "TARGET_POWERPC64"
4888 "rld%I2cl. %0,%1,%H2,32"
4889 [(set_attr "type" "delayed_compare")])
4891 (define_expand "ashldi3"
4892 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4893 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
4894 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4895 "TARGET_POWERPC64 || TARGET_POWER"
4896 "
4897 {
4898 if (TARGET_POWERPC64)
4899 ;
4900 else if (TARGET_POWER)
4901 {
4902 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
4903 DONE;
4904 }
4905 else
4906 FAIL;
4907 }")
4909 (define_insn ""
4910 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4911 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4912 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4913 "TARGET_POWERPC64"
4914 "sld%I2 %0,%1,%H2"
4915 [(set_attr "length" "8")])
4917 (define_insn ""
4918 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4919 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4920 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4921 (const_int 0)))
4922 (clobber (match_scratch:DI 3 "=r"))]
4923 "TARGET_POWERPC64"
4924 "sld%I2. %3,%1,%H2"
4925 [(set_attr "type" "delayed_compare")])
4927 (define_insn ""
4928 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4929 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4930 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4931 (const_int 0)))
4932 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4933 (ashift:DI (match_dup 1) (match_dup 2)))]
4934 "TARGET_POWERPC64"
4935 "sld%I2. %0,%1,%H2"
4936 [(set_attr "type" "delayed_compare")])
4938 (define_expand "lshrdi3"
4939 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4940 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
4941 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4942 "TARGET_POWERPC64 || TARGET_POWER"
4943 "
4944 {
4945 if (TARGET_POWERPC64)
4946 ;
4947 else if (TARGET_POWER)
4948 {
4949 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
4950 DONE;
4951 }
4952 else
4953 FAIL;
4954 }")
4956 (define_insn ""
4957 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4958 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4959 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4960 "TARGET_POWERPC64"
4961 "srd%I2 %0,%1,%H2")
4963 (define_insn ""
4964 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4965 (compare:CC (lshiftrt:DI
4966 (match_operand:DI 1 "gpc_reg_operand" "r")
4967 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4968 (const_int 0)))
4969 (clobber (match_scratch:DI 3 "=r"))]
4970 "TARGET_POWERPC64"
4971 "srd%I2. %3,%1,%H2"
4972 [(set_attr "type" "delayed_compare")])
4974 (define_insn ""
4975 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4976 (compare:CC (lshiftrt:DI
4977 (match_operand:DI 1 "gpc_reg_operand" "r")
4978 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4979 (const_int 0)))
4980 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4981 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
4982 "TARGET_POWERPC64"
4983 "srd%I2. %0,%1,%H2"
4984 [(set_attr "type" "delayed_compare")])
4986 (define_expand "ashrdi3"
4987 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4988 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
4989 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4990 "TARGET_POWERPC64 || TARGET_POWER"
4991 "
4992 {
4993 if (TARGET_POWERPC64)
4994 ;
4995 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
4996 {
4997 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
4998 DONE;
4999 }
5000 else
5001 FAIL;
5002 }")
5004 (define_insn ""
5005 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5006 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5007 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
5008 "TARGET_POWERPC64"
5009 "srad%I2 %0,%1,%H2")
5011 (define_insn ""
5012 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5013 (compare:CC (ashiftrt:DI
5014 (match_operand:DI 1 "gpc_reg_operand" "r")
5015 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
5016 (const_int 0)))
5017 (clobber (match_scratch:DI 3 "=r"))]
5018 "TARGET_POWERPC64"
5019 "srad%I2. %3,%1,%H2"
5020 [(set_attr "type" "delayed_compare")])
5022 (define_insn ""
5023 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5024 (compare:CC (ashiftrt:DI
5025 (match_operand:DI 1 "gpc_reg_operand" "r")
5026 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
5027 (const_int 0)))
5028 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5029 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5030 "TARGET_POWERPC64"
5031 "srad%I2. %0,%1,%H2"
5032 [(set_attr "type" "delayed_compare")])
5034 (define_insn "anddi3"
5035 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5036 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5037 (match_operand:DI 2 "and64_operand" "?r,S,K,J")))
5038 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
5039 "TARGET_POWERPC64"
5040 "@
5041 and %0,%1,%2
5042 rldic%B2 %0,%1,0,%S2
5043 andi. %0,%1,%b2
5044 andis. %0,%1,%u2")
5046 (define_insn "*anddi3_internal2"
5047 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
5048 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5049 (match_operand:DI 2 "and64_operand" "r,K,J,S"))
5050 (const_int 0)))
5051 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5052 "TARGET_POWERPC64"
5053 "@
5054 and. %3,%1,%2
5055 andi. %3,%1,%b2
5056 andis. %3,%1,%u2
5057 rldic%B2. %3,%1,0,%S2"
5058 [(set_attr "type" "compare,compare,compare,delayed_compare")])
5060 (define_insn "*anddi3_internal3"
5061 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
5062 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5063 (match_operand:DI 2 "and64_operand" "r,K,J,S"))
5064 (const_int 0)))
5065 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5066 (and:DI (match_dup 1) (match_dup 2)))]
5067 "TARGET_POWERPC64"
5068 "@
5069 and. %0,%1,%2
5070 andi. %0,%1,%b2
5071 andis. %0,%1,%u2
5072 rldic%B2. %3,%1,0,%S2"
5073 [(set_attr "type" "compare,compare,compare,delayed_compare")])
5075 (define_expand "iordi3"
5076 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5077 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
5078 (match_operand:DI 2 "reg_or_cint_operand" "")))]
5079 "TARGET_POWERPC64"
5080 "
5081 {
5082 if (GET_CODE (operands[2]) == CONST_INT
5083 && !logical_operand (operands[2], DImode))
5084 {
5085 HOST_WIDE_INT value = INTVAL (operands[2]);
5086 rtx tmp = ((reload_in_progress || reload_completed
5087 || rtx_equal_p (operands[0], operands[1]))
5088 ? operands[0] : gen_reg_rtx (DImode));
5090 emit_insn (gen_iordi3 (tmp, operands[1],
5091 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
5092 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
5093 DONE;
5094 }
5095 }")
5097 (define_insn "*iordi3_internal1"
5098 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
5099 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
5100 (match_operand:DI 2 "logical_operand" "r,K,J")))]
5101 "TARGET_POWERPC64"
5102 "@
5103 or %0,%1,%2
5104 ori %0,%1,%b2
5105 oris %0,%1,%u2")
5107 (define_insn "*iordi3_internal2"
5108 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5109 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5110 (match_operand:DI 2 "gpc_reg_operand" "r"))
5111 (const_int 0)))
5112 (clobber (match_scratch:DI 3 "=r"))]
5113 "TARGET_POWERPC64"
5114 "or. %3,%1,%2"
5115 [(set_attr "type" "compare")])
5117 (define_insn "*iordi3_internal3"
5118 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5119 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5120 (match_operand:DI 2 "gpc_reg_operand" "r"))
5121 (const_int 0)))
5122 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5123 (ior:DI (match_dup 1) (match_dup 2)))]
5124 "TARGET_POWERPC64"
5125 "or. %0,%1,%2"
5126 [(set_attr "type" "compare")])
5128 ;; Split an IOR that we can't do in one insn into two insns, each of which
5129 ;; does one 16-bit part. This is used by combine.
5131 (define_split
5132 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5133 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
5134 (match_operand:DI 2 "non_logical_cint_operand" "")))]
5135 "TARGET_POWERPC64"
5136 [(set (match_dup 0) (ior:DI (match_dup 1) (match_dup 3)))
5137 (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))]
5138 "
5139 {
5140 operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
5141 operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
5142 }")
5144 (define_expand "xordi3"
5145 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5146 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
5147 (match_operand:DI 2 "reg_or_cint_operand" "")))]
5148 "TARGET_POWERPC64"
5149 "
5150 {
5151 if (GET_CODE (operands[2]) == CONST_INT
5152 && !logical_operand (operands[2], DImode))
5153 {
5154 HOST_WIDE_INT value = INTVAL (operands[2]);
5155 rtx tmp = ((reload_in_progress || reload_completed
5156 || rtx_equal_p (operands[0], operands[1]))
5157 ? operands[0] : gen_reg_rtx (DImode));
5159 emit_insn (gen_xordi3 (tmp, operands[1],
5160 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
5161 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
5162 DONE;
5163 }
5164 }")
5166 (define_insn "*xordi3_internal1"
5167 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
5168 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
5169 (match_operand:DI 2 "logical_operand" "r,K,J")))]
5170 "TARGET_POWERPC64"
5171 "@
5172 xor %0,%1,%2
5173 xori %0,%1,%b2
5174 xoris %0,%1,%u2")
5176 (define_insn "*xordi3_internal2"
5177 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5178 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5179 (match_operand:DI 2 "gpc_reg_operand" "r"))
5180 (const_int 0)))
5181 (clobber (match_scratch:DI 3 "=r"))]
5182 "TARGET_POWERPC64"
5183 "xor. %3,%1,%2"
5184 [(set_attr "type" "compare")])
5186 (define_insn "*xordi3_internal3"
5187 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5188 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5189 (match_operand:DI 2 "gpc_reg_operand" "r"))
5190 (const_int 0)))
5191 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5192 (xor:DI (match_dup 1) (match_dup 2)))]
5193 "TARGET_POWERPC64"
5194 "xor. %0,%1,%2"
5195 [(set_attr "type" "compare")])
5197 ;; Split an XOR that we can't do in one insn into two insns, each of which
5198 ;; does one 16-bit part. This is used by combine.
5200 (define_split
5201 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5202 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
5203 (match_operand:DI 2 "non_logical_cint_operand" "")))]
5204 "TARGET_POWERPC64"
5205 [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 3)))
5206 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 4)))]
5207 "
5208 {
5209 operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
5210 operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
5211 }")
5213 (define_insn "*eqvdi3_internal1"
5214 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5215 (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5216 (match_operand:DI 2 "gpc_reg_operand" "r"))))]
5217 "TARGET_POWERPC64"
5218 "eqv %0,%1,%2")
5220 (define_insn "*eqvdi3_internal2"
5221 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5222 (compare:CC (not:DI (xor:DI
5223 (match_operand:DI 1 "gpc_reg_operand" "%r")
5224 (match_operand:DI 2 "gpc_reg_operand" "r")))
5225 (const_int 0)))
5226 (clobber (match_scratch:DI 3 "=r"))]
5227 "TARGET_POWERPC64"
5228 "eqv. %3,%1,%2"
5229 [(set_attr "type" "compare")])
5231 (define_insn "*eqvdi3_internal3"
5232 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5233 (compare:CC (not:DI (xor:DI
5234 (match_operand:DI 1 "gpc_reg_operand" "%r")
5235 (match_operand:DI 2 "gpc_reg_operand" "r")))
5236 (const_int 0)))
5237 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5238 (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
5239 "TARGET_POWERPC64"
5240 "eqv. %0,%1,%2"
5241 [(set_attr "type" "compare")])
5243 (define_insn "*andcdi3_internal1"
5244 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5245 (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5246 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5247 "TARGET_POWERPC64"
5248 "andc %0,%2,%1")
5250 (define_insn "*andcdi3_internal2"
5251 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5252 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5253 (match_operand:DI 2 "gpc_reg_operand" "r"))
5254 (const_int 0)))
5255 (clobber (match_scratch:DI 3 "=r"))]
5256 "TARGET_POWERPC64"
5257 "andc. %3,%2,%1"
5258 [(set_attr "type" "compare")])
5260 (define_insn "*andcdi3_internal3"
5261 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5262 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5263 (match_operand:DI 2 "gpc_reg_operand" "r"))
5264 (const_int 0)))
5265 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5266 (and:DI (not:DI (match_dup 1)) (match_dup 2)))]
5267 "TARGET_POWERPC64"
5268 "andc. %0,%2,%1"
5269 [(set_attr "type" "compare")])
5271 (define_insn "*iorcdi3_internal1"
5272 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5273 (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5274 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5275 "TARGET_POWERPC64"
5276 "orc %0,%2,%1")
5278 (define_insn "*iorcdi3_inernal2"
5279 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5280 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5281 (match_operand:DI 2 "gpc_reg_operand" "r"))
5282 (const_int 0)))
5283 (clobber (match_scratch:DI 3 "=r"))]
5284 "TARGET_POWERPC64"
5285 "orc. %3,%2,%1"
5286 [(set_attr "type" "compare")])
5288 (define_insn "*iorcdi3_internal3"
5289 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5290 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
5291 (match_operand:DI 2 "gpc_reg_operand" "r"))
5292 (const_int 0)))
5293 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5294 (ior:DI (not:DI (match_dup 1)) (match_dup 2)))]
5295 "TARGET_POWERPC64"
5296 "orc. %0,%2,%1"
5297 [(set_attr "type" "compare")])
5299 (define_insn "*nanddi3_internal1"
5300 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5301 (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5302 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
5303 "TARGET_POWERPC64"
5304 "nand %0,%1,%2")
5306 (define_insn "*nanddi3_internal2"
5307 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5308 (compare:CC (ior:DI
5309 (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5310 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
5311 (const_int 0)))
5312 (clobber (match_scratch:DI 3 "=r"))]
5313 "TARGET_POWERPC64"
5314 "nand. %3,%1,%2"
5315 [(set_attr "type" "compare")])
5317 (define_insn "*nanddi3_internal3"
5318 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5319 (compare:CC (ior:DI
5320 (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5321 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
5322 (const_int 0)))
5323 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5324 (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
5325 "TARGET_POWERPC64"
5326 "nand. %0,%1,%2"
5327 [(set_attr "type" "compare")])
5329 (define_insn "*nordi3_internal1"
5330 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5331 (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5332 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
5333 "TARGET_POWERPC64"
5334 "nor %0,%1,%2")
5336 (define_insn "*nordi3_internal2"
5337 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5338 (compare:CC (and:DI
5339 (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5340 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
5341 (const_int 0)))
5342 (clobber (match_scratch:DI 3 "=r"))]
5343 "TARGET_POWERPC64"
5344 "nor. %3,%1,%2"
5345 [(set_attr "type" "compare")])
5347 (define_insn "*nordi3_internal3"
5348 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5349 (compare:CC (and:DI
5350 (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5351 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
5352 (const_int 0)))
5353 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5354 (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
5355 "TARGET_POWERPC64"
5356 "nor. %0,%1,%2"
5357 [(set_attr "type" "compare")])
5358 \f
5359 ;; Now define ways of moving data around.
5361 ;; Elf specific ways of loading addresses for non-PIC code.
5362 ;; The output of this could be r0, but we limit it to base
5363 ;; registers, since almost all uses of this will need it
5364 ;; in a base register shortly.
5365 (define_insn "elf_high"
5366 [(set (match_operand:SI 0 "register_operand" "=b")
5367 (high:SI (match_operand 1 "" "")))]
5368 "TARGET_ELF && !TARGET_64BIT"
5369 "{cau|addis} %0,0,%1@ha")
5371 (define_insn "elf_low"
5372 [(set (match_operand:SI 0 "register_operand" "=r")
5373 (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
5374 (match_operand 2 "" "")))]
5375 "TARGET_ELF && !TARGET_64BIT"
5376 "{cal %0,%a2@l(%1)|addi %0,%1,%2@l}")
5378 ;; Set up a register with a value from the GOT table
5380 (define_expand "movsi_got"
5381 [(set (match_operand:SI 0 "register_operand" "")
5382 (unspec [(match_operand:SI 1 "got_operand" "")
5383 (match_dup 2)] 8))]
5384 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
5385 "
5386 {
5387 if (GET_CODE (operands[1]) == CONST)
5388 {
5389 rtx offset = const0_rtx;
5390 HOST_WIDE_INT value;
5392 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
5393 value = INTVAL (offset);
5394 if (value != 0)
5395 {
5396 rtx tmp = ((reload_in_progress || reload_completed)
5397 ? operands[0]
5398 : gen_reg_rtx (Pmode));
5399 emit_insn (gen_movsi_got (tmp, operands[1]));
5400 emit_insn (gen_addsi3 (operands[0], tmp, offset));
5401 DONE;
5402 }
5403 }
5405 operands[2] = rs6000_got_register (operands[1]);
5406 }")
5408 (define_insn "*movsi_got_internal"
5409 [(set (match_operand:SI 0 "register_operand" "=r")
5410 (unspec [(match_operand:SI 1 "got_no_const_operand" "")
5411 (match_operand:SI 2 "register_operand" "b")] 8))]
5412 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
5413 "{l|lwz} %0,%a1@got(%2)"
5414 [(set_attr "type" "load")])
5416 ;; Sometimes, though, the GOT `register' will be on the stack. Deal with
5417 ;; this case specially.
5418 ;; Force final to split this insn (if it hasn't been split already) to
5419 ;; avoid having to create a suitable output template.
5420 (define_insn "*movsi_got_internal_mem"
5421 [(set (match_operand:SI 0 "register_operand" "=r")
5422 (unspec [(match_operand:SI 1 "got_no_const_operand" "")
5423 (match_operand:SI 2 "memory_operand" "m")] 8))]
5424 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5425 && flag_pic == 1
5426 && (reload_in_progress || reload_completed)"
5427 "#"
5428 [(set_attr "type" "load")
5429 (set_attr "length" "8")])
5431 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
5432 ;; didn't get allocated to a hard register.
5433 (define_split
5434 [(set (match_operand:SI 0 "register_operand" "=r")
5435 (unspec [(match_operand:SI 1 "got_no_const_operand" "")
5436 (match_operand:SI 2 "memory_operand" "m")] 8))]
5437 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5438 && flag_pic == 1
5439 && (reload_in_progress || reload_completed)"
5440 [(set (match_dup 0) (match_dup 2))
5441 (set (match_dup 0) (unspec [(match_dup 1)(match_dup 0)] 8))]
5442 "")
5444 ;; For SI, we special-case integers that can't be loaded in one insn. We
5445 ;; do the load 16-bits at a time. We could do this by loading from memory,
5446 ;; and this is even supposed to be faster, but it is simpler not to get
5447 ;; integers in the TOC.
5448 (define_expand "movsi"
5449 [(set (match_operand:SI 0 "general_operand" "")
5450 (match_operand:SI 1 "any_operand" ""))]
5451 ""
5452 "
5453 {
5454 if (GET_CODE (operands[0]) != REG)
5455 operands[1] = force_reg (SImode, operands[1]);
5457 /* Convert a move of a CONST_DOUBLE into a CONST_INT */
5458 if (GET_CODE (operands[1]) == CONST_DOUBLE)
5459 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5461 /* Use default pattern for address of ELF small data */
5462 if (TARGET_ELF
5463 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5464 && (GET_CODE (operands[1]) == SYMBOL_REF
5465 || GET_CODE (operands[1]) == CONST)
5466 && small_data_operand (operands[1], SImode))
5467 {
5468 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
5469 DONE;
5470 }
5472 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5473 && flag_pic == 1 && got_operand (operands[1], SImode))
5474 {
5475 emit_insn (gen_movsi_got (operands[0], operands[1]));
5476 DONE;
5477 }
5479 if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT
5480 && !flag_pic
5481 && CONSTANT_P (operands[1])
5482 && GET_CODE (operands[1]) != HIGH
5483 && GET_CODE (operands[1]) != CONST_INT)
5484 {
5485 rtx target = (reload_completed || reload_in_progress)
5486 ? operands[0] : gen_reg_rtx (SImode);
5488 /* If this is a function address on -mcall-aixdesc or -mcall-nt,
5489 convert it to the address of the descriptor. */
5490 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
5491 && GET_CODE (operands[1]) == SYMBOL_REF
5492 && XSTR (operands[1], 0)[0] == '.')
5493 {
5494 char *name = XSTR (operands[1], 0);
5495 rtx new_ref;
5496 while (*name == '.')
5497 name++;
5498 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
5499 CONSTANT_POOL_ADDRESS_P (new_ref)
5500 = CONSTANT_POOL_ADDRESS_P (operands[1]);
5501 SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]);
5502 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
5503 operands[1] = new_ref;
5504 }
5506 emit_insn (gen_elf_high (target, operands[1]));
5507 emit_insn (gen_elf_low (operands[0], target, operands[1]));
5508 DONE;
5509 }
5511 if (GET_CODE (operands[1]) == CONST
5512 && DEFAULT_ABI == ABI_NT
5513 && !side_effects_p (operands[0]))
5514 {
5515 rtx const_term = const0_rtx;
5516 rtx sym = eliminate_constant_term (XEXP (operands[1], 0), &const_term);
5517 if (sym && GET_CODE (const_term) == CONST_INT
5518 && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF))
5519 {
5520 unsigned HOST_WIDE_INT value = INTVAL (const_term);
5521 int new_reg_p = (flag_expensive_optimizations
5522 && !reload_completed
5523 && !reload_in_progress);
5524 rtx tmp1 = ((new_reg_p && value != 0)
5525 ? gen_reg_rtx (SImode) : operands[0]);
5527 emit_insn (gen_movsi (tmp1, sym));
5528 if (INTVAL (const_term) != 0)
5529 emit_insn (gen_addsi3 (operands[0], tmp1, GEN_INT (value)));
5530 DONE;
5531 }
5532 else
5533 rs6000_fatal_bad_address (operands[1]);
5534 }
5536 if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT)
5537 && CONSTANT_P (operands[1])
5538 && GET_CODE (operands[1]) != CONST_INT
5539 && GET_CODE (operands[1]) != HIGH
5540 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
5541 {
5542 /* Emit a USE operation so that the constant isn't deleted if
5543 expensive optimizations are turned on because nobody
5544 references it. This should only be done for operands that
5545 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
5546 This should not be done for operands that contain LABEL_REFs.
5547 For now, we just handle the obvious case. */
5548 if (GET_CODE (operands[1]) != LABEL_REF)
5549 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
5551 /* If we are to limit the number of things we put in the TOC and
5552 this is a symbol plus a constant we can add in one insn,
5553 just put the symbol in the TOC and add the constant. Don't do
5554 this if reload is in progress. */
5555 if (GET_CODE (operands[1]) == CONST
5556 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
5557 && GET_CODE (XEXP (operands[1], 0)) == PLUS
5558 && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode)
5559 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
5560 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
5561 && ! side_effects_p (operands[0]))
5562 {
5563 rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0));
5564 rtx other = XEXP (XEXP (operands[1], 0), 1);
5566 emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other));
5567 DONE;
5568 }
5570 operands[1] = force_const_mem (SImode, operands[1]);
5571 if (! memory_address_p (SImode, XEXP (operands[1], 0))
5572 && ! reload_in_progress)
5573 operands[1] = change_address (operands[1], SImode,
5574 XEXP (operands[1], 0));
5575 }
5576 }")
5578 (define_insn ""
5579 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
5580 (match_operand:SI 1 "input_operand" "r,U,m,r,I,J,n,R,*h,r,r,0"))]
5581 "gpc_reg_operand (operands[0], SImode)
5582 || gpc_reg_operand (operands[1], SImode)"
5583 "@
5584 mr %0,%1
5585 {cal|la} %0,%a1
5586 {l%U1%X1|lwz%U1%X1} %0,%1
5587 {st%U0%X0|stw%U0%X0} %1,%0
5588 {lil|li} %0,%1
5589 {liu|lis} %0,%v1
5590 #
5591 {cal|la} %0,%1(%*)
5592 mf%1 %0
5593 mt%0 %1
5594 mt%0 %1
5595 cror 0,0,0"
5596 [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*")
5597 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")])
5599 ;; Split a load of a large constant into the appropriate two-insn
5600 ;; sequence.
5602 (define_split
5603 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5604 (match_operand:SI 1 "const_int_operand" ""))]
5605 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
5606 && (INTVAL (operands[1]) & 0xffff) != 0"
5607 [(set (match_dup 0)
5608 (match_dup 2))
5609 (set (match_dup 0)
5610 (ior:SI (match_dup 0)
5611 (match_dup 3)))]
5612 "
5613 {
5614 operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
5615 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
5616 }")
5618 (define_insn ""
5619 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
5620 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
5621 (const_int 0)))
5622 (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
5623 ""
5624 "mr. %0,%1"
5625 [(set_attr "type" "compare")])
5626 \f
5627 (define_expand "movhi"
5628 [(set (match_operand:HI 0 "general_operand" "")
5629 (match_operand:HI 1 "any_operand" ""))]
5630 ""
5631 "
5632 {
5633 if (GET_CODE (operands[0]) != REG)
5634 operands[1] = force_reg (HImode, operands[1]);
5636 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
5637 {
5638 operands[1] = force_const_mem (HImode, operands[1]);
5639 if (! memory_address_p (HImode, XEXP (operands[1], 0))
5640 && ! reload_in_progress)
5641 operands[1] = change_address (operands[1], HImode,
5642 XEXP (operands[1], 0));
5643 }
5644 }")
5646 (define_insn ""
5647 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
5648 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
5649 "gpc_reg_operand (operands[0], HImode)
5650 || gpc_reg_operand (operands[1], HImode)"
5651 "@
5652 mr %0,%1
5653 lhz%U1%X1 %0,%1
5654 sth%U0%X0 %1,%0
5655 {lil|li} %0,%w1
5656 mf%1 %0
5657 mt%0 %1
5658 mt%0 %1
5659 cror 0,0,0"
5660 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
5662 (define_expand "movqi"
5663 [(set (match_operand:QI 0 "general_operand" "")
5664 (match_operand:QI 1 "any_operand" ""))]
5665 ""
5666 "
5667 {
5668 if (GET_CODE (operands[0]) != REG)
5669 operands[1] = force_reg (QImode, operands[1]);
5671 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
5672 {
5673 operands[1] = force_const_mem (QImode, operands[1]);
5674 if (! memory_address_p (QImode, XEXP (operands[1], 0))
5675 && ! reload_in_progress)
5676 operands[1] = change_address (operands[1], QImode,
5677 XEXP (operands[1], 0));
5678 }
5679 }")
5681 (define_insn ""
5682 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
5683 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
5684 "gpc_reg_operand (operands[0], QImode)
5685 || gpc_reg_operand (operands[1], QImode)"
5686 "@
5687 mr %0,%1
5688 lbz%U1%X1 %0,%1
5689 stb%U0%X0 %1,%0
5690 {lil|li} %0,%1
5691 mf%1 %0
5692 mt%0 %1
5693 mt%0 %1
5694 cror 0,0,0"
5695 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
5696 \f
5697 ;; Here is how to move condition codes around. When we store CC data in
5698 ;; an integer register or memory, we store just the high-order 4 bits.
5699 ;; This lets us not shift in the most common case of CR0.
5700 (define_expand "movcc"
5701 [(set (match_operand:CC 0 "nonimmediate_operand" "")
5702 (match_operand:CC 1 "nonimmediate_operand" ""))]
5703 ""
5704 "")
5706 (define_insn ""
5707 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
5708 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
5709 "register_operand (operands[0], CCmode)
5710 || register_operand (operands[1], CCmode)"
5711 "@
5712 mcrf %0,%1
5713 mtcrf 128,%1
5714 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
5715 mfcr %0
5716 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
5717 mr %0,%1
5718 {l%U1%X1|lwz%U1%X1} %0,%1
5719 {st%U0%U1|stw%U0%U1} %1,%0"
5720 [(set_attr "type" "*,*,*,compare,*,*,load,store")
5721 (set_attr "length" "*,*,12,*,8,*,*,*")])
5722 \f
5723 ;; For floating-point, we normally deal with the floating-point registers
5724 ;; unless -msoft-float is used. The sole exception is that parameter passing
5725 ;; can produce floating-point values in fixed-point registers. Unless the
5726 ;; value is a simple constant or already in memory, we deal with this by
5727 ;; allocating memory and copying the value explicitly via that memory location.
5728 (define_expand "movsf"
5729 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5730 (match_operand:SF 1 "any_operand" ""))]
5731 ""
5732 "
5733 {
5734 /* If we are called from reload, we might be getting a SUBREG of a hard
5735 reg. So expand it. */
5736 if (GET_CODE (operands[0]) == SUBREG
5737 && GET_CODE (SUBREG_REG (operands[0])) == REG
5738 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
5739 operands[0] = alter_subreg (operands[0]);
5740 if (GET_CODE (operands[1]) == SUBREG
5741 && GET_CODE (SUBREG_REG (operands[1])) == REG
5742 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
5743 operands[1] = alter_subreg (operands[1]);
5745 if (TARGET_SOFT_FLOAT && GET_CODE (operands[0]) == MEM)
5746 operands[1] = force_reg (SFmode, operands[1]);
5748 else if (TARGET_HARD_FLOAT)
5749 {
5750 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
5751 {
5752 /* If this is a store to memory or another integer register do the
5753 move directly. Otherwise store to a temporary stack slot and
5754 load from there into a floating point register. */
5756 if (GET_CODE (operands[0]) == MEM
5757 || (GET_CODE (operands[0]) == REG
5758 && (REGNO (operands[0]) < 32
5759 || (reload_in_progress
5760 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
5761 {
5762 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
5763 operand_subword (operands[1], 0, 0, SFmode));
5764 DONE;
5765 }
5766 else
5767 {
5768 rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
5770 emit_move_insn (stack_slot, operands[1]);
5771 emit_move_insn (operands[0], stack_slot);
5772 DONE;
5773 }
5774 }
5776 if (GET_CODE (operands[0]) == MEM)
5777 {
5778 /* If operands[1] is a register, it may have double-precision data
5779 in it, so truncate it to single precision. We need not do
5780 this for POWERPC. */
5781 if (! TARGET_POWERPC && TARGET_HARD_FLOAT
5782 && GET_CODE (operands[1]) == REG)
5783 {
5784 rtx newreg
5785 = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
5786 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
5787 operands[1] = newreg;
5788 }
5790 operands[1] = force_reg (SFmode, operands[1]);
5791 }
5793 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
5794 {
5795 if (GET_CODE (operands[1]) == MEM
5796 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
5797 || GET_CODE (operands[1]) == CONST_DOUBLE
5798 #endif
5799 || (GET_CODE (operands[1]) == REG
5800 && (REGNO (operands[1]) < 32
5801 || (reload_in_progress
5802 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))))
5803 {
5804 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
5805 operand_subword (operands[1], 0, 0, SFmode));
5806 DONE;
5807 }
5808 else
5809 {
5810 rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
5812 emit_move_insn (stack_slot, operands[1]);
5813 emit_move_insn (operands[0], stack_slot);
5814 DONE;
5815 }
5816 }
5817 }
5819 if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT)
5820 {
5821 operands[1] = force_const_mem (SFmode, operands[1]);
5822 if (! memory_address_p (SFmode, XEXP (operands[1], 0))
5823 && ! reload_in_progress)
5824 operands[1] = change_address (operands[1], SFmode,
5825 XEXP (operands[1], 0));
5826 }
5827 }")
5829 (define_split
5830 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5831 (match_operand:SF 1 "const_double_operand" ""))]
5832 "! TARGET_POWERPC64 && reload_completed
5833 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
5834 || (GET_CODE (operands[0]) == SUBREG
5835 && GET_CODE (SUBREG_REG (operands[0])) == REG
5836 && REGNO (SUBREG_REG (operands[0])) <= 31))"
5837 [(set (match_dup 2) (match_dup 3))]
5838 "
5839 {
5840 long l;
5841 REAL_VALUE_TYPE rv;
5843 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
5844 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5846 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
5847 operands[3] = GEN_INT(l);
5848 }")
5850 (define_split
5851 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5852 (match_operand:SF 1 "const_double_operand" ""))]
5853 "TARGET_POWERPC64 && reload_completed
5854 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
5855 || (GET_CODE (operands[0]) == SUBREG
5856 && GET_CODE (SUBREG_REG (operands[0])) == REG
5857 && REGNO (SUBREG_REG (operands[0])) <= 31))"
5858 [(set (match_dup 2) (match_dup 3))]
5859 "
5860 {
5861 long l;
5862 REAL_VALUE_TYPE rv;
5864 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
5865 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5867 operands[2] = gen_lowpart (SImode, operands[0]);
5868 operands[3] = GEN_INT(l);
5869 }")
5871 (define_insn "*movsf_hardfloat"
5872 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,!r,!r")
5873 (match_operand:SF 1 "input_operand" "f,m,f,G,Fn"))]
5874 "(gpc_reg_operand (operands[0], SFmode)
5875 || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
5876 "@
5877 fmr %0,%1
5878 lfs%U1%X1 %0,%1
5879 stfs%U0%X0 %1,%0
5880 #
5881 #"
5882 [(set_attr "type" "fp,fpload,fpstore,*,*")
5883 (set_attr "length" "4,4,4,4,8")])
5885 (define_insn "*movsf_softfloat"
5886 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
5887 (match_operand:SF 1 "input_operand" "r,m,r,I,J,R,G,Fn"))]
5888 "(gpc_reg_operand (operands[0], SFmode)
5889 || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
5890 "@
5891 mr %0,%1
5892 {l%U1%X1|lwz%U1%X1} %0,%1
5893 {st%U0%X0|stw%U0%X0} %1,%0
5894 {lil|li} %0,%1
5895 {liu|lis} %0,%v1
5896 {cal|la} %0,%1(%*)
5897 #
5898 #"
5899 [(set_attr "type" "*,load,store,*,*,*,*,*")
5900 (set_attr "length" "4,4,4,4,4,4,4,8")])
5902 \f
5903 (define_expand "movdf"
5904 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5905 (match_operand:DF 1 "any_operand" ""))]
5906 ""
5907 "
5908 {
5909 if (GET_CODE (operands[0]) != REG)
5910 operands[1] = force_reg (DFmode, operands[1]);
5912 /* Stores between FPR and any non-FPR registers must go through a
5913 temporary stack slot. */
5915 if (TARGET_POWERPC64
5916 && GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
5917 && ((FP_REGNO_P (REGNO (operands[0]))
5918 && ! FP_REGNO_P (REGNO (operands[1])))
5919 || (FP_REGNO_P (REGNO (operands[1]))
5920 && ! FP_REGNO_P (REGNO (operands[0])))))
5921 {
5922 rtx stack_slot = assign_stack_temp (DFmode, 8, 0);
5924 emit_move_insn (stack_slot, operands[1]);
5925 emit_move_insn (operands[0], stack_slot);
5926 DONE;
5927 }
5929 if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode))
5930 {
5931 operands[1] = force_const_mem (DFmode, operands[1]);
5932 if (! memory_address_p (DFmode, XEXP (operands[1], 0))
5933 && ! reload_in_progress)
5934 operands[1] = change_address (operands[1], DFmode,
5935 XEXP (operands[1], 0));
5936 }
5937 }")
5939 (define_split
5940 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5941 (match_operand:DF 1 "const_int_operand" ""))]
5942 "! TARGET_POWERPC64 && reload_completed
5943 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
5944 || (GET_CODE (operands[0]) == SUBREG
5945 && GET_CODE (SUBREG_REG (operands[0])) == REG
5946 && REGNO (SUBREG_REG (operands[0])) <= 31))"
5947 [(set (match_dup 2) (match_dup 4))
5948 (set (match_dup 3) (match_dup 1))]
5949 "
5950 {
5951 int endian = (WORDS_BIG_ENDIAN == 0);
5952 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
5953 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5954 operands[4] = ((INTVAL (operands[1]) & 0x80000000)
5955 ? constm1_rtx : const0_rtx);
5956 }")
5958 (define_split
5959 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5960 (match_operand:DF 1 "const_double_operand" ""))]
5961 "! TARGET_POWERPC64 && reload_completed
5962 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
5963 || (GET_CODE (operands[0]) == SUBREG
5964 && GET_CODE (SUBREG_REG (operands[0])) == REG
5965 && REGNO (SUBREG_REG (operands[0])) <= 31))"
5966 [(set (match_dup 2) (match_dup 4))
5967 (set (match_dup 3) (match_dup 5))]
5968 "
5969 {
5970 int endian = (WORDS_BIG_ENDIAN == 0);
5971 long l[2];
5972 REAL_VALUE_TYPE rv;
5974 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
5975 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
5977 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
5978 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5979 operands[4] = GEN_INT (l[endian]);
5980 operands[5] = GEN_INT (l[1 - endian]);
5981 }")
5983 (define_split
5984 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5985 (match_operand:DF 1 "easy_fp_constant" ""))]
5986 "TARGET_POWERPC64 && reload_completed
5987 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
5988 || (GET_CODE (operands[0]) == SUBREG
5989 && GET_CODE (SUBREG_REG (operands[0])) == REG
5990 && REGNO (SUBREG_REG (operands[0])) <= 31))"
5991 [(set (match_dup 2) (match_dup 3))]
5992 "
5993 {
5994 int endian = (WORDS_BIG_ENDIAN == 0);
5995 long l[2];
5996 REAL_VALUE_TYPE rv;
5998 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
5999 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
6001 operands[2] = gen_lowpart (DImode, operands[0]);
6002 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
6003 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
6004 }")
6006 ;; Don't have reload use general registers to load a constant. First,
6007 ;; it might not work if the output operand has is the equivalent of
6008 ;; a non-offsettable memref, but also it is less efficient than loading
6009 ;; the constant into an FP register, since it will probably be used there.
6010 ;; The "??" is a kludge until we can figure out a more reasonable way
6011 ;; of handling these non-offsettable values.
6012 (define_insn "*movdf_hardfloat32"
6013 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m")
6014 (match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))]
6015 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
6016 && (register_operand (operands[0], DFmode)
6017 || register_operand (operands[1], DFmode))"
6018 "*
6019 {
6020 switch (which_alternative)
6021 {
6022 default:
6023 abort ();
6024 case 0:
6025 /* We normally copy the low-numbered register first. However, if
6026 the first register operand 0 is the same as the second register of
6027 operand 1, we must copy in the opposite order. */
6028 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
6029 return \"mr %L0,%L1\;mr %0,%1\";
6030 else
6031 return \"mr %0,%1\;mr %L0,%L1\";
6032 case 1:
6033 /* If the low-address word is used in the address, we must load it
6034 last. Otherwise, load it first. Note that we cannot have
6035 auto-increment in that case since the address register is known to be
6036 dead. */
6037 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6038 operands [1], 0))
6039 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
6040 else
6041 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
6042 case 2:
6043 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
6044 case 3:
6045 case 4:
6046 case 5:
6047 return \"#\";
6048 case 6:
6049 return \"fmr %0,%1\";
6050 case 7:
6051 return \"lfd%U1%X1 %0,%1\";
6052 case 8:
6053 return \"stfd%U0%X0 %1,%0\";
6054 }
6055 }"
6056 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
6057 (set_attr "length" "8,8,8,8,12,16,*,*,*")])
6059 (define_insn "*movdf_softfloat32"
6060 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r,r,r")
6061 (match_operand:DF 1 "input_operand" "r,o,r,G,H,F"))]
6062 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
6063 && (register_operand (operands[0], DFmode)
6064 || register_operand (operands[1], DFmode))"
6065 "*
6066 {
6067 switch (which_alternative)
6068 {
6069 default:
6070 abort ();
6071 case 0:
6072 /* We normally copy the low-numbered register first. However, if
6073 the first register operand 0 is the same as the second register of
6074 operand 1, we must copy in the opposite order. */
6075 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
6076 return \"mr %L0,%L1\;mr %0,%1\";
6077 else
6078 return \"mr %0,%1\;mr %L0,%L1\";
6079 case 1:
6080 /* If the low-address word is used in the address, we must load it
6081 last. Otherwise, load it first. Note that we cannot have
6082 auto-increment in that case since the address register is known to be
6083 dead. */
6084 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6085 operands [1], 0))
6086 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
6087 else
6088 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
6089 case 2:
6090 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
6091 case 3:
6092 case 4:
6093 case 5:
6094 return \"#\";
6095 }
6096 }"
6097 [(set_attr "type" "*,load,store,*,*,*")
6098 (set_attr "length" "8,8,8,8,12,16")])
6100 (define_insn "*movdf_hardfloat64"
6101 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m")
6102 (match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))]
6103 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
6104 && (register_operand (operands[0], DFmode)
6105 || register_operand (operands[1], DFmode))"
6106 "@
6107 mr %0,%1
6108 ld%U1%X1 %0,%1
6109 std%U0%X0 %1,%0
6110 #
6111 #
6112 #
6113 fmr %0,%1
6114 lfd%U1%X1 %0,%1
6115 stfd%U0%X0 %1,%0"
6116 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
6117 (set_attr "length" "4,4,4,8,12,16,4,4,4")])
6119 (define_insn "*movdf_softfloat64"
6120 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r,r,r")
6121 (match_operand:DF 1 "input_operand" "r,o,r,G,H,F"))]
6122 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
6123 && (register_operand (operands[0], DFmode)
6124 || register_operand (operands[1], DFmode))"
6125 "@
6126 mr %0,%1
6127 ld%U1%X1 %0,%1
6128 std%U0%X0 %1,%0
6129 #
6130 #
6131 #"
6132 [(set_attr "type" "*,load,store,*,*,*")
6133 (set_attr "length" "*,*,*,8,12,16")])
6134 \f
6135 ;; Next come the multi-word integer load and store and the load and store
6136 ;; multiple insns.
6137 (define_expand "movdi"
6138 [(set (match_operand:DI 0 "general_operand" "")
6139 (match_operand:DI 1 "any_operand" ""))]
6140 ""
6141 "
6142 {
6143 if (GET_CODE (operands[0]) != REG)
6144 operands[1] = force_reg (DImode, operands[1]);
6146 /* Convert a move of a CONST_DOUBLE into a CONST_INT
6147 only if sign-extended lower-half for 32-bit host. */
6148 if (GET_CODE (operands[1]) == CONST_DOUBLE
6149 #if HOST_BITS_PER_WIDE_INT == 32
6150 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
6151 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
6152 || (CONST_DOUBLE_HIGH (operands[1]) == 0xffffffff
6153 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))
6154 #endif
6155 )
6156 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6158 if (TARGET_64BIT
6159 && CONSTANT_P (operands[1])
6160 #if HOST_BITS_PER_WIDE_INT == 32
6161 && GET_CODE (operands[1]) != CONST_INT
6162 #endif
6163 && ! easy_fp_constant (operands[1], DImode)
6164 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
6165 {
6166 /* Emit a USE operation so that the constant isn't deleted if
6167 expensive optimizations are turned on because nobody
6168 references it. This should only be done for operands that
6169 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
6170 This should not be done for operands that contain LABEL_REFs.
6171 For now, we just handle the obvious case. */
6172 if (GET_CODE (operands[1]) != LABEL_REF)
6173 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
6175 /* If we are to limit the number of things we put in the TOC and
6176 this is a symbol plus a constant we can add in one insn,
6177 just put the symbol in the TOC and add the constant. Don't do
6178 this if reload is in progress. */
6179 if (GET_CODE (operands[1]) == CONST
6180 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
6181 && GET_CODE (XEXP (operands[1], 0)) == PLUS
6182 && add_operand (XEXP (XEXP (operands[1], 0), 1), DImode)
6183 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
6184 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
6185 && ! side_effects_p (operands[0]))
6186 {
6187 rtx sym = force_const_mem (DImode, XEXP (XEXP (operands[1], 0), 0));
6188 rtx other = XEXP (XEXP (operands[1], 0), 1);
6190 emit_insn (gen_adddi3 (operands[0], force_reg (DImode, sym), other));
6191 DONE;
6192 }
6194 operands[1] = force_const_mem (DImode, operands[1]);
6195 if (! memory_address_p (DImode, XEXP (operands[1], 0))
6196 && ! reload_in_progress)
6197 operands[1] = change_address (operands[1], DImode,
6198 XEXP (operands[1], 0));
6199 }
6200 }")
6202 (define_insn "*movdi_32"
6203 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
6204 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
6205 "! TARGET_POWERPC64
6206 && (gpc_reg_operand (operands[0], DImode)
6207 || gpc_reg_operand (operands[1], DImode))"
6208 "*
6209 {
6210 switch (which_alternative)
6211 {
6212 default:
6213 abort ();
6214 case 0:
6215 /* We normally copy the low-numbered register first. However, if
6216 the first register operand 0 is the same as the second register of
6217 operand 1, we must copy in the opposite order. */
6218 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
6219 return \"mr %L0,%L1\;mr %0,%1\";
6220 else
6221 return \"mr %0,%1\;mr %L0,%L1\";
6222 case 1:
6223 /* If the low-address word is used in the address, we must load it
6224 last. Otherwise, load it first. Note that we cannot have
6225 auto-increment in that case since the address register is known to be
6226 dead. */
6227 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6228 operands [1], 0))
6229 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
6230 else
6231 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
6232 case 2:
6233 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
6234 case 3:
6235 return \"fmr %0,%1\";
6236 case 4:
6237 return \"lfd%U1%X1 %0,%1\";
6238 case 5:
6239 return \"stfd%U0%X0 %1,%0\";
6240 case 6:
6241 case 7:
6242 case 8:
6243 case 9:
6244 case 10:
6245 return \"#\";
6246 }
6247 }"
6248 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
6249 (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")])
6251 (define_split
6252 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6253 (match_operand:DI 1 "const_int_operand" ""))]
6254 "! TARGET_POWERPC64 && reload_completed"
6255 [(set (match_dup 2) (match_dup 4))
6256 (set (match_dup 3) (match_dup 1))]
6257 "
6258 {
6259 operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
6260 operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
6261 operands[4] = ((INTVAL (operands[1]) & 0x80000000)
6262 ? constm1_rtx : const0_rtx);
6263 }")
6265 (define_split
6266 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6267 (match_operand:DI 1 "const_double_operand" ""))]
6268 "! TARGET_POWERPC64 && reload_completed"
6269 [(set (match_dup 2) (match_dup 4))
6270 (set (match_dup 3) (match_dup 5))]
6271 "
6272 {
6273 operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
6274 operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
6275 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6276 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6277 }")
6279 (define_insn "*movdi_64"
6280 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
6281 (match_operand:DI 1 "input_operand" "r,m,r,I,J,nF,R,f,m,f,*h,r,0"))]
6282 "TARGET_POWERPC64
6283 && (gpc_reg_operand (operands[0], DImode)
6284 || gpc_reg_operand (operands[1], DImode))"
6285 "@
6286 mr %0,%1
6287 ld%U1%X1 %0,%1
6288 std%U0%X0 %1,%0
6289 li %0,%1
6290 lis %0,%v1
6291 #
6292 {cal|la} %0,%1(%*)
6293 fmr %0,%1
6294 lfd%U1%X1 %0,%1
6295 stfd%U0%X0 %1,%0
6296 mf%1 %0
6297 mt%0 %1
6298 cror 0,0,0"
6299 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
6300 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
6302 (define_insn ""
6303 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6304 (match_operand:DI 1 "const_double_operand" "F"))]
6305 "TARGET_POWERPC64 && GET_CODE (operands[1]) == CONST_DOUBLE
6306 && num_insns_constant (operands[1], DImode) == 1"
6307 "*
6308 {
6309 return ((unsigned HOST_WIDE_INT)
6310 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
6311 ? \"li %0,%1\" : \"lis %0,%v1\";
6312 }")
6314 (define_split
6315 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6316 (match_operand:DI 1 "const_int_operand" ""))]
6317 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
6318 && num_insns_constant (operands[1], DImode) > 1"
6319 [(set (match_dup 0)
6320 (match_dup 2))
6321 (set (match_dup 0)
6322 (ior:DI (match_dup 0)
6323 (match_dup 3)))]
6324 "
6325 {
6326 operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
6327 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
6328 }")
6330 (define_split
6331 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6332 (match_operand:DI 1 "const_double_operand" ""))]
6333 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
6334 && GET_CODE (operands[1]) == CONST_DOUBLE
6335 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
6336 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
6337 || (CONST_DOUBLE_HIGH (operands[1]) == 0xffffffff
6338 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))"
6339 [(set (match_dup 0)
6340 (match_dup 2))
6341 (set (match_dup 0)
6342 (ior:DI (match_dup 0)
6343 (match_dup 3)))]
6344 "
6345 {
6346 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff0000);
6347 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff);
6348 }")
6350 (define_split
6351 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6352 (match_operand:DI 1 "const_double_operand" ""))]
6353 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
6354 && GET_CODE (operands[1]) == CONST_DOUBLE
6355 && CONST_DOUBLE_HIGH (operands[1]) == 0
6356 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0"
6357 [(set (match_dup 0)
6358 (match_dup 2))
6359 (set (match_dup 0)
6360 (zero_extend:DI (subreg:SI (match_dup 0) 0)))]
6361 "
6362 { operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); }")
6364 (define_split
6365 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6366 (match_operand:DI 1 "const_double_operand" ""))]
6367 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
6368 && GET_CODE (operands[1]) == CONST_DOUBLE
6369 && CONST_DOUBLE_LOW (operands[1]) == 0"
6370 [(set (match_dup 0)
6371 (match_dup 2))
6372 (set (match_dup 0)
6373 (ashift:DI (match_dup 0)
6374 (const_int 32)))]
6375 "
6376 { operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); }")
6378 ;; Generate all one-bits and clear left or right.
6379 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
6380 (define_split
6381 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6382 (match_operand:DI 1 "mask64_operand" ""))]
6383 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
6384 [(set (match_dup 0) (const_int -1))
6385 (set (match_dup 0)
6386 (and:DI (rotate:DI (match_dup 0)
6387 (const_int 0))
6388 (match_dup 1)))]
6389 "")
6391 ;; Split a load of a large constant into the appropriate five-instruction
6392 ;; sequence. Handle anything in a constant number of insns.
6393 ;; When non-easy constants can go in the TOC, this should use
6394 ;; easy_fp_constant predicate.
6395 (define_split
6396 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6397 (match_operand:DI 1 "const_double_operand" ""))]
6398 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
6399 [(set (match_dup 0)
6400 (match_dup 2))
6401 (set (match_dup 0)
6402 (ashift:DI (match_dup 0)
6403 (const_int 32)))
6404 (set (match_dup 0)
6405 (ior:DI (match_dup 0)
6406 (match_dup 3)))]
6407 "
6408 {
6409 HOST_WIDE_INT low;
6410 HOST_WIDE_INT high;
6412 if (GET_CODE (operands[1]) == CONST_DOUBLE)
6413 {
6414 low = CONST_DOUBLE_LOW (operands[1]);
6415 high = CONST_DOUBLE_HIGH (operands[1]);
6416 }
6417 else
6418 #if HOST_BITS_PER_WIDE_INT == 32
6419 {
6420 low = INTVAL (operands[1]);
6421 high = (low < 0) ? ~0 : 0;
6422 }
6423 #else
6424 {
6425 low = INTVAL (operands[1]) & 0xffffffff;
6426 high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
6427 }
6428 #endif
6430 operands[2] = GEN_INT (high);
6431 operands[3] = GEN_INT (low);
6432 }")
6434 (define_insn ""
6435 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
6436 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
6437 (const_int 0)))
6438 (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
6439 "TARGET_POWERPC64"
6440 "mr. %0,%1"
6441 [(set_attr "type" "compare")])
6442 \f
6443 ;; TImode is similar, except that we usually want to compute the address into
6444 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
6445 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
6446 (define_expand "movti"
6447 [(parallel [(set (match_operand:TI 0 "general_operand" "")
6448 (match_operand:TI 1 "general_operand" ""))
6449 (clobber (scratch:SI))])]
6450 "TARGET_STRING || TARGET_POWERPC64"
6451 "
6452 {
6453 if (GET_CODE (operands[0]) == MEM)
6454 operands[1] = force_reg (TImode, operands[1]);
6456 if (GET_CODE (operands[0]) == MEM
6457 && GET_CODE (XEXP (operands[0], 0)) != REG
6458 && ! reload_in_progress)
6459 operands[0] = change_address (operands[0], TImode,
6460 copy_addr_to_reg (XEXP (operands[0], 0)));
6462 if (GET_CODE (operands[1]) == MEM
6463 && GET_CODE (XEXP (operands[1], 0)) != REG
6464 && ! reload_in_progress)
6465 operands[1] = change_address (operands[1], TImode,
6466 copy_addr_to_reg (XEXP (operands[1], 0)));
6467 }")
6469 ;; We say that MQ is clobbered in the last alternative because the first
6470 ;; alternative would never get used otherwise since it would need a reload
6471 ;; while the 2nd alternative would not. We put memory cases first so they
6472 ;; are preferred. Otherwise, we'd try to reload the output instead of
6473 ;; giving the SCRATCH mq.
6474 (define_insn "*movti_power"
6475 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
6476 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
6477 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
6478 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
6479 && (gpc_reg_operand (operands[0], TImode)
6480 || gpc_reg_operand (operands[1], TImode))"
6481 "*
6482 {
6483 switch (which_alternative)
6484 {
6485 default:
6486 abort ();
6488 case 0:
6489 return \"{stsi|stswi} %1,%P0,16\";
6491 case 1:
6492 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
6494 case 2:
6495 /* Normally copy registers with lowest numbered register copied first.
6496 But copy in the other order if the first register of the output
6497 is the second, third, or fourth register in the input. */
6498 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
6499 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
6500 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
6501 else
6502 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
6503 case 3:
6504 /* If the address is not used in the output, we can use lsi. Otherwise,
6505 fall through to generating four loads. */
6506 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
6507 return \"{lsi|lswi} %0,%P1,16\";
6508 /* ... fall through ... */
6509 case 4:
6510 /* If the address register is the same as the register for the lowest-
6511 addressed word, load it last. Similarly for the next two words.
6512 Otherwise load lowest address to highest. */
6513 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6514 operands[1], 0))
6515 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
6516 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
6517 REGNO (operands[0]) + 2, operands[1], 0))
6518 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
6519 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
6520 REGNO (operands[0]) + 3, operands[1], 0))
6521 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
6522 else
6523 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
6524 }
6525 }"
6526 [(set_attr "type" "store,store,*,load,load")
6527 (set_attr "length" "*,16,16,*,16")])
6529 (define_insn "*movti_string"
6530 [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
6531 (match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
6532 (clobber (match_scratch:SI 2 "=X,X,X"))]
6533 "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64
6534 && (gpc_reg_operand (operands[0], TImode)
6535 || gpc_reg_operand (operands[1], TImode))"
6536 "*
6537 {
6538 switch (which_alternative)
6539 {
6540 default:
6541 abort ();
6543 case 0:
6544 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
6546 case 1:
6547 /* Normally copy registers with lowest numbered register copied first.
6548 But copy in the other order if the first register of the output
6549 is the second, third, or fourth register in the input. */
6550 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
6551 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
6552 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
6553 else
6554 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
6555 case 2:
6556 /* If the address register is the same as the register for the lowest-
6557 addressed word, load it last. Similarly for the next two words.
6558 Otherwise load lowest address to highest. */
6559 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6560 operands[1], 0))
6561 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
6562 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
6563 REGNO (operands[0]) + 2, operands[1], 0))
6564 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
6565 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
6566 REGNO (operands[0]) + 3, operands[1], 0))
6567 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
6568 else
6569 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
6570 }
6571 }"
6572 [(set_attr "type" "store,*,load")
6573 (set_attr "length" "16,16,16")])
6575 (define_insn "*movti_ppc64"
6576 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
6577 (match_operand:TI 1 "input_operand" "r,m,r"))]
6578 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
6579 || gpc_reg_operand (operands[1], TImode))"
6580 "*
6581 {
6582 switch (which_alternative)
6583 {
6584 default:
6585 abort ();
6586 case 0:
6587 /* We normally copy the low-numbered register first. However, if
6588 the first register operand 0 is the same as the second register of
6589 operand 1, we must copy in the opposite order. */
6590 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
6591 return \"mr %L0,%L1\;mr %0,%1\";
6592 else
6593 return \"mr %0,%1\;mr %L0,%L1\";
6594 case 1:
6595 /* If the low-address word is used in the address, we must load it
6596 last. Otherwise, load it first. Note that we cannot have
6597 auto-increment in that case since the address register is known to be
6598 dead. */
6599 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6600 operands [1], 0))
6601 return \"ld %L0,%L1\;ld %0,%1\";
6602 else
6603 return \"ld%U1 %0,%1\;ld %L0,%L1\";
6604 case 2:
6605 return \"std%U0 %1,%0\;std %L1,%L0\";
6606 }
6607 }"
6608 [(set_attr "type" "*,load,store")
6609 (set_attr "length" "8,8,8")])
6610 \f
6611 (define_expand "load_multiple"
6612 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
6613 (match_operand:SI 1 "" ""))
6614 (use (match_operand:SI 2 "" ""))])]
6615 "TARGET_STRING"
6616 "
6617 {
6618 int regno;
6619 int count;
6620 rtx from;
6621 int i;
6623 /* Support only loading a constant number of fixed-point registers from
6624 memory and only bother with this if more than two; the machine
6625 doesn't support more than eight. */
6626 if (GET_CODE (operands[2]) != CONST_INT
6627 || INTVAL (operands[2]) <= 2
6628 || INTVAL (operands[2]) > 8
6629 || GET_CODE (operands[1]) != MEM
6630 || GET_CODE (operands[0]) != REG
6631 || REGNO (operands[0]) >= 32)
6632 FAIL;
6634 count = INTVAL (operands[2]);
6635 regno = REGNO (operands[0]);
6637 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
6638 from = force_reg (SImode, XEXP (operands[1], 0));
6640 for (i = 0; i < count; i++)
6641 XVECEXP (operands[3], 0, i)
6642 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
6643 change_address (operands[1], SImode,
6644 plus_constant (from, i * 4)));
6645 }")
6647 (define_insn ""
6648 [(match_parallel 0 "load_multiple_operation"
6649 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
6650 (mem:SI
6651 (match_operand:SI 2 "register_operand" "b")))])]
6652 "TARGET_STRING"
6653 "*
6654 {
6655 /* We have to handle the case where the pseudo used to contain the address
6656 is assigned to one of the output registers. */
6657 int i, j;
6658 int words = XVECLEN (operands[0], 0);
6659 rtx xop[10];
6661 if (XVECLEN (operands[0], 0) == 1)
6662 return \"{l|lwz} %1,0(%2)\";
6664 for (i = 0; i < words; i++)
6665 if (refers_to_regno_p (REGNO (operands[1]) + i,
6666 REGNO (operands[1]) + i + 1, operands[2], 0))
6667 {
6668 if (i == words-1)
6669 {
6670 xop[0] = operands[1];
6671 xop[1] = operands[2];
6672 xop[2] = GEN_INT (4 * (words-1));
6673 output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop);
6674 return \"\";
6675 }
6676 else if (i == 0)
6677 {
6678 xop[0] = operands[1];
6679 xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6680 xop[2] = GEN_INT (4 * (words-1));
6681 output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop);
6682 return \"\";
6683 }
6684 else
6685 {
6686 for (j = 0; j < words; j++)
6687 if (j != i)
6688 {
6689 xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j);
6690 xop[1] = operands[2];
6691 xop[2] = GEN_INT (j * 4);
6692 output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop);
6693 }
6694 xop[0] = operands[2];
6695 xop[1] = GEN_INT (i * 4);
6696 output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop);
6697 return \"\";
6698 }
6699 }
6701 return \"{lsi|lswi} %1,%2,%N0\";
6702 }"
6703 [(set_attr "type" "load")
6704 (set_attr "length" "32")])
6706 \f
6707 (define_expand "store_multiple"
6708 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
6709 (match_operand:SI 1 "" ""))
6710 (clobber (scratch:SI))
6711 (use (match_operand:SI 2 "" ""))])]
6712 "TARGET_STRING"
6713 "
6714 {
6715 int regno;
6716 int count;
6717 rtx to;
6718 int i;
6720 /* Support only storing a constant number of fixed-point registers to
6721 memory and only bother with this if more than two; the machine
6722 doesn't support more than eight. */
6723 if (GET_CODE (operands[2]) != CONST_INT
6724 || INTVAL (operands[2]) <= 2
6725 || INTVAL (operands[2]) > 8
6726 || GET_CODE (operands[0]) != MEM
6727 || GET_CODE (operands[1]) != REG
6728 || REGNO (operands[1]) >= 32)
6729 FAIL;
6731 count = INTVAL (operands[2]);
6732 regno = REGNO (operands[1]);
6734 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
6735 to = force_reg (SImode, XEXP (operands[0], 0));
6737 XVECEXP (operands[3], 0, 0)
6738 = gen_rtx_SET (VOIDmode, change_address (operands[0], SImode, to),
6739 operands[1]);
6740 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
6741 gen_rtx_SCRATCH (SImode));
6743 for (i = 1; i < count; i++)
6744 XVECEXP (operands[3], 0, i + 1)
6745 = gen_rtx_SET (VOIDmode,
6746 change_address (operands[0], SImode,
6747 plus_constant (to, i * 4)),
6748 gen_rtx_REG (SImode, regno + i));
6749 }")
6751 (define_insn ""
6752 [(match_parallel 0 "store_multiple_operation"
6753 [(set (match_operand:SI 1 "indirect_operand" "=Q")
6754 (match_operand:SI 2 "gpc_reg_operand" "r"))
6755 (clobber (match_scratch:SI 3 "=q"))])]
6756 "TARGET_STRING && TARGET_POWER"
6757 "{stsi|stswi} %2,%P1,%O0"
6758 [(set_attr "type" "store")])
6760 (define_insn ""
6761 [(match_parallel 0 "store_multiple_operation"
6762 [(set (mem:SI (match_operand:SI 1 "register_operand" "b"))
6763 (match_operand:SI 2 "gpc_reg_operand" "r"))
6764 (clobber (match_scratch:SI 3 "X"))])]
6765 "TARGET_STRING && !TARGET_POWER"
6766 "{stsi|stswi} %2,%1,%O0"
6767 [(set_attr "type" "store")])
6769 \f
6770 ;; String/block move insn.
6771 ;; Argument 0 is the destination
6772 ;; Argument 1 is the source
6773 ;; Argument 2 is the length
6774 ;; Argument 3 is the alignment
6776 (define_expand "movstrsi"
6777 [(parallel [(set (match_operand:BLK 0 "" "")
6778 (match_operand:BLK 1 "" ""))
6779 (use (match_operand:SI 2 "" ""))
6780 (use (match_operand:SI 3 "" ""))])]
6781 ""
6782 "
6783 {
6784 if (expand_block_move (operands))
6785 DONE;
6786 else
6787 FAIL;
6788 }")
6790 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
6791 ;; register allocator doesn't have a clue about allocating 8 word registers
6792 (define_expand "movstrsi_8reg"
6793 [(parallel [(set (match_operand 0 "" "")
6794 (match_operand 1 "" ""))
6795 (use (match_operand 2 "" ""))
6796 (use (match_operand 3 "" ""))
6797 (clobber (reg:SI 5))
6798 (clobber (reg:SI 6))
6799 (clobber (reg:SI 7))
6800 (clobber (reg:SI 8))
6801 (clobber (reg:SI 9))
6802 (clobber (reg:SI 10))
6803 (clobber (reg:SI 11))
6804 (clobber (reg:SI 12))
6805 (clobber (match_scratch:SI 4 ""))])]
6806 "TARGET_STRING"
6807 "")
6809 (define_insn ""
6810 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6811 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6812 (use (match_operand:SI 2 "immediate_operand" "i"))
6813 (use (match_operand:SI 3 "immediate_operand" "i"))
6814 (clobber (match_operand:SI 4 "register_operand" "=r"))
6815 (clobber (reg:SI 6))
6816 (clobber (reg:SI 7))
6817 (clobber (reg:SI 8))
6818 (clobber (reg:SI 9))
6819 (clobber (reg:SI 10))
6820 (clobber (reg:SI 11))
6821 (clobber (reg:SI 12))
6822 (clobber (match_scratch:SI 5 "=q"))]
6823 "TARGET_STRING && TARGET_POWER
6824 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
6825 || INTVAL (operands[2]) == 0)
6826 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
6827 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
6828 && REGNO (operands[4]) == 5"
6829 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6830 [(set_attr "type" "load")
6831 (set_attr "length" "8")])
6833 (define_insn ""
6834 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6835 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6836 (use (match_operand:SI 2 "immediate_operand" "i"))
6837 (use (match_operand:SI 3 "immediate_operand" "i"))
6838 (clobber (match_operand:SI 4 "register_operand" "=r"))
6839 (clobber (reg:SI 6))
6840 (clobber (reg:SI 7))
6841 (clobber (reg:SI 8))
6842 (clobber (reg:SI 9))
6843 (clobber (reg:SI 10))
6844 (clobber (reg:SI 11))
6845 (clobber (reg:SI 12))
6846 (clobber (match_scratch:SI 5 "X"))]
6847 "TARGET_STRING && !TARGET_POWER
6848 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
6849 || INTVAL (operands[2]) == 0)
6850 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
6851 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
6852 && REGNO (operands[4]) == 5"
6853 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6854 [(set_attr "type" "load")
6855 (set_attr "length" "8")])
6857 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
6858 ;; register allocator doesn't have a clue about allocating 6 word registers
6859 (define_expand "movstrsi_6reg"
6860 [(parallel [(set (match_operand 0 "" "")
6861 (match_operand 1 "" ""))
6862 (use (match_operand 2 "" ""))
6863 (use (match_operand 3 "" ""))
6864 (clobber (reg:SI 7))
6865 (clobber (reg:SI 8))
6866 (clobber (reg:SI 9))
6867 (clobber (reg:SI 10))
6868 (clobber (reg:SI 11))
6869 (clobber (reg:SI 12))
6870 (clobber (match_scratch:SI 4 ""))])]
6871 "TARGET_STRING"
6872 "")
6874 (define_insn ""
6875 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6876 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6877 (use (match_operand:SI 2 "immediate_operand" "i"))
6878 (use (match_operand:SI 3 "immediate_operand" "i"))
6879 (clobber (match_operand:SI 4 "register_operand" "=r"))
6880 (clobber (reg:SI 8))
6881 (clobber (reg:SI 9))
6882 (clobber (reg:SI 10))
6883 (clobber (reg:SI 11))
6884 (clobber (reg:SI 12))
6885 (clobber (match_scratch:SI 5 "=q"))]
6886 "TARGET_STRING && TARGET_POWER
6887 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
6888 && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
6889 && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
6890 && REGNO (operands[4]) == 7"
6891 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6892 [(set_attr "type" "load")
6893 (set_attr "length" "8")])
6895 (define_insn ""
6896 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6897 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6898 (use (match_operand:SI 2 "immediate_operand" "i"))
6899 (use (match_operand:SI 3 "immediate_operand" "i"))
6900 (clobber (match_operand:SI 4 "register_operand" "=r"))
6901 (clobber (reg:SI 8))
6902 (clobber (reg:SI 9))
6903 (clobber (reg:SI 10))
6904 (clobber (reg:SI 11))
6905 (clobber (reg:SI 12))
6906 (clobber (match_scratch:SI 5 "X"))]
6907 "TARGET_STRING && !TARGET_POWER
6908 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
6909 && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
6910 && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
6911 && REGNO (operands[4]) == 7"
6912 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6913 [(set_attr "type" "load")
6914 (set_attr "length" "8")])
6916 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
6917 ;; problems with TImode
6918 (define_expand "movstrsi_4reg"
6919 [(parallel [(set (match_operand 0 "" "")
6920 (match_operand 1 "" ""))
6921 (use (match_operand 2 "" ""))
6922 (use (match_operand 3 "" ""))
6923 (clobber (reg:SI 9))
6924 (clobber (reg:SI 10))
6925 (clobber (reg:SI 11))
6926 (clobber (reg:SI 12))
6927 (clobber (match_scratch:SI 4 ""))])]
6928 "TARGET_STRING"
6929 "")
6931 (define_insn ""
6932 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6933 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6934 (use (match_operand:SI 2 "immediate_operand" "i"))
6935 (use (match_operand:SI 3 "immediate_operand" "i"))
6936 (clobber (match_operand:SI 4 "register_operand" "=r"))
6937 (clobber (reg:SI 10))
6938 (clobber (reg:SI 11))
6939 (clobber (reg:SI 12))
6940 (clobber (match_scratch:SI 5 "=q"))]
6941 "TARGET_STRING && TARGET_POWER
6942 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
6943 && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
6944 && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
6945 && REGNO (operands[4]) == 9"
6946 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6947 [(set_attr "type" "load")
6948 (set_attr "length" "8")])
6950 (define_insn ""
6951 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6952 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6953 (use (match_operand:SI 2 "immediate_operand" "i"))
6954 (use (match_operand:SI 3 "immediate_operand" "i"))
6955 (clobber (match_operand:SI 4 "register_operand" "=r"))
6956 (clobber (reg:SI 10))
6957 (clobber (reg:SI 11))
6958 (clobber (reg:SI 12))
6959 (clobber (match_scratch:SI 5 "X"))]
6960 "TARGET_STRING && !TARGET_POWER
6961 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
6962 && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
6963 && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
6964 && REGNO (operands[4]) == 9"
6965 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6966 [(set_attr "type" "load")
6967 (set_attr "length" "8")])
6969 ;; Move up to 8 bytes at a time.
6970 (define_expand "movstrsi_2reg"
6971 [(parallel [(set (match_operand 0 "" "")
6972 (match_operand 1 "" ""))
6973 (use (match_operand 2 "" ""))
6974 (use (match_operand 3 "" ""))
6975 (clobber (match_scratch:DI 4 ""))
6976 (clobber (match_scratch:SI 5 ""))])]
6977 "TARGET_STRING && !TARGET_64BIT"
6978 "")
6980 (define_insn ""
6981 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6982 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6983 (use (match_operand:SI 2 "immediate_operand" "i"))
6984 (use (match_operand:SI 3 "immediate_operand" "i"))
6985 (clobber (match_scratch:DI 4 "=&r"))
6986 (clobber (match_scratch:SI 5 "=q"))]
6987 "TARGET_STRING && TARGET_POWER && !TARGET_64BIT
6988 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
6989 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6990 [(set_attr "type" "load")
6991 (set_attr "length" "8")])
6993 (define_insn ""
6994 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6995 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6996 (use (match_operand:SI 2 "immediate_operand" "i"))
6997 (use (match_operand:SI 3 "immediate_operand" "i"))
6998 (clobber (match_scratch:DI 4 "=&r"))
6999 (clobber (match_scratch:SI 5 "X"))]
7000 "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
7001 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
7002 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
7003 [(set_attr "type" "load")
7004 (set_attr "length" "8")])
7006 ;; Move up to 4 bytes at a time.
7007 (define_expand "movstrsi_1reg"
7008 [(parallel [(set (match_operand 0 "" "")
7009 (match_operand 1 "" ""))
7010 (use (match_operand 2 "" ""))
7011 (use (match_operand 3 "" ""))
7012 (clobber (match_scratch:SI 4 ""))
7013 (clobber (match_scratch:SI 5 ""))])]
7014 "TARGET_STRING"
7015 "")
7017 (define_insn ""
7018 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
7019 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
7020 (use (match_operand:SI 2 "immediate_operand" "i"))
7021 (use (match_operand:SI 3 "immediate_operand" "i"))
7022 (clobber (match_scratch:SI 4 "=&r"))
7023 (clobber (match_scratch:SI 5 "=q"))]
7024 "TARGET_STRING && TARGET_POWER
7025 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
7026 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
7027 [(set_attr "type" "load")
7028 (set_attr "length" "8")])
7030 (define_insn ""
7031 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
7032 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
7033 (use (match_operand:SI 2 "immediate_operand" "i"))
7034 (use (match_operand:SI 3 "immediate_operand" "i"))
7035 (clobber (match_scratch:SI 4 "=&r"))
7036 (clobber (match_scratch:SI 5 "X"))]
7037 "TARGET_STRING && !TARGET_POWER
7038 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
7039 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
7040 [(set_attr "type" "load")
7041 (set_attr "length" "8")])
7043 \f
7044 ;; Define insns that do load or store with update. Some of these we can
7045 ;; get by using pre-decrement or pre-increment, but the hardware can also
7046 ;; do cases where the increment is not the size of the object.
7047 ;;
7048 ;; In all these cases, we use operands 0 and 1 for the register being
7049 ;; incremented because those are the operands that local-alloc will
7050 ;; tie and these are the pair most likely to be tieable (and the ones
7051 ;; that will benefit the most).
7053 (define_insn "*movdi_update1"
7054 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
7055 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
7056 (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
7057 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
7058 (plus:DI (match_dup 1) (match_dup 2)))]
7059 "TARGET_POWERPC64 && TARGET_UPDATE"
7060 "@
7061 ldux %3,%0,%2
7062 ldu %3,%2(%0)"
7063 [(set_attr "type" "load")])
7065 (define_insn "*movdi_update2"
7066 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
7067 (sign_extend:DI
7068 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
7069 (match_operand:DI 2 "gpc_reg_operand" "r")))))
7070 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
7071 (plus:DI (match_dup 1) (match_dup 2)))]
7072 "TARGET_POWERPC64"
7073 "lwaux %3,%0,%2"
7074 [(set_attr "type" "load")])
7076 (define_insn "movdi_update"
7077 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
7078 (match_operand:DI 2 "reg_or_short_operand" "r,I")))
7079 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
7080 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
7081 (plus:DI (match_dup 1) (match_dup 2)))]
7082 "TARGET_POWERPC64 && TARGET_UPDATE"
7083 "@
7084 stdux %3,%0,%2
7085 stdu %3,%2(%0)"
7086 [(set_attr "type" "store")])
7088 (define_insn "*movsi_update1"
7089 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
7090 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7091 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7092 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7093 (plus:SI (match_dup 1) (match_dup 2)))]
7094 ""
7095 "@
7096 {lux|lwzux} %3,%0,%2
7097 {lu|lwzu} %3,%2(%0)"
7098 [(set_attr "type" "load")])
7100 (define_insn "movsi_update"
7101 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7102 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7103 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
7104 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7105 (plus:SI (match_dup 1) (match_dup 2)))]
7106 "TARGET_UPDATE"
7107 "@
7108 {stux|stwux} %3,%0,%2
7109 {stu|stwu} %3,%2(%0)"
7110 [(set_attr "type" "store")])
7112 (define_insn "*movhi_update"
7113 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
7114 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7115 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7116 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7117 (plus:SI (match_dup 1) (match_dup 2)))]
7118 "TARGET_UPDATE"
7119 "@
7120 lhzux %3,%0,%2
7121 lhzu %3,%2(%0)"
7122 [(set_attr "type" "load")])
7124 (define_insn "*movhi_update2"
7125 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
7126 (zero_extend:SI
7127 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7128 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
7129 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7130 (plus:SI (match_dup 1) (match_dup 2)))]
7131 "TARGET_UPDATE"
7132 "@
7133 lhzux %3,%0,%2
7134 lhzu %3,%2(%0)"
7135 [(set_attr "type" "load")])
7137 (define_insn "*movhi_update3"
7138 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
7139 (sign_extend:SI
7140 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7141 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
7142 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7143 (plus:SI (match_dup 1) (match_dup 2)))]
7144 "TARGET_UPDATE"
7145 "@
7146 lhaux %3,%0,%2
7147 lhau %3,%2(%0)"
7148 [(set_attr "type" "load")])
7150 (define_insn "*movhi_update4"
7151 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7152 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7153 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
7154 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7155 (plus:SI (match_dup 1) (match_dup 2)))]
7156 "TARGET_UPDATE"
7157 "@
7158 sthux %3,%0,%2
7159 sthu %3,%2(%0)"
7160 [(set_attr "type" "store")])
7162 (define_insn "*movqi_update1"
7163 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
7164 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7165 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7166 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7167 (plus:SI (match_dup 1) (match_dup 2)))]
7168 "TARGET_UPDATE"
7169 "@
7170 lbzux %3,%0,%2
7171 lbzu %3,%2(%0)"
7172 [(set_attr "type" "load")])
7174 (define_insn "*movqi_update2"
7175 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
7176 (zero_extend:SI
7177 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7178 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
7179 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7180 (plus:SI (match_dup 1) (match_dup 2)))]
7181 "TARGET_UPDATE"
7182 "@
7183 lbzux %3,%0,%2
7184 lbzu %3,%2(%0)"
7185 [(set_attr "type" "load")])
7187 (define_insn "*movqi_update3"
7188 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7189 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7190 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
7191 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7192 (plus:SI (match_dup 1) (match_dup 2)))]
7193 "TARGET_UPDATE"
7194 "@
7195 stbux %3,%0,%2
7196 stbu %3,%2(%0)"
7197 [(set_attr "type" "store")])
7199 (define_insn "*movsf_update1"
7200 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
7201 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7202 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7203 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7204 (plus:SI (match_dup 1) (match_dup 2)))]
7205 "TARGET_HARD_FLOAT && TARGET_UPDATE"
7206 "@
7207 lfsux %3,%0,%2
7208 lfsu %3,%2(%0)"
7209 [(set_attr "type" "fpload")])
7211 (define_insn "*movsf_update2"
7212 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7213 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7214 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
7215 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7216 (plus:SI (match_dup 1) (match_dup 2)))]
7217 "TARGET_HARD_FLOAT && TARGET_UPDATE"
7218 "@
7219 stfsux %3,%0,%2
7220 stfsu %3,%2(%0)"
7221 [(set_attr "type" "fpstore")])
7223 (define_insn "*movsf_update3"
7224 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
7225 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7226 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7227 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7228 (plus:SI (match_dup 1) (match_dup 2)))]
7229 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
7230 "@
7231 {lux|lwzux} %3,%0,%2
7232 {lu|lwzu} %3,%2(%0)"
7233 [(set_attr "type" "load")])
7235 (define_insn "*movsf_update4"
7236 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7237 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7238 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
7239 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7240 (plus:SI (match_dup 1) (match_dup 2)))]
7241 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
7242 "@
7243 {stux|stwux} %3,%0,%2
7244 {stu|stwu} %3,%2(%0)"
7245 [(set_attr "type" "store")])
7247 (define_insn "*movdf_update1"
7248 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
7249 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7250 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
7251 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7252 (plus:SI (match_dup 1) (match_dup 2)))]
7253 "TARGET_HARD_FLOAT && TARGET_UPDATE"
7254 "@
7255 lfdux %3,%0,%2
7256 lfdu %3,%2(%0)"
7257 [(set_attr "type" "fpload")])
7259 (define_insn "*movdf_update2"
7260 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
7261 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
7262 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
7263 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
7264 (plus:SI (match_dup 1) (match_dup 2)))]
7265 "TARGET_HARD_FLOAT && TARGET_UPDATE"
7266 "@
7267 stfdux %3,%0,%2
7268 stfdu %3,%2(%0)"
7269 [(set_attr "type" "fpstore")])
7271 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
7273 (define_peephole
7274 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7275 (match_operand:DF 1 "memory_operand" ""))
7276 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
7277 (match_operand:DF 3 "memory_operand" ""))]
7278 "TARGET_POWER2
7279 && TARGET_HARD_FLOAT
7280 && registers_ok_for_quad_peep (operands[0], operands[2])
7281 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
7282 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
7283 "lfq%U1%X1 %0,%1")
7285 (define_peephole
7286 [(set (match_operand:DF 0 "memory_operand" "")
7287 (match_operand:DF 1 "gpc_reg_operand" "f"))
7288 (set (match_operand:DF 2 "memory_operand" "")
7289 (match_operand:DF 3 "gpc_reg_operand" "f"))]
7290 "TARGET_POWER2
7291 && TARGET_HARD_FLOAT
7292 && registers_ok_for_quad_peep (operands[1], operands[3])
7293 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
7294 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
7295 "stfq%U0%X0 %1,%0")
7296 \f
7297 ;; Next come insns related to the calling sequence.
7298 ;;
7299 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7300 ;; We move the back-chain and decrement the stack pointer.
7302 (define_expand "allocate_stack"
7303 [(set (match_operand 0 "register_operand" "=r")
7304 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
7305 (set (reg 1)
7306 (minus (reg 1) (match_dup 1)))]
7307 ""
7308 "
7309 { rtx chain = gen_reg_rtx (Pmode);
7310 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7311 rtx neg_op0;
7313 emit_move_insn (chain, stack_bot);
7315 /* Under Windows NT, we need to add stack probes for large/variable
7316 allocations, so do it via a call to the external function alloca
7317 instead of doing it inline. */
7318 if (DEFAULT_ABI == ABI_NT
7319 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 4096))
7320 {
7321 rtx tmp = gen_reg_rtx (Pmode);
7322 emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode,
7323 \"__allocate_stack\"),
7324 tmp, 0, Pmode, 1, operands[1], Pmode);
7325 emit_insn (gen_set_sp (tmp));
7326 emit_move_insn (operands[0], tmp);
7327 DONE;
7328 }
7330 if (GET_CODE (operands[1]) != CONST_INT
7331 || INTVAL (operands[1]) < -32767
7332 || INTVAL (operands[1]) > 32768)
7333 {
7334 neg_op0 = gen_reg_rtx (Pmode);
7335 if (TARGET_32BIT)
7336 emit_insn (gen_negsi2 (neg_op0, operands[1]));
7337 else
7338 emit_insn (gen_negdi2 (neg_op0, operands[1]));
7339 }
7340 else
7341 neg_op0 = GEN_INT (- INTVAL (operands[1]));
7343 if (TARGET_UPDATE)
7344 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
7345 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
7347 else
7348 {
7349 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
7350 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
7351 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
7352 }
7354 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7355 DONE;
7356 }")
7358 ;; Marker to indicate that the stack pointer was changed under NT in
7359 ;; ways not known to the compiler
7361 (define_insn "set_sp"
7362 [(set (reg:SI 1)
7363 (unspec [(match_operand:SI 0 "register_operand" "r")] 7))]
7364 ""
7365 ""
7366 [(set_attr "length" "0")])
7368 ;; These patterns say how to save and restore the stack pointer. We need not
7369 ;; save the stack pointer at function level since we are careful to preserve
7370 ;; the backchain. At block level, we have to restore the backchain when we
7371 ;; restore the stack pointer.
7372 ;;
7373 ;; For nonlocal gotos, we must save both the stack pointer and its backchain
7374 ;; and restore both. Note that in the nonlocal case, the save area is a
7375 ;; memory location.
7377 (define_expand "save_stack_function"
7378 [(use (const_int 0))]
7379 ""
7380 "")
7382 (define_expand "restore_stack_function"
7383 [(use (const_int 0))]
7384 ""
7385 "")
7387 (define_expand "restore_stack_block"
7388 [(use (match_operand 0 "register_operand" ""))
7389 (set (match_dup 2) (match_dup 3))
7390 (set (match_dup 0) (match_operand 1 "register_operand" ""))
7391 (set (match_dup 3) (match_dup 2))]
7392 ""
7393 "
7394 {
7395 operands[2] = gen_reg_rtx (Pmode);
7396 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
7397 }")
7399 (define_expand "save_stack_nonlocal"
7400 [(match_operand 0 "memory_operand" "")
7401 (match_operand 1 "register_operand" "")]
7402 ""
7403 "
7404 {
7405 rtx temp = gen_reg_rtx (Pmode);
7407 /* Copy the backchain to the first word, sp to the second. */
7408 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
7409 emit_move_insn (operand_subword (operands[0], 0, 0,
7410 (TARGET_32BIT ? DImode : TImode)),
7411 temp);
7412 emit_move_insn (operand_subword (operands[0], 1, 0,
7413 (TARGET_32BIT ? DImode : TImode)),
7414 operands[1]);
7415 DONE;
7416 }")
7418 (define_expand "restore_stack_nonlocal"
7419 [(match_operand 0 "register_operand" "")
7420 (match_operand 1 "memory_operand" "")]
7421 ""
7422 "
7423 {
7424 rtx temp = gen_reg_rtx (Pmode);
7426 /* Restore the backchain from the first word, sp from the second. */
7427 emit_move_insn (temp,
7428 operand_subword (operands[1], 0, 0,
7429 (TARGET_32BIT ? DImode : TImode)));
7430 emit_move_insn (operands[0],
7431 operand_subword (operands[1], 1, 0,
7432 (TARGET_32BIT ? DImode : TImode)));
7433 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
7434 DONE;
7435 }")
7437 ;; If we have -mminimal-toc, we need to reload r30 after a nonlocal goto.
7439 (define_insn "nonlocal_goto_receiver"
7440 [(unspec_volatile [(const_int 0)] 1)]
7441 "TARGET_TOC && TARGET_MINIMAL_TOC"
7442 "*
7443 {
7444 rs6000_output_load_toc_table (asm_out_file, 30);
7445 return \"\";
7446 }"
7447 [(set_attr "type" "load")])
7448 \f
7449 ;; A function pointer under AIX is a pointer to a data area whose first word
7450 ;; contains the actual address of the function, whose second word contains a
7451 ;; pointer to its TOC, and whose third word contains a value to place in the
7452 ;; static chain register (r11). Note that if we load the static chain, our
7453 ;; "trampoline" need not have any executable code.
7454 ;;
7455 ;; operands[0] is a register pointing to the 3 word descriptor
7456 ;; (aka, the function address)
7457 ;; operands[1] is the stack size to clean up
7458 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
7459 ;; (must be 0 for AIX)
7460 ;; operands[3] is location to store the TOC
7461 ;; operands[4] is the TOC register
7462 ;; operands[5] is the static chain register
7463 ;;
7464 ;; We do not break this into separate insns, so that the scheduler will not try
7465 ;; to move the load of the new TOC before any loads from the TOC.
7467 (define_insn "call_indirect_aix32"
7468 [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
7469 (match_operand 1 "const_int_operand" "n"))
7470 (use (match_operand 2 "const_int_operand" "n"))
7471 (use (match_operand 3 "offsettable_addr_operand" "p"))
7472 (use (match_operand 4 "register_operand" "r"))
7473 (clobber (match_operand 5 "register_operand" "=r"))
7474 (clobber (match_scratch:SI 6 "=&r"))
7475 (clobber (match_scratch:SI 7 "=l"))]
7476 "DEFAULT_ABI == ABI_AIX
7477 && (INTVAL (operands[2]) == CALL_NORMAL
7478 || (INTVAL (operands[2]) & CALL_LONG) != 0)"
7479 "{st|stw} %4,%a3\;{l|lwz} %6,0(%0)\;{l|lwz} %4,4(%0)\;mt%7 %6\;{l|lwz} %5,8(%0)\;{brl|blrl}\;{l|lwz} %4,%a3"
7480 [(set_attr "type" "load")
7481 (set_attr "length" "28")])
7483 (define_insn "call_indirect_aix64"
7484 [(call (mem:SI (match_operand:DI 0 "register_operand" "b"))
7485 (match_operand 1 "const_int_operand" "n"))
7486 (use (match_operand 2 "const_int_operand" "n"))
7487 (use (match_operand 3 "offsettable_addr_operand" "p"))
7488 (use (match_operand 4 "register_operand" "r"))
7489 (clobber (match_operand 5 "register_operand" "=r"))
7490 (clobber (match_scratch:SI 6 "=&r"))
7491 (clobber (match_scratch:SI 7 "=l"))]
7492 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX
7493 && (INTVAL (operands[2]) == CALL_NORMAL
7494 || (INTVAL (operands[2]) & CALL_LONG) != 0)"
7495 "stw %4,%a3\;ld %6,0(%0)\;ld %4,8(%0)\;mt%7 %6\;ld %5,16(%0)\;blrl\;ld %4,%a3"
7496 [(set_attr "type" "load")
7497 (set_attr "length" "28")])
7499 (define_insn "call_value_indirect_aix32"
7500 [(set (match_operand 0 "register_operand" "fg")
7501 (call (mem:SI (match_operand:SI 1 "register_operand" "b"))
7502 (match_operand 2 "const_int_operand" "n")))
7503 (use (match_operand 3 "const_int_operand" "n"))
7504 (use (match_operand 4 "offsettable_addr_operand" "p"))
7505 (use (match_operand 5 "register_operand" "r"))
7506 (clobber (match_operand 6 "register_operand" "=r"))
7507 (clobber (match_scratch:SI 7 "=&r"))
7508 (clobber (match_scratch:SI 8 "=l"))]
7509 "DEFAULT_ABI == ABI_AIX
7510 && (INTVAL (operands[3]) == CALL_NORMAL
7511 || (INTVAL (operands[3]) & CALL_LONG) != 0)"
7512 "{st|stw} %5,%a4\;{l|lwz} %7,0(%1)\;{l|lwz} %5,4(%1)\;mt%8 %7\;{l|lwz} %6,8(%1)\;{brl|blrl}\;{l|lwz} %5,%a4"
7513 [(set_attr "type" "load")
7514 (set_attr "length" "28")])
7516 (define_insn "call_value_indirect_aix64"
7517 [(set (match_operand 0 "register_operand" "fg")
7518 (call (mem:SI (match_operand:DI 1 "register_operand" "b"))
7519 (match_operand 2 "const_int_operand" "n")))
7520 (use (match_operand 3 "const_int_operand" "n"))
7521 (use (match_operand 4 "offsettable_addr_operand" "p"))
7522 (use (match_operand 5 "register_operand" "r"))
7523 (clobber (match_operand 6 "register_operand" "=r"))
7524 (clobber (match_scratch:SI 7 "=&r"))
7525 (clobber (match_scratch:SI 8 "=l"))]
7526 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX
7527 && (INTVAL (operands[3]) == CALL_NORMAL
7528 || (INTVAL (operands[3]) & CALL_LONG) != 0)"
7529 "stw %5,%a4\;ld %7,0(%1)\;ld %5,8(%1)\;mt%8 %7\;ld %6,16(%1)\;blrl\;ld %5,%a4"
7530 [(set_attr "type" "load")
7531 (set_attr "length" "28")])
7533 ;; A function pointer undef NT is a pointer to a data area whose first word
7534 ;; contains the actual address of the function, whose second word contains a
7535 ;; pointer to its TOC. The static chain is not stored under NT, which means
7536 ;; that we need a trampoline.
7537 ;;
7538 ;; operands[0] is an SImode pseudo in which we place the address of
7539 ;; the function.
7540 ;; operands[1] is the stack size to clean up
7541 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
7542 ;; (must be 0 for NT)
7543 ;; operands[3] is location to store the TOC
7544 ;; operands[4] is the TOC register
7545 ;;
7546 ;; We do not break this into separate insns, so that the scheduler will not try
7547 ;; to move the load of the new TOC before any loads from the TOC.
7549 (define_insn "call_indirect_nt"
7550 [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
7551 (match_operand 1 "const_int_operand" "n"))
7552 (use (match_operand 2 "const_int_operand" "n"))
7553 (use (match_operand 3 "offsettable_addr_operand" "p"))
7554 (use (match_operand 4 "register_operand" "r"))
7555 (clobber (match_scratch:SI 5 "=&r"))
7556 (clobber (match_scratch:SI 6 "=l"))]
7557 "DEFAULT_ABI == ABI_NT
7558 && (INTVAL (operands[2]) == CALL_NORMAL
7559 || (INTVAL (operands[2]) & CALL_LONG) != 0)"
7560 "{st|stw} %4,%a3\;{l|lwz} %5,0(%0)\;{l|lwz} %4,4(%0)\;mt%6 %5\;{brl|blrl}\;{l|lwz} %4,%a3"
7561 [(set_attr "type" "load")
7562 (set_attr "length" "24")])
7564 (define_insn "call_value_indirect_nt"
7565 [(set (match_operand 0 "register_operand" "fg")
7566 (call (mem:SI (match_operand:SI 1 "register_operand" "b"))
7567 (match_operand 2 "const_int_operand" "n")))
7568 (use (match_operand 3 "const_int_operand" "n"))
7569 (use (match_operand 4 "offsettable_addr_operand" "p"))
7570 (use (match_operand 5 "register_operand" "r"))
7571 (clobber (match_scratch:SI 6 "=&r"))
7572 (clobber (match_scratch:SI 7 "=l"))]
7573 "DEFAULT_ABI == ABI_NT
7574 && (INTVAL (operands[3]) == CALL_NORMAL
7575 || (INTVAL (operands[3]) & CALL_LONG) != 0)"
7576 "{st|stw} %5,%a4\;{l|lwz} %6,0(%1)\;{l|lwz} %5,4(%1)\;mt%7 %6\;{brl|blrl}\;{l|lwz} %5,%a4"
7577 [(set_attr "type" "load")
7578 (set_attr "length" "24")])
7580 ;; A function pointer under System V is just a normal pointer
7581 ;; operands[0] is the function pointer
7582 ;; operands[1] is the stack size to clean up
7583 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument which
7584 ;; indicates how to set cr1
7586 (define_insn "call_indirect_sysv"
7587 [(call (mem:SI (match_operand:SI 0 "register_operand" "l,l"))
7588 (match_operand 1 "const_int_operand" "n,n"))
7589 (use (match_operand 2 "const_int_operand" "O,n"))
7590 (clobber (match_scratch:SI 3 "=l,l"))]
7591 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS
7592 || DEFAULT_ABI == ABI_AIX_NODESC"
7593 "*
7594 {
7595 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7596 output_asm_insn (\"crxor 6,6,6\", operands);
7598 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7599 output_asm_insn (\"creqv 6,6,6\", operands);
7601 return \"{brl|blrl}\";
7602 }"
7603 [(set_attr "type" "jmpreg")
7604 (set_attr "length" "4,8")])
7606 (define_insn "call_value_indirect_sysv"
7607 [(set (match_operand 0 "register_operand" "=fg,fg")
7608 (call (mem:SI (match_operand:SI 1 "register_operand" "l,l"))
7609 (match_operand 2 "const_int_operand" "n,n")))
7610 (use (match_operand 3 "const_int_operand" "O,n"))
7611 (clobber (match_scratch:SI 4 "=l,l"))]
7612 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS
7613 || DEFAULT_ABI == ABI_AIX_NODESC"
7614 "*
7615 {
7616 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7617 output_asm_insn (\"crxor 6,6,6\", operands);
7619 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
7620 output_asm_insn (\"creqv 6,6,6\", operands);
7622 return \"{brl|blrl}\";
7623 }"
7624 [(set_attr "type" "jmpreg")
7625 (set_attr "length" "4,8")])
7627 ;; Now the definitions for the call and call_value insns
7628 (define_expand "call"
7629 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
7630 (match_operand 1 "" ""))
7631 (use (match_operand 2 "" ""))
7632 (clobber (scratch:SI))])]
7633 ""
7634 "
7635 {
7636 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
7637 abort ();
7639 operands[0] = XEXP (operands[0], 0);
7641 /* Convert NT DLL imports into an indirect call. */
7642 if (GET_CODE (operands[0]) == SYMBOL_REF
7643 && (INTVAL (operands[2]) & CALL_NT_DLLIMPORT) != 0)
7644 {
7645 operands[0] = rs6000_dll_import_ref (operands[0]);
7646 operands[2] = GEN_INT ((int)CALL_NORMAL);
7647 }
7649 if (GET_CODE (operands[0]) != SYMBOL_REF
7650 || (INTVAL (operands[2]) & CALL_LONG) != 0)
7651 {
7652 if (INTVAL (operands[2]) & CALL_LONG)
7653 operands[0] = rs6000_longcall_ref (operands[0]);
7655 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC
7656 || DEFAULT_ABI == ABI_SOLARIS)
7657 emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[0]),
7658 operands[1], operands[2]));
7659 else
7660 {
7661 rtx toc_reg = gen_rtx_REG (Pmode, 2);
7662 rtx toc_addr = RS6000_SAVE_TOC;
7664 if (DEFAULT_ABI == ABI_AIX)
7665 {
7666 /* AIX function pointers are really pointers to a three word
7667 area. */
7668 rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
7669 emit_call_insn (TARGET_32BIT
7670 ? gen_call_indirect_aix32
7671 (force_reg (Pmode, operands[0]),
7672 operands[1], operands[2],
7673 toc_addr, toc_reg, static_chain)
7674 : gen_call_indirect_aix64
7675 (force_reg (Pmode, operands[0]),
7676 operands[1], operands[2],
7677 toc_addr, toc_reg, static_chain));
7678 }
7679 else if (DEFAULT_ABI == ABI_NT)
7680 {
7681 /* NT function pointers are really pointers to a two word area */
7682 emit_call_insn (gen_call_indirect_nt (force_reg (Pmode,
7683 operands[0]),
7684 operands[1], operands[2],
7685 toc_addr, toc_reg));
7686 }
7687 else
7688 abort ();
7689 }
7690 DONE;
7691 }
7692 }")
7694 (define_expand "call_value"
7695 [(parallel [(set (match_operand 0 "" "")
7696 (call (mem:SI (match_operand 1 "address_operand" ""))
7697 (match_operand 2 "" "")))
7698 (use (match_operand 3 "" ""))
7699 (clobber (scratch:SI))])]
7700 ""
7701 "
7702 {
7703 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
7704 abort ();
7706 operands[1] = XEXP (operands[1], 0);
7708 /* Convert NT DLL imports into an indirect call. */
7709 if (GET_CODE (operands[1]) == SYMBOL_REF
7710 && (INTVAL (operands[3]) & CALL_NT_DLLIMPORT) != 0)
7711 {
7712 operands[1] = rs6000_dll_import_ref (operands[1]);
7713 operands[3] = GEN_INT ((int)CALL_NORMAL);
7714 }
7716 if (GET_CODE (operands[1]) != SYMBOL_REF
7717 || (INTVAL (operands[3]) & CALL_LONG) != 0)
7718 {
7719 if (INTVAL (operands[2]) & CALL_LONG)
7720 operands[1] = rs6000_longcall_ref (operands[1]);
7722 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC
7723 || DEFAULT_ABI == ABI_SOLARIS)
7724 emit_call_insn (gen_call_value_indirect_sysv (operands[0], operands[1],
7725 operands[2],
7726 operands[3]));
7727 else
7728 {
7729 rtx toc_reg = gen_rtx_REG (Pmode, 2);
7730 rtx toc_addr = RS6000_SAVE_TOC;
7732 if (DEFAULT_ABI == ABI_AIX)
7733 {
7734 /* AIX function pointers are really pointers to a three word
7735 area. */
7736 rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
7737 emit_call_insn (TARGET_32BIT
7738 ? gen_call_value_indirect_aix32
7739 (operands[0],
7740 force_reg (Pmode, operands[1]),
7741 operands[2], operands[3],
7742 toc_addr, toc_reg, static_chain)
7743 : gen_call_value_indirect_aix64
7744 (operands[0],
7745 force_reg (Pmode, operands[1]),
7746 operands[2], operands[3],
7747 toc_addr, toc_reg, static_chain));
7748 }
7749 else if (DEFAULT_ABI == ABI_NT)
7750 {
7751 /* NT function pointers are really pointers to a two word area */
7752 emit_call_insn (gen_call_value_indirect_nt
7753 (operands[0],
7754 force_reg (Pmode, operands[1]),
7755 operands[2], operands[3], toc_addr, toc_reg));
7756 }
7757 else
7758 abort ();
7759 }
7760 DONE;
7761 }
7762 }")
7764 ;; Call to function in current module. No TOC pointer reload needed.
7765 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
7766 ;; either the function was not prototyped, or it was prototyped as a
7767 ;; variable argument function. It is > 0 if FP registers were passed
7768 ;; and < 0 if they were not.
7770 (define_insn "*call_local32"
7771 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
7772 (match_operand 1 "" "g,g"))
7773 (use (match_operand:SI 2 "immediate_operand" "O,n"))
7774 (clobber (match_scratch:SI 3 "=l,l"))]
7775 "(INTVAL (operands[2]) & CALL_LONG) == 0"
7776 "*
7777 {
7778 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7779 output_asm_insn (\"crxor 6,6,6\", operands);
7781 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7782 output_asm_insn (\"creqv 6,6,6\", operands);
7784 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
7785 }"
7786 [(set_attr "type" "branch")
7787 (set_attr "length" "4,8")])
7789 (define_insn "*call_local64"
7790 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
7791 (match_operand 1 "" "g,g"))
7792 (use (match_operand:SI 2 "immediate_operand" "O,n"))
7793 (clobber (match_scratch:SI 3 "=l,l"))]
7794 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
7795 "*
7796 {
7797 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7798 output_asm_insn (\"crxor 6,6,6\", operands);
7800 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7801 output_asm_insn (\"creqv 6,6,6\", operands);
7803 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
7804 }"
7805 [(set_attr "type" "branch")
7806 (set_attr "length" "4,8")])
7808 (define_insn "*ret_call_local32"
7809 [(set (match_operand 0 "" "=fg,fg")
7810 (call (mem:SI
7811 (match_operand:SI 1 "current_file_function_operand" "s,s"))
7812 (match_operand 2 "" "g,g")))
7813 (use (match_operand:SI 3 "immediate_operand" "O,n"))
7814 (clobber (match_scratch:SI 4 "=l,l"))]
7815 "(INTVAL (operands[3]) & CALL_LONG) == 0"
7816 "*
7817 {
7818 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7819 output_asm_insn (\"crxor 6,6,6\", operands);
7821 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
7822 output_asm_insn (\"creqv 6,6,6\", operands);
7824 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
7825 }"
7826 [(set_attr "type" "branch")
7827 (set_attr "length" "4,8")])
7830 (define_insn "*ret_call_local64"
7831 [(set (match_operand 0 "" "=fg,fg")
7832 (call (mem:SI
7833 (match_operand:DI 1 "current_file_function_operand" "s,s"))
7834 (match_operand 2 "" "g,g")))
7835 (use (match_operand:SI 3 "immediate_operand" "O,n"))
7836 (clobber (match_scratch:SI 4 "=l,l"))]
7837 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
7838 "*
7839 {
7840 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7841 output_asm_insn (\"crxor 6,6,6\", operands);
7843 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
7844 output_asm_insn (\"creqv 6,6,6\", operands);
7846 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
7847 }"
7848 [(set_attr "type" "branch")
7849 (set_attr "length" "4,8")])
7851 ;; Call to function which may be in another module. Restore the TOC
7852 ;; pointer (r2) after the call unless this is System V.
7853 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
7854 ;; either the function was not prototyped, or it was prototyped as a
7855 ;; variable argument function. It is > 0 if FP registers were passed
7856 ;; and < 0 if they were not.
7858 (define_insn "*call_nonlocal_aix32"
7859 [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
7860 (match_operand 1 "" "fg,fg"))
7861 (use (match_operand:SI 2 "immediate_operand" "O,n"))
7862 (clobber (match_scratch:SI 3 "=l,l"))]
7863 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
7864 && (INTVAL (operands[2]) & CALL_LONG) == 0"
7865 "*
7866 {
7867 /* Indirect calls should go through call_indirect */
7868 if (GET_CODE (operands[0]) == REG)
7869 abort ();
7871 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7872 output_asm_insn (\"crxor 6,6,6\", operands);
7874 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7875 output_asm_insn (\"creqv 6,6,6\", operands);
7877 return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\";
7878 }"
7879 [(set_attr "type" "branch")
7880 (set_attr "length" "8,12")])
7882 (define_insn "*call_nonlocal_aix64"
7883 [(call (mem:SI (match_operand:DI 0 "call_operand" "s,s"))
7884 (match_operand 1 "" "fg,fg"))
7885 (use (match_operand:SI 2 "immediate_operand" "O,n"))
7886 (clobber (match_scratch:SI 3 "=l,l"))]
7887 "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
7888 && (INTVAL (operands[2]) & CALL_LONG) == 0"
7889 "*
7890 {
7891 /* Indirect calls should go through call_indirect */
7892 if (GET_CODE (operands[0]) == REG)
7893 abort ();
7895 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7896 output_asm_insn (\"crxor 6,6,6\", operands);
7898 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7899 output_asm_insn (\"creqv 6,6,6\", operands);
7901 return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\";
7902 }"
7903 [(set_attr "type" "branch")
7904 (set_attr "length" "8,12")])
7906 (define_insn "*call_nonlocal_sysv"
7907 [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
7908 (match_operand 1 "" "fg,fg"))
7909 (use (match_operand:SI 2 "immediate_operand" "O,n"))
7910 (clobber (match_scratch:SI 3 "=l,l"))]
7911 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4
7912 || DEFAULT_ABI == ABI_SOLARIS)
7913 && (INTVAL (operands[2]) & CALL_LONG) == 0"
7914 "*
7915 {
7916 /* Indirect calls should go through call_indirect */
7917 if (GET_CODE (operands[0]) == REG)
7918 abort ();
7920 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7921 output_asm_insn (\"crxor 6,6,6\", operands);
7923 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7924 output_asm_insn (\"creqv 6,6,6\", operands);
7926 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\";
7927 }"
7928 [(set_attr "type" "branch")
7929 (set_attr "length" "4,8")])
7931 (define_insn "*ret_call_nonlocal_aix32"
7932 [(set (match_operand 0 "" "=fg,fg")
7933 (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
7934 (match_operand 2 "" "fg,fg")))
7935 (use (match_operand:SI 3 "immediate_operand" "O,n"))
7936 (clobber (match_scratch:SI 4 "=l,l"))]
7937 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
7938 && (INTVAL (operands[3]) & CALL_LONG) == 0"
7939 "*
7940 {
7941 /* This should be handled by call_value_indirect */
7942 if (GET_CODE (operands[1]) == REG)
7943 abort ();
7945 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7946 output_asm_insn (\"crxor 6,6,6\", operands);
7948 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
7949 output_asm_insn (\"creqv 6,6,6\", operands);
7951 return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\";
7952 }"
7953 [(set_attr "type" "branch")
7954 (set_attr "length" "8,12")])
7956 (define_insn "*ret_call_nonlocal_aix64"
7957 [(set (match_operand 0 "" "=fg,fg")
7958 (call (mem:SI (match_operand:DI 1 "call_operand" "s,s"))
7959 (match_operand 2 "" "fg,fg")))
7960 (use (match_operand:SI 3 "immediate_operand" "O,n"))
7961 (clobber (match_scratch:SI 4 "=l,l"))]
7962 "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
7963 && (INTVAL (operands[3]) & CALL_LONG) == 0"
7964 "*
7965 {
7966 /* This should be handled by call_value_indirect */
7967 if (GET_CODE (operands[1]) == REG)
7968 abort ();
7970 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7971 output_asm_insn (\"crxor 6,6,6\", operands);
7973 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
7974 output_asm_insn (\"creqv 6,6,6\", operands);
7976 return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\";
7977 }"
7978 [(set_attr "type" "branch")
7979 (set_attr "length" "8,12")])
7981 (define_insn "*ret_call_nonlocal_sysv"
7982 [(set (match_operand 0 "" "=fg,fg")
7983 (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
7984 (match_operand 2 "" "fg,fg")))
7985 (use (match_operand:SI 3 "immediate_operand" "O,n"))
7986 (clobber (match_scratch:SI 4 "=l,l"))]
7987 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4
7988 || DEFAULT_ABI == ABI_SOLARIS)
7989 && (INTVAL (operands[3]) & CALL_LONG) == 0"
7990 "*
7991 {
7992 /* This should be handled by call_value_indirect */
7993 if (GET_CODE (operands[1]) == REG)
7994 abort ();
7996 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7997 output_asm_insn (\"crxor 6,6,6\", operands);
7999 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
8000 output_asm_insn (\"creqv 6,6,6\", operands);
8002 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\";
8003 }"
8004 [(set_attr "type" "branch")
8005 (set_attr "length" "4,8")])
8007 ;; Call subroutine returning any type.
8008 (define_expand "untyped_call"
8009 [(parallel [(call (match_operand 0 "" "")
8010 (const_int 0))
8011 (match_operand 1 "" "")
8012 (match_operand 2 "" "")])]
8013 ""
8014 "
8015 {
8016 int i;
8018 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx));
8020 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8021 {
8022 rtx set = XVECEXP (operands[2], 0, i);
8023 emit_move_insn (SET_DEST (set), SET_SRC (set));
8024 }
8026 /* The optimizer does not know that the call sets the function value
8027 registers we stored in the result block. We avoid problems by
8028 claiming that all hard registers are used and clobbered at this
8029 point. */
8030 emit_insn (gen_blockage ());
8032 DONE;
8033 }")
8035 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8036 ;; all of memory. This blocks insns from being moved across this point.
8038 (define_insn "blockage"
8039 [(unspec_volatile [(const_int 0)] 0)]
8040 ""
8041 "")
8043 ;; V.4 specific code to initialize the PIC register
8045 (define_insn "init_v4_pic"
8046 [(set (match_operand:SI 0 "register_operand" "=l")
8047 (unspec [(const_int 0)] 7))]
8048 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS"
8049 "bl _GLOBAL_OFFSET_TABLE_@local-4"
8050 [(set_attr "type" "branch")
8051 (set_attr "length" "4")])
8053 \f
8054 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
8055 ;; signed & unsigned, and one type of branch.
8056 ;;
8057 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
8058 ;; insns, and branches. We store the operands of compares until we see
8059 ;; how it is used.
8060 (define_expand "cmpsi"
8061 [(set (cc0)
8062 (compare (match_operand:SI 0 "gpc_reg_operand" "")
8063 (match_operand:SI 1 "reg_or_short_operand" "")))]
8064 ""
8065 "
8066 {
8067 /* Take care of the possibility that operands[1] might be negative but
8068 this might be a logical operation. That insn doesn't exist. */
8069 if (GET_CODE (operands[1]) == CONST_INT
8070 && INTVAL (operands[1]) < 0)
8071 operands[1] = force_reg (SImode, operands[1]);
8073 rs6000_compare_op0 = operands[0];
8074 rs6000_compare_op1 = operands[1];
8075 rs6000_compare_fp_p = 0;
8076 DONE;
8077 }")
8079 (define_expand "cmpdi"
8080 [(set (cc0)
8081 (compare (match_operand:DI 0 "gpc_reg_operand" "")
8082 (match_operand:DI 1 "reg_or_short_operand" "")))]
8083 "TARGET_POWERPC64"
8084 "
8085 {
8086 /* Take care of the possibility that operands[1] might be negative but
8087 this might be a logical operation. That insn doesn't exist. */
8088 if (GET_CODE (operands[1]) == CONST_INT
8089 && INTVAL (operands[1]) < 0)
8090 operands[1] = force_reg (DImode, operands[1]);
8092 rs6000_compare_op0 = operands[0];
8093 rs6000_compare_op1 = operands[1];
8094 rs6000_compare_fp_p = 0;
8095 DONE;
8096 }")
8098 (define_expand "cmpsf"
8099 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
8100 (match_operand:SF 1 "gpc_reg_operand" "")))]
8101 "TARGET_HARD_FLOAT"
8102 "
8103 {
8104 rs6000_compare_op0 = operands[0];
8105 rs6000_compare_op1 = operands[1];
8106 rs6000_compare_fp_p = 1;
8107 DONE;
8108 }")
8110 (define_expand "cmpdf"
8111 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
8112 (match_operand:DF 1 "gpc_reg_operand" "")))]
8113 "TARGET_HARD_FLOAT"
8114 "
8115 {
8116 rs6000_compare_op0 = operands[0];
8117 rs6000_compare_op1 = operands[1];
8118 rs6000_compare_fp_p = 1;
8119 DONE;
8120 }")
8122 (define_expand "beq"
8123 [(set (match_dup 2) (match_dup 1))
8124 (set (pc)
8125 (if_then_else (eq (match_dup 2)
8126 (const_int 0))
8127 (label_ref (match_operand 0 "" ""))
8128 (pc)))]
8129 ""
8130 "
8131 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8132 operands[1] = gen_rtx_COMPARE (mode,
8133 rs6000_compare_op0, rs6000_compare_op1);
8134 operands[2] = gen_reg_rtx (mode);
8135 }")
8137 (define_expand "bne"
8138 [(set (match_dup 2) (match_dup 1))
8139 (set (pc)
8140 (if_then_else (ne (match_dup 2)
8141 (const_int 0))
8142 (label_ref (match_operand 0 "" ""))
8143 (pc)))]
8144 ""
8145 "
8146 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8147 operands[1] = gen_rtx_COMPARE (mode,
8148 rs6000_compare_op0, rs6000_compare_op1);
8149 operands[2] = gen_reg_rtx (mode);
8150 }")
8152 (define_expand "blt"
8153 [(set (match_dup 2) (match_dup 1))
8154 (set (pc)
8155 (if_then_else (lt (match_dup 2)
8156 (const_int 0))
8157 (label_ref (match_operand 0 "" ""))
8158 (pc)))]
8159 ""
8160 "
8161 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8162 operands[1] = gen_rtx_COMPARE (mode,
8163 rs6000_compare_op0, rs6000_compare_op1);
8164 operands[2] = gen_reg_rtx (mode);
8165 }")
8167 (define_expand "bgt"
8168 [(set (match_dup 2) (match_dup 1))
8169 (set (pc)
8170 (if_then_else (gt (match_dup 2)
8171 (const_int 0))
8172 (label_ref (match_operand 0 "" ""))
8173 (pc)))]
8174 ""
8175 "
8176 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8177 operands[1] = gen_rtx_COMPARE (mode,
8178 rs6000_compare_op0, rs6000_compare_op1);
8179 operands[2] = gen_reg_rtx (mode);
8180 }")
8182 (define_expand "ble"
8183 [(set (match_dup 2) (match_dup 1))
8184 (set (pc)
8185 (if_then_else (le (match_dup 2)
8186 (const_int 0))
8187 (label_ref (match_operand 0 "" ""))
8188 (pc)))]
8189 ""
8190 "
8191 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8192 operands[1] = gen_rtx_COMPARE (mode,
8193 rs6000_compare_op0, rs6000_compare_op1);
8194 operands[2] = gen_reg_rtx (mode);
8195 }")
8197 (define_expand "bge"
8198 [(set (match_dup 2) (match_dup 1))
8199 (set (pc)
8200 (if_then_else (ge (match_dup 2)
8201 (const_int 0))
8202 (label_ref (match_operand 0 "" ""))
8203 (pc)))]
8204 ""
8205 "
8206 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8207 operands[1] = gen_rtx_COMPARE (mode,
8208 rs6000_compare_op0, rs6000_compare_op1);
8209 operands[2] = gen_reg_rtx (mode);
8210 }")
8212 (define_expand "bgtu"
8213 [(set (match_dup 2) (match_dup 1))
8214 (set (pc)
8215 (if_then_else (gtu (match_dup 2)
8216 (const_int 0))
8217 (label_ref (match_operand 0 "" ""))
8218 (pc)))]
8219 ""
8220 "
8221 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8222 rs6000_compare_op0, rs6000_compare_op1);
8223 operands[2] = gen_reg_rtx (CCUNSmode);
8224 }")
8226 (define_expand "bltu"
8227 [(set (match_dup 2) (match_dup 1))
8228 (set (pc)
8229 (if_then_else (ltu (match_dup 2)
8230 (const_int 0))
8231 (label_ref (match_operand 0 "" ""))
8232 (pc)))]
8233 ""
8234 "
8235 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8236 rs6000_compare_op0, rs6000_compare_op1);
8237 operands[2] = gen_reg_rtx (CCUNSmode);
8238 }")
8240 (define_expand "bgeu"
8241 [(set (match_dup 2) (match_dup 1))
8242 (set (pc)
8243 (if_then_else (geu (match_dup 2)
8244 (const_int 0))
8245 (label_ref (match_operand 0 "" ""))
8246 (pc)))]
8247 ""
8248 "
8249 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8250 rs6000_compare_op0, rs6000_compare_op1);
8251 operands[2] = gen_reg_rtx (CCUNSmode);
8252 }")
8254 (define_expand "bleu"
8255 [(set (match_dup 2) (match_dup 1))
8256 (set (pc)
8257 (if_then_else (leu (match_dup 2)
8258 (const_int 0))
8259 (label_ref (match_operand 0 "" ""))
8260 (pc)))]
8261 ""
8262 "
8263 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8264 rs6000_compare_op0, rs6000_compare_op1);
8265 operands[2] = gen_reg_rtx (CCUNSmode);
8266 }")
8268 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
8269 ;; For SEQ, likewise, except that comparisons with zero should be done
8270 ;; with an scc insns. However, due to the order that combine see the
8271 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
8272 ;; the cases we don't want to handle.
8273 (define_expand "seq"
8274 [(set (match_dup 2) (match_dup 1))
8275 (set (match_operand:SI 0 "gpc_reg_operand" "")
8276 (eq:SI (match_dup 2) (const_int 0)))]
8277 ""
8278 "
8279 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8280 operands[1] = gen_rtx_COMPARE (mode,
8281 rs6000_compare_op0, rs6000_compare_op1);
8282 operands[2] = gen_reg_rtx (mode);
8283 }")
8285 (define_expand "sne"
8286 [(set (match_dup 2) (match_dup 1))
8287 (set (match_operand:SI 0 "gpc_reg_operand" "")
8288 (ne:SI (match_dup 2) (const_int 0)))]
8289 ""
8290 "
8291 { if (! rs6000_compare_fp_p)
8292 FAIL;
8294 operands[1] = gen_rtx_COMPARE (CCFPmode,
8295 rs6000_compare_op0, rs6000_compare_op1);
8296 operands[2] = gen_reg_rtx (CCFPmode);
8297 }")
8299 ;; A > 0 is best done using the portable sequence, so fail in that case.
8300 (define_expand "sgt"
8301 [(set (match_dup 2) (match_dup 1))
8302 (set (match_operand:SI 0 "gpc_reg_operand" "")
8303 (gt:SI (match_dup 2) (const_int 0)))]
8304 ""
8305 "
8306 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8308 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
8309 FAIL;
8311 operands[1] = gen_rtx_COMPARE (mode,
8312 rs6000_compare_op0, rs6000_compare_op1);
8313 operands[2] = gen_reg_rtx (mode);
8314 }")
8316 ;; A < 0 is best done in the portable way for A an integer.
8317 (define_expand "slt"
8318 [(set (match_dup 2) (match_dup 1))
8319 (set (match_operand:SI 0 "gpc_reg_operand" "")
8320 (lt:SI (match_dup 2) (const_int 0)))]
8321 ""
8322 "
8323 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8325 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
8326 FAIL;
8328 operands[1] = gen_rtx_COMPARE (mode,
8329 rs6000_compare_op0, rs6000_compare_op1);
8330 operands[2] = gen_reg_rtx (mode);
8331 }")
8333 (define_expand "sge"
8334 [(set (match_dup 2) (match_dup 1))
8335 (set (match_operand:SI 0 "gpc_reg_operand" "")
8336 (ge:SI (match_dup 2) (const_int 0)))]
8337 ""
8338 "
8339 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8340 operands[1] = gen_rtx_COMPARE (mode,
8341 rs6000_compare_op0, rs6000_compare_op1);
8342 operands[2] = gen_reg_rtx (mode);
8343 }")
8345 ;; A <= 0 is best done the portable way for A an integer.
8346 (define_expand "sle"
8347 [(set (match_dup 2) (match_dup 1))
8348 (set (match_operand:SI 0 "gpc_reg_operand" "")
8349 (le:SI (match_dup 2) (const_int 0)))]
8350 ""
8351 "
8352 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
8354 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
8355 FAIL;
8357 operands[1] = gen_rtx_COMPARE (mode,
8358 rs6000_compare_op0, rs6000_compare_op1);
8359 operands[2] = gen_reg_rtx (mode);
8360 }")
8362 (define_expand "sgtu"
8363 [(set (match_dup 2) (match_dup 1))
8364 (set (match_operand:SI 0 "gpc_reg_operand" "")
8365 (gtu:SI (match_dup 2) (const_int 0)))]
8366 ""
8367 "
8368 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8369 rs6000_compare_op0, rs6000_compare_op1);
8370 operands[2] = gen_reg_rtx (CCUNSmode);
8371 }")
8373 (define_expand "sltu"
8374 [(set (match_dup 2) (match_dup 1))
8375 (set (match_operand:SI 0 "gpc_reg_operand" "")
8376 (ltu:SI (match_dup 2) (const_int 0)))]
8377 ""
8378 "
8379 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8380 rs6000_compare_op0, rs6000_compare_op1);
8381 operands[2] = gen_reg_rtx (CCUNSmode);
8382 }")
8384 (define_expand "sgeu"
8385 [(set (match_dup 2) (match_dup 1))
8386 (set (match_operand:SI 0 "gpc_reg_operand" "")
8387 (geu:SI (match_dup 2) (const_int 0)))]
8388 ""
8389 "
8390 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8391 rs6000_compare_op0, rs6000_compare_op1);
8392 operands[2] = gen_reg_rtx (CCUNSmode);
8393 }")
8395 (define_expand "sleu"
8396 [(set (match_dup 2) (match_dup 1))
8397 (set (match_operand:SI 0 "gpc_reg_operand" "")
8398 (leu:SI (match_dup 2) (const_int 0)))]
8399 ""
8400 "
8401 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
8402 rs6000_compare_op0, rs6000_compare_op1);
8403 operands[2] = gen_reg_rtx (CCUNSmode);
8404 }")
8405 \f
8406 ;; Here are the actual compare insns.
8407 (define_insn ""
8408 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
8409 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
8410 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
8411 ""
8412 "{cmp%I2|cmpw%I2} %0,%1,%2"
8413 [(set_attr "type" "compare")])
8415 (define_insn ""
8416 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
8417 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
8418 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
8419 "TARGET_POWERPC64"
8420 "cmpd%I2 %0,%1,%2"
8421 [(set_attr "type" "compare")])
8423 ;; If we are comparing a register for equality with a large constant,
8424 ;; we can do this with an XOR followed by a compare. But we need a scratch
8425 ;; register for the result of the XOR.
8427 (define_split
8428 [(set (match_operand:CC 0 "cc_reg_operand" "")
8429 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
8430 (match_operand:SI 2 "non_short_cint_operand" "")))
8431 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
8432 "find_single_use (operands[0], insn, 0)
8433 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
8434 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
8435 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
8436 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
8437 "
8438 {
8439 /* Get the constant we are comparing against, C, and see what it looks like
8440 sign-extended to 16 bits. Then see what constant could be XOR'ed
8441 with C to get the sign-extended value. */
8443 int c = INTVAL (operands[2]);
8444 int sextc = (c << 16) >> 16;
8445 int xorv = c ^ sextc;
8447 operands[4] = GEN_INT (xorv);
8448 operands[5] = GEN_INT (sextc);
8449 }")
8451 (define_insn ""
8452 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
8453 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
8454 (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
8455 ""
8456 "{cmpl%I2|cmplw%I2} %0,%1,%W2"
8457 [(set_attr "type" "compare")])
8459 (define_insn ""
8460 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
8461 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
8462 (match_operand:DI 2 "reg_or_u_short_operand" "rI")))]
8463 ""
8464 "cmpld%I2 %0,%1,%W2"
8465 [(set_attr "type" "compare")])
8467 ;; The following two insns don't exist as single insns, but if we provide
8468 ;; them, we can swap an add and compare, which will enable us to overlap more
8469 ;; of the required delay between a compare and branch. We generate code for
8470 ;; them by splitting.
8472 (define_insn ""
8473 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
8474 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
8475 (match_operand:SI 2 "short_cint_operand" "i")))
8476 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8477 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
8478 ""
8479 "#"
8480 [(set_attr "length" "8")])
8482 (define_insn ""
8483 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
8484 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
8485 (match_operand:SI 2 "u_short_cint_operand" "i")))
8486 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8487 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
8488 ""
8489 "#"
8490 [(set_attr "length" "8")])
8492 (define_split
8493 [(set (match_operand:CC 3 "cc_reg_operand" "")
8494 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
8495 (match_operand:SI 2 "short_cint_operand" "")))
8496 (set (match_operand:SI 0 "gpc_reg_operand" "")
8497 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
8498 ""
8499 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
8500 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
8502 (define_split
8503 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
8504 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
8505 (match_operand:SI 2 "u_short_cint_operand" "")))
8506 (set (match_operand:SI 0 "gpc_reg_operand" "")
8507 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
8508 ""
8509 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
8510 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
8512 (define_insn ""
8513 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
8514 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
8515 (match_operand:SF 2 "gpc_reg_operand" "f")))]
8516 "TARGET_HARD_FLOAT"
8517 "fcmpu %0,%1,%2"
8518 [(set_attr "type" "fpcompare")])
8520 (define_insn ""
8521 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
8522 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
8523 (match_operand:DF 2 "gpc_reg_operand" "f")))]
8524 "TARGET_HARD_FLOAT"
8525 "fcmpu %0,%1,%2"
8526 [(set_attr "type" "fpcompare")])
8527 \f
8528 ;; Now we have the scc insns. We can do some combinations because of the
8529 ;; way the machine works.
8530 ;;
8531 ;; Note that this is probably faster if we can put an insn between the
8532 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
8533 ;; cases the insns below which don't use an intermediate CR field will
8534 ;; be used instead.
8535 (define_insn ""
8536 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8537 (match_operator:SI 1 "scc_comparison_operator"
8538 [(match_operand 2 "cc_reg_operand" "y")
8539 (const_int 0)]))]
8540 ""
8541 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
8542 [(set_attr "length" "12")])
8544 (define_insn ""
8545 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8546 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
8547 [(match_operand 2 "cc_reg_operand" "y")
8548 (const_int 0)])
8549 (const_int 0)))
8550 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
8551 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
8552 ""
8553 "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1"
8554 [(set_attr "type" "delayed_compare")
8555 (set_attr "length" "12")])
8557 (define_insn ""
8558 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8559 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
8560 [(match_operand 2 "cc_reg_operand" "y")
8561 (const_int 0)])
8562 (match_operand:SI 3 "const_int_operand" "n")))]
8563 ""
8564 "*
8565 {
8566 int is_bit = ccr_bit (operands[1], 1);
8567 int put_bit = 31 - (INTVAL (operands[3]) & 31);
8568 int count;
8570 if (is_bit >= put_bit)
8571 count = is_bit - put_bit;
8572 else
8573 count = 32 - (put_bit - is_bit);
8575 operands[4] = GEN_INT (count);
8576 operands[5] = GEN_INT (put_bit);
8578 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
8579 }"
8580 [(set_attr "length" "12")])
8582 (define_insn ""
8583 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8584 (compare:CC
8585 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
8586 [(match_operand 2 "cc_reg_operand" "y")
8587 (const_int 0)])
8588 (match_operand:SI 3 "const_int_operand" "n"))
8589 (const_int 0)))
8590 (set (match_operand:SI 4 "gpc_reg_operand" "=r")
8591 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
8592 (match_dup 3)))]
8593 ""
8594 "*
8595 {
8596 int is_bit = ccr_bit (operands[1], 1);
8597 int put_bit = 31 - (INTVAL (operands[3]) & 31);
8598 int count;
8600 if (is_bit >= put_bit)
8601 count = is_bit - put_bit;
8602 else
8603 count = 32 - (put_bit - is_bit);
8605 operands[5] = GEN_INT (count);
8606 operands[6] = GEN_INT (put_bit);
8608 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
8609 }"
8610 [(set_attr "type" "delayed_compare")
8611 (set_attr "length" "12")])
8613 ;; If we are comparing the result of two comparisons, this can be done
8614 ;; using creqv or crxor.
8616 (define_insn ""
8617 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
8618 (compare:CCEQ (match_operator 1 "scc_comparison_operator"
8619 [(match_operand 2 "cc_reg_operand" "y")
8620 (const_int 0)])
8621 (match_operator 3 "scc_comparison_operator"
8622 [(match_operand 4 "cc_reg_operand" "y")
8623 (const_int 0)])))]
8624 "REGNO (operands[2]) != REGNO (operands[4])"
8625 "*
8626 {
8627 enum rtx_code code1, code2;
8629 code1 = GET_CODE (operands[1]);
8630 code2 = GET_CODE (operands[3]);
8632 if ((code1 == EQ || code1 == LT || code1 == GT
8633 || code1 == LTU || code1 == GTU
8634 || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
8635 !=
8636 (code2 == EQ || code2 == LT || code2 == GT
8637 || code2 == LTU || code2 == GTU
8638 || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
8639 return \"%C1%C3crxor %E0,%j1,%j3\";
8640 else
8641 return \"%C1%C3creqv %E0,%j1,%j3\";
8642 }"
8643 [(set_attr "length" "12")])
8645 ;; There is a 3 cycle delay between consecutive mfcr instructions
8646 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
8648 (define_peephole
8649 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8650 (match_operator:SI 1 "scc_comparison_operator"
8651 [(match_operand 2 "cc_reg_operand" "y")
8652 (const_int 0)]))
8653 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
8654 (match_operator:SI 4 "scc_comparison_operator"
8655 [(match_operand 5 "cc_reg_operand" "y")
8656 (const_int 0)]))]
8657 "REGNO (operands[2]) != REGNO (operands[5])"
8658 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
8659 [(set_attr "length" "20")])
8661 ;; There are some scc insns that can be done directly, without a compare.
8662 ;; These are faster because they don't involve the communications between
8663 ;; the FXU and branch units. In fact, we will be replacing all of the
8664 ;; integer scc insns here or in the portable methods in emit_store_flag.
8665 ;;
8666 ;; Also support (neg (scc ..)) since that construct is used to replace
8667 ;; branches, (plus (scc ..) ..) since that construct is common and
8668 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
8669 ;; cases where it is no more expensive than (neg (scc ..)).
8671 ;; Have reload force a constant into a register for the simple insns that
8672 ;; otherwise won't accept constants. We do this because it is faster than
8673 ;; the cmp/mfcr sequence we would otherwise generate.
8675 (define_insn ""
8676 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8677 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8678 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
8679 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
8680 ""
8681 "@
8682 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
8683 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
8684 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
8685 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
8686 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
8687 [(set_attr "length" "12,8,12,12,12")])
8689 (define_insn ""
8690 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
8691 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
8692 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
8693 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
8694 "TARGET_POWERPC64"
8695 "@
8696 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
8697 subfic %3,%1,0\;adde %0,%3,%1
8698 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
8699 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
8700 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
8701 [(set_attr "length" "12,8,12,12,12")])
8703 (define_insn ""
8704 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
8705 (compare:CC
8706 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8707 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
8708 (const_int 0)))
8709 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8710 (eq:SI (match_dup 1) (match_dup 2)))
8711 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
8712 ""
8713 "@
8714 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
8715 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
8716 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
8717 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
8718 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0"
8719 [(set_attr "type" "compare")
8720 (set_attr "length" "12,8,12,12,12")])
8722 (define_insn ""
8723 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
8724 (compare:CC
8725 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
8726 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))
8727 (const_int 0)))
8728 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
8729 (eq:DI (match_dup 1) (match_dup 2)))
8730 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
8731 "TARGET_POWERPC64"
8732 "@
8733 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
8734 subfic %3,%1,0\;adde. %0,%3,%1
8735 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
8736 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
8737 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0"
8738 [(set_attr "type" "compare")
8739 (set_attr "length" "12,8,12,12,12")])
8741 ;; We have insns of the form shown by the first define_insn below. If
8742 ;; there is something inside the comparison operation, we must split it.
8743 (define_split
8744 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8745 (plus:SI (match_operator 1 "comparison_operator"
8746 [(match_operand:SI 2 "" "")
8747 (match_operand:SI 3
8748 "reg_or_cint_operand" "")])
8749 (match_operand:SI 4 "gpc_reg_operand" "")))
8750 (clobber (match_operand:SI 5 "register_operand" ""))]
8751 "! gpc_reg_operand (operands[2], SImode)"
8752 [(set (match_dup 5) (match_dup 2))
8753 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
8754 (match_dup 4)))])
8756 (define_insn ""
8757 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8758 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8759 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
8760 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
8761 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
8762 ""
8763 "@
8764 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
8765 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
8766 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
8767 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
8768 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
8769 [(set_attr "length" "12,8,12,12,12")])
8771 (define_insn ""
8772 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
8773 (compare:CC
8774 (plus:SI
8775 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8776 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
8777 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
8778 (const_int 0)))
8779 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
8780 ""
8781 "@
8782 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
8783 {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
8784 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
8785 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
8786 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
8787 [(set_attr "type" "compare")
8788 (set_attr "length" "12,8,12,12,12")])
8790 (define_insn ""
8791 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
8792 (compare:CC
8793 (plus:SI
8794 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8795 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
8796 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
8797 (const_int 0)))
8798 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8799 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8800 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
8801 ""
8802 "@
8803 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
8804 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
8805 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
8806 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
8807 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
8808 [(set_attr "type" "compare")
8809 (set_attr "length" "12,8,12,12,12")])
8811 (define_insn ""
8812 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8813 (neg:SI
8814 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8815 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
8816 ""
8817 "@
8818 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
8819 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
8820 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
8821 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
8822 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
8823 [(set_attr "length" "12,8,12,12,12")])
8825 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
8826 ;; since it nabs/sr is just as fast.
8827 (define_insn ""
8828 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8829 (lshiftrt:SI (neg:SI
8830 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
8831 (const_int 31)))
8832 (clobber (match_scratch:SI 2 "=&r"))]
8833 "!TARGET_POWER"
8834 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
8835 [(set_attr "length" "8")])
8837 (define_insn ""
8838 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8839 (lshiftrt:DI (neg:DI
8840 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
8841 (const_int 63)))
8842 (clobber (match_scratch:DI 2 "=&r"))]
8843 "TARGET_POWERPC64"
8844 "addic %2,%1,-1\;subfe %0,%2,%1"
8845 [(set_attr "length" "8")])
8847 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
8848 (define_insn ""
8849 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8850 (plus:SI (lshiftrt:SI
8851 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
8852 (const_int 31))
8853 (match_operand:SI 2 "gpc_reg_operand" "r")))
8854 (clobber (match_scratch:SI 3 "=&r"))]
8855 ""
8856 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
8857 [(set_attr "length" "8")])
8859 (define_insn ""
8860 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8861 (plus:DI (lshiftrt:DI
8862 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
8863 (const_int 63))
8864 (match_operand:DI 2 "gpc_reg_operand" "r")))
8865 (clobber (match_scratch:DI 3 "=&r"))]
8866 "TARGET_POWERPC64"
8867 "addic %3,%1,-1\;addze %0,%2"
8868 [(set_attr "length" "8")])
8870 (define_insn ""
8871 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8872 (compare:CC
8873 (plus:SI (lshiftrt:SI
8874 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
8875 (const_int 31))
8876 (match_operand:SI 2 "gpc_reg_operand" "r"))
8877 (const_int 0)))
8878 (clobber (match_scratch:SI 3 "=&r"))]
8879 ""
8880 "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2"
8881 [(set_attr "type" "compare")
8882 (set_attr "length" "8")])
8884 (define_insn ""
8885 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8886 (compare:CC
8887 (plus:DI (lshiftrt:DI
8888 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
8889 (const_int 63))
8890 (match_operand:DI 2 "gpc_reg_operand" "r"))
8891 (const_int 0)))
8892 (clobber (match_scratch:DI 3 "=&r"))]
8893 "TARGET_POWERPC64"
8894 "addic %3,%1,-1\;addze. %3,%2"
8895 [(set_attr "type" "compare")
8896 (set_attr "length" "8")])
8898 (define_insn ""
8899 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
8900 (compare:CC
8901 (plus:SI (lshiftrt:SI
8902 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
8903 (const_int 31))
8904 (match_operand:SI 2 "gpc_reg_operand" "r"))
8905 (const_int 0)))
8906 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8907 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
8908 (match_dup 2)))
8909 (clobber (match_scratch:SI 3 "=&r"))]
8910 ""
8911 "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2"
8912 [(set_attr "type" "compare")
8913 (set_attr "length" "8")])
8915 (define_insn ""
8916 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
8917 (compare:CC
8918 (plus:DI (lshiftrt:DI
8919 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
8920 (const_int 63))
8921 (match_operand:DI 2 "gpc_reg_operand" "r"))
8922 (const_int 0)))
8923 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
8924 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
8925 (match_dup 2)))
8926 (clobber (match_scratch:DI 3 "=&r"))]
8927 "TARGET_POWERPC64"
8928 "addic %3,%1,-1\;addze. %0,%2"
8929 [(set_attr "type" "compare")
8930 (set_attr "length" "8")])
8932 (define_insn ""
8933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8934 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8935 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
8936 (clobber (match_scratch:SI 3 "=r,X"))]
8937 "TARGET_POWER"
8938 "@
8939 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
8940 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
8941 [(set_attr "length" "12")])
8943 (define_insn ""
8944 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
8945 (compare:CC
8946 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8947 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
8948 (const_int 0)))
8949 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8950 (le:SI (match_dup 1) (match_dup 2)))
8951 (clobber (match_scratch:SI 3 "=r,X"))]
8952 "TARGET_POWER"
8953 "@
8954 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
8955 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31"
8956 [(set_attr "type" "compare,delayed_compare")
8957 (set_attr "length" "12")])
8959 (define_insn ""
8960 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8961 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8962 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
8963 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
8964 (clobber (match_scratch:SI 4 "=&r,&r"))]
8965 "TARGET_POWER"
8966 "@
8967 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
8968 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
8969 [(set_attr "length" "12")])
8971 (define_insn ""
8972 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
8973 (compare:CC
8974 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8975 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
8976 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8977 (const_int 0)))
8978 (clobber (match_scratch:SI 4 "=&r,&r"))]
8979 "TARGET_POWER"
8980 "@
8981 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
8982 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3"
8983 [(set_attr "type" "compare")
8984 (set_attr "length" "12")])
8986 (define_insn ""
8987 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
8988 (compare:CC
8989 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8990 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
8991 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8992 (const_int 0)))
8993 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8994 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8995 (clobber (match_scratch:SI 4 "=&r,&r"))]
8996 "TARGET_POWER"
8997 "@
8998 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
8999 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3"
9000 [(set_attr "type" "compare")
9001 (set_attr "length" "12")])
9003 (define_insn ""
9004 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9005 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9006 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
9007 "TARGET_POWER"
9008 "@
9009 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
9010 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
9011 [(set_attr "length" "12")])
9013 (define_insn ""
9014 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9015 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9016 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
9017 ""
9018 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
9019 [(set_attr "length" "12")])
9021 (define_insn ""
9022 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
9023 (compare:CC
9024 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9025 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9026 (const_int 0)))
9027 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9028 (leu:SI (match_dup 1) (match_dup 2)))]
9029 ""
9030 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
9031 [(set_attr "type" "compare")
9032 (set_attr "length" "12")])
9034 (define_insn ""
9035 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9036 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9037 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9038 (match_operand:SI 3 "gpc_reg_operand" "r")))
9039 (clobber (match_scratch:SI 4 "=&r"))]
9040 ""
9041 "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
9042 [(set_attr "length" "8")])
9044 (define_insn ""
9045 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9046 (compare:CC
9047 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9048 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9049 (match_operand:SI 3 "gpc_reg_operand" "r"))
9050 (const_int 0)))
9051 (clobber (match_scratch:SI 4 "=&r"))]
9052 ""
9053 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3"
9054 [(set_attr "type" "compare")
9055 (set_attr "length" "8")])
9057 (define_insn ""
9058 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
9059 (compare:CC
9060 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9061 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9062 (match_operand:SI 3 "gpc_reg_operand" "r"))
9063 (const_int 0)))
9064 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9065 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9066 (clobber (match_scratch:SI 4 "=&r"))]
9067 ""
9068 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3"
9069 [(set_attr "type" "compare")
9070 (set_attr "length" "8")])
9072 (define_insn ""
9073 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9074 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9075 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
9076 ""
9077 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
9078 [(set_attr "length" "12")])
9080 (define_insn ""
9081 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9082 (and:SI (neg:SI
9083 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9084 (match_operand:SI 2 "reg_or_short_operand" "rI")))
9085 (match_operand:SI 3 "gpc_reg_operand" "r")))
9086 (clobber (match_scratch:SI 4 "=&r"))]
9087 ""
9088 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
9089 [(set_attr "length" "12")])
9091 (define_insn ""
9092 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9093 (compare:CC
9094 (and:SI (neg:SI
9095 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9096 (match_operand:SI 2 "reg_or_short_operand" "rI")))
9097 (match_operand:SI 3 "gpc_reg_operand" "r"))
9098 (const_int 0)))
9099 (clobber (match_scratch:SI 4 "=&r"))]
9100 ""
9101 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
9102 [(set_attr "type" "compare")
9103 (set_attr "length" "12")])
9105 (define_insn ""
9106 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
9107 (compare:CC
9108 (and:SI (neg:SI
9109 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9110 (match_operand:SI 2 "reg_or_short_operand" "rI")))
9111 (match_operand:SI 3 "gpc_reg_operand" "r"))
9112 (const_int 0)))
9113 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9114 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
9115 (clobber (match_scratch:SI 4 "=&r"))]
9116 ""
9117 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
9118 [(set_attr "type" "compare")
9119 (set_attr "length" "12")])
9121 (define_insn ""
9122 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9123 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9124 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
9125 "TARGET_POWER"
9126 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
9127 [(set_attr "length" "12")])
9129 (define_insn ""
9130 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
9131 (compare:CC
9132 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9133 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9134 (const_int 0)))
9135 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9136 (lt:SI (match_dup 1) (match_dup 2)))]
9137 "TARGET_POWER"
9138 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
9139 [(set_attr "type" "delayed_compare")
9140 (set_attr "length" "12")])
9142 (define_insn ""
9143 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9144 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9145 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9146 (match_operand:SI 3 "gpc_reg_operand" "r")))
9147 (clobber (match_scratch:SI 4 "=&r"))]
9148 "TARGET_POWER"
9149 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
9150 [(set_attr "length" "12")])
9152 (define_insn ""
9153 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9154 (compare:CC
9155 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9156 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9157 (match_operand:SI 3 "gpc_reg_operand" "r"))
9158 (const_int 0)))
9159 (clobber (match_scratch:SI 4 "=&r"))]
9160 "TARGET_POWER"
9161 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
9162 [(set_attr "type" "compare")
9163 (set_attr "length" "12")])
9165 (define_insn ""
9166 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
9167 (compare:CC
9168 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9169 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9170 (match_operand:SI 3 "gpc_reg_operand" "r"))
9171 (const_int 0)))
9172 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9173 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9174 (clobber (match_scratch:SI 4 "=&r"))]
9175 "TARGET_POWER"
9176 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
9177 [(set_attr "type" "compare")
9178 (set_attr "length" "12")])
9180 (define_insn ""
9181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9182 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9183 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
9184 "TARGET_POWER"
9185 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
9186 [(set_attr "length" "12")])
9188 (define_insn ""
9189 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9190 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9191 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
9192 ""
9193 "@
9194 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
9195 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
9196 [(set_attr "length" "12")])
9198 (define_insn ""
9199 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
9200 (compare:CC
9201 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9202 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
9203 (const_int 0)))
9204 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9205 (ltu:SI (match_dup 1) (match_dup 2)))]
9206 ""
9207 "@
9208 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
9209 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
9210 [(set_attr "type" "compare")
9211 (set_attr "length" "12")])
9213 (define_insn ""
9214 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
9215 (plus:SI
9216 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
9217 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
9218 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
9219 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
9220 ""
9221 "@
9222 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
9223 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
9224 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
9225 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
9226 [(set_attr "length" "12")])
9228 (define_insn ""
9229 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
9230 (compare:CC
9231 (plus:SI (ltu:SI
9232 (match_operand:SI 1 "gpc_reg_operand" "r,r")
9233 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
9234 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9235 (const_int 0)))
9236 (clobber (match_scratch:SI 4 "=&r,&r"))]
9237 ""
9238 "@
9239 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
9240 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"
9241 [(set_attr "type" "compare")
9242 (set_attr "length" "12")])
9244 (define_insn ""
9245 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
9246 (compare:CC
9247 (plus:SI (ltu:SI
9248 (match_operand:SI 1 "gpc_reg_operand" "r,r")
9249 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
9250 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9251 (const_int 0)))
9252 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9253 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9254 (clobber (match_scratch:SI 4 "=&r,&r"))]
9255 ""
9256 "@
9257 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
9258 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
9259 [(set_attr "type" "compare")
9260 (set_attr "length" "12")])
9262 (define_insn ""
9263 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9264 (neg:SI (ltu:SI
9265 (match_operand:SI 1 "gpc_reg_operand" "r,r")
9266 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
9267 ""
9268 "@
9269 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
9270 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
9271 [(set_attr "length" "8")])
9273 (define_insn ""
9274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9275 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9276 (match_operand:SI 2 "reg_or_short_operand" "rI")))
9277 (clobber (match_scratch:SI 3 "=r"))]
9278 "TARGET_POWER"
9279 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
9280 [(set_attr "length" "12")])
9282 (define_insn ""
9283 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
9284 (compare:CC
9285 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9286 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9287 (const_int 0)))
9288 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9289 (ge:SI (match_dup 1) (match_dup 2)))
9290 (clobber (match_scratch:SI 3 "=r"))]
9291 "TARGET_POWER"
9292 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3"
9293 [(set_attr "type" "compare")
9294 (set_attr "length" "12")])
9296 (define_insn ""
9297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9298 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9299 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9300 (match_operand:SI 3 "gpc_reg_operand" "r")))
9301 (clobber (match_scratch:SI 4 "=&r"))]
9302 "TARGET_POWER"
9303 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
9304 [(set_attr "length" "12")])
9306 (define_insn ""
9307 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9308 (compare:CC
9309 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9310 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9311 (match_operand:SI 3 "gpc_reg_operand" "r"))
9312 (const_int 0)))
9313 (clobber (match_scratch:SI 4 "=&r"))]
9314 "TARGET_POWER"
9315 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
9316 [(set_attr "type" "compare")
9317 (set_attr "length" "12")])
9319 (define_insn ""
9320 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
9321 (compare:CC
9322 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9323 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9324 (match_operand:SI 3 "gpc_reg_operand" "r"))
9325 (const_int 0)))
9326 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9327 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9328 (clobber (match_scratch:SI 4 "=&r"))]
9329 "TARGET_POWER"
9330 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
9331 [(set_attr "type" "compare")
9332 (set_attr "length" "12")])
9334 (define_insn ""
9335 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9336 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9337 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
9338 "TARGET_POWER"
9339 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
9340 [(set_attr "length" "12")])
9342 ;; This is (and (neg (ge X (const_int 0))) Y).
9343 (define_insn ""
9344 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9345 (and:SI (neg:SI
9346 (lshiftrt:SI
9347 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
9348 (const_int 31)))
9349 (match_operand:SI 2 "gpc_reg_operand" "r")))
9350 (clobber (match_scratch:SI 3 "=&r"))]
9351 ""
9352 "{srai|srawi} %3,%1,31\;andc %0,%2,%3"
9353 [(set_attr "length" "8")])
9355 (define_insn ""
9356 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9357 (compare:CC
9358 (and:SI (neg:SI
9359 (lshiftrt:SI
9360 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
9361 (const_int 31)))
9362 (match_operand:SI 2 "gpc_reg_operand" "r"))
9363 (const_int 0)))
9364 (clobber (match_scratch:SI 3 "=&r"))]
9365 ""
9366 "{srai|srawi} %3,%1,31\;andc. %3,%2,%3"
9367 [(set_attr "type" "compare")
9368 (set_attr "length" "8")])
9370 (define_insn ""
9371 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
9372 (compare:CC
9373 (and:SI (neg:SI
9374 (lshiftrt:SI
9375 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
9376 (const_int 31)))
9377 (match_operand:SI 2 "gpc_reg_operand" "r"))
9378 (const_int 0)))
9379 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9380 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
9381 (const_int 31)))
9382 (match_dup 2)))
9383 (clobber (match_scratch:SI 3 "=&r"))]
9384 ""
9385 "{srai|srawi} %3,%1,31\;andc. %0,%2,%3"
9386 [(set_attr "type" "compare")
9387 (set_attr "length" "8")])
9389 (define_insn ""
9390 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9391 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9392 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
9393 ""
9394 "@
9395 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
9396 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
9397 [(set_attr "length" "12")])
9399 (define_insn ""
9400 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
9401 (compare:CC
9402 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9403 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
9404 (const_int 0)))
9405 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9406 (geu:SI (match_dup 1) (match_dup 2)))]
9407 ""
9408 "@
9409 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
9410 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
9411 [(set_attr "type" "compare")
9412 (set_attr "length" "12")])
9414 (define_insn ""
9415 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9416 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9417 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
9418 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
9419 (clobber (match_scratch:SI 4 "=&r,&r"))]
9420 ""
9421 "@
9422 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
9423 {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
9424 [(set_attr "length" "8")])
9426 (define_insn ""
9427 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
9428 (compare:CC
9429 (plus:SI (geu:SI
9430 (match_operand:SI 1 "gpc_reg_operand" "r,r")
9431 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
9432 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9433 (const_int 0)))
9434 (clobber (match_scratch:SI 4 "=&r,&r"))]
9435 ""
9436 "@
9437 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
9438 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
9439 [(set_attr "type" "compare")
9440 (set_attr "length" "8")])
9442 (define_insn ""
9443 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
9444 (compare:CC
9445 (plus:SI (geu:SI
9446 (match_operand:SI 1 "gpc_reg_operand" "r,r")
9447 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
9448 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9449 (const_int 0)))
9450 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9451 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9452 (clobber (match_scratch:SI 4 "=&r,&r"))]
9453 ""
9454 "@
9455 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
9456 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
9457 [(set_attr "type" "compare")
9458 (set_attr "length" "8")])
9460 (define_insn ""
9461 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9462 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9463 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
9464 ""
9465 "@
9466 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
9467 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
9468 [(set_attr "length" "12")])
9470 (define_insn ""
9471 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9472 (and:SI (neg:SI
9473 (geu:SI
9474 (match_operand:SI 1 "gpc_reg_operand" "r,r")
9475 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
9476 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
9477 (clobber (match_scratch:SI 4 "=&r,&r"))]
9478 ""
9479 "@
9480 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
9481 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
9482 [(set_attr "length" "12")])
9484 (define_insn ""
9485 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
9486 (compare:CC
9487 (and:SI (neg:SI
9488 (geu:SI
9489 (match_operand:SI 1 "gpc_reg_operand" "r,r")
9490 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
9491 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9492 (const_int 0)))
9493 (clobber (match_scratch:SI 4 "=&r,&r"))]
9494 ""
9495 "@
9496 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9497 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
9498 [(set_attr "type" "compare")
9499 (set_attr "length" "12")])
9501 (define_insn ""
9502 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
9503 (compare:CC
9504 (and:SI (neg:SI
9505 (geu:SI
9506 (match_operand:SI 1 "gpc_reg_operand" "r,r")
9507 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
9508 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9509 (const_int 0)))
9510 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9511 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
9512 (clobber (match_scratch:SI 4 "=&r,&r"))]
9513 ""
9514 "@
9515 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
9516 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
9517 [(set_attr "type" "compare")
9518 (set_attr "length" "12")])
9520 (define_insn ""
9521 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9522 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9523 (const_int 0)))]
9524 ""
9525 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
9526 [(set_attr "length" "12")])
9528 (define_insn ""
9529 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
9530 (compare:CC
9531 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9532 (const_int 0))
9533 (const_int 0)))
9534 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9535 (gt:SI (match_dup 1) (const_int 0)))]
9536 ""
9537 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31"
9538 [(set_attr "type" "delayed_compare")
9539 (set_attr "length" "12")])
9541 (define_insn ""
9542 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9543 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9544 (match_operand:SI 2 "reg_or_short_operand" "r")))]
9545 "TARGET_POWER"
9546 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
9547 [(set_attr "length" "12")])
9549 (define_insn ""
9550 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
9551 (compare:CC
9552 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9553 (match_operand:SI 2 "reg_or_short_operand" "r"))
9554 (const_int 0)))
9555 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9556 (gt:SI (match_dup 1) (match_dup 2)))]
9557 "TARGET_POWER"
9558 "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
9559 [(set_attr "type" "delayed_compare")
9560 (set_attr "length" "12")])
9562 (define_insn ""
9563 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9564 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9565 (const_int 0))
9566 (match_operand:SI 2 "gpc_reg_operand" "r")))
9567 (clobber (match_scratch:SI 3 "=&r"))]
9568 ""
9569 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
9570 [(set_attr "length" "12")])
9572 (define_insn ""
9573 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9574 (compare:CC
9575 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9576 (const_int 0))
9577 (match_operand:SI 2 "gpc_reg_operand" "r"))
9578 (const_int 0)))
9579 (clobber (match_scratch:SI 3 "=&r"))]
9580 ""
9581 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2"
9582 [(set_attr "type" "compare")
9583 (set_attr "length" "12")])
9585 (define_insn ""
9586 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
9587 (compare:CC
9588 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9589 (const_int 0))
9590 (match_operand:SI 2 "gpc_reg_operand" "r"))
9591 (const_int 0)))
9592 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9593 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
9594 (clobber (match_scratch:SI 3 "=&r"))]
9595 ""
9596 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2"
9597 [(set_attr "type" "compare")
9598 (set_attr "length" "12")])
9600 (define_insn ""
9601 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9602 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9603 (match_operand:SI 2 "reg_or_short_operand" "r"))
9604 (match_operand:SI 3 "gpc_reg_operand" "r")))
9605 (clobber (match_scratch:SI 4 "=&r"))]
9606 "TARGET_POWER"
9607 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
9608 [(set_attr "length" "12")])
9610 (define_insn ""
9611 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
9612 (compare:CC
9613 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9614 (match_operand:SI 2 "reg_or_short_operand" "r"))
9615 (match_operand:SI 3 "gpc_reg_operand" "r"))
9616 (const_int 0)))
9617 (clobber (match_scratch:SI 4 "=&r"))]
9618 "TARGET_POWER"
9619 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
9620 [(set_attr "type" "compare")
9621 (set_attr "length" "12")])
9623 (define_insn ""
9624 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
9625 (compare:CC
9626 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9627 (match_operand:SI 2 "reg_or_short_operand" "r"))
9628 (match_operand:SI 3 "gpc_reg_operand" "r"))
9629 (const_int 0)))
9630 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9631 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9632 (clobber (match_scratch:SI 4 "=&r"))]
9633 "TARGET_POWER"
9634 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
9635 [(set_attr "type" "compare")
9636 (set_attr "length" "12")])
9638 (define_insn ""
9639 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9640 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9641 (const_int 0))))]
9642 ""
9643 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
9644 [(set_attr "length" "12")])
9646 (define_insn ""
9647 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9648 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9649 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
9650 "TARGET_POWER"
9651 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
9652 [(set_attr "length" "12")])
9654 (define_insn ""
9655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9656 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9657 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
9658 ""
9659 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
9660 [(set_attr "length" "12")])
9662 (define_insn ""
9663 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
9664 (compare:CC
9665 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9666 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9667 (const_int 0)))
9668 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9669 (gtu:SI (match_dup 1) (match_dup 2)))]
9670 ""
9671 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
9672 [(set_attr "type" "compare")
9673 (set_attr "length" "12")])
9675 (define_insn ""
9676 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
9677 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
9678 (match_operand:SI 2 "reg_or_short_operand" "I,r,rI"))
9679 (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))
9680 (clobber (match_scratch:SI 4 "=&r,&r,&r"))]
9681 ""
9682 "@
9683 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
9684 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
9685 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
9686 [(set_attr "length" "8,12,12")])
9688 (define_insn ""
9689 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
9690 (compare:CC
9691 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9692 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
9693 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9694 (const_int 0)))
9695 (clobber (match_scratch:SI 4 "=&r,&r"))]
9696 ""
9697 "@
9698 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
9699 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
9700 [(set_attr "type" "compare")
9701 (set_attr "length" "8,12")])
9703 (define_insn ""
9704 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
9705 (compare:CC
9706 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9707 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
9708 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9709 (const_int 0)))
9710 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9711 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9712 (clobber (match_scratch:SI 4 "=&r,&r"))]
9713 ""
9714 "@
9715 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
9716 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
9717 [(set_attr "type" "compare")
9718 (set_attr "length" "8,12")])
9720 (define_insn ""
9721 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9722 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9723 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
9724 ""
9725 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
9726 [(set_attr "length" "8")])
9727 \f
9728 ;; Define both directions of branch and return. If we need a reload
9729 ;; register, we'd rather use CR0 since it is much easier to copy a
9730 ;; register CC value to there.
9732 (define_insn ""
9733 [(set (pc)
9734 (if_then_else (match_operator 1 "branch_comparison_operator"
9735 [(match_operand 2
9736 "cc_reg_operand" "x,?y")
9737 (const_int 0)])
9738 (label_ref (match_operand 0 "" ""))
9739 (pc)))]
9740 ""
9741 "*
9742 {
9743 if (get_attr_length (insn) == 8)
9744 return \"%C1bc %t1,%j1,%l0\";
9745 else
9746 return \"%C1bc %T1,%j1,%$+8\;b %l0\";
9748 }"
9749 [(set_attr "type" "branch")])
9751 (define_insn ""
9752 [(set (pc)
9753 (if_then_else (match_operator 0 "branch_comparison_operator"
9754 [(match_operand 1
9755 "cc_reg_operand" "x,?y")
9756 (const_int 0)])
9757 (return)
9758 (pc)))]
9759 "direct_return ()"
9760 "{%C0bcr|%C0bclr} %t0,%j0"
9761 [(set_attr "type" "branch")
9762 (set_attr "length" "8")])
9764 (define_insn ""
9765 [(set (pc)
9766 (if_then_else (match_operator 1 "branch_comparison_operator"
9767 [(match_operand 2
9768 "cc_reg_operand" "x,?y")
9769 (const_int 0)])
9770 (pc)
9771 (label_ref (match_operand 0 "" ""))))]
9772 ""
9773 "*
9774 {
9775 if (get_attr_length (insn) == 8)
9776 return \"%C1bc %T1,%j1,%l0\";
9777 else
9778 return \"%C1bc %t1,%j1,%$+8\;b %l0\";
9779 }"
9780 [(set_attr "type" "branch")])
9782 (define_insn ""
9783 [(set (pc)
9784 (if_then_else (match_operator 0 "branch_comparison_operator"
9785 [(match_operand 1
9786 "cc_reg_operand" "x,?y")
9787 (const_int 0)])
9788 (pc)
9789 (return)))]
9790 "direct_return ()"
9791 "{%C0bcr|%C0bclr} %T0,%j0"
9792 [(set_attr "type" "branch")
9793 (set_attr "length" "8")])
9795 ;; Unconditional branch and return.
9797 (define_insn "jump"
9798 [(set (pc)
9799 (label_ref (match_operand 0 "" "")))]
9800 ""
9801 "b %l0"
9802 [(set_attr "type" "branch")])
9804 (define_insn "return"
9805 [(return)]
9806 "direct_return ()"
9807 "{br|blr}"
9808 [(set_attr "type" "jmpreg")])
9810 (define_insn "indirect_jump"
9811 [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
9812 ""
9813 "@
9814 bctr
9815 {br|blr}"
9816 [(set_attr "type" "jmpreg")])
9818 (define_insn ""
9819 [(set (pc) (match_operand:DI 0 "register_operand" "c,l"))]
9820 "TARGET_POWERPC64"
9821 "@
9822 bctr
9823 {br|blr}"
9824 [(set_attr "type" "jmpreg")])
9826 ;; Table jump for switch statements:
9827 (define_expand "tablejump"
9828 [(use (match_operand 0 "" ""))
9829 (use (label_ref (match_operand 1 "" "")))]
9830 ""
9831 "
9832 {
9833 if (TARGET_32BIT)
9834 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
9835 else
9836 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
9837 DONE;
9838 }")
9840 (define_expand "tablejumpsi"
9841 [(set (match_dup 3)
9842 (plus:SI (match_operand:SI 0 "" "")
9843 (match_dup 2)))
9844 (parallel [(set (pc) (match_dup 3))
9845 (use (label_ref (match_operand 1 "" "")))])]
9846 ""
9847 "
9848 { operands[0] = force_reg (SImode, operands[0]);
9849 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
9850 operands[3] = gen_reg_rtx (SImode);
9851 }")
9853 (define_expand "tablejumpdi"
9854 [(set (match_dup 3)
9855 (plus:DI (match_operand:DI 0 "" "")
9856 (match_dup 2)))
9857 (parallel [(set (pc) (match_dup 3))
9858 (use (label_ref (match_operand 1 "" "")))])]
9859 ""
9860 "
9861 { operands[0] = force_reg (DImode, operands[0]);
9862 operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (SImode, operands[1]));
9863 operands[3] = gen_reg_rtx (DImode);
9864 }")
9866 (define_insn ""
9867 [(set (pc)
9868 (match_operand:SI 0 "register_operand" "c,l"))
9869 (use (label_ref (match_operand 1 "" "")))]
9870 ""
9871 "@
9872 bctr
9873 {br|blr}"
9874 [(set_attr "type" "jmpreg")])
9876 (define_insn ""
9877 [(set (pc)
9878 (match_operand:DI 0 "register_operand" "c,l"))
9879 (use (label_ref (match_operand 1 "" "")))]
9880 "TARGET_POWERPC64"
9881 "@
9882 bctr
9883 {br|blr}"
9884 [(set_attr "type" "jmpreg")])
9886 (define_insn "nop"
9887 [(const_int 0)]
9888 ""
9889 "{cror 0,0,0|nop}")
9890 \f
9891 ;; Define the subtract-one-and-jump insns, starting with the template
9892 ;; so loop.c knows what to generate.
9894 (define_expand "decrement_and_branch_on_count"
9895 [(parallel [(set (pc)
9896 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
9897 (const_int 1))
9898 (label_ref (match_operand 1 "" ""))
9899 (pc)))
9900 (set (match_dup 0)
9901 (plus:SI (match_dup 0)
9902 (const_int -1)))
9903 (clobber (match_scratch:CC 2 ""))
9904 (clobber (match_scratch:SI 3 ""))])]
9905 ""
9906 "")
9908 ;; We need to be able to do this for any operand, including MEM, or we
9909 ;; will cause reload to blow up since we don't allow output reloads on
9910 ;; JUMP_INSNs.
9911 ;; In order that the length attribute is calculated correctly, the
9912 ;; label MUST be operand 0.
9914 (define_insn ""
9915 [(set (pc)
9916 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
9917 (const_int 1))
9918 (label_ref (match_operand 0 "" ""))
9919 (pc)))
9920 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9921 (plus:SI (match_dup 1)
9922 (const_int -1)))
9923 (clobber (match_scratch:CC 3 "=X,&x,&x"))
9924 (clobber (match_scratch:SI 4 "=X,X,r"))]
9925 ""
9926 "*
9927 {
9928 if (which_alternative != 0)
9929 return \"#\";
9930 else if (get_attr_length (insn) == 8)
9931 return \"{bdn|bdnz} %l0\";
9932 else
9933 return \"bdz %$+8\;b %l0\";
9934 }"
9935 [(set_attr "type" "branch")
9936 (set_attr "length" "*,12,16")])
9938 (define_insn ""
9939 [(set (pc)
9940 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
9941 (const_int 1))
9942 (pc)
9943 (label_ref (match_operand 0 "" ""))))
9944 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9945 (plus:SI (match_dup 1)
9946 (const_int -1)))
9947 (clobber (match_scratch:CC 3 "=X,&x,&x"))
9948 (clobber (match_scratch:SI 4 "=X,X,r"))]
9949 ""
9950 "*
9951 {
9952 if (which_alternative != 0)
9953 return \"#\";
9954 else if (get_attr_length (insn) == 8)
9955 return \"bdz %l0\";
9956 else
9957 return \"{bdn|bdnz} %$+8\;b %l0\";
9958 }"
9959 [(set_attr "type" "branch")
9960 (set_attr "length" "*,12,16")])
9962 ;; Similar, but we can use GE since we have a REG_NONNEG.
9963 (define_insn ""
9964 [(set (pc)
9965 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
9966 (const_int 0))
9967 (label_ref (match_operand 0 "" ""))
9968 (pc)))
9969 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9970 (plus:SI (match_dup 1)
9971 (const_int -1)))
9972 (clobber (match_scratch:CC 3 "=X,&x,&X"))
9973 (clobber (match_scratch:SI 4 "=X,X,r"))]
9974 "find_reg_note (insn, REG_NONNEG, 0)"
9975 "*
9976 {
9977 if (which_alternative != 0)
9978 return \"#\";
9979 else if (get_attr_length (insn) == 8)
9980 return \"{bdn|bdnz} %l0\";
9981 else
9982 return \"bdz %$+8\;b %l0\";
9983 }"
9984 [(set_attr "type" "branch")
9985 (set_attr "length" "*,12,16")])
9987 (define_insn ""
9988 [(set (pc)
9989 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
9990 (const_int 0))
9991 (pc)
9992 (label_ref (match_operand 0 "" ""))))
9993 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9994 (plus:SI (match_dup 1)
9995 (const_int -1)))
9996 (clobber (match_scratch:CC 3 "=X,&x,&X"))
9997 (clobber (match_scratch:SI 4 "=X,X,r"))]
9998 "find_reg_note (insn, REG_NONNEG, 0)"
9999 "*
10000 {
10001 if (which_alternative != 0)
10002 return \"#\";
10003 else if (get_attr_length (insn) == 8)
10004 return \"bdz %l0\";
10005 else
10006 return \"{bdn|bdnz} %$+8\;b %l0\";
10007 }"
10008 [(set_attr "type" "branch")
10009 (set_attr "length" "*,12,16")])
10011 (define_insn ""
10012 [(set (pc)
10013 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
10014 (const_int 1))
10015 (label_ref (match_operand 0 "" ""))
10016 (pc)))
10017 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
10018 (plus:SI (match_dup 1)
10019 (const_int -1)))
10020 (clobber (match_scratch:CC 3 "=X,&x,&x"))
10021 (clobber (match_scratch:SI 4 "=X,X,r"))]
10022 ""
10023 "*
10024 {
10025 if (which_alternative != 0)
10026 return \"#\";
10027 else if (get_attr_length (insn) == 8)
10028 return \"bdz %l0\";
10029 else
10030 return \"{bdn|bdnz} %$+8\;b %l0\";
10031 }"
10032 [(set_attr "type" "branch")
10033 (set_attr "length" "*,12,16")])
10035 (define_insn ""
10036 [(set (pc)
10037 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
10038 (const_int 1))
10039 (pc)
10040 (label_ref (match_operand 0 "" ""))))
10041 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
10042 (plus:SI (match_dup 1)
10043 (const_int -1)))
10044 (clobber (match_scratch:CC 3 "=X,&x,&x"))
10045 (clobber (match_scratch:SI 4 "=X,X,r"))]
10046 ""
10047 "*
10048 {
10049 if (which_alternative != 0)
10050 return \"#\";
10051 else if (get_attr_length (insn) == 8)
10052 return \"{bdn|bdnz} %l0\";
10053 else
10054 return \"bdz %$+8\;b %l0\";
10055 }"
10056 [(set_attr "type" "branch")
10057 (set_attr "length" "*,12,16")])
10059 (define_split
10060 [(set (pc)
10061 (if_then_else
10062 (match_operator 2 "comparison_operator"
10063 [(match_operand:SI 1 "gpc_reg_operand" "")
10064 (const_int 1)])
10065 (match_operand 5 "" "")
10066 (match_operand 6 "" "")))
10067 (set (match_operand:SI 0 "gpc_reg_operand" "")
10068 (plus:SI (match_dup 1)
10069 (const_int -1)))
10070 (clobber (match_scratch:CC 3 ""))
10071 (clobber (match_scratch:SI 4 ""))]
10072 "reload_completed"
10073 [(parallel [(set (match_dup 3)
10074 (compare:CC (plus:SI (match_dup 1)
10075 (const_int -1))
10076 (const_int 0)))
10077 (set (match_dup 0)
10078 (plus:SI (match_dup 1)
10079 (const_int -1)))])
10080 (set (pc) (if_then_else (match_dup 7)
10081 (match_dup 5)
10082 (match_dup 6)))]
10083 "
10084 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
10085 const0_rtx); }")
10087 (define_split
10088 [(set (pc)
10089 (if_then_else
10090 (match_operator 2 "comparison_operator"
10091 [(match_operand:SI 1 "gpc_reg_operand" "")
10092 (const_int 1)])
10093 (match_operand 5 "" "")
10094 (match_operand 6 "" "")))
10095 (set (match_operand:SI 0 "general_operand" "")
10096 (plus:SI (match_dup 1) (const_int -1)))
10097 (clobber (match_scratch:CC 3 ""))
10098 (clobber (match_scratch:SI 4 ""))]
10099 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
10100 [(parallel [(set (match_dup 3)
10101 (compare:CC (plus:SI (match_dup 1)
10102 (const_int -1))
10103 (const_int 0)))
10104 (set (match_dup 4)
10105 (plus:SI (match_dup 1)
10106 (const_int -1)))])
10107 (set (match_dup 0)
10108 (match_dup 4))
10109 (set (pc) (if_then_else (match_dup 7)
10110 (match_dup 5)
10111 (match_dup 6)))]
10112 "
10113 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
10114 const0_rtx); }")