1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0
, i960_compare_op1
;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment
;
53 static int i960_last_maxbitalignment
;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type
;
60 /* The leaf-procedure return register. Set only if this is a leaf routine. */
62 static int i960_leaf_ret_reg
;
64 /* True if replacing tail calls with jumps is OK. */
66 static int tail_call_ok
;
68 /* A string containing a list of insns to emit in the epilogue so as to
69 restore all registers saved by the prologue. Created by the prologue
70 code as it saves registers away. */
72 char epilogue_string
[1000];
74 /* A unique number (per function) for return labels. */
76 static int ret_label
= 0;
78 /* This is true if FNDECL is either a varargs or a stdarg function.
79 This is used to help identify functions that use an argument block. */
81 #define VARARGS_STDARG_FUNCTION(FNDECL) \
82 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
83 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
84 || current_function_varargs)
86 /* Handle pragmas for compatibility with Intel's compilers. */
88 /* ??? This is incomplete, since it does not handle all pragmas that the
89 intel compilers understand. */
92 process_pragma (finput
, t
)
100 if (TREE_CODE (t
) != IDENTIFIER_NODE
)
103 pname
= IDENTIFIER_POINTER (t
);
105 if (strcmp (pname
, "align") == 0)
113 } while (c
== ' ' || c
== '\t');
117 while (c
>= '0' && c
<= '9')
119 if (s
< buf
+ sizeof buf
- 1)
125 /* We had to read a non-numerical character to get out of the
126 while loop---often a newline. So, we have to put it back to
127 make sure we continue to parse everything properly. */
134 /* Return to last alignment. */
135 align
= i960_last_maxbitalignment
/ 8;
142 i960_last_maxbitalignment
= i960_maxbitalignment
;
143 i960_maxbitalignment
= align
* 8;
147 /* Silently ignore bad values. */
151 /* NOTE: ic960 R3.0 pragma align definition:
153 #pragma align [(size)] | (identifier=size[,...])
154 #pragma noalign [(identifier)[,...]]
156 (all parens are optional)
158 - size is [1,2,4,8,16]
159 - noalign means size==1
160 - applies only to component elements of a struct (and union?)
161 - identifier applies to structure tag (only)
162 - missing identifier means next struct
164 - alignment rules for bitfields need more investigation */
169 /* Should be pragma 'far' or equivalent for callx/balx here. */
174 /* Initialize variables before compiling any files. */
179 if (TARGET_IC_COMPAT2_0
)
181 i960_maxbitalignment
= 8;
182 i960_last_maxbitalignment
= 128;
186 i960_maxbitalignment
= 128;
187 i960_last_maxbitalignment
= 8;
191 /* Return true if OP can be used as the source of an fp move insn. */
194 fpmove_src_operand (op
, mode
)
196 enum machine_mode mode
;
198 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
202 /* Return true if OP is a register or zero. */
205 reg_or_zero_operand (op
, mode
)
207 enum machine_mode mode
;
209 return register_operand (op
, mode
) || op
== const0_rtx
;
213 /* Return truth value of whether OP can be used as an operands in a three
214 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
217 arith_operand (op
, mode
)
219 enum machine_mode mode
;
221 return (register_operand (op
, mode
) || literal (op
, mode
));
224 /* Return truth value of whether OP can be used as an operands in a three
225 address logic insn, possibly complementing OP, of mode MODE. */
228 logic_operand (op
, mode
)
230 enum machine_mode mode
;
232 return (register_operand (op
, mode
)
233 || (GET_CODE (op
) == CONST_INT
234 && INTVAL(op
) >= -32 && INTVAL(op
) < 32));
237 /* Return true if OP is a register or a valid floating point literal. */
240 fp_arith_operand (op
, mode
)
242 enum machine_mode mode
;
244 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
247 /* Return true is OP is a register or a valid signed integer literal. */
250 signed_arith_operand (op
, mode
)
252 enum machine_mode mode
;
254 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
257 /* Return truth value of whether OP is a integer which fits the
258 range constraining immediate operands in three-address insns. */
263 enum machine_mode mode
;
265 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
268 /* Return true if OP is a float constant of 1. */
271 fp_literal_one (op
, mode
)
273 enum machine_mode mode
;
275 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
278 /* Return true if OP is a float constant of 0. */
281 fp_literal_zero (op
, mode
)
283 enum machine_mode mode
;
285 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
288 /* Return true if OP is a valid floating point literal. */
293 enum machine_mode mode
;
295 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
298 /* Return true if OP is a valid signed immediate constant. */
301 signed_literal(op
, mode
)
303 enum machine_mode mode
;
305 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
308 /* Return truth value of statement that OP is a symbolic memory
309 operand of mode MODE. */
312 symbolic_memory_operand (op
, mode
)
314 enum machine_mode mode
;
316 if (GET_CODE (op
) == SUBREG
)
317 op
= SUBREG_REG (op
);
318 if (GET_CODE (op
) != MEM
)
321 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
322 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
325 /* Return truth value of whether OP is EQ or NE. */
330 enum machine_mode mode
;
332 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
335 /* OP is an integer register or a constant. */
338 arith32_operand (op
, mode
)
340 enum machine_mode mode
;
342 if (register_operand (op
, mode
))
344 return (CONSTANT_P (op
));
347 /* Return true if OP is an integer constant which is a power of 2. */
350 power2_operand (op
,mode
)
352 enum machine_mode mode
;
354 if (GET_CODE (op
) != CONST_INT
)
357 return exact_log2 (INTVAL (op
)) >= 0;
360 /* Return true if OP is an integer constant which is the complement of a
364 cmplpower2_operand (op
, mode
)
366 enum machine_mode mode
;
368 if (GET_CODE (op
) != CONST_INT
)
371 return exact_log2 (~ INTVAL (op
)) >= 0;
374 /* If VAL has only one bit set, return the index of that bit. Otherwise
383 for (i
= 0; val
!= 0; i
++, val
>>= 1)
395 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
396 The return value indicates how many consecutive non-zero bits exist
397 if this is a mask. This is the same as the next function, except that
398 it does not indicate what the start and stop bit positions are. */
404 register int start
, end
, i
;
407 for (i
= 0; val
!= 0; val
>>= 1, i
++)
417 /* Still looking for the first bit. */
421 /* We've seen the start of a bit sequence, and now a zero. There
422 must be more one bits, otherwise we would have exited the loop.
423 Therefore, it is not a mask. */
428 /* The bit string has ones from START to END bit positions only. */
429 return end
- start
+ 1;
432 /* If VAL is a mask, then return nonzero, with S set to the starting bit
433 position and E set to the ending bit position of the mask. The return
434 value indicates how many consecutive bits exist in the mask. This is
435 the same as the previous function, except that it also indicates the
436 start and end bit positions of the mask. */
443 register int start
, end
, i
;
447 for (i
= 0; val
!= 0; val
>>= 1, i
++)
458 /* Still looking for the first bit. */
462 /* We've seen the start of a bit sequence, and now a zero. There
463 must be more one bits, otherwise we would have exited the loop.
464 Therefor, it is not a mask. */
473 /* The bit string has ones from START to END bit positions only. */
476 return ((start
< 0) ? 0 : end
- start
+ 1);
479 /* Return the machine mode to use for a comparison. */
482 select_cc_mode (op
, x
)
486 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
491 /* X and Y are two things to compare using CODE. Emit the compare insn and
492 return the rtx for register 36 in the proper mode. */
495 gen_compare_reg (code
, x
, y
)
500 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
501 enum machine_mode mode
502 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
506 if (! arith_operand (x
, mode
))
507 x
= force_reg (SImode
, x
);
508 if (! arith_operand (y
, mode
))
509 y
= force_reg (SImode
, y
);
512 cc_reg
= gen_rtx_REG (ccmode
, 36);
513 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
514 gen_rtx_COMPARE (ccmode
, x
, y
)));
519 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
520 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
521 are 4. Indexed addresses are cost 6. */
523 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
526 i960_address_cost (x
)
530 /* Handled before calling here. */
531 if (GET_CODE (x
) == REG
)
534 if (GET_CODE (x
) == PLUS
)
536 rtx base
= XEXP (x
, 0);
537 rtx offset
= XEXP (x
, 1);
539 if (GET_CODE (base
) == SUBREG
)
540 base
= SUBREG_REG (base
);
541 if (GET_CODE (offset
) == SUBREG
)
542 offset
= SUBREG_REG (offset
);
544 if (GET_CODE (base
) == REG
)
546 if (GET_CODE (offset
) == REG
)
548 if (GET_CODE (offset
) == CONST_INT
)
550 if ((unsigned)INTVAL (offset
) < 2047)
554 if (CONSTANT_P (offset
))
557 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
560 /* This is an invalid address. The return value doesn't matter, but
561 for convenience we make this more expensive than anything else. */
564 if (GET_CODE (x
) == MULT
)
567 /* Symbol_refs and other unrecognized addresses are cost 4. */
571 /* Emit insns to move operands[1] into operands[0].
573 Return 1 if we have written out everything that needs to be done to
574 do the move. Otherwise, return 0 and the caller will emit the move
578 emit_move_sequence (operands
, mode
)
580 enum machine_mode mode
;
582 /* We can only store registers to memory. */
584 if (GET_CODE (operands
[0]) == MEM
&& GET_CODE (operands
[1]) != REG
)
585 operands
[1] = force_reg (mode
, operands
[1]);
587 /* Storing multi-word values in unaligned hard registers to memory may
588 require a scratch since we have to store them a register at a time and
589 adding 4 to the memory address may not yield a valid insn. */
590 /* ??? We don't always need the scratch, but that would complicate things.
592 /* ??? We must also handle stores to pseudos here, because the pseudo may be
593 replaced with a MEM later. This would be cleaner if we didn't have
594 a separate pattern for unaligned DImode/TImode stores. */
595 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
596 && (GET_CODE (operands
[0]) == MEM
597 || (GET_CODE (operands
[0]) == REG
598 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
599 && GET_CODE (operands
[1]) == REG
600 && REGNO (operands
[1]) < FIRST_PSEUDO_REGISTER
601 && ! HARD_REGNO_MODE_OK (REGNO (operands
[1]), mode
))
603 emit_insn (gen_rtx_PARALLEL
606 gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]),
607 gen_rtx_CLOBBER (VOIDmode
,
608 gen_rtx_SCRATCH (Pmode
)))));
615 /* Output assembler to move a double word value. */
618 i960_output_move_double (dst
, src
)
623 if (GET_CODE (dst
) == REG
624 && GET_CODE (src
) == REG
)
626 if ((REGNO (src
) & 1)
627 || (REGNO (dst
) & 1))
629 /* We normally copy the low-numbered register first. However, if
630 the second source register is the same as the first destination
631 register, we must copy in the opposite order. */
632 if (REGNO (src
) + 1 == REGNO (dst
))
633 return "mov %D1,%D0\n\tmov %1,%0";
635 return "mov %1,%0\n\tmov %D1,%D0";
640 else if (GET_CODE (dst
) == REG
641 && GET_CODE (src
) == CONST_INT
642 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
645 return "mov %1,%0\n\tmov 0,%D0";
649 else if (GET_CODE (dst
) == REG
650 && GET_CODE (src
) == MEM
)
654 /* One can optimize a few cases here, but you have to be
655 careful of clobbering registers used in the address and
659 operands
[2] = gen_rtx_REG (Pmode
, REGNO (dst
) + 1);
660 operands
[3] = gen_rtx_MEM (word_mode
, operands
[2]);
661 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
662 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands
);
668 else if (GET_CODE (dst
) == MEM
669 && GET_CODE (src
) == REG
)
673 /* This is handled by emit_move_sequence so we shouldn't get here. */
682 /* Output assembler to move a quad word value. */
685 i960_output_move_quad (dst
, src
)
690 if (GET_CODE (dst
) == REG
691 && GET_CODE (src
) == REG
)
693 if ((REGNO (src
) & 3)
694 || (REGNO (dst
) & 3))
696 /* We normally copy starting with the low numbered register.
697 However, if there is an overlap such that the first dest reg
698 is <= the last source reg but not < the first source reg, we
699 must copy in the opposite order. */
700 if (REGNO (dst
) <= REGNO (src
) + 3
701 && REGNO (dst
) >= REGNO (src
))
702 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
704 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
709 else if (GET_CODE (dst
) == REG
710 && GET_CODE (src
) == CONST_INT
711 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
714 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
718 else if (GET_CODE (dst
) == REG
719 && GET_CODE (src
) == MEM
)
723 /* One can optimize a few cases here, but you have to be
724 careful of clobbering registers used in the address and
728 operands
[2] = gen_rtx_REG (Pmode
, REGNO (dst
) + 3);
729 operands
[3] = gen_rtx_MEM (word_mode
, operands
[2]);
730 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
731 operands
[5] = adj_offsettable_operand (operands
[4], UNITS_PER_WORD
);
732 operands
[6] = adj_offsettable_operand (operands
[5], UNITS_PER_WORD
);
733 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands
);
739 else if (GET_CODE (dst
) == MEM
740 && GET_CODE (src
) == REG
)
744 /* This is handled by emit_move_sequence so we shouldn't get here. */
753 /* Emit insns to load a constant to non-floating point registers.
754 Uses several strategies to try to use as few insns as possible. */
757 i960_output_ldconst (dst
, src
)
758 register rtx dst
, src
;
761 register unsigned rsrc2
;
762 enum machine_mode mode
= GET_MODE (dst
);
765 operands
[0] = operands
[2] = dst
;
766 operands
[1] = operands
[3] = src
;
768 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
769 must be a ldconst insn. */
771 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
773 output_asm_insn ("ldconst %1,%0", operands
);
776 else if (mode
== XFmode
)
782 if (fp_literal_zero (src
, XFmode
))
785 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
786 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
788 output_asm_insn ("# ldconst %1,%0",operands
);
790 for (i
= 0; i
< 3; i
++)
792 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + i
);
793 operands
[1] = GEN_INT (value_long
[i
]);
794 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
800 else if (mode
== DFmode
)
804 if (fp_literal_zero (src
, DFmode
))
807 split_double (src
, &first
, &second
);
809 output_asm_insn ("# ldconst %1,%0",operands
);
811 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
));
813 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
815 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + 1);
816 operands
[1] = second
;
817 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
821 else if (mode
== SFmode
)
826 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
827 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
829 output_asm_insn ("# ldconst %1,%0",operands
);
830 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
));
831 operands
[1] = GEN_INT (value
);
832 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
836 else if (mode
== TImode
)
838 /* ??? This is currently not handled at all. */
841 /* Note: lowest order word goes in lowest numbered reg. */
842 rsrc1
= INTVAL (src
);
843 if (rsrc1
>= 0 && rsrc1
< 32)
846 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
847 /* Go pick up the low-order word. */
849 else if (mode
== DImode
)
851 rtx upperhalf
, lowerhalf
, xoperands
[2];
853 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
854 split_double (src
, &lowerhalf
, &upperhalf
);
859 /* Note: lowest order word goes in lowest numbered reg. */
860 /* Numbers from 0 to 31 can be handled with a single insn. */
861 rsrc1
= INTVAL (lowerhalf
);
862 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
865 /* Output the upper half with a recursive call. */
866 xoperands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + 1);
867 xoperands
[1] = upperhalf
;
868 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
870 /* The lower word is emitted as normally. */
874 rsrc1
= INTVAL (src
);
880 else if (mode
== HImode
)
889 /* ldconst 0..31,X -> mov 0..31,X */
892 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
897 /* ldconst 32..63,X -> add 31,nn,X */
900 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
902 operands
[1] = GEN_INT (rsrc1
- 31);
903 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
909 /* ldconst -1..-31 -> sub 0,0..31,X */
912 /* return 'sub -(%1),0,%0' */
913 operands
[1] = GEN_INT (- rsrc1
);
914 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
918 /* ldconst -32 -> not 31,X */
921 operands
[1] = GEN_INT (~rsrc1
);
922 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
927 /* If const is a single bit. */
928 if (bitpos (rsrc1
) >= 0)
930 operands
[1] = GEN_INT (bitpos (rsrc1
));
931 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
935 /* If const is a bit string of less than 6 bits (1..31 shifted). */
940 if (bitstr (rsrc1
, &s
, &e
) < 6)
942 rsrc2
= ((unsigned int) rsrc1
) >> s
;
943 operands
[1] = GEN_INT (rsrc2
);
944 operands
[2] = GEN_INT (s
);
945 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
950 /* Unimplemented cases:
951 const is in range 0..31 but rotated around end of word:
952 ror 31,3,g0 -> ldconst 0xe0000003,g0
954 and any 2 instruction cases that might be worthwhile */
956 output_asm_insn ("ldconst %1,%0", operands
);
960 /* Determine if there is an opportunity for a bypass optimization.
961 Bypass succeeds on the 960K* if the destination of the previous
962 instruction is the second operand of the current instruction.
963 Bypass always succeeds on the C*.
965 Return 1 if the pattern should interchange the operands.
967 CMPBR_FLAG is true if this is for a compare-and-branch insn.
968 OP1 and OP2 are the two source operands of a 3 operand insn. */
971 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
972 register rtx insn
, op1
, op2
;
975 register rtx prev_insn
, prev_dest
;
980 /* Can't do this if op1 isn't a register. */
984 /* Can't do this for a compare-and-branch if both ops aren't regs. */
985 if (cmpbr_flag
&& ! REG_P (op2
))
988 prev_insn
= prev_real_insn (insn
);
990 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
991 && GET_CODE (PATTERN (prev_insn
)) == SET
)
993 prev_dest
= SET_DEST (PATTERN (prev_insn
));
994 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
995 || (GET_CODE (prev_dest
) == SUBREG
996 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
997 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
1003 /* Output the code which declares the function name. This also handles
1004 leaf routines, which have special requirements, and initializes some
1005 global variables. */
1008 i960_function_name_declare (file
, name
, fndecl
)
1017 /* Increment global return label. */
1021 /* Compute whether tail calls and leaf routine optimizations can be performed
1022 for this function. */
1024 if (TARGET_TAILCALL
)
1029 if (TARGET_LEAFPROC
)
1034 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1035 argblock, because argblock uses g14 implicitly. */
1037 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
1043 /* See if caller passes in an address to return value. */
1045 if (aggregate_value_p (DECL_RESULT (fndecl
)))
1051 /* Can not use tail calls or make this a leaf routine if there is a non
1054 if (get_frame_size () != 0)
1057 /* I don't understand this condition, and do not think that it is correct.
1058 Apparently this is just checking whether the frame pointer is used, and
1059 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1062 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1063 if (GET_CODE (insn
) == INSN
1064 && reg_mentioned_p (frame_pointer_rtx
, insn
))
1070 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1073 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1074 if (GET_CODE (insn
) == CALL_INSN
)
1080 /* Can not be a leaf routine if any non-call clobbered registers are
1081 used in this function. */
1084 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1085 if (regs_ever_live
[i
]
1086 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1088 /* Global registers. */
1089 if (i
< 16 && i
> 7 && i
!= 13)
1091 /* Local registers. */
1096 /* Now choose a leaf return register, if we can find one, and if it is
1097 OK for this to be a leaf routine. */
1099 i960_leaf_ret_reg
= -1;
1101 if (optimize
&& leaf_proc_ok
)
1103 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
1104 if (regs_ever_live
[i
] == 0)
1106 i960_leaf_ret_reg
= i
;
1107 regs_ever_live
[i
] = 1;
1112 /* Do this after choosing the leaf return register, so it will be listed
1113 if one was chosen. */
1115 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
1116 fprintf (file
, "\t# Registers used: ");
1118 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1120 if (regs_ever_live
[i
])
1122 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
1124 if (i
> 15 && j
== 0)
1126 fprintf (file
,"\n\t#\t\t ");
1132 fprintf (file
, "\n");
1134 if (i960_leaf_ret_reg
>= 0)
1136 /* Make it a leaf procedure. */
1138 if (TREE_PUBLIC (fndecl
))
1139 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1141 fprintf (file
, "\t.leafproc\t");
1142 assemble_name (file
, name
);
1143 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1144 ASM_OUTPUT_LABEL (file
, name
);
1145 fprintf (file
, "\tlda LR%d,g14\n", ret_label
);
1146 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
1147 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
1149 if (TARGET_C_SERIES
)
1151 fprintf (file
, "\tlda 0,g14\n");
1152 i960_last_insn_type
= I_TYPE_MEM
;
1156 fprintf (file
, "\tmov 0,g14\n");
1157 i960_last_insn_type
= I_TYPE_REG
;
1162 ASM_OUTPUT_LABEL (file
, name
);
1163 i960_last_insn_type
= I_TYPE_CTRL
;
1167 /* Compute and return the frame size. */
1170 compute_frame_size (size
)
1174 int outgoing_args_size
= current_function_outgoing_args_size
;
1176 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1177 as size is concerned. */
1178 actual_fsize
= (size
+ 15) & -16;
1179 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1181 return actual_fsize
;
1184 /* Output code for the function prologue. */
1187 i960_function_prologue (file
, size
)
1191 register int i
, j
, nr
;
1194 int actual_fsize
, offset
;
1196 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1198 int regs
[FIRST_PSEUDO_REGISTER
];
1200 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1201 if (regs_ever_live
[i
]
1202 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1205 /* Count global registers that need saving. */
1212 epilogue_string
[0] = '\0';
1214 if (profile_flag
|| profile_block_flag
)
1216 /* When profiling, we may use registers 20 to 27 to save arguments, so
1217 they can't be used here for saving globals. J is the number of
1218 argument registers the mcount call will save. */
1219 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1222 for (i
= 20; i
<= j
+ 20; i
++)
1226 /* First look for local registers to save globals in. */
1227 for (i
= 0; i
< 16; i
++)
1232 /* Start at r4, not r3. */
1233 for (j
= 20; j
< 32; j
++)
1240 regs_ever_live
[j
] = 1;
1242 if (i
<= 14 && i
% 2 == 0 && j
<= 30 && j
% 2 == 0
1243 && regs
[i
+1] != 0 && regs
[j
+1] == 0)
1248 regs_ever_live
[j
+1] = 1;
1250 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && j
<= 28 && j
% 4 == 0
1251 && regs
[i
+2] != 0 && regs
[j
+2] == 0)
1256 regs_ever_live
[j
+2] = 1;
1258 if (nr
== 3 && regs
[i
+3] != 0 && regs
[j
+3] == 0)
1263 regs_ever_live
[j
+3] = 1;
1266 fprintf (file
, "\tmov%s %s,%s\n",
1269 (nr
== 2) ? "l" : ""),
1270 reg_names
[i
], reg_names
[j
]);
1271 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1274 (nr
== 2) ? "l" : ""),
1275 reg_names
[j
], reg_names
[i
]);
1276 strcat (epilogue_string
, tmpstr
);
1284 /* N_iregs is now the number of global registers that haven't been saved
1287 rsize
= (n_iregs
* 4);
1288 actual_fsize
= compute_frame_size (size
) + rsize
;
1290 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1291 size up to the nearest multiple of 16. I don't know whether this is
1292 necessary, or even desirable.
1294 The frame pointer must be aligned, but the call instruction takes care of
1295 that. If we leave the stack pointer unaligned, we may save a little on
1296 dynamic stack allocation. And we don't lose, at least according to the
1298 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1301 /* Allocate space for register save and locals. */
1302 if (actual_fsize
> 0)
1304 if (actual_fsize
< 32)
1305 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1307 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1310 /* Take hardware register save area created by the call instruction
1311 into account, but store them before the argument block area. */
1312 offset
= 64 + actual_fsize
- compute_frame_size (0) - rsize
;
1313 /* Save registers on stack if needed. */
1314 for (i
= 0, j
= n_iregs
; j
> 0 && i
< 16; i
++)
1321 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1324 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1328 if (nr
== 3 && regs
[i
+3] == -1)
1331 fprintf (file
,"\tst%s %s,%d(fp)\n",
1334 (nr
== 2) ? "l" : ""),
1335 reg_names
[i
], offset
);
1336 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1339 (nr
== 2) ? "l" : ""),
1340 offset
, reg_names
[i
]);
1341 strcat (epilogue_string
, tmpstr
);
1347 if (actual_fsize
== 0 && size
== 0 && rsize
== 0)
1350 fprintf (file
, "\t#Prologue stats:\n");
1351 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1354 fprintf (file
, "\t# Local Variable Size: %d bytes\n", size
);
1356 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1358 fprintf (file
, "\t#End Prologue#\n");
1361 /* Output code for the function profiler. */
1364 output_function_profiler (file
, labelno
)
1368 /* The last used parameter register. */
1370 int i
, j
, increment
;
1371 int varargs_stdarg_function
1372 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1374 /* Figure out the last used parameter register. The proper thing to do
1375 is to walk incoming args of the function. A function might have live
1376 parameter registers even if it has no incoming args. Note that we
1377 don't have to save parameter registers g8 to g11 because they are
1380 /* See also output_function_prologue, which tries to use local registers
1381 for preserved call-saved global registers. */
1383 for (last_parm_reg
= 7;
1384 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1388 /* Save parameter registers in regs r4 (20) to r11 (27). */
1390 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1392 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1394 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1396 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1401 fprintf (file
, "\tmov%s g%d,r%d\n",
1402 (increment
== 4 ? "q" : increment
== 3 ? "t"
1403 : increment
== 2 ? "l": ""), i
, j
);
1406 /* If this function uses the arg pointer, then save it in r3 and then
1409 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1410 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1412 /* Load location address into g0 and call mcount. */
1414 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1416 /* If this function uses the arg pointer, restore it. */
1418 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1419 fprintf (file
, "\tmov r3,g14\n");
1421 /* Restore parameter registers. */
1423 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1425 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1427 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1429 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1434 fprintf (file
, "\tmov%s r%d,g%d\n",
1435 (increment
== 4 ? "q" : increment
== 3 ? "t"
1436 : increment
== 2 ? "l": ""), j
, i
);
1440 /* Output code for the function epilogue. */
1443 i960_function_epilogue (file
, size
)
1447 if (i960_leaf_ret_reg
>= 0)
1449 fprintf (file
, "LR%d: ret\n", ret_label
);
1453 if (*epilogue_string
== 0)
1457 /* Emit a return insn, but only if control can fall through to here. */
1459 tmp
= get_last_insn ();
1462 if (GET_CODE (tmp
) == BARRIER
)
1464 if (GET_CODE (tmp
) == CODE_LABEL
)
1466 if (GET_CODE (tmp
) == JUMP_INSN
)
1468 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1472 if (GET_CODE (tmp
) == NOTE
)
1474 tmp
= PREV_INSN (tmp
);
1479 fprintf (file
, "LR%d: ret\n", ret_label
);
1483 fprintf (file
, "LR%d:\n", ret_label
);
1485 fprintf (file
, "\t#EPILOGUE#\n");
1487 /* Output the string created by the prologue which will restore all
1488 registers saved by the prologue. */
1490 if (epilogue_string
[0] != '\0')
1491 fprintf (file
, "%s", epilogue_string
);
1493 /* Must clear g14 on return if this function set it.
1494 Only varargs/stdarg functions modify g14. */
1496 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1497 fprintf (file
, "\tmov 0,g14\n");
1499 fprintf (file
, "\tret\n");
1500 fprintf (file
, "\t#End Epilogue#\n");
1503 /* Output code for a call insn. */
1506 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1507 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1509 int argsize
= INTVAL (argsize_rtx
);
1510 rtx nexti
= next_real_insn (insn
);
1512 int varargs_stdarg_function
1513 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1515 operands
[0] = target
;
1516 operands
[1] = arg_pointer
;
1518 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1519 output_asm_insn ("mov g14,r3", operands
);
1522 output_asm_insn ("lda %a1,g14", operands
);
1523 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1524 output_asm_insn ("mov 0,g14", operands
);
1526 /* The code used to assume that calls to SYMBOL_REFs could not be more
1527 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1528 feature is now implemented by relaxing in the GNU linker. It can convert
1529 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1531 /* Nexti could be zero if the called routine is volatile. */
1532 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1533 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1535 /* Delete following return insn. */
1536 if (nexti
&& no_labels_between_p (insn
, nexti
))
1537 delete_insn (nexti
);
1538 output_asm_insn ("bx %0", operands
);
1539 return "# notreached";
1542 output_asm_insn ("callx %0", operands
);
1544 /* If the caller sets g14 to the address of the argblock, then the caller
1545 must clear it after the return. */
1547 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1548 output_asm_insn ("mov r3,g14", operands
);
1549 else if (argsize
> 48)
1550 output_asm_insn ("mov 0,g14", operands
);
1555 /* Output code for a return insn. */
1558 i960_output_ret_insn (insn
)
1561 static char lbuf
[20];
1563 if (*epilogue_string
!= 0)
1565 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1568 sprintf (lbuf
, "b LR%d", ret_label
);
1572 /* Must clear g14 on return if this function set it.
1573 Only varargs/stdarg functions modify g14. */
1575 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1576 output_asm_insn ("mov 0,g14", 0);
1578 if (i960_leaf_ret_reg
>= 0)
1580 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1587 /* Return a character string representing the branch prediction
1588 opcode to be tacked on an instruction. This must at least
1589 return a null string. */
1592 i960_br_predict_opcode (lab_ref
, insn
)
1595 if (TARGET_BRANCH_PREDICT
)
1597 unsigned long label_uid
;
1599 if (GET_CODE (lab_ref
) == CODE_LABEL
)
1600 label_uid
= INSN_UID (lab_ref
);
1601 else if (GET_CODE (lab_ref
) == LABEL_REF
)
1602 label_uid
= INSN_UID (XEXP (lab_ref
, 0));
1606 /* If not optimizing, then the insn_addresses array will not be
1607 valid. In this case, always return ".t" since most branches
1608 are taken. If optimizing, return .t for backward branches
1609 and .f for forward branches. */
1611 || insn_addresses
[label_uid
] < insn_addresses
[INSN_UID (insn
)])
1620 /* Print the operand represented by rtx X formatted by code CODE. */
1623 i960_print_operand (file
, x
, code
)
1628 enum rtx_code rtxcode
= GET_CODE (x
);
1635 /* Second reg of a double or quad. */
1636 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1640 /* Third reg of a quad. */
1641 fprintf (file
, "%s", reg_names
[REGNO (x
)+2]);
1645 /* Fourth reg of a quad. */
1646 fprintf (file
, "%s", reg_names
[REGNO (x
)+3]);
1650 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1658 else if (rtxcode
== MEM
)
1660 output_address (XEXP (x
, 0));
1663 else if (rtxcode
== CONST_INT
)
1665 HOST_WIDE_INT val
= INTVAL (x
);
1668 if (val
> 9999 || val
< -999)
1669 fprintf (file
, "0x%x", val
);
1671 fprintf (file
, "%d", val
);
1674 else if (rtxcode
== CONST_DOUBLE
)
1679 if (x
== CONST0_RTX (GET_MODE (x
)))
1681 fprintf (file
, "0f0.0");
1684 else if (x
== CONST1_RTX (GET_MODE (x
)))
1686 fprintf (file
, "0f1.0");
1690 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1691 REAL_VALUE_TO_DECIMAL (d
, "%#g", dstr
);
1692 fprintf (file
, "0f%s", dstr
);
1699 /* Branch or jump, depending on assembler. */
1700 if (TARGET_ASM_COMPAT
)
1707 /* Sign of condition. */
1708 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1709 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1711 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1712 || (rtxcode
== GE
) || (rtxcode
== LE
))
1719 /* Inverted condition. */
1720 rtxcode
= reverse_condition (rtxcode
);
1724 /* Inverted condition w/ reversed operands. */
1725 rtxcode
= reverse_condition (rtxcode
);
1729 /* Reversed operand condition. */
1730 rtxcode
= swap_condition (rtxcode
);
1734 /* Normal condition. */
1736 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1737 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1738 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1739 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1740 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1741 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1742 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1743 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1744 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1745 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1750 output_addr_const (file
, x
);
1760 /* Print a memory address as an operand to reference that memory location.
1762 This is exactly the same as legitimate_address_p, except that it the prints
1763 addresses instead of recognizing them. */
1766 i960_print_operand_addr (file
, addr
)
1778 if (GET_CODE (addr
) == REG
)
1780 else if (CONSTANT_P (addr
))
1782 else if (GET_CODE (addr
) == PLUS
)
1786 op0
= XEXP (addr
, 0);
1787 op1
= XEXP (addr
, 1);
1789 if (GET_CODE (op0
) == REG
)
1792 if (GET_CODE (op1
) == REG
)
1794 else if (CONSTANT_P (op1
))
1799 else if (GET_CODE (op0
) == PLUS
)
1801 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1803 ireg
= XEXP (XEXP (op0
, 0), 0);
1804 scale
= XEXP (XEXP (op0
, 0), 1);
1805 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1807 breg
= XEXP (op0
, 1);
1813 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1815 breg
= XEXP (op0
, 0);
1816 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1818 ireg
= XEXP (op0
, 1);
1827 else if (GET_CODE (op0
) == MULT
)
1829 ireg
= XEXP (op0
, 0);
1830 scale
= XEXP (op0
, 1);
1831 if (GET_CODE (op1
) == REG
)
1833 else if (CONSTANT_P (op1
))
1841 else if (GET_CODE (addr
) == MULT
)
1843 ireg
= XEXP (addr
, 0);
1844 scale
= XEXP (addr
, 1);
1850 output_addr_const (file
, offset
);
1852 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1854 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1857 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1858 that is a valid memory address for an instruction.
1859 The MODE argument is the machine mode for the MEM expression
1860 that wants to use this address.
1862 On 80960, legitimate addresses are:
1864 disp (12 or 32 bit) ld foo,r0
1865 base + index ld (g0)[g1*1],r0
1866 base + displ ld 0xf00(g0),r0
1867 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1868 index*scale + base ld (g0)[g1*4],r0
1869 index*scale + displ ld 0xf00[g1*4],r0
1870 index*scale ld [g1*4],r0
1871 index + base + displ ld 0xf00(g0)[g1*1],r0
1873 In each case, scale can be 1, 2, 4, 8, or 16. */
1875 /* This is exactly the same as i960_print_operand_addr, except that
1876 it recognizes addresses instead of printing them.
1878 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1879 convert common non-canonical forms to canonical form so that they will
1882 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1883 where a register is valid. */
1885 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1886 ((GET_CODE (X) == REG \
1887 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1888 || (GET_CODE (X) == SUBREG \
1889 && GET_CODE (SUBREG_REG (X)) == REG \
1890 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1891 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1893 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1894 ((GET_CODE (X) == REG \
1895 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1896 || (GET_CODE (X) == SUBREG \
1897 && GET_CODE (SUBREG_REG (X)) == REG \
1898 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1899 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1902 legitimate_address_p (mode
, addr
, strict
)
1903 enum machine_mode mode
;
1907 if (RTX_OK_FOR_BASE_P (addr
, strict
))
1909 else if (CONSTANT_P (addr
))
1911 else if (GET_CODE (addr
) == PLUS
)
1915 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1918 op0
= XEXP (addr
, 0);
1919 op1
= XEXP (addr
, 1);
1921 if (RTX_OK_FOR_BASE_P (op0
, strict
))
1923 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
1925 else if (CONSTANT_P (op1
))
1930 else if (GET_CODE (op0
) == PLUS
)
1932 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1934 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
1935 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
1938 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
1939 && CONSTANT_P (op1
))
1944 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
1946 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
1947 && CONSTANT_P (op1
))
1955 else if (GET_CODE (op0
) == MULT
)
1957 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
1958 && SCALE_TERM_P (XEXP (op0
, 1))))
1961 if (RTX_OK_FOR_BASE_P (op1
, strict
))
1963 else if (CONSTANT_P (op1
))
1971 else if (GET_CODE (addr
) == MULT
)
1973 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
1976 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
1977 && SCALE_TERM_P (XEXP (addr
, 1)));
1983 /* Try machine-dependent ways of modifying an illegitimate address
1984 to be legitimate. If we find one, return the new, valid address.
1985 This macro is used in only one place: `memory_address' in explow.c.
1987 This converts some non-canonical addresses to canonical form so they
1988 can be recognized. */
1991 legitimize_address (x
, oldx
, mode
)
1994 enum machine_mode mode
;
1996 if (GET_CODE (x
) == SYMBOL_REF
)
1999 x
= copy_to_reg (x
);
2002 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2005 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2006 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2007 created by virtual register instantiation, register elimination, and
2008 similar optimizations. */
2009 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
2010 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2011 x
= gen_rtx_PLUS (Pmode
,
2012 gen_rtx_PLUS (Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
2013 XEXP (XEXP (x
, 1), 1));
2015 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2016 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2017 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2018 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2019 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2020 && CONSTANT_P (XEXP (x
, 1)))
2022 rtx constant
, other
;
2024 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2026 constant
= XEXP (x
, 1);
2027 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2029 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2031 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2032 other
= XEXP (x
, 1);
2038 x
= gen_rtx_PLUS (Pmode
,
2039 gen_rtx_PLUS (Pmode
, XEXP (XEXP (x
, 0), 0),
2040 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
2041 plus_constant (other
, INTVAL (constant
)));
2048 /* Return the most stringent alignment that we are willing to consider
2049 objects of size SIZE and known alignment ALIGN as having. */
2052 i960_alignment (size
, align
)
2058 if (! TARGET_STRICT_ALIGN
)
2059 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
2061 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2070 /* Modes for condition codes. */
2072 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
2074 /* Modes for single-word (and smaller) quantities. */
2077 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
2078 | (1 << (int) DFmode) | (1 << (int) XFmode)))
2080 /* Modes for double-word (and smaller) quantities. */
2083 & ~ ((1 << (int) TImode) | (1 << (int) XFmode)))
2085 /* Modes for quad-word quantities. */
2086 #define T_MODES (~C_MODES)
2088 /* Modes for single-float quantities. */
2089 #define SF_MODES ((1 << (int) SFmode))
2091 /* Modes for double-float quantities. */
2092 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
2094 /* Modes for quad-float quantities. */
2095 #define XF_MODES (DF_MODES | (1 << (int) XFmode) | (1 << (int) DCmode))
2097 unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] = {
2098 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2099 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2100 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2101 T_MODES
, S_MODES
, D_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2103 XF_MODES
, XF_MODES
, XF_MODES
, XF_MODES
, C_MODES
};
2106 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2107 advantage of machine specific facts, such as knowing that the frame pointer
2108 is always 16 byte aligned. */
2111 i960_expr_alignment (x
, size
)
2120 switch (GET_CODE(x
))
2125 if ((align
& 0xf) == 0)
2127 else if ((align
& 0x7) == 0)
2129 else if ((align
& 0x3) == 0)
2131 else if ((align
& 0x1) == 0)
2138 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
2139 i960_expr_alignment (XEXP (x
, 1), size
));
2143 /* If this is a valid program, objects are guaranteed to be
2144 correctly aligned for whatever size the reference actually is. */
2145 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2149 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
2154 align
= i960_expr_alignment (XEXP (x
, 0));
2156 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2158 align
= align
<< INTVAL (XEXP (x
, 1));
2159 align
= MIN (align
, 16);
2164 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
2165 i960_expr_alignment (XEXP (x
, 1), size
));
2167 align
= MIN (align
, 16);
2174 /* Return true if it is possible to reference both BASE and OFFSET, which
2175 have alignment at least as great as 4 byte, as if they had alignment valid
2176 for an object of size SIZE. */
2179 i960_improve_align (base
, offset
, size
)
2186 /* We have at least a word reference to the object, so we know it has to
2187 be aligned at least to 4 bytes. */
2189 i
= MIN (i960_expr_alignment (base
, 4),
2190 i960_expr_alignment (offset
, 4));
2194 /* We know the size of the request. If strict align is not enabled, we
2195 can guess that the alignment is OK for the requested size. */
2197 if (! TARGET_STRICT_ALIGN
)
2198 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2204 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2205 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2208 i960_si_ti (base
, offset
)
2212 return i960_improve_align (base
, offset
, 16);
2215 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2216 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2219 i960_si_di (base
, offset
)
2223 return i960_improve_align (base
, offset
, 8);
2226 /* Return raw values of size and alignment (in words) for the data
2227 type being accessed. These values will be rounded by the caller. */
2230 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2231 enum machine_mode mode
;
2238 /* Use formal alignment requirements of type being passed, except make
2239 it at least a word. If we don't have a type, this is a library call,
2240 and the parm has to be of scalar type. In this case, consider its
2241 formal alignment requirement to be its size in words. */
2243 if (mode
== BLKmode
)
2244 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2245 else if (mode
== VOIDmode
)
2247 /* End of parm list. */
2248 if (type
== 0 || TYPE_MODE (type
) != VOIDmode
)
2253 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2257 /* ??? This is a hack to properly correct the alignment of XFmode
2258 values without affecting anything else. */
2264 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2265 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2273 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2274 Any arg that is bigger than 4 words is placed on the stack and all
2275 subsequent arguments are placed on the stack.
2277 Additionally, parameters with an alignment requirement stronger than
2278 a word must be aligned appropriately. Note that this means that a
2279 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2280 passed in an odd/even register pair. */
2282 /* Update CUM to advance past an argument described by MODE and TYPE. */
2285 i960_function_arg_advance (cum
, mode
, type
, named
)
2286 CUMULATIVE_ARGS
*cum
;
2287 enum machine_mode mode
;
2293 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2295 if (size
> 4 || cum
->ca_nstackparms
!= 0
2296 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2297 || MUST_PASS_IN_STACK (mode
, type
))
2299 /* Indicate that all the registers are in use, even if all are not,
2300 so va_start will compute the right value. */
2301 cum
->ca_nregparms
= NPARM_REGS
;
2302 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2305 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2308 /* Return the register that the argument described by MODE and TYPE is
2309 passed in, or else return 0 if it is passed on the stack. */
2312 i960_function_arg (cum
, mode
, type
, named
)
2313 CUMULATIVE_ARGS
*cum
;
2314 enum machine_mode mode
;
2321 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2323 if (size
> 4 || cum
->ca_nstackparms
!= 0
2324 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2325 || MUST_PASS_IN_STACK (mode
, type
))
2327 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2332 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2333 ret
= gen_rtx_REG (mode
, cum
->ca_nregparms
);
2339 /* Floating-point support. */
2342 i960_output_long_double (file
, value
)
2344 REAL_VALUE_TYPE value
;
2349 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value
, value_long
);
2350 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2353 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2354 value_long
[0], dstr
, value_long
[1], value_long
[2]);
2355 fprintf (file
, "\t.word\t0x0\n");
2359 i960_output_double (file
, value
)
2361 REAL_VALUE_TYPE value
;
2366 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2367 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2369 fprintf (file
, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2370 value_long
[0], dstr
, value_long
[1]);
2374 i960_output_float (file
, value
)
2376 REAL_VALUE_TYPE value
;
2381 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2382 REAL_VALUE_TO_DECIMAL (value
, "%.12g", dstr
);
2384 fprintf (file
, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long
, dstr
);
2387 /* Return the number of bits that an object of size N bytes is aligned to. */
2390 i960_object_bytes_bitalign (n
)
2394 else if (n
> 4) n
= 64;
2395 else if (n
> 2) n
= 32;
2396 else if (n
> 1) n
= 16;
2402 /* Compute the alignment for an aggregate type TSIZE.
2403 Alignment is MAX (greatest member alignment,
2404 MIN (pragma align, structure size alignment)). */
2407 i960_round_align (align
, tsize
)
2413 if (TREE_CODE (tsize
) != INTEGER_CST
)
2416 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2418 /* Handle #pragma align. */
2419 if (new_align
> i960_maxbitalignment
)
2420 new_align
= i960_maxbitalignment
;
2422 if (align
< new_align
)
2428 /* Do any needed setup for a varargs function. For the i960, we must
2429 create a register parameter block if one doesn't exist, and then copy
2430 all register parameters to memory. */
2433 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2434 CUMULATIVE_ARGS
*cum
;
2435 enum machine_mode mode
;
2440 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2441 int first_reg
= cum
->ca_nregparms
;
2443 /* Copy only unnamed register arguments to memory. If there are
2444 any stack parms, there are no unnamed arguments in registers, and
2445 an argument block was already allocated by the caller.
2446 Remember that any arg bigger than 4 words is passed on the stack as
2447 are all subsequent args.
2449 If there are no stack arguments but there are exactly NPARM_REGS
2450 registers, either there were no extra arguments or the caller
2451 allocated an argument block. */
2453 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2455 rtx label
= gen_label_rtx ();
2458 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2459 and we need to allocate a chunk to save the registers (if any
2460 arguments were passed on the stack the caller would allocate the
2461 48 bytes as well). We must allocate all 48 bytes (12*4) because
2462 va_start assumes it. */
2463 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2464 emit_jump_insn (gen_bne (label
));
2465 emit_insn (gen_rtx_SET (VOIDmode
, arg_pointer_rtx
,
2466 stack_pointer_rtx
));
2467 emit_insn (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
2468 memory_address (SImode
,
2469 plus_constant (stack_pointer_rtx
,
2473 /* ??? Note that we unnecessarily store one extra register for stdarg
2474 fns. We could optimize this, but it's kept as for now. */
2475 regblock
= gen_rtx_MEM (BLKmode
,
2476 plus_constant (arg_pointer_rtx
,
2478 move_block_from_reg (first_reg
, regblock
,
2479 NPARM_REGS
- first_reg
,
2480 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2484 /* Calculate the final size of the reg parm stack space for the current
2485 function, based on how many bytes would be allocated on the stack. */
2488 i960_final_reg_parm_stack_space (const_size
, var_size
)
2492 if (var_size
|| const_size
> 48)
2498 /* Calculate the size of the reg parm stack space. This is a bit complicated
2502 i960_reg_parm_stack_space (fndecl
)
2505 /* In this case, we are called from emit_library_call, and we don't need
2506 to pretend we have more space for parameters than what's apparent. */
2510 /* In this case, we are called from locate_and_pad_parms when we're
2511 not IN_REGS, so we have an arg block. */
2512 if (fndecl
!= current_function_decl
)
2515 /* Otherwise, we have an arg block if the current function has more than
2516 48 bytes of parameters. */
2517 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2523 /* Return the register class of a scratch register needed to copy IN into
2524 or out of a register in CLASS in MODE. If it can be done directly,
2525 NO_REGS is returned. */
2528 secondary_reload_class (class, mode
, in
)
2529 enum reg_class
class;
2530 enum machine_mode mode
;
2535 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2536 regno
= true_regnum (in
);
2538 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2539 LOCAL_OR_GLOBAL_REGS into anything. */
2540 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2541 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2544 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2545 if (class == FP_REGS
2546 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2547 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2550 return LOCAL_OR_GLOBAL_REGS
;
2553 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2554 function unit it executed on. */
2556 /* ??? This would make more sense as an attribute. */
2559 i960_scan_opcode (p
)
2571 /* Ret is not actually of type REG, but it won't matter, because no
2572 insn will ever follow it. */
2575 i960_last_insn_type
= I_TYPE_REG
;
2579 if (p
[1] == 'x' || p
[3] == 'x')
2580 i960_last_insn_type
= I_TYPE_MEM
;
2581 i960_last_insn_type
= I_TYPE_CTRL
;
2586 i960_last_insn_type
= I_TYPE_CTRL
;
2593 i960_last_insn_type
= I_TYPE_MEM
;
2595 i960_last_insn_type
= I_TYPE_CTRL
;
2597 else if (p
[1] == 'm')
2600 i960_last_insn_type
= I_TYPE_REG
;
2601 else if (p
[4] == 'b' || p
[4] == 'j')
2602 i960_last_insn_type
= I_TYPE_CTRL
;
2604 i960_last_insn_type
= I_TYPE_REG
;
2607 i960_last_insn_type
= I_TYPE_REG
;
2611 i960_last_insn_type
= I_TYPE_MEM
;
2616 i960_last_insn_type
= I_TYPE_MEM
;
2618 i960_last_insn_type
= I_TYPE_REG
;