1 /* Perform branch target register load optimizations.
2 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
26 #include "hard-reg-set.h"
33 #include "insn-attr.h"
38 #include "tree-pass.h"
40 /* Target register optimizations - these are performed after reload. */
42 typedef struct btr_def_group_s
44 struct btr_def_group_s
*next
;
46 struct btr_def_s
*members
;
49 typedef struct btr_user_s
51 struct btr_user_s
*next
;
55 /* If INSN has a single use of a single branch register, then
56 USE points to it within INSN. If there is more than
57 one branch register use, or the use is in some way ambiguous,
61 int first_reaching_def
;
62 char other_use_this_block
;
65 /* btr_def structs appear on three lists:
66 1. A list of all btr_def structures (head is
67 ALL_BTR_DEFS, linked by the NEXT field).
68 2. A list of branch reg definitions per basic block (head is
69 BB_BTR_DEFS[i], linked by the NEXT_THIS_BB field).
70 3. A list of all branch reg definitions belonging to the same
71 group (head is in a BTR_DEF_GROUP struct, linked by
72 NEXT_THIS_GROUP field). */
74 typedef struct btr_def_s
76 struct btr_def_s
*next_this_bb
;
77 struct btr_def_s
*next_this_group
;
83 /* For a branch register setting insn that has a constant
84 source (i.e. a label), group links together all the
85 insns with the same source. For other branch register
86 setting insns, group is NULL. */
89 /* If this def has a reaching use which is not a simple use
90 in a branch instruction, then has_ambiguous_use will be true,
91 and we will not attempt to migrate this definition. */
92 char has_ambiguous_use
;
93 /* live_range is an approximation to the true live range for this
94 def/use web, because it records the set of blocks that contain
95 the live range. There could be other live ranges for the same
96 branch register in that set of blocks, either in the block
97 containing the def (before the def), or in a block containing
98 a use (after the use). If there are such other live ranges, then
99 other_btr_uses_before_def or other_btr_uses_after_use must be set true
101 char other_btr_uses_before_def
;
102 char other_btr_uses_after_use
;
103 /* We set own_end when we have moved a definition into a dominator.
104 Thus, when a later combination removes this definition again, we know
105 to clear out trs_live_at_end again. */
110 static int issue_rate
;
112 static int basic_block_freq (basic_block
);
113 static int insn_sets_btr_p (rtx
, int, int *);
114 static rtx
*find_btr_use (rtx
);
115 static int btr_referenced_p (rtx
, rtx
*);
116 static int find_btr_reference (rtx
*, void *);
117 static void find_btr_def_group (btr_def_group
*, btr_def
);
118 static btr_def
add_btr_def (fibheap_t
, basic_block
, int, rtx
,
119 unsigned int, int, btr_def_group
*);
120 static btr_user
new_btr_user (basic_block
, int, rtx
);
121 static void dump_hard_reg_set (HARD_REG_SET
);
122 static void dump_btrs_live (int);
123 static void note_other_use_this_block (unsigned int, btr_user
);
124 static void compute_defs_uses_and_gen (fibheap_t
, btr_def
*,btr_user
*,
125 sbitmap
*, sbitmap
*, HARD_REG_SET
*);
126 static void compute_kill (sbitmap
*, sbitmap
*, HARD_REG_SET
*);
127 static void compute_out (sbitmap
*bb_out
, sbitmap
*, sbitmap
*, int);
128 static void link_btr_uses (btr_def
*, btr_user
*, sbitmap
*, sbitmap
*, int);
129 static void build_btr_def_use_webs (fibheap_t
);
130 static int block_at_edge_of_live_range_p (int, btr_def
);
131 static void clear_btr_from_live_range (btr_def def
);
132 static void add_btr_to_live_range (btr_def
, int);
133 static void augment_live_range (bitmap
, HARD_REG_SET
*, basic_block
,
135 static int choose_btr (HARD_REG_SET
);
136 static void combine_btr_defs (btr_def
, HARD_REG_SET
*);
137 static void btr_def_live_range (btr_def
, HARD_REG_SET
*);
138 static void move_btr_def (basic_block
, int, btr_def
, bitmap
, HARD_REG_SET
*);
139 static int migrate_btr_def (btr_def
, int);
140 static void migrate_btr_defs (enum reg_class
, int);
141 static int can_move_up (basic_block
, rtx
, int);
142 static void note_btr_set (rtx
, rtx
, void *);
144 /* The following code performs code motion of target load instructions
145 (instructions that set branch target registers), to move them
146 forward away from the branch instructions and out of loops (or,
147 more generally, from a more frequently executed place to a less
148 frequently executed place).
149 Moving target load instructions further in front of the branch
150 instruction that uses the target register value means that the hardware
151 has a better chance of preloading the instructions at the branch
152 target by the time the branch is reached. This avoids bubbles
153 when a taken branch needs to flush out the pipeline.
154 Moving target load instructions out of loops means they are executed
157 /* An obstack to hold the def-use web data structures built up for
158 migrating branch target load instructions. */
159 static struct obstack migrate_btrl_obstack
;
161 /* Array indexed by basic block number, giving the set of registers
162 live in that block. */
163 static HARD_REG_SET
*btrs_live
;
165 /* Array indexed by basic block number, giving the set of registers live at
166 the end of that block, including any uses by a final jump insn, if any. */
167 static HARD_REG_SET
*btrs_live_at_end
;
169 /* Set of all target registers that we are willing to allocate. */
170 static HARD_REG_SET all_btrs
;
172 /* Provide lower and upper bounds for target register numbers, so that
173 we don't need to search through all the hard registers all the time. */
174 static int first_btr
, last_btr
;
178 /* Return an estimate of the frequency of execution of block bb. */
180 basic_block_freq (basic_block bb
)
182 return bb
->frequency
;
185 static rtx
*btr_reference_found
;
187 /* A subroutine of btr_referenced_p, called through for_each_rtx.
188 PREG is a pointer to an rtx that is to be excluded from the
189 traversal. If we find a reference to a target register anywhere
190 else, return 1, and put a pointer to it into btr_reference_found. */
192 find_btr_reference (rtx
*px
, void *preg
)
203 for (i
= hard_regno_nregs
[regno
][GET_MODE (x
)] - 1; i
>= 0; i
--)
204 if (TEST_HARD_REG_BIT (all_btrs
, regno
+i
))
206 btr_reference_found
= px
;
212 /* Return nonzero if X references (sets or reads) any branch target register.
213 If EXCLUDEP is set, disregard any references within the rtx pointed to
214 by it. If returning nonzero, also set btr_reference_found as above. */
216 btr_referenced_p (rtx x
, rtx
*excludep
)
218 return for_each_rtx (&x
, find_btr_reference
, excludep
);
221 /* Return true if insn is an instruction that sets a target register.
222 if CHECK_CONST is true, only return true if the source is constant.
223 If such a set is found and REGNO is nonzero, assign the register number
224 of the destination register to *REGNO. */
226 insn_sets_btr_p (rtx insn
, int check_const
, int *regno
)
230 if (NONJUMP_INSN_P (insn
)
231 && (set
= single_set (insn
)))
233 rtx dest
= SET_DEST (set
);
234 rtx src
= SET_SRC (set
);
236 if (GET_CODE (dest
) == SUBREG
)
237 dest
= XEXP (dest
, 0);
240 && TEST_HARD_REG_BIT (all_btrs
, REGNO (dest
)))
242 gcc_assert (!btr_referenced_p (src
, NULL
));
244 if (!check_const
|| CONSTANT_P (src
))
247 *regno
= REGNO (dest
);
255 /* Find and return a use of a target register within an instruction INSN. */
257 find_btr_use (rtx insn
)
259 return btr_referenced_p (insn
, NULL
) ? btr_reference_found
: NULL
;
262 /* Find the group that the target register definition DEF belongs
263 to in the list starting with *ALL_BTR_DEF_GROUPS. If no such
264 group exists, create one. Add def to the group. */
266 find_btr_def_group (btr_def_group
*all_btr_def_groups
, btr_def def
)
268 if (insn_sets_btr_p (def
->insn
, 1, NULL
))
270 btr_def_group this_group
;
271 rtx def_src
= SET_SRC (single_set (def
->insn
));
273 /* ?? This linear search is an efficiency concern, particularly
274 as the search will almost always fail to find a match. */
275 for (this_group
= *all_btr_def_groups
;
277 this_group
= this_group
->next
)
278 if (rtx_equal_p (def_src
, this_group
->src
))
283 this_group
= obstack_alloc (&migrate_btrl_obstack
,
284 sizeof (struct btr_def_group_s
));
285 this_group
->src
= def_src
;
286 this_group
->members
= NULL
;
287 this_group
->next
= *all_btr_def_groups
;
288 *all_btr_def_groups
= this_group
;
290 def
->group
= this_group
;
291 def
->next_this_group
= this_group
->members
;
292 this_group
->members
= def
;
298 /* Create a new target register definition structure, for a definition in
299 block BB, instruction INSN, and insert it into ALL_BTR_DEFS. Return
300 the new definition. */
302 add_btr_def (fibheap_t all_btr_defs
, basic_block bb
, int insn_luid
, rtx insn
,
303 unsigned int dest_reg
, int other_btr_uses_before_def
,
304 btr_def_group
*all_btr_def_groups
)
307 = obstack_alloc (&migrate_btrl_obstack
, sizeof (struct btr_def_s
));
309 this->luid
= insn_luid
;
311 this->btr
= dest_reg
;
312 this->cost
= basic_block_freq (bb
);
313 this->has_ambiguous_use
= 0;
314 this->other_btr_uses_before_def
= other_btr_uses_before_def
;
315 this->other_btr_uses_after_use
= 0;
316 this->next_this_bb
= NULL
;
317 this->next_this_group
= NULL
;
319 this->live_range
= NULL
;
320 find_btr_def_group (all_btr_def_groups
, this);
322 fibheap_insert (all_btr_defs
, -this->cost
, this);
326 "Found target reg definition: sets %u { bb %d, insn %d }%s priority %d\n",
327 dest_reg
, bb
->index
, INSN_UID (insn
), (this->group
? "" : ":not const"),
333 /* Create a new target register user structure, for a use in block BB,
334 instruction INSN. Return the new user. */
336 new_btr_user (basic_block bb
, int insn_luid
, rtx insn
)
338 /* This instruction reads target registers. We need
339 to decide whether we can replace all target register
342 rtx
*usep
= find_btr_use (PATTERN (insn
));
344 btr_user user
= NULL
;
348 int unambiguous_single_use
;
350 /* We want to ensure that USE is the only use of a target
351 register in INSN, so that we know that to rewrite INSN to use
352 a different target register, all we have to do is replace USE. */
353 unambiguous_single_use
= !btr_referenced_p (PATTERN (insn
), usep
);
354 if (!unambiguous_single_use
)
357 use
= usep
? *usep
: NULL_RTX
;
358 user
= obstack_alloc (&migrate_btrl_obstack
, sizeof (struct btr_user_s
));
360 user
->luid
= insn_luid
;
363 user
->other_use_this_block
= 0;
365 user
->n_reaching_defs
= 0;
366 user
->first_reaching_def
= -1;
370 fprintf (dump_file
, "Uses target reg: { bb %d, insn %d }",
371 bb
->index
, INSN_UID (insn
));
374 fprintf (dump_file
, ": unambiguous use of reg %d\n",
381 /* Write the contents of S to the dump file. */
383 dump_hard_reg_set (HARD_REG_SET s
)
386 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
387 if (TEST_HARD_REG_BIT (s
, reg
))
388 fprintf (dump_file
, " %d", reg
);
391 /* Write the set of target regs live in block BB to the dump file. */
393 dump_btrs_live (int bb
)
395 fprintf (dump_file
, "BB%d live:", bb
);
396 dump_hard_reg_set (btrs_live
[bb
]);
397 fprintf (dump_file
, "\n");
400 /* REGNO is the number of a branch target register that is being used or
401 set. USERS_THIS_BB is a list of preceding branch target register users;
402 If any of them use the same register, set their other_use_this_block
405 note_other_use_this_block (unsigned int regno
, btr_user users_this_bb
)
409 for (user
= users_this_bb
; user
!= NULL
; user
= user
->next
)
410 if (user
->use
&& REGNO (user
->use
) == regno
)
411 user
->other_use_this_block
= 1;
415 btr_user users_this_bb
;
416 HARD_REG_SET btrs_written_in_block
;
417 HARD_REG_SET btrs_live_in_block
;
422 /* Called via note_stores or directly to register stores into /
423 clobbers of a branch target register DEST that are not recognized as
424 straightforward definitions. DATA points to information about the
425 current basic block that needs updating. */
427 note_btr_set (rtx dest
, rtx set ATTRIBUTE_UNUSED
, void *data
)
429 defs_uses_info
*info
= data
;
430 int regno
, end_regno
;
434 regno
= REGNO (dest
);
435 end_regno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (dest
)];
436 for (; regno
< end_regno
; regno
++)
437 if (TEST_HARD_REG_BIT (all_btrs
, regno
))
439 note_other_use_this_block (regno
, info
->users_this_bb
);
440 SET_HARD_REG_BIT (info
->btrs_written_in_block
, regno
);
441 SET_HARD_REG_BIT (info
->btrs_live_in_block
, regno
);
442 sbitmap_difference (info
->bb_gen
, info
->bb_gen
,
443 info
->btr_defset
[regno
- first_btr
]);
448 compute_defs_uses_and_gen (fibheap_t all_btr_defs
, btr_def
*def_array
,
449 btr_user
*use_array
, sbitmap
*btr_defset
,
450 sbitmap
*bb_gen
, HARD_REG_SET
*btrs_written
)
452 /* Scan the code building up the set of all defs and all uses.
453 For each target register, build the set of defs of that register.
454 For each block, calculate the set of target registers
455 written in that block.
456 Also calculate the set of btrs ever live in that block.
460 btr_def_group all_btr_def_groups
= NULL
;
463 sbitmap_vector_zero (bb_gen
, n_basic_blocks
);
464 for (i
= NUM_FIXED_BLOCKS
; i
< n_basic_blocks
; i
++)
466 basic_block bb
= BASIC_BLOCK (i
);
468 btr_def defs_this_bb
= NULL
;
473 info
.users_this_bb
= NULL
;
474 info
.bb_gen
= bb_gen
[i
];
475 info
.btr_defset
= btr_defset
;
477 CLEAR_HARD_REG_SET (info
.btrs_live_in_block
);
478 CLEAR_HARD_REG_SET (info
.btrs_written_in_block
);
479 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
480 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
481 && REGNO_REG_SET_P (bb
->il
.rtl
->global_live_at_start
, reg
))
482 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
484 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
486 insn
= NEXT_INSN (insn
), insn_luid
++)
491 int insn_uid
= INSN_UID (insn
);
493 if (insn_sets_btr_p (insn
, 0, ®no
))
495 btr_def def
= add_btr_def (
496 all_btr_defs
, bb
, insn_luid
, insn
, regno
,
497 TEST_HARD_REG_BIT (info
.btrs_live_in_block
, regno
),
498 &all_btr_def_groups
);
500 def_array
[insn_uid
] = def
;
501 SET_HARD_REG_BIT (info
.btrs_written_in_block
, regno
);
502 SET_HARD_REG_BIT (info
.btrs_live_in_block
, regno
);
503 sbitmap_difference (bb_gen
[i
], bb_gen
[i
],
504 btr_defset
[regno
- first_btr
]);
505 SET_BIT (bb_gen
[i
], insn_uid
);
506 def
->next_this_bb
= defs_this_bb
;
508 SET_BIT (btr_defset
[regno
- first_btr
], insn_uid
);
509 note_other_use_this_block (regno
, info
.users_this_bb
);
511 /* Check for the blockage emitted by expand_nl_goto_receiver. */
512 else if (current_function_has_nonlocal_label
513 && GET_CODE (PATTERN (insn
)) == ASM_INPUT
)
517 /* Do the equivalent of calling note_other_use_this_block
518 for every target register. */
519 for (user
= info
.users_this_bb
; user
!= NULL
;
522 user
->other_use_this_block
= 1;
523 IOR_HARD_REG_SET (info
.btrs_written_in_block
, all_btrs
);
524 IOR_HARD_REG_SET (info
.btrs_live_in_block
, all_btrs
);
525 sbitmap_zero (info
.bb_gen
);
529 if (btr_referenced_p (PATTERN (insn
), NULL
))
531 btr_user user
= new_btr_user (bb
, insn_luid
, insn
);
533 use_array
[insn_uid
] = user
;
535 SET_HARD_REG_BIT (info
.btrs_live_in_block
,
540 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
541 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
542 && refers_to_regno_p (reg
, reg
+ 1, user
->insn
,
545 note_other_use_this_block (reg
,
547 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
549 note_stores (PATTERN (insn
), note_btr_set
, &info
);
551 user
->next
= info
.users_this_bb
;
552 info
.users_this_bb
= user
;
556 HARD_REG_SET
*clobbered
= &call_used_reg_set
;
557 HARD_REG_SET call_saved
;
558 rtx pat
= PATTERN (insn
);
561 /* Check for sibcall. */
562 if (GET_CODE (pat
) == PARALLEL
)
563 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
564 if (GET_CODE (XVECEXP (pat
, 0, i
)) == RETURN
)
566 COMPL_HARD_REG_SET (call_saved
,
568 clobbered
= &call_saved
;
571 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
572 if (TEST_HARD_REG_BIT (*clobbered
, regno
))
573 note_btr_set (regno_reg_rtx
[regno
], NULL_RTX
, &info
);
579 COPY_HARD_REG_SET (btrs_live
[i
], info
.btrs_live_in_block
);
580 COPY_HARD_REG_SET (btrs_written
[i
], info
.btrs_written_in_block
);
582 REG_SET_TO_HARD_REG_SET (btrs_live_at_end
[i
], bb
->il
.rtl
->global_live_at_end
);
583 /* If this block ends in a jump insn, add any uses or even clobbers
584 of branch target registers that it might have. */
585 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
) && ! INSN_P (insn
); )
586 insn
= PREV_INSN (insn
);
587 /* ??? for the fall-through edge, it would make sense to insert the
588 btr set on the edge, but that would require to split the block
589 early on so that we can distinguish between dominance from the fall
590 through edge - which can use the call-clobbered registers - from
591 dominance by the throw edge. */
592 if (can_throw_internal (insn
))
596 COPY_HARD_REG_SET (tmp
, call_used_reg_set
);
597 AND_HARD_REG_SET (tmp
, all_btrs
);
598 IOR_HARD_REG_SET (btrs_live_at_end
[i
], tmp
);
601 if (can_throw
|| JUMP_P (insn
))
605 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
606 if (refers_to_regno_p (regno
, regno
+1, insn
, NULL
))
607 SET_HARD_REG_BIT (btrs_live_at_end
[i
], regno
);
616 compute_kill (sbitmap
*bb_kill
, sbitmap
*btr_defset
,
617 HARD_REG_SET
*btrs_written
)
622 /* For each basic block, form the set BB_KILL - the set
623 of definitions that the block kills. */
624 sbitmap_vector_zero (bb_kill
, n_basic_blocks
);
625 for (i
= NUM_FIXED_BLOCKS
; i
< n_basic_blocks
; i
++)
627 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
628 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
629 && TEST_HARD_REG_BIT (btrs_written
[i
], regno
))
630 sbitmap_a_or_b (bb_kill
[i
], bb_kill
[i
],
631 btr_defset
[regno
- first_btr
]);
636 compute_out (sbitmap
*bb_out
, sbitmap
*bb_gen
, sbitmap
*bb_kill
, int max_uid
)
638 /* Perform iterative dataflow:
639 Initially, for all blocks, BB_OUT = BB_GEN.
641 BB_IN = union over predecessors of BB_OUT(pred)
642 BB_OUT = (BB_IN - BB_KILL) + BB_GEN
643 Iterate until the bb_out sets stop growing. */
646 sbitmap bb_in
= sbitmap_alloc (max_uid
);
648 for (i
= NUM_FIXED_BLOCKS
; i
< n_basic_blocks
; i
++)
649 sbitmap_copy (bb_out
[i
], bb_gen
[i
]);
655 for (i
= NUM_FIXED_BLOCKS
; i
< n_basic_blocks
; i
++)
657 sbitmap_union_of_preds (bb_in
, bb_out
, i
);
658 changed
|= sbitmap_union_of_diff_cg (bb_out
[i
], bb_gen
[i
],
662 sbitmap_free (bb_in
);
666 link_btr_uses (btr_def
*def_array
, btr_user
*use_array
, sbitmap
*bb_out
,
667 sbitmap
*btr_defset
, int max_uid
)
670 sbitmap reaching_defs
= sbitmap_alloc (max_uid
);
672 /* Link uses to the uses lists of all of their reaching defs.
673 Count up the number of reaching defs of each use. */
674 for (i
= NUM_FIXED_BLOCKS
; i
< n_basic_blocks
; i
++)
676 basic_block bb
= BASIC_BLOCK (i
);
680 sbitmap_union_of_preds (reaching_defs
, bb_out
, i
);
681 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
683 insn
= NEXT_INSN (insn
))
687 int insn_uid
= INSN_UID (insn
);
689 btr_def def
= def_array
[insn_uid
];
690 btr_user user
= use_array
[insn_uid
];
693 /* Remove all reaching defs of regno except
695 sbitmap_difference (reaching_defs
, reaching_defs
,
696 btr_defset
[def
->btr
- first_btr
]);
697 SET_BIT(reaching_defs
, insn_uid
);
702 /* Find all the reaching defs for this use. */
703 sbitmap reaching_defs_of_reg
= sbitmap_alloc(max_uid
);
704 unsigned int uid
= 0;
705 sbitmap_iterator sbi
;
709 reaching_defs_of_reg
,
711 btr_defset
[REGNO (user
->use
) - first_btr
]);
716 sbitmap_zero (reaching_defs_of_reg
);
717 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
718 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
719 && refers_to_regno_p (reg
, reg
+ 1, user
->insn
,
721 sbitmap_a_or_b_and_c (reaching_defs_of_reg
,
722 reaching_defs_of_reg
,
724 btr_defset
[reg
- first_btr
]);
726 EXECUTE_IF_SET_IN_SBITMAP (reaching_defs_of_reg
, 0, uid
, sbi
)
728 btr_def def
= def_array
[uid
];
730 /* We now know that def reaches user. */
734 "Def in insn %d reaches use in insn %d\n",
737 user
->n_reaching_defs
++;
739 def
->has_ambiguous_use
= 1;
740 if (user
->first_reaching_def
!= -1)
741 { /* There is more than one reaching def. This is
742 a rare case, so just give up on this def/use
743 web when it occurs. */
744 def
->has_ambiguous_use
= 1;
745 def_array
[user
->first_reaching_def
]
746 ->has_ambiguous_use
= 1;
749 "(use %d has multiple reaching defs)\n",
753 user
->first_reaching_def
= uid
;
754 if (user
->other_use_this_block
)
755 def
->other_btr_uses_after_use
= 1;
756 user
->next
= def
->uses
;
759 sbitmap_free (reaching_defs_of_reg
);
766 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
767 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
768 && TEST_HARD_REG_BIT (call_used_reg_set
, regno
))
769 sbitmap_difference (reaching_defs
, reaching_defs
,
770 btr_defset
[regno
- first_btr
]);
775 sbitmap_free (reaching_defs
);
779 build_btr_def_use_webs (fibheap_t all_btr_defs
)
781 const int max_uid
= get_max_uid ();
782 btr_def
*def_array
= XCNEWVEC (btr_def
, max_uid
);
783 btr_user
*use_array
= XCNEWVEC (btr_user
, max_uid
);
784 sbitmap
*btr_defset
= sbitmap_vector_alloc (
785 (last_btr
- first_btr
) + 1, max_uid
);
786 sbitmap
*bb_gen
= sbitmap_vector_alloc (n_basic_blocks
, max_uid
);
787 HARD_REG_SET
*btrs_written
= XCNEWVEC (HARD_REG_SET
, n_basic_blocks
);
791 sbitmap_vector_zero (btr_defset
, (last_btr
- first_btr
) + 1);
793 compute_defs_uses_and_gen (all_btr_defs
, def_array
, use_array
, btr_defset
,
794 bb_gen
, btrs_written
);
796 bb_kill
= sbitmap_vector_alloc (n_basic_blocks
, max_uid
);
797 compute_kill (bb_kill
, btr_defset
, btrs_written
);
800 bb_out
= sbitmap_vector_alloc (n_basic_blocks
, max_uid
);
801 compute_out (bb_out
, bb_gen
, bb_kill
, max_uid
);
803 sbitmap_vector_free (bb_gen
);
804 sbitmap_vector_free (bb_kill
);
806 link_btr_uses (def_array
, use_array
, bb_out
, btr_defset
, max_uid
);
808 sbitmap_vector_free (bb_out
);
809 sbitmap_vector_free (btr_defset
);
814 /* Return true if basic block BB contains the start or end of the
815 live range of the definition DEF, AND there are other live
816 ranges of the same target register that include BB. */
818 block_at_edge_of_live_range_p (int bb
, btr_def def
)
820 if (def
->other_btr_uses_before_def
&& BASIC_BLOCK (bb
) == def
->bb
)
822 else if (def
->other_btr_uses_after_use
)
825 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
826 if (BASIC_BLOCK (bb
) == user
->bb
)
832 /* We are removing the def/use web DEF. The target register
833 used in this web is therefore no longer live in the live range
834 of this web, so remove it from the live set of all basic blocks
835 in the live range of the web.
836 Blocks at the boundary of the live range may contain other live
837 ranges for the same target register, so we have to be careful
838 to remove the target register from the live set of these blocks
839 only if they do not contain other live ranges for the same register. */
841 clear_btr_from_live_range (btr_def def
)
846 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
848 if ((!def
->other_btr_uses_before_def
849 && !def
->other_btr_uses_after_use
)
850 || !block_at_edge_of_live_range_p (bb
, def
))
852 CLEAR_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
853 CLEAR_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
859 CLEAR_HARD_REG_BIT (btrs_live_at_end
[def
->bb
->index
], def
->btr
);
863 /* We are adding the def/use web DEF. Add the target register used
864 in this web to the live set of all of the basic blocks that contain
865 the live range of the web.
866 If OWN_END is set, also show that the register is live from our
867 definitions at the end of the basic block where it is defined. */
869 add_btr_to_live_range (btr_def def
, int own_end
)
874 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
876 SET_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
877 SET_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
883 SET_HARD_REG_BIT (btrs_live_at_end
[def
->bb
->index
], def
->btr
);
888 /* Update a live range to contain the basic block NEW_BLOCK, and all
889 blocks on paths between the existing live range and NEW_BLOCK.
890 HEAD is a block contained in the existing live range that dominates
891 all other blocks in the existing live range.
892 Also add to the set BTRS_LIVE_IN_RANGE all target registers that
893 are live in the blocks that we add to the live range.
894 If FULL_RANGE is set, include the full live range of NEW_BB;
895 otherwise, if NEW_BB dominates HEAD_BB, only add registers that
896 are life at the end of NEW_BB for NEW_BB itself.
897 It is a precondition that either NEW_BLOCK dominates HEAD,or
898 HEAD dom NEW_BLOCK. This is used to speed up the
899 implementation of this function. */
901 augment_live_range (bitmap live_range
, HARD_REG_SET
*btrs_live_in_range
,
902 basic_block head_bb
, basic_block new_bb
, int full_range
)
904 basic_block
*worklist
, *tos
;
906 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks
+ 1);
908 if (dominated_by_p (CDI_DOMINATORS
, new_bb
, head_bb
))
910 if (new_bb
== head_bb
)
913 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[new_bb
->index
]);
923 int new_block
= new_bb
->index
;
925 gcc_assert (dominated_by_p (CDI_DOMINATORS
, head_bb
, new_bb
));
927 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[head_bb
->index
]);
928 bitmap_set_bit (live_range
, new_block
);
929 /* A previous btr migration could have caused a register to be
930 live just at the end of new_block which we need in full, so
931 use trs_live_at_end even if full_range is set. */
932 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live_at_end
[new_block
]);
934 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[new_block
]);
938 "Adding end of block %d and rest of %d to live range\n",
939 new_block
, head_bb
->index
);
940 fprintf (dump_file
,"Now live btrs are ");
941 dump_hard_reg_set (*btrs_live_in_range
);
942 fprintf (dump_file
, "\n");
944 FOR_EACH_EDGE (e
, ei
, head_bb
->preds
)
948 while (tos
!= worklist
)
950 basic_block bb
= *--tos
;
951 if (!bitmap_bit_p (live_range
, bb
->index
))
956 bitmap_set_bit (live_range
, bb
->index
);
957 IOR_HARD_REG_SET (*btrs_live_in_range
,
958 btrs_live
[bb
->index
]);
959 /* A previous btr migration could have caused a register to be
960 live just at the end of a block which we need in full. */
961 IOR_HARD_REG_SET (*btrs_live_in_range
,
962 btrs_live_at_end
[bb
->index
]);
966 "Adding block %d to live range\n", bb
->index
);
967 fprintf (dump_file
,"Now live btrs are ");
968 dump_hard_reg_set (*btrs_live_in_range
);
969 fprintf (dump_file
, "\n");
972 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
974 basic_block pred
= e
->src
;
975 if (!bitmap_bit_p (live_range
, pred
->index
))
984 /* Return the most desirable target register that is not in
985 the set USED_BTRS. */
987 choose_btr (HARD_REG_SET used_btrs
)
990 GO_IF_HARD_REG_SUBSET (all_btrs
, used_btrs
, give_up
);
992 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
994 #ifdef REG_ALLOC_ORDER
995 int regno
= reg_alloc_order
[i
];
999 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
1000 && !TEST_HARD_REG_BIT (used_btrs
, regno
))
1007 /* Calculate the set of basic blocks that contain the live range of
1008 the def/use web DEF.
1009 Also calculate the set of target registers that are live at time
1010 in this live range, but ignore the live range represented by DEF
1011 when calculating this set. */
1013 btr_def_live_range (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
1015 if (!def
->live_range
)
1019 def
->live_range
= BITMAP_ALLOC (NULL
);
1021 bitmap_set_bit (def
->live_range
, def
->bb
->index
);
1022 COPY_HARD_REG_SET (*btrs_live_in_range
,
1023 (flag_btr_bb_exclusive
1024 ? btrs_live
: btrs_live_at_end
)[def
->bb
->index
]);
1026 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1027 augment_live_range (def
->live_range
, btrs_live_in_range
,
1029 (flag_btr_bb_exclusive
1030 || user
->insn
!= BB_END (def
->bb
)
1031 || !JUMP_P (user
->insn
)));
1035 /* def->live_range is accurate, but we need to recompute
1036 the set of target registers live over it, because migration
1037 of other PT instructions may have affected it.
1040 unsigned def_bb
= flag_btr_bb_exclusive
? -1 : def
->bb
->index
;
1043 CLEAR_HARD_REG_SET (*btrs_live_in_range
);
1044 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
1046 IOR_HARD_REG_SET (*btrs_live_in_range
,
1048 ? btrs_live_at_end
: btrs_live
) [bb
]);
1051 if (!def
->other_btr_uses_before_def
&&
1052 !def
->other_btr_uses_after_use
)
1053 CLEAR_HARD_REG_BIT (*btrs_live_in_range
, def
->btr
);
1056 /* Merge into the def/use web DEF any other def/use webs in the same
1057 group that are dominated by DEF, provided that there is a target
1058 register available to allocate to the merged web. */
1060 combine_btr_defs (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
1064 for (other_def
= def
->group
->members
;
1066 other_def
= other_def
->next_this_group
)
1068 if (other_def
!= def
1069 && other_def
->uses
!= NULL
1070 && ! other_def
->has_ambiguous_use
1071 && dominated_by_p (CDI_DOMINATORS
, other_def
->bb
, def
->bb
))
1073 /* def->bb dominates the other def, so def and other_def could
1075 /* Merge their live ranges, and get the set of
1076 target registers live over the merged range. */
1078 HARD_REG_SET combined_btrs_live
;
1079 bitmap combined_live_range
= BITMAP_ALLOC (NULL
);
1082 if (other_def
->live_range
== NULL
)
1084 HARD_REG_SET dummy_btrs_live_in_range
;
1085 btr_def_live_range (other_def
, &dummy_btrs_live_in_range
);
1087 COPY_HARD_REG_SET (combined_btrs_live
, *btrs_live_in_range
);
1088 bitmap_copy (combined_live_range
, def
->live_range
);
1090 for (user
= other_def
->uses
; user
!= NULL
; user
= user
->next
)
1091 augment_live_range (combined_live_range
, &combined_btrs_live
,
1093 (flag_btr_bb_exclusive
1094 || user
->insn
!= BB_END (def
->bb
)
1095 || !JUMP_P (user
->insn
)));
1097 btr
= choose_btr (combined_btrs_live
);
1100 /* We can combine them. */
1103 "Combining def in insn %d with def in insn %d\n",
1104 INSN_UID (other_def
->insn
), INSN_UID (def
->insn
));
1107 user
= other_def
->uses
;
1108 while (user
!= NULL
)
1110 btr_user next
= user
->next
;
1112 user
->next
= def
->uses
;
1116 /* Combining def/use webs can make target registers live
1117 after uses where they previously were not. This means
1118 some REG_DEAD notes may no longer be correct. We could
1119 be more precise about this if we looked at the combined
1120 live range, but here I just delete any REG_DEAD notes
1121 in case they are no longer correct. */
1122 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1123 remove_note (user
->insn
,
1124 find_regno_note (user
->insn
, REG_DEAD
,
1125 REGNO (user
->use
)));
1126 clear_btr_from_live_range (other_def
);
1127 other_def
->uses
= NULL
;
1128 bitmap_copy (def
->live_range
, combined_live_range
);
1129 if (other_def
->btr
== btr
&& other_def
->other_btr_uses_after_use
)
1130 def
->other_btr_uses_after_use
= 1;
1131 COPY_HARD_REG_SET (*btrs_live_in_range
, combined_btrs_live
);
1133 /* Delete the old target register initialization. */
1134 delete_insn (other_def
->insn
);
1137 BITMAP_FREE (combined_live_range
);
1142 /* Move the definition DEF from its current position to basic
1143 block NEW_DEF_BB, and modify it to use branch target register BTR.
1144 Delete the old defining insn, and insert a new one in NEW_DEF_BB.
1145 Update all reaching uses of DEF in the RTL to use BTR.
1146 If this new position means that other defs in the
1147 same group can be combined with DEF then combine them. */
1149 move_btr_def (basic_block new_def_bb
, int btr
, btr_def def
, bitmap live_range
,
1150 HARD_REG_SET
*btrs_live_in_range
)
1152 /* We can move the instruction.
1153 Set a target register in block NEW_DEF_BB to the value
1154 needed for this target register definition.
1155 Replace all uses of the old target register definition by
1156 uses of the new definition. Delete the old definition. */
1157 basic_block b
= new_def_bb
;
1158 rtx insp
= BB_HEAD (b
);
1159 rtx old_insn
= def
->insn
;
1163 enum machine_mode btr_mode
;
1168 fprintf(dump_file
, "migrating to basic block %d, using reg %d\n",
1169 new_def_bb
->index
, btr
);
1171 clear_btr_from_live_range (def
);
1173 def
->bb
= new_def_bb
;
1175 def
->cost
= basic_block_freq (new_def_bb
);
1176 bitmap_copy (def
->live_range
, live_range
);
1177 combine_btr_defs (def
, btrs_live_in_range
);
1179 def
->other_btr_uses_before_def
1180 = TEST_HARD_REG_BIT (btrs_live
[b
->index
], btr
) ? 1 : 0;
1181 add_btr_to_live_range (def
, 1);
1183 insp
= NEXT_INSN (insp
);
1184 /* N.B.: insp is expected to be NOTE_INSN_BASIC_BLOCK now. Some
1185 optimizations can result in insp being both first and last insn of
1187 /* ?? some assertions to check that insp is sensible? */
1189 if (def
->other_btr_uses_before_def
)
1192 for (insp
= BB_END (b
); ! INSN_P (insp
); insp
= PREV_INSN (insp
))
1193 gcc_assert (insp
!= BB_HEAD (b
));
1195 if (JUMP_P (insp
) || can_throw_internal (insp
))
1196 insp
= PREV_INSN (insp
);
1199 set
= single_set (old_insn
);
1200 src
= SET_SRC (set
);
1201 btr_mode
= GET_MODE (SET_DEST (set
));
1202 btr_rtx
= gen_rtx_REG (btr_mode
, btr
);
1204 new_insn
= gen_move_insn (btr_rtx
, src
);
1206 /* Insert target register initialization at head of basic block. */
1207 def
->insn
= emit_insn_after (new_insn
, insp
);
1209 regs_ever_live
[btr
] = 1;
1212 fprintf (dump_file
, "New pt is insn %d, inserted after insn %d\n",
1213 INSN_UID (def
->insn
), INSN_UID (insp
));
1215 /* Delete the old target register initialization. */
1216 delete_insn (old_insn
);
1218 /* Replace each use of the old target register by a use of the new target
1220 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1222 /* Some extra work here to ensure consistent modes, because
1223 it seems that a target register REG rtx can be given a different
1224 mode depending on the context (surely that should not be
1226 rtx replacement_rtx
;
1227 if (GET_MODE (user
->use
) == GET_MODE (btr_rtx
)
1228 || GET_MODE (user
->use
) == VOIDmode
)
1229 replacement_rtx
= btr_rtx
;
1231 replacement_rtx
= gen_rtx_REG (GET_MODE (user
->use
), btr
);
1232 replace_rtx (user
->insn
, user
->use
, replacement_rtx
);
1233 user
->use
= replacement_rtx
;
1237 /* We anticipate intra-block scheduling to be done. See if INSN could move
1238 up within BB by N_INSNS. */
1240 can_move_up (basic_block bb
, rtx insn
, int n_insns
)
1242 while (insn
!= BB_HEAD (bb
) && n_insns
> 0)
1244 insn
= PREV_INSN (insn
);
1245 /* ??? What if we have an anti-dependency that actually prevents the
1246 scheduler from doing the move? We'd like to re-allocate the register,
1247 but not necessarily put the load into another basic block. */
1251 return n_insns
<= 0;
1254 /* Attempt to migrate the target register definition DEF to an
1255 earlier point in the flowgraph.
1257 It is a precondition of this function that DEF is migratable:
1258 i.e. it has a constant source, and all uses are unambiguous.
1260 Only migrations that reduce the cost of DEF will be made.
1261 MIN_COST is the lower bound on the cost of the DEF after migration.
1262 If we migrate DEF so that its cost falls below MIN_COST,
1263 then we do not attempt to migrate further. The idea is that
1264 we migrate definitions in a priority order based on their cost,
1265 when the cost of this definition falls below MIN_COST, then
1266 there is another definition with cost == MIN_COST which now
1267 has a higher priority than this definition.
1269 Return nonzero if there may be benefit from attempting to
1270 migrate this DEF further (i.e. we have reduced the cost below
1271 MIN_COST, but we may be able to reduce it further).
1272 Return zero if no further migration is possible. */
1274 migrate_btr_def (btr_def def
, int min_cost
)
1277 HARD_REG_SET btrs_live_in_range
;
1278 int btr_used_near_def
= 0;
1279 int def_basic_block_freq
;
1288 "Attempting to migrate pt from insn %d (cost = %d, min_cost = %d) ... ",
1289 INSN_UID (def
->insn
), def
->cost
, min_cost
);
1291 if (!def
->group
|| def
->has_ambiguous_use
)
1292 /* These defs are not migratable. */
1295 fprintf (dump_file
, "it's not migratable\n");
1300 /* We have combined this def with another in the same group, so
1301 no need to consider it further.
1305 fprintf (dump_file
, "it's already combined with another pt\n");
1309 btr_def_live_range (def
, &btrs_live_in_range
);
1310 live_range
= BITMAP_ALLOC (NULL
);
1311 bitmap_copy (live_range
, def
->live_range
);
1313 #ifdef INSN_SCHEDULING
1314 def_latency
= insn_default_latency (def
->insn
) * issue_rate
;
1316 def_latency
= issue_rate
;
1319 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1321 if (user
->bb
== def
->bb
1322 && user
->luid
> def
->luid
1323 && (def
->luid
+ def_latency
) > user
->luid
1324 && ! can_move_up (def
->bb
, def
->insn
,
1325 (def
->luid
+ def_latency
) - user
->luid
))
1327 btr_used_near_def
= 1;
1332 def_basic_block_freq
= basic_block_freq (def
->bb
);
1334 for (try = get_immediate_dominator (CDI_DOMINATORS
, def
->bb
);
1335 !give_up
&& try && try != ENTRY_BLOCK_PTR
&& def
->cost
>= min_cost
;
1336 try = get_immediate_dominator (CDI_DOMINATORS
, try))
1338 /* Try to move the instruction that sets the target register into
1340 int try_freq
= basic_block_freq (try);
1344 /* If TRY has abnormal edges, skip it. */
1345 FOR_EACH_EDGE (e
, ei
, try->succs
)
1346 if (e
->flags
& EDGE_COMPLEX
)
1352 fprintf (dump_file
, "trying block %d ...", try->index
);
1354 if (try_freq
< def_basic_block_freq
1355 || (try_freq
== def_basic_block_freq
&& btr_used_near_def
))
1358 augment_live_range (live_range
, &btrs_live_in_range
, def
->bb
, try,
1359 flag_btr_bb_exclusive
);
1362 fprintf (dump_file
, "Now btrs live in range are: ");
1363 dump_hard_reg_set (btrs_live_in_range
);
1364 fprintf (dump_file
, "\n");
1366 btr
= choose_btr (btrs_live_in_range
);
1369 move_btr_def (try, btr
, def
, live_range
, &btrs_live_in_range
);
1370 bitmap_copy(live_range
, def
->live_range
);
1371 btr_used_near_def
= 0;
1373 def_basic_block_freq
= basic_block_freq (def
->bb
);
1377 /* There are no free target registers available to move
1378 this far forward, so give up */
1382 "giving up because there are no free target registers\n");
1391 fprintf (dump_file
, "failed to move\n");
1393 BITMAP_FREE (live_range
);
1397 /* Attempt to move instructions that set target registers earlier
1398 in the flowgraph, away from their corresponding uses. */
1400 migrate_btr_defs (enum reg_class btr_class
, int allow_callee_save
)
1402 fibheap_t all_btr_defs
= fibheap_new ();
1405 gcc_obstack_init (&migrate_btrl_obstack
);
1410 for (i
= NUM_FIXED_BLOCKS
; i
< n_basic_blocks
; i
++)
1412 basic_block bb
= BASIC_BLOCK (i
);
1414 "Basic block %d: count = " HOST_WIDEST_INT_PRINT_DEC
1415 " loop-depth = %d idom = %d\n",
1416 i
, (HOST_WIDEST_INT
) bb
->count
, bb
->loop_depth
,
1417 get_immediate_dominator (CDI_DOMINATORS
, bb
)->index
);
1421 CLEAR_HARD_REG_SET (all_btrs
);
1422 for (first_btr
= -1, reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
1423 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) btr_class
], reg
)
1424 && (allow_callee_save
|| call_used_regs
[reg
] || regs_ever_live
[reg
]))
1426 SET_HARD_REG_BIT (all_btrs
, reg
);
1432 btrs_live
= xcalloc (n_basic_blocks
, sizeof (HARD_REG_SET
));
1433 btrs_live_at_end
= xcalloc (n_basic_blocks
, sizeof (HARD_REG_SET
));
1435 build_btr_def_use_webs (all_btr_defs
);
1437 while (!fibheap_empty (all_btr_defs
))
1439 btr_def def
= fibheap_extract_min (all_btr_defs
);
1440 int min_cost
= -fibheap_min_key (all_btr_defs
);
1441 if (migrate_btr_def (def
, min_cost
))
1443 fibheap_insert (all_btr_defs
, -def
->cost
, (void *) def
);
1447 "Putting insn %d back on queue with priority %d\n",
1448 INSN_UID (def
->insn
), def
->cost
);
1452 BITMAP_FREE (def
->live_range
);
1456 free (btrs_live_at_end
);
1457 obstack_free (&migrate_btrl_obstack
, NULL
);
1458 fibheap_delete (all_btr_defs
);
1462 branch_target_load_optimize (bool after_prologue_epilogue_gen
)
1464 enum reg_class
class = targetm
.branch_target_register_class ();
1465 if (class != NO_REGS
)
1467 /* Initialize issue_rate. */
1468 if (targetm
.sched
.issue_rate
)
1469 issue_rate
= targetm
.sched
.issue_rate ();
1473 /* Build the CFG for migrate_btr_defs. */
1475 /* This may or may not be needed, depending on where we
1477 cleanup_cfg (optimize
? CLEANUP_EXPENSIVE
: 0);
1482 /* Dominator info is also needed for migrate_btr_def. */
1483 calculate_dominance_info (CDI_DOMINATORS
);
1484 migrate_btr_defs (class,
1485 (targetm
.branch_target_register_callee_saved
1486 (after_prologue_epilogue_gen
)));
1488 free_dominance_info (CDI_DOMINATORS
);
1490 update_life_info (NULL
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
1491 PROP_DEATH_NOTES
| PROP_REG_INFO
);
1496 gate_handle_branch_target_load_optimize (void)
1498 return (optimize
> 0 && flag_branch_target_load_optimize2
);
1503 rest_of_handle_branch_target_load_optimize (void)
1505 static int warned
= 0;
1507 /* Leave this a warning for now so that it is possible to experiment
1508 with running this pass twice. In 3.6, we should either make this
1509 an error, or use separate dump files. */
1510 if (flag_branch_target_load_optimize
1511 && flag_branch_target_load_optimize2
1514 warning (0, "branch target register load optimization is not intended "
1520 branch_target_load_optimize (epilogue_completed
);
1524 struct tree_opt_pass pass_branch_target_load_optimize
=
1527 gate_handle_branch_target_load_optimize
, /* gate */
1528 rest_of_handle_branch_target_load_optimize
, /* execute */
1531 0, /* static_pass_number */
1533 0, /* properties_required */
1534 0, /* properties_provided */
1535 0, /* properties_destroyed */
1536 0, /* todo_flags_start */
1538 TODO_ggc_collect
, /* todo_flags_finish */