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EnumSet*.class: Regenerate
[official-gcc.git] / gcc / longlong.h
blob0d8e01d3bf2ba6d3a7bd1fff9e4260e07250ed86
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2004,
3 2005, 2007 Free Software Foundation, Inc.
4
5 This definition file is free software; you can redistribute it
6 and/or modify it under the terms of the GNU General Public
7 License as published by the Free Software Foundation; either
8 version 3, or (at your option) any later version.
9
10 This definition file is distributed in the hope that it will be
11 useful, but WITHOUT ANY WARRANTY; without even the implied
12 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 See the GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING3. If not see
17 <http://www.gnu.org/licenses/>. */
18
19 /* You have to define the following before including this file:
20
21 UWtype -- An unsigned type, default type for operations (typically a "word")
22 UHWtype -- An unsigned type, at least half the size of UWtype.
23 UDWtype -- An unsigned type, at least twice as large a UWtype
24 W_TYPE_SIZE -- size in bits of UWtype
25
26 UQItype -- Unsigned 8 bit type.
27 SItype, USItype -- Signed and unsigned 32 bit types.
28 DItype, UDItype -- Signed and unsigned 64 bit types.
29
30 On a 32 bit machine UWtype should typically be USItype;
31 on a 64 bit machine, UWtype should typically be UDItype. */
32
33 #define __BITS4 (W_TYPE_SIZE / 4)
34 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
35 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
36 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
37
38 #ifndef W_TYPE_SIZE
39 #define W_TYPE_SIZE 32
40 #define UWtype USItype
41 #define UHWtype USItype
42 #define UDWtype UDItype
43 #endif
44
45 extern const UQItype __clz_tab[256];
46
47 /* Define auxiliary asm macros.
48
49 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
50 UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
51 word product in HIGH_PROD and LOW_PROD.
52
53 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
54 UDWtype product. This is just a variant of umul_ppmm.
55
56 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
57 denominator) divides a UDWtype, composed by the UWtype integers
58 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
59 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
60 than DENOMINATOR for correct operation. If, in addition, the most
61 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
62 UDIV_NEEDS_NORMALIZATION is defined to 1.
63
64 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
65 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
66 is rounded towards 0.
67
68 5) count_leading_zeros(count, x) counts the number of zero-bits from the
69 msb to the first nonzero bit in the UWtype X. This is the number of
70 steps X needs to be shifted left to set the msb. Undefined for X == 0,
71 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
72
73 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
74 from the least significant end.
75
76 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
77 high_addend_2, low_addend_2) adds two UWtype integers, composed by
78 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
79 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
80 (i.e. carry out) is not stored anywhere, and is lost.
81
82 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
83 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
84 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
85 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
86 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
87 and is lost.
88
89 If any of these macros are left undefined for a particular CPU,
90 C macros are used. */
91
92 /* The CPUs come in alphabetical order below.
93
94 Please add support for more CPUs here, or improve the current support
95 for the CPUs below!
96 (E.g. WE32100, IBM360.) */
97
98 #if defined (__GNUC__) && !defined (NO_ASM)
99
100 /* We sometimes need to clobber "cc" with gcc2, but that would not be
101 understood by gcc1. Use cpp to avoid major code duplication. */
102 #if __GNUC__ < 2
103 #define __CLOBBER_CC
104 #define __AND_CLOBBER_CC
105 #else /* __GNUC__ >= 2 */
106 #define __CLOBBER_CC : "cc"
107 #define __AND_CLOBBER_CC , "cc"
108 #endif /* __GNUC__ < 2 */
109
110 #if defined (__alpha) && W_TYPE_SIZE == 64
111 #define umul_ppmm(ph, pl, m0, m1) \
112 do { \
113 UDItype __m0 = (m0), __m1 = (m1); \
114 (ph) = __builtin_alpha_umulh (__m0, __m1); \
115 (pl) = __m0 * __m1; \
116 } while (0)
117 #define UMUL_TIME 46
118 #ifndef LONGLONG_STANDALONE
119 #define udiv_qrnnd(q, r, n1, n0, d) \
120 do { UDItype __r; \
121 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
122 (r) = __r; \
123 } while (0)
124 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
125 #define UDIV_TIME 220
126 #endif /* LONGLONG_STANDALONE */
127 #ifdef __alpha_cix__
128 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
129 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
130 #define COUNT_LEADING_ZEROS_0 64
131 #else
132 #define count_leading_zeros(COUNT,X) \
133 do { \
134 UDItype __xr = (X), __t, __a; \
135 __t = __builtin_alpha_cmpbge (0, __xr); \
136 __a = __clz_tab[__t ^ 0xff] - 1; \
137 __t = __builtin_alpha_extbl (__xr, __a); \
138 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
139 } while (0)
140 #define count_trailing_zeros(COUNT,X) \
141 do { \
142 UDItype __xr = (X), __t, __a; \
143 __t = __builtin_alpha_cmpbge (0, __xr); \
144 __t = ~__t & -~__t; \
145 __a = ((__t & 0xCC) != 0) * 2; \
146 __a += ((__t & 0xF0) != 0) * 4; \
147 __a += ((__t & 0xAA) != 0); \
148 __t = __builtin_alpha_extbl (__xr, __a); \
149 __a <<= 3; \
150 __t &= -__t; \
151 __a += ((__t & 0xCC) != 0) * 2; \
152 __a += ((__t & 0xF0) != 0) * 4; \
153 __a += ((__t & 0xAA) != 0); \
154 (COUNT) = __a; \
155 } while (0)
156 #endif /* __alpha_cix__ */
157 #endif /* __alpha */
158
159 #if defined (__arc__) && W_TYPE_SIZE == 32
160 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
161 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
162 : "=r" ((USItype) (sh)), \
163 "=&r" ((USItype) (sl)) \
164 : "%r" ((USItype) (ah)), \
165 "rIJ" ((USItype) (bh)), \
166 "%r" ((USItype) (al)), \
167 "rIJ" ((USItype) (bl)))
168 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
169 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
170 : "=r" ((USItype) (sh)), \
171 "=&r" ((USItype) (sl)) \
172 : "r" ((USItype) (ah)), \
173 "rIJ" ((USItype) (bh)), \
174 "r" ((USItype) (al)), \
175 "rIJ" ((USItype) (bl)))
176 /* Call libgcc routine. */
177 #define umul_ppmm(w1, w0, u, v) \
178 do { \
179 DWunion __w; \
180 __w.ll = __umulsidi3 (u, v); \
181 w1 = __w.s.high; \
182 w0 = __w.s.low; \
183 } while (0)
184 #define __umulsidi3 __umulsidi3
185 UDItype __umulsidi3 (USItype, USItype);
186 #endif
187
188 #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
189 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
190 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
191 : "=r" ((USItype) (sh)), \
192 "=&r" ((USItype) (sl)) \
193 : "%r" ((USItype) (ah)), \
194 "rI" ((USItype) (bh)), \
195 "%r" ((USItype) (al)), \
196 "rI" ((USItype) (bl)) __CLOBBER_CC)
197 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
198 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
199 : "=r" ((USItype) (sh)), \
200 "=&r" ((USItype) (sl)) \
201 : "r" ((USItype) (ah)), \
202 "rI" ((USItype) (bh)), \
203 "r" ((USItype) (al)), \
204 "rI" ((USItype) (bl)) __CLOBBER_CC)
205 #define umul_ppmm(xh, xl, a, b) \
206 {register USItype __t0, __t1, __t2; \
207 __asm__ ("%@ Inlined umul_ppmm\n" \
208 " mov %2, %5, lsr #16\n" \
209 " mov %0, %6, lsr #16\n" \
210 " bic %3, %5, %2, lsl #16\n" \
211 " bic %4, %6, %0, lsl #16\n" \
212 " mul %1, %3, %4\n" \
213 " mul %4, %2, %4\n" \
214 " mul %3, %0, %3\n" \
215 " mul %0, %2, %0\n" \
216 " adds %3, %4, %3\n" \
217 " addcs %0, %0, #65536\n" \
218 " adds %1, %1, %3, lsl #16\n" \
219 " adc %0, %0, %3, lsr #16" \
220 : "=&r" ((USItype) (xh)), \
221 "=r" ((USItype) (xl)), \
222 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
223 : "r" ((USItype) (a)), \
224 "r" ((USItype) (b)) __CLOBBER_CC );}
225 #define UMUL_TIME 20
226 #define UDIV_TIME 100
227 #endif /* __arm__ */
228
229 #if defined (__hppa) && W_TYPE_SIZE == 32
230 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
231 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
232 : "=r" ((USItype) (sh)), \
233 "=&r" ((USItype) (sl)) \
234 : "%rM" ((USItype) (ah)), \
235 "rM" ((USItype) (bh)), \
236 "%rM" ((USItype) (al)), \
237 "rM" ((USItype) (bl)))
238 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
239 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
240 : "=r" ((USItype) (sh)), \
241 "=&r" ((USItype) (sl)) \
242 : "rM" ((USItype) (ah)), \
243 "rM" ((USItype) (bh)), \
244 "rM" ((USItype) (al)), \
245 "rM" ((USItype) (bl)))
246 #if defined (_PA_RISC1_1)
247 #define umul_ppmm(w1, w0, u, v) \
248 do { \
249 union \
250 { \
251 UDItype __f; \
252 struct {USItype __w1, __w0;} __w1w0; \
253 } __t; \
254 __asm__ ("xmpyu %1,%2,%0" \
255 : "=x" (__t.__f) \
256 : "x" ((USItype) (u)), \
257 "x" ((USItype) (v))); \
258 (w1) = __t.__w1w0.__w1; \
259 (w0) = __t.__w1w0.__w0; \
260 } while (0)
261 #define UMUL_TIME 8
262 #else
263 #define UMUL_TIME 30
264 #endif
265 #define UDIV_TIME 40
266 #define count_leading_zeros(count, x) \
267 do { \
268 USItype __tmp; \
269 __asm__ ( \
270 "ldi 1,%0\n" \
271 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
272 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
273 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
274 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
275 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
276 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
277 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
278 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
279 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
280 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
281 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
282 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
283 " extru %1,30,1,%1 ; Extract bit 1.\n" \
284 " sub %0,%1,%0 ; Subtract it.\n" \
285 : "=r" (count), "=r" (__tmp) : "1" (x)); \
286 } while (0)
287 #endif
288
289 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
290 #define smul_ppmm(xh, xl, m0, m1) \
291 do { \
292 union {DItype __ll; \
293 struct {USItype __h, __l;} __i; \
294 } __x; \
295 __asm__ ("lr %N0,%1\n\tmr %0,%2" \
296 : "=&r" (__x.__ll) \
297 : "r" (m0), "r" (m1)); \
298 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
299 } while (0)
300 #define sdiv_qrnnd(q, r, n1, n0, d) \
301 do { \
302 union {DItype __ll; \
303 struct {USItype __h, __l;} __i; \
304 } __x; \
305 __x.__i.__h = n1; __x.__i.__l = n0; \
306 __asm__ ("dr %0,%2" \
307 : "=r" (__x.__ll) \
308 : "0" (__x.__ll), "r" (d)); \
309 (q) = __x.__i.__l; (r) = __x.__i.__h; \
310 } while (0)
311 #endif
312
313 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
314 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
315 __asm__ ("addl %5,%1\n\tadcl %3,%0" \
316 : "=r" ((USItype) (sh)), \
317 "=&r" ((USItype) (sl)) \
318 : "%0" ((USItype) (ah)), \
319 "g" ((USItype) (bh)), \
320 "%1" ((USItype) (al)), \
321 "g" ((USItype) (bl)))
322 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
323 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \
324 : "=r" ((USItype) (sh)), \
325 "=&r" ((USItype) (sl)) \
326 : "0" ((USItype) (ah)), \
327 "g" ((USItype) (bh)), \
328 "1" ((USItype) (al)), \
329 "g" ((USItype) (bl)))
330 #define umul_ppmm(w1, w0, u, v) \
331 __asm__ ("mull %3" \
332 : "=a" ((USItype) (w0)), \
333 "=d" ((USItype) (w1)) \
334 : "%0" ((USItype) (u)), \
335 "rm" ((USItype) (v)))
336 #define udiv_qrnnd(q, r, n1, n0, dv) \
337 __asm__ ("divl %4" \
338 : "=a" ((USItype) (q)), \
339 "=d" ((USItype) (r)) \
340 : "0" ((USItype) (n0)), \
341 "1" ((USItype) (n1)), \
342 "rm" ((USItype) (dv)))
343 #define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
344 #define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
345 #define UMUL_TIME 40
346 #define UDIV_TIME 40
347 #endif /* 80x86 */
348
349 #if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
350 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
351 __asm__ ("addq %5,%1\n\tadcq %3,%0" \
352 : "=r" ((UDItype) (sh)), \
353 "=&r" ((UDItype) (sl)) \
354 : "%0" ((UDItype) (ah)), \
355 "rme" ((UDItype) (bh)), \
356 "%1" ((UDItype) (al)), \
357 "rme" ((UDItype) (bl)))
358 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
359 __asm__ ("subq %5,%1\n\tsbbq %3,%0" \
360 : "=r" ((UDItype) (sh)), \
361 "=&r" ((UDItype) (sl)) \
362 : "0" ((UDItype) (ah)), \
363 "rme" ((UDItype) (bh)), \
364 "1" ((UDItype) (al)), \
365 "rme" ((UDItype) (bl)))
366 #define umul_ppmm(w1, w0, u, v) \
367 __asm__ ("mulq %3" \
368 : "=a" ((UDItype) (w0)), \
369 "=d" ((UDItype) (w1)) \
370 : "%0" ((UDItype) (u)), \
371 "rm" ((UDItype) (v)))
372 #define udiv_qrnnd(q, r, n1, n0, dv) \
373 __asm__ ("divq %4" \
374 : "=a" ((UDItype) (q)), \
375 "=d" ((UDItype) (r)) \
376 : "0" ((UDItype) (n0)), \
377 "1" ((UDItype) (n1)), \
378 "rm" ((UDItype) (dv)))
379 #define count_leading_zeros(count, x) ((count) = __builtin_clzl (x))
380 #define count_trailing_zeros(count, x) ((count) = __builtin_ctzl (x))
381 #define UMUL_TIME 40
382 #define UDIV_TIME 40
383 #endif /* x86_64 */
384
385 #if defined (__i960__) && W_TYPE_SIZE == 32
386 #define umul_ppmm(w1, w0, u, v) \
387 ({union {UDItype __ll; \
388 struct {USItype __l, __h;} __i; \
389 } __xx; \
390 __asm__ ("emul %2,%1,%0" \
391 : "=d" (__xx.__ll) \
392 : "%dI" ((USItype) (u)), \
393 "dI" ((USItype) (v))); \
394 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
395 #define __umulsidi3(u, v) \
396 ({UDItype __w; \
397 __asm__ ("emul %2,%1,%0" \
398 : "=d" (__w) \
399 : "%dI" ((USItype) (u)), \
400 "dI" ((USItype) (v))); \
401 __w; })
402 #endif /* __i960__ */
403
404 #if defined (__M32R__) && W_TYPE_SIZE == 32
405 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
406 /* The cmp clears the condition bit. */ \
407 __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
408 : "=r" ((USItype) (sh)), \
409 "=&r" ((USItype) (sl)) \
410 : "0" ((USItype) (ah)), \
411 "r" ((USItype) (bh)), \
412 "1" ((USItype) (al)), \
413 "r" ((USItype) (bl)) \
414 : "cbit")
415 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
416 /* The cmp clears the condition bit. */ \
417 __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
418 : "=r" ((USItype) (sh)), \
419 "=&r" ((USItype) (sl)) \
420 : "0" ((USItype) (ah)), \
421 "r" ((USItype) (bh)), \
422 "1" ((USItype) (al)), \
423 "r" ((USItype) (bl)) \
424 : "cbit")
425 #endif /* __M32R__ */
426
427 #if defined (__mc68000__) && W_TYPE_SIZE == 32
428 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
429 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
430 : "=d" ((USItype) (sh)), \
431 "=&d" ((USItype) (sl)) \
432 : "%0" ((USItype) (ah)), \
433 "d" ((USItype) (bh)), \
434 "%1" ((USItype) (al)), \
435 "g" ((USItype) (bl)))
436 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
437 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
438 : "=d" ((USItype) (sh)), \
439 "=&d" ((USItype) (sl)) \
440 : "0" ((USItype) (ah)), \
441 "d" ((USItype) (bh)), \
442 "1" ((USItype) (al)), \
443 "g" ((USItype) (bl)))
444
445 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
446 #if (defined (__mc68020__) && !defined (__mc68060__))
447 #define umul_ppmm(w1, w0, u, v) \
448 __asm__ ("mulu%.l %3,%1:%0" \
449 : "=d" ((USItype) (w0)), \
450 "=d" ((USItype) (w1)) \
451 : "%0" ((USItype) (u)), \
452 "dmi" ((USItype) (v)))
453 #define UMUL_TIME 45
454 #define udiv_qrnnd(q, r, n1, n0, d) \
455 __asm__ ("divu%.l %4,%1:%0" \
456 : "=d" ((USItype) (q)), \
457 "=d" ((USItype) (r)) \
458 : "0" ((USItype) (n0)), \
459 "1" ((USItype) (n1)), \
460 "dmi" ((USItype) (d)))
461 #define UDIV_TIME 90
462 #define sdiv_qrnnd(q, r, n1, n0, d) \
463 __asm__ ("divs%.l %4,%1:%0" \
464 : "=d" ((USItype) (q)), \
465 "=d" ((USItype) (r)) \
466 : "0" ((USItype) (n0)), \
467 "1" ((USItype) (n1)), \
468 "dmi" ((USItype) (d)))
469
470 #elif defined (__mcoldfire__) /* not mc68020 */
471
472 #define umul_ppmm(xh, xl, a, b) \
473 __asm__ ("| Inlined umul_ppmm\n" \
474 " move%.l %2,%/d0\n" \
475 " move%.l %3,%/d1\n" \
476 " move%.l %/d0,%/d2\n" \
477 " swap %/d0\n" \
478 " move%.l %/d1,%/d3\n" \
479 " swap %/d1\n" \
480 " move%.w %/d2,%/d4\n" \
481 " mulu %/d3,%/d4\n" \
482 " mulu %/d1,%/d2\n" \
483 " mulu %/d0,%/d3\n" \
484 " mulu %/d0,%/d1\n" \
485 " move%.l %/d4,%/d0\n" \
486 " clr%.w %/d0\n" \
487 " swap %/d0\n" \
488 " add%.l %/d0,%/d2\n" \
489 " add%.l %/d3,%/d2\n" \
490 " jcc 1f\n" \
491 " add%.l %#65536,%/d1\n" \
492 "1: swap %/d2\n" \
493 " moveq %#0,%/d0\n" \
494 " move%.w %/d2,%/d0\n" \
495 " move%.w %/d4,%/d2\n" \
496 " move%.l %/d2,%1\n" \
497 " add%.l %/d1,%/d0\n" \
498 " move%.l %/d0,%0" \
499 : "=g" ((USItype) (xh)), \
500 "=g" ((USItype) (xl)) \
501 : "g" ((USItype) (a)), \
502 "g" ((USItype) (b)) \
503 : "d0", "d1", "d2", "d3", "d4")
504 #define UMUL_TIME 100
505 #define UDIV_TIME 400
506 #else /* not ColdFire */
507 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
508 #define umul_ppmm(xh, xl, a, b) \
509 __asm__ ("| Inlined umul_ppmm\n" \
510 " move%.l %2,%/d0\n" \
511 " move%.l %3,%/d1\n" \
512 " move%.l %/d0,%/d2\n" \
513 " swap %/d0\n" \
514 " move%.l %/d1,%/d3\n" \
515 " swap %/d1\n" \
516 " move%.w %/d2,%/d4\n" \
517 " mulu %/d3,%/d4\n" \
518 " mulu %/d1,%/d2\n" \
519 " mulu %/d0,%/d3\n" \
520 " mulu %/d0,%/d1\n" \
521 " move%.l %/d4,%/d0\n" \
522 " eor%.w %/d0,%/d0\n" \
523 " swap %/d0\n" \
524 " add%.l %/d0,%/d2\n" \
525 " add%.l %/d3,%/d2\n" \
526 " jcc 1f\n" \
527 " add%.l %#65536,%/d1\n" \
528 "1: swap %/d2\n" \
529 " moveq %#0,%/d0\n" \
530 " move%.w %/d2,%/d0\n" \
531 " move%.w %/d4,%/d2\n" \
532 " move%.l %/d2,%1\n" \
533 " add%.l %/d1,%/d0\n" \
534 " move%.l %/d0,%0" \
535 : "=g" ((USItype) (xh)), \
536 "=g" ((USItype) (xl)) \
537 : "g" ((USItype) (a)), \
538 "g" ((USItype) (b)) \
539 : "d0", "d1", "d2", "d3", "d4")
540 #define UMUL_TIME 100
541 #define UDIV_TIME 400
542
543 #endif /* not mc68020 */
544
545 /* The '020, '030, '040 and '060 have bitfield insns.
546 cpu32 disguises as a 68020, but lacks them. */
547 #if defined (__mc68020__) && !defined (__mcpu32__)
548 #define count_leading_zeros(count, x) \
549 __asm__ ("bfffo %1{%b2:%b2},%0" \
550 : "=d" ((USItype) (count)) \
551 : "od" ((USItype) (x)), "n" (0))
552 /* Some ColdFire architectures have a ff1 instruction supported via
553 __builtin_clz. */
554 #elif defined (__mcfisaaplus__) || defined (__mcfisac__)
555 #define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
556 #define COUNT_LEADING_ZEROS_0 32
557 #endif
558 #endif /* mc68000 */
559
560 #if defined (__m88000__) && W_TYPE_SIZE == 32
561 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
562 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
563 : "=r" ((USItype) (sh)), \
564 "=&r" ((USItype) (sl)) \
565 : "%rJ" ((USItype) (ah)), \
566 "rJ" ((USItype) (bh)), \
567 "%rJ" ((USItype) (al)), \
568 "rJ" ((USItype) (bl)))
569 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
570 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
571 : "=r" ((USItype) (sh)), \
572 "=&r" ((USItype) (sl)) \
573 : "rJ" ((USItype) (ah)), \
574 "rJ" ((USItype) (bh)), \
575 "rJ" ((USItype) (al)), \
576 "rJ" ((USItype) (bl)))
577 #define count_leading_zeros(count, x) \
578 do { \
579 USItype __cbtmp; \
580 __asm__ ("ff1 %0,%1" \
581 : "=r" (__cbtmp) \
582 : "r" ((USItype) (x))); \
583 (count) = __cbtmp ^ 31; \
584 } while (0)
585 #define COUNT_LEADING_ZEROS_0 63 /* sic */
586 #if defined (__mc88110__)
587 #define umul_ppmm(wh, wl, u, v) \
588 do { \
589 union {UDItype __ll; \
590 struct {USItype __h, __l;} __i; \
591 } __xx; \
592 __asm__ ("mulu.d %0,%1,%2" \
593 : "=r" (__xx.__ll) \
594 : "r" ((USItype) (u)), \
595 "r" ((USItype) (v))); \
596 (wh) = __xx.__i.__h; \
597 (wl) = __xx.__i.__l; \
598 } while (0)
599 #define udiv_qrnnd(q, r, n1, n0, d) \
600 ({union {UDItype __ll; \
601 struct {USItype __h, __l;} __i; \
602 } __xx; \
603 USItype __q; \
604 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
605 __asm__ ("divu.d %0,%1,%2" \
606 : "=r" (__q) \
607 : "r" (__xx.__ll), \
608 "r" ((USItype) (d))); \
609 (r) = (n0) - __q * (d); (q) = __q; })
610 #define UMUL_TIME 5
611 #define UDIV_TIME 25
612 #else
613 #define UMUL_TIME 17
614 #define UDIV_TIME 150
615 #endif /* __mc88110__ */
616 #endif /* __m88000__ */
617
618 #if defined (__mips__) && W_TYPE_SIZE == 32
619 #define umul_ppmm(w1, w0, u, v) \
620 __asm__ ("multu %2,%3" \
621 : "=l" ((USItype) (w0)), \
622 "=h" ((USItype) (w1)) \
623 : "d" ((USItype) (u)), \
624 "d" ((USItype) (v)))
625 #define UMUL_TIME 10
626 #define UDIV_TIME 100
627
628 #if (__mips == 32 || __mips == 64) && ! __mips16
629 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
630 #define COUNT_LEADING_ZEROS_0 32
631 #endif
632 #endif /* __mips__ */
633
634 #if defined (__ns32000__) && W_TYPE_SIZE == 32
635 #define umul_ppmm(w1, w0, u, v) \
636 ({union {UDItype __ll; \
637 struct {USItype __l, __h;} __i; \
638 } __xx; \
639 __asm__ ("meid %2,%0" \
640 : "=g" (__xx.__ll) \
641 : "%0" ((USItype) (u)), \
642 "g" ((USItype) (v))); \
643 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
644 #define __umulsidi3(u, v) \
645 ({UDItype __w; \
646 __asm__ ("meid %2,%0" \
647 : "=g" (__w) \
648 : "%0" ((USItype) (u)), \
649 "g" ((USItype) (v))); \
650 __w; })
651 #define udiv_qrnnd(q, r, n1, n0, d) \
652 ({union {UDItype __ll; \
653 struct {USItype __l, __h;} __i; \
654 } __xx; \
655 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
656 __asm__ ("deid %2,%0" \
657 : "=g" (__xx.__ll) \
658 : "0" (__xx.__ll), \
659 "g" ((USItype) (d))); \
660 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
661 #define count_trailing_zeros(count,x) \
662 do { \
663 __asm__ ("ffsd %2,%0" \
664 : "=r" ((USItype) (count)) \
665 : "0" ((USItype) 0), \
666 "r" ((USItype) (x))); \
667 } while (0)
668 #endif /* __ns32000__ */
669
670 /* FIXME: We should test _IBMR2 here when we add assembly support for the
671 system vendor compilers.
672 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
673 enough, since that hits ARM and m68k too. */
674 #if (defined (_ARCH_PPC) /* AIX */ \
675 || defined (_ARCH_PWR) /* AIX */ \
676 || defined (_ARCH_COM) /* AIX */ \
677 || defined (__powerpc__) /* gcc */ \
678 || defined (__POWERPC__) /* BEOS */ \
679 || defined (__ppc__) /* Darwin */ \
680 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
681 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
682 && CPU_FAMILY == PPC) \
683 ) && W_TYPE_SIZE == 32
684 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
685 do { \
686 if (__builtin_constant_p (bh) && (bh) == 0) \
687 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
688 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
689 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
690 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
691 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
692 else \
693 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
694 : "=r" (sh), "=&r" (sl) \
695 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
696 } while (0)
697 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
698 do { \
699 if (__builtin_constant_p (ah) && (ah) == 0) \
700 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
701 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
702 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
703 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
704 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
705 else if (__builtin_constant_p (bh) && (bh) == 0) \
706 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
707 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
708 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
709 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
710 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
711 else \
712 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
713 : "=r" (sh), "=&r" (sl) \
714 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
715 } while (0)
716 #define count_leading_zeros(count, x) \
717 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
718 #define COUNT_LEADING_ZEROS_0 32
719 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
720 || defined (__ppc__) \
721 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
722 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
723 && CPU_FAMILY == PPC)
724 #define umul_ppmm(ph, pl, m0, m1) \
725 do { \
726 USItype __m0 = (m0), __m1 = (m1); \
727 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
728 (pl) = __m0 * __m1; \
729 } while (0)
730 #define UMUL_TIME 15
731 #define smul_ppmm(ph, pl, m0, m1) \
732 do { \
733 SItype __m0 = (m0), __m1 = (m1); \
734 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
735 (pl) = __m0 * __m1; \
736 } while (0)
737 #define SMUL_TIME 14
738 #define UDIV_TIME 120
739 #elif defined (_ARCH_PWR)
740 #define UMUL_TIME 8
741 #define smul_ppmm(xh, xl, m0, m1) \
742 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
743 #define SMUL_TIME 4
744 #define sdiv_qrnnd(q, r, nh, nl, d) \
745 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
746 #define UDIV_TIME 100
747 #endif
748 #endif /* 32-bit POWER architecture variants. */
749
750 /* We should test _IBMR2 here when we add assembly support for the system
751 vendor compilers. */
752 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
753 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
754 do { \
755 if (__builtin_constant_p (bh) && (bh) == 0) \
756 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
757 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
758 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
759 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
760 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
761 else \
762 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
763 : "=r" (sh), "=&r" (sl) \
764 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
765 } while (0)
766 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
767 do { \
768 if (__builtin_constant_p (ah) && (ah) == 0) \
769 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
770 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
771 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
772 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
773 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
774 else if (__builtin_constant_p (bh) && (bh) == 0) \
775 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
776 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
777 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
778 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
779 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
780 else \
781 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
782 : "=r" (sh), "=&r" (sl) \
783 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
784 } while (0)
785 #define count_leading_zeros(count, x) \
786 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
787 #define COUNT_LEADING_ZEROS_0 64
788 #define umul_ppmm(ph, pl, m0, m1) \
789 do { \
790 UDItype __m0 = (m0), __m1 = (m1); \
791 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
792 (pl) = __m0 * __m1; \
793 } while (0)
794 #define UMUL_TIME 15
795 #define smul_ppmm(ph, pl, m0, m1) \
796 do { \
797 DItype __m0 = (m0), __m1 = (m1); \
798 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
799 (pl) = __m0 * __m1; \
800 } while (0)
801 #define SMUL_TIME 14 /* ??? */
802 #define UDIV_TIME 120 /* ??? */
803 #endif /* 64-bit PowerPC. */
804
805 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
806 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
807 __asm__ ("a %1,%5\n\tae %0,%3" \
808 : "=r" ((USItype) (sh)), \
809 "=&r" ((USItype) (sl)) \
810 : "%0" ((USItype) (ah)), \
811 "r" ((USItype) (bh)), \
812 "%1" ((USItype) (al)), \
813 "r" ((USItype) (bl)))
814 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
815 __asm__ ("s %1,%5\n\tse %0,%3" \
816 : "=r" ((USItype) (sh)), \
817 "=&r" ((USItype) (sl)) \
818 : "0" ((USItype) (ah)), \
819 "r" ((USItype) (bh)), \
820 "1" ((USItype) (al)), \
821 "r" ((USItype) (bl)))
822 #define umul_ppmm(ph, pl, m0, m1) \
823 do { \
824 USItype __m0 = (m0), __m1 = (m1); \
825 __asm__ ( \
826 "s r2,r2\n" \
827 " mts r10,%2\n" \
828 " m r2,%3\n" \
829 " m r2,%3\n" \
830 " m r2,%3\n" \
831 " m r2,%3\n" \
832 " m r2,%3\n" \
833 " m r2,%3\n" \
834 " m r2,%3\n" \
835 " m r2,%3\n" \
836 " m r2,%3\n" \
837 " m r2,%3\n" \
838 " m r2,%3\n" \
839 " m r2,%3\n" \
840 " m r2,%3\n" \
841 " m r2,%3\n" \
842 " m r2,%3\n" \
843 " m r2,%3\n" \
844 " cas %0,r2,r0\n" \
845 " mfs r10,%1" \
846 : "=r" ((USItype) (ph)), \
847 "=r" ((USItype) (pl)) \
848 : "%r" (__m0), \
849 "r" (__m1) \
850 : "r2"); \
851 (ph) += ((((SItype) __m0 >> 31) & __m1) \
852 + (((SItype) __m1 >> 31) & __m0)); \
853 } while (0)
854 #define UMUL_TIME 20
855 #define UDIV_TIME 200
856 #define count_leading_zeros(count, x) \
857 do { \
858 if ((x) >= 0x10000) \
859 __asm__ ("clz %0,%1" \
860 : "=r" ((USItype) (count)) \
861 : "r" ((USItype) (x) >> 16)); \
862 else \
863 { \
864 __asm__ ("clz %0,%1" \
865 : "=r" ((USItype) (count)) \
866 : "r" ((USItype) (x))); \
867 (count) += 16; \
868 } \
869 } while (0)
870 #endif
871
872 #if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
873 #ifndef __sh1__
874 #define umul_ppmm(w1, w0, u, v) \
875 __asm__ ( \
876 "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
877 : "=r<" ((USItype)(w1)), \
878 "=r<" ((USItype)(w0)) \
879 : "r" ((USItype)(u)), \
880 "r" ((USItype)(v)) \
881 : "macl", "mach")
882 #define UMUL_TIME 5
883 #endif
884
885 /* This is the same algorithm as __udiv_qrnnd_c. */
886 #define UDIV_NEEDS_NORMALIZATION 1
887
888 #define udiv_qrnnd(q, r, n1, n0, d) \
889 do { \
890 extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
891 __attribute__ ((visibility ("hidden"))); \
892 /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
893 __asm__ ( \
894 "mov%M4 %4,r5\n" \
895 " swap.w %3,r4\n" \
896 " swap.w r5,r6\n" \
897 " jsr @%5\n" \
898 " shll16 r6\n" \
899 " swap.w r4,r4\n" \
900 " jsr @%5\n" \
901 " swap.w r1,%0\n" \
902 " or r1,%0" \
903 : "=r" (q), "=&z" (r) \
904 : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
905 : "r1", "r2", "r4", "r5", "r6", "pr"); \
906 } while (0)
907
908 #define UDIV_TIME 80
909
910 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
911 __asm__ ("clrt;subc %5,%1; subc %4,%0" \
912 : "=r" (sh), "=r" (sl) \
913 : "0" (ah), "1" (al), "r" (bh), "r" (bl))
914
915 #endif /* __sh__ */
916
917 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
918 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
919 #define count_leading_zeros(count, x) \
920 do \
921 { \
922 UDItype x_ = (USItype)(x); \
923 SItype c_; \
924 \
925 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
926 (count) = c_ - 31; \
927 } \
928 while (0)
929 #define COUNT_LEADING_ZEROS_0 32
930 #endif
931
932 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
933 && W_TYPE_SIZE == 32
934 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
935 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
936 : "=r" ((USItype) (sh)), \
937 "=&r" ((USItype) (sl)) \
938 : "%rJ" ((USItype) (ah)), \
939 "rI" ((USItype) (bh)), \
940 "%rJ" ((USItype) (al)), \
941 "rI" ((USItype) (bl)) \
942 __CLOBBER_CC)
943 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
944 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
945 : "=r" ((USItype) (sh)), \
946 "=&r" ((USItype) (sl)) \
947 : "rJ" ((USItype) (ah)), \
948 "rI" ((USItype) (bh)), \
949 "rJ" ((USItype) (al)), \
950 "rI" ((USItype) (bl)) \
951 __CLOBBER_CC)
952 #if defined (__sparc_v8__)
953 #define umul_ppmm(w1, w0, u, v) \
954 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
955 : "=r" ((USItype) (w1)), \
956 "=r" ((USItype) (w0)) \
957 : "r" ((USItype) (u)), \
958 "r" ((USItype) (v)))
959 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
960 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
961 : "=&r" ((USItype) (__q)), \
962 "=&r" ((USItype) (__r)) \
963 : "r" ((USItype) (__n1)), \
964 "r" ((USItype) (__n0)), \
965 "r" ((USItype) (__d)))
966 #else
967 #if defined (__sparclite__)
968 /* This has hardware multiply but not divide. It also has two additional
969 instructions scan (ffs from high bit) and divscc. */
970 #define umul_ppmm(w1, w0, u, v) \
971 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
972 : "=r" ((USItype) (w1)), \
973 "=r" ((USItype) (w0)) \
974 : "r" ((USItype) (u)), \
975 "r" ((USItype) (v)))
976 #define udiv_qrnnd(q, r, n1, n0, d) \
977 __asm__ ("! Inlined udiv_qrnnd\n" \
978 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
979 " tst %%g0\n" \
980 " divscc %3,%4,%%g1\n" \
981 " divscc %%g1,%4,%%g1\n" \
982 " divscc %%g1,%4,%%g1\n" \
983 " divscc %%g1,%4,%%g1\n" \
984 " divscc %%g1,%4,%%g1\n" \
985 " divscc %%g1,%4,%%g1\n" \
986 " divscc %%g1,%4,%%g1\n" \
987 " divscc %%g1,%4,%%g1\n" \
988 " divscc %%g1,%4,%%g1\n" \
989 " divscc %%g1,%4,%%g1\n" \
990 " divscc %%g1,%4,%%g1\n" \
991 " divscc %%g1,%4,%%g1\n" \
992 " divscc %%g1,%4,%%g1\n" \
993 " divscc %%g1,%4,%%g1\n" \
994 " divscc %%g1,%4,%%g1\n" \
995 " divscc %%g1,%4,%%g1\n" \
996 " divscc %%g1,%4,%%g1\n" \
997 " divscc %%g1,%4,%%g1\n" \
998 " divscc %%g1,%4,%%g1\n" \
999 " divscc %%g1,%4,%%g1\n" \
1000 " divscc %%g1,%4,%%g1\n" \
1001 " divscc %%g1,%4,%%g1\n" \
1002 " divscc %%g1,%4,%%g1\n" \
1003 " divscc %%g1,%4,%%g1\n" \
1004 " divscc %%g1,%4,%%g1\n" \
1005 " divscc %%g1,%4,%%g1\n" \
1006 " divscc %%g1,%4,%%g1\n" \
1007 " divscc %%g1,%4,%%g1\n" \
1008 " divscc %%g1,%4,%%g1\n" \
1009 " divscc %%g1,%4,%%g1\n" \
1010 " divscc %%g1,%4,%%g1\n" \
1011 " divscc %%g1,%4,%0\n" \
1012 " rd %%y,%1\n" \
1013 " bl,a 1f\n" \
1014 " add %1,%4,%1\n" \
1015 "1: ! End of inline udiv_qrnnd" \
1016 : "=r" ((USItype) (q)), \
1017 "=r" ((USItype) (r)) \
1018 : "r" ((USItype) (n1)), \
1019 "r" ((USItype) (n0)), \
1020 "rI" ((USItype) (d)) \
1021 : "g1" __AND_CLOBBER_CC)
1022 #define UDIV_TIME 37
1023 #define count_leading_zeros(count, x) \
1024 do { \
1025 __asm__ ("scan %1,1,%0" \
1026 : "=r" ((USItype) (count)) \
1027 : "r" ((USItype) (x))); \
1028 } while (0)
1029 /* Early sparclites return 63 for an argument of 0, but they warn that future
1030 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
1031 undefined. */
1032 #else
1033 /* SPARC without integer multiplication and divide instructions.
1034 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
1035 #define umul_ppmm(w1, w0, u, v) \
1036 __asm__ ("! Inlined umul_ppmm\n" \
1037 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
1038 " sra %3,31,%%o5 ! Don't move this insn\n" \
1039 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
1040 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
1041 " mulscc %%g1,%3,%%g1\n" \
1042 " mulscc %%g1,%3,%%g1\n" \
1043 " mulscc %%g1,%3,%%g1\n" \
1044 " mulscc %%g1,%3,%%g1\n" \
1045 " mulscc %%g1,%3,%%g1\n" \
1046 " mulscc %%g1,%3,%%g1\n" \
1047 " mulscc %%g1,%3,%%g1\n" \
1048 " mulscc %%g1,%3,%%g1\n" \
1049 " mulscc %%g1,%3,%%g1\n" \
1050 " mulscc %%g1,%3,%%g1\n" \
1051 " mulscc %%g1,%3,%%g1\n" \
1052 " mulscc %%g1,%3,%%g1\n" \
1053 " mulscc %%g1,%3,%%g1\n" \
1054 " mulscc %%g1,%3,%%g1\n" \
1055 " mulscc %%g1,%3,%%g1\n" \
1056 " mulscc %%g1,%3,%%g1\n" \
1057 " mulscc %%g1,%3,%%g1\n" \
1058 " mulscc %%g1,%3,%%g1\n" \
1059 " mulscc %%g1,%3,%%g1\n" \
1060 " mulscc %%g1,%3,%%g1\n" \
1061 " mulscc %%g1,%3,%%g1\n" \
1062 " mulscc %%g1,%3,%%g1\n" \
1063 " mulscc %%g1,%3,%%g1\n" \
1064 " mulscc %%g1,%3,%%g1\n" \
1065 " mulscc %%g1,%3,%%g1\n" \
1066 " mulscc %%g1,%3,%%g1\n" \
1067 " mulscc %%g1,%3,%%g1\n" \
1068 " mulscc %%g1,%3,%%g1\n" \
1069 " mulscc %%g1,%3,%%g1\n" \
1070 " mulscc %%g1,%3,%%g1\n" \
1071 " mulscc %%g1,%3,%%g1\n" \
1072 " mulscc %%g1,%3,%%g1\n" \
1073 " mulscc %%g1,0,%%g1\n" \
1074 " add %%g1,%%o5,%0\n" \
1075 " rd %%y,%1" \
1076 : "=r" ((USItype) (w1)), \
1077 "=r" ((USItype) (w0)) \
1078 : "%rI" ((USItype) (u)), \
1079 "r" ((USItype) (v)) \
1080 : "g1", "o5" __AND_CLOBBER_CC)
1081 #define UMUL_TIME 39 /* 39 instructions */
1082 /* It's quite necessary to add this much assembler for the sparc.
1083 The default udiv_qrnnd (in C) is more than 10 times slower! */
1084 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1085 __asm__ ("! Inlined udiv_qrnnd\n" \
1086 " mov 32,%%g1\n" \
1087 " subcc %1,%2,%%g0\n" \
1088 "1: bcs 5f\n" \
1089 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1090 " sub %1,%2,%1 ! this kills msb of n\n" \
1091 " addx %1,%1,%1 ! so this can't give carry\n" \
1092 " subcc %%g1,1,%%g1\n" \
1093 "2: bne 1b\n" \
1094 " subcc %1,%2,%%g0\n" \
1095 " bcs 3f\n" \
1096 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1097 " b 3f\n" \
1098 " sub %1,%2,%1 ! this kills msb of n\n" \
1099 "4: sub %1,%2,%1\n" \
1100 "5: addxcc %1,%1,%1\n" \
1101 " bcc 2b\n" \
1102 " subcc %%g1,1,%%g1\n" \
1103 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1104 " bne 4b\n" \
1105 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1106 " sub %1,%2,%1\n" \
1107 "3: xnor %0,0,%0\n" \
1108 " ! End of inline udiv_qrnnd" \
1109 : "=&r" ((USItype) (__q)), \
1110 "=&r" ((USItype) (__r)) \
1111 : "r" ((USItype) (__d)), \
1112 "1" ((USItype) (__n1)), \
1113 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1114 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1115 #endif /* __sparclite__ */
1116 #endif /* __sparc_v8__ */
1117 #endif /* sparc32 */
1118
1119 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1120 && W_TYPE_SIZE == 64
1121 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1122 __asm__ ("addcc %r4,%5,%1\n\t" \
1123 "add %r2,%3,%0\n\t" \
1124 "bcs,a,pn %%xcc, 1f\n\t" \
1125 "add %0, 1, %0\n" \
1126 "1:" \
1127 : "=r" ((UDItype)(sh)), \
1128 "=&r" ((UDItype)(sl)) \
1129 : "%rJ" ((UDItype)(ah)), \
1130 "rI" ((UDItype)(bh)), \
1131 "%rJ" ((UDItype)(al)), \
1132 "rI" ((UDItype)(bl)) \
1133 __CLOBBER_CC)
1134
1135 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1136 __asm__ ("subcc %r4,%5,%1\n\t" \
1137 "sub %r2,%3,%0\n\t" \
1138 "bcs,a,pn %%xcc, 1f\n\t" \
1139 "sub %0, 1, %0\n\t" \
1140 "1:" \
1141 : "=r" ((UDItype)(sh)), \
1142 "=&r" ((UDItype)(sl)) \
1143 : "rJ" ((UDItype)(ah)), \
1144 "rI" ((UDItype)(bh)), \
1145 "rJ" ((UDItype)(al)), \
1146 "rI" ((UDItype)(bl)) \
1147 __CLOBBER_CC)
1148
1149 #define umul_ppmm(wh, wl, u, v) \
1150 do { \
1151 UDItype tmp1, tmp2, tmp3, tmp4; \
1152 __asm__ __volatile__ ( \
1153 "srl %7,0,%3\n\t" \
1154 "mulx %3,%6,%1\n\t" \
1155 "srlx %6,32,%2\n\t" \
1156 "mulx %2,%3,%4\n\t" \
1157 "sllx %4,32,%5\n\t" \
1158 "srl %6,0,%3\n\t" \
1159 "sub %1,%5,%5\n\t" \
1160 "srlx %5,32,%5\n\t" \
1161 "addcc %4,%5,%4\n\t" \
1162 "srlx %7,32,%5\n\t" \
1163 "mulx %3,%5,%3\n\t" \
1164 "mulx %2,%5,%5\n\t" \
1165 "sethi %%hi(0x80000000),%2\n\t" \
1166 "addcc %4,%3,%4\n\t" \
1167 "srlx %4,32,%4\n\t" \
1168 "add %2,%2,%2\n\t" \
1169 "movcc %%xcc,%%g0,%2\n\t" \
1170 "addcc %5,%4,%5\n\t" \
1171 "sllx %3,32,%3\n\t" \
1172 "add %1,%3,%1\n\t" \
1173 "add %5,%2,%0" \
1174 : "=r" ((UDItype)(wh)), \
1175 "=&r" ((UDItype)(wl)), \
1176 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1177 : "r" ((UDItype)(u)), \
1178 "r" ((UDItype)(v)) \
1179 __CLOBBER_CC); \
1180 } while (0)
1181 #define UMUL_TIME 96
1182 #define UDIV_TIME 230
1183 #endif /* sparc64 */
1184
1185 #if defined (__vax__) && W_TYPE_SIZE == 32
1186 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1187 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1188 : "=g" ((USItype) (sh)), \
1189 "=&g" ((USItype) (sl)) \
1190 : "%0" ((USItype) (ah)), \
1191 "g" ((USItype) (bh)), \
1192 "%1" ((USItype) (al)), \
1193 "g" ((USItype) (bl)))
1194 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1195 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1196 : "=g" ((USItype) (sh)), \
1197 "=&g" ((USItype) (sl)) \
1198 : "0" ((USItype) (ah)), \
1199 "g" ((USItype) (bh)), \
1200 "1" ((USItype) (al)), \
1201 "g" ((USItype) (bl)))
1202 #define umul_ppmm(xh, xl, m0, m1) \
1203 do { \
1204 union { \
1205 UDItype __ll; \
1206 struct {USItype __l, __h;} __i; \
1207 } __xx; \
1208 USItype __m0 = (m0), __m1 = (m1); \
1209 __asm__ ("emul %1,%2,$0,%0" \
1210 : "=r" (__xx.__ll) \
1211 : "g" (__m0), \
1212 "g" (__m1)); \
1213 (xh) = __xx.__i.__h; \
1214 (xl) = __xx.__i.__l; \
1215 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1216 + (((SItype) __m1 >> 31) & __m0)); \
1217 } while (0)
1218 #define sdiv_qrnnd(q, r, n1, n0, d) \
1219 do { \
1220 union {DItype __ll; \
1221 struct {SItype __l, __h;} __i; \
1222 } __xx; \
1223 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1224 __asm__ ("ediv %3,%2,%0,%1" \
1225 : "=g" (q), "=g" (r) \
1226 : "g" (__xx.__ll), "g" (d)); \
1227 } while (0)
1228 #endif /* __vax__ */
1229
1230 #if defined (__xtensa__) && W_TYPE_SIZE == 32
1231 /* This code is not Xtensa-configuration-specific, so rely on the compiler
1232 to expand builtin functions depending on what configuration features
1233 are available. This avoids library calls when the operation can be
1234 performed in-line. */
1235 #define umul_ppmm(w1, w0, u, v) \
1236 do { \
1237 DWunion __w; \
1238 __w.ll = __builtin_umulsidi3 (u, v); \
1239 w1 = __w.s.high; \
1240 w0 = __w.s.low; \
1241 } while (0)
1242 #define __umulsidi3(u, v) __builtin_umulsidi3 (u, v)
1243 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
1244 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
1245 #endif /* __xtensa__ */
1246
1247 #if defined (__z8000__) && W_TYPE_SIZE == 16
1248 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1249 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1250 : "=r" ((unsigned int)(sh)), \
1251 "=&r" ((unsigned int)(sl)) \
1252 : "%0" ((unsigned int)(ah)), \
1253 "r" ((unsigned int)(bh)), \
1254 "%1" ((unsigned int)(al)), \
1255 "rQR" ((unsigned int)(bl)))
1256 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1257 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1258 : "=r" ((unsigned int)(sh)), \
1259 "=&r" ((unsigned int)(sl)) \
1260 : "0" ((unsigned int)(ah)), \
1261 "r" ((unsigned int)(bh)), \
1262 "1" ((unsigned int)(al)), \
1263 "rQR" ((unsigned int)(bl)))
1264 #define umul_ppmm(xh, xl, m0, m1) \
1265 do { \
1266 union {long int __ll; \
1267 struct {unsigned int __h, __l;} __i; \
1268 } __xx; \
1269 unsigned int __m0 = (m0), __m1 = (m1); \
1270 __asm__ ("mult %S0,%H3" \
1271 : "=r" (__xx.__i.__h), \
1272 "=r" (__xx.__i.__l) \
1273 : "%1" (__m0), \
1274 "rQR" (__m1)); \
1275 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1276 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1277 + (((signed int) __m1 >> 15) & __m0)); \
1278 } while (0)
1279 #endif /* __z8000__ */
1280
1281 #endif /* __GNUC__ */
1282
1283 /* If this machine has no inline assembler, use C macros. */
1284
1285 #if !defined (add_ssaaaa)
1286 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1287 do { \
1288 UWtype __x; \
1289 __x = (al) + (bl); \
1290 (sh) = (ah) + (bh) + (__x < (al)); \
1291 (sl) = __x; \
1292 } while (0)
1293 #endif
1294
1295 #if !defined (sub_ddmmss)
1296 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1297 do { \
1298 UWtype __x; \
1299 __x = (al) - (bl); \
1300 (sh) = (ah) - (bh) - (__x > (al)); \
1301 (sl) = __x; \
1302 } while (0)
1303 #endif
1304
1305 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1306 smul_ppmm. */
1307 #if !defined (umul_ppmm) && defined (smul_ppmm)
1308 #define umul_ppmm(w1, w0, u, v) \
1309 do { \
1310 UWtype __w1; \
1311 UWtype __xm0 = (u), __xm1 = (v); \
1312 smul_ppmm (__w1, w0, __xm0, __xm1); \
1313 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1314 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1315 } while (0)
1316 #endif
1317
1318 /* If we still don't have umul_ppmm, define it using plain C. */
1319 #if !defined (umul_ppmm)
1320 #define umul_ppmm(w1, w0, u, v) \
1321 do { \
1322 UWtype __x0, __x1, __x2, __x3; \
1323 UHWtype __ul, __vl, __uh, __vh; \
1324 \
1325 __ul = __ll_lowpart (u); \
1326 __uh = __ll_highpart (u); \
1327 __vl = __ll_lowpart (v); \
1328 __vh = __ll_highpart (v); \
1329 \
1330 __x0 = (UWtype) __ul * __vl; \
1331 __x1 = (UWtype) __ul * __vh; \
1332 __x2 = (UWtype) __uh * __vl; \
1333 __x3 = (UWtype) __uh * __vh; \
1334 \
1335 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1336 __x1 += __x2; /* but this indeed can */ \
1337 if (__x1 < __x2) /* did we get it? */ \
1338 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1339 \
1340 (w1) = __x3 + __ll_highpart (__x1); \
1341 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1342 } while (0)
1343 #endif
1344
1345 #if !defined (__umulsidi3)
1346 #define __umulsidi3(u, v) \
1347 ({DWunion __w; \
1348 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1349 __w.ll; })
1350 #endif
1351
1352 /* Define this unconditionally, so it can be used for debugging. */
1353 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1354 do { \
1355 UWtype __d1, __d0, __q1, __q0; \
1356 UWtype __r1, __r0, __m; \
1357 __d1 = __ll_highpart (d); \
1358 __d0 = __ll_lowpart (d); \
1359 \
1360 __r1 = (n1) % __d1; \
1361 __q1 = (n1) / __d1; \
1362 __m = (UWtype) __q1 * __d0; \
1363 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1364 if (__r1 < __m) \
1365 { \
1366 __q1--, __r1 += (d); \
1367 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1368 if (__r1 < __m) \
1369 __q1--, __r1 += (d); \
1370 } \
1371 __r1 -= __m; \
1372 \
1373 __r0 = __r1 % __d1; \
1374 __q0 = __r1 / __d1; \
1375 __m = (UWtype) __q0 * __d0; \
1376 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1377 if (__r0 < __m) \
1378 { \
1379 __q0--, __r0 += (d); \
1380 if (__r0 >= (d)) \
1381 if (__r0 < __m) \
1382 __q0--, __r0 += (d); \
1383 } \
1384 __r0 -= __m; \
1385 \
1386 (q) = (UWtype) __q1 * __ll_B | __q0; \
1387 (r) = __r0; \
1388 } while (0)
1389
1390 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1391 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1392 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1393 #define udiv_qrnnd(q, r, nh, nl, d) \
1394 do { \
1395 USItype __r; \
1396 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1397 (r) = __r; \
1398 } while (0)
1399 #endif
1400
1401 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1402 #if !defined (udiv_qrnnd)
1403 #define UDIV_NEEDS_NORMALIZATION 1
1404 #define udiv_qrnnd __udiv_qrnnd_c
1405 #endif
1406
1407 #if !defined (count_leading_zeros)
1408 #define count_leading_zeros(count, x) \
1409 do { \
1410 UWtype __xr = (x); \
1411 UWtype __a; \
1412 \
1413 if (W_TYPE_SIZE <= 32) \
1414 { \
1415 __a = __xr < ((UWtype)1<<2*__BITS4) \
1416 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1417 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1418 } \
1419 else \
1420 { \
1421 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1422 if (((__xr >> __a) & 0xff) != 0) \
1423 break; \
1424 } \
1425 \
1426 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1427 } while (0)
1428 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1429 #endif
1430
1431 #if !defined (count_trailing_zeros)
1432 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1433 defined in asm, but if it is not, the C version above is good enough. */
1434 #define count_trailing_zeros(count, x) \
1435 do { \
1436 UWtype __ctz_x = (x); \
1437 UWtype __ctz_c; \
1438 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1439 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1440 } while (0)
1441 #endif
1442
1443 #ifndef UDIV_NEEDS_NORMALIZATION
1444 #define UDIV_NEEDS_NORMALIZATION 0
1445 #endif
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