PR tree-optimization/81303
[official-gcc.git] / gcc / testsuite / gcc.dg / zero_bits_compound-2.c
blob64e6744b7924b19b70d363f458314cbf3931ae83
1 /* Test whether an AND mask or'ed with the know zero bits that equals a mode
2 mask is a candidate for zero extendion. */
4 /* { dg-do compile { target i?86-*-* x86_64-*-* s390*-*-* aarch64*-*-* } } */
5 /* { dg-require-effective-target lp64 } */
6 /* { dg-options "-O3 -dP -fdump-rtl-combine" } */
8 unsigned long foo (unsigned char c)
10 unsigned long l;
11 unsigned int i;
13 i = ((unsigned int)c) << 8;
14 i |= ((unsigned int)c) << 20;
15 asm volatile ("":::);
16 i = i & 0x0fe0fe00;
17 asm volatile ("":::);
18 l = (unsigned long)i;
20 return l;
23 unsigned long bar (unsigned char c)
25 unsigned long l;
26 unsigned int i;
28 i = ((unsigned int)c) << 8;
29 i |= ((unsigned int)c) << 20;
30 asm volatile ("":::);
31 i = i & 0x07f007f0;
32 asm volatile ("":::);
33 l = (unsigned long)i;
35 return l;
38 /* Check that an AND expression was used. */
39 /* { dg-final { scan-assembler-times "\\(and:" 2 { target { ! aarch64*-*-* } } } } */
40 /* { dg-final { scan-rtl-dump "\\(and:DI" "combine" { target aarch64*-*-* } } } */
41 /* { dg-final { scan-rtl-dump "\\(and:SI" "combine" { target aarch64*-*-* } } } */