gcc/testsuite/gcc.dg/zero_bits_compound-1.c

   1 /* Test whether an AND mask or'ed with the know zero bits that equals a mode
   2    mask is a candidate for zero extendion.  */
   3
   4 /* Note: This test requires that char, int and long have different sizes and the
   5    target has a way to do 32 -> 64 bit zero extension other than AND.  */
   6
   7 /* { dg-do compile { target i?86-*-* x86_64-*-* s390*-*-* aarch64*-*-* } } */
   8 /* { dg-require-effective-target lp64 } */
   9 /* { dg-options "-O3 -dP" } */
  10
  11 unsigned long foo (unsigned char c)
  12 {
  13   unsigned long l;
  14   unsigned int i;
  15
  16   i = ((unsigned int)c) << 8;
  17   i |= ((unsigned int)c) << 20;
  18   asm volatile ("":::);
  19   i = i & 0x0ff0ff00;
  20   asm volatile ("":::);
  21   l = (unsigned long)i;
  22
  23   return l;
  24 }
  25
  26 unsigned long bar (unsigned char c)
  27 {
  28   unsigned long l;
  29   unsigned int i;
  30
  31   i = ((unsigned int)c) << 8;
  32   i |= ((unsigned int)c) << 20;
  33   asm volatile ("":::);
  34   i = i & 0x0ffffff0;
  35   asm volatile ("":::);
  36   l = (unsigned long)i;
  37
  38   return l;
  39 }
  40
  41 /* Check that no pattern containing an AND expression was used.  */
  42 /* { dg-final { scan-assembler-not "\\(and:" } } */