1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
29 #include "coretypes.h"
31 #include "hard-reg-set.h"
36 #include "basic-block.h"
38 #include "addresses.h"
40 #include "insn-config.h"
50 #include "tree-pass.h"
53 /* Maximum register number used in this function, plus one. */
57 static void init_reg_sets_1 (void);
58 static void init_reg_autoinc (void);
60 /* If we have auto-increment or auto-decrement and we can have secondary
61 reloads, we are not allowed to use classes requiring secondary
62 reloads for pseudos auto-incremented since reload can't handle it. */
63 /* We leave it to target hooks to decide if we have secondary reloads, so
64 assume that we might have them. */
65 #if defined(AUTO_INC_DEC) /* */
66 #define FORBIDDEN_INC_DEC_CLASSES
69 /* Register tables used by many passes. */
71 /* Indexed by hard register number, contains 1 for registers
72 that are fixed use (stack pointer, pc, frame pointer, etc.).
73 These are the registers that cannot be used to allocate
74 a pseudo reg for general use. */
76 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
78 /* Same info as a HARD_REG_SET. */
80 HARD_REG_SET fixed_reg_set
;
82 /* Data for initializing the above. */
84 static const char initial_fixed_regs
[] = FIXED_REGISTERS
;
86 /* Indexed by hard register number, contains 1 for registers
87 that are fixed use or are clobbered by function calls.
88 These are the registers that cannot be used to allocate
89 a pseudo reg whose life crosses calls unless we are able
90 to save/restore them across the calls. */
92 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
94 /* Same info as a HARD_REG_SET. */
96 HARD_REG_SET call_used_reg_set
;
98 /* HARD_REG_SET of registers we want to avoid caller saving. */
99 HARD_REG_SET losing_caller_save_reg_set
;
101 /* Data for initializing the above. */
103 static const char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
105 /* This is much like call_used_regs, except it doesn't have to
106 be a superset of FIXED_REGISTERS. This vector indicates
107 what is really call clobbered, and is used when defining
108 regs_invalidated_by_call. */
110 #ifdef CALL_REALLY_USED_REGISTERS
111 char call_really_used_regs
[] = CALL_REALLY_USED_REGISTERS
;
114 #ifdef CALL_REALLY_USED_REGISTERS
115 #define CALL_REALLY_USED_REGNO_P(X) call_really_used_regs[X]
117 #define CALL_REALLY_USED_REGNO_P(X) call_used_regs[X]
121 /* Indexed by hard register number, contains 1 for registers that are
122 fixed use or call used registers that cannot hold quantities across
123 calls even if we are willing to save and restore them. call fixed
124 registers are a subset of call used registers. */
126 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
128 /* The same info as a HARD_REG_SET. */
130 HARD_REG_SET call_fixed_reg_set
;
132 /* Indexed by hard register number, contains 1 for registers
133 that are being used for global register decls.
134 These must be exempt from ordinary flow analysis
135 and are also considered fixed. */
137 char global_regs
[FIRST_PSEUDO_REGISTER
];
139 /* Contains 1 for registers that are set or clobbered by calls. */
140 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
141 for someone's bright idea to have call_used_regs strictly include
142 fixed_regs. Which leaves us guessing as to the set of fixed_regs
143 that are actually preserved. We know for sure that those associated
144 with the local stack frame are safe, but scant others. */
146 HARD_REG_SET regs_invalidated_by_call
;
148 /* Table of register numbers in the order in which to try to use them. */
149 #ifdef REG_ALLOC_ORDER
150 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
152 /* The inverse of reg_alloc_order. */
153 int inv_reg_alloc_order
[FIRST_PSEUDO_REGISTER
];
156 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
158 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
160 /* The same information, but as an array of unsigned ints. We copy from
161 these unsigned ints to the table above. We do this so the tm.h files
162 do not have to be aware of the wordsize for machines with <= 64 regs.
163 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
166 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32)
168 static const unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
169 = REG_CLASS_CONTENTS
;
171 /* For each reg class, number of regs it contains. */
173 unsigned int reg_class_size
[N_REG_CLASSES
];
175 /* For each reg class, table listing all the containing classes. */
177 static enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
179 /* For each reg class, table listing all the classes contained in it. */
181 static enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
183 /* For each pair of reg classes,
184 a largest reg class contained in their union. */
186 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
188 /* For each pair of reg classes,
189 the smallest reg class containing their union. */
191 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
193 /* Array containing all of the register names. */
195 const char * reg_names
[] = REGISTER_NAMES
;
197 /* Array containing all of the register class names. */
199 const char * reg_class_names
[] = REG_CLASS_NAMES
;
201 /* For each hard register, the widest mode object that it can contain.
202 This will be a MODE_INT mode if the register can hold integers. Otherwise
203 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
206 enum machine_mode reg_raw_mode
[FIRST_PSEUDO_REGISTER
];
208 /* 1 if there is a register of given mode. */
210 bool have_regs_of_mode
[MAX_MACHINE_MODE
];
212 /* 1 if class does contain register of given mode. */
214 char contains_reg_of_mode
[N_REG_CLASSES
] [MAX_MACHINE_MODE
];
216 /* Maximum cost of moving from a register in one class to a register in
217 another class. Based on REGISTER_MOVE_COST. */
219 move_table
*move_cost
[MAX_MACHINE_MODE
];
221 /* Similar, but here we don't have to move if the first index is a subset
222 of the second so in that case the cost is zero. */
224 move_table
*may_move_in_cost
[MAX_MACHINE_MODE
];
226 /* Similar, but here we don't have to move if the first index is a superset
227 of the second so in that case the cost is zero. */
229 move_table
*may_move_out_cost
[MAX_MACHINE_MODE
];
231 /* Keep track of the last mode we initialized move costs for. */
232 static int last_mode_for_init_move_cost
;
234 #ifdef FORBIDDEN_INC_DEC_CLASSES
236 /* These are the classes that regs which are auto-incremented or decremented
239 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
241 /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec
244 static char *in_inc_dec
;
246 #endif /* FORBIDDEN_INC_DEC_CLASSES */
248 /* Sample MEM values for use by memory_move_secondary_cost. */
250 static GTY(()) rtx top_of_stack
[MAX_MACHINE_MODE
];
252 /* No more global register variables may be declared; true once
253 regclass has been initialized. */
255 static int no_global_reg_vars
= 0;
257 /* Specify number of hard registers given machine mode occupy. */
258 unsigned char hard_regno_nregs
[FIRST_PSEUDO_REGISTER
][MAX_MACHINE_MODE
];
260 /* Given a register bitmap, turn on the bits in a HARD_REG_SET that
261 correspond to the hard registers, if any, set in that map. This
262 could be done far more efficiently by having all sorts of special-cases
263 with moving single words, but probably isn't worth the trouble. */
266 reg_set_to_hard_reg_set (HARD_REG_SET
*to
, const_bitmap from
)
271 EXECUTE_IF_SET_IN_BITMAP (from
, 0, i
, bi
)
273 if (i
>= FIRST_PSEUDO_REGISTER
)
275 SET_HARD_REG_BIT (*to
, i
);
280 /* Function called only once to initialize the above data on reg usage.
281 Once this is done, various switches may override. */
288 /* First copy the register information from the initial int form into
291 for (i
= 0; i
< N_REG_CLASSES
; i
++)
293 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
295 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
296 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
297 if (int_reg_class_contents
[i
][j
/ 32]
298 & ((unsigned) 1 << (j
% 32)))
299 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
302 /* Sanity check: make sure the target macros FIXED_REGISTERS and
303 CALL_USED_REGISTERS had the right number of initializers. */
304 gcc_assert (sizeof fixed_regs
== sizeof initial_fixed_regs
);
305 gcc_assert (sizeof call_used_regs
== sizeof initial_call_used_regs
);
307 memcpy (fixed_regs
, initial_fixed_regs
, sizeof fixed_regs
);
308 memcpy (call_used_regs
, initial_call_used_regs
, sizeof call_used_regs
);
309 memset (global_regs
, 0, sizeof global_regs
);
312 /* Initialize may_move_cost and friends for mode M. */
315 init_move_cost (enum machine_mode m
)
317 static unsigned short last_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
318 bool all_match
= true;
321 gcc_assert (have_regs_of_mode
[m
]);
322 for (i
= 0; i
< N_REG_CLASSES
; i
++)
323 if (contains_reg_of_mode
[i
][m
])
324 for (j
= 0; j
< N_REG_CLASSES
; j
++)
327 if (!contains_reg_of_mode
[j
][m
])
331 cost
= REGISTER_MOVE_COST (m
, i
, j
);
332 gcc_assert (cost
< 65535);
334 all_match
&= (last_move_cost
[i
][j
] == cost
);
335 last_move_cost
[i
][j
] = cost
;
337 if (all_match
&& last_mode_for_init_move_cost
!= -1)
339 move_cost
[m
] = move_cost
[last_mode_for_init_move_cost
];
340 may_move_in_cost
[m
] = may_move_in_cost
[last_mode_for_init_move_cost
];
341 may_move_out_cost
[m
] = may_move_out_cost
[last_mode_for_init_move_cost
];
344 last_mode_for_init_move_cost
= m
;
345 move_cost
[m
] = (move_table
*)xmalloc (sizeof (move_table
)
347 may_move_in_cost
[m
] = (move_table
*)xmalloc (sizeof (move_table
)
349 may_move_out_cost
[m
] = (move_table
*)xmalloc (sizeof (move_table
)
351 for (i
= 0; i
< N_REG_CLASSES
; i
++)
352 if (contains_reg_of_mode
[i
][m
])
353 for (j
= 0; j
< N_REG_CLASSES
; j
++)
356 enum reg_class
*p1
, *p2
;
358 if (last_move_cost
[i
][j
] == 65535)
360 move_cost
[m
][i
][j
] = 65535;
361 may_move_in_cost
[m
][i
][j
] = 65535;
362 may_move_out_cost
[m
][i
][j
] = 65535;
366 cost
= last_move_cost
[i
][j
];
368 for (p2
= ®_class_subclasses
[j
][0];
369 *p2
!= LIM_REG_CLASSES
; p2
++)
370 if (*p2
!= i
&& contains_reg_of_mode
[*p2
][m
])
371 cost
= MAX (cost
, move_cost
[m
][i
][*p2
]);
373 for (p1
= ®_class_subclasses
[i
][0];
374 *p1
!= LIM_REG_CLASSES
; p1
++)
375 if (*p1
!= j
&& contains_reg_of_mode
[*p1
][m
])
376 cost
= MAX (cost
, move_cost
[m
][*p1
][j
]);
378 gcc_assert (cost
<= 65535);
379 move_cost
[m
][i
][j
] = cost
;
381 if (reg_class_subset_p (i
, j
))
382 may_move_in_cost
[m
][i
][j
] = 0;
384 may_move_in_cost
[m
][i
][j
] = cost
;
386 if (reg_class_subset_p (j
, i
))
387 may_move_out_cost
[m
][i
][j
] = 0;
389 may_move_out_cost
[m
][i
][j
] = cost
;
393 for (j
= 0; j
< N_REG_CLASSES
; j
++)
395 move_cost
[m
][i
][j
] = 65535;
396 may_move_in_cost
[m
][i
][j
] = 65535;
397 may_move_out_cost
[m
][i
][j
] = 65535;
401 /* We need to save copies of some of the register information which
402 can be munged by command-line switches so we can restore it during
403 subsequent back-end reinitialization. */
405 static char saved_fixed_regs
[FIRST_PSEUDO_REGISTER
];
406 static char saved_call_used_regs
[FIRST_PSEUDO_REGISTER
];
407 #ifdef CALL_REALLY_USED_REGISTERS
408 static char saved_call_really_used_regs
[FIRST_PSEUDO_REGISTER
];
410 static const char *saved_reg_names
[FIRST_PSEUDO_REGISTER
];
412 /* Save the register information. */
415 save_register_info (void)
417 /* Sanity check: make sure the target macros FIXED_REGISTERS and
418 CALL_USED_REGISTERS had the right number of initializers. */
419 gcc_assert (sizeof fixed_regs
== sizeof saved_fixed_regs
);
420 gcc_assert (sizeof call_used_regs
== sizeof saved_call_used_regs
);
421 memcpy (saved_fixed_regs
, fixed_regs
, sizeof fixed_regs
);
422 memcpy (saved_call_used_regs
, call_used_regs
, sizeof call_used_regs
);
424 /* Likewise for call_really_used_regs. */
425 #ifdef CALL_REALLY_USED_REGISTERS
426 gcc_assert (sizeof call_really_used_regs
427 == sizeof saved_call_really_used_regs
);
428 memcpy (saved_call_really_used_regs
, call_really_used_regs
,
429 sizeof call_really_used_regs
);
432 /* And similarly for reg_names. */
433 gcc_assert (sizeof reg_names
== sizeof saved_reg_names
);
434 memcpy (saved_reg_names
, reg_names
, sizeof reg_names
);
437 /* Restore the register information. */
440 restore_register_info (void)
442 memcpy (fixed_regs
, saved_fixed_regs
, sizeof fixed_regs
);
443 memcpy (call_used_regs
, saved_call_used_regs
, sizeof call_used_regs
);
445 #ifdef CALL_REALLY_USED_REGISTERS
446 memcpy (call_really_used_regs
, saved_call_really_used_regs
,
447 sizeof call_really_used_regs
);
450 memcpy (reg_names
, saved_reg_names
, sizeof reg_names
);
453 /* After switches have been processed, which perhaps alter
454 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
457 init_reg_sets_1 (void)
460 unsigned int /* enum machine_mode */ m
;
462 restore_register_info ();
464 #ifdef REG_ALLOC_ORDER
465 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
466 inv_reg_alloc_order
[reg_alloc_order
[i
]] = i
;
469 /* This macro allows the fixed or call-used registers
470 and the register classes to depend on target flags. */
472 #ifdef CONDITIONAL_REGISTER_USAGE
473 CONDITIONAL_REGISTER_USAGE
;
476 /* Compute number of hard regs in each class. */
478 memset (reg_class_size
, 0, sizeof reg_class_size
);
479 for (i
= 0; i
< N_REG_CLASSES
; i
++)
480 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
481 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
484 /* Initialize the table of subunions.
485 reg_class_subunion[I][J] gets the largest-numbered reg-class
486 that is contained in the union of classes I and J. */
488 memset (reg_class_subunion
, 0, sizeof reg_class_subunion
);
489 for (i
= 0; i
< N_REG_CLASSES
; i
++)
491 for (j
= 0; j
< N_REG_CLASSES
; j
++)
496 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
497 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
498 for (k
= 0; k
< N_REG_CLASSES
; k
++)
499 if (hard_reg_set_subset_p (reg_class_contents
[k
], c
)
500 && !hard_reg_set_subset_p (reg_class_contents
[k
],
502 [(int) reg_class_subunion
[i
][j
]]))
503 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
507 /* Initialize the table of superunions.
508 reg_class_superunion[I][J] gets the smallest-numbered reg-class
509 containing the union of classes I and J. */
511 memset (reg_class_superunion
, 0, sizeof reg_class_superunion
);
512 for (i
= 0; i
< N_REG_CLASSES
; i
++)
514 for (j
= 0; j
< N_REG_CLASSES
; j
++)
519 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
520 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
521 for (k
= 0; k
< N_REG_CLASSES
; k
++)
522 if (hard_reg_set_subset_p (c
, reg_class_contents
[k
]))
525 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
529 /* Initialize the tables of subclasses and superclasses of each reg class.
530 First clear the whole table, then add the elements as they are found. */
532 for (i
= 0; i
< N_REG_CLASSES
; i
++)
534 for (j
= 0; j
< N_REG_CLASSES
; j
++)
536 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
537 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
541 for (i
= 0; i
< N_REG_CLASSES
; i
++)
543 if (i
== (int) NO_REGS
)
546 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
547 if (hard_reg_set_subset_p (reg_class_contents
[i
],
548 reg_class_contents
[j
]))
550 /* Reg class I is a subclass of J.
551 Add J to the table of superclasses of I. */
554 p
= ®_class_superclasses
[i
][0];
555 while (*p
!= LIM_REG_CLASSES
) p
++;
556 *p
= (enum reg_class
) j
;
557 /* Add I to the table of superclasses of J. */
558 p
= ®_class_subclasses
[j
][0];
559 while (*p
!= LIM_REG_CLASSES
) p
++;
560 *p
= (enum reg_class
) i
;
564 /* Initialize "constant" tables. */
566 CLEAR_HARD_REG_SET (fixed_reg_set
);
567 CLEAR_HARD_REG_SET (call_used_reg_set
);
568 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
569 CLEAR_HARD_REG_SET (regs_invalidated_by_call
);
570 CLEAR_HARD_REG_SET (losing_caller_save_reg_set
);
572 memcpy (call_fixed_regs
, fixed_regs
, sizeof call_fixed_regs
);
574 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
576 /* call_used_regs must include fixed_regs. */
577 gcc_assert (!fixed_regs
[i
] || call_used_regs
[i
]);
578 #ifdef CALL_REALLY_USED_REGISTERS
579 /* call_used_regs must include call_really_used_regs. */
580 gcc_assert (!call_really_used_regs
[i
] || call_used_regs
[i
]);
584 SET_HARD_REG_BIT (fixed_reg_set
, i
);
586 if (call_used_regs
[i
])
587 SET_HARD_REG_BIT (call_used_reg_set
, i
);
588 if (call_fixed_regs
[i
])
589 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
590 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i
)))
591 SET_HARD_REG_BIT (losing_caller_save_reg_set
, i
);
593 /* There are a couple of fixed registers that we know are safe to
594 exclude from being clobbered by calls:
596 The frame pointer is always preserved across calls. The arg pointer
597 is if it is fixed. The stack pointer usually is, unless
598 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
599 If we are generating PIC code, the PIC offset table register is
600 preserved across calls, though the target can override that. */
602 if (i
== STACK_POINTER_REGNUM
)
604 else if (global_regs
[i
])
605 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
606 else if (i
== FRAME_POINTER_REGNUM
)
608 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
609 else if (i
== HARD_FRAME_POINTER_REGNUM
)
612 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
613 else if (i
== ARG_POINTER_REGNUM
&& fixed_regs
[i
])
616 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
617 else if (i
== (unsigned) PIC_OFFSET_TABLE_REGNUM
&& fixed_regs
[i
])
620 else if (CALL_REALLY_USED_REGNO_P (i
))
621 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
624 /* Preserve global registers if called more than once. */
625 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
629 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
630 SET_HARD_REG_BIT (fixed_reg_set
, i
);
631 SET_HARD_REG_BIT (call_used_reg_set
, i
);
632 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
636 memset (have_regs_of_mode
, 0, sizeof (have_regs_of_mode
));
637 memset (contains_reg_of_mode
, 0, sizeof (contains_reg_of_mode
));
638 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
640 HARD_REG_SET ok_regs
;
641 CLEAR_HARD_REG_SET (ok_regs
);
642 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
643 if (!fixed_regs
[j
] && HARD_REGNO_MODE_OK (j
, m
))
644 SET_HARD_REG_BIT (ok_regs
, j
);
646 for (i
= 0; i
< N_REG_CLASSES
; i
++)
647 if ((unsigned) CLASS_MAX_NREGS (i
, m
) <= reg_class_size
[i
]
648 && hard_reg_set_intersect_p (ok_regs
, reg_class_contents
[i
]))
650 contains_reg_of_mode
[i
][m
] = 1;
651 have_regs_of_mode
[m
] = 1;
655 /* Reset move_cost and friends, making sure we only free shared
656 table entries once. */
657 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
660 for (j
= 0; j
< i
&& move_cost
[i
] != move_cost
[j
]; j
++)
665 free (may_move_in_cost
[i
]);
666 free (may_move_out_cost
[i
]);
669 memset (move_cost
, 0, sizeof move_cost
);
670 memset (may_move_in_cost
, 0, sizeof may_move_in_cost
);
671 memset (may_move_out_cost
, 0, sizeof may_move_out_cost
);
672 last_mode_for_init_move_cost
= -1;
675 /* Compute the table of register modes.
676 These values are used to record death information for individual registers
677 (as opposed to a multi-register mode).
678 This function might be invoked more than once, if the target has support
679 for changing register usage conventions on a per-function basis.
683 init_reg_modes_target (void)
687 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
688 for (j
= 0; j
< MAX_MACHINE_MODE
; j
++)
689 hard_regno_nregs
[i
][j
] = HARD_REGNO_NREGS(i
, (enum machine_mode
)j
);
691 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
693 reg_raw_mode
[i
] = choose_hard_reg_mode (i
, 1, false);
695 /* If we couldn't find a valid mode, just use the previous mode.
696 ??? One situation in which we need to do this is on the mips where
697 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
698 to use DF mode for the even registers and VOIDmode for the odd
699 (for the cpu models where the odd ones are inaccessible). */
700 if (reg_raw_mode
[i
] == VOIDmode
)
701 reg_raw_mode
[i
] = i
== 0 ? word_mode
: reg_raw_mode
[i
-1];
705 /* Finish initializing the register sets and initialize the register modes.
706 This function might be invoked more than once, if the target has support
707 for changing register usage conventions on a per-function basis.
713 /* This finishes what was started by init_reg_sets, but couldn't be done
714 until after register usage was specified. */
720 /* Initialize some fake stack-frame MEM references for use in
721 memory_move_secondary_cost. */
724 init_fake_stack_mems (void)
729 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
730 top_of_stack
[i
] = gen_rtx_MEM (i
, stack_pointer_rtx
);
735 /* Compute extra cost of moving registers to/from memory due to reloads.
736 Only needed if secondary reloads are required for memory moves. */
739 memory_move_secondary_cost (enum machine_mode mode
, enum reg_class
class, int in
)
741 enum reg_class altclass
;
742 int partial_cost
= 0;
743 /* We need a memory reference to feed to SECONDARY... macros. */
744 /* mem may be unused even if the SECONDARY_ macros are defined. */
745 rtx mem ATTRIBUTE_UNUSED
= top_of_stack
[(int) mode
];
748 altclass
= secondary_reload_class (in
? 1 : 0, class, mode
, mem
);
750 if (altclass
== NO_REGS
)
754 partial_cost
= REGISTER_MOVE_COST (mode
, altclass
, class);
756 partial_cost
= REGISTER_MOVE_COST (mode
, class, altclass
);
758 if (class == altclass
)
759 /* This isn't simply a copy-to-temporary situation. Can't guess
760 what it is, so MEMORY_MOVE_COST really ought not to be calling
763 I'm tempted to put in an assert here, but returning this will
764 probably only give poor estimates, which is what we would've
765 had before this code anyways. */
768 /* Check if the secondary reload register will also need a
770 return memory_move_secondary_cost (mode
, altclass
, in
) + partial_cost
;
773 /* Return a machine mode that is legitimate for hard reg REGNO and large
774 enough to save nregs. If we can't find one, return VOIDmode.
775 If CALL_SAVED is true, only consider modes that are call saved. */
778 choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED
,
779 unsigned int nregs
, bool call_saved
)
781 unsigned int /* enum machine_mode */ m
;
782 enum machine_mode found_mode
= VOIDmode
, mode
;
784 /* We first look for the largest integer mode that can be validly
785 held in REGNO. If none, we look for the largest floating-point mode.
786 If we still didn't find a valid mode, try CCmode. */
788 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
790 mode
= GET_MODE_WIDER_MODE (mode
))
791 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
792 && HARD_REGNO_MODE_OK (regno
, mode
)
793 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
796 if (found_mode
!= VOIDmode
)
799 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
801 mode
= GET_MODE_WIDER_MODE (mode
))
802 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
803 && HARD_REGNO_MODE_OK (regno
, mode
)
804 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
807 if (found_mode
!= VOIDmode
)
810 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT
);
812 mode
= GET_MODE_WIDER_MODE (mode
))
813 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
814 && HARD_REGNO_MODE_OK (regno
, mode
)
815 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
818 if (found_mode
!= VOIDmode
)
821 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT
);
823 mode
= GET_MODE_WIDER_MODE (mode
))
824 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
825 && HARD_REGNO_MODE_OK (regno
, mode
)
826 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
829 if (found_mode
!= VOIDmode
)
832 /* Iterate over all of the CCmodes. */
833 for (m
= (unsigned int) CCmode
; m
< (unsigned int) NUM_MACHINE_MODES
; ++m
)
835 mode
= (enum machine_mode
) m
;
836 if ((unsigned) hard_regno_nregs
[regno
][mode
] == nregs
837 && HARD_REGNO_MODE_OK (regno
, mode
)
838 && (! call_saved
|| ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
842 /* We can't find a mode valid for this register. */
846 /* Specify the usage characteristics of the register named NAME.
847 It should be a fixed register if FIXED and a
848 call-used register if CALL_USED. */
851 fix_register (const char *name
, int fixed
, int call_used
)
855 /* Decode the name and update the primary form of
856 the register info. */
858 if ((i
= decode_reg_name (name
)) >= 0)
860 if ((i
== STACK_POINTER_REGNUM
861 #ifdef HARD_FRAME_POINTER_REGNUM
862 || i
== HARD_FRAME_POINTER_REGNUM
864 || i
== FRAME_POINTER_REGNUM
867 && (fixed
== 0 || call_used
== 0))
869 static const char * const what_option
[2][2] = {
870 { "call-saved", "call-used" },
871 { "no-such-option", "fixed" }};
873 error ("can't use '%s' as a %s register", name
,
874 what_option
[fixed
][call_used
]);
878 fixed_regs
[i
] = fixed
;
879 call_used_regs
[i
] = call_used
;
880 #ifdef CALL_REALLY_USED_REGISTERS
882 call_really_used_regs
[i
] = call_used
;
888 warning (0, "unknown register name: %s", name
);
892 /* Mark register number I as global. */
895 globalize_reg (int i
)
897 if (fixed_regs
[i
] == 0 && no_global_reg_vars
)
898 error ("global register variable follows a function definition");
902 warning (0, "register used for two global register variables");
906 if (call_used_regs
[i
] && ! fixed_regs
[i
])
907 warning (0, "call-clobbered register used for global register variable");
911 /* If we're globalizing the frame pointer, we need to set the
912 appropriate regs_invalidated_by_call bit, even if it's already
913 set in fixed_regs. */
914 if (i
!= STACK_POINTER_REGNUM
)
915 SET_HARD_REG_BIT (regs_invalidated_by_call
, i
);
917 /* If already fixed, nothing else to do. */
921 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
922 #ifdef CALL_REALLY_USED_REGISTERS
923 call_really_used_regs
[i
] = 1;
926 SET_HARD_REG_BIT (fixed_reg_set
, i
);
927 SET_HARD_REG_BIT (call_used_reg_set
, i
);
928 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
931 /* Now the data and code for the `regclass' pass, which happens
932 just before local-alloc. */
934 /* The `costs' struct records the cost of using a hard register of each class
935 and of using memory for each pseudo. We use this data to set up
936 register class preferences. */
940 int cost
[N_REG_CLASSES
];
944 /* Structure used to record preferences of given pseudo. */
947 /* (enum reg_class) prefclass is the preferred class. May be
948 NO_REGS if no class is better than memory. */
951 /* altclass is a register class that we should use for allocating
952 pseudo if no register in the preferred class is available.
953 If no register in this class is available, memory is preferred.
955 It might appear to be more general to have a bitmask of classes here,
956 but since it is recommended that there be a class corresponding to the
957 union of most major pair of classes, that generality is not required. */
961 /* Record the cost of each class for each pseudo. */
963 static struct costs
*costs
;
965 /* Initialized once, and used to initialize cost values for each insn. */
967 static struct costs init_cost
;
969 /* Record preferences of each pseudo.
970 This is available after `regclass' is run. */
972 static struct reg_pref
*reg_pref
;
974 /* Frequency of executions of current insn. */
976 static int frequency
;
978 static rtx
scan_one_insn (rtx
, int);
979 static void record_operand_costs (rtx
, struct costs
*, struct reg_pref
*);
980 static void dump_regclass (FILE *);
981 static void record_reg_classes (int, int, rtx
*, enum machine_mode
*,
982 const char **, rtx
, struct costs
*,
984 static int copy_cost (rtx
, enum machine_mode
, enum reg_class
, int,
985 secondary_reload_info
*);
986 static void record_address_regs (enum machine_mode
, rtx
, int, enum rtx_code
,
988 #ifdef FORBIDDEN_INC_DEC_CLASSES
989 static int auto_inc_dec_reg_p (rtx
, enum machine_mode
);
991 static void reg_scan_mark_refs (rtx
, rtx
);
993 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
996 ok_for_index_p_nonstrict (rtx reg
)
998 unsigned regno
= REGNO (reg
);
999 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
1002 /* A version of regno_ok_for_base_p for use during regclass, when all pseudos
1003 should count as OK. Arguments as for regno_ok_for_base_p. */
1006 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
,
1007 enum rtx_code outer_code
, enum rtx_code index_code
)
1009 unsigned regno
= REGNO (reg
);
1010 if (regno
>= FIRST_PSEUDO_REGISTER
)
1013 return ok_for_base_p_1 (regno
, mode
, outer_code
, index_code
);
1016 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
1017 This function is sometimes called before the info has been computed.
1018 When that happens, just return GENERAL_REGS, which is innocuous. */
1021 reg_preferred_class (int regno
)
1024 return GENERAL_REGS
;
1026 return (enum reg_class
) reg_pref
[regno
].prefclass
;
1030 reg_alternate_class (int regno
)
1035 return (enum reg_class
) reg_pref
[regno
].altclass
;
1038 /* Initialize some global data for this pass. */
1041 regclass_init (void)
1046 df_compute_regs_ever_live (true);
1048 init_cost
.mem_cost
= 10000;
1049 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1050 init_cost
.cost
[i
] = 10000;
1052 /* This prevents dump_flow_info from losing if called
1053 before regclass is run. */
1056 /* No more global register variables may be declared. */
1057 no_global_reg_vars
= 1;
1061 struct tree_opt_pass pass_regclass_init
=
1063 "regclass", /* name */
1065 regclass_init
, /* execute */
1068 0, /* static_pass_number */
1070 0, /* properties_required */
1071 0, /* properties_provided */
1072 0, /* properties_destroyed */
1073 0, /* todo_flags_start */
1074 0, /* todo_flags_finish */
1080 /* Dump register costs. */
1082 dump_regclass (FILE *dump
)
1085 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1087 int /* enum reg_class */ class;
1090 fprintf (dump
, " Register %i costs:", i
);
1091 for (class = 0; class < (int) N_REG_CLASSES
; class++)
1092 if (contains_reg_of_mode
[(enum reg_class
) class][PSEUDO_REGNO_MODE (i
)]
1093 #ifdef FORBIDDEN_INC_DEC_CLASSES
1095 || !forbidden_inc_dec_class
[(enum reg_class
) class])
1097 #ifdef CANNOT_CHANGE_MODE_CLASS
1098 && ! invalid_mode_change_p (i
, (enum reg_class
) class,
1099 PSEUDO_REGNO_MODE (i
))
1102 fprintf (dump
, " %s:%i", reg_class_names
[class],
1103 costs
[i
].cost
[(enum reg_class
) class]);
1104 fprintf (dump
, " MEM:%i\n", costs
[i
].mem_cost
);
1110 /* Calculate the costs of insn operands. */
1113 record_operand_costs (rtx insn
, struct costs
*op_costs
,
1114 struct reg_pref
*reg_pref
)
1116 const char *constraints
[MAX_RECOG_OPERANDS
];
1117 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
1120 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1122 constraints
[i
] = recog_data
.constraints
[i
];
1123 modes
[i
] = recog_data
.operand_mode
[i
];
1126 /* If we get here, we are set up to record the costs of all the
1127 operands for this insn. Start by initializing the costs.
1128 Then handle any address registers. Finally record the desired
1129 classes for any pseudos, doing it twice if some pair of
1130 operands are commutative. */
1132 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1134 op_costs
[i
] = init_cost
;
1136 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
1137 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
1139 if (MEM_P (recog_data
.operand
[i
]))
1140 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
1141 XEXP (recog_data
.operand
[i
], 0),
1142 0, MEM
, SCRATCH
, frequency
* 2);
1143 else if (constraints
[i
][0] == 'p'
1144 || EXTRA_ADDRESS_CONSTRAINT (constraints
[i
][0], constraints
[i
]))
1145 record_address_regs (VOIDmode
, recog_data
.operand
[i
], 0, ADDRESS
,
1146 SCRATCH
, frequency
* 2);
1149 /* Check for commutative in a separate loop so everything will
1150 have been initialized. We must do this even if one operand
1151 is a constant--see addsi3 in m68k.md. */
1153 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
1154 if (constraints
[i
][0] == '%')
1156 const char *xconstraints
[MAX_RECOG_OPERANDS
];
1159 /* Handle commutative operands by swapping the constraints.
1160 We assume the modes are the same. */
1162 for (j
= 0; j
< recog_data
.n_operands
; j
++)
1163 xconstraints
[j
] = constraints
[j
];
1165 xconstraints
[i
] = constraints
[i
+1];
1166 xconstraints
[i
+1] = constraints
[i
];
1167 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1168 recog_data
.operand
, modes
,
1169 xconstraints
, insn
, op_costs
, reg_pref
);
1172 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1173 recog_data
.operand
, modes
,
1174 constraints
, insn
, op_costs
, reg_pref
);
1177 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1178 time it would save code to put a certain register in a certain class.
1179 PASS, when nonzero, inhibits some optimizations which need only be done
1181 Return the last insn processed, so that the scan can be continued from
1185 scan_one_insn (rtx insn
, int pass ATTRIBUTE_UNUSED
)
1187 enum rtx_code pat_code
;
1190 struct costs op_costs
[MAX_RECOG_OPERANDS
];
1195 pat_code
= GET_CODE (PATTERN (insn
));
1197 || pat_code
== CLOBBER
1198 || pat_code
== ASM_INPUT
1199 || pat_code
== ADDR_VEC
1200 || pat_code
== ADDR_DIFF_VEC
)
1203 set
= single_set (insn
);
1204 extract_insn (insn
);
1206 /* If this insn loads a parameter from its stack slot, then
1207 it represents a savings, rather than a cost, if the
1208 parameter is stored in memory. Record this fact. */
1210 if (set
!= 0 && REG_P (SET_DEST (set
))
1211 && MEM_P (SET_SRC (set
))
1212 && (note
= find_reg_note (insn
, REG_EQUIV
,
1214 && MEM_P (XEXP (note
, 0)))
1216 costs
[REGNO (SET_DEST (set
))].mem_cost
1217 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)),
1220 record_address_regs (GET_MODE (SET_SRC (set
)), XEXP (SET_SRC (set
), 0),
1221 0, MEM
, SCRATCH
, frequency
* 2);
1225 record_operand_costs (insn
, op_costs
, reg_pref
);
1227 /* Now add the cost for each operand to the total costs for
1230 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1231 if (REG_P (recog_data
.operand
[i
])
1232 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1234 int regno
= REGNO (recog_data
.operand
[i
]);
1235 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
1237 p
->mem_cost
+= q
->mem_cost
* frequency
;
1238 for (j
= 0; j
< N_REG_CLASSES
; j
++)
1239 p
->cost
[j
] += q
->cost
[j
] * frequency
;
1245 /* Initialize information about which register classes can be used for
1246 pseudos that are auto-incremented or auto-decremented. */
1249 init_reg_autoinc (void)
1251 #ifdef FORBIDDEN_INC_DEC_CLASSES
1254 memset (forbidden_inc_dec_class
, 0, sizeof forbidden_inc_dec_class
);
1255 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1257 rtx r
= gen_rtx_raw_REG (VOIDmode
, 0);
1258 enum machine_mode m
;
1261 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1262 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
1266 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
1267 m
= (enum machine_mode
) ((int) m
+ 1))
1268 if (HARD_REGNO_MODE_OK (j
, m
))
1270 /* ??? There are two assumptions here; that the base class does not
1271 depend on the exact outer code (POST_INC vs. PRE_INC etc.), and
1272 that it does not depend on the machine mode of the memory
1274 enum reg_class base_class
1275 = base_reg_class (VOIDmode
, POST_INC
, SCRATCH
);
1279 /* If a register is not directly suitable for an
1280 auto-increment or decrement addressing mode and
1281 requires secondary reloads, disallow its class from
1282 being used in such addresses. */
1284 if ((secondary_reload_class (0, base_class
, m
, r
)
1285 || secondary_reload_class (1, base_class
, m
, r
))
1286 && ! auto_inc_dec_reg_p (r
, m
))
1287 forbidden_inc_dec_class
[i
] = 1;
1291 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1294 /* This is a pass of the compiler that scans all instructions
1295 and calculates the preferred class for each pseudo-register.
1296 This information can be accessed later by calling `reg_preferred_class'.
1297 This pass comes just before local register allocation. */
1300 regclass (rtx f
, int nregs
)
1305 max_regno
= max_reg_num ();
1309 reg_renumber
= xmalloc (max_regno
* sizeof (short));
1310 reg_pref
= XCNEWVEC (struct reg_pref
, max_regno
);
1311 memset (reg_renumber
, -1, max_regno
* sizeof (short));
1313 costs
= XNEWVEC (struct costs
, nregs
);
1315 #ifdef FORBIDDEN_INC_DEC_CLASSES
1317 in_inc_dec
= XNEWVEC (char, nregs
);
1319 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1321 /* Normally we scan the insns once and determine the best class to use for
1322 each register. However, if -fexpensive_optimizations are on, we do so
1323 twice, the second time using the tentative best classes to guide the
1326 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1331 fprintf (dump_file
, "\n\nPass %i\n\n",pass
);
1332 /* Zero out our accumulation of the cost of each class for each reg. */
1334 memset (costs
, 0, nregs
* sizeof (struct costs
));
1336 #ifdef FORBIDDEN_INC_DEC_CLASSES
1337 memset (in_inc_dec
, 0, nregs
);
1340 /* Scan the instructions and record each time it would
1341 save code to put a certain register in a certain class. */
1345 frequency
= REG_FREQ_MAX
;
1346 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1347 insn
= scan_one_insn (insn
, pass
);
1352 /* Show that an insn inside a loop is likely to be executed three
1353 times more than insns outside a loop. This is much more
1354 aggressive than the assumptions made elsewhere and is being
1355 tried as an experiment. */
1356 frequency
= REG_FREQ_FROM_BB (bb
);
1357 for (insn
= BB_HEAD (bb
); ; insn
= NEXT_INSN (insn
))
1359 insn
= scan_one_insn (insn
, pass
);
1360 if (insn
== BB_END (bb
))
1365 /* Now for each register look at how desirable each class is
1366 and find which class is preferred. Store that in
1367 `prefclass'. Record in `altclass' the largest register
1368 class any of whose registers is better than memory. */
1372 dump_regclass (dump_file
);
1373 fprintf (dump_file
,"\n");
1375 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
1377 int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1378 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
1379 /* This is an enum reg_class, but we call it an int
1380 to save lots of casts. */
1382 struct costs
*p
= &costs
[i
];
1384 if (regno_reg_rtx
[i
] == NULL
)
1387 /* In non-optimizing compilation REG_N_REFS is not initialized
1389 if (optimize
&& !REG_N_REFS (i
) && !REG_N_SETS (i
))
1392 for (class = (int) ALL_REGS
- 1; class > 0; class--)
1394 /* Ignore classes that are too small for this operand or
1395 invalid for an operand that was auto-incremented. */
1396 if (!contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (i
)]
1397 #ifdef FORBIDDEN_INC_DEC_CLASSES
1398 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1400 #ifdef CANNOT_CHANGE_MODE_CLASS
1401 || invalid_mode_change_p (i
, (enum reg_class
) class,
1402 PSEUDO_REGNO_MODE (i
))
1406 else if (p
->cost
[class] < best_cost
)
1408 best_cost
= p
->cost
[class];
1409 best
= (enum reg_class
) class;
1411 else if (p
->cost
[class] == best_cost
)
1412 best
= reg_class_subunion
[(int) best
][class];
1415 /* If no register class is better than memory, use memory. */
1416 if (p
->mem_cost
< best_cost
)
1419 /* Record the alternate register class; i.e., a class for which
1420 every register in it is better than using memory. If adding a
1421 class would make a smaller class (i.e., no union of just those
1422 classes exists), skip that class. The major unions of classes
1423 should be provided as a register class. Don't do this if we
1424 will be doing it again later. */
1426 if ((pass
== 1 || dump_file
) || ! flag_expensive_optimizations
)
1427 for (class = 0; class < N_REG_CLASSES
; class++)
1428 if (p
->cost
[class] < p
->mem_cost
1429 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
1430 > reg_class_size
[(int) alt
])
1431 #ifdef FORBIDDEN_INC_DEC_CLASSES
1432 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1434 #ifdef CANNOT_CHANGE_MODE_CLASS
1435 && ! invalid_mode_change_p (i
, (enum reg_class
) class,
1436 PSEUDO_REGNO_MODE (i
))
1439 alt
= reg_class_subunion
[(int) alt
][class];
1441 /* If we don't add any classes, nothing to try. */
1446 && (reg_pref
[i
].prefclass
!= (int) best
1447 || reg_pref
[i
].altclass
!= (int) alt
))
1449 fprintf (dump_file
, " Register %i", i
);
1450 if (alt
== ALL_REGS
|| best
== ALL_REGS
)
1451 fprintf (dump_file
, " pref %s\n", reg_class_names
[(int) best
]);
1452 else if (alt
== NO_REGS
)
1453 fprintf (dump_file
, " pref %s or none\n", reg_class_names
[(int) best
]);
1455 fprintf (dump_file
, " pref %s, else %s\n",
1456 reg_class_names
[(int) best
],
1457 reg_class_names
[(int) alt
]);
1460 /* We cast to (int) because (char) hits bugs in some compilers. */
1461 reg_pref
[i
].prefclass
= (int) best
;
1462 reg_pref
[i
].altclass
= (int) alt
;
1466 #ifdef FORBIDDEN_INC_DEC_CLASSES
1472 /* Record the cost of using memory or registers of various classes for
1473 the operands in INSN.
1475 N_ALTS is the number of alternatives.
1477 N_OPS is the number of operands.
1479 OPS is an array of the operands.
1481 MODES are the modes of the operands, in case any are VOIDmode.
1483 CONSTRAINTS are the constraints to use for the operands. This array
1484 is modified by this procedure.
1486 This procedure works alternative by alternative. For each alternative
1487 we assume that we will be able to allocate all pseudos to their ideal
1488 register class and calculate the cost of using that alternative. Then
1489 we compute for each operand that is a pseudo-register, the cost of
1490 having the pseudo allocated to each register class and using it in that
1491 alternative. To this cost is added the cost of the alternative.
1493 The cost of each class for this insn is its lowest cost among all the
1497 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
1498 enum machine_mode
*modes
, const char **constraints
,
1499 rtx insn
, struct costs
*op_costs
,
1500 struct reg_pref
*reg_pref
)
1506 /* Process each alternative, each time minimizing an operand's cost with
1507 the cost for each operand in that alternative. */
1509 for (alt
= 0; alt
< n_alts
; alt
++)
1511 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
1514 enum reg_class classes
[MAX_RECOG_OPERANDS
];
1515 int allows_mem
[MAX_RECOG_OPERANDS
];
1518 for (i
= 0; i
< n_ops
; i
++)
1520 const char *p
= constraints
[i
];
1522 enum machine_mode mode
= modes
[i
];
1523 int allows_addr
= 0;
1527 /* Initially show we know nothing about the register class. */
1528 classes
[i
] = NO_REGS
;
1531 /* If this operand has no constraints at all, we can conclude
1532 nothing about it since anything is valid. */
1536 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1537 memset (&this_op_costs
[i
], 0, sizeof this_op_costs
[i
]);
1542 /* If this alternative is only relevant when this operand
1543 matches a previous operand, we do different things depending
1544 on whether this operand is a pseudo-reg or not. We must process
1545 any modifiers for the operand before we can make this test. */
1547 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
1550 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
1552 /* Copy class and whether memory is allowed from the matching
1553 alternative. Then perform any needed cost computations
1554 and/or adjustments. */
1556 classes
[i
] = classes
[j
];
1557 allows_mem
[i
] = allows_mem
[j
];
1559 if (!REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1561 /* If this matches the other operand, we have no added
1563 if (rtx_equal_p (ops
[j
], op
))
1566 /* If we can put the other operand into a register, add to
1567 the cost of this alternative the cost to copy this
1568 operand to the register used for the other operand. */
1570 else if (classes
[j
] != NO_REGS
)
1572 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
1576 else if (!REG_P (ops
[j
])
1577 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
1579 /* This op is a pseudo but the one it matches is not. */
1581 /* If we can't put the other operand into a register, this
1582 alternative can't be used. */
1584 if (classes
[j
] == NO_REGS
)
1587 /* Otherwise, add to the cost of this alternative the cost
1588 to copy the other operand to the register used for this
1592 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
1596 /* The costs of this operand are not the same as the other
1597 operand since move costs are not symmetric. Moreover,
1598 if we cannot tie them, this alternative needs to do a
1599 copy, which is one instruction. */
1601 struct costs
*pp
= &this_op_costs
[i
];
1602 move_table
*intable
= NULL
;
1603 move_table
*outtable
= NULL
;
1604 int op_class
= (int) classes
[i
];
1606 if (!move_cost
[mode
])
1607 init_move_cost (mode
);
1608 intable
= may_move_in_cost
[mode
];
1609 outtable
= may_move_out_cost
[mode
];
1611 /* The loop is performance critical, so unswitch it manually.
1613 switch (recog_data
.operand_type
[i
])
1616 for (class = 0; class < N_REG_CLASSES
; class++)
1617 pp
->cost
[class] = (intable
[class][op_class
]
1618 + outtable
[op_class
][class]);
1621 for (class = 0; class < N_REG_CLASSES
; class++)
1622 pp
->cost
[class] = intable
[class][op_class
];
1625 for (class = 0; class < N_REG_CLASSES
; class++)
1626 pp
->cost
[class] = outtable
[op_class
][class];
1630 /* If the alternative actually allows memory, make things
1631 a bit cheaper since we won't need an extra insn to
1635 = ((recog_data
.operand_type
[i
] != OP_IN
1636 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1638 + (recog_data
.operand_type
[i
] != OP_OUT
1639 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1640 : 0) - allows_mem
[i
]);
1642 /* If we have assigned a class to this register in our
1643 first pass, add a cost to this alternative corresponding
1644 to what we would add if this register were not in the
1645 appropriate class. */
1647 if (reg_pref
&& reg_pref
[REGNO (op
)].prefclass
!= NO_REGS
)
1649 += (may_move_in_cost
[mode
]
1650 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1651 [(int) classes
[i
]]);
1653 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
1654 && ! find_reg_note (insn
, REG_DEAD
, op
))
1657 /* This is in place of ordinary cost computation
1658 for this operand, so skip to the end of the
1659 alternative (should be just one character). */
1660 while (*p
&& *p
++ != ',')
1668 /* Scan all the constraint letters. See if the operand matches
1669 any of the constraints. Collect the valid register classes
1670 and see if this operand accepts memory. */
1679 /* Ignore the next letter for this pass. */
1685 case '!': case '#': case '&':
1686 case '0': case '1': case '2': case '3': case '4':
1687 case '5': case '6': case '7': case '8': case '9':
1692 win
= address_operand (op
, GET_MODE (op
));
1693 /* We know this operand is an address, so we want it to be
1694 allocated to a register that can be the base of an
1695 address, i.e. BASE_REG_CLASS. */
1697 = reg_class_subunion
[(int) classes
[i
]]
1698 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1701 case 'm': case 'o': case 'V':
1702 /* It doesn't seem worth distinguishing between offsettable
1703 and non-offsettable addresses here. */
1711 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1712 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1718 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1719 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1725 if (GET_CODE (op
) == CONST_DOUBLE
1726 || (GET_CODE (op
) == CONST_VECTOR
1727 && (GET_MODE_CLASS (GET_MODE (op
))
1728 == MODE_VECTOR_FLOAT
)))
1734 if (GET_CODE (op
) == CONST_DOUBLE
1735 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1740 if (GET_CODE (op
) == CONST_INT
1741 || (GET_CODE (op
) == CONST_DOUBLE
1742 && GET_MODE (op
) == VOIDmode
))
1746 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
1751 if (GET_CODE (op
) == CONST_INT
1752 || (GET_CODE (op
) == CONST_DOUBLE
1753 && GET_MODE (op
) == VOIDmode
))
1765 if (GET_CODE (op
) == CONST_INT
1766 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1777 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
1782 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1786 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) != NO_REGS
)
1788 = reg_class_subunion
[(int) classes
[i
]]
1789 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1790 #ifdef EXTRA_CONSTRAINT_STR
1791 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1794 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1796 /* Every MEM can be reloaded to fit. */
1801 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1803 /* Every address can be reloaded to fit. */
1805 if (address_operand (op
, GET_MODE (op
)))
1807 /* We know this operand is an address, so we want it to
1808 be allocated to a register that can be the base of an
1809 address, i.e. BASE_REG_CLASS. */
1811 = reg_class_subunion
[(int) classes
[i
]]
1812 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1817 p
+= CONSTRAINT_LEN (c
, p
);
1824 /* How we account for this operand now depends on whether it is a
1825 pseudo register or not. If it is, we first check if any
1826 register classes are valid. If not, we ignore this alternative,
1827 since we want to assume that all pseudos get allocated for
1828 register preferencing. If some register class is valid, compute
1829 the costs of moving the pseudo into that class. */
1831 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1833 if (classes
[i
] == NO_REGS
)
1835 /* We must always fail if the operand is a REG, but
1836 we did not find a suitable class.
1838 Otherwise we may perform an uninitialized read
1839 from this_op_costs after the `continue' statement
1845 struct costs
*pp
= &this_op_costs
[i
];
1846 move_table
*intable
= NULL
;
1847 move_table
*outtable
= NULL
;
1848 int op_class
= (int) classes
[i
];
1850 if (!move_cost
[mode
])
1851 init_move_cost (mode
);
1852 intable
= may_move_in_cost
[mode
];
1853 outtable
= may_move_out_cost
[mode
];
1855 /* The loop is performance critical, so unswitch it manually.
1857 switch (recog_data
.operand_type
[i
])
1860 for (class = 0; class < N_REG_CLASSES
; class++)
1861 pp
->cost
[class] = (intable
[class][op_class
]
1862 + outtable
[op_class
][class]);
1865 for (class = 0; class < N_REG_CLASSES
; class++)
1866 pp
->cost
[class] = intable
[class][op_class
];
1869 for (class = 0; class < N_REG_CLASSES
; class++)
1870 pp
->cost
[class] = outtable
[op_class
][class];
1874 /* If the alternative actually allows memory, make things
1875 a bit cheaper since we won't need an extra insn to
1879 = ((recog_data
.operand_type
[i
] != OP_IN
1880 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1882 + (recog_data
.operand_type
[i
] != OP_OUT
1883 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1884 : 0) - allows_mem
[i
]);
1886 /* If we have assigned a class to this register in our
1887 first pass, add a cost to this alternative corresponding
1888 to what we would add if this register were not in the
1889 appropriate class. */
1891 if (reg_pref
&& reg_pref
[REGNO (op
)].prefclass
!= NO_REGS
)
1893 += (may_move_in_cost
[mode
]
1894 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1895 [(int) classes
[i
]]);
1899 /* Otherwise, if this alternative wins, either because we
1900 have already determined that or if we have a hard register of
1901 the proper class, there is no cost for this alternative. */
1905 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1908 /* If registers are valid, the cost of this alternative includes
1909 copying the object to and/or from a register. */
1911 else if (classes
[i
] != NO_REGS
)
1913 if (recog_data
.operand_type
[i
] != OP_OUT
)
1914 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
1916 if (recog_data
.operand_type
[i
] != OP_IN
)
1917 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
1920 /* The only other way this alternative can be used is if this is a
1921 constant that could be placed into memory. */
1923 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
1924 alt_cost
+= MEMORY_MOVE_COST (mode
, classes
[i
], 1);
1932 /* Finally, update the costs with the information we've calculated
1933 about this alternative. */
1935 for (i
= 0; i
< n_ops
; i
++)
1937 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1939 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1940 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1942 pp
->mem_cost
= MIN (pp
->mem_cost
,
1943 (qq
->mem_cost
+ alt_cost
) * scale
);
1945 for (class = 0; class < N_REG_CLASSES
; class++)
1946 pp
->cost
[class] = MIN (pp
->cost
[class],
1947 (qq
->cost
[class] + alt_cost
) * scale
);
1951 /* If this insn is a single set copying operand 1 to operand 0
1952 and one operand is a pseudo with the other a hard reg or a pseudo
1953 that prefers a register that is in its own register class then
1954 we may want to adjust the cost of that register class to -1.
1956 Avoid the adjustment if the source does not die to avoid stressing of
1957 register allocator by preferrencing two colliding registers into single
1960 Also avoid the adjustment if a copy between registers of the class
1961 is expensive (ten times the cost of a default copy is considered
1962 arbitrarily expensive). This avoids losing when the preferred class
1963 is very expensive as the source of a copy instruction. */
1965 if ((set
= single_set (insn
)) != 0
1966 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
1967 && REG_P (ops
[0]) && REG_P (ops
[1])
1968 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
1969 for (i
= 0; i
<= 1; i
++)
1970 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1972 unsigned int regno
= REGNO (ops
[!i
]);
1973 enum machine_mode mode
= GET_MODE (ops
[!i
]);
1976 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_pref
!= 0
1977 && reg_pref
[regno
].prefclass
!= NO_REGS
)
1979 enum reg_class pref
= reg_pref
[regno
].prefclass
;
1981 if ((reg_class_size
[(unsigned char) pref
]
1982 == (unsigned) CLASS_MAX_NREGS (pref
, mode
))
1983 && REGISTER_MOVE_COST (mode
, pref
, pref
) < 10 * 2)
1984 op_costs
[i
].cost
[(unsigned char) pref
] = -1;
1986 else if (regno
< FIRST_PSEUDO_REGISTER
)
1987 for (class = 0; class < N_REG_CLASSES
; class++)
1988 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1989 && reg_class_size
[class] == (unsigned) CLASS_MAX_NREGS (class, mode
))
1991 if (reg_class_size
[class] == 1)
1992 op_costs
[i
].cost
[class] = -1;
1993 else if (in_hard_reg_set_p (reg_class_contents
[class],
1995 op_costs
[i
].cost
[class] = -1;
2000 /* Compute the cost of loading X into (if TO_P is nonzero) or from (if
2001 TO_P is zero) a register of class CLASS in mode MODE.
2003 X must not be a pseudo. */
2006 copy_cost (rtx x
, enum machine_mode mode
, enum reg_class
class, int to_p
,
2007 secondary_reload_info
*prev_sri
)
2009 enum reg_class secondary_class
= NO_REGS
;
2010 secondary_reload_info sri
;
2012 /* If X is a SCRATCH, there is actually nothing to move since we are
2013 assuming optimal allocation. */
2015 if (GET_CODE (x
) == SCRATCH
)
2018 /* Get the class we will actually use for a reload. */
2019 class = PREFERRED_RELOAD_CLASS (x
, class);
2021 /* If we need a secondary reload for an intermediate, the
2022 cost is that to load the input into the intermediate register, then
2025 sri
.prev_sri
= prev_sri
;
2027 secondary_class
= targetm
.secondary_reload (to_p
, x
, class, mode
, &sri
);
2029 if (!move_cost
[mode
])
2030 init_move_cost (mode
);
2032 if (secondary_class
!= NO_REGS
)
2033 return (move_cost
[mode
][(int) secondary_class
][(int) class]
2035 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
2037 /* For memory, use the memory move cost, for (hard) registers, use the
2038 cost to move between the register classes, and use 2 for everything
2039 else (constants). */
2041 if (MEM_P (x
) || class == NO_REGS
)
2042 return sri
.extra_cost
+ MEMORY_MOVE_COST (mode
, class, to_p
);
2045 return (sri
.extra_cost
2046 + move_cost
[mode
][(int) REGNO_REG_CLASS (REGNO (x
))][(int) class]);
2049 /* If this is a constant, we may eventually want to call rtx_cost here. */
2050 return sri
.extra_cost
+ COSTS_N_INSNS (1);
2053 /* Record the pseudo registers we must reload into hard registers
2054 in a subexpression of a memory address, X.
2056 If CONTEXT is 0, we are looking at the base part of an address, otherwise we
2057 are looking at the index part.
2059 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE
2060 give the context that the rtx appears in. These three arguments are
2061 passed down to base_reg_class.
2063 SCALE is twice the amount to multiply the cost by (it is twice so we
2064 can represent half-cost adjustments). */
2067 record_address_regs (enum machine_mode mode
, rtx x
, int context
,
2068 enum rtx_code outer_code
, enum rtx_code index_code
,
2071 enum rtx_code code
= GET_CODE (x
);
2072 enum reg_class
class;
2075 class = INDEX_REG_CLASS
;
2077 class = base_reg_class (mode
, outer_code
, index_code
);
2090 /* When we have an address that is a sum,
2091 we must determine whether registers are "base" or "index" regs.
2092 If there is a sum of two registers, we must choose one to be
2093 the "base". Luckily, we can use the REG_POINTER to make a good
2094 choice most of the time. We only need to do this on machines
2095 that can have two registers in an address and where the base
2096 and index register classes are different.
2098 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
2099 that seems bogus since it should only be set when we are sure
2100 the register is being used as a pointer. */
2103 rtx arg0
= XEXP (x
, 0);
2104 rtx arg1
= XEXP (x
, 1);
2105 enum rtx_code code0
= GET_CODE (arg0
);
2106 enum rtx_code code1
= GET_CODE (arg1
);
2108 /* Look inside subregs. */
2109 if (code0
== SUBREG
)
2110 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
2111 if (code1
== SUBREG
)
2112 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
2114 /* If this machine only allows one register per address, it must
2115 be in the first operand. */
2117 if (MAX_REGS_PER_ADDRESS
== 1)
2118 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
2120 /* If index and base registers are the same on this machine, just
2121 record registers in any non-constant operands. We assume here,
2122 as well as in the tests below, that all addresses are in
2125 else if (INDEX_REG_CLASS
== base_reg_class (VOIDmode
, PLUS
, SCRATCH
))
2127 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
2128 if (! CONSTANT_P (arg1
))
2129 record_address_regs (mode
, arg1
, context
, PLUS
, code0
, scale
);
2132 /* If the second operand is a constant integer, it doesn't change
2133 what class the first operand must be. */
2135 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
2136 record_address_regs (mode
, arg0
, context
, PLUS
, code1
, scale
);
2138 /* If the second operand is a symbolic constant, the first operand
2139 must be an index register. */
2141 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
2142 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
2144 /* If both operands are registers but one is already a hard register
2145 of index or reg-base class, give the other the class that the
2146 hard register is not. */
2148 else if (code0
== REG
&& code1
== REG
2149 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
2150 && (ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
2151 || ok_for_index_p_nonstrict (arg0
)))
2152 record_address_regs (mode
, arg1
,
2153 ok_for_base_p_nonstrict (arg0
, mode
, PLUS
, REG
)
2156 else if (code0
== REG
&& code1
== REG
2157 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
2158 && (ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
2159 || ok_for_index_p_nonstrict (arg1
)))
2160 record_address_regs (mode
, arg0
,
2161 ok_for_base_p_nonstrict (arg1
, mode
, PLUS
, REG
)
2165 /* If one operand is known to be a pointer, it must be the base
2166 with the other operand the index. Likewise if the other operand
2169 else if ((code0
== REG
&& REG_POINTER (arg0
))
2172 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
);
2173 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
);
2175 else if ((code1
== REG
&& REG_POINTER (arg1
))
2178 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
);
2179 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
);
2182 /* Otherwise, count equal chances that each might be a base
2183 or index register. This case should be rare. */
2187 record_address_regs (mode
, arg0
, 0, PLUS
, code1
, scale
/ 2);
2188 record_address_regs (mode
, arg0
, 1, PLUS
, code1
, scale
/ 2);
2189 record_address_regs (mode
, arg1
, 0, PLUS
, code0
, scale
/ 2);
2190 record_address_regs (mode
, arg1
, 1, PLUS
, code0
, scale
/ 2);
2195 /* Double the importance of a pseudo register that is incremented
2196 or decremented, since it would take two extra insns
2197 if it ends up in the wrong place. */
2200 record_address_regs (mode
, XEXP (x
, 0), 0, code
,
2201 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
2202 if (REG_P (XEXP (XEXP (x
, 1), 1)))
2203 record_address_regs (mode
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
2211 /* Double the importance of a pseudo register that is incremented
2212 or decremented, since it would take two extra insns
2213 if it ends up in the wrong place. If the operand is a pseudo,
2214 show it is being used in an INC_DEC context. */
2216 #ifdef FORBIDDEN_INC_DEC_CLASSES
2217 if (REG_P (XEXP (x
, 0))
2218 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
2219 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
2222 record_address_regs (mode
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
2227 struct costs
*pp
= &costs
[REGNO (x
)];
2230 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
, class, 1) * scale
) / 2;
2232 if (!move_cost
[Pmode
])
2233 init_move_cost (Pmode
);
2234 for (i
= 0; i
< N_REG_CLASSES
; i
++)
2235 pp
->cost
[i
] += (may_move_in_cost
[Pmode
][i
][(int) class] * scale
) / 2;
2241 const char *fmt
= GET_RTX_FORMAT (code
);
2243 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2245 record_address_regs (mode
, XEXP (x
, i
), context
, code
, SCRATCH
,
2251 #ifdef FORBIDDEN_INC_DEC_CLASSES
2253 /* Return 1 if REG is valid as an auto-increment memory reference
2254 to an object of MODE. */
2257 auto_inc_dec_reg_p (rtx reg
, enum machine_mode mode
)
2259 if (HAVE_POST_INCREMENT
2260 && memory_address_p (mode
, gen_rtx_POST_INC (Pmode
, reg
)))
2263 if (HAVE_POST_DECREMENT
2264 && memory_address_p (mode
, gen_rtx_POST_DEC (Pmode
, reg
)))
2267 if (HAVE_PRE_INCREMENT
2268 && memory_address_p (mode
, gen_rtx_PRE_INC (Pmode
, reg
)))
2271 if (HAVE_PRE_DECREMENT
2272 && memory_address_p (mode
, gen_rtx_PRE_DEC (Pmode
, reg
)))
2280 /* Allocate space for reg info. */
2282 allocate_reg_info (void)
2284 int size
= max_reg_num ();
2286 gcc_assert (! reg_pref
&& ! reg_renumber
);
2287 reg_renumber
= XNEWVEC (short, size
);
2288 reg_pref
= XCNEWVEC (struct reg_pref
, size
);
2289 memset (reg_renumber
, -1, size
* sizeof (short));
2293 /* Resize reg info. The new elements will be uninitialized. */
2295 resize_reg_info (void)
2297 int size
= max_reg_num ();
2299 gcc_assert (reg_pref
&& reg_renumber
);
2300 reg_renumber
= XRESIZEVEC (short, reg_renumber
, size
);
2301 reg_pref
= XRESIZEVEC (struct reg_pref
, reg_pref
, size
);
2305 /* Free up the space allocated by allocate_reg_info. */
2307 free_reg_info (void)
2317 free (reg_renumber
);
2318 reg_renumber
= NULL
;
2325 /* Set up preferred and alternate classes for REGNO as PREFCLASS and
2328 setup_reg_classes (int regno
,
2329 enum reg_class prefclass
, enum reg_class altclass
)
2331 if (reg_pref
== NULL
)
2333 reg_pref
[regno
].prefclass
= prefclass
;
2334 reg_pref
[regno
].altclass
= altclass
;
2338 /* This is the `regscan' pass of the compiler, run just before cse and
2339 again just before loop. It finds the first and last use of each
2343 reg_scan (rtx f
, unsigned int nregs ATTRIBUTE_UNUSED
)
2347 timevar_push (TV_REG_SCAN
);
2349 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
2352 reg_scan_mark_refs (PATTERN (insn
), insn
);
2353 if (REG_NOTES (insn
))
2354 reg_scan_mark_refs (REG_NOTES (insn
), insn
);
2357 timevar_pop (TV_REG_SCAN
);
2361 /* X is the expression to scan. INSN is the insn it appears in.
2362 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2363 We should only record information for REGs with numbers
2364 greater than or equal to MIN_REGNO. */
2366 extern struct tree_opt_pass
*current_pass
;
2369 reg_scan_mark_refs (rtx x
, rtx insn
)
2377 code
= GET_CODE (x
);
2396 reg_scan_mark_refs (XEXP (x
, 0), insn
);
2398 reg_scan_mark_refs (XEXP (x
, 1), insn
);
2403 reg_scan_mark_refs (XEXP (x
, 1), insn
);
2407 if (MEM_P (XEXP (x
, 0)))
2408 reg_scan_mark_refs (XEXP (XEXP (x
, 0), 0), insn
);
2412 /* Count a set of the destination if it is a register. */
2413 for (dest
= SET_DEST (x
);
2414 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
2415 || GET_CODE (dest
) == ZERO_EXTEND
;
2416 dest
= XEXP (dest
, 0))
2419 /* If this is setting a pseudo from another pseudo or the sum of a
2420 pseudo and a constant integer and the other pseudo is known to be
2421 a pointer, set the destination to be a pointer as well.
2423 Likewise if it is setting the destination from an address or from a
2424 value equivalent to an address or to the sum of an address and
2427 But don't do any of this if the pseudo corresponds to a user
2428 variable since it should have already been set as a pointer based
2431 if (REG_P (SET_DEST (x
))
2432 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
2433 /* If the destination pseudo is set more than once, then other
2434 sets might not be to a pointer value (consider access to a
2435 union in two threads of control in the presence of global
2436 optimizations). So only set REG_POINTER on the destination
2437 pseudo if this is the only set of that pseudo. */
2438 && DF_REG_DEF_COUNT (REGNO (SET_DEST (x
))) == 1
2439 && ! REG_USERVAR_P (SET_DEST (x
))
2440 && ! REG_POINTER (SET_DEST (x
))
2441 && ((REG_P (SET_SRC (x
))
2442 && REG_POINTER (SET_SRC (x
)))
2443 || ((GET_CODE (SET_SRC (x
)) == PLUS
2444 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2445 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2446 && REG_P (XEXP (SET_SRC (x
), 0))
2447 && REG_POINTER (XEXP (SET_SRC (x
), 0)))
2448 || GET_CODE (SET_SRC (x
)) == CONST
2449 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
2450 || GET_CODE (SET_SRC (x
)) == LABEL_REF
2451 || (GET_CODE (SET_SRC (x
)) == HIGH
2452 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
2453 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
2454 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
2455 || ((GET_CODE (SET_SRC (x
)) == PLUS
2456 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2457 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
2458 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
2459 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
2460 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
2461 && (GET_CODE (XEXP (note
, 0)) == CONST
2462 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
2463 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
2464 REG_POINTER (SET_DEST (x
)) = 1;
2466 /* If this is setting a register from a register or from a simple
2467 conversion of a register, propagate REG_EXPR. */
2468 if (REG_P (dest
) && !REG_ATTRS (dest
))
2470 rtx src
= SET_SRC (x
);
2472 while (GET_CODE (src
) == SIGN_EXTEND
2473 || GET_CODE (src
) == ZERO_EXTEND
2474 || GET_CODE (src
) == TRUNCATE
2475 || (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)))
2476 src
= XEXP (src
, 0);
2478 set_reg_attrs_from_value (dest
, src
);
2481 /* ... fall through ... */
2485 const char *fmt
= GET_RTX_FORMAT (code
);
2487 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2490 reg_scan_mark_refs (XEXP (x
, i
), insn
);
2491 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
2494 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2495 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
);
2502 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2506 reg_class_subset_p (enum reg_class c1
, enum reg_class c2
)
2510 || hard_reg_set_subset_p (reg_class_contents
[(int) c1
],
2511 reg_class_contents
[(int) c2
]));
2514 /* Return nonzero if there is a register that is in both C1 and C2. */
2517 reg_classes_intersect_p (enum reg_class c1
, enum reg_class c2
)
2522 || hard_reg_set_intersect_p (reg_class_contents
[(int) c1
],
2523 reg_class_contents
[(int) c2
]));
2526 #ifdef CANNOT_CHANGE_MODE_CLASS
2528 struct subregs_of_mode_node
2531 unsigned char modes
[MAX_MACHINE_MODE
];
2534 static htab_t subregs_of_mode
;
2537 som_hash (const void *x
)
2539 const struct subregs_of_mode_node
*a
= x
;
2544 som_eq (const void *x
, const void *y
)
2546 const struct subregs_of_mode_node
*a
= x
;
2547 const struct subregs_of_mode_node
*b
= y
;
2548 return a
->block
== b
->block
;
2553 record_subregs_of_mode (rtx subreg
)
2555 struct subregs_of_mode_node dummy
, *node
;
2556 enum machine_mode mode
;
2560 if (!REG_P (SUBREG_REG (subreg
)))
2563 regno
= REGNO (SUBREG_REG (subreg
));
2564 mode
= GET_MODE (subreg
);
2566 if (regno
< FIRST_PSEUDO_REGISTER
)
2569 dummy
.block
= regno
& -8;
2570 slot
= htab_find_slot_with_hash (subregs_of_mode
, &dummy
,
2571 dummy
.block
, INSERT
);
2575 node
= XCNEW (struct subregs_of_mode_node
);
2576 node
->block
= regno
& -8;
2580 node
->modes
[mode
] |= 1 << (regno
& 7);
2584 /* Call record_subregs_of_mode for all the subregs in X. */
2587 find_subregs_of_mode (rtx x
)
2589 enum rtx_code code
= GET_CODE (x
);
2590 const char * const fmt
= GET_RTX_FORMAT (code
);
2594 record_subregs_of_mode (x
);
2596 /* Time for some deep diving. */
2597 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2600 find_subregs_of_mode (XEXP (x
, i
));
2601 else if (fmt
[i
] == 'E')
2604 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2605 find_subregs_of_mode (XVECEXP (x
, i
, j
));
2611 init_subregs_of_mode (void)
2616 if (subregs_of_mode
)
2617 htab_empty (subregs_of_mode
);
2619 subregs_of_mode
= htab_create (100, som_hash
, som_eq
, free
);
2622 FOR_BB_INSNS (bb
, insn
)
2624 find_subregs_of_mode (PATTERN (insn
));
2630 /* Set bits in *USED which correspond to registers which can't change
2631 their mode from FROM to any mode in which REGNO was encountered. */
2634 cannot_change_mode_set_regs (HARD_REG_SET
*used
, enum machine_mode from
,
2637 struct subregs_of_mode_node dummy
, *node
;
2638 enum machine_mode to
;
2642 gcc_assert (subregs_of_mode
);
2643 dummy
.block
= regno
& -8;
2644 node
= htab_find_with_hash (subregs_of_mode
, &dummy
, dummy
.block
);
2648 mask
= 1 << (regno
& 7);
2649 for (to
= VOIDmode
; to
< NUM_MACHINE_MODES
; to
++)
2650 if (node
->modes
[to
] & mask
)
2651 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2652 if (!TEST_HARD_REG_BIT (*used
, i
)
2653 && REG_CANNOT_CHANGE_MODE_P (i
, from
, to
))
2654 SET_HARD_REG_BIT (*used
, i
);
2657 /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM
2661 invalid_mode_change_p (unsigned int regno
,
2662 enum reg_class
class ATTRIBUTE_UNUSED
,
2663 enum machine_mode from
)
2665 struct subregs_of_mode_node dummy
, *node
;
2666 enum machine_mode to
;
2669 gcc_assert (subregs_of_mode
);
2670 dummy
.block
= regno
& -8;
2671 node
= htab_find_with_hash (subregs_of_mode
, &dummy
, dummy
.block
);
2675 mask
= 1 << (regno
& 7);
2676 for (to
= VOIDmode
; to
< NUM_MACHINE_MODES
; to
++)
2677 if (node
->modes
[to
] & mask
)
2678 if (CANNOT_CHANGE_MODE_CLASS (from
, to
, class))
2685 finish_subregs_of_mode (void)
2687 htab_delete (subregs_of_mode
);
2688 subregs_of_mode
= 0;
2693 init_subregs_of_mode (void)
2698 finish_subregs_of_mode (void)
2703 #endif /* CANNOT_CHANGE_MODE_CLASS */
2706 gate_subregs_of_mode_init (void)
2708 #ifdef CANNOT_CHANGE_MODE_CLASS
2715 struct tree_opt_pass pass_subregs_of_mode_init
=
2717 "subregs_of_mode_init", /* name */
2718 gate_subregs_of_mode_init
, /* gate */
2719 init_subregs_of_mode
, /* execute */
2722 0, /* static_pass_number */
2724 0, /* properties_required */
2725 0, /* properties_provided */
2726 0, /* properties_destroyed */
2727 0, /* todo_flags_start */
2728 0, /* todo_flags_finish */
2732 struct tree_opt_pass pass_subregs_of_mode_finish
=
2734 "subregs_of_mode_finish", /* name */
2735 gate_subregs_of_mode_init
, /* gate */
2736 finish_subregs_of_mode
, /* execute */
2739 0, /* static_pass_number */
2741 0, /* properties_required */
2742 0, /* properties_provided */
2743 0, /* properties_destroyed */
2744 0, /* todo_flags_start */
2745 0, /* todo_flags_finish */
2751 #include "gt-regclass.h"