Merge -r 127928:132243 from trunk
[official-gcc.git] / gcc / config / spu / spu_mfcio.h
blob7653c8d5b392946ed8ec314c9346b2e9b39f2f88
1 /* Copyright (C) 2006 Free Software Foundation, Inc.
3 This file is free software; you can redistribute it and/or modify it under
4 the terms of the GNU General Public License as published by the Free
5 Software Foundation; either version 2 of the License, or (at your option)
6 any later version.
8 This file is distributed in the hope that it will be useful, but WITHOUT
9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 for more details.
13 You should have received a copy of the GNU General Public License
14 along with this file; see the file COPYING. If not, write to the Free
15 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
16 02110-1301, USA. */
18 /* As a special exception, if you include this header file into source files
19 compiled by GCC, this header file does not by itself cause the resulting
20 executable to be covered by the GNU General Public License. This exception
21 does not however invalidate any other reasons why the executable file might be
22 covered by the GNU General Public License. */
24 #ifndef __SPU_MFCIO_H__
25 #define __SPU_MFCIO_H__ 1
27 #include <spu_intrinsics.h>
28 #ifdef __IN_LIBGCC2
29 typedef unsigned long long uint64_t;
30 #else
31 #include <stdint.h>
32 #endif
35 /****************************************************************/
36 /* DMA list element structure*/
37 /****************************************************************/
39 #ifdef __GNUC__
40 __extension__
41 #endif
42 typedef struct mfc_list_element {
43 uint64_t notify : 1; /** Stall-and-notify bit */
44 uint64_t reserved : 16;
45 uint64_t size : 15; /** Transfer size */
46 uint64_t eal : 32; /** Lower word of effective address */
47 } mfc_list_element_t;
49 /****************************************************************/
50 /* DMA max/min size definitions. */
51 /****************************************************************/
53 #define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
54 #define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
56 #define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
57 #define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
59 #define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
60 #define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
62 #define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
63 #define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
65 /****************************************************************/
66 /* MFC DMA Command flags which identify classes of operations. */
67 /****************************************************************/
68 /* Note: These flags may be used in conjunction with the base command types
69 (i.e. MFC_PUT_CMD, MFC_PUTR_CMD, MFC_GET_CMD, and MFC_SNDSIG_CMD)
70 to construct the various command permutations.
73 #define MFC_BARRIER_ENABLE 0x0001
74 #define MFC_FENCE_ENABLE 0x0002
75 #define MFC_LIST_ENABLE 0x0004 /* SPU Only */
76 #define MFC_START_ENABLE 0x0008 /* PU Only */
77 #define MFC_RESULT_ENABLE 0x0010
79 /****************************************************************/
80 /* MFC DMA Put Commands */
81 /****************************************************************/
83 #define MFC_PUT_CMD 0x0020
84 #define MFC_PUTS_CMD 0x0028 /* PU Only */
85 #define MFC_PUTR_CMD 0x0030
86 #define MFC_PUTF_CMD 0x0022
87 #define MFC_PUTB_CMD 0x0021
88 #define MFC_PUTFS_CMD 0x002A /* PU Only */
89 #define MFC_PUTBS_CMD 0x0029 /* PU Only */
90 #define MFC_PUTRF_CMD 0x0032
91 #define MFC_PUTRB_CMD 0x0031
92 #define MFC_PUTL_CMD 0x0024 /* SPU Only */
93 #define MFC_PUTRL_CMD 0x0034 /* SPU Only */
94 #define MFC_PUTLF_CMD 0x0026 /* SPU Only */
95 #define MFC_PUTLB_CMD 0x0025 /* SPU Only */
96 #define MFC_PUTRLF_CMD 0x0036 /* SPU Only */
97 #define MFC_PUTRLB_CMD 0x0035 /* SPU Only */
99 /****************************************************************/
100 /* MFC DMA Get Commands */
101 /****************************************************************/
103 #define MFC_GET_CMD 0x0040
104 #define MFC_GETS_CMD 0x0048 /* PU Only */
105 #define MFC_GETF_CMD 0x0042
106 #define MFC_GETB_CMD 0x0041
107 #define MFC_GETFS_CMD 0x004A /* PU Only */
108 #define MFC_GETBS_CMD 0x0049 /* PU Only */
109 #define MFC_GETL_CMD 0x0044 /* SPU Only */
110 #define MFC_GETLF_CMD 0x0046 /* SPU Only */
111 #define MFC_GETLB_CMD 0x0045 /* SPU Only */
113 /****************************************************************/
114 /* MFC Synchronization Commands */
115 /****************************************************************/
117 #define MFC_SNDSIG_CMD 0x00A0
118 #define MFC_SNDSIGB_CMD 0x00A1
119 #define MFC_SNDSIGF_CMD 0x00A2
120 #define MFC_BARRIER_CMD 0x00C0
121 #define MFC_EIEIO_CMD 0x00C8
122 #define MFC_SYNC_CMD 0x00CC
124 /****************************************************************/
125 /* MFC Atomic Commands */
126 /****************************************************************/
128 #define MFC_GETLLAR_CMD 0x00D0 /* SPU Only */
129 #define MFC_PUTLLC_CMD 0x00B4 /* SPU Only */
130 #define MFC_PUTLLUC_CMD 0x00B0 /* SPU Only */
131 #define MFC_PUTQLLUC_CMD 0x00B8 /* SPU Only */
133 /****************************************************************/
134 /* Channel Defines */
135 /****************************************************************/
137 /* Events Defines for channels
138 * 0 (SPU_RdEventStat),
139 * 1 (SPU_WrEventMask), and
140 * 2 (SPU_WrEventAck).
142 #define MFC_TAG_STATUS_UPDATE_EVENT 0x00000001
143 #define MFC_LIST_STALL_NOTIFY_EVENT 0x00000002
144 #define MFC_COMMAND_QUEUE_AVAILABLE_EVENT 0x00000008
145 #define MFC_IN_MBOX_AVAILABLE_EVENT 0x00000010
146 #define MFC_DECREMENTER_EVENT 0x00000020
147 #define MFC_OUT_INTR_MBOX_AVAILABLE_EVENT 0x00000040
148 #define MFC_OUT_MBOX_AVAILABLE_EVENT 0x00000080
149 #define MFC_SIGNAL_NOTIFY_2_EVENT 0x00000100
150 #define MFC_SIGNAL_NOTIFY_1_EVENT 0x00000200
151 #define MFC_LLR_LOST_EVENT 0x00000400
152 #define MFC_PRIV_ATTN_EVENT 0x00000800
153 #define MFC_MULTI_SRC_SYNC_EVENT 0x00001000
155 /* Tag Status Update defines for channel 23 (MFC_WrTagUpdate) */
156 #define MFC_TAG_UPDATE_IMMEDIATE 0x0
157 #define MFC_TAG_UPDATE_ANY 0x1
158 #define MFC_TAG_UPDATE_ALL 0x2
160 /* Atomic Command Status defines for channel 27 (MFC_RdAtomicStat) */
161 #define MFC_PUTLLC_STATUS 0x00000001
162 #define MFC_PUTLLUC_STATUS 0x00000002
163 #define MFC_GETLLAR_STATUS 0x00000004
166 /****************************************************************/
167 /* Definitions for constructing a 32-bit command word */
168 /* including the transfer and replacement class id and the */
169 /* command opcode. */
170 /****************************************************************/
171 #define MFC_CMD_WORD(_tid, _rid, _cmd) (((_tid)<<24)|((_rid)<<16)|(_cmd))
174 /* Addressing Utilities */
175 #define mfc_ea2h(ea) (unsigned int)((unsigned long long)(ea)>>32)
176 #define mfc_ea2l(ea) (unsigned int)(ea)
177 #define mfc_hl2ea(h,l) si_to_ullong(si_selb(si_from_uint(h),\
178 si_rotqbyi(si_from_uint(l), -4),\
179 si_fsmbi(0x0f0f)))
180 #define mfc_ceil128(v) (((v) + 127) & ~127)
182 /* MFC DMA */
183 #define mfc_put( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUT_CMD))
184 #define mfc_putf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTF_CMD))
185 #define mfc_putb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTB_CMD))
186 #define mfc_get( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GET_CMD))
187 #define mfc_getf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETF_CMD))
188 #define mfc_getb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETB_CMD))
190 /* MFC list DMA */
191 #define mfc_putl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTL_CMD))
192 #define mfc_putlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLF_CMD))
193 #define mfc_putlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLB_CMD))
194 #define mfc_getl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETL_CMD))
195 #define mfc_getlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLF_CMD))
196 #define mfc_getlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLB_CMD))
198 /* MFC Atomic Update DMA */
199 #define mfc_getllar( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_GETLLAR_CMD))
200 #define mfc_putllc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLC_CMD))
201 #define mfc_putlluc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLUC_CMD))
202 #define mfc_putqlluc(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128,tag,MFC_CMD_WORD(tid,rid,MFC_PUTQLLUC_CMD))
204 /* MFC Synchronization Commands */
205 #define mfc_sndsig( ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIG_CMD))
206 #define mfc_sndsigb(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGB_CMD))
207 #define mfc_sndsigf(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGF_CMD))
208 #define mfc_barrier(tag) spu_mfcdma32(0,0,0,tag,MFC_BARRIER_CMD)
209 #define mfc_eieio(tag,tid,rid) spu_mfcdma32(0,0,0,tag,MFC_CMD_WORD(tid,rid,MFC_EIEIO_CMD))
210 #define mfc_sync(tag) spu_mfcdma32(0,0,0,tag,MFC_SYNC_CMD)
212 /* DMA Queue */
213 #define mfc_stat_cmd_queue() spu_readchcnt(MFC_Cmd)
215 /* MFC Tag-Status */
216 #define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
217 #define mfc_read_tag_mask() spu_readch(MFC_RdTagMask)
219 #define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
220 #define mfc_write_tag_update_immediate() mfc_write_tag_update(MFC_TAG_UPDATE_IMMEDIATE)
221 #define mfc_write_tag_update_any() mfc_write_tag_update(MFC_TAG_UPDATE_ANY)
222 #define mfc_write_tag_update_all() mfc_write_tag_update(MFC_TAG_UPDATE_ALL)
223 #define mfc_stat_tag_update() spu_readchcnt(MFC_WrTagUpdate)
225 #define mfc_read_tag_status() spu_readch(MFC_RdTagStat)
226 #define mfc_read_tag_status_immediate() (mfc_write_tag_update_immediate(), mfc_read_tag_status())
227 #define mfc_read_tag_status_any() (mfc_write_tag_update_any(), mfc_read_tag_status())
228 #define mfc_read_tag_status_all() (mfc_write_tag_update_all(), mfc_read_tag_status())
229 #define mfc_stat_tag_status() spu_readchcnt(MFC_RdTagStat)
231 /* MFC List Stall-and-Notify Tag */
232 #define mfc_read_list_stall_status() spu_readch(MFC_RdListStallStat)
233 #define mfc_stat_list_stall_status() spu_readchcnt(MFC_RdListStallStat)
234 #define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
236 /* Atomic DMA */
237 #define mfc_read_atomic_status() spu_readch(MFC_RdAtomicStat)
238 #define mfc_stat_atomic_status() spu_readchcnt(MFC_RdAtomicStat)
240 /* MFC Multi-source Synchronization */
241 #define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
242 #define mfc_stat_multi_src_sync_request() spu_readchcnt(MFC_WrMSSyncReq)
244 /* SPU Signal */
245 #define spu_read_signal1() spu_readch(SPU_RdSigNotify1)
246 #define spu_stat_signal1() spu_readchcnt(SPU_RdSigNotify1)
247 #define spu_read_signal2() spu_readch(SPU_RdSigNotify2)
248 #define spu_stat_signal2() spu_readchcnt(SPU_RdSigNotify2)
250 /* SPU/PPE Mailbox */
251 #define spu_read_in_mbox() spu_readch(SPU_RdInMbox)
252 #define spu_stat_in_mbox() spu_readchcnt(SPU_RdInMbox)
253 #define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
254 #define spu_stat_out_mbox() spu_readchcnt(SPU_WrOutMbox)
255 #define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
256 #define spu_stat_out_intr_mbox() spu_readchcnt(SPU_WrOutIntrMbox)
258 /* SPU Decrementer */
259 #define spu_read_decrementer() spu_readch(SPU_RdDec)
260 #define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
262 /* SPU Event */
263 #define spu_read_event_status() spu_readch(SPU_RdEventStat)
264 #define spu_stat_event_status() spu_readchcnt(SPU_RdEventStat)
265 #define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
266 #define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
267 #define spu_read_event_mask() spu_readch(SPU_RdEventMask)
269 /* SPU State Management */
270 #define spu_read_machine_status() spu_readch(SPU_MachStat)
271 #define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
272 #define spu_read_srr0() spu_readch(SPU_RdSRR0)
275 /* MFC Tag Manager */
277 #define MFC_TAG_INVALID 0xFFFFFFFF
278 #define MFC_TAG_VALID 0x00000000
280 #define mfc_tag_reserve() \
281 __mfc_tag_reserve()
282 #define mfc_tag_release(tag) \
283 __mfc_tag_release((tag))
284 #define mfc_multi_tag_reserve(nr_tags) \
285 __mfc_multi_tag_reserve((nr_tags))
286 #define mfc_multi_tag_release(tag, nr_tags) \
287 __mfc_multi_tag_release((tag),(nr_tags))
289 extern unsigned int __mfc_tag_reserve (void);
290 extern unsigned int __mfc_tag_release (unsigned int);
291 extern unsigned int __mfc_multi_tag_reserve (unsigned int);
292 extern unsigned int __mfc_multi_tag_release (unsigned int, unsigned int);
294 #endif /* __SPU_MFCIO_H__ */