gcc/config/pa/pa64-regs.h

   1 /* Configuration for GCC-compiler for PA-RISC.
   2    Copyright (C) 1999, 2000, 2003, 2004, 2007 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 /* Standard register usage.
  21
  22    It is safe to refer to actual register numbers in this file.  */
  23
  24 /* Number of actual hardware registers.
  25    The hardware registers are assigned numbers for the compiler
  26    from 0 to just below FIRST_PSEUDO_REGISTER.
  27    All registers that the compiler knows about must be given numbers,
  28    even those that are not normally considered general registers.
  29
  30    HP-PA 2.0w has 32 fullword registers and 32 floating point
  31    registers. However, the floating point registers behave
  32    differently: the left and right halves of registers are addressable
  33    as 32-bit registers.
  34
  35    Due to limitations within GCC itself, we do not expose the left/right
  36    half addressability when in wide mode.  This is not a major performance
  37    issue as using the halves independently triggers false dependency stalls
  38    anyway.  */
  39
  40 #define FIRST_PSEUDO_REGISTER 61  /* 32 general regs + 28 fp regs +
  41                                      + 1 shift reg */
  42
  43 /* 1 for registers that have pervasive standard uses
  44    and are not available for the register allocator.
  45
  46    On the HP-PA, these are:
  47    Reg 0        = 0 (hardware). However, 0 is used for condition code,
  48                   so is not fixed.
  49    Reg 1        = ADDIL target/Temporary (hardware).
  50    Reg 2        = Return Pointer
  51    Reg 3        = Frame Pointer
  52    Reg 4        = Frame Pointer (>8k varying frame with HP compilers only)
  53    Reg 4-18     = Preserved Registers
  54    Reg 19       = Linkage Table Register in HPUX 8.0 shared library scheme.
  55    Reg 20-22    = Temporary Registers
  56    Reg 23-26    = Temporary/Parameter Registers
  57    Reg 27       = Global Data Pointer (hp)
  58    Reg 28       = Temporary/Return Value register
  59    Reg 29       = Temporary/Static Chain/Return Value register #2
  60    Reg 30       = stack pointer
  61    Reg 31       = Temporary/Millicode Return Pointer (hp)
  62
  63    Freg 0-3     = Status Registers      -- Not known to the compiler.
  64    Freg 4-7     = Arguments/Return Value
  65    Freg 8-11    = Temporary Registers
  66    Freg 12-21   = Preserved Registers
  67    Freg 22-31 = Temporary Registers
  68
  69 */
  70
  71 #define FIXED_REGISTERS  \
  72  {0, 0, 0, 0, 0, 0, 0, 0, \
  73   0, 0, 0, 0, 0, 0, 0, 0, \
  74   0, 0, 0, 0, 0, 0, 0, 0, \
  75   0, 0, 0, 1, 0, 0, 1, 0, \
  76   /* fp registers */      \
  77   0, 0, 0, 0, 0, 0, 0, 0, \
  78   0, 0, 0, 0, 0, 0, 0, 0, \
  79   0, 0, 0, 0, 0, 0, 0, 0, \
  80   0, 0, 0, 0,             \
  81   /* shift register */    \
  82   0}
  83
  84 /* 1 for registers not available across function calls.
  85    These must include the FIXED_REGISTERS and also any
  86    registers that can be used without being saved.
  87    The latter must include the registers where values are returned
  88    and the register where structure-value addresses are passed.
  89    Aside from that, you can include as many other registers as you like.  */
  90 #define CALL_USED_REGISTERS  \
  91  {1, 1, 1, 0, 0, 0, 0, 0, \
  92   0, 0, 0, 0, 0, 0, 0, 0, \
  93   0, 0, 0, 1, 1, 1, 1, 1, \
  94   1, 1, 1, 1, 1, 1, 1, 1, \
  95   /* fp registers */      \
  96   1, 1, 1, 1, 1, 1, 1, 1, \
  97   0, 0, 0, 0, 0, 0, 0, 0, \
  98   0, 0, 1, 1, 1, 1, 1, 1, \
  99   1, 1, 1, 1,             \
 100   /* shift register */    \
 101   1}
 102
 103 #define CONDITIONAL_REGISTER_USAGE \
 104 {                                               \
 105   int i;                                        \
 106   if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
 107     {                                           \
 108       for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)\
 109         fixed_regs[i] = call_used_regs[i] = 1;  \
 110     }                                           \
 111   if (flag_pic)                                 \
 112     fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;    \
 113 }
 114
 115 /* Allocate the call used registers first.  This should minimize
 116    the number of registers that need to be saved (as call used
 117    registers will generally not be allocated across a call).
 118
 119    Experimentation has shown slightly better results by allocating
 120    FP registers first.  We allocate the caller-saved registers more
 121    or less in reverse order to their allocation as arguments.  */
 122
 123 #define REG_ALLOC_ORDER \
 124  {                                      \
 125   /* caller-saved fp regs.  */          \
 126   50, 51, 52, 53, 54, 55, 56, 57,       \
 127   58, 59, 39, 38, 37, 36, 35, 34,       \
 128   33, 32,                               \
 129   /* caller-saved general regs.  */     \
 130   28, 31, 19, 20, 21, 22, 23, 24,       \
 131   25, 26, 29,  2,                       \
 132   /* callee-saved fp regs.  */          \
 133   40, 41, 42, 43, 44, 45, 46, 47,       \
 134   48, 49,                               \
 135   /* callee-saved general regs.  */     \
 136    3,  4,  5,  6,  7,  8,  9, 10,       \
 137   11, 12, 13, 14, 15, 16, 17, 18,       \
 138   /* special registers.  */             \
 139    1, 27, 30,  0, 60}
 140
 141
 142 /* Return number of consecutive hard regs needed starting at reg REGNO
 143    to hold something of mode MODE.
 144    This is ordinarily the length in words of a value of mode MODE
 145    but can be less for certain modes in special long registers.
 146
 147    For PA64, GPRs and FPRs hold 64 bits worth.  We ignore the 32-bit
 148    addressability of the FPRs and pretend each register holds precisely
 149    WORD_SIZE bits.  Note that SCmode values are placed in a single FPR.
 150    Thus, any patterns defined to operate on these values would have to
 151    use the 32-bit addressability of the FPR registers.  */
 152 #define HARD_REGNO_NREGS(REGNO, MODE)                                   \
 153   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 154
 155 /* These are the valid FP modes.  */
 156 #define VALID_FP_MODE_P(MODE)                                           \
 157   ((MODE) == SFmode || (MODE) == DFmode                                 \
 158    || (MODE) == SCmode || (MODE) == DCmode                              \
 159    || (MODE) == SImode || (MODE) == DImode)
 160
 161 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
 162    On the HP-PA, the cpu registers can hold any mode.  We
 163    force this to be an even register is it cannot hold the full mode.  */
 164 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
 165   ((REGNO) == 0                                                         \
 166    ? (MODE) == CCmode || (MODE) == CCFPmode                             \
 167    /* Make wide modes be in aligned registers.  */                      \
 168    : FP_REGNO_P (REGNO)                                                 \
 169      ? (VALID_FP_MODE_P (MODE)                                          \
 170         && (GET_MODE_SIZE (MODE) <= 8                                   \
 171             || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 1) == 0)       \
 172             || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 3) == 0)))     \
 173    : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD                            \
 174       || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD                    \
 175           && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28))  \
 176       || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD                    \
 177           && ((REGNO) & 3) == 3 && (REGNO) <= 23)))
 178
 179 /* How to renumber registers for dbx and gdb.
 180
 181    Registers 0  - 31 remain unchanged.
 182
 183    Registers 32 - 59 are mapped to 72, 74, 76 ...
 184
 185    Register 60 is mapped to 32.  */
 186 #define DBX_REGISTER_NUMBER(REGNO) \
 187   ((REGNO) <= 31 ? (REGNO) : ((REGNO) < 60 ? (REGNO - 32) * 2 + 72 : 32))
 188
 189 /* We must not use the DBX register numbers for the DWARF 2 CFA column
 190    numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
 191    Instead use the identity mapping.  */
 192 #define DWARF_FRAME_REGNUM(REG) REG
 193
 194 /* Define the classes of registers for register constraints in the
 195    machine description.  Also define ranges of constants.
 196
 197    One of the classes must always be named ALL_REGS and include all hard regs.
 198    If there is more than one class, another class must be named NO_REGS
 199    and contain no registers.
 200
 201    The name GENERAL_REGS must be the name of a class (or an alias for
 202    another name such as ALL_REGS).  This is the class of registers
 203    that is allowed by "g" or "r" in a register constraint.
 204    Also, registers outside this class are allocated only when
 205    instructions express preferences for them.
 206
 207    The classes must be numbered in nondecreasing order; that is,
 208    a larger-numbered class must never be contained completely
 209    in a smaller-numbered class.
 210
 211    For any two classes, it is very desirable that there be another
 212    class that represents their union.  */
 213
 214   /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
 215      1.1 fp regs, and the high 1.1 fp regs, to which the operands of
 216      fmpyadd and fmpysub are restricted.  */
 217
 218 enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
 219                  GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
 220
 221 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 222
 223 /* Give names of register classes as strings for dump file.  */
 224
 225 #define REG_CLASS_NAMES \
 226   {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
 227    "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
 228
 229 /* Define which registers fit in which classes.
 230    This is an initializer for a vector of HARD_REG_SET
 231    of length N_REG_CLASSES. Register 0, the "condition code" register,
 232    is in no class.  */
 233
 234 #define REG_CLASS_CONTENTS      \
 235  {{0x00000000, 0x00000000},     /* NO_REGS */                   \
 236   {0x00000002, 0x00000000},     /* R1_REGS */                   \
 237   {0xfffffffe, 0x00000000},     /* GENERAL_REGS */              \
 238   {0x00000000, 0x00000000},     /* FPUPPER_REGS */                      \
 239   {0x00000000, 0x0fffffff},     /* FP_REGS */                   \
 240   {0xfffffffe, 0x0fffffff},     /* GENERAL_OR_FP_REGS */        \
 241   {0x00000000, 0x10000000},     /* SHIFT_REGS */                \
 242   {0xfffffffe, 0x1fffffff}}     /* ALL_REGS */
 243
 244 /* Defines invalid mode changes.  */
 245
 246 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
 247   pa_cannot_change_mode_class (FROM, TO, CLASS)
 248
 249 /* Return the class number of the smallest class containing
 250    reg number REGNO.  This could be a conditional expression
 251    or could index an array.  */
 252
 253 #define REGNO_REG_CLASS(REGNO)                                          \
 254   ((REGNO) == 0 ? NO_REGS                                               \
 255    : (REGNO) == 1 ? R1_REGS                                             \
 256    : (REGNO) < 32 ? GENERAL_REGS                                        \
 257    : (REGNO) < 60 ? FP_REGS                                             \
 258    : SHIFT_REGS)
 259
 260 /* Return the maximum number of consecutive registers
 261    needed to represent mode MODE in a register of class CLASS.  */
 262 #define CLASS_MAX_NREGS(CLASS, MODE)                                    \
 263   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 264
 265 /* 1 if N is a possible register number for function argument passing.  */
 266
 267 #define FUNCTION_ARG_REGNO_P(N) \
 268   ((((N) >= 19) && (N) <= 26) \
 269    || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39))
 270
 271 /* How to refer to registers in assembler output.
 272    This sequence is indexed by compiler's hard-register-number (see above).  */
 273
 274 #define REGISTER_NAMES \
 275 {"%r0",   "%r1",    "%r2",   "%r3",    "%r4",   "%r5",    "%r6",   "%r7",    \
 276  "%r8",   "%r9",    "%r10",  "%r11",   "%r12",  "%r13",   "%r14",  "%r15",   \
 277  "%r16",  "%r17",   "%r18",  "%r19",   "%r20",  "%r21",   "%r22",  "%r23",   \
 278  "%r24",  "%r25",   "%r26",  "%r27",   "%r28",  "%r29",   "%r30",  "%r31",   \
 279  "%fr4",  "%fr5",   "%fr6",  "%fr7",   "%fr8",  "%fr9",   "%fr10", "%fr11",  \
 280  "%fr12", "%fr13",  "%fr14", "%fr15",  "%fr16", "%fr17",  "%fr18", "%fr19",  \
 281  "%fr20", "%fr21",  "%fr22", "%fr23",  "%fr24", "%fr25",  "%fr26", "%fr27",  \
 282  "%fr28", "%fr29",  "%fr30", "%fr31", "SAR"}
 283
 284 #define ADDITIONAL_REGISTER_NAMES \
 285  {{"%cr11",60}}
 286
 287 #define FP_SAVED_REG_LAST 49
 288 #define FP_SAVED_REG_FIRST 40
 289 #define FP_REG_STEP 1
 290 #define FP_REG_FIRST 32
 291 #define FP_REG_LAST 59