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Merge -r 127928:132243 from trunk
[official-gcc.git] / gcc / config / mips / mips.h
blob7d94ebddd56fb08a803aea8655ecf74d2149693a
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF2_1,
45 PROCESSOR_24KF1_1,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF2_1,
48 PROCESSOR_74KF1_1,
49 PROCESSOR_74KF3_2,
50 PROCESSOR_M4K,
51 PROCESSOR_R3900,
52 PROCESSOR_R6000,
53 PROCESSOR_R4000,
54 PROCESSOR_R4100,
55 PROCESSOR_R4111,
56 PROCESSOR_R4120,
57 PROCESSOR_R4130,
58 PROCESSOR_R4300,
59 PROCESSOR_R4600,
60 PROCESSOR_R4650,
61 PROCESSOR_R5000,
62 PROCESSOR_R5400,
63 PROCESSOR_R5500,
64 PROCESSOR_R7000,
65 PROCESSOR_R8000,
66 PROCESSOR_R9000,
67 PROCESSOR_SB1,
68 PROCESSOR_SB1A,
69 PROCESSOR_SR71000,
70 PROCESSOR_MAX
71 };
72
73 /* Costs of various operations on the different architectures. */
74
75 struct mips_rtx_cost_data
76 {
77 unsigned short fp_add;
78 unsigned short fp_mult_sf;
79 unsigned short fp_mult_df;
80 unsigned short fp_div_sf;
81 unsigned short fp_div_df;
82 unsigned short int_mult_si;
83 unsigned short int_mult_di;
84 unsigned short int_div_si;
85 unsigned short int_div_di;
86 unsigned short branch_cost;
87 unsigned short memory_latency;
88 };
89
90 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
91 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
92 to work on a 64-bit machine. */
93
94 #define ABI_32 0
95 #define ABI_N32 1
96 #define ABI_64 2
97 #define ABI_EABI 3
98 #define ABI_O64 4
99
100 /* Masks that affect tuning.
101
102 PTF_AVOID_BRANCHLIKELY
103 Set if it is usually not profitable to use branch-likely instructions
104 for this target, typically because the branches are always predicted
105 taken and so incur a large overhead when not taken. */
106 #define PTF_AVOID_BRANCHLIKELY 0x1
107
108 /* Information about one recognized processor. Defined here for the
109 benefit of TARGET_CPU_CPP_BUILTINS. */
110 struct mips_cpu_info {
111 /* The 'canonical' name of the processor as far as GCC is concerned.
112 It's typically a manufacturer's prefix followed by a numerical
113 designation. It should be lowercase. */
114 const char *name;
115
116 /* The internal processor number that most closely matches this
117 entry. Several processors can have the same value, if there's no
118 difference between them from GCC's point of view. */
119 enum processor_type cpu;
120
121 /* The ISA level that the processor implements. */
122 int isa;
123
124 /* A mask of PTF_* values. */
125 unsigned int tune_flags;
126 };
127
128 /* Enumerates the setting of the -mcode-readable option. */
129 enum mips_code_readable_setting {
130 CODE_READABLE_NO,
131 CODE_READABLE_PCREL,
132 CODE_READABLE_YES
133 };
134
135 /* Macros to silence warnings about numbers being signed in traditional
136 C and unsigned in ISO C when compiled on 32-bit hosts. */
137
138 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
139 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
140 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
141
142 \f
143 /* Run-time compilation parameters selecting different hardware subsets. */
144
145 /* True if we are generating position-independent VxWorks RTP code. */
146 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
147
148 /* True if the call patterns should be split into a jalr followed by
149 an instruction to restore $gp. It is only safe to split the load
150 from the call when every use of $gp is explicit. */
151
152 #define TARGET_SPLIT_CALLS \
153 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
154
155 /* True if we're generating a form of -mabicalls in which we can use
156 operators like %hi and %lo to refer to locally-binding symbols.
157 We can only do this for -mno-shared, and only then if we can use
158 relocation operations instead of assembly macros. It isn't really
159 worth using absolute sequences for 64-bit symbols because GOT
160 accesses are so much shorter. */
161
162 #define TARGET_ABSOLUTE_ABICALLS \
163 (TARGET_ABICALLS \
164 && !TARGET_SHARED \
165 && TARGET_EXPLICIT_RELOCS \
166 && !ABI_HAS_64BIT_SYMBOLS)
167
168 /* True if we can optimize sibling calls. For simplicity, we only
169 handle cases in which call_insn_operand will reject invalid
170 sibcall addresses. There are two cases in which this isn't true:
171
172 - TARGET_MIPS16. call_insn_operand accepts constant addresses
173 but there is no direct jump instruction. It isn't worth
174 using sibling calls in this case anyway; they would usually
175 be longer than normal calls.
176
177 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
178 accepts global constants, but all sibcalls must be indirect. */
179 #define TARGET_SIBCALLS \
180 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
181
182 /* True if we need to use a global offset table to access some symbols. */
183 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
184
185 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
186 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
187
188 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
189 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
190
191 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
192 This is true for both the PIC and non-PIC VxWorks RTP modes. */
193 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
194
195 /* True if .gpword or .gpdword should be used for switch tables.
196
197 Although GAS does understand .gpdword, the SGI linker mishandles
198 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
199 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
200 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
201
202 /* Generate mips16 code */
203 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
204 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
205 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
206 /* Generate mips16e register save/restore sequences. */
207 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
208
209 /* True if we're generating a form of MIPS16 code in which general
210 text loads are allowed. */
211 #define TARGET_MIPS16_TEXT_LOADS \
212 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
213
214 /* True if we're generating a form of MIPS16 code in which PC-relative
215 loads are allowed. */
216 #define TARGET_MIPS16_PCREL_LOADS \
217 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
218
219 /* Generic ISA defines. */
220 #define ISA_MIPS1 (mips_isa == 1)
221 #define ISA_MIPS2 (mips_isa == 2)
222 #define ISA_MIPS3 (mips_isa == 3)
223 #define ISA_MIPS4 (mips_isa == 4)
224 #define ISA_MIPS32 (mips_isa == 32)
225 #define ISA_MIPS32R2 (mips_isa == 33)
226 #define ISA_MIPS64 (mips_isa == 64)
227
228 /* Architecture target defines. */
229 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
230 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
231 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
232 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
233 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
234 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
235 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
236 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
237 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
238 || mips_arch == PROCESSOR_SB1A)
239 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
240
241 /* Scheduling target defines. */
242 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
243 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
244 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
245 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
246 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
247 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
248 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
249 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
250 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
251 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
252 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
253 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
254 || mips_tune == PROCESSOR_SB1A)
255 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
256 || mips_tune == PROCESSOR_24KF2_1 \
257 || mips_tune == PROCESSOR_24KF1_1)
258 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
259 || mips_tune == PROCESSOR_74KF2_1 \
260 || mips_tune == PROCESSOR_74KF1_1 \
261 || mips_tune == PROCESSOR_74KF3_2)
262 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
263
264 /* True if the pre-reload scheduler should try to create chains of
265 multiply-add or multiply-subtract instructions. For example,
266 suppose we have:
267
268 t1 = a * b
269 t2 = t1 + c * d
270 t3 = e * f
271 t4 = t3 - g * h
272
273 t1 will have a higher priority than t2 and t3 will have a higher
274 priority than t4. However, before reload, there is no dependence
275 between t1 and t3, and they can often have similar priorities.
276 The scheduler will then tend to prefer:
277
278 t1 = a * b
279 t3 = e * f
280 t2 = t1 + c * d
281 t4 = t3 - g * h
282
283 which stops us from making full use of macc/madd-style instructions.
284 This sort of situation occurs frequently in Fourier transforms and
285 in unrolled loops.
286
287 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
288 queue so that chained multiply-add and multiply-subtract instructions
289 appear ahead of any other instruction that is likely to clobber lo.
290 In the example above, if t2 and t3 become ready at the same time,
291 the code ensures that t2 is scheduled first.
292
293 Multiply-accumulate instructions are a bigger win for some targets
294 than others, so this macro is defined on an opt-in basis. */
295 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
296 || TUNE_MIPS4120 \
297 || TUNE_MIPS4130 \
298 || TUNE_24K)
299
300 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
301 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
302
303 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
304 directly accessible, while the command-line options select
305 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
306 in use. */
307 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
308 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
309
310 /* IRIX specific stuff. */
311 #define TARGET_IRIX 0
312 #define TARGET_IRIX6 0
313
314 /* Define preprocessor macros for the -march and -mtune options.
315 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
316 processor. If INFO's canonical name is "foo", define PREFIX to
317 be "foo", and define an additional macro PREFIX_FOO. */
318 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
319 do \
320 { \
321 char *macro, *p; \
322 \
323 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
324 for (p = macro; *p != 0; p++) \
325 *p = TOUPPER (*p); \
326 \
327 builtin_define (macro); \
328 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
329 free (macro); \
330 } \
331 while (0)
332
333 /* Target CPU builtins. */
334 #define TARGET_CPU_CPP_BUILTINS() \
335 do \
336 { \
337 /* Everyone but IRIX defines this to mips. */ \
338 if (!TARGET_IRIX) \
339 builtin_assert ("machine=mips"); \
340 \
341 builtin_assert ("cpu=mips"); \
342 builtin_define ("__mips__"); \
343 builtin_define ("_mips"); \
344 \
345 /* We do this here because __mips is defined below and so we \
346 can't use builtin_define_std. We don't ever want to define \
347 "mips" for VxWorks because some of the VxWorks headers \
348 construct include filenames from a root directory macro, \
349 an architecture macro and a filename, where the architecture \
350 macro expands to 'mips'. If we define 'mips' to 1, the \
351 architecture macro expands to 1 as well. */ \
352 if (!flag_iso && !TARGET_VXWORKS) \
353 builtin_define ("mips"); \
354 \
355 if (TARGET_64BIT) \
356 builtin_define ("__mips64"); \
357 \
358 if (!TARGET_IRIX) \
359 { \
360 /* Treat _R3000 and _R4000 like register-size \
361 defines, which is how they've historically \
362 been used. */ \
363 if (TARGET_64BIT) \
364 { \
365 builtin_define_std ("R4000"); \
366 builtin_define ("_R4000"); \
367 } \
368 else \
369 { \
370 builtin_define_std ("R3000"); \
371 builtin_define ("_R3000"); \
372 } \
373 } \
374 if (TARGET_FLOAT64) \
375 builtin_define ("__mips_fpr=64"); \
376 else \
377 builtin_define ("__mips_fpr=32"); \
378 \
379 if (TARGET_MIPS16) \
380 builtin_define ("__mips16"); \
381 \
382 if (TARGET_MIPS3D) \
383 builtin_define ("__mips3d"); \
384 \
385 if (TARGET_SMARTMIPS) \
386 builtin_define ("__mips_smartmips"); \
387 \
388 if (TARGET_DSP) \
389 { \
390 builtin_define ("__mips_dsp"); \
391 if (TARGET_DSPR2) \
392 { \
393 builtin_define ("__mips_dspr2"); \
394 builtin_define ("__mips_dsp_rev=2"); \
395 } \
396 else \
397 builtin_define ("__mips_dsp_rev=1"); \
398 } \
399 \
400 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
401 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
402 \
403 if (ISA_MIPS1) \
404 { \
405 builtin_define ("__mips=1"); \
406 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
407 } \
408 else if (ISA_MIPS2) \
409 { \
410 builtin_define ("__mips=2"); \
411 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
412 } \
413 else if (ISA_MIPS3) \
414 { \
415 builtin_define ("__mips=3"); \
416 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
417 } \
418 else if (ISA_MIPS4) \
419 { \
420 builtin_define ("__mips=4"); \
421 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
422 } \
423 else if (ISA_MIPS32) \
424 { \
425 builtin_define ("__mips=32"); \
426 builtin_define ("__mips_isa_rev=1"); \
427 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
428 } \
429 else if (ISA_MIPS32R2) \
430 { \
431 builtin_define ("__mips=32"); \
432 builtin_define ("__mips_isa_rev=2"); \
433 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
434 } \
435 else if (ISA_MIPS64) \
436 { \
437 builtin_define ("__mips=64"); \
438 builtin_define ("__mips_isa_rev=1"); \
439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
440 } \
441 \
442 switch (mips_abi) \
443 { \
444 case ABI_32: \
445 builtin_define ("_ABIO32=1"); \
446 builtin_define ("_MIPS_SIM=_ABIO32"); \
447 break; \
448 \
449 case ABI_N32: \
450 builtin_define ("_ABIN32=2"); \
451 builtin_define ("_MIPS_SIM=_ABIN32"); \
452 break; \
453 \
454 case ABI_64: \
455 builtin_define ("_ABI64=3"); \
456 builtin_define ("_MIPS_SIM=_ABI64"); \
457 break; \
458 \
459 case ABI_O64: \
460 builtin_define ("_ABIO64=4"); \
461 builtin_define ("_MIPS_SIM=_ABIO64"); \
462 break; \
463 } \
464 \
465 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
466 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
467 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
468 builtin_define_with_int_value ("_MIPS_FPSET", \
469 32 / MAX_FPRS_PER_FMT); \
470 \
471 /* These defines reflect the ABI in use, not whether the \
472 FPU is directly accessible. */ \
473 if (TARGET_HARD_FLOAT_ABI) \
474 builtin_define ("__mips_hard_float"); \
475 else \
476 builtin_define ("__mips_soft_float"); \
477 \
478 if (TARGET_SINGLE_FLOAT) \
479 builtin_define ("__mips_single_float"); \
480 \
481 if (TARGET_PAIRED_SINGLE_FLOAT) \
482 builtin_define ("__mips_paired_single_float"); \
483 \
484 if (TARGET_BIG_ENDIAN) \
485 { \
486 builtin_define_std ("MIPSEB"); \
487 builtin_define ("_MIPSEB"); \
488 } \
489 else \
490 { \
491 builtin_define_std ("MIPSEL"); \
492 builtin_define ("_MIPSEL"); \
493 } \
494 \
495 /* Macros dependent on the C dialect. */ \
496 if (preprocessing_asm_p ()) \
497 { \
498 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
499 builtin_define ("_LANGUAGE_ASSEMBLY"); \
500 } \
501 else if (c_dialect_cxx ()) \
502 { \
503 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
504 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
505 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
506 } \
507 else \
508 { \
509 builtin_define_std ("LANGUAGE_C"); \
510 builtin_define ("_LANGUAGE_C"); \
511 } \
512 if (c_dialect_objc ()) \
513 { \
514 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
515 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
516 /* Bizarre, but needed at least for Irix. */ \
517 builtin_define_std ("LANGUAGE_C"); \
518 builtin_define ("_LANGUAGE_C"); \
519 } \
520 \
521 if (mips_abi == ABI_EABI) \
522 builtin_define ("__mips_eabi"); \
523 } \
524 while (0)
525
526 /* Default target_flags if no switches are specified */
527
528 #ifndef TARGET_DEFAULT
529 #define TARGET_DEFAULT 0
530 #endif
531
532 #ifndef TARGET_CPU_DEFAULT
533 #define TARGET_CPU_DEFAULT 0
534 #endif
535
536 #ifndef TARGET_ENDIAN_DEFAULT
537 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
538 #endif
539
540 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
541 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
542 #endif
543
544 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
545 #ifndef MIPS_ISA_DEFAULT
546 #ifndef MIPS_CPU_STRING_DEFAULT
547 #define MIPS_CPU_STRING_DEFAULT "from-abi"
548 #endif
549 #endif
550
551 #ifdef IN_LIBGCC2
552 #undef TARGET_64BIT
553 /* Make this compile time constant for libgcc2 */
554 #ifdef __mips64
555 #define TARGET_64BIT 1
556 #else
557 #define TARGET_64BIT 0
558 #endif
559 #endif /* IN_LIBGCC2 */
560
561 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
562 when compiled with hardware floating point. This is because MIPS16
563 code cannot save and restore the floating-point registers, which is
564 important if in a mixed MIPS16/non-MIPS16 environment. */
565
566 #ifdef IN_LIBGCC2
567 #if __mips_hard_float
568 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
569 #endif
570 #endif /* IN_LIBGCC2 */
571
572 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
573
574 #ifndef MULTILIB_ENDIAN_DEFAULT
575 #if TARGET_ENDIAN_DEFAULT == 0
576 #define MULTILIB_ENDIAN_DEFAULT "EL"
577 #else
578 #define MULTILIB_ENDIAN_DEFAULT "EB"
579 #endif
580 #endif
581
582 #ifndef MULTILIB_ISA_DEFAULT
583 # if MIPS_ISA_DEFAULT == 1
584 # define MULTILIB_ISA_DEFAULT "mips1"
585 # else
586 # if MIPS_ISA_DEFAULT == 2
587 # define MULTILIB_ISA_DEFAULT "mips2"
588 # else
589 # if MIPS_ISA_DEFAULT == 3
590 # define MULTILIB_ISA_DEFAULT "mips3"
591 # else
592 # if MIPS_ISA_DEFAULT == 4
593 # define MULTILIB_ISA_DEFAULT "mips4"
594 # else
595 # if MIPS_ISA_DEFAULT == 32
596 # define MULTILIB_ISA_DEFAULT "mips32"
597 # else
598 # if MIPS_ISA_DEFAULT == 33
599 # define MULTILIB_ISA_DEFAULT "mips32r2"
600 # else
601 # if MIPS_ISA_DEFAULT == 64
602 # define MULTILIB_ISA_DEFAULT "mips64"
603 # else
604 # define MULTILIB_ISA_DEFAULT "mips1"
605 # endif
606 # endif
607 # endif
608 # endif
609 # endif
610 # endif
611 # endif
612 #endif
613
614 #ifndef MULTILIB_DEFAULTS
615 #define MULTILIB_DEFAULTS \
616 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
617 #endif
618
619 /* We must pass -EL to the linker by default for little endian embedded
620 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
621 linker will default to using big-endian output files. The OUTPUT_FORMAT
622 line must be in the linker script, otherwise -EB/-EL will not work. */
623
624 #ifndef ENDIAN_SPEC
625 #if TARGET_ENDIAN_DEFAULT == 0
626 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
627 #else
628 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
629 #endif
630 #endif
631
632 /* A spec condition that matches all non-mips16 -mips arguments. */
633
634 #define MIPS_ISA_LEVEL_OPTION_SPEC \
635 "mips1|mips2|mips3|mips4|mips32*|mips64*"
636
637 /* A spec condition that matches all non-mips16 architecture arguments. */
638
639 #define MIPS_ARCH_OPTION_SPEC \
640 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
641
642 /* A spec that infers a -mips argument from an -march argument,
643 or injects the default if no architecture is specified. */
644
645 #define MIPS_ISA_LEVEL_SPEC \
646 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
647 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
648 %{march=mips2|march=r6000:-mips2} \
649 %{march=mips3|march=r4*|march=vr4*|march=orion:-mips3} \
650 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \
651 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
652 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
653 |march=34k*|march=74k*: -mips32r2} \
654 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
655 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
656
657 /* A spec that infers a -mhard-float or -msoft-float setting from an
658 -march argument. Note that soft-float and hard-float code are not
659 link-compatible. */
660
661 #define MIPS_ARCH_FLOAT_SPEC \
662 "%{mhard-float|msoft-float|march=mips*:; \
663 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
664 |march=34kc|march=74kc|march=5kc: -msoft-float; \
665 march=*: -mhard-float}"
666
667 /* A spec condition that matches 32-bit options. It only works if
668 MIPS_ISA_LEVEL_SPEC has been applied. */
669
670 #define MIPS_32BIT_OPTION_SPEC \
671 "mips1|mips2|mips32*|mgp32"
672
673 /* Support for a compile-time default CPU, et cetera. The rules are:
674 --with-arch is ignored if -march is specified or a -mips is specified
675 (other than -mips16).
676 --with-tune is ignored if -mtune is specified.
677 --with-abi is ignored if -mabi is specified.
678 --with-float is ignored if -mhard-float or -msoft-float are
679 specified.
680 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
681 specified. */
682 #define OPTION_DEFAULT_SPECS \
683 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
684 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
685 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
686 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
687 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
688 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }
689
690
691 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
692 && ISA_HAS_COND_TRAP)
693
694 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
695
696 /* True if the ABI can only work with 64-bit integer registers. We
697 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
698 otherwise floating-point registers must also be 64-bit. */
699 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
700
701 /* Likewise for 32-bit regs. */
702 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
703
704 /* True if symbols are 64 bits wide. At present, n64 is the only
705 ABI for which this is true. */
706 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
707
708 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
709 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
710 || ISA_MIPS4 \
711 || ISA_MIPS64)
712
713 /* ISA has branch likely instructions (e.g. mips2). */
714 /* Disable branchlikely for tx39 until compare rewrite. They haven't
715 been generated up to this point. */
716 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
717
718 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
719 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
720 || TARGET_MIPS5400 \
721 || TARGET_MIPS5500 \
722 || TARGET_MIPS7000 \
723 || TARGET_MIPS9000 \
724 || TARGET_MAD \
725 || ISA_MIPS32 \
726 || ISA_MIPS32R2 \
727 || ISA_MIPS64) \
728 && !TARGET_MIPS16)
729
730 /* ISA has the conditional move instructions introduced in mips4. */
731 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
732 || ISA_MIPS32 \
733 || ISA_MIPS32R2 \
734 || ISA_MIPS64) \
735 && !TARGET_MIPS5500 \
736 && !TARGET_MIPS16)
737
738 /* ISA has LDC1 and SDC1. */
739 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
740
741 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
742 branch on CC, and move (both FP and non-FP) on CC. */
743 #define ISA_HAS_8CC (ISA_MIPS4 \
744 || ISA_MIPS32 \
745 || ISA_MIPS32R2 \
746 || ISA_MIPS64)
747
748 /* This is a catch all for other mips4 instructions: indexed load, the
749 FP madd and msub instructions, and the FP recip and recip sqrt
750 instructions. */
751 #define ISA_HAS_FP4 ((ISA_MIPS4 \
752 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
753 || ISA_MIPS64) \
754 && !TARGET_MIPS16)
755
756 /* ISA has paired-single instructions. */
757 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64)
758
759 /* ISA has conditional trap instructions. */
760 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
761 && !TARGET_MIPS16)
762
763 /* ISA has integer multiply-accumulate instructions, madd and msub. */
764 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
765 || ISA_MIPS32R2 \
766 || ISA_MIPS64) \
767 && !TARGET_MIPS16)
768
769 /* Integer multiply-accumulate instructions should be generated. */
770 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
771
772 /* ISA has floating-point nmadd and nmsub instructions for mode MODE. */
773 #define ISA_HAS_NMADD_NMSUB(MODE) \
774 ((ISA_MIPS4 \
775 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
776 || ISA_MIPS64) \
777 && (!TARGET_MIPS5400 || TARGET_MAD) \
778 && !TARGET_MIPS16)
779
780 /* ISA has count leading zeroes/ones instruction (not implemented). */
781 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
782 || ISA_MIPS32R2 \
783 || ISA_MIPS64) \
784 && !TARGET_MIPS16)
785
786 /* ISA has three operand multiply instructions that put
787 the high part in an accumulator: mulhi or mulhiu. */
788 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
789 || TARGET_MIPS5500 \
790 || TARGET_SR71K) \
791 && !TARGET_MIPS16)
792
793 /* ISA has three operand multiply instructions that
794 negates the result and puts the result in an accumulator. */
795 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
796 || TARGET_MIPS5500 \
797 || TARGET_SR71K) \
798 && !TARGET_MIPS16)
799
800 /* ISA has three operand multiply instructions that subtracts the
801 result from a 4th operand and puts the result in an accumulator. */
802 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
803 || TARGET_MIPS5500 \
804 || TARGET_SR71K) \
805 && !TARGET_MIPS16)
806
807 /* ISA has three operand multiply instructions that the result
808 from a 4th operand and puts the result in an accumulator. */
809 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
810 || TARGET_MIPS4130 \
811 || TARGET_MIPS5400 \
812 || TARGET_MIPS5500 \
813 || TARGET_SR71K) \
814 && !TARGET_MIPS16)
815
816 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
817 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
818 || TARGET_MIPS4130) \
819 && !TARGET_MIPS16)
820
821 /* ISA has the "ror" (rotate right) instructions. */
822 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
823 || TARGET_MIPS5400 \
824 || TARGET_MIPS5500 \
825 || TARGET_SR71K \
826 || TARGET_SMARTMIPS) \
827 && !TARGET_MIPS16)
828
829 /* ISA has data prefetch instructions. This controls use of 'pref'. */
830 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
831 || ISA_MIPS32 \
832 || ISA_MIPS32R2 \
833 || ISA_MIPS64) \
834 && !TARGET_MIPS16)
835
836 /* ISA has data indexed prefetch instructions. This controls use of
837 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
838 (prefx is a cop1x instruction, so can only be used if FP is
839 enabled.) */
840 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
841 || ISA_MIPS32R2 \
842 || ISA_MIPS64) \
843 && !TARGET_MIPS16)
844
845 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
846 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
847 also requires TARGET_DOUBLE_FLOAT. */
848 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
849
850 /* ISA includes the MIPS32r2 seb and seh instructions. */
851 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
852 && !TARGET_MIPS16)
853
854 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
855 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
856 && !TARGET_MIPS16)
857
858 /* ISA has instructions for accessing top part of 64-bit fp regs. */
859 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
860
861 /* ISA has lwxs instruction (load w/scaled index address. */
862 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
863
864 /* The DSP ASE is available. */
865 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
866
867 /* Revision 2 of the DSP ASE is available. */
868 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
869
870 /* True if the result of a load is not available to the next instruction.
871 A nop will then be needed between instructions like "lw $4,..."
872 and "addiu $4,$4,1". */
873 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
874 && !TARGET_MIPS3900 \
875 && !TARGET_MIPS16)
876
877 /* Likewise mtc1 and mfc1. */
878 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
879
880 /* Likewise floating-point comparisons. */
881 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
882
883 /* True if mflo and mfhi can be immediately followed by instructions
884 which write to the HI and LO registers.
885
886 According to MIPS specifications, MIPS ISAs I, II, and III need
887 (at least) two instructions between the reads of HI/LO and
888 instructions which write them, and later ISAs do not. Contradicting
889 the MIPS specifications, some MIPS IV processor user manuals (e.g.
890 the UM for the NEC Vr5000) document needing the instructions between
891 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
892 MIPS64 and later ISAs to have the interlocks, plus any specific
893 earlier-ISA CPUs for which CPU documentation declares that the
894 instructions are really interlocked. */
895 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
896 || ISA_MIPS32R2 \
897 || ISA_MIPS64 \
898 || TARGET_MIPS5500)
899
900 /* ISA includes synci, jr.hb and jalr.hb. */
901 #define ISA_HAS_SYNCI (ISA_MIPS32R2 && !TARGET_MIPS16)
902
903 /* ISA includes sync. */
904 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
905 #define GENERATE_SYNC \
906 (target_flags_explicit & MASK_LLSC \
907 ? TARGET_LLSC && !TARGET_MIPS16 \
908 : ISA_HAS_SYNC)
909
910 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
911 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
912 instructions. */
913 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
914 #define GENERATE_LL_SC \
915 (target_flags_explicit & MASK_LLSC \
916 ? TARGET_LLSC && !TARGET_MIPS16 \
917 : ISA_HAS_LL_SC)
918 \f
919 /* Add -G xx support. */
920
921 #undef SWITCH_TAKES_ARG
922 #define SWITCH_TAKES_ARG(CHAR) \
923 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
924
925 #define OVERRIDE_OPTIONS mips_override_options ()
926
927 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
928
929 /* Show we can debug even without a frame pointer. */
930 #define CAN_DEBUG_WITHOUT_FP
931 \f
932 /* Tell collect what flags to pass to nm. */
933 #ifndef NM_FLAGS
934 #define NM_FLAGS "-Bn"
935 #endif
936
937 \f
938 #ifndef MIPS_ABI_DEFAULT
939 #define MIPS_ABI_DEFAULT ABI_32
940 #endif
941
942 /* Use the most portable ABI flag for the ASM specs. */
943
944 #if MIPS_ABI_DEFAULT == ABI_32
945 #define MULTILIB_ABI_DEFAULT "mabi=32"
946 #endif
947
948 #if MIPS_ABI_DEFAULT == ABI_O64
949 #define MULTILIB_ABI_DEFAULT "mabi=o64"
950 #endif
951
952 #if MIPS_ABI_DEFAULT == ABI_N32
953 #define MULTILIB_ABI_DEFAULT "mabi=n32"
954 #endif
955
956 #if MIPS_ABI_DEFAULT == ABI_64
957 #define MULTILIB_ABI_DEFAULT "mabi=64"
958 #endif
959
960 #if MIPS_ABI_DEFAULT == ABI_EABI
961 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
962 #endif
963
964 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
965 to the assembler. It may be overridden by subtargets. */
966 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
967 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
968 %{noasmopt:-O0} \
969 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
970 #endif
971
972 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
973 the assembler. It may be overridden by subtargets.
974
975 Beginning with gas 2.13, -mdebug must be passed to correctly handle
976 COFF debugging info. */
977
978 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
979 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
980 %{g} %{g0} %{g1} %{g2} %{g3} \
981 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
982 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
983 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
984 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
985 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
986 #endif
987
988 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
989 overridden by subtargets. */
990
991 #ifndef SUBTARGET_ASM_SPEC
992 #define SUBTARGET_ASM_SPEC ""
993 #endif
994
995 #undef ASM_SPEC
996 #define ASM_SPEC "\
997 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
998 %{mips32} %{mips32r2} %{mips64} \
999 %{mips16} %{mno-mips16:-no-mips16} \
1000 %{mips3d} %{mno-mips3d:-no-mips3d} \
1001 %{mdmx} %{mno-mdmx:-no-mdmx} \
1002 %{mdsp} %{mno-dsp} \
1003 %{mdspr2} %{mno-dspr2} \
1004 %{msmartmips} %{mno-smartmips} \
1005 %{mmt} %{mno-mt} \
1006 %{mfix-vr4120} %{mfix-vr4130} \
1007 %(subtarget_asm_optimizing_spec) \
1008 %(subtarget_asm_debugging_spec) \
1009 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
1010 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1011 %{mfp32} %{mfp64} \
1012 %{mshared} %{mno-shared} \
1013 %{msym32} %{mno-sym32} \
1014 %{mtune=*} %{v} \
1015 %(subtarget_asm_spec)"
1016
1017 /* Extra switches sometimes passed to the linker. */
1018 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1019 will interpret it as a -b option. */
1020
1021 #ifndef LINK_SPEC
1022 #define LINK_SPEC "\
1023 %(endian_spec) \
1024 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1025 %{bestGnum} %{shared} %{non_shared}"
1026 #endif /* LINK_SPEC defined */
1027
1028
1029 /* Specs for the compiler proper */
1030
1031 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1032 overridden by subtargets. */
1033 #ifndef SUBTARGET_CC1_SPEC
1034 #define SUBTARGET_CC1_SPEC ""
1035 #endif
1036
1037 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1038
1039 #undef CC1_SPEC
1040 #define CC1_SPEC "\
1041 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1042 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1043 %{save-temps: } \
1044 %(subtarget_cc1_spec)"
1045
1046 /* Preprocessor specs. */
1047
1048 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1049 overridden by subtargets. */
1050 #ifndef SUBTARGET_CPP_SPEC
1051 #define SUBTARGET_CPP_SPEC ""
1052 #endif
1053
1054 #define CPP_SPEC "%(subtarget_cpp_spec)"
1055
1056 /* This macro defines names of additional specifications to put in the specs
1057 that can be used in various specifications like CC1_SPEC. Its definition
1058 is an initializer with a subgrouping for each command option.
1059
1060 Each subgrouping contains a string constant, that defines the
1061 specification name, and a string constant that used by the GCC driver
1062 program.
1063
1064 Do not define this macro if it does not need to do anything. */
1065
1066 #define EXTRA_SPECS \
1067 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1068 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1069 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1070 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1071 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1072 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1073 { "endian_spec", ENDIAN_SPEC }, \
1074 SUBTARGET_EXTRA_SPECS
1075
1076 #ifndef SUBTARGET_EXTRA_SPECS
1077 #define SUBTARGET_EXTRA_SPECS
1078 #endif
1079 \f
1080 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1081 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1082 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1083
1084 #ifndef PREFERRED_DEBUGGING_TYPE
1085 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1086 #endif
1087
1088 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1089
1090 /* By default, turn on GDB extensions. */
1091 #define DEFAULT_GDB_EXTENSIONS 1
1092
1093 /* Local compiler-generated symbols must have a prefix that the assembler
1094 understands. By default, this is $, although some targets (e.g.,
1095 NetBSD-ELF) need to override this. */
1096
1097 #ifndef LOCAL_LABEL_PREFIX
1098 #define LOCAL_LABEL_PREFIX "$"
1099 #endif
1100
1101 /* By default on the mips, external symbols do not have an underscore
1102 prepended, but some targets (e.g., NetBSD) require this. */
1103
1104 #ifndef USER_LABEL_PREFIX
1105 #define USER_LABEL_PREFIX ""
1106 #endif
1107
1108 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1109 since the length can run past this up to a continuation point. */
1110 #undef DBX_CONTIN_LENGTH
1111 #define DBX_CONTIN_LENGTH 1500
1112
1113 /* How to renumber registers for dbx and gdb. */
1114 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1115
1116 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1117 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1118
1119 /* The DWARF 2 CFA column which tracks the return address. */
1120 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1121
1122 /* Before the prologue, RA lives in r31. */
1123 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1124
1125 /* Describe how we implement __builtin_eh_return. */
1126 #define EH_RETURN_DATA_REGNO(N) \
1127 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1128
1129 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1130
1131 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1132 The default for this in 64-bit mode is 8, which causes problems with
1133 SFmode register saves. */
1134 #define DWARF_CIE_DATA_ALIGNMENT -4
1135
1136 /* Correct the offset of automatic variables and arguments. Note that
1137 the MIPS debug format wants all automatic variables and arguments
1138 to be in terms of the virtual frame pointer (stack pointer before
1139 any adjustment in the function), while the MIPS 3.0 linker wants
1140 the frame pointer to be the stack pointer after the initial
1141 adjustment. */
1142
1143 #define DEBUGGER_AUTO_OFFSET(X) \
1144 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1145 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1146 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1147 \f
1148 /* Target machine storage layout */
1149
1150 #define BITS_BIG_ENDIAN 0
1151 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1152 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1153
1154 /* Define this to set the endianness to use in libgcc2.c, which can
1155 not depend on target_flags. */
1156 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1157 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1158 #else
1159 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1160 #endif
1161
1162 #define MAX_BITS_PER_WORD 64
1163
1164 /* Width of a word, in units (bytes). */
1165 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1166 #ifndef IN_LIBGCC2
1167 #define MIN_UNITS_PER_WORD 4
1168 #endif
1169
1170 /* For MIPS, width of a floating point register. */
1171 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1172
1173 /* The number of consecutive floating-point registers needed to store the
1174 largest format supported by the FPU. */
1175 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1176
1177 /* The number of consecutive floating-point registers needed to store the
1178 smallest format supported by the FPU. */
1179 #define MIN_FPRS_PER_FMT \
1180 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 ? 1 : MAX_FPRS_PER_FMT)
1181
1182 /* The largest size of value that can be held in floating-point
1183 registers and moved with a single instruction. */
1184 #define UNITS_PER_HWFPVALUE \
1185 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1186
1187 /* The largest size of value that can be held in floating-point
1188 registers. */
1189 #define UNITS_PER_FPVALUE \
1190 (TARGET_SOFT_FLOAT_ABI ? 0 \
1191 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1192 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1193
1194 /* The number of bytes in a double. */
1195 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1196
1197 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1198
1199 /* Set the sizes of the core types. */
1200 #define SHORT_TYPE_SIZE 16
1201 #define INT_TYPE_SIZE 32
1202 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1203 #define LONG_LONG_TYPE_SIZE 64
1204
1205 #define FLOAT_TYPE_SIZE 32
1206 #define DOUBLE_TYPE_SIZE 64
1207 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1208
1209 /* Define the sizes of fixed-point types. */
1210 #define SHORT_FRACT_TYPE_SIZE 8
1211 #define FRACT_TYPE_SIZE 16
1212 #define LONG_FRACT_TYPE_SIZE 32
1213 #define LONG_LONG_FRACT_TYPE_SIZE 64
1214
1215 #define SHORT_ACCUM_TYPE_SIZE 16
1216 #define ACCUM_TYPE_SIZE 32
1217 #define LONG_ACCUM_TYPE_SIZE 64
1218 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1219 doesn't support 128-bit integers for MIPS32 currently. */
1220 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1221
1222 /* long double is not a fixed mode, but the idea is that, if we
1223 support long double, we also want a 128-bit integer type. */
1224 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1225
1226 #ifdef IN_LIBGCC2
1227 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1228 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1229 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1230 # else
1231 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1232 # endif
1233 #endif
1234
1235 /* Width in bits of a pointer. */
1236 #ifndef POINTER_SIZE
1237 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1238 #endif
1239
1240 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1241 #define PARM_BOUNDARY BITS_PER_WORD
1242
1243 /* Allocation boundary (in *bits*) for the code of a function. */
1244 #define FUNCTION_BOUNDARY 32
1245
1246 /* Alignment of field after `int : 0' in a structure. */
1247 #define EMPTY_FIELD_BOUNDARY 32
1248
1249 /* Every structure's size must be a multiple of this. */
1250 /* 8 is observed right on a DECstation and on riscos 4.02. */
1251 #define STRUCTURE_SIZE_BOUNDARY 8
1252
1253 /* There is no point aligning anything to a rounder boundary than this. */
1254 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1255
1256 /* All accesses must be aligned. */
1257 #define STRICT_ALIGNMENT 1
1258
1259 /* Define this if you wish to imitate the way many other C compilers
1260 handle alignment of bitfields and the structures that contain
1261 them.
1262
1263 The behavior is that the type written for a bit-field (`int',
1264 `short', or other integer type) imposes an alignment for the
1265 entire structure, as if the structure really did contain an
1266 ordinary field of that type. In addition, the bit-field is placed
1267 within the structure so that it would fit within such a field,
1268 not crossing a boundary for it.
1269
1270 Thus, on most machines, a bit-field whose type is written as `int'
1271 would not cross a four-byte boundary, and would force four-byte
1272 alignment for the whole structure. (The alignment used may not
1273 be four bytes; it is controlled by the other alignment
1274 parameters.)
1275
1276 If the macro is defined, its definition should be a C expression;
1277 a nonzero value for the expression enables this behavior. */
1278
1279 #define PCC_BITFIELD_TYPE_MATTERS 1
1280
1281 /* If defined, a C expression to compute the alignment given to a
1282 constant that is being placed in memory. CONSTANT is the constant
1283 and ALIGN is the alignment that the object would ordinarily have.
1284 The value of this macro is used instead of that alignment to align
1285 the object.
1286
1287 If this macro is not defined, then ALIGN is used.
1288
1289 The typical use of this macro is to increase alignment for string
1290 constants to be word aligned so that `strcpy' calls that copy
1291 constants can be done inline. */
1292
1293 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1294 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1295 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1296
1297 /* If defined, a C expression to compute the alignment for a static
1298 variable. TYPE is the data type, and ALIGN is the alignment that
1299 the object would ordinarily have. The value of this macro is used
1300 instead of that alignment to align the object.
1301
1302 If this macro is not defined, then ALIGN is used.
1303
1304 One use of this macro is to increase alignment of medium-size
1305 data to make it all fit in fewer cache lines. Another is to
1306 cause character arrays to be word-aligned so that `strcpy' calls
1307 that copy constants to character arrays can be done inline. */
1308
1309 #undef DATA_ALIGNMENT
1310 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1311 ((((ALIGN) < BITS_PER_WORD) \
1312 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1313 || TREE_CODE (TYPE) == UNION_TYPE \
1314 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1315
1316 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1317 character arrays to be word-aligned so that `strcpy' calls that copy
1318 constants to character arrays can be done inline, and 'strcmp' can be
1319 optimised to use word loads. */
1320 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1321 DATA_ALIGNMENT (TYPE, ALIGN)
1322
1323 #define PAD_VARARGS_DOWN \
1324 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1325
1326 /* Define if operations between registers always perform the operation
1327 on the full register even if a narrower mode is specified. */
1328 #define WORD_REGISTER_OPERATIONS
1329
1330 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1331 moves. All other references are zero extended. */
1332 #define LOAD_EXTEND_OP(MODE) \
1333 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1334 ? SIGN_EXTEND : ZERO_EXTEND)
1335
1336 /* Define this macro if it is advisable to hold scalars in registers
1337 in a wider mode than that declared by the program. In such cases,
1338 the value is constrained to be within the bounds of the declared
1339 type, but kept valid in the wider mode. The signedness of the
1340 extension may differ from that of the type. */
1341
1342 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1343 if (GET_MODE_CLASS (MODE) == MODE_INT \
1344 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1345 { \
1346 if ((MODE) == SImode) \
1347 (UNSIGNEDP) = 0; \
1348 (MODE) = Pmode; \
1349 }
1350
1351 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1352 Extensions of pointers to word_mode must be signed. */
1353 #define POINTERS_EXTEND_UNSIGNED false
1354
1355 /* Define if loading short immediate values into registers sign extends. */
1356 #define SHORT_IMMEDIATES_SIGN_EXTEND
1357
1358 /* The [d]clz instructions have the natural values at 0. */
1359
1360 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1361 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1362 \f
1363 /* Standard register usage. */
1364
1365 /* Number of hardware registers. We have:
1366
1367 - 32 integer registers
1368 - 32 floating point registers
1369 - 8 condition code registers
1370 - 2 accumulator registers (hi and lo)
1371 - 32 registers each for coprocessors 0, 2 and 3
1372 - 3 fake registers:
1373 - ARG_POINTER_REGNUM
1374 - FRAME_POINTER_REGNUM
1375 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1376 - 3 dummy entries that were used at various times in the past.
1377 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1378 - 6 DSP control registers */
1379
1380 #define FIRST_PSEUDO_REGISTER 188
1381
1382 /* By default, fix the kernel registers ($26 and $27), the global
1383 pointer ($28) and the stack pointer ($29). This can change
1384 depending on the command-line options.
1385
1386 Regarding coprocessor registers: without evidence to the contrary,
1387 it's best to assume that each coprocessor register has a unique
1388 use. This can be overridden, in, e.g., mips_override_options or
1389 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1390 for a particular target. */
1391
1392 #define FIXED_REGISTERS \
1393 { \
1394 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1395 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1396 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1397 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1398 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1399 /* COP0 registers */ \
1400 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1401 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1402 /* COP2 registers */ \
1403 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1404 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1405 /* COP3 registers */ \
1406 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1407 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1408 /* 6 DSP accumulator registers & 6 control registers */ \
1409 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1410 }
1411
1412
1413 /* Set up this array for o32 by default.
1414
1415 Note that we don't mark $31 as a call-clobbered register. The idea is
1416 that it's really the call instructions themselves which clobber $31.
1417 We don't care what the called function does with it afterwards.
1418
1419 This approach makes it easier to implement sibcalls. Unlike normal
1420 calls, sibcalls don't clobber $31, so the register reaches the
1421 called function in tact. EPILOGUE_USES says that $31 is useful
1422 to the called function. */
1423
1424 #define CALL_USED_REGISTERS \
1425 { \
1426 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1427 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1428 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1429 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1430 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1431 /* COP0 registers */ \
1432 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1433 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1434 /* COP2 registers */ \
1435 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1436 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1437 /* COP3 registers */ \
1438 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1439 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1440 /* 6 DSP accumulator registers & 6 control registers */ \
1441 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1442 }
1443
1444
1445 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1446
1447 #define CALL_REALLY_USED_REGISTERS \
1448 { /* General registers. */ \
1449 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1450 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1451 /* Floating-point registers. */ \
1452 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1453 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1454 /* Others. */ \
1455 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1456 /* COP0 registers */ \
1457 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1458 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1459 /* COP2 registers */ \
1460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1462 /* COP3 registers */ \
1463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1465 /* 6 DSP accumulator registers & 6 control registers */ \
1466 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1467 }
1468
1469 /* Internal macros to classify a register number as to whether it's a
1470 general purpose register, a floating point register, a
1471 multiply/divide register, or a status register. */
1472
1473 #define GP_REG_FIRST 0
1474 #define GP_REG_LAST 31
1475 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1476 #define GP_DBX_FIRST 0
1477
1478 #define FP_REG_FIRST 32
1479 #define FP_REG_LAST 63
1480 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1481 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1482
1483 #define MD_REG_FIRST 64
1484 #define MD_REG_LAST 65
1485 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1486 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1487
1488 /* The DWARF 2 CFA column which tracks the return address from a
1489 signal handler context. This means that to maintain backwards
1490 compatibility, no hard register can be assigned this column if it
1491 would need to be handled by the DWARF unwinder. */
1492 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1493
1494 #define ST_REG_FIRST 67
1495 #define ST_REG_LAST 74
1496 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1497
1498
1499 /* FIXME: renumber. */
1500 #define COP0_REG_FIRST 80
1501 #define COP0_REG_LAST 111
1502 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1503
1504 #define COP2_REG_FIRST 112
1505 #define COP2_REG_LAST 143
1506 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1507
1508 #define COP3_REG_FIRST 144
1509 #define COP3_REG_LAST 175
1510 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1511 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1512 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1513
1514 #define DSP_ACC_REG_FIRST 176
1515 #define DSP_ACC_REG_LAST 181
1516 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1517
1518 #define AT_REGNUM (GP_REG_FIRST + 1)
1519 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1520 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1521
1522 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1523 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1524 should be used instead. */
1525 #define FPSW_REGNUM ST_REG_FIRST
1526
1527 #define GP_REG_P(REGNO) \
1528 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1529 #define M16_REG_P(REGNO) \
1530 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1531 #define FP_REG_P(REGNO) \
1532 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1533 #define MD_REG_P(REGNO) \
1534 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1535 #define ST_REG_P(REGNO) \
1536 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1537 #define COP0_REG_P(REGNO) \
1538 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1539 #define COP2_REG_P(REGNO) \
1540 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1541 #define COP3_REG_P(REGNO) \
1542 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1543 #define ALL_COP_REG_P(REGNO) \
1544 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1545 /* Test if REGNO is one of the 6 new DSP accumulators. */
1546 #define DSP_ACC_REG_P(REGNO) \
1547 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1548 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1549 #define ACC_REG_P(REGNO) \
1550 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1551
1552 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1553
1554 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1555 to initialize the mips16 gp pseudo register. */
1556 #define CONST_GP_P(X) \
1557 (GET_CODE (X) == CONST \
1558 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1559 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1560
1561 /* Return coprocessor number from register number. */
1562
1563 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1564 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1565 : COP3_REG_P (REGNO) ? '3' : '?')
1566
1567
1568 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1569
1570 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1571 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1572
1573 #define MODES_TIEABLE_P mips_modes_tieable_p
1574
1575 /* Register to use for pushing function arguments. */
1576 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1577
1578 /* These two registers don't really exist: they get eliminated to either
1579 the stack or hard frame pointer. */
1580 #define ARG_POINTER_REGNUM 77
1581 #define FRAME_POINTER_REGNUM 78
1582
1583 /* $30 is not available on the mips16, so we use $17 as the frame
1584 pointer. */
1585 #define HARD_FRAME_POINTER_REGNUM \
1586 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1587
1588 #define FRAME_POINTER_REQUIRED (mips_frame_pointer_required ())
1589
1590 /* Register in which static-chain is passed to a function. */
1591 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1592
1593 /* Registers used as temporaries in prologue/epilogue code. If we're
1594 generating mips16 code, these registers must come from the core set
1595 of 8. The prologue register mustn't conflict with any incoming
1596 arguments, the static chain pointer, or the frame pointer. The
1597 epilogue temporary mustn't conflict with the return registers, the
1598 frame pointer, the EH stack adjustment, or the EH data registers. */
1599
1600 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1601 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1602
1603 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1604 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1605
1606 /* Define this macro if it is as good or better to call a constant
1607 function address than to call an address kept in a register. */
1608 #define NO_FUNCTION_CSE 1
1609
1610 /* The ABI-defined global pointer. Sometimes we use a different
1611 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1612 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1613
1614 /* We normally use $28 as the global pointer. However, when generating
1615 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1616 register instead. They can then avoid saving and restoring $28
1617 and perhaps avoid using a frame at all.
1618
1619 When a leaf function uses something other than $28, mips_expand_prologue
1620 will modify pic_offset_table_rtx in place. Take the register number
1621 from there after reload. */
1622 #define PIC_OFFSET_TABLE_REGNUM \
1623 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1624
1625 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1626 \f
1627 /* Define the classes of registers for register constraints in the
1628 machine description. Also define ranges of constants.
1629
1630 One of the classes must always be named ALL_REGS and include all hard regs.
1631 If there is more than one class, another class must be named NO_REGS
1632 and contain no registers.
1633
1634 The name GENERAL_REGS must be the name of a class (or an alias for
1635 another name such as ALL_REGS). This is the class of registers
1636 that is allowed by "g" or "r" in a register constraint.
1637 Also, registers outside this class are allocated only when
1638 instructions express preferences for them.
1639
1640 The classes must be numbered in nondecreasing order; that is,
1641 a larger-numbered class must never be contained completely
1642 in a smaller-numbered class.
1643
1644 For any two classes, it is very desirable that there be another
1645 class that represents their union. */
1646
1647 enum reg_class
1648 {
1649 NO_REGS, /* no registers in set */
1650 M16_NA_REGS, /* mips16 regs not used to pass args */
1651 M16_REGS, /* mips16 directly accessible registers */
1652 T_REG, /* mips16 T register ($24) */
1653 M16_T_REGS, /* mips16 registers plus T register */
1654 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1655 V1_REG, /* Register $v1 ($3) used for TLS access. */
1656 LEA_REGS, /* Every GPR except $25 */
1657 GR_REGS, /* integer registers */
1658 FP_REGS, /* floating point registers */
1659 MD0_REG, /* first multiply/divide register */
1660 MD1_REG, /* second multiply/divide register */
1661 MD_REGS, /* multiply/divide registers (hi/lo) */
1662 COP0_REGS, /* generic coprocessor classes */
1663 COP2_REGS,
1664 COP3_REGS,
1665 HI_AND_GR_REGS, /* union classes */
1666 LO_AND_GR_REGS,
1667 HI_AND_FP_REGS,
1668 COP0_AND_GR_REGS,
1669 COP2_AND_GR_REGS,
1670 COP3_AND_GR_REGS,
1671 ALL_COP_REGS,
1672 ALL_COP_AND_GR_REGS,
1673 ST_REGS, /* status registers (fp status) */
1674 DSP_ACC_REGS, /* DSP accumulator registers */
1675 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1676 ALL_REGS, /* all registers */
1677 LIM_REG_CLASSES /* max value + 1 */
1678 };
1679
1680 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1681
1682 #define GENERAL_REGS GR_REGS
1683
1684 /* An initializer containing the names of the register classes as C
1685 string constants. These names are used in writing some of the
1686 debugging dumps. */
1687
1688 #define REG_CLASS_NAMES \
1689 { \
1690 "NO_REGS", \
1691 "M16_NA_REGS", \
1692 "M16_REGS", \
1693 "T_REG", \
1694 "M16_T_REGS", \
1695 "PIC_FN_ADDR_REG", \
1696 "V1_REG", \
1697 "LEA_REGS", \
1698 "GR_REGS", \
1699 "FP_REGS", \
1700 "MD0_REG", \
1701 "MD1_REG", \
1702 "MD_REGS", \
1703 /* coprocessor registers */ \
1704 "COP0_REGS", \
1705 "COP2_REGS", \
1706 "COP3_REGS", \
1707 "HI_AND_GR_REGS", \
1708 "LO_AND_GR_REGS", \
1709 "HI_AND_FP_REGS", \
1710 "COP0_AND_GR_REGS", \
1711 "COP2_AND_GR_REGS", \
1712 "COP3_AND_GR_REGS", \
1713 "ALL_COP_REGS", \
1714 "ALL_COP_AND_GR_REGS", \
1715 "ST_REGS", \
1716 "DSP_ACC_REGS", \
1717 "ACC_REGS", \
1718 "ALL_REGS" \
1719 }
1720
1721 /* An initializer containing the contents of the register classes,
1722 as integers which are bit masks. The Nth integer specifies the
1723 contents of class N. The way the integer MASK is interpreted is
1724 that register R is in the class if `MASK & (1 << R)' is 1.
1725
1726 When the machine has more than 32 registers, an integer does not
1727 suffice. Then the integers are replaced by sub-initializers,
1728 braced groupings containing several integers. Each
1729 sub-initializer must be suitable as an initializer for the type
1730 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1731
1732 #define REG_CLASS_CONTENTS \
1733 { \
1734 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1735 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1736 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1737 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1738 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1739 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1740 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1741 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1742 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1743 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1744 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1745 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1746 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1747 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1748 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1749 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1750 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1751 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1752 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1753 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1754 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1755 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1756 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1757 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1758 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1759 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1760 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1761 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1762 }
1763
1764
1765 /* A C expression whose value is a register class containing hard
1766 register REGNO. In general there is more that one such class;
1767 choose a class which is "minimal", meaning that no smaller class
1768 also contains the register. */
1769
1770 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1771
1772 /* A macro whose definition is the name of the class to which a
1773 valid base register must belong. A base register is one used in
1774 an address which is the register value plus a displacement. */
1775
1776 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1777
1778 /* A macro whose definition is the name of the class to which a
1779 valid index register must belong. An index register is one used
1780 in an address where its value is either multiplied by a scale
1781 factor or added to another register (as well as added to a
1782 displacement). */
1783
1784 #define INDEX_REG_CLASS NO_REGS
1785
1786 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1787 registers explicitly used in the rtl to be used as spill registers
1788 but prevents the compiler from extending the lifetime of these
1789 registers. */
1790
1791 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1792
1793 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1794 is the default value (allocate the registers in numeric order). We
1795 define it just so that we can override it for the mips16 target in
1796 ORDER_REGS_FOR_LOCAL_ALLOC. */
1797
1798 #define REG_ALLOC_ORDER \
1799 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1800 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1801 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1802 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1803 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1804 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1805 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1806 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1807 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1808 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1809 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1810 176,177,178,179,180,181,182,183,184,185,186,187 \
1811 }
1812
1813 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1814 to be rearranged based on a particular function. On the mips16, we
1815 want to allocate $24 (T_REG) before other registers for
1816 instructions for which it is possible. */
1817
1818 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1819
1820 /* True if VALUE is an unsigned 6-bit number. */
1821
1822 #define UIMM6_OPERAND(VALUE) \
1823 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1824
1825 /* True if VALUE is a signed 10-bit number. */
1826
1827 #define IMM10_OPERAND(VALUE) \
1828 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1829
1830 /* True if VALUE is a signed 16-bit number. */
1831
1832 #define SMALL_OPERAND(VALUE) \
1833 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1834
1835 /* True if VALUE is an unsigned 16-bit number. */
1836
1837 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1838 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1839
1840 /* True if VALUE can be loaded into a register using LUI. */
1841
1842 #define LUI_OPERAND(VALUE) \
1843 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1844 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1845
1846 /* Return a value X with the low 16 bits clear, and such that
1847 VALUE - X is a signed 16-bit value. */
1848
1849 #define CONST_HIGH_PART(VALUE) \
1850 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1851
1852 #define CONST_LOW_PART(VALUE) \
1853 ((VALUE) - CONST_HIGH_PART (VALUE))
1854
1855 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1856 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1857 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1858
1859 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1860 mips_preferred_reload_class (X, CLASS)
1861
1862 /* The HI and LO registers can only be reloaded via the general
1863 registers. Condition code registers can only be loaded to the
1864 general registers, and from the floating point registers. */
1865
1866 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1867 mips_secondary_reload_class (CLASS, MODE, X, true)
1868 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1869 mips_secondary_reload_class (CLASS, MODE, X, false)
1870
1871 /* Return the maximum number of consecutive registers
1872 needed to represent mode MODE in a register of class CLASS. */
1873
1874 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1875
1876 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1877 mips_cannot_change_mode_class (FROM, TO, CLASS)
1878 \f
1879 /* Stack layout; function entry, exit and calling. */
1880
1881 #define STACK_GROWS_DOWNWARD
1882
1883 /* The offset of the first local variable from the beginning of the frame.
1884 See mips_compute_frame_info for details about the frame layout. */
1885
1886 #define STARTING_FRAME_OFFSET \
1887 (current_function_outgoing_args_size \
1888 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1889
1890 #define RETURN_ADDR_RTX mips_return_addr
1891
1892 /* Since the mips16 ISA mode is encoded in the least-significant bit
1893 of the address, mask it off return addresses for purposes of
1894 finding exception handling regions. */
1895
1896 #define MASK_RETURN_ADDR GEN_INT (-2)
1897
1898
1899 /* Similarly, don't use the least-significant bit to tell pointers to
1900 code from vtable index. */
1901
1902 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1903
1904 /* The eliminations to $17 are only used for mips16 code. See the
1905 definition of HARD_FRAME_POINTER_REGNUM. */
1906
1907 #define ELIMINABLE_REGS \
1908 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1909 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1910 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1911 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1912 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1913 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1914
1915 /* Make sure that we're not trying to eliminate to the wrong hard frame
1916 pointer. */
1917 #define CAN_ELIMINATE(FROM, TO) \
1918 ((TO) == HARD_FRAME_POINTER_REGNUM || (TO) == STACK_POINTER_REGNUM)
1919
1920 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1921 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1922
1923 /* Allocate stack space for arguments at the beginning of each function. */
1924 #define ACCUMULATE_OUTGOING_ARGS 1
1925
1926 /* The argument pointer always points to the first argument. */
1927 #define FIRST_PARM_OFFSET(FNDECL) 0
1928
1929 /* o32 and o64 reserve stack space for all argument registers. */
1930 #define REG_PARM_STACK_SPACE(FNDECL) \
1931 (TARGET_OLDABI \
1932 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1933 : 0)
1934
1935 /* Define this if it is the responsibility of the caller to
1936 allocate the area reserved for arguments passed in registers.
1937 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1938 of this macro is to determine whether the space is included in
1939 `current_function_outgoing_args_size'. */
1940 #define OUTGOING_REG_PARM_STACK_SPACE 1
1941
1942 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1943 \f
1944 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1945
1946 /* Symbolic macros for the registers used to return integer and floating
1947 point values. */
1948
1949 #define GP_RETURN (GP_REG_FIRST + 2)
1950 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1951
1952 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1953
1954 /* Symbolic macros for the first/last argument registers. */
1955
1956 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1957 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1958 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1959 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1960
1961 #define LIBCALL_VALUE(MODE) \
1962 mips_function_value (NULL_TREE, MODE)
1963
1964 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1965 mips_function_value (VALTYPE, VOIDmode)
1966
1967 /* 1 if N is a possible register number for a function value.
1968 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1969 Currently, R2 and F0 are only implemented here (C has no complex type) */
1970
1971 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1972 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1973 && (N) == FP_RETURN + 2))
1974
1975 /* 1 if N is a possible register number for function argument passing.
1976 We have no FP argument registers when soft-float. When FP registers
1977 are 32 bits, we can't directly reference the odd numbered ones. */
1978
1979 #define FUNCTION_ARG_REGNO_P(N) \
1980 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1981 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1982 && !fixed_regs[N])
1983 \f
1984 /* This structure has to cope with two different argument allocation
1985 schemes. Most MIPS ABIs view the arguments as a structure, of which
1986 the first N words go in registers and the rest go on the stack. If I
1987 < N, the Ith word might go in Ith integer argument register or in a
1988 floating-point register. For these ABIs, we only need to remember
1989 the offset of the current argument into the structure.
1990
1991 The EABI instead allocates the integer and floating-point arguments
1992 separately. The first N words of FP arguments go in FP registers,
1993 the rest go on the stack. Likewise, the first N words of the other
1994 arguments go in integer registers, and the rest go on the stack. We
1995 need to maintain three counts: the number of integer registers used,
1996 the number of floating-point registers used, and the number of words
1997 passed on the stack.
1998
1999 We could keep separate information for the two ABIs (a word count for
2000 the standard ABIs, and three separate counts for the EABI). But it
2001 seems simpler to view the standard ABIs as forms of EABI that do not
2002 allocate floating-point registers.
2003
2004 So for the standard ABIs, the first N words are allocated to integer
2005 registers, and mips_function_arg decides on an argument-by-argument
2006 basis whether that argument should really go in an integer register,
2007 or in a floating-point one. */
2008
2009 typedef struct mips_args {
2010 /* Always true for varargs functions. Otherwise true if at least
2011 one argument has been passed in an integer register. */
2012 int gp_reg_found;
2013
2014 /* The number of arguments seen so far. */
2015 unsigned int arg_number;
2016
2017 /* The number of integer registers used so far. For all ABIs except
2018 EABI, this is the number of words that have been added to the
2019 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2020 unsigned int num_gprs;
2021
2022 /* For EABI, the number of floating-point registers used so far. */
2023 unsigned int num_fprs;
2024
2025 /* The number of words passed on the stack. */
2026 unsigned int stack_words;
2027
2028 /* On the mips16, we need to keep track of which floating point
2029 arguments were passed in general registers, but would have been
2030 passed in the FP regs if this were a 32-bit function, so that we
2031 can move them to the FP regs if we wind up calling a 32-bit
2032 function. We record this information in fp_code, encoded in base
2033 four. A zero digit means no floating point argument, a one digit
2034 means an SFmode argument, and a two digit means a DFmode argument,
2035 and a three digit is not used. The low order digit is the first
2036 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2037 an SFmode argument. ??? A more sophisticated approach will be
2038 needed if MIPS_ABI != ABI_32. */
2039 int fp_code;
2040
2041 /* True if the function has a prototype. */
2042 int prototype;
2043 } CUMULATIVE_ARGS;
2044
2045 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2046 for a call to a function whose data type is FNTYPE.
2047 For a library call, FNTYPE is 0. */
2048
2049 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2050 mips_init_cumulative_args (&CUM, FNTYPE)
2051
2052 /* Update the data in CUM to advance over an argument
2053 of mode MODE and data type TYPE.
2054 (TYPE is null for libcalls where that information may not be available.) */
2055
2056 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2057 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
2058
2059 /* Determine where to put an argument to a function.
2060 Value is zero to push the argument on the stack,
2061 or a hard register in which to store the argument.
2062
2063 MODE is the argument's machine mode.
2064 TYPE is the data type of the argument (as a tree).
2065 This is null for libcalls where that information may
2066 not be available.
2067 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2068 the preceding args and about the function being called.
2069 NAMED is nonzero if this argument is a named parameter
2070 (otherwise it is an extra parameter matching an ellipsis). */
2071
2072 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2073 mips_function_arg (&CUM, MODE, TYPE, NAMED)
2074
2075 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2076
2077 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2078 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2079
2080 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2081 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2082
2083 /* True if using EABI and varargs can be passed in floating-point
2084 registers. Under these conditions, we need a more complex form
2085 of va_list, which tracks GPR, FPR and stack arguments separately. */
2086 #define EABI_FLOAT_VARARGS_P \
2087 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2088
2089 \f
2090 /* Say that the epilogue uses the return address register. Note that
2091 in the case of sibcalls, the values "used by the epilogue" are
2092 considered live at the start of the called function.
2093
2094 If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
2095 See the comment above load_call<mode> for details. */
2096 #define EPILOGUE_USES(REGNO) \
2097 ((REGNO) == 31 || (TARGET_USE_GOT && (REGNO) == GOT_VERSION_REGNUM))
2098
2099 /* Treat LOC as a byte offset from the stack pointer and round it up
2100 to the next fully-aligned offset. */
2101 #define MIPS_STACK_ALIGN(LOC) \
2102 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2103
2104 \f
2105 /* Output assembler code to FILE to increment profiler label # LABELNO
2106 for profiling a function entry. */
2107
2108 #define FUNCTION_PROFILER(FILE, LABELNO) \
2109 { \
2110 if (TARGET_MIPS16) \
2111 sorry ("mips16 function profiling"); \
2112 fprintf (FILE, "\t.set\tnoat\n"); \
2113 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2114 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2115 if (!TARGET_NEWABI) \
2116 { \
2117 fprintf (FILE, \
2118 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2119 TARGET_64BIT ? "dsubu" : "subu", \
2120 reg_names[STACK_POINTER_REGNUM], \
2121 reg_names[STACK_POINTER_REGNUM], \
2122 Pmode == DImode ? 16 : 8); \
2123 } \
2124 fprintf (FILE, "\tjal\t_mcount\n"); \
2125 fprintf (FILE, "\t.set\tat\n"); \
2126 }
2127
2128 /* The profiler preserves all interesting registers, including $31. */
2129 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2130
2131 /* No mips port has ever used the profiler counter word, so don't emit it
2132 or the label for it. */
2133
2134 #define NO_PROFILE_COUNTERS 1
2135
2136 /* Define this macro if the code for function profiling should come
2137 before the function prologue. Normally, the profiling code comes
2138 after. */
2139
2140 /* #define PROFILE_BEFORE_PROLOGUE */
2141
2142 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2143 the stack pointer does not matter. The value is tested only in
2144 functions that have frame pointers.
2145 No definition is equivalent to always zero. */
2146
2147 #define EXIT_IGNORE_STACK 1
2148
2149 \f
2150 /* A C statement to output, on the stream FILE, assembler code for a
2151 block of data that contains the constant parts of a trampoline.
2152 This code should not include a label--the label is taken care of
2153 automatically. */
2154
2155 #define TRAMPOLINE_TEMPLATE(STREAM) \
2156 { \
2157 if (ptr_mode == DImode) \
2158 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2159 else \
2160 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2161 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2162 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2163 if (ptr_mode == DImode) \
2164 { \
2165 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2166 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2167 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2168 } \
2169 else \
2170 { \
2171 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2172 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2173 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2174 } \
2175 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2176 if (ptr_mode == DImode) \
2177 { \
2178 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2179 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2180 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2181 } \
2182 else \
2183 { \
2184 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2185 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2186 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2187 } \
2188 }
2189
2190 /* A C expression for the size in bytes of the trampoline, as an
2191 integer. */
2192
2193 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2194
2195 /* Alignment required for trampolines, in bits. */
2196
2197 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2198
2199 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2200 program and data caches. */
2201
2202 #ifndef CACHE_FLUSH_FUNC
2203 #define CACHE_FLUSH_FUNC "_flush_cache"
2204 #endif
2205
2206 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2207 /* Flush both caches. We need to flush the data cache in case \
2208 the system has a write-back cache. */ \
2209 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2210 0, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2211 GEN_INT (3), TYPE_MODE (integer_type_node))
2212
2213 /* A C statement to initialize the variable parts of a trampoline.
2214 ADDR is an RTX for the address of the trampoline; FNADDR is an
2215 RTX for the address of the nested function; STATIC_CHAIN is an
2216 RTX for the static chain value that should be passed to the
2217 function when it is called. */
2218
2219 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2220 { \
2221 rtx func_addr, chain_addr, end_addr; \
2222 \
2223 func_addr = plus_constant (ADDR, 32); \
2224 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2225 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2226 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2227 end_addr = gen_reg_rtx (Pmode); \
2228 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2229 GEN_INT (TRAMPOLINE_SIZE))); \
2230 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2231 }
2232 \f
2233 /* Addressing modes, and classification of registers for them. */
2234
2235 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2236 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2237 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2238
2239 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2240 and check its validity for a certain class.
2241 We have two alternate definitions for each of them.
2242 The usual definition accepts all pseudo regs; the other rejects them all.
2243 The symbol REG_OK_STRICT causes the latter definition to be used.
2244
2245 Most source files want to accept pseudo regs in the hope that
2246 they will get allocated to the class that the insn wants them to be in.
2247 Some source files that are used after register allocation
2248 need to be strict. */
2249
2250 #ifndef REG_OK_STRICT
2251 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2252 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2253 #else
2254 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2255 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2256 #endif
2257
2258 #define REG_OK_FOR_INDEX_P(X) 0
2259
2260 \f
2261 /* Maximum number of registers that can appear in a valid memory address. */
2262
2263 #define MAX_REGS_PER_ADDRESS 1
2264
2265 #ifdef REG_OK_STRICT
2266 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2267 { \
2268 if (mips_legitimate_address_p (MODE, X, 1)) \
2269 goto ADDR; \
2270 }
2271 #else
2272 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2273 { \
2274 if (mips_legitimate_address_p (MODE, X, 0)) \
2275 goto ADDR; \
2276 }
2277 #endif
2278
2279 /* Check for constness inline but use mips_legitimate_address_p
2280 to check whether a constant really is an address. */
2281
2282 #define CONSTANT_ADDRESS_P(X) \
2283 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2284
2285 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2286
2287 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2288 do { \
2289 if (mips_legitimize_address (&(X), MODE)) \
2290 goto WIN; \
2291 } while (0)
2292
2293
2294 /* A C statement or compound statement with a conditional `goto
2295 LABEL;' executed if memory address X (an RTX) can have different
2296 meanings depending on the machine mode of the memory reference it
2297 is used for.
2298
2299 Autoincrement and autodecrement addresses typically have
2300 mode-dependent effects because the amount of the increment or
2301 decrement is the size of the operand being addressed. Some
2302 machines have other mode-dependent addresses. Many RISC machines
2303 have no mode-dependent addresses.
2304
2305 You may assume that ADDR is a valid address for the machine. */
2306
2307 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2308
2309 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2310 'the start of the function that this code is output in'. */
2311
2312 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2313 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2314 asm_fprintf ((FILE), "%U%s", \
2315 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2316 else \
2317 asm_fprintf ((FILE), "%U%s", (NAME))
2318 \f
2319 /* Flag to mark a function decl symbol that requires a long call. */
2320 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2321 #define SYMBOL_REF_LONG_CALL_P(X) \
2322 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2323
2324 /* True if we're generating a form of MIPS16 code in which jump tables
2325 are stored in the text section and encoded as 16-bit PC-relative
2326 offsets. This is only possible when general text loads are allowed,
2327 since the table access itself will be an "lh" instruction. */
2328 /* ??? 16-bit offsets can overflow in large functions. */
2329 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2330
2331 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2332
2333 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2334
2335 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2336
2337 /* Define this as 1 if `char' should by default be signed; else as 0. */
2338 #ifndef DEFAULT_SIGNED_CHAR
2339 #define DEFAULT_SIGNED_CHAR 1
2340 #endif
2341
2342 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2343 we generally don't want to use them for copying arbitrary data.
2344 A single N-word move is usually the same cost as N single-word moves. */
2345 #define MOVE_MAX UNITS_PER_WORD
2346 #define MAX_MOVE_MAX 8
2347
2348 /* Define this macro as a C expression which is nonzero if
2349 accessing less than a word of memory (i.e. a `char' or a
2350 `short') is no faster than accessing a word of memory, i.e., if
2351 such access require more than one instruction or if there is no
2352 difference in cost between byte and (aligned) word loads.
2353
2354 On RISC machines, it tends to generate better code to define
2355 this as 1, since it avoids making a QI or HI mode register.
2356
2357 But, generating word accesses for -mips16 is generally bad as shifts
2358 (often extended) would be needed for byte accesses. */
2359 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2360
2361 /* Define this to be nonzero if shift instructions ignore all but the low-order
2362 few bits. */
2363 #define SHIFT_COUNT_TRUNCATED 1
2364
2365 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2366 is done just by pretending it is already truncated. */
2367 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2368 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2369
2370
2371 /* Specify the machine mode that pointers have.
2372 After generation of rtl, the compiler makes no further distinction
2373 between pointers and any other objects of this machine mode. */
2374
2375 #ifndef Pmode
2376 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2377 #endif
2378
2379 /* Give call MEMs SImode since it is the "most permissive" mode
2380 for both 32-bit and 64-bit targets. */
2381
2382 #define FUNCTION_MODE SImode
2383
2384 \f
2385 /* A C expression for the cost of moving data from a register in
2386 class FROM to one in class TO. The classes are expressed using
2387 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2388 the default; other values are interpreted relative to that.
2389
2390 It is not required that the cost always equal 2 when FROM is the
2391 same as TO; on some machines it is expensive to move between
2392 registers if they are not general registers.
2393
2394 If reload sees an insn consisting of a single `set' between two
2395 hard registers, and if `REGISTER_MOVE_COST' applied to their
2396 classes returns a value of 2, reload does not check to ensure
2397 that the constraints of the insn are met. Setting a cost of
2398 other than 2 will allow reload to verify that the constraints are
2399 met. You should do this if the `movM' pattern's constraints do
2400 not allow such copying. */
2401
2402 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2403 mips_register_move_cost (MODE, FROM, TO)
2404
2405 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2406 (mips_cost->memory_latency \
2407 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2408
2409 /* Define if copies to/from condition code registers should be avoided.
2410
2411 This is needed for the MIPS because reload_outcc is not complete;
2412 it needs to handle cases where the source is a general or another
2413 condition code register. */
2414 #define AVOID_CCMODE_COPIES
2415
2416 /* A C expression for the cost of a branch instruction. A value of
2417 1 is the default; other values are interpreted relative to that. */
2418
2419 #define BRANCH_COST mips_branch_cost
2420 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2421
2422 /* If defined, modifies the length assigned to instruction INSN as a
2423 function of the context in which it is used. LENGTH is an lvalue
2424 that contains the initially computed length of the insn and should
2425 be updated with the correct length of the insn. */
2426 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2427 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2428
2429 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2430 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2431 its operands. */
2432 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2433 "%*" OPCODE "%?\t" OPERANDS "%/"
2434
2435 /* Return the asm template for a call. INSN is the instruction's mnemonic
2436 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2437 of the target.
2438
2439 When generating GOT code without explicit relocation operators,
2440 all calls should use assembly macros. Otherwise, all indirect
2441 calls should use "jr" or "jalr"; we will arrange to restore $gp
2442 afterwards if necessary. Finally, we can only generate direct
2443 calls for -mabicalls by temporarily switching to non-PIC mode. */
2444 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2445 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2446 ? "%*" INSN "\t%" #OPNO "%/" \
2447 : REG_P (OPERANDS[OPNO]) \
2448 ? "%*" INSN "r\t%" #OPNO "%/" \
2449 : TARGET_ABICALLS \
2450 ? (".option\tpic0\n\t" \
2451 "%*" INSN "\t%" #OPNO "%/\n\t" \
2452 ".option\tpic2") \
2453 : "%*" INSN "\t%" #OPNO "%/")
2454 \f
2455 /* Control the assembler format that we output. */
2456
2457 /* Output to assembler file text saying following lines
2458 may contain character constants, extra white space, comments, etc. */
2459
2460 #ifndef ASM_APP_ON
2461 #define ASM_APP_ON " #APP\n"
2462 #endif
2463
2464 /* Output to assembler file text saying following lines
2465 no longer contain unusual constructs. */
2466
2467 #ifndef ASM_APP_OFF
2468 #define ASM_APP_OFF " #NO_APP\n"
2469 #endif
2470
2471 #define REGISTER_NAMES \
2472 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2473 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2474 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2475 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2476 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2477 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2478 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2479 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2480 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2481 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2482 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2483 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2484 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2485 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2486 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2487 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2488 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2489 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2490 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2491 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2492 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2493 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2494 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2495 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2496
2497 /* List the "software" names for each register. Also list the numerical
2498 names for $fp and $sp. */
2499
2500 #define ADDITIONAL_REGISTER_NAMES \
2501 { \
2502 { "$29", 29 + GP_REG_FIRST }, \
2503 { "$30", 30 + GP_REG_FIRST }, \
2504 { "at", 1 + GP_REG_FIRST }, \
2505 { "v0", 2 + GP_REG_FIRST }, \
2506 { "v1", 3 + GP_REG_FIRST }, \
2507 { "a0", 4 + GP_REG_FIRST }, \
2508 { "a1", 5 + GP_REG_FIRST }, \
2509 { "a2", 6 + GP_REG_FIRST }, \
2510 { "a3", 7 + GP_REG_FIRST }, \
2511 { "t0", 8 + GP_REG_FIRST }, \
2512 { "t1", 9 + GP_REG_FIRST }, \
2513 { "t2", 10 + GP_REG_FIRST }, \
2514 { "t3", 11 + GP_REG_FIRST }, \
2515 { "t4", 12 + GP_REG_FIRST }, \
2516 { "t5", 13 + GP_REG_FIRST }, \
2517 { "t6", 14 + GP_REG_FIRST }, \
2518 { "t7", 15 + GP_REG_FIRST }, \
2519 { "s0", 16 + GP_REG_FIRST }, \
2520 { "s1", 17 + GP_REG_FIRST }, \
2521 { "s2", 18 + GP_REG_FIRST }, \
2522 { "s3", 19 + GP_REG_FIRST }, \
2523 { "s4", 20 + GP_REG_FIRST }, \
2524 { "s5", 21 + GP_REG_FIRST }, \
2525 { "s6", 22 + GP_REG_FIRST }, \
2526 { "s7", 23 + GP_REG_FIRST }, \
2527 { "t8", 24 + GP_REG_FIRST }, \
2528 { "t9", 25 + GP_REG_FIRST }, \
2529 { "k0", 26 + GP_REG_FIRST }, \
2530 { "k1", 27 + GP_REG_FIRST }, \
2531 { "gp", 28 + GP_REG_FIRST }, \
2532 { "sp", 29 + GP_REG_FIRST }, \
2533 { "fp", 30 + GP_REG_FIRST }, \
2534 { "ra", 31 + GP_REG_FIRST }, \
2535 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2536 }
2537
2538 /* This is meant to be redefined in the host dependent files. It is a
2539 set of alternative names and regnums for mips coprocessors. */
2540
2541 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2542
2543 #define PRINT_OPERAND mips_print_operand
2544 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2545 #define PRINT_OPERAND_ADDRESS mips_print_operand_address
2546
2547 /* A C statement, to be executed after all slot-filler instructions
2548 have been output. If necessary, call `dbr_sequence_length' to
2549 determine the number of slots filled in a sequence (zero if not
2550 currently outputting a sequence), to decide how many no-ops to
2551 output, or whatever.
2552
2553 Don't define this macro if it has nothing to do, but it is
2554 helpful in reading assembly output if the extent of the delay
2555 sequence is made explicit (e.g. with white space).
2556
2557 Note that output routines for instructions with delay slots must
2558 be prepared to deal with not being output as part of a sequence
2559 (i.e. when the scheduling pass is not run, or when no slot
2560 fillers could be found.) The variable `final_sequence' is null
2561 when not processing a sequence, otherwise it contains the
2562 `sequence' rtx being output. */
2563
2564 #define DBR_OUTPUT_SEQEND(STREAM) \
2565 do \
2566 { \
2567 if (set_nomacro > 0 && --set_nomacro == 0) \
2568 fputs ("\t.set\tmacro\n", STREAM); \
2569 \
2570 if (set_noreorder > 0 && --set_noreorder == 0) \
2571 fputs ("\t.set\treorder\n", STREAM); \
2572 \
2573 fputs ("\n", STREAM); \
2574 } \
2575 while (0)
2576
2577 /* How to tell the debugger about changes of source files. */
2578 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
2579
2580 /* mips-tfile does not understand .stabd directives. */
2581 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2582 dbxout_begin_stabn_sline (LINE); \
2583 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2584 } while (0)
2585
2586 /* Use .loc directives for SDB line numbers. */
2587 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2588 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2589
2590 /* The MIPS implementation uses some labels for its own purpose. The
2591 following lists what labels are created, and are all formed by the
2592 pattern $L[a-z].*. The machine independent portion of GCC creates
2593 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2594
2595 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2596 $Lb[0-9]+ Begin blocks for MIPS debug support
2597 $Lc[0-9]+ Label for use in s<xx> operation.
2598 $Le[0-9]+ End blocks for MIPS debug support */
2599
2600 #undef ASM_DECLARE_OBJECT_NAME
2601 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2602 mips_declare_object (STREAM, NAME, "", ":\n")
2603
2604 /* Globalizing directive for a label. */
2605 #define GLOBAL_ASM_OP "\t.globl\t"
2606
2607 /* This says how to define a global common symbol. */
2608
2609 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2610
2611 /* This says how to define a local common symbol (i.e., not visible to
2612 linker). */
2613
2614 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2615 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2616 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2617 #endif
2618
2619 /* This says how to output an external. It would be possible not to
2620 output anything and let undefined symbol become external. However
2621 the assembler uses length information on externals to allocate in
2622 data/sdata bss/sbss, thereby saving exec time. */
2623
2624 #undef ASM_OUTPUT_EXTERNAL
2625 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2626 mips_output_external(STREAM,DECL,NAME)
2627
2628 /* This is how to declare a function name. The actual work of
2629 emitting the label is moved to function_prologue, so that we can
2630 get the line number correctly emitted before the .ent directive,
2631 and after any .file directives. Define as empty so that the function
2632 is not declared before the .ent directive elsewhere. */
2633
2634 #undef ASM_DECLARE_FUNCTION_NAME
2635 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2636
2637 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2638 #define FUNCTION_NAME_ALREADY_DECLARED 0
2639 #endif
2640
2641 /* This is how to store into the string LABEL
2642 the symbol_ref name of an internal numbered label where
2643 PREFIX is the class of label and NUM is the number within the class.
2644 This is suitable for output with `assemble_name'. */
2645
2646 #undef ASM_GENERATE_INTERNAL_LABEL
2647 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2648 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2649
2650 /* This is how to output an element of a case-vector that is absolute. */
2651
2652 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2653 fprintf (STREAM, "\t%s\t%sL%d\n", \
2654 ptr_mode == DImode ? ".dword" : ".word", \
2655 LOCAL_LABEL_PREFIX, \
2656 VALUE)
2657
2658 /* This is how to output an element of a case-vector. We can make the
2659 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2660 is supported. */
2661
2662 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2663 do { \
2664 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2665 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2666 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2667 else if (TARGET_GPWORD) \
2668 fprintf (STREAM, "\t%s\t%sL%d\n", \
2669 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2670 LOCAL_LABEL_PREFIX, VALUE); \
2671 else if (TARGET_RTP_PIC) \
2672 { \
2673 /* Make the entry relative to the start of the function. */ \
2674 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2675 fprintf (STREAM, "\t%s\t%sL%d-", \
2676 Pmode == DImode ? ".dword" : ".word", \
2677 LOCAL_LABEL_PREFIX, VALUE); \
2678 assemble_name (STREAM, XSTR (fnsym, 0)); \
2679 fprintf (STREAM, "\n"); \
2680 } \
2681 else \
2682 fprintf (STREAM, "\t%s\t%sL%d\n", \
2683 ptr_mode == DImode ? ".dword" : ".word", \
2684 LOCAL_LABEL_PREFIX, VALUE); \
2685 } while (0)
2686
2687 /* This is how to output an assembler line
2688 that says to advance the location counter
2689 to a multiple of 2**LOG bytes. */
2690
2691 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2692 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2693
2694 /* This is how to output an assembler line to advance the location
2695 counter by SIZE bytes. */
2696
2697 #undef ASM_OUTPUT_SKIP
2698 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2699 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2700
2701 /* This is how to output a string. */
2702 #undef ASM_OUTPUT_ASCII
2703 #define ASM_OUTPUT_ASCII mips_output_ascii
2704
2705 /* Output #ident as a in the read-only data section. */
2706 #undef ASM_OUTPUT_IDENT
2707 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2708 { \
2709 const char *p = STRING; \
2710 int size = strlen (p) + 1; \
2711 switch_to_section (readonly_data_section); \
2712 assemble_string (p, size); \
2713 }
2714 \f
2715 /* Default to -G 8 */
2716 #ifndef MIPS_DEFAULT_GVALUE
2717 #define MIPS_DEFAULT_GVALUE 8
2718 #endif
2719
2720 /* Define the strings to put out for each section in the object file. */
2721 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2722 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2723
2724 #undef READONLY_DATA_SECTION_ASM_OP
2725 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2726 \f
2727 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2728 do \
2729 { \
2730 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2731 TARGET_64BIT ? "daddiu" : "addiu", \
2732 reg_names[STACK_POINTER_REGNUM], \
2733 reg_names[STACK_POINTER_REGNUM], \
2734 TARGET_64BIT ? "sd" : "sw", \
2735 reg_names[REGNO], \
2736 reg_names[STACK_POINTER_REGNUM]); \
2737 } \
2738 while (0)
2739
2740 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2741 do \
2742 { \
2743 if (! set_noreorder) \
2744 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2745 \
2746 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2747 TARGET_64BIT ? "ld" : "lw", \
2748 reg_names[REGNO], \
2749 reg_names[STACK_POINTER_REGNUM], \
2750 TARGET_64BIT ? "daddu" : "addu", \
2751 reg_names[STACK_POINTER_REGNUM], \
2752 reg_names[STACK_POINTER_REGNUM]); \
2753 \
2754 if (! set_noreorder) \
2755 fprintf (STREAM, "\t.set\treorder\n"); \
2756 } \
2757 while (0)
2758
2759 /* How to start an assembler comment.
2760 The leading space is important (the mips native assembler requires it). */
2761 #ifndef ASM_COMMENT_START
2762 #define ASM_COMMENT_START " #"
2763 #endif
2764 \f
2765 /* Default definitions for size_t and ptrdiff_t. We must override the
2766 definitions from ../svr4.h on mips-*-linux-gnu. */
2767
2768 #undef SIZE_TYPE
2769 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2770
2771 #undef PTRDIFF_TYPE
2772 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2773
2774 /* The maximum number of bytes that can be copied by one iteration of
2775 a movmemsi loop; see mips_block_move_loop. */
2776 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2777 (UNITS_PER_WORD * 4)
2778
2779 /* The maximum number of bytes that can be copied by a straight-line
2780 implementation of movmemsi; see mips_block_move_straight. We want
2781 to make sure that any loop-based implementation will iterate at
2782 least twice. */
2783 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2784 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2785
2786 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2787 values were determined experimentally by benchmarking with CSiBE.
2788 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2789 for o32 where we have to restore $gp afterwards as well as make an
2790 indirect call), but in practice, bumping this up higher for
2791 TARGET_ABICALLS doesn't make much difference to code size. */
2792
2793 #define MIPS_CALL_RATIO 8
2794
2795 /* Any loop-based implementation of movmemsi will have at least
2796 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2797 moves, so allow individual copies of fewer elements.
2798
2799 When movmemsi is not available, use a value approximating
2800 the length of a memcpy call sequence, so that move_by_pieces
2801 will generate inline code if it is shorter than a function call.
2802 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2803 we'll have to generate a load/store pair for each, halve the
2804 value of MIPS_CALL_RATIO to take that into account. */
2805
2806 #define MOVE_RATIO \
2807 (HAVE_movmemsi \
2808 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2809 : MIPS_CALL_RATIO / 2)
2810
2811 /* movmemsi is meant to generate code that is at least as good as
2812 move_by_pieces. However, movmemsi effectively uses a by-pieces
2813 implementation both for moves smaller than a word and for word-aligned
2814 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
2815 allow the tree-level optimisers to do such moves by pieces, as it
2816 often exposes other optimization opportunities. We might as well
2817 continue to use movmemsi at the rtl level though, as it produces
2818 better code when scheduling is disabled (such as at -O). */
2819
2820 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2821 (HAVE_movmemsi \
2822 ? (!currently_expanding_to_rtl \
2823 && ((ALIGN) < BITS_PER_WORD \
2824 ? (SIZE) < UNITS_PER_WORD \
2825 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
2826 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2827 < (unsigned int) MOVE_RATIO))
2828
2829 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2830 of the length of a memset call, but use the default otherwise. */
2831
2832 #define CLEAR_RATIO \
2833 (optimize_size ? MIPS_CALL_RATIO : 15)
2834
2835 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2836 optimizing for size adjust the ratio to account for the overhead of
2837 loading the constant and replicating it across the word. */
2838
2839 #define SET_RATIO \
2840 (optimize_size ? MIPS_CALL_RATIO - 2 : 15)
2841
2842 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2843 in that case each word takes 3 insns (lui, ori, sw), or more in
2844 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2845 and let the move_by_pieces code copy the string from read-only
2846 memory. In the future, this could be tuned further for multi-issue
2847 CPUs that can issue stores down one pipe and arithmetic instructions
2848 down another; in that case, the lui/ori/sw combination would be a
2849 win for long enough strings. */
2850
2851 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2852 \f
2853 #ifndef __mips16
2854 /* Since the bits of the _init and _fini function is spread across
2855 many object files, each potentially with its own GP, we must assume
2856 we need to load our GP. We don't preserve $gp or $ra, since each
2857 init/fini chunk is supposed to initialize $gp, and crti/crtn
2858 already take care of preserving $ra and, when appropriate, $gp. */
2859 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2860 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2861 asm (SECTION_OP "\n\
2862 .set noreorder\n\
2863 bal 1f\n\
2864 nop\n\
2865 1: .cpload $31\n\
2866 .set reorder\n\
2867 jal " USER_LABEL_PREFIX #FUNC "\n\
2868 " TEXT_SECTION_ASM_OP);
2869 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2870 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2871 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2872 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2873 asm (SECTION_OP "\n\
2874 .set noreorder\n\
2875 bal 1f\n\
2876 nop\n\
2877 1: .set reorder\n\
2878 .cpsetup $31, $2, 1b\n\
2879 jal " USER_LABEL_PREFIX #FUNC "\n\
2880 " TEXT_SECTION_ASM_OP);
2881 #endif
2882 #endif
2883
2884 #ifndef HAVE_AS_TLS
2885 #define HAVE_AS_TLS 0
2886 #endif
2887
2888 /* Return an asm string that atomically:
2889
2890 - Compares memory reference %1 to register %2 and, if they are
2891 equal, changes %1 to %3.
2892
2893 - Sets register %0 to the old value of memory reference %1.
2894
2895 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
2896 and OP is the instruction that should be used to load %3 into a
2897 register. */
2898 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
2899 "%(%<%[%|sync\n" \
2900 "1:\tll" SUFFIX "\t%0,%1\n" \
2901 "\tbne\t%0,%z2,2f\n" \
2902 "\t" OP "\t%@,%3\n" \
2903 "\tsc" SUFFIX "\t%@,%1\n" \
2904 "\tbeq\t%@,%.,1b\n" \
2905 "\tnop\n" \
2906 "2:\tsync%-%]%>%)"
2907
2908 /* Return an asm string that atomically:
2909
2910 - Sets memory reference %0 to %0 INSN %1.
2911
2912 SUFFIX is the suffix that should be added to "ll" and "sc"
2913 instructions. */
2914 #define MIPS_SYNC_OP(SUFFIX, INSN) \
2915 "%(%<%[%|sync\n" \
2916 "1:\tll" SUFFIX "\t%@,%0\n" \
2917 "\t" INSN "\t%@,%@,%1\n" \
2918 "\tsc" SUFFIX "\t%@,%0\n" \
2919 "\tbeq\t%@,%.,1b\n" \
2920 "\tnop\n" \
2921 "\tsync%-%]%>%)"
2922
2923 /* Return an asm string that atomically:
2924
2925 - Sets memory reference %1 to %1 INSN %2.
2926
2927 - Sets register %0 to the old value of memory reference %1.
2928
2929 SUFFIX is the suffix that should be added to "ll" and "sc"
2930 instructions. */
2931 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
2932 "%(%<%[%|sync\n" \
2933 "1:\tll" SUFFIX "\t%0,%1\n" \
2934 "\t" INSN "\t%@,%0,%2\n" \
2935 "\tsc" SUFFIX "\t%@,%1\n" \
2936 "\tbeq\t%@,%.,1b\n" \
2937 "\tnop\n" \
2938 "\tsync%-%]%>%)"
2939
2940 /* Return an asm string that atomically:
2941
2942 - Sets memory reference %1 to %1 INSN %2.
2943
2944 - Sets register %0 to the new value of memory reference %1.
2945
2946 SUFFIX is the suffix that should be added to "ll" and "sc"
2947 instructions. */
2948 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
2949 "%(%<%[%|sync\n" \
2950 "1:\tll" SUFFIX "\t%0,%1\n" \
2951 "\t" INSN "\t%@,%0,%2\n" \
2952 "\tsc" SUFFIX "\t%@,%1\n" \
2953 "\tbeq\t%@,%.,1b\n" \
2954 "\t" INSN "\t%0,%0,%2\n" \
2955 "\tsync%-%]%>%)"
2956
2957 /* Return an asm string that atomically:
2958
2959 - Sets memory reference %0 to ~%0 AND %1.
2960
2961 SUFFIX is the suffix that should be added to "ll" and "sc"
2962 instructions. INSN is the and instruction needed to and a register
2963 with %2. */
2964 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
2965 "%(%<%[%|sync\n" \
2966 "1:\tll" SUFFIX "\t%@,%0\n" \
2967 "\tnor\t%@,%@,%.\n" \
2968 "\t" INSN "\t%@,%@,%1\n" \
2969 "\tsc" SUFFIX "\t%@,%0\n" \
2970 "\tbeq\t%@,%.,1b\n" \
2971 "\tnop\n" \
2972 "\tsync%-%]%>%)"
2973
2974 /* Return an asm string that atomically:
2975
2976 - Sets memory reference %1 to ~%1 AND %2.
2977
2978 - Sets register %0 to the old value of memory reference %1.
2979
2980 SUFFIX is the suffix that should be added to "ll" and "sc"
2981 instructions. INSN is the and instruction needed to and a register
2982 with %2. */
2983 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
2984 "%(%<%[%|sync\n" \
2985 "1:\tll" SUFFIX "\t%0,%1\n" \
2986 "\tnor\t%@,%0,%.\n" \
2987 "\t" INSN "\t%@,%@,%2\n" \
2988 "\tsc" SUFFIX "\t%@,%1\n" \
2989 "\tbeq\t%@,%.,1b\n" \
2990 "\tnop\n" \
2991 "\tsync%-%]%>%)"
2992
2993 /* Return an asm string that atomically:
2994
2995 - Sets memory reference %1 to ~%1 AND %2.
2996
2997 - Sets register %0 to the new value of memory reference %1.
2998
2999 SUFFIX is the suffix that should be added to "ll" and "sc"
3000 instructions. INSN is the and instruction needed to and a register
3001 with %2. */
3002 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
3003 "%(%<%[%|sync\n" \
3004 "1:\tll" SUFFIX "\t%0,%1\n" \
3005 "\tnor\t%0,%0,%.\n" \
3006 "\t" INSN "\t%@,%0,%2\n" \
3007 "\tsc" SUFFIX "\t%@,%1\n" \
3008 "\tbeq\t%@,%.,1b\n" \
3009 "\t" INSN "\t%0,%0,%2\n" \
3010 "\tsync%-%]%>%)"
3011
3012 /* Return an asm string that atomically:
3013
3014 - Sets memory reference %1 to %2.
3015
3016 - Sets register %0 to the old value of memory reference %1.
3017
3018 SUFFIX is the suffix that should be added to "ll" and "sc"
3019 instructions. OP is the and instruction that should be used to
3020 load %2 into a register. */
3021 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3022 "%(%<%[%|\n" \
3023 "1:\tll" SUFFIX "\t%0,%1\n" \
3024 "\t" OP "\t%@,%2\n" \
3025 "\tsc" SUFFIX "\t%@,%1\n" \
3026 "\tbeq\t%@,%.,1b\n" \
3027 "\tnop\n" \
3028 "\tsync%-%]%>%)"
3029
3030 #ifndef USED_FOR_TARGET
3031 extern const enum reg_class mips_regno_to_class[];
3032 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3033 extern bool mips_print_operand_punct[256];
3034 extern const char *current_function_file; /* filename current function is in */
3035 extern int num_source_filenames; /* current .file # */
3036 extern int set_noreorder; /* # of nested .set noreorder's */
3037 extern int set_nomacro; /* # of nested .set nomacro's */
3038 extern int mips_dbx_regno[];
3039 extern int mips_dwarf_regno[];
3040 extern bool mips_split_p[];
3041 extern GTY(()) rtx cmp_operands[2];
3042 extern enum processor_type mips_arch; /* which cpu to codegen for */
3043 extern enum processor_type mips_tune; /* which cpu to schedule for */
3044 extern int mips_isa; /* architectural level */
3045 extern int mips_abi; /* which ABI to use */
3046 extern const struct mips_cpu_info *mips_arch_info;
3047 extern const struct mips_cpu_info *mips_tune_info;
3048 extern const struct mips_rtx_cost_data *mips_cost;
3049 extern enum mips_code_readable_setting mips_code_readable;
3050 #endif
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