1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;;- Information about MCF5200 port.
24 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
25 ;;- 68k ISA. Differences include reduced support for byte and word
26 ;;- operands and the removal of BCD, bitfield, rotate, and integer
27 ;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the
28 ;;- removed opcodes and addressing modes off.
32 ;;- instruction definitions
34 ;;- @@The original PO technology requires these to be ordered by speed,
35 ;;- @@ so that assigner will pick the fastest.
37 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
39 ;;- When naming insn's (operand 0 of define_insn) be careful about using
40 ;;- names from other targets machine descriptions.
42 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
43 ;;- updates for most instructions.
45 ;;- Operand classes for the register allocator:
46 ;;- 'a' one of the address registers can be used.
47 ;;- 'd' one of the data registers can be used.
48 ;;- 'f' one of the m68881/fpu registers can be used
49 ;;- 'r' either a data or an address register can be used.
51 ;;- Immediate Floating point operator constraints
52 ;;- 'G' a floating point constant that is *NOT* one of the standard
53 ;; 68881 constant values (to force calling output_move_const_double
54 ;; to get it from rom if it is a 68881 constant).
56 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
59 ;;- Immediate integer operand constraints:
61 ;;- 'J' -32768 .. 32767
62 ;;- 'K' all integers EXCEPT -128 .. 127
64 ;;- 'M' all integers EXCEPT -256 .. 255
70 ;;- "%." size separator ("." or "") move%.l d0,d1
71 ;;- "%-" push operand "sp@-" move%.l d0,%-
72 ;;- "%+" pop operand "sp@+" move%.l d0,%+
73 ;;- "%@" top of stack "sp@" move%.l d0,%@
74 ;;- "%!" fpcr register
75 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
76 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
78 ;;- Information about 68040 port.
80 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
81 ;;- be emulated in software by the OS. It is faster to avoid these
82 ;;- instructions and issue a library call rather than trapping into
83 ;;- the kernel. The affected instructions are fintrz and fscale. The
84 ;;- TUNE_68040 flag turns the use of the opcodes off.
86 ;;- The '040 also implements a set of new floating-point instructions
87 ;;- which specify the rounding precision in the opcode. This finally
88 ;;- permit the 68k series to be truly IEEE compliant, and solves all
89 ;;- issues of excess precision accumulating in the extended registers.
90 ;;- By default, GCC does not use these instructions, since such code will
91 ;;- not run on an '030. To use these instructions, use the -m68040-only
94 ;;- These new instructions aren't directly in the md. They are brought
95 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
98 ;;- Information about 68060 port.
100 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
101 ;;- be emulated in software by the OS. It is faster to avoid these
102 ;;- instructions and issue a library call rather than trapping into
103 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
104 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
105 ;;- fscale. The TUNE_68060 flag turns the use of the opcodes off.
107 ;;- Some of these insn's are composites of several m68000 op codes.
108 ;;- The assembler (or final @@??) insures that the appropriate one is
120 ;; UNSPEC_VOLATILE usage:
123 [(UNSPECV_BLOCKAGE 0)
126 ;; Registers by name.
137 (include "predicates.md")
138 (include "constraints.md")
140 ;; ::::::::::::::::::::
144 ;; ::::::::::::::::::::
147 (define_attr "cpu" "cf_v2, unknown" (const (symbol_ref "m68k_sched_cpu")))
150 ;; Basically, an asm pattern.
152 "add_l, addq_l, asr_l, bcc, bclr, bra, bset, bsr,
153 clr_b, clr_w, clr_l, cmp_l,
154 ext_w, extb_l, ext_l,
155 fadd, fcmp, fdiv, ff1, fintrz, fmove, fmul, fsqrt, fsub, ftst, jmp, jsr,
158 move_b, move_w, move_l, moveq_l, mov3q_l, mvs_b, mvs_w, mvz_b, mvz_w,
159 muls_w, muls_l, mulu_w, mulu_l,
163 trap, tst_b, tst_l, tst_w,
165 (const_string "unknown"))
167 ;; Instruction type for use in scheduling description.
168 ;; _l and _w suffixes indicate size of the operands of instruction.
169 ;; alu - usual arithmetic or logic instruction.
170 ;; alu_reg1 - arithmetic or logic instruction with one operand that is
172 ;; alu_regx - arithmetic or logic instruction which has a register for its
174 ;; aluq - arithmetic or logic instruction which has a quick immediate (the one
175 ;; that is encoded in the instruction word) for its Y operand.
176 ;; <all other values> - corresponding asm instructions.
178 "alu_l, alu_reg1, alu_regx, aluq_l, bcc, bra, bsr, clr, cmp_l, jmp, jsr, lea,
179 mov3q_l, move, move_l, moveq_l, mul_l, mul_w, pea, rts, tst, tst_l, unlk,
181 (cond [(eq_attr "type" "add_l,sub_l") (const_string "alu_l")
182 (eq_attr "type" "ext_w,extb_l,ext_l,neg_l,not_l")
183 (const_string "alu_reg1")
184 (eq_attr "type" "asr_l,lsr_l") (const_string "alu_regx")
185 (eq_attr "type" "addq_l,subq_l") (const_string "aluq_l")
186 (eq_attr "type" "bcc") (const_string "bcc")
187 (eq_attr "type" "bra") (const_string "bra")
188 (eq_attr "type" "bsr") (const_string "bsr")
189 (eq_attr "type" "clr_b,clr_l,clr_w") (const_string "clr")
190 (eq_attr "type" "cmp_l") (const_string "cmp_l")
191 (eq_attr "type" "jmp") (const_string "jmp")
192 (eq_attr "type" "jsr") (const_string "jsr")
193 (eq_attr "type" "lea") (const_string "lea")
194 (eq_attr "type" "mov3q_l") (const_string "mov3q_l")
195 (eq_attr "type" "move_b,move_w") (const_string "move")
196 (eq_attr "type" "move_l") (const_string "move_l")
197 (eq_attr "type" "moveq_l") (const_string "moveq_l")
198 (eq_attr "type" "muls_l,mulu_l") (const_string "mul_l")
199 (eq_attr "type" "muls_w,mulu_w") (const_string "mul_w")
200 (eq_attr "type" "pea") (const_string "pea")
201 (eq_attr "type" "rts") (const_string "rts")
202 (eq_attr "type" "tst_b,tst_w") (const_string "tst")
203 (eq_attr "type" "tst_l") (const_string "tst_l")
204 (eq_attr "type" "unlk") (const_string "unlk")]
205 (const_string "unknown")))
207 ;; Index of the X or Y operand in recog_data.operand[].
208 ;; Should be used only within opx_type and opy_type.
209 (define_attr "opx" "" (const_int 0))
210 (define_attr "opy" "" (const_int 1))
212 ;; Type of the X operand.
213 ;; See m68k.c: enum attr_op_type.
214 (define_attr "opx_type"
215 "none, reg, mem1, mem234, mem5, mem6, mem7, imm_q, imm_w, imm_l"
216 (cond [(eq_attr "type1" "rts,unlk") (const_string "none")
217 (eq_attr "type1" "alu_reg1,alu_regx,lea,moveq_l,mul_l,mul_w")
219 (eq_attr "type1" "pea") (const_string "mem1")
220 (eq_attr "type1" "bcc") (const_string "imm_q")
221 (eq_attr "type1" "bra,bsr") (const_string "imm_w")
222 (eq_attr "type1" "jmp,jsr")
223 (symbol_ref "m68k_sched_attr_opx_type (insn, 1)")]
224 (symbol_ref "m68k_sched_attr_opx_type (insn, 0)")))
226 ;; Type of the Y operand.
227 ;; See m68k.c: enum attr_op_type.
228 (define_attr "opy_type"
229 "none, reg, mem1, mem234, mem5, mem6, mem7, imm_q, imm_w, imm_l"
230 (cond [(eq_attr "type1" "alu_reg1,bcc,bra,bsr,clr,jmp,jsr,rts,tst,tst_l,
231 unlk") (const_string "none")
232 (eq_attr "type1" "mov3q_l,moveq_l,aluq_l") (const_string "imm_q")
233 (eq_attr "type1" "lea,pea")
234 (symbol_ref "m68k_sched_attr_opy_type (insn, 1)")]
235 (symbol_ref "m68k_sched_attr_opy_type (insn, 0)")))
237 ;; Instruction size in words.
238 (define_attr "size" ""
239 (cond [(eq_attr "type1" "alu_reg1,moveq_l,rts,unlk") (const_int 1)]
240 (symbol_ref "m68k_sched_attr_size (insn)")))
242 ;; Access to the X operand: none, read, write, read/write, unknown.
243 ;; Access to the Y operand is either none (if opy_type is none)
244 ;; or read otherwise.
245 (define_attr "opx_access" "none, r, w, rw, unknown"
246 (cond [(eq_attr "type1" "rts,unlk") (const_string "none")
247 (eq_attr "type1" "bcc,bra,bsr,cmp_l,jmp,jsr,tst,tst_l")
249 (eq_attr "type1" "clr,lea,mov3q_l,move,move_l,moveq_l,pea")
251 (eq_attr "type1" "alu_l,alu_reg1,alu_regx,aluq_l")
253 (const_string "unknown")))
255 ;; Memory relation of operands:
256 ;; r - register or immediate operand
257 ;; m - non-indexed memory location
258 ;; i - indexed memory location
260 (define_attr "opx_mem" "r, m, i, unknown"
261 (cond [(eq_attr "opx_type" "none,reg,imm_q,imm_w,imm_l") (const_string "r")
262 (eq_attr "opx_type" "mem1,mem234,mem5,mem7") (const_string "m")
263 (eq_attr "opx_type" "mem6") (const_string "i")]
264 (const_string "unknown")))
266 (define_attr "opy_mem" "r, m, i, unknown"
267 (cond [(eq_attr "opy_type" "none,reg,imm_q,imm_w,imm_l") (const_string "r")
268 (eq_attr "opy_type" "mem1,mem234,mem5,mem7") (const_string "m")
269 (eq_attr "opy_type" "mem6") (const_string "i")]
270 (const_string "unknown")))
272 ;; Memory accesses of the insn.
273 ;; 00 - no memory references
274 ;; 10 - memory is read
275 ;; i10 - indexed memory is read
276 ;; 01 - memory is written
277 ;; 0i1 - indexed memory is written
278 ;; 11 - memory is read, memory is written
279 ;; i11 - indexed memory is read, memory is written
280 ;; 1i1 - memory is read, indexed memory is written
282 ;; unknown - should now occur on normal insn.
283 ;; ??? This attribute is implemented in C to spare genattrtab from
284 ;; ??? optimizing it.
285 (define_attr "op_mem" "00, 10, i0, 01, 0i, 11, i1, 1i, unknown"
286 ; (cond [(and (eq_attr "opy_mem" "r") (eq_attr "opx_mem" "r"))
287 ; (const_string "00")
289 ; (and (eq_attr "opy_mem" "r") (eq_attr "opx_mem" "m"))
290 ; (cond [(eq_attr "opx_access" "r") (const_string "10")
291 ; (eq_attr "opx_access" "w") (const_string "01")
292 ; (eq_attr "opx_access" "rw") (const_string "11")]
293 ; (const_string "unknown"))
295 ; (and (eq_attr "opy_mem" "r") (eq_attr "opx_mem" "i"))
296 ; (cond [(eq_attr "opx_access" "r") (const_string "i0")
297 ; (eq_attr "opx_access" "w") (const_string "0i")
298 ; (eq_attr "opx_access" "rw") (const_string "i1")]
299 ; (const_string "unknown"))
301 ; (and (eq_attr "opy_mem" "m") (eq_attr "opx_mem" "r"))
302 ; (const_string "10")
304 ; (and (eq_attr "opy_mem" "m") (eq_attr "opx_mem" "m"))
305 ; (cond [(eq_attr "opx_access" "w") (const_string "11")]
306 ; (const_string "unknown"))
308 ; (and (eq_attr "opy_mem" "m") (eq_attr "opx_mem" "i"))
309 ; (cond [(eq_attr "opx_access" "w") (const_string "1i")]
310 ; (const_string "unknown"))
312 ; (and (eq_attr "opy_mem" "i") (eq_attr "opx_mem" "r"))
313 ; (const_string "i0")
315 ; (and (eq_attr "opy_mem" "i") (eq_attr "opx_mem" "m"))
316 ; (cond [(eq_attr "opx_access" "w") (const_string "i1")]
317 ; (const_string "unknown"))]
318 ; (const_string "unknown"))
319 (symbol_ref "m68k_sched_attr_op_mem (insn)"))
321 ;; Attribute to support partial automata description.
322 ;; This attribute has value 'yes' for instructions that are not
323 ;; fully handled yet.
324 (define_attr "guess" "yes, no"
325 (cond [(ior (eq (symbol_ref "reload_completed") (const_int 0))
326 (eq_attr "type1" "unknown"))
327 (const_string "yes")]
328 (const_string "no")))
330 ;; Attribute to support statistics gathering.
331 ;; Todo means that insn lacks something to get pipeline description.
332 ;; Done means that insn was transformed to suit pipeline description.
333 ;; Nothing means that insn was originally good enough for scheduling.
334 (define_attr "split" "todo, done, nothing"
335 (if_then_else (eq_attr "type" "unknown")
336 (const_string "todo")
337 (const_string "nothing")))
339 ;; Mode macros for floating point operations.
340 ;; Valid floating point modes
341 (define_mode_iterator FP [SF DF (XF "TARGET_68881")])
342 ;; Mnemonic infix to round result
343 (define_mode_attr round [(SF "%$") (DF "%&") (XF "")])
344 ;; Mnemonic infix to round result for mul or div instruction
345 (define_mode_attr round_mul [(SF "sgl") (DF "%&") (XF "")])
346 ;; Suffix specifying source operand format
347 (define_mode_attr prec [(SF "s") (DF "d") (XF "x")])
348 ;; Allowable D registers
349 (define_mode_attr dreg [(SF "d") (DF "") (XF "")])
350 ;; Allowable 68881 constant constraints
351 (define_mode_attr const [(SF "F") (DF "G") (XF "")])
354 (define_insn_and_split "*movdf_internal"
355 [(set (match_operand:DF 0 "push_operand" "=m, m")
356 (match_operand:DF 1 "general_operand" "f, ro<>E"))]
361 "&& reload_completed && (extract_constrain_insn_cached (insn), which_alternative == 1)"
364 m68k_emit_move_double (operands);
367 [(set_attr "type" "fmove,*")
368 (set_attr "split" "done,*")])
370 (define_insn_and_split "pushdi"
371 [(set (match_operand:DI 0 "push_operand" "=m")
372 (match_operand:DI 1 "general_operand" "ro<>Fi"))]
375 "&& reload_completed"
378 m68k_emit_move_double (operands);
382 ;; We don't want to allow a constant operand for test insns because
383 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
384 ;; be folded while optimizing anyway.
386 (define_expand "tstdi"
387 [(parallel [(set (cc0)
388 (match_operand:DI 0 "nonimmediate_operand" ""))
389 (clobber (match_scratch:SI 1 ""))
390 (clobber (match_scratch:DI 2 ""))])]
392 "m68k_last_compare_had_fp_operands = 0;")
396 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
397 (clobber (match_scratch:SI 1 "=X,d"))
398 (clobber (match_scratch:DI 2 "=d,X"))]
401 if (which_alternative == 0)
405 xoperands[0] = operands[2];
406 xoperands[1] = operands[0];
407 output_move_double (xoperands);
408 cc_status.flags |= CC_REVERSED; /*|*/
409 return "neg%.l %R2\;negx%.l %2";
411 if (find_reg_note (insn, REG_DEAD, operands[0]))
413 cc_status.flags |= CC_REVERSED; /*|*/
414 return "neg%.l %R0\;negx%.l %0";
418 'sub' clears %1, and also clears the X cc bit
419 'tst' sets the Z cc bit according to the low part of the DImode operand
420 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part.
422 return "sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0";
425 (define_expand "tstsi"
427 (match_operand:SI 0 "nonimmediate_operand" ""))]
429 "m68k_last_compare_had_fp_operands = 0;")
431 ;; If you think that the 68020 does not support tstl a0,
432 ;; reread page B-167 of the 68020 manual more carefully.
433 (define_insn "*tstsi_internal_68020_cf"
435 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
436 "TARGET_68020 || TARGET_COLDFIRE"
438 [(set_attr "type" "tst_l")])
440 ;; On an address reg, cmpw may replace cmpl.
441 (define_insn "*tstsi_internal"
443 (match_operand:SI 0 "nonimmediate_operand" "dm,r"))]
444 "!(TARGET_68020 || TARGET_COLDFIRE)"
448 [(set_attr "type" "tst_l,*")])
450 ;; This can't use an address register, because comparisons
451 ;; with address registers as second operand always test the whole word.
452 (define_expand "tsthi"
454 (match_operand:HI 0 "nonimmediate_operand" ""))]
456 "m68k_last_compare_had_fp_operands = 0;")
458 (define_insn "*tsthi_internal"
460 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
463 [(set_attr "type" "tst_w")])
465 (define_expand "tstqi"
467 (match_operand:QI 0 "nonimmediate_operand" ""))]
469 "m68k_last_compare_had_fp_operands = 0;")
471 (define_insn "*tstqi_internal"
473 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
476 [(set_attr "type" "tst_b")])
478 (define_expand "tst<mode>"
480 (match_operand:FP 0 "general_operand" ""))]
483 m68k_last_compare_had_fp_operands = 1;
486 (define_insn "tst<mode>_68881"
488 (match_operand:FP 0 "general_operand" "f<FP:dreg>m"))]
491 cc_status.flags = CC_IN_68881;
492 if (FP_REG_P (operands[0]))
494 return "ftst%.<FP:prec> %0";
497 (define_insn "tst<mode>_cf"
499 (match_operand:FP 0 "general_operand" "f<FP:dreg><Q>U"))]
500 "TARGET_COLDFIRE_FPU"
502 cc_status.flags = CC_IN_68881;
503 if (FP_REG_P (operands[0]))
505 return "ftst%.<FP:prec> %0";
507 [(set_attr "type" "ftst")])
510 ;; compare instructions.
512 (define_expand "cmpdi"
515 (compare (match_operand:DI 0 "nonimmediate_operand" "")
516 (match_operand:DI 1 "general_operand" "")))
517 (clobber (match_dup 2))])]
519 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
523 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
524 (match_operand:DI 2 "general_operand" "d,0")))
525 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
528 if (rtx_equal_p (operands[0], operands[1]))
529 return "sub%.l %R2,%R0\;subx%.l %2,%0";
532 cc_status.flags |= CC_REVERSED; /*|*/
533 return "sub%.l %R1,%R0\;subx%.l %1,%0";
537 (define_expand "cmpsi"
539 (compare (match_operand:SI 0 "nonimmediate_operand" "")
540 (match_operand:SI 1 "general_operand" "")))]
543 m68k_last_compare_had_fp_operands = 0;
546 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
549 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
550 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
553 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
554 return "cmpm%.l %1,%0";
555 if (REG_P (operands[1])
556 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
558 cc_status.flags |= CC_REVERSED; /*|*/
559 return "cmp%.l %d0,%d1";
561 if (ADDRESS_REG_P (operands[0])
562 && GET_CODE (operands[1]) == CONST_INT
563 && INTVAL (operands[1]) < 0x8000
564 && INTVAL (operands[1]) >= -0x8000)
565 return "cmp%.w %1,%0";
566 return "cmp%.l %d1,%d0";
569 (define_insn "*cmpsi_cf"
571 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
572 (match_operand:SI 1 "general_operand" "r,mrKs")))]
575 if (REG_P (operands[1])
576 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
578 cc_status.flags |= CC_REVERSED; /*|*/
579 return "cmp%.l %d0,%d1";
581 return "cmp%.l %d1,%d0";
583 [(set_attr "type" "cmp_l")])
585 (define_expand "cmphi"
587 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
588 (match_operand:HI 1 "general_src_operand" "")))]
590 "m68k_last_compare_had_fp_operands = 0;")
594 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
595 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
598 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
599 return "cmpm%.w %1,%0";
600 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
601 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
603 cc_status.flags |= CC_REVERSED;
604 return "cmp%.w %d0,%d1";
606 return "cmp%.w %d1,%d0";
609 (define_expand "cmpqi"
611 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
612 (match_operand:QI 1 "general_src_operand" "")))]
614 "m68k_last_compare_had_fp_operands = 0;")
618 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
619 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
622 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
623 return "cmpm%.b %1,%0";
624 if (REG_P (operands[1])
625 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
627 cc_status.flags |= CC_REVERSED; /*|*/
628 return "cmp%.b %d0,%d1";
630 return "cmp%.b %d1,%d0";
633 (define_expand "cmp<mode>"
635 (compare (match_operand:FP 0 "register_operand" "")
636 (match_operand:FP 1 "fp_src_operand" "")))]
638 "m68k_last_compare_had_fp_operands = 1;")
640 (define_insn "*cmp<mode>_68881"
642 (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg>mF")
643 (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg>mF,f")))]
645 && (register_operand (operands[0], <MODE>mode)
646 || register_operand (operands[1], <MODE>mode))"
649 fcmp%.<FP:prec> %f1,%0
650 fcmp%.<FP:prec> %0,%f1"
651 [(set_attr "type" "fcmp")])
653 (define_insn "*cmp<mode>_cf"
655 (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg><Q>U")
656 (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg><Q>U,f")))]
658 && (register_operand (operands[0], <MODE>mode)
659 || register_operand (operands[1], <MODE>mode))"
662 fcmp%.<FP:prec> %f1,%0
663 fcmp%.<FP:prec> %0,%f1"
664 [(set_attr "type" "fcmp")])
666 ;; Recognizers for btst instructions.
668 ;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is
669 ;; specified as a constant, so we must disable all patterns that may extract
670 ;; from a MEM at a constant bit position if we can't use this as a constraint.
673 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
675 (minus:SI (const_int 7)
676 (match_operand:SI 1 "general_operand" "di"))))]
679 return output_btst (operands, operands[1], operands[0], insn, 7);
682 ;; This is the same as the above pattern except for the constraints. The 'i'
686 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
688 (minus:SI (const_int 7)
689 (match_operand:SI 1 "general_operand" "d"))))]
692 return output_btst (operands, operands[1], operands[0], insn, 7);
696 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
698 (minus:SI (const_int 31)
699 (match_operand:SI 1 "general_operand" "di"))))]
702 return output_btst (operands, operands[1], operands[0], insn, 31);
705 ;; The following two patterns are like the previous two
706 ;; except that they use the fact that bit-number operands
707 ;; are automatically masked to 3 or 5 bits.
710 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
712 (minus:SI (const_int 7)
714 (match_operand:SI 1 "register_operand" "d")
718 return output_btst (operands, operands[1], operands[0], insn, 7);
722 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
724 (minus:SI (const_int 31)
726 (match_operand:SI 1 "register_operand" "d")
730 return output_btst (operands, operands[1], operands[0], insn, 31);
733 ;; Nonoffsettable mem refs are ok in this one pattern
734 ;; since we don't try to adjust them.
736 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
738 (match_operand:SI 1 "const_int_operand" "n")))]
739 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
741 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
742 return output_btst (operands, operands[1], operands[0], insn, 7);
746 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
748 (match_operand:SI 1 "const_int_operand" "n")))]
751 if (GET_CODE (operands[0]) == MEM)
753 operands[0] = adjust_address (operands[0], QImode,
754 INTVAL (operands[1]) / 8);
755 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
756 return output_btst (operands, operands[1], operands[0], insn, 7);
758 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
759 return output_btst (operands, operands[1], operands[0], insn, 31);
762 ;; This is the same as the above pattern except for the constraints.
763 ;; The 'o' has been replaced with 'Q'.
766 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
768 (match_operand:SI 1 "const_int_operand" "n")))]
771 if (GET_CODE (operands[0]) == MEM)
773 operands[0] = adjust_address (operands[0], QImode,
774 INTVAL (operands[1]) / 8);
775 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
776 return output_btst (operands, operands[1], operands[0], insn, 7);
778 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
779 return output_btst (operands, operands[1], operands[0], insn, 31);
785 ;; A special case in which it is not desirable
786 ;; to reload the constant into a data register.
787 (define_insn "pushexthisi_const"
788 [(set (match_operand:SI 0 "push_operand" "=m,m,m")
789 (match_operand:SI 1 "const_int_operand" "C0,R,J"))]
790 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
795 [(set_attr "type" "clr_l,mov3q_l,pea")
796 (set_attr "split" "done")])
799 ;(define_insn "swapsi"
800 ; [(set (match_operand:SI 0 "nonimmediate_operand" "+r")
801 ; (match_operand:SI 1 "general_operand" "+r"))
802 ; (set (match_dup 1) (match_dup 0))]
806 ;; Special case of fullword move when source is zero for 68000_10.
807 ;; moveq is faster on the 68000.
808 (define_insn "*movsi_const0_68000_10"
809 [(set (match_operand:SI 0 "movsi_const0_operand" "=d,a,g")
816 [(set_attr "type" "moveq_l,sub_l,clr_l")
817 (set_attr "opy_type" "imm_q,reg,*")
818 (set_attr "split" "done")])
820 ;; Special case of fullword move when source is zero for 68040_60.
821 ;; On the '040, 'subl an,an' takes 2 clocks while lea takes only 1
822 (define_insn "*movsi_const0_68040_60"
823 [(set (match_operand:SI 0 "movsi_const0_operand" "=a,g")
827 if (which_alternative == 0)
828 return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0";
829 else if (which_alternative == 1)
837 [(set_attr "type" "lea,clr_l")
838 (set_attr "opy_type" "imm_w,*")
839 (set_attr "split" "done")])
841 ;; Special case of fullword move when source is zero.
842 (define_insn "*movsi_const0"
843 [(set (match_operand:SI 0 "movsi_const0_operand" "=a,g")
845 "!(TUNE_68000_10 || TUNE_68040_60)"
849 [(set_attr "type" "sub_l,clr_l")
850 (set_attr "opy_type" "reg,*")
851 (set_attr "split" "done")])
853 ;; General case of fullword move.
855 ;; This is the main "hook" for PIC code. When generating
856 ;; PIC, movsi is responsible for determining when the source address
857 ;; needs PIC relocation and appropriately calling legitimize_pic_address
858 ;; to perform the actual relocation.
860 ;; In both the PIC and non-PIC cases the patterns generated will
861 ;; matched by the next define_insn.
862 (define_expand "movsi"
863 [(set (match_operand:SI 0 "" "")
864 (match_operand:SI 1 "" ""))]
867 rtx tmp, base, offset;
869 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
871 /* The source is an address which requires PIC relocation.
872 Call legitimize_pic_address with the source, mode, and a relocation
873 register (a new pseudo, or the final destination if reload_in_progress
874 is set). Then fall through normally */
875 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
876 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
878 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
880 /* Don't allow writes to memory except via a register;
881 the m68k doesn't consider PC-relative addresses to be writable. */
882 if (symbolic_operand (operands[0], SImode))
883 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
884 else if (GET_CODE (operands[0]) == MEM
885 && symbolic_operand (XEXP (operands[0], 0), SImode))
886 operands[0] = gen_rtx_MEM (SImode,
887 force_reg (SImode, XEXP (operands[0], 0)));
889 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
891 split_const (operands[1], &base, &offset);
892 if (GET_CODE (base) == SYMBOL_REF
893 && !offset_within_block_p (base, INTVAL (offset)))
895 tmp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (SImode);
896 emit_move_insn (tmp, base);
897 emit_insn (gen_addsi3 (operands[0], tmp, offset));
903 ;; General case of fullword move.
904 (define_insn "*movsi_m68k"
905 ;; Notes: make sure no alternative allows g vs g.
906 ;; We don't allow f-regs since fixed point cannot go in them.
907 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
908 (match_operand:SI 1 "general_src_operand" "damSnT,n,i"))]
909 "!TARGET_COLDFIRE && reload_completed"
911 return output_move_simode (operands);
914 ;; Before reload is completed the register constraints
915 ;; force integer constants in range for a moveq to be reloaded
916 ;; if they are headed for memory.
917 (define_insn "*movsi_m68k2"
918 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
919 (match_operand:SI 1 "general_src_operand" "damSKT,n,i"))]
923 return output_move_simode (operands);
926 ;; ColdFire move instructions can have at most one operand of mode >= 6.
927 (define_insn "*movsi_cf"
928 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d, d, d, d, d, a,Ap, a, r<Q>,g, U")
929 (match_operand:SI 1 "general_operand" " R,CQ,CW,CZ,CS,Ci,J,J Cs,Cs, g, Rr<Q>,U"))]
932 switch (which_alternative)
935 return "mov3q%.l %1,%0";
938 return "moveq %1,%0";
942 unsigned u = INTVAL (operands[1]);
944 operands[1] = GEN_INT ((u << 16) | (u >> 16)); /*|*/
945 return "moveq %1,%0\n\tswap %0";
949 return "mvz%.w %1,%0";
952 return "mvs%.w %1,%0";
955 return "move%.l %1,%0";
958 return "move%.w %1,%0";
969 return "move%.l %1,%0";
976 [(set_attr "type" "mov3q_l, moveq_l,*, mvz_w, mvs_w, move_l, move_w, pea, lea, move_l, move_l, move_l")
978 (if_then_else (eq_attr "alternative" "2")
980 (const_string "done")))])
982 ;; Special case of fullword move, where we need to get a non-GOT PIC
983 ;; reference into an address register.
985 [(set (match_operand:SI 0 "nonimmediate_operand" "=a<")
986 (match_operand:SI 1 "pcrel_address" ""))]
989 if (push_operand (operands[0], SImode))
994 (define_expand "movhi"
995 [(set (match_operand:HI 0 "nonimmediate_operand" "")
996 (match_operand:HI 1 "general_operand" ""))]
1001 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
1002 (match_operand:HI 1 "general_src_operand" "gS"))]
1004 "* return output_move_himode (operands);")
1007 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g,U")
1008 (match_operand:HI 1 "general_operand" "g,r<Q>,U"))]
1010 "* return output_move_himode (operands);")
1012 (define_expand "movstricthi"
1013 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1014 (match_operand:HI 1 "general_src_operand" ""))]
1019 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
1020 (match_operand:HI 1 "general_src_operand" "rmSn"))]
1022 "* return output_move_stricthi (operands);")
1025 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
1026 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
1028 "* return output_move_stricthi (operands);")
1030 (define_expand "movqi"
1031 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1032 (match_operand:QI 1 "general_src_operand" ""))]
1037 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
1038 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
1040 "* return output_move_qimode (operands);")
1043 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,U,d*a")
1044 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,U,di*a"))]
1046 "* return output_move_qimode (operands);")
1048 (define_expand "movstrictqi"
1049 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1050 (match_operand:QI 1 "general_src_operand" ""))]
1055 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
1056 (match_operand:QI 1 "general_src_operand" "dmSn"))]
1058 "* return output_move_strictqi (operands);")
1060 (define_insn "*movstrictqi_cf"
1061 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d, Ac, d,m"))
1062 (match_operand:QI 1 "general_src_operand" "C0,C0, dmn,d"))]
1069 [(set_attr "type" "clr_b,clr_b,move_b,move_b")
1070 (set_attr "split" "done")])
1072 (define_expand "pushqi1"
1073 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))
1074 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int 1)))
1075 (match_operand:QI 0 "general_operand" ""))]
1079 (define_expand "reload_insf"
1080 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1081 (match_operand:SF 1 "general_operand" "mf"))
1082 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
1083 "TARGET_COLDFIRE_FPU"
1085 if (emit_move_sequence (operands, SFmode, operands[2]))
1088 /* We don't want the clobber emitted, so handle this ourselves. */
1089 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1093 (define_expand "reload_outsf"
1094 [(set (match_operand:SF 0 "general_operand" "")
1095 (match_operand:SF 1 "register_operand" "f"))
1096 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
1097 "TARGET_COLDFIRE_FPU"
1099 if (emit_move_sequence (operands, SFmode, operands[2]))
1102 /* We don't want the clobber emitted, so handle this ourselves. */
1103 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1107 (define_expand "movsf"
1108 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1109 (match_operand:SF 1 "general_operand" ""))]
1114 [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
1115 (match_operand:SF 1 "general_operand" "rmfF"))]
1118 if (FP_REG_P (operands[0]))
1120 if (FP_REG_P (operands[1]))
1121 return "f%$move%.x %1,%0";
1122 else if (ADDRESS_REG_P (operands[1]))
1123 return "move%.l %1,%-\;f%$move%.s %+,%0";
1124 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1125 return output_move_const_single (operands);
1126 return "f%$move%.s %f1,%0";
1128 if (FP_REG_P (operands[1]))
1130 if (ADDRESS_REG_P (operands[0]))
1131 return "fmove%.s %1,%-\;move%.l %+,%0";
1132 return "fmove%.s %f1,%0";
1134 if (operands[1] == CONST0_RTX (SFmode)
1135 /* clr insns on 68000 read before writing. */
1136 && ((TARGET_68010 || TARGET_COLDFIRE)
1137 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1139 if (ADDRESS_REG_P (operands[0]))
1141 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1143 return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0";
1145 return "sub%.l %0,%0";
1147 /* moveq is faster on the 68000. */
1148 if (DATA_REG_P (operands[0]) && TUNE_68000_10)
1149 return "moveq #0,%0";
1152 return "move%.l %1,%0";
1155 (define_insn "movsf_cf_soft"
1156 [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>,g,U")
1157 (match_operand:SF 1 "general_operand" "g,r<Q>,U"))]
1158 "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU"
1160 [(set_attr "type" "move_l")])
1162 ;; SFmode MEMs are restricted to modes 2-4 if TARGET_COLDFIRE_FPU.
1163 ;; The move instructions can handle all combinations.
1164 (define_insn "movsf_cf_hard"
1165 [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>U, f, f,mr,f,r<Q>,f
1167 (match_operand:SF 1 "general_operand" " f, r<Q>U,f,rm,F,F, m
1169 "TARGET_COLDFIRE_FPU"
1171 if (which_alternative == 4 || which_alternative == 5) {
1175 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1176 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1177 xoperands[0] = operands[0];
1178 xoperands[1] = GEN_INT (l);
1179 if (which_alternative == 5) {
1181 if (ADDRESS_REG_P (xoperands[0]))
1182 output_asm_insn ("sub%.l %0,%0", xoperands);
1184 output_asm_insn ("clr%.l %0", xoperands);
1186 if (GET_CODE (operands[0]) == MEM
1187 && symbolic_operand (XEXP (operands[0], 0), SImode))
1188 output_asm_insn ("move%.l %1,%-;move%.l %+,%0", xoperands);
1190 output_asm_insn ("move%.l %1,%0", xoperands);
1194 output_asm_insn ("move%.l %1,%-;fsmove%.s %+,%0", xoperands);
1196 output_asm_insn ("clr%.l %-;fsmove%.s %+,%0", xoperands);
1199 if (FP_REG_P (operands[0]))
1201 if (ADDRESS_REG_P (operands[1]))
1202 return "move%.l %1,%-;fsmove%.s %+,%0";
1203 if (FP_REG_P (operands[1]))
1204 return "fsmove%.d %1,%0";
1205 return "fsmove%.s %f1,%0";
1207 if (FP_REG_P (operands[1]))
1209 if (ADDRESS_REG_P (operands[0]))
1210 return "fmove%.s %1,%-;move%.l %+,%0";
1211 return "fmove%.s %f1,%0";
1213 if (operands[1] == CONST0_RTX (SFmode))
1215 if (ADDRESS_REG_P (operands[0]))
1216 return "sub%.l %0,%0";
1219 return "move%.l %1,%0";
1222 (define_expand "reload_indf"
1223 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1224 (match_operand:DF 1 "general_operand" "mf"))
1225 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
1226 "TARGET_COLDFIRE_FPU"
1228 if (emit_move_sequence (operands, DFmode, operands[2]))
1231 /* We don't want the clobber emitted, so handle this ourselves. */
1232 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1236 (define_expand "reload_outdf"
1237 [(set (match_operand:DF 0 "general_operand" "")
1238 (match_operand:DF 1 "register_operand" "f"))
1239 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
1240 "TARGET_COLDFIRE_FPU"
1242 if (emit_move_sequence (operands, DFmode, operands[2]))
1245 /* We don't want the clobber emitted, so handle this ourselves. */
1246 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1250 (define_expand "movdf"
1251 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1252 (match_operand:DF 1 "general_operand" ""))]
1255 if (TARGET_COLDFIRE_FPU)
1256 if (emit_move_sequence (operands, DFmode, 0))
1261 [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
1262 (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
1263 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
1264 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1267 if (FP_REG_P (operands[0]))
1269 if (FP_REG_P (operands[1]))
1270 return "f%&move%.x %1,%0";
1271 if (REG_P (operands[1]))
1274 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1275 output_asm_insn ("move%.l %1,%-", xoperands);
1276 output_asm_insn ("move%.l %1,%-", operands);
1277 return "f%&move%.d %+,%0";
1279 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1280 return output_move_const_double (operands);
1281 return "f%&move%.d %f1,%0";
1283 else if (FP_REG_P (operands[1]))
1285 if (REG_P (operands[0]))
1287 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1288 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1289 return "move%.l %+,%0";
1292 return "fmove%.d %f1,%0";
1294 return output_move_double (operands);
1297 (define_insn_and_split "movdf_cf_soft"
1298 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
1299 (match_operand:DF 1 "general_operand" "g,r"))]
1300 "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU"
1302 "&& reload_completed"
1305 m68k_emit_move_double (operands);
1309 (define_insn "movdf_cf_hard"
1310 [(set (match_operand:DF 0 "nonimmediate_operand" "=f, <Q>U,r,f,r,r,m,f")
1311 (match_operand:DF 1 "general_operand" " f<Q>U,f, f,r,r,m,r,E"))]
1312 "TARGET_COLDFIRE_FPU"
1318 switch (which_alternative)
1321 return "fdmove%.d %1,%0";
1323 return "fmove%.d %1,%0";
1325 return "fmove%.d %1,%-;move%.l %+,%0;move%.l %+,%R0";
1327 return "move%.l %R1,%-;move%.l %1,%-;fdmove%.d %+,%0";
1328 case 4: case 5: case 6:
1329 return output_move_double (operands);
1331 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1332 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
1333 xoperands[0] = operands[0];
1334 xoperands[1] = GEN_INT (l[0]);
1335 xoperands[2] = GEN_INT (l[1]);
1336 if (operands[1] == CONST0_RTX (DFmode))
1337 output_asm_insn ("clr%.l %-;clr%.l %-;fdmove%.d %+,%0",
1341 output_asm_insn ("clr%.l %-;move%.l %1,%-;fdmove%.d %+,%0",
1344 output_asm_insn ("move%.l %2,%-;move%.l %1,%-;fdmove%.d %+,%0",
1350 ;; ??? The XFmode patterns are schizophrenic about whether constants are
1351 ;; allowed. Most but not all have predicates and constraint that disallow
1352 ;; constants. Most but not all have output templates that handle constants.
1353 ;; See also LEGITIMATE_CONSTANT_P.
1355 (define_expand "movxf"
1356 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1357 (match_operand:XF 1 "general_operand" ""))]
1360 /* We can't rewrite operands during reload. */
1361 if (! reload_in_progress)
1363 if (CONSTANT_P (operands[1]))
1365 operands[1] = force_const_mem (XFmode, operands[1]);
1366 if (! memory_address_p (XFmode, XEXP (operands[1], 0)))
1367 operands[1] = adjust_address (operands[1], XFmode, 0);
1369 if (flag_pic && TARGET_PCREL)
1371 /* Don't allow writes to memory except via a register; the
1372 m68k doesn't consider PC-relative addresses to be writable. */
1373 if (GET_CODE (operands[0]) == MEM
1374 && symbolic_operand (XEXP (operands[0], 0), SImode))
1375 operands[0] = gen_rtx_MEM (XFmode,
1376 force_reg (SImode, XEXP (operands[0], 0)));
1382 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r,m,!r")
1383 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r,!r,m"))]
1386 if (FP_REG_P (operands[0]))
1388 if (FP_REG_P (operands[1]))
1389 return "fmove%.x %1,%0";
1390 if (REG_P (operands[1]))
1393 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1394 output_asm_insn ("move%.l %1,%-", xoperands);
1395 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1396 output_asm_insn ("move%.l %1,%-", xoperands);
1397 output_asm_insn ("move%.l %1,%-", operands);
1398 return "fmove%.x %+,%0";
1400 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1401 return "fmove%.x %1,%0";
1402 return "fmove%.x %f1,%0";
1404 if (FP_REG_P (operands[1]))
1406 if (REG_P (operands[0]))
1408 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
1409 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1410 output_asm_insn ("move%.l %+,%0", operands);
1411 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1412 return "move%.l %+,%0";
1414 /* Must be memory destination. */
1415 return "fmove%.x %f1,%0";
1417 return output_move_double (operands);
1421 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1422 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1423 "! TARGET_68881 && ! TARGET_COLDFIRE"
1425 if (FP_REG_P (operands[0]))
1427 if (FP_REG_P (operands[1]))
1428 return "fmove%.x %1,%0";
1429 if (REG_P (operands[1]))
1432 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1433 output_asm_insn ("move%.l %1,%-", xoperands);
1434 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1435 output_asm_insn ("move%.l %1,%-", xoperands);
1436 output_asm_insn ("move%.l %1,%-", operands);
1437 return "fmove%.x %+,%0";
1439 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1440 return "fmove%.x %1,%0";
1441 return "fmove%.x %f1,%0";
1443 if (FP_REG_P (operands[1]))
1445 if (REG_P (operands[0]))
1447 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
1448 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1449 output_asm_insn ("move%.l %+,%0", operands);
1450 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1451 return "move%.l %+,%0";
1454 return "fmove%.x %f1,%0";
1456 return output_move_double (operands);
1460 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1461 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1462 "! TARGET_68881 && TARGET_COLDFIRE"
1463 "* return output_move_double (operands);")
1465 (define_expand "movdi"
1466 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1467 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1468 (match_operand:DI 1 "general_operand" ""))]
1472 ;; movdi can apply to fp regs in some cases
1474 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1475 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>")
1476 (match_operand:DI 1 "general_operand" "rF,m,roi<>F"))]
1477 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f")
1478 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))]
1479 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1480 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1483 if (FP_REG_P (operands[0]))
1485 if (FP_REG_P (operands[1]))
1486 return "fmove%.x %1,%0";
1487 if (REG_P (operands[1]))
1490 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1491 output_asm_insn ("move%.l %1,%-", xoperands);
1492 output_asm_insn ("move%.l %1,%-", operands);
1493 return "fmove%.d %+,%0";
1495 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1496 return output_move_const_double (operands);
1497 return "fmove%.d %f1,%0";
1499 else if (FP_REG_P (operands[1]))
1501 if (REG_P (operands[0]))
1503 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1504 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1505 return "move%.l %+,%0";
1508 return "fmove%.d %f1,%0";
1510 return output_move_double (operands);
1514 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
1515 (match_operand:DI 1 "general_operand" "g,r"))]
1517 "* return output_move_double (operands);")
1519 ;; Thus goes after the move instructions
1520 ;; because the move instructions are better (require no spilling)
1521 ;; when they can apply. It goes before the add/sub insns
1522 ;; so we will prefer it to them.
1524 (define_insn "pushasi"
1525 [(set (match_operand:SI 0 "push_operand" "=m")
1526 (match_operand:SI 1 "address_operand" "p"))]
1529 [(set_attr "type" "pea")])
1531 ;; truncation instructions
1532 (define_insn "truncsiqi2"
1533 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1535 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1538 if (GET_CODE (operands[0]) == REG)
1540 /* Must clear condition codes, since the move.l bases them on
1541 the entire 32 bits, not just the desired 8 bits. */
1543 return "move%.l %1,%0";
1545 if (GET_CODE (operands[1]) == MEM)
1546 operands[1] = adjust_address (operands[1], QImode, 3);
1547 return "move%.b %1,%0";
1550 (define_insn "trunchiqi2"
1551 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1553 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1556 if (GET_CODE (operands[0]) == REG
1557 && (GET_CODE (operands[1]) == MEM
1558 || GET_CODE (operands[1]) == CONST_INT))
1560 /* Must clear condition codes, since the move.w bases them on
1561 the entire 16 bits, not just the desired 8 bits. */
1563 return "move%.w %1,%0";
1565 if (GET_CODE (operands[0]) == REG)
1567 /* Must clear condition codes, since the move.l bases them on
1568 the entire 32 bits, not just the desired 8 bits. */
1570 return "move%.l %1,%0";
1572 if (GET_CODE (operands[1]) == MEM)
1573 operands[1] = adjust_address (operands[1], QImode, 1);
1574 return "move%.b %1,%0";
1577 (define_insn "truncsihi2"
1578 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
1580 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1583 if (GET_CODE (operands[0]) == REG)
1585 /* Must clear condition codes, since the move.l bases them on
1586 the entire 32 bits, not just the desired 8 bits. */
1588 return "move%.l %1,%0";
1590 if (GET_CODE (operands[1]) == MEM)
1591 operands[1] = adjust_address (operands[1], QImode, 2);
1592 return "move%.w %1,%0";
1595 ;; zero extension instructions
1597 ;; two special patterns to match various post_inc/pre_dec patterns
1598 (define_insn_and_split "*zero_extend_inc"
1599 [(set (match_operand 0 "post_inc_operand" "")
1600 (zero_extend (match_operand 1 "register_operand" "")))]
1601 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT &&
1602 GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT &&
1603 GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2"
1611 operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0);
1614 (define_insn_and_split "*zero_extend_dec"
1615 [(set (match_operand 0 "pre_dec_operand" "")
1616 (zero_extend (match_operand 1 "register_operand" "")))]
1617 "(GET_MODE (operands[0]) != HImode || XEXP (XEXP (operands[0], 0), 0) != stack_pointer_rtx) &&
1618 GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT &&
1619 GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT &&
1620 GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2"
1628 operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0);
1631 (define_insn_and_split "zero_extendqidi2"
1632 [(set (match_operand:DI 0 "register_operand" "")
1633 (zero_extend:DI (match_operand:QI 1 "nonimmediate_src_operand" "")))]
1638 (zero_extend:SI (match_dup 1)))
1642 operands[2] = gen_lowpart (SImode, operands[0]);
1643 operands[3] = gen_highpart (SImode, operands[0]);
1646 (define_insn_and_split "zero_extendhidi2"
1647 [(set (match_operand:DI 0 "register_operand" "")
1648 (zero_extend:DI (match_operand:HI 1 "nonimmediate_src_operand" "")))]
1653 (zero_extend:SI (match_dup 1)))
1657 operands[2] = gen_lowpart (SImode, operands[0]);
1658 operands[3] = gen_highpart (SImode, operands[0]);
1661 (define_expand "zero_extendsidi2"
1662 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1663 (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
1666 if (GET_CODE (operands[0]) == MEM
1667 && GET_CODE (operands[1]) == MEM)
1668 operands[1] = force_reg (SImode, operands[1]);
1671 (define_insn_and_split "*zero_extendsidi2"
1672 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1673 (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
1674 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1682 operands[2] = gen_lowpart (SImode, operands[0]);
1683 operands[3] = gen_highpart (SImode, operands[0]);
1686 (define_insn "*zero_extendhisi2_cf"
1687 [(set (match_operand:SI 0 "register_operand" "=d")
1688 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1691 [(set_attr "type" "mvz_w")])
1693 (define_insn "zero_extendhisi2"
1694 [(set (match_operand:SI 0 "register_operand" "=d")
1695 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1699 (define_expand "zero_extendqihi2"
1700 [(set (match_operand:HI 0 "register_operand" "")
1701 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "")))]
1705 (define_insn "*zero_extendqihi2"
1706 [(set (match_operand:HI 0 "register_operand" "=d")
1707 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1711 (define_insn "*zero_extendqisi2_cfv4"
1712 [(set (match_operand:SI 0 "register_operand" "=d")
1713 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1716 [(set_attr "type" "mvz_b")])
1718 (define_insn "zero_extendqisi2"
1719 [(set (match_operand:SI 0 "register_operand" "=d")
1720 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1724 ;; these two pattern split everything else which isn't matched by
1725 ;; something else above
1727 [(set (match_operand 0 "register_operand" "")
1728 (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
1731 && reg_mentioned_p (operands[0], operands[1])"
1732 [(set (strict_low_part (match_dup 2))
1735 (match_op_dup 4 [(match_dup 0) (match_dup 3)]))]
1737 operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]);
1738 operands[3] = GEN_INT (GET_MODE_MASK (GET_MODE (operands[1])));
1739 operands[4] = gen_rtx_AND (GET_MODE (operands[0]), operands[0], operands[3]);
1743 [(set (match_operand 0 "register_operand" "")
1744 (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
1745 "!ISA_HAS_MVS_MVZ && reload_completed"
1748 (set (strict_low_part (match_dup 2))
1751 operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]);
1754 ;; sign extension instructions
1756 (define_insn "extendqidi2"
1757 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1758 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1762 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1763 if (ISA_HAS_MVS_MVZ)
1764 return "mvs%.b %1,%2\;smi %0\;extb%.l %0";
1765 if (TARGET_68020 || TARGET_COLDFIRE)
1767 if (ADDRESS_REG_P (operands[1]))
1768 return "move%.w %1,%2\;extb%.l %2\;smi %0\;extb%.l %0";
1770 return "move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0";
1774 if (ADDRESS_REG_P (operands[1]))
1775 return "move%.w %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0";
1777 return "move%.b %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0";
1781 (define_insn "extendhidi2"
1782 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1784 (match_operand:HI 1 "general_src_operand" "rmS")))]
1788 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1789 if (ISA_HAS_MVS_MVZ)
1790 return "mvs%.w %1,%2\;smi %0\;extb%.l %0";
1791 if (TARGET_68020 || TARGET_COLDFIRE)
1792 return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0";
1794 return "move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0";
1797 (define_insn "extendsidi2"
1798 [(set (match_operand:DI 0 "register_operand" "=d")
1799 (sign_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "rm")))]
1803 if (TARGET_68020 || TARGET_COLDFIRE)
1804 return "move%.l %1,%R0\;smi %0\;extb%.l %0";
1806 return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0";
1809 (define_insn "*extendsidi2_mem"
1810 [(set (match_operand:DI 0 "memory_operand" "=o,<")
1811 (sign_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "rm,rm")))
1812 (clobber (match_scratch:SI 2 "=d,d"))]
1816 operands[3] = adjust_address (operands[0], SImode,
1817 which_alternative == 0 ? 4 : 0);
1818 operands[0] = adjust_address (operands[0], SImode, 0);
1819 if (TARGET_68020 || TARGET_COLDFIRE)
1820 return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
1822 return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
1825 ;; Special case when one can avoid register clobbering, copy and test
1826 ;; Maybe there is a way to make that the general case, by forcing the
1827 ;; result of the SI tree to be in the lower register of the DI target
1829 (define_insn "extendplussidi"
1830 [(set (match_operand:DI 0 "register_operand" "=d")
1831 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1832 (match_operand:SI 2 "general_operand" "rmn"))))]
1836 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1837 if (GET_CODE (operands[1]) == CONST_INT
1838 && (unsigned) INTVAL (operands[1]) > 8)
1840 rtx tmp = operands[1];
1842 operands[1] = operands[2];
1845 if (GET_CODE (operands[1]) == REG
1846 && REGNO (operands[1]) == REGNO (operands[3]))
1847 output_asm_insn ("add%.l %2,%3", operands);
1849 output_asm_insn ("move%.l %2,%3\;add%.l %1,%3", operands);
1850 if (TARGET_68020 || TARGET_COLDFIRE)
1851 return "smi %0\;extb%.l %0";
1853 return "smi %0\;ext%.w %0\;ext%.l %0";
1856 (define_expand "extendhisi2"
1857 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1859 (match_operand:HI 1 "nonimmediate_src_operand" "")))]
1863 (define_insn "*cfv4_extendhisi2"
1864 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1866 (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1869 [(set_attr "type" "mvs_w")])
1871 (define_insn "*68k_extendhisi2"
1872 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
1874 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1879 [(set_attr "type" "ext_l,move_w")])
1881 (define_insn "extendqihi2"
1882 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
1883 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1886 [(set_attr "type" "ext_w")])
1888 (define_expand "extendqisi2"
1889 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1890 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1891 "TARGET_68020 || TARGET_COLDFIRE"
1894 (define_insn "*cfv4_extendqisi2"
1895 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1896 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))]
1899 [(set_attr "type" "mvs_b")])
1901 (define_insn "*68k_extendqisi2"
1902 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1903 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1904 "TARGET_68020 || (TARGET_COLDFIRE && !ISA_HAS_MVS_MVZ)"
1906 [(set_attr "type" "extb_l")])
1908 ;; Conversions between float and double.
1910 (define_expand "extendsfdf2"
1911 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1913 (match_operand:SF 1 "general_operand" "")))]
1918 [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
1920 (match_operand:SF 1 "general_operand" "f,dmF")))]
1923 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1925 if (REGNO (operands[0]) == REGNO (operands[1]))
1927 /* Extending float to double in an fp-reg is a no-op.
1928 NOTICE_UPDATE_CC has already assumed that the
1929 cc will be set. So cancel what it did. */
1930 cc_status = cc_prev_status;
1933 return "f%&move%.x %1,%0";
1935 if (FP_REG_P (operands[0]))
1936 return "f%&move%.s %f1,%0";
1937 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1939 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1940 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1941 return "move%.l %+,%0";
1943 return "fmove%.d %f1,%0";
1946 (define_insn "extendsfdf2_cf"
1947 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f")
1949 (match_operand:SF 1 "general_operand" "f,<Q>U")))]
1950 "TARGET_COLDFIRE_FPU"
1952 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1954 if (REGNO (operands[0]) == REGNO (operands[1]))
1956 /* Extending float to double in an fp-reg is a no-op.
1957 NOTICE_UPDATE_CC has already assumed that the
1958 cc will be set. So cancel what it did. */
1959 cc_status = cc_prev_status;
1962 return "fdmove%.d %1,%0";
1964 return "fdmove%.s %f1,%0";
1967 ;; This cannot output into an f-reg because there is no way to be
1968 ;; sure of truncating in that case.
1969 (define_expand "truncdfsf2"
1970 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1972 (match_operand:DF 1 "general_operand" "")))]
1976 ;; On the '040 we can truncate in a register accurately and easily.
1978 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1980 (match_operand:DF 1 "general_operand" "fmG")))]
1981 "TARGET_68881 && TARGET_68040"
1983 if (FP_REG_P (operands[1]))
1984 return "f%$move%.x %1,%0";
1985 return "f%$move%.d %f1,%0";
1988 (define_insn "truncdfsf2_cf"
1989 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d<Q>U")
1991 (match_operand:DF 1 "general_operand" "<Q>U,f")))]
1992 "TARGET_COLDFIRE_FPU"
1996 [(set_attr "type" "fmove")])
1998 (define_insn "*truncdfsf2_68881"
1999 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
2001 (match_operand:DF 1 "general_operand" "f")))]
2004 [(set_attr "type" "fmove")])
2006 ;; Conversion between fixed point and floating point.
2007 ;; Note that among the fix-to-float insns
2008 ;; the ones that start with SImode come first.
2009 ;; That is so that an operand that is a CONST_INT
2010 ;; (and therefore lacks a specific machine mode).
2011 ;; will be recognized as SImode (which is always valid)
2012 ;; rather than as QImode or HImode.
2014 (define_expand "floatsi<mode>2"
2015 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2016 (float:FP (match_operand:SI 1 "general_operand" "")))]
2020 (define_insn "floatsi<mode>2_68881"
2021 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2022 (float:FP (match_operand:SI 1 "general_operand" "dmi")))]
2024 "f<FP:round>move%.l %1,%0")
2026 (define_insn "floatsi<mode>2_cf"
2027 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2028 (float:FP (match_operand:SI 1 "general_operand" "d<Q>U")))]
2029 "TARGET_COLDFIRE_FPU"
2030 "f<FP:prec>move%.l %1,%0"
2031 [(set_attr "type" "fmove")])
2034 (define_expand "floathi<mode>2"
2035 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2036 (float:FP (match_operand:HI 1 "general_operand" "")))]
2040 (define_insn "floathi<mode>2_68881"
2041 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2042 (float:FP (match_operand:HI 1 "general_operand" "dmn")))]
2045 [(set_attr "type" "fmove")])
2047 (define_insn "floathi<mode>2_cf"
2048 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2049 (float:FP (match_operand:HI 1 "general_operand" "d<Q>U")))]
2050 "TARGET_COLDFIRE_FPU"
2052 [(set_attr "type" "fmove")])
2055 (define_expand "floatqi<mode>2"
2056 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2057 (float:FP (match_operand:QI 1 "general_operand" "")))]
2061 (define_insn "floatqi<mode>2_68881"
2062 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2063 (float:FP (match_operand:QI 1 "general_operand" "dmn")))]
2066 [(set_attr "type" "fmove")])
2068 (define_insn "floatqi<mode>2_cf"
2069 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2070 (float:FP (match_operand:QI 1 "general_operand" "d<Q>U")))]
2071 "TARGET_COLDFIRE_FPU"
2073 [(set_attr "type" "fmove")])
2076 ;; New routines to convert floating-point values to integers
2077 ;; to be used on the '040. These should be faster than trapping
2078 ;; into the kernel to emulate fintrz. They should also be faster
2079 ;; than calling the subroutines fixsfsi or fixdfsi.
2081 (define_insn "fix_truncdfsi2"
2082 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2083 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2084 (clobber (match_scratch:SI 2 "=d"))
2085 (clobber (match_scratch:SI 3 "=d"))]
2086 "TARGET_68881 && TUNE_68040"
2089 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!";
2092 (define_insn "fix_truncdfhi2"
2093 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
2094 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2095 (clobber (match_scratch:SI 2 "=d"))
2096 (clobber (match_scratch:SI 3 "=d"))]
2097 "TARGET_68881 && TUNE_68040"
2100 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!";
2103 (define_insn "fix_truncdfqi2"
2104 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
2105 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2106 (clobber (match_scratch:SI 2 "=d"))
2107 (clobber (match_scratch:SI 3 "=d"))]
2108 "TARGET_68881 && TUNE_68040"
2111 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!";
2114 ;; Convert a float to a float whose value is an integer.
2115 ;; This is the first stage of converting it to an integer type.
2117 (define_expand "ftrunc<mode>2"
2118 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2119 (fix:FP (match_operand:FP 1 "general_operand" "")))]
2120 "TARGET_HARD_FLOAT && !TUNE_68040"
2123 (define_insn "ftrunc<mode>2_68881"
2124 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2125 (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
2126 "TARGET_68881 && !TUNE_68040"
2128 if (FP_REG_P (operands[1]))
2129 return "fintrz%.x %f1,%0";
2130 return "fintrz%.<FP:prec> %f1,%0";
2133 (define_insn "ftrunc<mode>2_cf"
2134 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2135 (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))]
2136 "TARGET_COLDFIRE_FPU"
2138 if (FP_REG_P (operands[1]))
2139 return "fintrz%.d %f1,%0";
2140 return "fintrz%.<FP:prec> %f1,%0";
2142 [(set_attr "type" "fintrz")])
2144 ;; Convert a float whose value is an integer
2145 ;; to an actual integer. Second stage of converting float to integer type.
2146 (define_expand "fix<mode>qi2"
2147 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2148 (fix:QI (match_operand:FP 1 "general_operand" "")))]
2152 (define_insn "fix<mode>qi2_68881"
2153 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
2154 (fix:QI (match_operand:FP 1 "general_operand" "f")))]
2158 (define_insn "fix<mode>qi2_cf"
2159 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U")
2160 (fix:QI (match_operand:FP 1 "general_operand" "f")))]
2161 "TARGET_COLDFIRE_FPU"
2163 [(set_attr "type" "fmove")])
2165 (define_expand "fix<mode>hi2"
2166 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2167 (fix:HI (match_operand:FP 1 "general_operand" "")))]
2171 (define_insn "fix<mode>hi2_68881"
2172 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
2173 (fix:HI (match_operand:FP 1 "general_operand" "f")))]
2177 (define_insn "fix<mode>hi2_cf"
2178 [(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U")
2179 (fix:HI (match_operand:FP 1 "general_operand" "f")))]
2180 "TARGET_COLDFIRE_FPU"
2182 [(set_attr "type" "fmove")])
2184 (define_expand "fix<mode>si2"
2185 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2186 (fix:SI (match_operand:FP 1 "general_operand" "")))]
2190 (define_insn "fix<mode>si2_68881"
2191 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2192 (fix:SI (match_operand:FP 1 "general_operand" "f")))]
2196 (define_insn "fix<mode>si2_cf"
2197 [(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U")
2198 (fix:SI (match_operand:FP 1 "general_operand" "f")))]
2199 "TARGET_COLDFIRE_FPU"
2201 [(set_attr "type" "fmove")])
2206 (define_insn "adddi_lshrdi_63"
2207 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
2208 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2211 (clobber (match_scratch:SI 2 "=d"))]
2214 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2215 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2217 "move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0";
2218 if (GET_CODE (operands[1]) == REG)
2219 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2220 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2221 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2222 operands[4] = operands[1];
2224 operands[4] = adjust_address (operands[1], SImode, 4);
2225 if (GET_CODE (operands[1]) == MEM
2226 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2227 output_asm_insn ("move%.l %4,%3", operands);
2228 output_asm_insn ("move%.l %1,%0\;smi %2", operands);
2229 if (TARGET_68020 || TARGET_COLDFIRE)
2230 output_asm_insn ("extb%.l %2", operands);
2232 output_asm_insn ("ext%.w %2\;ext%.l %2", operands);
2233 if (GET_CODE (operands[1]) != MEM
2234 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2235 output_asm_insn ("move%.l %4,%3", operands);
2236 return "sub%.l %2,%3\;subx%.l %2,%0";
2239 (define_insn "adddi_sexthishl32"
2240 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2241 (plus:DI (ashift:DI (sign_extend:DI
2242 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2244 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2245 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2249 if (ADDRESS_REG_P (operands[0]))
2250 return "add%.w %1,%0";
2251 else if (ADDRESS_REG_P (operands[3]))
2252 return "move%.w %1,%3\;add%.l %3,%0";
2254 return "move%.w %1,%3\;ext%.l %3\;add%.l %3,%0";
2257 (define_insn "*adddi_dilshr32"
2258 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
2259 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
2261 (match_operand:DI 2 "general_operand" "0,0")))]
2265 if (GET_CODE (operands[0]) == REG)
2266 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2268 operands[2] = adjust_address (operands[0], SImode, 4);
2269 return "add%.l %1,%2\;negx%.l %0\;neg%.l %0";
2272 (define_insn "*adddi_dilshr32_cf"
2273 [(set (match_operand:DI 0 "register_operand" "=d")
2274 (plus:DI (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "ro")
2276 (match_operand:DI 2 "register_operand" "0")))]
2280 return "add%.l %1,%R0\;negx%.l %0\;neg%.l %0";
2283 (define_insn "adddi_dishl32"
2284 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
2285 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2286 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2287 ;; (const_int 32))))]
2288 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d")
2290 (match_operand:DI 2 "general_operand" "0,0")))]
2294 if (GET_CODE (operands[1]) == REG)
2295 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2297 operands[1] = adjust_address (operands[1], SImode, 4);
2298 return "add%.l %1,%0";
2300 [(set_attr "type" "add_l")])
2302 (define_insn "adddi3"
2303 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
2304 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0")
2305 (match_operand:DI 2 "general_operand" "d,no>,d,a")))
2306 (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))]
2309 if (DATA_REG_P (operands[0]))
2311 if (DATA_REG_P (operands[2]))
2312 return "add%.l %R2,%R0\;addx%.l %2,%0";
2313 else if (GET_CODE (operands[2]) == MEM
2314 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2315 return "move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0";
2321 if (GET_CODE (operands[2]) == REG)
2323 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2326 else if (CONSTANT_P (operands[2]))
2327 split_double (operands[2], &high, &low);
2330 low = adjust_address (operands[2], SImode, 4);
2334 operands[1] = low, operands[2] = high;
2335 xoperands[0] = operands[3];
2336 if (GET_CODE (operands[1]) == CONST_INT
2337 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2338 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2340 xoperands[1] = operands[2];
2342 output_asm_insn (output_move_simode (xoperands), xoperands);
2343 if (GET_CODE (operands[1]) == CONST_INT)
2345 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2346 return "addq%.l %1,%R0\;addx%.l %3,%0";
2347 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2349 operands[1] = GEN_INT (-INTVAL (operands[1]));
2350 return "subq%.l %1,%R0\;subx%.l %3,%0";
2353 return "add%.l %1,%R0\;addx%.l %3,%0";
2358 gcc_assert (GET_CODE (operands[0]) == MEM);
2360 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2362 operands[1] = gen_rtx_MEM (SImode,
2363 plus_constant (XEXP(operands[0], 0), -8));
2364 return "move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1";
2366 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2368 operands[1] = XEXP(operands[0], 0);
2369 return "add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1";
2373 operands[1] = adjust_address (operands[0], SImode, 4);
2374 return "add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0";
2379 (define_insn "addsi_lshrsi_31"
2380 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2381 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2386 operands[2] = operands[0];
2387 operands[3] = gen_label_rtx();
2388 if (GET_CODE (operands[0]) == MEM)
2390 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2391 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2392 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2393 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2395 output_asm_insn ("move%.l %1,%0", operands);
2396 output_asm_insn ("jpl %l3", operands);
2397 output_asm_insn ("addq%.l #1,%2", operands);
2398 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2399 CODE_LABEL_NUMBER (operands[3]));
2403 (define_expand "addsi3"
2404 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2405 (plus:SI (match_operand:SI 1 "general_operand" "")
2406 (match_operand:SI 2 "general_src_operand" "")))]
2410 ;; Note that the middle two alternatives are near-duplicates
2411 ;; in order to handle insns generated by reload.
2412 ;; This is needed since they are not themselves reloaded,
2413 ;; so commutativity won't apply to them.
2414 (define_insn "*addsi3_internal"
2415 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
2416 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2417 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2421 "* return output_addsi3 (operands);")
2423 (define_insn_and_split "*addsi3_5200"
2424 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr,mr,m,r, ?a,?a,?a,?a")
2425 (plus:SI (match_operand:SI 1 "general_operand" "%0, 0, 0,0, a, a, r, a")
2426 (match_operand:SI 2 "general_src_operand" " I, L, d,mrKi,Cj,r, a, J")))]
2429 switch (which_alternative)
2432 return "addq%.l %2,%0";
2435 operands[2] = GEN_INT (- INTVAL (operands[2]));
2436 return "subq%.l %2,%0";
2440 return "add%.l %2,%0";
2443 /* move%.l %2,%0\n\tadd%.l %1,%0 */
2447 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2450 return MOTOROLA ? "lea (%2,%1.l),%0" : "lea %2@(0,%1:l),%0";
2453 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2460 "&& reload_completed && (extract_constrain_insn_cached (insn), which_alternative == 4) && !operands_match_p (operands[0], operands[1])"
2464 (plus:SI (match_dup 0)
2467 [(set_attr "type" "addq_l,subq_l,add_l,add_l,*,lea,lea,lea")
2468 (set_attr "opy" "2,2,2,2,*,*,*,*")
2469 (set_attr "opy_type" "*,*,*,*,*,mem6,mem6,mem5")
2470 (set_attr "split" "done,done,done,done,*,done,done,done")])
2473 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2474 (plus:SI (match_operand:SI 1 "general_operand" "0")
2476 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2480 (define_insn "addhi3"
2481 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2482 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2483 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2486 if (GET_CODE (operands[2]) == CONST_INT)
2488 /* If the constant would be a negative number when interpreted as
2489 HImode, make it negative. This is usually, but not always, done
2490 elsewhere in the compiler. First check for constants out of range,
2491 which could confuse us. */
2493 if (INTVAL (operands[2]) >= 32768)
2494 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2496 if (INTVAL (operands[2]) > 0
2497 && INTVAL (operands[2]) <= 8)
2498 return "addq%.w %2,%0";
2499 if (INTVAL (operands[2]) < 0
2500 && INTVAL (operands[2]) >= -8)
2502 operands[2] = GEN_INT (- INTVAL (operands[2]));
2503 return "subq%.w %2,%0";
2505 /* On the CPU32 it is faster to use two addqw instructions to
2506 add a small integer (8 < N <= 16) to a register.
2507 Likewise for subqw. */
2508 if (TUNE_CPU32 && REG_P (operands[0]))
2510 if (INTVAL (operands[2]) > 8
2511 && INTVAL (operands[2]) <= 16)
2513 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2514 return "addq%.w #8,%0\;addq%.w %2,%0";
2516 if (INTVAL (operands[2]) < -8
2517 && INTVAL (operands[2]) >= -16)
2519 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2520 return "subq%.w #8,%0\;subq%.w %2,%0";
2523 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2524 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2526 return "add%.w %2,%0";
2529 ;; These insns must use MATCH_DUP instead of the more expected
2530 ;; use of a matching constraint because the "output" here is also
2531 ;; an input, so you can't use the matching constraint. That also means
2532 ;; that you can't use the "%", so you need patterns with the matched
2533 ;; operand in both positions.
2536 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2537 (plus:HI (match_dup 0)
2538 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2541 if (GET_CODE (operands[1]) == CONST_INT)
2543 /* If the constant would be a negative number when interpreted as
2544 HImode, make it negative. This is usually, but not always, done
2545 elsewhere in the compiler. First check for constants out of range,
2546 which could confuse us. */
2548 if (INTVAL (operands[1]) >= 32768)
2549 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2551 if (INTVAL (operands[1]) > 0
2552 && INTVAL (operands[1]) <= 8)
2553 return "addq%.w %1,%0";
2554 if (INTVAL (operands[1]) < 0
2555 && INTVAL (operands[1]) >= -8)
2557 operands[1] = GEN_INT (- INTVAL (operands[1]));
2558 return "subq%.w %1,%0";
2560 /* On the CPU32 it is faster to use two addqw instructions to
2561 add a small integer (8 < N <= 16) to a register.
2562 Likewise for subqw. */
2563 if (TUNE_CPU32 && REG_P (operands[0]))
2565 if (INTVAL (operands[1]) > 8
2566 && INTVAL (operands[1]) <= 16)
2568 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2569 return "addq%.w #8,%0\;addq%.w %1,%0";
2571 if (INTVAL (operands[1]) < -8
2572 && INTVAL (operands[1]) >= -16)
2574 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2575 return "subq%.w #8,%0\;subq%.w %1,%0";
2578 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2579 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
2581 return "add%.w %1,%0";
2585 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2586 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2590 if (GET_CODE (operands[1]) == CONST_INT)
2592 /* If the constant would be a negative number when interpreted as
2593 HImode, make it negative. This is usually, but not always, done
2594 elsewhere in the compiler. First check for constants out of range,
2595 which could confuse us. */
2597 if (INTVAL (operands[1]) >= 32768)
2598 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2600 if (INTVAL (operands[1]) > 0
2601 && INTVAL (operands[1]) <= 8)
2602 return "addq%.w %1,%0";
2603 if (INTVAL (operands[1]) < 0
2604 && INTVAL (operands[1]) >= -8)
2606 operands[1] = GEN_INT (- INTVAL (operands[1]));
2607 return "subq%.w %1,%0";
2609 /* On the CPU32 it is faster to use two addqw instructions to
2610 add a small integer (8 < N <= 16) to a register.
2611 Likewise for subqw. */
2612 if (TUNE_CPU32 && REG_P (operands[0]))
2614 if (INTVAL (operands[1]) > 8
2615 && INTVAL (operands[1]) <= 16)
2617 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2618 return "addq%.w #8,%0\;addq%.w %1,%0";
2620 if (INTVAL (operands[1]) < -8
2621 && INTVAL (operands[1]) >= -16)
2623 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2624 return "subq%.w #8,%0\;subq%.w %1,%0";
2627 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2628 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
2630 return "add%.w %1,%0";
2633 (define_insn "addqi3"
2634 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2635 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2636 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2639 if (GET_CODE (operands[2]) == CONST_INT)
2641 if (INTVAL (operands[2]) >= 128)
2642 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2644 if (INTVAL (operands[2]) > 0
2645 && INTVAL (operands[2]) <= 8)
2646 return "addq%.b %2,%0";
2647 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2649 operands[2] = GEN_INT (- INTVAL (operands[2]));
2650 return "subq%.b %2,%0";
2653 return "add%.b %2,%0";
2657 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2658 (plus:QI (match_dup 0)
2659 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2662 if (GET_CODE (operands[1]) == CONST_INT)
2664 if (INTVAL (operands[1]) >= 128)
2665 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2667 if (INTVAL (operands[1]) > 0
2668 && INTVAL (operands[1]) <= 8)
2669 return "addq%.b %1,%0";
2670 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2672 operands[1] = GEN_INT (- INTVAL (operands[1]));
2673 return "subq%.b %1,%0";
2676 return "add%.b %1,%0";
2680 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2681 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2685 if (GET_CODE (operands[1]) == CONST_INT)
2687 if (INTVAL (operands[1]) >= 128)
2688 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2690 if (INTVAL (operands[1]) > 0
2691 && INTVAL (operands[1]) <= 8)
2692 return "addq%.b %1,%0";
2693 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2695 operands[1] = GEN_INT (- INTVAL (operands[1]));
2696 return "subq%.b %1,%0";
2699 return "add%.b %1,%0";
2702 (define_expand "add<mode>3"
2703 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2704 (plus:FP (match_operand:FP 1 "general_operand" "")
2705 (match_operand:FP 2 "general_operand" "")))]
2709 (define_insn "add<mode>3_floatsi_68881"
2710 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2711 (plus:FP (float:FP (match_operand:SI 2 "general_operand" "dmi"))
2712 (match_operand:FP 1 "general_operand" "0")))]
2714 "f<FP:round>add%.l %2,%0")
2716 (define_insn "add<mode>3_floathi_68881"
2717 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2718 (plus:FP (float:FP (match_operand:HI 2 "general_operand" "dmn"))
2719 (match_operand:FP 1 "general_operand" "0")))]
2721 "f<FP:round>add%.w %2,%0")
2723 (define_insn "add<mode>3_floatqi_68881"
2724 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2725 (plus:FP (float:FP (match_operand:QI 2 "general_operand" "dmn"))
2726 (match_operand:FP 1 "general_operand" "0")))]
2728 "f<FP:round>add%.b %2,%0")
2730 (define_insn "add<mode>3_68881"
2731 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2732 (plus:FP (match_operand:FP 1 "general_operand" "%0")
2733 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
2736 if (FP_REG_P (operands[2]))
2737 return "f<FP:round>add%.x %2,%0";
2738 return "f<FP:round>add%.<FP:prec> %f2,%0";
2741 (define_insn "add<mode>3_cf"
2742 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2743 (plus:FP (match_operand:FP 1 "general_operand" "%0")
2744 (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))]
2745 "TARGET_COLDFIRE_FPU"
2747 if (FP_REG_P (operands[2]))
2748 return "f<FP:prec>add%.d %2,%0";
2749 return "f<FP:prec>add%.<FP:prec> %2,%0";
2751 [(set_attr "type" "fadd")])
2753 ;; subtract instructions
2755 (define_insn "subdi_sexthishl32"
2756 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2757 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2758 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2760 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2764 if (ADDRESS_REG_P (operands[0]))
2765 return "sub%.w %2,%0";
2766 else if (ADDRESS_REG_P (operands[3]))
2767 return "move%.w %2,%3\;sub%.l %3,%0";
2769 return "move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0";
2772 (define_insn "subdi_dishl32"
2773 [(set (match_operand:DI 0 "nonimmediate_operand" "+ro")
2774 (minus:DI (match_dup 0)
2775 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2780 if (GET_CODE (operands[1]) == REG)
2781 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2783 operands[1] = adjust_address (operands[1], SImode, 4);
2784 return "sub%.l %1,%0";
2786 [(set_attr "type" "sub_l")])
2788 (define_insn "subdi3"
2789 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
2790 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2791 (match_operand:DI 2 "general_operand" "d,no>,d,a")))
2792 (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))]
2795 if (DATA_REG_P (operands[0]))
2797 if (DATA_REG_P (operands[2]))
2798 return "sub%.l %R2,%R0\;subx%.l %2,%0";
2799 else if (GET_CODE (operands[2]) == MEM
2800 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2802 return "move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0";
2809 if (GET_CODE (operands[2]) == REG)
2811 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2814 else if (CONSTANT_P (operands[2]))
2815 split_double (operands[2], &high, &low);
2818 low = adjust_address (operands[2], SImode, 4);
2822 operands[1] = low, operands[2] = high;
2823 xoperands[0] = operands[3];
2824 if (GET_CODE (operands[1]) == CONST_INT
2825 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2826 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2828 xoperands[1] = operands[2];
2830 output_asm_insn (output_move_simode (xoperands), xoperands);
2831 if (GET_CODE (operands[1]) == CONST_INT)
2833 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2834 return "subq%.l %1,%R0\;subx%.l %3,%0";
2835 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2837 operands[1] = GEN_INT (-INTVAL (operands[1]));
2838 return "addq%.l %1,%R0\;addx%.l %3,%0";
2841 return "sub%.l %1,%R0\;subx%.l %3,%0";
2846 gcc_assert (GET_CODE (operands[0]) == MEM);
2848 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2851 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2852 return "move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1";
2854 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2856 operands[1] = XEXP(operands[0], 0);
2857 return "sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1";
2861 operands[1] = adjust_address (operands[0], SImode, 4);
2862 return "sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0";
2867 (define_insn "subsi3"
2868 [(set (match_operand:SI 0 "nonimmediate_operand" "=mda,m,d,a")
2869 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0")
2870 (match_operand:SI 2 "general_src_operand" "I,dT,mSrT,mSrs")))]
2877 [(set_attr "type" "subq_l,sub_l,sub_l,sub_l")
2878 (set_attr "opy" "2")])
2881 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2882 (minus:SI (match_operand:SI 1 "general_operand" "0")
2884 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2888 (define_insn "subhi3"
2889 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2890 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2891 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2896 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2897 (minus:HI (match_dup 0)
2898 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2902 (define_insn "subqi3"
2903 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2904 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2905 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2910 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2911 (minus:QI (match_dup 0)
2912 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2916 (define_expand "sub<mode>3"
2917 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2918 (minus:FP (match_operand:FP 1 "general_operand" "")
2919 (match_operand:FP 2 "general_operand" "")))]
2923 (define_insn "sub<mode>3_floatsi_68881"
2924 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2925 (minus:FP (match_operand:FP 1 "general_operand" "0")
2926 (float:FP (match_operand:SI 2 "general_operand" "dmi"))))]
2928 "f<FP:round>sub%.l %2,%0")
2930 (define_insn "sub<mode>3_floathi_68881"
2931 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2932 (minus:FP (match_operand:FP 1 "general_operand" "0")
2933 (float:FP (match_operand:HI 2 "general_operand" "dmn"))))]
2935 "f<FP:round>sub%.w %2,%0")
2937 (define_insn "sub<mode>3_floatqi_68881"
2938 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2939 (minus:FP (match_operand:FP 1 "general_operand" "0")
2940 (float:FP (match_operand:QI 2 "general_operand" "dmn"))))]
2942 "f<FP:round>sub%.b %2,%0")
2944 (define_insn "sub<mode>3_68881"
2945 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2946 (minus:FP (match_operand:FP 1 "general_operand" "0")
2947 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
2950 if (FP_REG_P (operands[2]))
2951 return "f<FP:round>sub%.x %2,%0";
2952 return "f<FP:round>sub%.<FP:prec> %f2,%0";
2955 (define_insn "sub<mode>3_cf"
2956 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2957 (minus:FP (match_operand:FP 1 "general_operand" "0")
2958 (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))]
2959 "TARGET_COLDFIRE_FPU"
2961 if (FP_REG_P (operands[2]))
2962 return "f<FP:prec>sub%.d %2,%0";
2963 return "f<FP:prec>sub%.<FP:prec> %2,%0";
2965 [(set_attr "type" "fsub")])
2967 ;; multiply instructions
2969 (define_insn "mulhi3"
2970 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
2971 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2972 (match_operand:HI 2 "general_src_operand" "dmSn")))]
2975 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2977 [(set_attr "type" "muls_w")
2978 (set_attr "opy" "2")])
2980 (define_insn "mulhisi3"
2981 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2982 (mult:SI (sign_extend:SI
2983 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2985 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2988 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2990 [(set_attr "type" "muls_w")
2991 (set_attr "opy" "2")])
2993 (define_insn "*mulhisisi3_s"
2994 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2995 (mult:SI (sign_extend:SI
2996 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2997 (match_operand:SI 2 "const_int_operand" "n")))]
2998 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
3000 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
3002 [(set_attr "type" "muls_w")
3003 (set_attr "opy" "2")])
3005 (define_expand "mulsi3"
3006 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3007 (mult:SI (match_operand:SI 1 "general_operand" "")
3008 (match_operand:SI 2 "general_operand" "")))]
3009 "TARGET_68020 || TARGET_COLDFIRE"
3012 (define_insn "*mulsi3_68020"
3013 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3014 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3015 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
3019 [(set_attr "type" "muls_l")
3020 (set_attr "opy" "2")])
3022 (define_insn "*mulsi3_cf"
3023 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3024 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3025 (match_operand:SI 2 "general_operand" "d<Q>")))]
3028 [(set_attr "type" "muls_l")
3029 (set_attr "opy" "2")])
3031 (define_insn "umulhisi3"
3032 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3033 (mult:SI (zero_extend:SI
3034 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3036 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3039 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
3041 [(set_attr "type" "mulu_w")
3042 (set_attr "opy" "2")])
3044 (define_insn "*mulhisisi3_z"
3045 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3046 (mult:SI (zero_extend:SI
3047 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3048 (match_operand:SI 2 "const_int_operand" "n")))]
3049 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
3051 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
3053 [(set_attr "type" "mulu_w")
3054 (set_attr "opy" "2")])
3056 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
3057 ;; proper matching constraint. This is because the matching is between
3058 ;; the high-numbered word of the DImode operand[0] and operand[1].
3059 (define_expand "umulsidi3"
3061 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
3062 (mult:SI (match_operand:SI 1 "register_operand" "")
3063 (match_operand:SI 2 "register_operand" "")))
3064 (set (subreg:SI (match_dup 0) 0)
3065 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3066 (zero_extend:DI (match_dup 2)))
3067 (const_int 32))))])]
3068 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3072 [(set (match_operand:SI 0 "register_operand" "=d")
3073 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3074 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3075 (set (match_operand:SI 3 "register_operand" "=d")
3076 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3077 (zero_extend:DI (match_dup 2)))
3079 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3082 ; Match immediate case. For 2.4 only match things < 2^31.
3083 ; It's tricky with larger values in these patterns since we need to match
3084 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3087 [(set (match_operand:SI 0 "register_operand" "=d")
3088 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3089 (match_operand:SI 2 "const_int_operand" "n")))
3090 (set (match_operand:SI 3 "register_operand" "=d")
3091 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3094 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE
3095 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3098 (define_expand "mulsidi3"
3100 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
3101 (mult:SI (match_operand:SI 1 "register_operand" "")
3102 (match_operand:SI 2 "register_operand" "")))
3103 (set (subreg:SI (match_dup 0) 0)
3104 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3105 (sign_extend:DI (match_dup 2)))
3106 (const_int 32))))])]
3107 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3111 [(set (match_operand:SI 0 "register_operand" "=d")
3112 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3113 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3114 (set (match_operand:SI 3 "register_operand" "=d")
3115 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3116 (sign_extend:DI (match_dup 2)))
3118 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3122 [(set (match_operand:SI 0 "register_operand" "=d")
3123 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3124 (match_operand:SI 2 "const_int_operand" "n")))
3125 (set (match_operand:SI 3 "register_operand" "=d")
3126 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3129 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3132 (define_expand "umulsi3_highpart"
3134 [(set (match_operand:SI 0 "register_operand" "")
3137 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3138 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3140 (clobber (match_dup 3))])]
3141 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3143 operands[3] = gen_reg_rtx (SImode);
3145 if (GET_CODE (operands[2]) == CONST_INT)
3147 operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
3150 /* We have to adjust the operand order for the matching constraints. */
3151 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3152 operands[1], operands[2]));
3158 [(set (match_operand:SI 0 "register_operand" "=d")
3161 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3162 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3164 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3165 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3168 (define_insn "const_umulsi3_highpart"
3169 [(set (match_operand:SI 0 "register_operand" "=d")
3172 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3173 (match_operand:DI 3 "const_uint32_operand" "n"))
3175 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3176 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3179 (define_expand "smulsi3_highpart"
3181 [(set (match_operand:SI 0 "register_operand" "")
3184 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3185 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3187 (clobber (match_dup 3))])]
3188 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3190 operands[3] = gen_reg_rtx (SImode);
3191 if (GET_CODE (operands[2]) == CONST_INT)
3193 /* We have to adjust the operand order for the matching constraints. */
3194 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3195 operands[1], operands[2]));
3201 [(set (match_operand:SI 0 "register_operand" "=d")
3204 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3205 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3207 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3208 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3211 (define_insn "const_smulsi3_highpart"
3212 [(set (match_operand:SI 0 "register_operand" "=d")
3215 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3216 (match_operand:DI 3 "const_sint32_operand" "n"))
3218 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3219 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3222 (define_expand "mul<mode>3"
3223 [(set (match_operand:FP 0 "nonimmediate_operand" "")
3224 (mult:FP (match_operand:FP 1 "general_operand" "")
3225 (match_operand:FP 2 "general_operand" "")))]
3229 (define_insn "mul<mode>3_floatsi_68881"
3230 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3231 (mult:FP (float:FP (match_operand:SI 2 "general_operand" "dmi"))
3232 (match_operand:FP 1 "general_operand" "0")))]
3236 ? "f<FP:round>mul%.l %2,%0"
3237 : "f<FP:round_mul>mul%.l %2,%0";
3240 (define_insn "mul<mode>3_floathi_68881"
3241 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3242 (mult:FP (float:FP (match_operand:HI 2 "general_operand" "dmn"))
3243 (match_operand:FP 1 "general_operand" "0")))]
3247 ? "f<FP:round>mul%.w %2,%0"
3248 : "f<FP:round_mul>mul%.w %2,%0";
3251 (define_insn "mul<mode>3_floatqi_68881"
3252 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3253 (mult:FP (float:FP (match_operand:QI 2 "general_operand" "dmn"))
3254 (match_operand:FP 1 "general_operand" "0")))]
3258 ? "f<FP:round>mul%.b %2,%0"
3259 : "f<FP:round_mul>mul%.b %2,%0";
3262 (define_insn "muldf_68881"
3263 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3264 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3265 (match_operand:DF 2 "general_operand" "fmG")))]
3268 if (GET_CODE (operands[2]) == CONST_DOUBLE
3269 && floating_exact_log2 (operands[2]) && !TUNE_68040_60)
3271 int i = floating_exact_log2 (operands[2]);
3272 operands[2] = GEN_INT (i);
3273 return "fscale%.l %2,%0";
3275 if (REG_P (operands[2]))
3276 return "f%&mul%.x %2,%0";
3277 return "f%&mul%.d %f2,%0";
3280 (define_insn "mulsf_68881"
3281 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3282 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3283 (match_operand:SF 2 "general_operand" "fdmF")))]
3286 if (FP_REG_P (operands[2]))
3287 return (TARGET_68040
3289 : "fsglmul%.x %2,%0");
3290 return (TARGET_68040
3292 : "fsglmul%.s %f2,%0");
3295 (define_insn "mulxf3_68881"
3296 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
3297 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
3298 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
3301 return "fmul%.x %f2,%0";
3304 (define_insn "fmul<mode>3_cf"
3305 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3306 (mult:FP (match_operand:FP 1 "general_operand" "%0")
3307 (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))]
3308 "TARGET_COLDFIRE_FPU"
3310 if (FP_REG_P (operands[2]))
3311 return "f<FP:prec>mul%.d %2,%0";
3312 return "f<FP:prec>mul%.<FP:prec> %2,%0";
3314 [(set_attr "type" "fmul")])
3316 ;; divide instructions
3318 (define_expand "div<mode>3"
3319 [(set (match_operand:FP 0 "nonimmediate_operand" "")
3320 (div:FP (match_operand:FP 1 "general_operand" "")
3321 (match_operand:FP 2 "general_operand" "")))]
3325 (define_insn "div<mode>3_floatsi_68881"
3326 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3327 (div:FP (match_operand:FP 1 "general_operand" "0")
3328 (float:FP (match_operand:SI 2 "general_operand" "dmi"))))]
3332 ? "f<FP:round>div%.l %2,%0"
3333 : "f<FP:round_mul>div%.l %2,%0";
3336 (define_insn "div<mode>3_floathi_68881"
3337 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3338 (div:FP (match_operand:FP 1 "general_operand" "0")
3339 (float:FP (match_operand:HI 2 "general_operand" "dmn"))))]
3343 ? "f<FP:round>div%.w %2,%0"
3344 : "f<FP:round_mul>div%.w %2,%0";
3347 (define_insn "div<mode>3_floatqi_68881"
3348 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3349 (div:FP (match_operand:FP 1 "general_operand" "0")
3350 (float:FP (match_operand:QI 2 "general_operand" "dmn"))))]
3354 ? "f<FP:round>div%.b %2,%0"
3355 : "f<FP:round_mul>div%.b %2,%0";
3358 (define_insn "div<mode>3_68881"
3359 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3360 (div:FP (match_operand:FP 1 "general_operand" "0")
3361 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
3364 if (FP_REG_P (operands[2]))
3365 return (TARGET_68040
3366 ? "f<FP:round>div%.x %2,%0"
3367 : "f<FP:round_mul>div%.x %2,%0");
3368 return (TARGET_68040
3369 ? "f<FP:round>div%.<FP:prec> %f2,%0"
3370 : "f<FP:round_mul>div%.<FP:prec> %f2,%0");
3373 (define_insn "div<mode>3_cf"
3374 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3375 (div:FP (match_operand:FP 1 "general_operand" "0")
3376 (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))]
3377 "TARGET_COLDFIRE_FPU"
3379 if (FP_REG_P (operands[2]))
3380 return "f<FP:prec>div%.d %2,%0";
3381 return "f<FP:prec>div%.<FP:prec> %2,%0";
3383 [(set_attr "type" "fdiv")])
3385 ;; Remainder instructions.
3387 (define_expand "divmodsi4"
3389 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3390 (div:SI (match_operand:SI 1 "general_operand" "")
3391 (match_operand:SI 2 "general_src_operand" "")))
3392 (set (match_operand:SI 3 "nonimmediate_operand" "")
3393 (mod:SI (match_dup 1) (match_dup 2)))])]
3394 "TARGET_68020 || TARGET_CF_HWDIV"
3398 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3399 (div:SI (match_operand:SI 1 "general_operand" "0")
3400 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3401 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3402 (mod:SI (match_dup 1) (match_dup 2)))]
3405 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3406 return "divs%.l %2,%0";
3407 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3408 return "rems%.l %2,%3:%0";
3410 return "rems%.l %2,%3:%0\;divs%.l %2,%0";
3414 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3415 (div:SI (match_operand:SI 1 "general_operand" "0")
3416 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3417 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3418 (mod:SI (match_dup 1) (match_dup 2)))]
3421 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3422 return "divs%.l %2,%0";
3424 return "divsl%.l %2,%3:%0";
3427 (define_expand "udivmodsi4"
3429 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3430 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3431 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3432 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3433 (umod:SI (match_dup 1) (match_dup 2)))])]
3434 "TARGET_68020 || TARGET_CF_HWDIV"
3438 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3439 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3440 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3441 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3442 (umod:SI (match_dup 1) (match_dup 2)))]
3445 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3446 return "divu%.l %2,%0";
3447 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3448 return "remu%.l %2,%3:%0";
3450 return "remu%.l %2,%3:%0\;divu%.l %2,%0";
3454 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3455 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3456 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3457 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3458 (umod:SI (match_dup 1) (match_dup 2)))]
3459 "TARGET_68020 && !TARGET_COLDFIRE"
3461 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3462 return "divu%.l %2,%0";
3464 return "divul%.l %2,%3:%0";
3467 (define_insn "divmodhi4"
3468 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3469 (div:HI (match_operand:HI 1 "general_operand" "0")
3470 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3471 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3472 (mod:HI (match_dup 1) (match_dup 2)))]
3473 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3475 output_asm_insn (MOTOROLA ?
3476 "ext%.l %0\;divs%.w %2,%0" :
3477 "extl %0\;divs %2,%0",
3479 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3482 return "move%.l %0,%3\;swap %3";
3488 (define_insn "udivmodhi4"
3489 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3490 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3491 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3492 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3493 (umod:HI (match_dup 1) (match_dup 2)))]
3494 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3496 if (ISA_HAS_MVS_MVZ)
3497 output_asm_insn (MOTOROLA ?
3498 "mvz%.w %0,%0\;divu%.w %2,%0" :
3499 "mvz%.w %0,%0\;divu %2,%0",
3502 output_asm_insn (MOTOROLA ?
3503 "and%.l #0xFFFF,%0\;divu%.w %2,%0" :
3504 "and%.l #0xFFFF,%0\;divu %2,%0",
3507 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3510 return "move%.l %0,%3\;swap %3";
3516 ;; logical-and instructions
3518 ;; "anddi3" is mainly here to help combine().
3519 (define_insn "anddi3"
3520 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3521 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3522 (match_operand:DI 2 "general_operand" "dn,don")))]
3526 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3527 if (CONSTANT_P (operands[2]))
3531 split_double (operands[2], &hi, &lo);
3533 switch (INTVAL (hi))
3536 output_asm_insn ("clr%.l %0", operands);
3544 xoperands[0] = operands[0];
3546 output_asm_insn (output_andsi3 (xoperands), xoperands);
3549 if (GET_CODE (operands[0]) == REG)
3550 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3552 operands[0] = adjust_address (operands[0], SImode, 4);
3553 switch (INTVAL (lo))
3556 output_asm_insn ("clr%.l %0", operands);
3564 xoperands[0] = operands[0];
3566 output_asm_insn (output_andsi3 (xoperands), xoperands);
3571 if (GET_CODE (operands[0]) != REG)
3573 operands[1] = adjust_address (operands[0], SImode, 4);
3574 return "and%.l %2,%0\;and%.l %R2,%1";
3576 if (GET_CODE (operands[2]) != REG)
3578 operands[1] = adjust_address (operands[2], SImode, 4);
3579 return "and%.l %2,%0\;and%.l %1,%R0";
3581 return "and%.l %2,%0\;and%.l %R2,%R0";
3584 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3585 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3586 ;; can't allocate pseudos into it.
3588 (define_expand "andsi3"
3589 [(set (match_operand:SI 0 "not_sp_operand" "")
3590 (and:SI (match_operand:SI 1 "general_operand" "")
3591 (match_operand:SI 2 "general_src_operand" "")))]
3595 ;; produced by split operations after reload finished
3596 (define_insn "*andsi3_split"
3597 [(set (match_operand:SI 0 "register_operand" "=d")
3598 (and:SI (match_operand:SI 1 "register_operand" "0")
3599 (match_operand:SI 2 "const_int_operand" "i")))]
3600 "reload_completed && !TARGET_COLDFIRE"
3602 return output_andsi3 (operands);
3605 (define_insn "andsi3_internal"
3606 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3607 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3608 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3611 return output_andsi3 (operands);
3614 (define_insn "andsi3_5200"
3615 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3616 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3617 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3621 && DATA_REG_P (operands[0])
3622 && GET_CODE (operands[2]) == CONST_INT)
3624 if (INTVAL (operands[2]) == 0x000000ff)
3625 return "mvz%.b %0,%0";
3626 else if (INTVAL (operands[2]) == 0x0000ffff)
3627 return "mvz%.w %0,%0";
3629 return output_andsi3 (operands);
3632 (define_insn "andhi3"
3633 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3634 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3635 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3640 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3641 (and:HI (match_dup 0)
3642 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3647 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3648 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3653 (define_insn "andqi3"
3654 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3655 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3656 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3661 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3662 (and:QI (match_dup 0)
3663 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3668 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3669 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3674 ;; inclusive-or instructions
3676 (define_insn "iordi_zext"
3677 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3678 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3679 (match_operand:DI 2 "general_operand" "0,0")))]
3685 if (GET_CODE (operands[0]) == REG)
3686 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3688 operands[0] = adjust_address (operands[0], SImode, 4);
3689 if (GET_MODE (operands[1]) == SImode)
3690 return "or%.l %1,%0";
3691 byte_mode = (GET_MODE (operands[1]) == QImode);
3692 if (GET_CODE (operands[0]) == MEM)
3693 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3696 return "or%.b %1,%0";
3698 return "or%.w %1,%0";
3701 ;; "iordi3" is mainly here to help combine().
3702 (define_insn "iordi3"
3703 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3704 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3705 (match_operand:DI 2 "general_operand" "dn,don")))]
3709 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3710 if (CONSTANT_P (operands[2]))
3714 split_double (operands[2], &hi, &lo);
3716 switch (INTVAL (hi))
3721 /* FIXME : a scratch register would be welcome here if operand[0]
3722 is not a register */
3723 output_asm_insn ("move%.l #-1,%0", operands);
3729 xoperands[0] = operands[0];
3731 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3734 if (GET_CODE (operands[0]) == REG)
3735 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3737 operands[0] = adjust_address (operands[0], SImode, 4);
3738 switch (INTVAL (lo))
3743 /* FIXME : a scratch register would be welcome here if operand[0]
3744 is not a register */
3745 output_asm_insn ("move%.l #-1,%0", operands);
3751 xoperands[0] = operands[0];
3753 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3758 if (GET_CODE (operands[0]) != REG)
3760 operands[1] = adjust_address (operands[0], SImode, 4);
3761 return "or%.l %2,%0\;or%.l %R2,%1";
3763 if (GET_CODE (operands[2]) != REG)
3765 operands[1] = adjust_address (operands[2], SImode, 4);
3766 return "or%.l %2,%0\;or%.l %1,%R0";
3768 return "or%.l %2,%0\;or%.l %R2,%R0";
3771 (define_expand "iorsi3"
3772 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3773 (ior:SI (match_operand:SI 1 "general_operand" "")
3774 (match_operand:SI 2 "general_src_operand" "")))]
3778 (define_insn "iorsi3_internal"
3779 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3780 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3781 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3784 return output_iorsi3 (operands);
3787 (define_insn "iorsi3_5200"
3788 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3789 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3790 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3793 return output_iorsi3 (operands);
3796 (define_insn "iorhi3"
3797 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3798 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3799 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3804 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3805 (ior:HI (match_dup 0)
3806 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3811 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3812 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3817 (define_insn "iorqi3"
3818 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3819 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3820 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3825 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3826 (ior:QI (match_dup 0)
3827 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3832 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3833 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3838 ;; On all 68k models, this makes faster code in a special case.
3839 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3841 (define_insn "iorsi_zexthi_ashl16"
3842 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
3843 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3844 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3849 if (GET_CODE (operands[2]) != REG)
3850 operands[2] = adjust_address (operands[2], HImode, 2);
3851 if (GET_CODE (operands[2]) != REG
3852 || REGNO (operands[2]) != REGNO (operands[0]))
3853 output_asm_insn ("move%.w %2,%0", operands);
3854 return "swap %0\;mov%.w %1,%0";
3857 (define_insn "iorsi_zext"
3858 [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
3859 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3860 (match_operand:SI 2 "general_operand" "0,0")))]
3866 byte_mode = (GET_MODE (operands[1]) == QImode);
3867 if (GET_CODE (operands[0]) == MEM)
3868 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3871 return "or%.b %1,%0";
3873 return "or%.w %1,%0";
3878 ;; "xordi3" is mainly here to help combine().
3879 (define_insn "xordi3"
3880 [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
3881 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3882 (match_operand:DI 2 "general_operand" "dn")))]
3886 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3888 if (CONSTANT_P (operands[2]))
3892 split_double (operands[2], &hi, &lo);
3894 switch (INTVAL (hi))
3899 output_asm_insn ("not%.l %0", operands);
3902 /* FIXME : a scratch register would be welcome here if
3903 -128 <= INTVAL (hi) < -1 */
3907 xoperands[0] = operands[0];
3909 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3912 if (GET_CODE (operands[0]) == REG)
3913 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3915 operands[0] = adjust_address (operands[0], SImode, 4);
3916 switch (INTVAL (lo))
3921 output_asm_insn ("not%.l %0", operands);
3924 /* FIXME : a scratch register would be welcome here if
3925 -128 <= INTVAL (lo) < -1 */
3927 /* FIXME : this should be merged with xorsi3 */
3931 xoperands[0] = operands[0];
3933 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3938 if (GET_CODE (operands[0]) != REG)
3940 operands[1] = adjust_address (operands[0], SImode, 4);
3941 return "eor%.l %2,%0\;eor%.l %R2,%1";
3943 if (GET_CODE (operands[2]) != REG)
3945 operands[1] = adjust_address (operands[2], SImode, 4);
3946 return "eor%.l %2,%0\;eor%.l %1,%R0";
3948 return "eor%.l %2,%0\;eor%.l %R2,%R0";
3951 (define_expand "xorsi3"
3952 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3953 (xor:SI (match_operand:SI 1 "general_operand" "")
3954 (match_operand:SI 2 "general_operand" "")))]
3958 (define_insn "xorsi3_internal"
3959 [(set (match_operand:SI 0 "nonimmediate_operand" "=do,m")
3960 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3961 (match_operand:SI 2 "general_operand" "di,dKT")))]
3965 return output_xorsi3 (operands);
3968 (define_insn "xorsi3_5200"
3969 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
3970 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3971 (match_operand:SI 2 "general_operand" "d,Ks")))]
3974 return output_xorsi3 (operands);
3977 (define_insn "xorhi3"
3978 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3979 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3980 (match_operand:HI 2 "general_operand" "dn")))]
3985 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3986 (xor:HI (match_dup 0)
3987 (match_operand:HI 1 "general_operand" "dn")))]
3992 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3993 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3998 (define_insn "xorqi3"
3999 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4000 (xor:QI (match_operand:QI 1 "general_operand" "%0")
4001 (match_operand:QI 2 "general_operand" "dn")))]
4006 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4007 (xor:QI (match_dup 0)
4008 (match_operand:QI 1 "general_operand" "dn")))]
4013 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4014 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4019 ;; negation instructions
4021 (define_expand "negdi2"
4022 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4023 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4026 if (TARGET_COLDFIRE)
4027 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4029 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4033 (define_insn "negdi2_internal"
4034 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
4035 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4038 if (which_alternative == 0)
4039 return "neg%.l %0\;negx%.l %0";
4040 if (GET_CODE (operands[0]) == REG)
4041 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4043 operands[1] = adjust_address (operands[0], SImode, 4);
4044 if (ADDRESS_REG_P (operands[0]))
4045 return "exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0";
4047 return "neg%.l %1\;negx%.l %0";
4050 (define_insn "negdi2_5200"
4051 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4052 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4055 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4056 return "neg%.l %1\;negx%.l %0";
4059 (define_expand "negsi2"
4060 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4061 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4064 if (TARGET_COLDFIRE)
4065 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4067 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4071 (define_insn "negsi2_internal"
4072 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
4073 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4076 [(set_attr "type" "neg_l")])
4078 (define_insn "negsi2_5200"
4079 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4080 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4083 [(set_attr "type" "neg_l")])
4085 (define_insn "neghi2"
4086 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4087 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4092 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4093 (neg:HI (match_dup 0)))]
4097 (define_insn "negqi2"
4098 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4099 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4104 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4105 (neg:QI (match_dup 0)))]
4109 ;; If using software floating point, just flip the sign bit.
4111 (define_expand "negsf2"
4112 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4113 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4116 if (!TARGET_HARD_FLOAT)
4121 target = operand_subword_force (operands[0], 0, SFmode);
4122 result = expand_binop (SImode, xor_optab,
4123 operand_subword_force (operands[1], 0, SFmode),
4124 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
4125 gcc_assert (result);
4127 if (result != target)
4128 emit_move_insn (result, target);
4130 /* Make a place for REG_EQUAL. */
4131 emit_move_insn (operands[0], operands[0]);
4136 (define_expand "negdf2"
4137 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4138 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4141 if (!TARGET_HARD_FLOAT)
4148 target = operand_subword (operands[0], 0, 1, DFmode);
4149 result = expand_binop (SImode, xor_optab,
4150 operand_subword_force (operands[1], 0, DFmode),
4151 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
4152 gcc_assert (result);
4154 if (result != target)
4155 emit_move_insn (result, target);
4157 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4158 operand_subword_force (operands[1], 1, DFmode));
4160 insns = get_insns ();
4163 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4168 (define_expand "negxf2"
4169 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4170 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
4180 target = operand_subword (operands[0], 0, 1, XFmode);
4181 result = expand_binop (SImode, xor_optab,
4182 operand_subword_force (operands[1], 0, XFmode),
4183 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
4184 gcc_assert (result);
4186 if (result != target)
4187 emit_move_insn (result, target);
4189 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
4190 operand_subword_force (operands[1], 1, XFmode));
4191 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
4192 operand_subword_force (operands[1], 2, XFmode));
4194 insns = get_insns ();
4197 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4202 (define_insn "neg<mode>2_68881"
4203 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
4204 (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))]
4207 if (DATA_REG_P (operands[0]))
4209 operands[1] = GEN_INT (31);
4210 return "bchg %1,%0";
4212 if (FP_REG_P (operands[1]))
4213 return "f<FP:round>neg%.x %1,%0";
4214 return "f<FP:round>neg%.<FP:prec> %f1,%0";
4217 (define_insn "neg<mode>2_cf"
4218 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
4219 (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))]
4220 "TARGET_COLDFIRE_FPU"
4222 if (DATA_REG_P (operands[0]))
4224 operands[1] = GEN_INT (31);
4225 return "bchg %1,%0";
4227 if (FP_REG_P (operands[1]))
4228 return "f<FP:prec>neg%.d %1,%0";
4229 return "f<FP:prec>neg%.<FP:prec> %1,%0";
4232 ;; Sqrt instruction for the 68881
4234 (define_expand "sqrt<mode>2"
4235 [(set (match_operand:FP 0 "nonimmediate_operand" "")
4236 (sqrt:FP (match_operand:FP 1 "general_operand" "")))]
4240 (define_insn "sqrt<mode>2_68881"
4241 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
4242 (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
4245 if (FP_REG_P (operands[1]))
4246 return "f<FP:round>sqrt%.x %1,%0";
4247 return "f<FP:round>sqrt%.<FP:prec> %1,%0";
4249 [(set_attr "type" "fsqrt")])
4251 (define_insn "sqrt<mode>2_cf"
4252 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
4253 (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))]
4254 "TARGET_COLDFIRE_FPU"
4256 if (FP_REG_P (operands[1]))
4257 return "f<FP:prec>sqrt%.d %1,%0";
4258 return "f<FP:prec>sqrt%.<FP:prec> %1,%0";
4260 ;; Absolute value instructions
4261 ;; If using software floating point, just zero the sign bit.
4263 (define_expand "abssf2"
4264 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4265 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4268 if (!TARGET_HARD_FLOAT)
4273 target = operand_subword_force (operands[0], 0, SFmode);
4274 result = expand_binop (SImode, and_optab,
4275 operand_subword_force (operands[1], 0, SFmode),
4276 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4277 gcc_assert (result);
4279 if (result != target)
4280 emit_move_insn (result, target);
4282 /* Make a place for REG_EQUAL. */
4283 emit_move_insn (operands[0], operands[0]);
4288 (define_expand "absdf2"
4289 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4290 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4293 if (!TARGET_HARD_FLOAT)
4300 target = operand_subword (operands[0], 0, 1, DFmode);
4301 result = expand_binop (SImode, and_optab,
4302 operand_subword_force (operands[1], 0, DFmode),
4303 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4304 gcc_assert (result);
4306 if (result != target)
4307 emit_move_insn (result, target);
4309 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4310 operand_subword_force (operands[1], 1, DFmode));
4312 insns = get_insns ();
4315 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4320 (define_expand "absxf2"
4321 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4322 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
4332 target = operand_subword (operands[0], 0, 1, XFmode);
4333 result = expand_binop (SImode, and_optab,
4334 operand_subword_force (operands[1], 0, XFmode),
4335 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4336 gcc_assert (result);
4338 if (result != target)
4339 emit_move_insn (result, target);
4341 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
4342 operand_subword_force (operands[1], 1, XFmode));
4343 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
4344 operand_subword_force (operands[1], 2, XFmode));
4346 insns = get_insns ();
4349 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4354 (define_insn "abs<mode>2_68881"
4355 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
4356 (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))]
4359 if (DATA_REG_P (operands[0]))
4361 operands[1] = GEN_INT (31);
4362 return "bclr %1,%0";
4364 if (FP_REG_P (operands[1]))
4365 return "f<FP:round>abs%.x %1,%0";
4366 return "f<FP:round>abs%.<FP:prec> %f1,%0";
4369 (define_insn "abs<mode>2_cf"
4370 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
4371 (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))]
4372 "TARGET_COLDFIRE_FPU"
4374 if (DATA_REG_P (operands[0]))
4376 operands[1] = GEN_INT (31);
4377 return "bclr %1,%0";
4379 if (FP_REG_P (operands[1]))
4380 return "f<FP:prec>abs%.d %1,%0";
4381 return "f<FP:prec>abs%.<FP:prec> %1,%0";
4384 ;; bit indexing instructions
4386 ;; ColdFire ff1 instruction implements clz.
4387 (define_insn "clzsi2"
4388 [(set (match_operand:SI 0 "register_operand" "=d")
4389 (clz:SI (match_operand:SI 1 "register_operand" "0")))]
4392 [(set_attr "type" "ff1")])
4394 ;; one complement instructions
4396 ;; "one_cmpldi2" is mainly here to help combine().
4397 (define_insn "one_cmpldi2"
4398 [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
4399 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4403 if (GET_CODE (operands[0]) == REG)
4404 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4405 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4406 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4407 operands[1] = operands[0];
4409 operands[1] = adjust_address (operands[0], SImode, 4);
4410 return "not%.l %1\;not%.l %0";
4413 (define_expand "one_cmplsi2"
4414 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4415 (not:SI (match_operand:SI 1 "general_operand" "")))]
4418 if (TARGET_COLDFIRE)
4419 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4421 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4425 (define_insn "one_cmplsi2_internal"
4426 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
4427 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4431 (define_insn "one_cmplsi2_5200"
4432 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4433 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4436 [(set_attr "type" "not_l")])
4438 (define_insn "one_cmplhi2"
4439 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4440 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4445 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4446 (not:HI (match_dup 0)))]
4450 (define_insn "one_cmplqi2"
4451 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4452 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4457 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4458 (not:QI (match_dup 0)))]
4462 ;; arithmetic shift instructions
4463 ;; We don't need the shift memory by 1 bit instruction
4465 (define_insn "ashldi_extsi"
4466 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
4468 (match_operator:DI 2 "extend_operator"
4469 [(match_operand:SI 1 "general_operand" "rm")])
4474 if (GET_CODE (operands[0]) == REG)
4475 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4477 operands[2] = adjust_address (operands[0], SImode, 4);
4478 if (ADDRESS_REG_P (operands[0]))
4479 return "move%.l %1,%0\;sub%.l %2,%2";
4481 return "move%.l %1,%0\;clr%.l %2";
4484 (define_insn "ashldi_sexthi"
4485 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
4486 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4488 (clobber (match_scratch:SI 2 "=a,X"))]
4492 if (GET_CODE (operands[0]) == MEM)
4494 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4495 return "clr%.l %0\;move%.w %1,%2\;move%.l %2,%0";
4496 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4497 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %0";
4500 operands[3] = adjust_address (operands[0], SImode, 4);
4501 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %3";
4504 else if (DATA_REG_P (operands[0]))
4505 return "move%.w %1,%0\;ext%.l %0\;clr%.l %R0";
4507 return "move%.w %1,%0\;sub%.l %R0,%R0";
4510 (define_insn "*ashldi3_const1"
4511 [(set (match_operand:DI 0 "register_operand" "=d")
4512 (ashift:DI (match_operand:DI 1 "register_operand" "0")
4515 "add%.l %R0,%R0\;addx%.l %0,%0")
4518 [(set (match_operand:DI 0 "register_operand" "")
4519 (ashift:DI (match_operand:DI 1 "register_operand" "")
4521 "reload_completed && !TARGET_COLDFIRE"
4523 (ashift:DI (match_dup 1) (const_int 1)))
4525 (ashift:DI (match_dup 0) (const_int 1)))]
4529 [(set (match_operand:DI 0 "register_operand" "")
4530 (ashift:DI (match_operand:DI 1 "register_operand" "")
4532 "reload_completed && !TARGET_COLDFIRE"
4534 (ashift:DI (match_dup 1) (const_int 2)))
4536 (ashift:DI (match_dup 0) (const_int 1)))]
4540 [(set (match_operand:DI 0 "register_operand" "")
4541 (ashift:DI (match_operand:DI 1 "register_operand" "")
4543 "reload_completed && !TARGET_COLDFIRE"
4545 (rotate:SI (match_dup 2) (const_int 8)))
4547 (rotate:SI (match_dup 3) (const_int 8)))
4548 (set (strict_low_part (subreg:QI (match_dup 0) 3))
4549 (subreg:QI (match_dup 0) 7))
4550 (set (strict_low_part (subreg:QI (match_dup 0) 7))
4553 operands[2] = gen_highpart (SImode, operands[0]);
4554 operands[3] = gen_lowpart (SImode, operands[0]);
4558 [(set (match_operand:DI 0 "register_operand" "")
4559 (ashift:DI (match_operand:DI 1 "register_operand" "")
4561 "reload_completed && !TARGET_COLDFIRE"
4563 (rotate:SI (match_dup 2) (const_int 16)))
4565 (rotate:SI (match_dup 3) (const_int 16)))
4566 (set (strict_low_part (subreg:HI (match_dup 0) 2))
4567 (subreg:HI (match_dup 0) 6))
4568 (set (strict_low_part (subreg:HI (match_dup 0) 6))
4571 operands[2] = gen_highpart (SImode, operands[0]);
4572 operands[3] = gen_lowpart (SImode, operands[0]);
4576 [(set (match_operand:DI 0 "pre_dec_operand" "")
4577 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
4580 [(set (match_dup 0) (const_int 0))
4581 (set (match_dup 0) (match_dup 1))]
4583 operands[0] = adjust_address(operands[0], SImode, 0);
4584 operands[1] = gen_lowpart(SImode, operands[1]);
4588 [(set (match_operand:DI 0 "post_inc_operand" "")
4589 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
4592 [(set (match_dup 0) (match_dup 1))
4593 (set (match_dup 0) (const_int 0))]
4595 operands[0] = adjust_address(operands[0], SImode, 0);
4596 operands[1] = gen_lowpart(SImode, operands[1]);
4599 (define_insn_and_split "*ashldi3_const32"
4600 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>")
4601 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "ro")
4605 "&& reload_completed"
4606 [(set (match_dup 4) (match_dup 3))
4607 (set (match_dup 2) (const_int 0))]
4608 "split_di(operands, 2, operands + 2, operands + 4);")
4611 [(set (match_operand:DI 0 "register_operand" "")
4612 (ashift:DI (match_operand:DI 1 "register_operand" "")
4613 (match_operand 2 "const_int_operand" "")))]
4614 "reload_completed && !TARGET_COLDFIRE
4615 && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40"
4616 [(set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 2)))
4617 (set (match_dup 3) (match_dup 4))
4618 (set (match_dup 4) (const_int 0))]
4620 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4621 operands[3] = gen_highpart (SImode, operands[0]);
4622 operands[4] = gen_lowpart (SImode, operands[0]);
4626 [(set (match_operand:DI 0 "register_operand" "")
4627 (ashift:DI (match_operand:DI 1 "register_operand" "")
4629 "reload_completed && !TARGET_COLDFIRE"
4630 [(set (match_dup 2) (match_dup 3))
4632 (rotate:SI (match_dup 2) (const_int 16)))
4633 (set (match_dup 3) (const_int 0))
4634 (set (strict_low_part (subreg:HI (match_dup 0) 2))
4637 operands[2] = gen_highpart (SImode, operands[0]);
4638 operands[3] = gen_lowpart (SImode, operands[0]);
4642 [(set (match_operand:DI 0 "register_operand" "")
4643 (ashift:DI (match_operand:DI 1 "register_operand" "")
4644 (match_operand 2 "const_int_operand" "")))]
4645 "reload_completed && !TARGET_COLDFIRE
4646 && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 63"
4647 [(set (match_dup 3) (match_dup 2))
4648 (set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 3)))
4649 (set (match_dup 3) (match_dup 4))
4650 (set (match_dup 4) (const_int 0))]
4652 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4653 operands[3] = gen_highpart (SImode, operands[0]);
4654 operands[4] = gen_lowpart (SImode, operands[0]);
4657 (define_insn "*ashldi3"
4658 [(set (match_operand:DI 0 "register_operand" "=d")
4659 (ashift:DI (match_operand:DI 1 "register_operand" "0")
4660 (match_operand 2 "const_int_operand" "n")))]
4662 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4663 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4664 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4667 (define_expand "ashldi3"
4668 [(set (match_operand:DI 0 "register_operand" "")
4669 (ashift:DI (match_operand:DI 1 "register_operand" "")
4670 (match_operand 2 "const_int_operand" "")))]
4673 /* ??? This is a named pattern like this is not allowed to FAIL based
4675 if (GET_CODE (operands[2]) != CONST_INT
4676 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4677 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4678 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4682 ;; On most 68k models, this makes faster code in a special case.
4684 (define_insn "ashlsi_16"
4685 [(set (match_operand:SI 0 "register_operand" "=d")
4686 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4691 return "swap %0\;clr%.w %0";
4694 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4695 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4697 ;; On the 68000, this makes faster code in a special case.
4699 (define_insn "ashlsi_17_24"
4700 [(set (match_operand:SI 0 "register_operand" "=d")
4701 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4702 (match_operand:SI 2 "const_int_operand" "n")))]
4704 && INTVAL (operands[2]) > 16
4705 && INTVAL (operands[2]) <= 24"
4709 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4710 return "lsl%.w %2,%0\;swap %0\;clr%.w %0";
4713 (define_insn "ashlsi3"
4714 [(set (match_operand:SI 0 "register_operand" "=d")
4715 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4716 (match_operand:SI 2 "general_operand" "dI")))]
4719 if (operands[2] == const1_rtx)
4721 cc_status.flags = CC_NO_OVERFLOW;
4722 return "add%.l %0,%0";
4724 return "lsl%.l %2,%0";
4727 (define_insn "ashlhi3"
4728 [(set (match_operand:HI 0 "register_operand" "=d")
4729 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4730 (match_operand:HI 2 "general_operand" "dI")))]
4735 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4736 (ashift:HI (match_dup 0)
4737 (match_operand:HI 1 "general_operand" "dI")))]
4741 (define_insn "ashlqi3"
4742 [(set (match_operand:QI 0 "register_operand" "=d")
4743 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4744 (match_operand:QI 2 "general_operand" "dI")))]
4749 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4750 (ashift:QI (match_dup 0)
4751 (match_operand:QI 1 "general_operand" "dI")))]
4755 ;; On most 68k models, this makes faster code in a special case.
4757 (define_insn "ashrsi_16"
4758 [(set (match_operand:SI 0 "register_operand" "=d")
4759 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4762 "swap %0\;ext%.l %0")
4764 ;; On the 68000, this makes faster code in a special case.
4767 [(set (match_operand:SI 0 "register_operand" "=d")
4768 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4769 (match_operand:SI 2 "const_int_operand" "n")))]
4771 && INTVAL (operands[2]) > 16
4772 && INTVAL (operands[2]) <= 24"
4774 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4775 return "swap %0\;asr%.w %2,%0\;ext%.l %0";
4778 (define_insn "subreghi1ashrdi_const32"
4779 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4780 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4781 (const_int 32)) 6))]
4784 if (GET_CODE (operands[1]) != REG)
4785 operands[1] = adjust_address (operands[1], HImode, 2);
4786 return "move%.w %1,%0";
4788 [(set_attr "type" "move_w")])
4790 (define_insn "subregsi1ashrdi_const32"
4791 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4792 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4793 (const_int 32)) 4))]
4796 return "move%.l %1,%0";
4798 [(set_attr "type" "move_l")])
4800 (define_insn "*ashrdi3_const1"
4801 [(set (match_operand:DI 0 "register_operand" "=d")
4802 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
4806 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4807 return "asr%.l #1,%0\;roxr%.l #1,%1";
4811 [(set (match_operand:DI 0 "register_operand" "")
4812 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4814 "reload_completed && !TARGET_COLDFIRE"
4816 (ashiftrt:DI (match_dup 1) (const_int 1)))
4818 (ashiftrt:DI (match_dup 0) (const_int 1)))]
4822 [(set (match_operand:DI 0 "register_operand" "")
4823 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4825 "reload_completed && !TARGET_COLDFIRE"
4827 (ashiftrt:DI (match_dup 1) (const_int 2)))
4829 (ashiftrt:DI (match_dup 0) (const_int 1)))]
4833 [(set (match_operand:DI 0 "register_operand" "")
4834 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4836 "reload_completed && !TARGET_COLDFIRE"
4837 [(set (strict_low_part (subreg:QI (match_dup 0) 7))
4838 (subreg:QI (match_dup 0) 3))
4840 (ashiftrt:SI (match_dup 2) (const_int 8)))
4842 (rotatert:SI (match_dup 3) (const_int 8)))]
4844 operands[2] = gen_highpart (SImode, operands[0]);
4845 operands[3] = gen_lowpart (SImode, operands[0]);
4849 [(set (match_operand:DI 0 "register_operand" "")
4850 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4852 "reload_completed && !TARGET_COLDFIRE"
4853 [(set (strict_low_part (subreg:HI (match_dup 0) 6))
4854 (subreg:HI (match_dup 0) 2))
4856 (rotate:SI (match_dup 2) (const_int 16)))
4858 (rotate:SI (match_dup 3) (const_int 16)))
4860 (sign_extend:SI (subreg:HI (match_dup 2) 2)))]
4862 operands[2] = gen_highpart (SImode, operands[0]);
4863 operands[3] = gen_lowpart (SImode, operands[0]);
4866 (define_insn "*ashrdi_const32"
4867 [(set (match_operand:DI 0 "register_operand" "=d")
4868 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro")
4874 return "move%.l %1,%R0\;smi %0\;extb%.l %0";
4876 return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0";
4879 (define_insn "*ashrdi_const32_mem"
4880 [(set (match_operand:DI 0 "memory_operand" "=o,<")
4881 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro,ro")
4883 (clobber (match_scratch:SI 2 "=d,d"))]
4887 operands[3] = adjust_address (operands[0], SImode,
4888 which_alternative == 0 ? 4 : 0);
4889 operands[0] = adjust_address (operands[0], SImode, 0);
4890 if (TARGET_68020 || TARGET_COLDFIRE)
4891 return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
4893 return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
4897 [(set (match_operand:DI 0 "register_operand" "")
4898 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4900 "reload_completed && !TARGET_COLDFIRE"
4902 (ashiftrt:SI (match_dup 3) (const_int 31)))
4905 "split_di(operands, 1, operands + 2, operands + 3);")
4907 ;; The predicate below must be general_operand, because ashrdi3 allows that
4908 (define_insn "ashrdi_const"
4909 [(set (match_operand:DI 0 "register_operand" "=d")
4910 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
4911 (match_operand 2 "const_int_operand" "n")))]
4913 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4914 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4915 || INTVAL (operands[2]) == 31
4916 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4918 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4920 if (INTVAL (operands[2]) == 48)
4921 return "swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0";
4922 if (INTVAL (operands[2]) == 31)
4923 return "add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0";
4924 if (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)
4926 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4927 output_asm_insn (INTVAL (operands[2]) <= 8 ? "asr%.l %2,%0" :
4928 "moveq %2,%1\;asr%.l %1,%0", operands);
4929 output_asm_insn ("mov%.l %0,%1\;smi %0", operands);
4930 return INTVAL (operands[2]) >= 15 ? "ext%.w %d0" :
4931 TARGET_68020 ? "extb%.l %0" : "ext%.w %0\;ext%.l %0";
4936 (define_expand "ashrdi3"
4937 [(set (match_operand:DI 0 "register_operand" "")
4938 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4939 (match_operand 2 "const_int_operand" "")))]
4942 /* ??? This is a named pattern like this is not allowed to FAIL based
4944 if (GET_CODE (operands[2]) != CONST_INT
4945 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4946 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4947 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4951 ;; On all 68k models, this makes faster code in a special case.
4953 (define_insn "ashrsi_31"
4954 [(set (match_operand:SI 0 "register_operand" "=d")
4955 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4959 return "add%.l %0,%0\;subx%.l %0,%0";
4962 (define_insn "ashrsi3"
4963 [(set (match_operand:SI 0 "register_operand" "=d")
4964 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4965 (match_operand:SI 2 "general_operand" "dI")))]
4968 [(set_attr "type" "asr_l")
4969 (set_attr "opy" "2")])
4971 (define_insn "ashrhi3"
4972 [(set (match_operand:HI 0 "register_operand" "=d")
4973 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4974 (match_operand:HI 2 "general_operand" "dI")))]
4979 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4980 (ashiftrt:HI (match_dup 0)
4981 (match_operand:HI 1 "general_operand" "dI")))]
4985 (define_insn "ashrqi3"
4986 [(set (match_operand:QI 0 "register_operand" "=d")
4987 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4988 (match_operand:QI 2 "general_operand" "dI")))]
4993 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4994 (ashiftrt:QI (match_dup 0)
4995 (match_operand:QI 1 "general_operand" "dI")))]
4999 ;; logical shift instructions
5001 ;; commented out because of reload problems in 950612-1.c
5004 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
5005 ;; (const_int 32)) 4))
5006 ;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm")
5007 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
5008 ;; (const_int 32)) 4))]
5011 ;; return "move%.l %0,%1";
5016 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
5017 ;; (const_int 32)) 0))
5018 ;; (set (match_operand:DI 1 "nonimmediate_operand" "=do")
5019 ;; (lshiftrt:DI (match_dup 0)
5020 ;; (const_int 32)))]
5023 ;; if (GET_CODE (operands[1]) == REG)
5024 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
5026 ;; operands[2] = adjust_address (operands[1], SImode, 4);
5027 ;; return "move%.l %0,%2\;clr%.l %1";
5030 (define_insn "subreg1lshrdi_const32"
5031 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5032 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
5033 (const_int 32)) 4))]
5036 [(set_attr "type" "move_l")])
5038 (define_insn "*lshrdi3_const1"
5039 [(set (match_operand:DI 0 "register_operand" "=d")
5040 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
5043 "lsr%.l #1,%0\;roxr%.l #1,%R0")
5046 [(set (match_operand:DI 0 "register_operand" "")
5047 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5049 "reload_completed && !TARGET_COLDFIRE"
5051 (lshiftrt:DI (match_dup 1) (const_int 1)))
5053 (lshiftrt:DI (match_dup 0) (const_int 1)))]
5057 [(set (match_operand:DI 0 "register_operand" "")
5058 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5060 "reload_completed && !TARGET_COLDFIRE"
5062 (lshiftrt:DI (match_dup 1) (const_int 2)))
5064 (lshiftrt:DI (match_dup 0) (const_int 1)))]
5068 [(set (match_operand:DI 0 "register_operand" "")
5069 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5071 "reload_completed && !TARGET_COLDFIRE"
5072 [(set (strict_low_part (subreg:QI (match_dup 0) 7))
5073 (subreg:QI (match_dup 0) 3))
5075 (lshiftrt:SI (match_dup 2) (const_int 8)))
5077 (rotatert:SI (match_dup 3) (const_int 8)))]
5079 operands[2] = gen_highpart (SImode, operands[0]);
5080 operands[3] = gen_lowpart (SImode, operands[0]);
5084 [(set (match_operand:DI 0 "register_operand" "")
5085 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5087 "reload_completed && !TARGET_COLDFIRE"
5088 [(set (strict_low_part (subreg:HI (match_dup 0) 6))
5089 (subreg:HI (match_dup 0) 2))
5090 (set (strict_low_part (subreg:HI (match_dup 0) 2))
5093 (rotate:SI (match_dup 3) (const_int 16)))
5095 (rotate:SI (match_dup 2) (const_int 16)))]
5097 operands[2] = gen_highpart (SImode, operands[0]);
5098 operands[3] = gen_lowpart (SImode, operands[0]);
5102 [(set (match_operand:DI 0 "pre_dec_operand" "")
5103 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
5106 [(set (match_dup 0) (match_dup 1))
5107 (set (match_dup 0) (const_int 0))]
5109 operands[0] = adjust_address(operands[0], SImode, 0);
5110 operands[1] = gen_highpart(SImode, operands[1]);
5114 [(set (match_operand:DI 0 "post_inc_operand" "")
5115 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
5118 [(set (match_dup 0) (const_int 0))
5119 (set (match_dup 0) (match_dup 1))]
5121 operands[0] = adjust_address(operands[0], SImode, 0);
5122 operands[1] = gen_highpart(SImode, operands[1]);
5126 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5127 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
5130 [(set (match_dup 2) (match_dup 5))
5131 (set (match_dup 4) (const_int 0))]
5132 "split_di(operands, 2, operands + 2, operands + 4);")
5134 (define_insn "*lshrdi_const32"
5135 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>")
5136 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
5142 [(set (match_operand:DI 0 "register_operand" "")
5143 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5144 (match_operand 2 "const_int_operand" "")))]
5145 "reload_completed && !TARGET_COLDFIRE
5146 && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40"
5147 [(set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 2)))
5148 (set (match_dup 4) (match_dup 3))
5149 (set (match_dup 3) (const_int 0))]
5151 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
5152 operands[3] = gen_highpart (SImode, operands[0]);
5153 operands[4] = gen_lowpart (SImode, operands[0]);
5157 [(set (match_operand:DI 0 "register_operand" "")
5158 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5161 [(set (match_dup 3) (match_dup 2))
5162 (set (strict_low_part (subreg:HI (match_dup 0) 6))
5164 (set (match_dup 2) (const_int 0))
5166 (rotate:SI (match_dup 3) (const_int 16)))]
5168 operands[2] = gen_highpart (SImode, operands[0]);
5169 operands[3] = gen_lowpart (SImode, operands[0]);
5173 [(set (match_operand:DI 0 "register_operand" "")
5174 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5175 (match_operand 2 "const_int_operand" "")))]
5176 "reload_completed && !TARGET_COLDFIRE
5177 && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 62"
5178 [(set (match_dup 4) (match_dup 2))
5179 (set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 4)))
5180 (set (match_dup 4) (match_dup 3))
5181 (set (match_dup 3) (const_int 0))]
5183 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
5184 operands[3] = gen_highpart (SImode, operands[0]);
5185 operands[4] = gen_lowpart (SImode, operands[0]);
5188 (define_insn "*lshrdi_const63"
5189 [(set (match_operand:DI 0 "register_operand" "=d")
5190 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
5193 "add%.l %0,%0\;clr%.l %0\;clr%.l %R1\;addx%.l %R1,%R1")
5195 (define_insn "*lshrdi3_const"
5196 [(set (match_operand:DI 0 "register_operand" "=d")
5197 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
5198 (match_operand 2 "const_int_operand" "n")))]
5200 && ((INTVAL (operands[2]) >= 2 && INTVAL (operands[2]) <= 3)
5201 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
5202 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
5205 (define_expand "lshrdi3"
5206 [(set (match_operand:DI 0 "register_operand" "")
5207 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5208 (match_operand 2 "const_int_operand" "")))]
5211 /* ??? This is a named pattern like this is not allowed to FAIL based
5213 if (GET_CODE (operands[2]) != CONST_INT
5214 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
5215 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
5216 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
5220 ;; On all 68k models, this makes faster code in a special case.
5222 (define_insn "lshrsi_31"
5223 [(set (match_operand:SI 0 "register_operand" "=d")
5224 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5228 return "add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0";
5231 ;; On most 68k models, this makes faster code in a special case.
5233 (define_insn "lshrsi_16"
5234 [(set (match_operand:SI 0 "register_operand" "=d")
5235 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5240 return "clr%.w %0\;swap %0";
5243 ;; On the 68000, this makes faster code in a special case.
5245 (define_insn "lshrsi_17_24"
5246 [(set (match_operand:SI 0 "register_operand" "=d")
5247 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5248 (match_operand:SI 2 "const_int_operand" "n")))]
5250 && INTVAL (operands[2]) > 16
5251 && INTVAL (operands[2]) <= 24"
5253 /* I think lsr%.w sets the CC properly. */
5254 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
5255 return "clr%.w %0\;swap %0\;lsr%.w %2,%0";
5258 (define_insn "lshrsi3"
5259 [(set (match_operand:SI 0 "register_operand" "=d")
5260 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5261 (match_operand:SI 2 "general_operand" "dI")))]
5264 [(set_attr "type" "lsr_l")
5265 (set_attr "opy" "2")])
5267 (define_insn "lshrhi3"
5268 [(set (match_operand:HI 0 "register_operand" "=d")
5269 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
5270 (match_operand:HI 2 "general_operand" "dI")))]
5275 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5276 (lshiftrt:HI (match_dup 0)
5277 (match_operand:HI 1 "general_operand" "dI")))]
5281 (define_insn "lshrqi3"
5282 [(set (match_operand:QI 0 "register_operand" "=d")
5283 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
5284 (match_operand:QI 2 "general_operand" "dI")))]
5289 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5290 (lshiftrt:QI (match_dup 0)
5291 (match_operand:QI 1 "general_operand" "dI")))]
5295 ;; rotate instructions
5297 (define_insn "rotlsi3"
5298 [(set (match_operand:SI 0 "register_operand" "=d")
5299 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5300 (match_operand:SI 2 "general_operand" "dINO")))]
5303 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5305 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5307 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
5308 return "ror%.l %2,%0";
5311 return "rol%.l %2,%0";
5314 (define_insn "rotlhi3"
5315 [(set (match_operand:HI 0 "register_operand" "=d")
5316 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5317 (match_operand:HI 2 "general_operand" "dIP")))]
5320 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5322 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5323 return "ror%.w %2,%0";
5326 return "rol%.w %2,%0";
5330 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5331 (rotate:HI (match_dup 0)
5332 (match_operand:HI 1 "general_operand" "dIP")))]
5335 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5337 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5338 return "ror%.w %2,%0";
5341 return "rol%.w %2,%0";
5344 (define_insn "rotlqi3"
5345 [(set (match_operand:QI 0 "register_operand" "=d")
5346 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5347 (match_operand:QI 2 "general_operand" "dI")))]
5350 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5352 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5353 return "ror%.b %2,%0";
5356 return "rol%.b %2,%0";
5360 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5361 (rotate:QI (match_dup 0)
5362 (match_operand:QI 1 "general_operand" "dI")))]
5365 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5367 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5368 return "ror%.b %2,%0";
5371 return "rol%.b %2,%0";
5374 (define_insn "rotrsi3"
5375 [(set (match_operand:SI 0 "register_operand" "=d")
5376 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5377 (match_operand:SI 2 "general_operand" "dI")))]
5381 (define_insn "rotrhi3"
5382 [(set (match_operand:HI 0 "register_operand" "=d")
5383 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5384 (match_operand:HI 2 "general_operand" "dI")))]
5389 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5390 (rotatert:HI (match_dup 0)
5391 (match_operand:HI 1 "general_operand" "dI")))]
5395 (define_insn "rotrqi3"
5396 [(set (match_operand:QI 0 "register_operand" "=d")
5397 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5398 (match_operand:QI 2 "general_operand" "dI")))]
5403 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5404 (rotatert:QI (match_dup 0)
5405 (match_operand:QI 1 "general_operand" "dI")))]
5410 ;; Bit set/clear in memory byte.
5412 ;; set bit, bit number is int
5413 (define_insn "bsetmemqi"
5414 [(set (match_operand:QI 0 "memory_operand" "+m")
5415 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5416 (match_operand:SI 1 "general_operand" "d")) 3)
5421 return "bset %1,%0";
5423 [(set_attr "type" "bset")])
5425 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5426 (define_insn "*bsetmemqi_ext"
5427 [(set (match_operand:QI 0 "memory_operand" "+m")
5428 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5429 (match_operator:SI 2 "extend_operator"
5430 [(match_operand 1 "general_operand" "d")])) 3)
5435 return "bset %1,%0";
5437 [(set_attr "type" "bset")])
5439 ;; clear bit, bit number is int
5440 (define_insn "bclrmemqi"
5441 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5443 (minus:SI (const_int 7)
5444 (match_operand:SI 1 "general_operand" "d")))
5449 return "bclr %1,%0";
5451 [(set_attr "type" "bclr")])
5453 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5454 (define_insn "*bclrmemqi_ext"
5455 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5457 (minus:SI (const_int 7)
5458 (match_operator:SI 2 "extend_operator"
5459 [(match_operand 1 "general_operand" "d")])))
5464 return "bclr %1,%0";
5466 [(set_attr "type" "bclr")])
5468 ;; Special cases of bit-field insns which we should
5469 ;; recognize in preference to the general case.
5470 ;; These handle aligned 8-bit and 16-bit fields,
5471 ;; which can usually be done with move instructions.
5474 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5475 ; alignment of structure members is specified.
5477 ; The move is allowed to be odd byte aligned, because that's still faster
5478 ; than an odd byte aligned bit-field instruction.
5481 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5483 (match_operand:SI 1 "const_int_operand" "n"))
5484 (match_operand:SI 2 "general_src_operand" "rmSi"))]
5485 "TARGET_68020 && TARGET_BITFIELD
5486 && (INTVAL (operands[1]) % 8) == 0
5487 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5490 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
5492 return "move%.l %2,%0";
5496 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5497 (match_operand:SI 1 "const_int_operand" "n")
5498 (match_operand:SI 2 "const_int_operand" "n"))
5499 (match_operand:SI 3 "register_operand" "d"))]
5500 "TARGET_68020 && TARGET_BITFIELD
5501 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5502 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5503 && (GET_CODE (operands[0]) == REG
5504 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5506 if (REG_P (operands[0]))
5508 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5509 return "bfins %3,%0{%b2:%b1}";
5512 operands[0] = adjust_address (operands[0],
5513 INTVAL (operands[1]) == 8 ? QImode : HImode,
5514 INTVAL (operands[2]) / 8);
5516 if (GET_CODE (operands[3]) == MEM)
5517 operands[3] = adjust_address (operands[3],
5518 INTVAL (operands[1]) == 8 ? QImode : HImode,
5519 (32 - INTVAL (operands[1])) / 8);
5521 if (INTVAL (operands[1]) == 8)
5522 return "move%.b %3,%0";
5523 return "move%.w %3,%0";
5528 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5529 ; alignment of structure members is specified.
5531 ; The move is allowed to be odd byte aligned, because that's still faster
5532 ; than an odd byte aligned bit-field instruction.
5535 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5536 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5538 (match_operand:SI 2 "const_int_operand" "n")))]
5539 "TARGET_68020 && TARGET_BITFIELD
5540 && (INTVAL (operands[2]) % 8) == 0
5541 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5544 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5546 return "move%.l %1,%0";
5550 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
5551 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5552 (match_operand:SI 2 "const_int_operand" "n")
5553 (match_operand:SI 3 "const_int_operand" "n")))]
5554 "TARGET_68020 && TARGET_BITFIELD
5555 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5556 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5557 && (GET_CODE (operands[1]) == REG
5558 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5560 cc_status.flags |= CC_NOT_NEGATIVE;
5561 if (REG_P (operands[1]))
5563 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5564 return "bfextu %1{%b3:%b2},%0";
5568 = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
5570 output_asm_insn ("clr%.l %0", operands);
5571 if (GET_CODE (operands[0]) == MEM)
5572 operands[0] = adjust_address (operands[0],
5573 INTVAL (operands[2]) == 8 ? QImode : HImode,
5574 (32 - INTVAL (operands[1])) / 8);
5576 if (INTVAL (operands[2]) == 8)
5577 return "move%.b %1,%0";
5578 return "move%.w %1,%0";
5582 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5583 ; alignment of structure members is specified.
5585 ; The move is allowed to be odd byte aligned, because that's still faster
5586 ; than an odd byte aligned bit-field instruction.
5589 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5590 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5592 (match_operand:SI 2 "const_int_operand" "n")))]
5593 "TARGET_68020 && TARGET_BITFIELD
5594 && (INTVAL (operands[2]) % 8) == 0
5595 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5598 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5600 return "move%.l %1,%0";
5604 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5605 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5606 (match_operand:SI 2 "const_int_operand" "n")
5607 (match_operand:SI 3 "const_int_operand" "n")))]
5608 "TARGET_68020 && TARGET_BITFIELD
5609 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5610 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5611 && (GET_CODE (operands[1]) == REG
5612 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5614 if (REG_P (operands[1]))
5616 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5617 return "bfexts %1{%b3:%b2},%0";
5621 = adjust_address (operands[1],
5622 INTVAL (operands[2]) == 8 ? QImode : HImode,
5623 INTVAL (operands[3]) / 8);
5625 if (INTVAL (operands[2]) == 8)
5626 return "move%.b %1,%0\;extb%.l %0";
5627 return "move%.w %1,%0\;ext%.l %0";
5630 ;; Bit-field instructions, general cases.
5631 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5632 ;; so that its address is reloaded.
5634 (define_expand "extv"
5635 [(set (match_operand:SI 0 "register_operand" "")
5636 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5637 (match_operand:SI 2 "const_int_operand" "")
5638 (match_operand:SI 3 "const_int_operand" "")))]
5639 "TARGET_68020 && TARGET_BITFIELD"
5643 [(set (match_operand:SI 0 "register_operand" "=d")
5644 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5645 (match_operand:SI 2 "nonmemory_operand" "dn")
5646 (match_operand:SI 3 "nonmemory_operand" "dn")))]
5647 "TARGET_68020 && TARGET_BITFIELD"
5648 "bfexts %1{%b3:%b2},%0")
5650 (define_expand "extzv"
5651 [(set (match_operand:SI 0 "register_operand" "")
5652 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5653 (match_operand:SI 2 "const_int_operand" "")
5654 (match_operand:SI 3 "const_int_operand" "")))]
5655 "TARGET_68020 && TARGET_BITFIELD"
5659 [(set (match_operand:SI 0 "register_operand" "=d")
5660 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
5661 (match_operand:SI 2 "nonmemory_operand" "dn")
5662 (match_operand:SI 3 "nonmemory_operand" "dn")))]
5663 "TARGET_68020 && TARGET_BITFIELD"
5665 if (GET_CODE (operands[2]) == CONST_INT)
5667 if (INTVAL (operands[2]) != 32)
5668 cc_status.flags |= CC_NOT_NEGATIVE;
5674 return "bfextu %1{%b3:%b2},%0";
5678 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5679 (match_operand:SI 1 "nonmemory_operand" "dn")
5680 (match_operand:SI 2 "nonmemory_operand" "dn"))
5681 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5682 (match_operand 3 "const_int_operand" "n")))]
5683 "TARGET_68020 && TARGET_BITFIELD
5684 && (INTVAL (operands[3]) == -1
5685 || (GET_CODE (operands[1]) == CONST_INT
5686 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5689 return "bfchg %0{%b2:%b1}";
5693 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5694 (match_operand:SI 1 "nonmemory_operand" "dn")
5695 (match_operand:SI 2 "nonmemory_operand" "dn"))
5697 "TARGET_68020 && TARGET_BITFIELD"
5700 return "bfclr %0{%b2:%b1}";
5704 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5705 (match_operand:SI 1 "general_operand" "dn")
5706 (match_operand:SI 2 "general_operand" "dn"))
5708 "TARGET_68020 && TARGET_BITFIELD"
5711 return "bfset %0{%b2:%b1}";
5714 (define_expand "insv"
5715 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
5716 (match_operand:SI 1 "const_int_operand" "")
5717 (match_operand:SI 2 "const_int_operand" ""))
5718 (match_operand:SI 3 "register_operand" ""))]
5719 "TARGET_68020 && TARGET_BITFIELD"
5723 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5724 (match_operand:SI 1 "nonmemory_operand" "dn")
5725 (match_operand:SI 2 "nonmemory_operand" "dn"))
5726 (match_operand:SI 3 "register_operand" "d"))]
5727 "TARGET_68020 && TARGET_BITFIELD"
5728 "bfins %3,%0{%b2:%b1}")
5730 ;; Now recognize bit-field insns that operate on registers
5731 ;; (or at least were intended to do so).
5734 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5735 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5736 (match_operand:SI 2 "const_int_operand" "n")
5737 (match_operand:SI 3 "const_int_operand" "n")))]
5738 "TARGET_68020 && TARGET_BITFIELD"
5739 "bfexts %1{%b3:%b2},%0")
5742 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5743 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5744 (match_operand:SI 2 "const_int_operand" "n")
5745 (match_operand:SI 3 "const_int_operand" "n")))]
5746 "TARGET_68020 && TARGET_BITFIELD"
5748 if (GET_CODE (operands[2]) == CONST_INT)
5750 if (INTVAL (operands[2]) != 32)
5751 cc_status.flags |= CC_NOT_NEGATIVE;
5757 return "bfextu %1{%b3:%b2},%0";
5761 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5762 (match_operand:SI 1 "const_int_operand" "n")
5763 (match_operand:SI 2 "const_int_operand" "n"))
5765 "TARGET_68020 && TARGET_BITFIELD"
5768 return "bfclr %0{%b2:%b1}";
5772 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5773 (match_operand:SI 1 "const_int_operand" "n")
5774 (match_operand:SI 2 "const_int_operand" "n"))
5776 "TARGET_68020 && TARGET_BITFIELD"
5779 return "bfset %0{%b2:%b1}";
5783 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5784 (match_operand:SI 1 "const_int_operand" "n")
5785 (match_operand:SI 2 "const_int_operand" "n"))
5786 (match_operand:SI 3 "register_operand" "d"))]
5787 "TARGET_68020 && TARGET_BITFIELD"
5790 /* These special cases are now recognized by a specific pattern. */
5791 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5792 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5793 return "move%.w %3,%0";
5794 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5795 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5796 return "move%.b %3,%0";
5798 return "bfins %3,%0{%b2:%b1}";
5801 ;; Special patterns for optimizing bit-field instructions.
5805 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5806 (match_operand:SI 1 "const_int_operand" "n")
5807 (match_operand:SI 2 "general_operand" "dn")))]
5808 "TARGET_68020 && TARGET_BITFIELD"
5810 if (operands[1] == const1_rtx
5811 && GET_CODE (operands[2]) == CONST_INT)
5813 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5814 return output_btst (operands,
5815 GEN_INT (width - INTVAL (operands[2])),
5816 operands[0], insn, 1000);
5817 /* Pass 1000 as SIGNPOS argument so that btst will
5818 not think we are testing the sign bit for an `and'
5819 and assume that nonzero implies a negative result. */
5821 if (INTVAL (operands[1]) != 32)
5822 cc_status.flags = CC_NOT_NEGATIVE;
5823 return "bftst %0{%b2:%b1}";
5827 ;;; now handle the register cases
5830 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5831 (match_operand:SI 1 "const_int_operand" "n")
5832 (match_operand:SI 2 "general_operand" "dn")))]
5833 "TARGET_68020 && TARGET_BITFIELD"
5835 if (operands[1] == const1_rtx
5836 && GET_CODE (operands[2]) == CONST_INT)
5838 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5839 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5840 operands[0], insn, 1000);
5841 /* Pass 1000 as SIGNPOS argument so that btst will
5842 not think we are testing the sign bit for an `and'
5843 and assume that nonzero implies a negative result. */
5845 if (INTVAL (operands[1]) != 32)
5846 cc_status.flags = CC_NOT_NEGATIVE;
5847 return "bftst %0{%b2:%b1}";
5850 (define_insn "scc0_di"
5851 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
5852 (match_operator 1 "valid_dbcc_comparison_p"
5853 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5856 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5859 (define_insn "scc0_di_5200"
5860 [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
5861 (match_operator 1 "valid_dbcc_comparison_p"
5862 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5865 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5868 (define_insn "scc_di"
5869 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
5870 (match_operator 1 "valid_dbcc_comparison_p"
5871 [(match_operand:DI 2 "general_operand" "ro,r")
5872 (match_operand:DI 3 "general_operand" "r,ro")]))]
5875 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5878 (define_insn "scc_di_5200"
5879 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
5880 (match_operator 1 "valid_dbcc_comparison_p"
5881 [(match_operand:DI 2 "general_operand" "ro,r")
5882 (match_operand:DI 3 "general_operand" "r,ro")]))]
5885 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5888 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5889 ;; memory, but we cannot allow it to be in memory in case the address
5890 ;; needs to be reloaded.
5892 (define_expand "seq"
5893 [(set (match_operand:QI 0 "register_operand" "")
5894 (eq:QI (cc0) (const_int 0)))]
5897 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5898 && m68k_last_compare_had_fp_operands)
5900 m68k_last_compare_had_fp_operands = 0;
5906 [(set (match_operand:QI 0 "register_operand" "=d")
5907 (eq:QI (cc0) (const_int 0)))]
5910 cc_status = cc_prev_status;
5911 OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0");
5914 (define_expand "sne"
5915 [(set (match_operand:QI 0 "register_operand" "")
5916 (ne:QI (cc0) (const_int 0)))]
5919 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5920 && m68k_last_compare_had_fp_operands)
5922 m68k_last_compare_had_fp_operands = 0;
5928 [(set (match_operand:QI 0 "register_operand" "=d")
5929 (ne:QI (cc0) (const_int 0)))]
5932 cc_status = cc_prev_status;
5933 OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0");
5936 (define_expand "sgt"
5937 [(set (match_operand:QI 0 "register_operand" "")
5938 (gt:QI (cc0) (const_int 0)))]
5941 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5942 && m68k_last_compare_had_fp_operands)
5944 m68k_last_compare_had_fp_operands = 0;
5950 [(set (match_operand:QI 0 "register_operand" "=d")
5951 (gt:QI (cc0) (const_int 0)))]
5954 cc_status = cc_prev_status;
5955 OUTPUT_JUMP ("sgt %0", "fsgt %0", 0);
5958 (define_expand "sgtu"
5959 [(set (match_operand:QI 0 "register_operand" "")
5960 (gtu:QI (cc0) (const_int 0)))]
5965 [(set (match_operand:QI 0 "register_operand" "=d")
5966 (gtu:QI (cc0) (const_int 0)))]
5969 cc_status = cc_prev_status;
5973 (define_expand "slt"
5974 [(set (match_operand:QI 0 "register_operand" "")
5975 (lt:QI (cc0) (const_int 0)))]
5978 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5979 && m68k_last_compare_had_fp_operands)
5981 m68k_last_compare_had_fp_operands = 0;
5987 [(set (match_operand:QI 0 "register_operand" "=d")
5988 (lt:QI (cc0) (const_int 0)))]
5991 cc_status = cc_prev_status;
5992 OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0");
5995 (define_expand "sltu"
5996 [(set (match_operand:QI 0 "register_operand" "")
5997 (ltu:QI (cc0) (const_int 0)))]
6002 [(set (match_operand:QI 0 "register_operand" "=d")
6003 (ltu:QI (cc0) (const_int 0)))]
6006 cc_status = cc_prev_status;
6010 (define_expand "sge"
6011 [(set (match_operand:QI 0 "register_operand" "")
6012 (ge:QI (cc0) (const_int 0)))]
6015 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
6016 && m68k_last_compare_had_fp_operands)
6018 m68k_last_compare_had_fp_operands = 0;
6024 [(set (match_operand:QI 0 "register_operand" "=d")
6025 (ge:QI (cc0) (const_int 0)))]
6028 cc_status = cc_prev_status;
6029 OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0");
6032 (define_expand "sgeu"
6033 [(set (match_operand:QI 0 "register_operand" "")
6034 (geu:QI (cc0) (const_int 0)))]
6039 [(set (match_operand:QI 0 "register_operand" "=d")
6040 (geu:QI (cc0) (const_int 0)))]
6043 cc_status = cc_prev_status;
6046 [(set_attr "type" "scc")])
6048 (define_expand "sle"
6049 [(set (match_operand:QI 0 "register_operand" "")
6050 (le:QI (cc0) (const_int 0)))]
6053 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
6054 && m68k_last_compare_had_fp_operands)
6056 m68k_last_compare_had_fp_operands = 0;
6062 [(set (match_operand:QI 0 "register_operand" "=d")
6063 (le:QI (cc0) (const_int 0)))]
6066 cc_status = cc_prev_status;
6067 OUTPUT_JUMP ("sle %0", "fsle %0", 0);
6070 (define_expand "sleu"
6071 [(set (match_operand:QI 0 "register_operand" "")
6072 (leu:QI (cc0) (const_int 0)))]
6077 [(set (match_operand:QI 0 "register_operand" "=d")
6078 (leu:QI (cc0) (const_int 0)))]
6081 cc_status = cc_prev_status;
6084 [(set_attr "type" "scc")])
6086 (define_expand "sordered"
6087 [(set (match_operand:QI 0 "register_operand" "")
6088 (ordered:QI (cc0) (const_int 0)))]
6089 "TARGET_68881 && !TUNE_68060"
6091 gcc_assert (m68k_last_compare_had_fp_operands);
6092 m68k_last_compare_had_fp_operands = 0;
6095 (define_insn "*sordered_1"
6096 [(set (match_operand:QI 0 "register_operand" "=d")
6097 (ordered:QI (cc0) (const_int 0)))]
6098 "TARGET_68881 && !TUNE_68060"
6100 cc_status = cc_prev_status;
6104 (define_expand "sunordered"
6105 [(set (match_operand:QI 0 "register_operand" "")
6106 (unordered:QI (cc0) (const_int 0)))]
6107 "TARGET_68881 && !TUNE_68060"
6109 gcc_assert (m68k_last_compare_had_fp_operands);
6110 m68k_last_compare_had_fp_operands = 0;
6113 (define_insn "*sunordered_1"
6114 [(set (match_operand:QI 0 "register_operand" "=d")
6115 (unordered:QI (cc0) (const_int 0)))]
6116 "TARGET_68881 && !TUNE_68060"
6118 cc_status = cc_prev_status;
6122 (define_expand "suneq"
6123 [(set (match_operand:QI 0 "register_operand" "")
6124 (uneq:QI (cc0) (const_int 0)))]
6125 "TARGET_68881 && !TUNE_68060"
6127 gcc_assert (m68k_last_compare_had_fp_operands);
6128 m68k_last_compare_had_fp_operands = 0;
6131 (define_insn "*suneq_1"
6132 [(set (match_operand:QI 0 "register_operand" "=d")
6133 (uneq:QI (cc0) (const_int 0)))]
6134 "TARGET_68881 && !TUNE_68060"
6136 cc_status = cc_prev_status;
6140 (define_expand "sunge"
6141 [(set (match_operand:QI 0 "register_operand" "")
6142 (unge:QI (cc0) (const_int 0)))]
6143 "TARGET_68881 && !TUNE_68060"
6145 gcc_assert (m68k_last_compare_had_fp_operands);
6146 m68k_last_compare_had_fp_operands = 0;
6149 (define_insn "*sunge_1"
6150 [(set (match_operand:QI 0 "register_operand" "=d")
6151 (unge:QI (cc0) (const_int 0)))]
6152 "TARGET_68881 && !TUNE_68060"
6154 cc_status = cc_prev_status;
6158 (define_expand "sungt"
6159 [(set (match_operand:QI 0 "register_operand" "")
6160 (ungt:QI (cc0) (const_int 0)))]
6161 "TARGET_68881 && !TUNE_68060"
6163 gcc_assert (m68k_last_compare_had_fp_operands);
6164 m68k_last_compare_had_fp_operands = 0;
6167 (define_insn "*sungt_1"
6168 [(set (match_operand:QI 0 "register_operand" "=d")
6169 (ungt:QI (cc0) (const_int 0)))]
6170 "TARGET_68881 && !TUNE_68060"
6172 cc_status = cc_prev_status;
6176 (define_expand "sunle"
6177 [(set (match_operand:QI 0 "register_operand" "")
6178 (unle:QI (cc0) (const_int 0)))]
6179 "TARGET_68881 && !TUNE_68060"
6181 gcc_assert (m68k_last_compare_had_fp_operands);
6182 m68k_last_compare_had_fp_operands = 0;
6185 (define_insn "*sunle_1"
6186 [(set (match_operand:QI 0 "register_operand" "=d")
6187 (unle:QI (cc0) (const_int 0)))]
6188 "TARGET_68881 && !TUNE_68060"
6190 cc_status = cc_prev_status;
6194 (define_expand "sunlt"
6195 [(set (match_operand:QI 0 "register_operand" "")
6196 (unlt:QI (cc0) (const_int 0)))]
6197 "TARGET_68881 && !TUNE_68060"
6199 gcc_assert (m68k_last_compare_had_fp_operands);
6200 m68k_last_compare_had_fp_operands = 0;
6203 (define_insn "*sunlt_1"
6204 [(set (match_operand:QI 0 "register_operand" "=d")
6205 (unlt:QI (cc0) (const_int 0)))]
6206 "TARGET_68881 && !TUNE_68060"
6208 cc_status = cc_prev_status;
6212 (define_expand "sltgt"
6213 [(set (match_operand:QI 0 "register_operand" "")
6214 (ltgt:QI (cc0) (const_int 0)))]
6215 "TARGET_68881 && !TUNE_68060"
6217 gcc_assert (m68k_last_compare_had_fp_operands);
6218 m68k_last_compare_had_fp_operands = 0;
6221 (define_insn "*sltgt_1"
6222 [(set (match_operand:QI 0 "register_operand" "=d")
6223 (ltgt:QI (cc0) (const_int 0)))]
6224 "TARGET_68881 && !TUNE_68060"
6226 cc_status = cc_prev_status;
6230 (define_insn "*fsogt_1"
6231 [(set (match_operand:QI 0 "register_operand" "=d")
6232 (not:QI (unle:QI (cc0) (const_int 0))))]
6233 "TARGET_68881 && !TUNE_68060"
6235 cc_status = cc_prev_status;
6239 (define_insn "*fsoge_1"
6240 [(set (match_operand:QI 0 "register_operand" "=d")
6241 (not:QI (unlt:QI (cc0) (const_int 0))))]
6242 "TARGET_68881 && !TUNE_68060"
6244 cc_status = cc_prev_status;
6248 (define_insn "*fsolt_1"
6249 [(set (match_operand:QI 0 "register_operand" "=d")
6250 (not:QI (unge:QI (cc0) (const_int 0))))]
6251 "TARGET_68881 && !TUNE_68060"
6253 cc_status = cc_prev_status;
6257 (define_insn "*fsole_1"
6258 [(set (match_operand:QI 0 "register_operand" "=d")
6259 (not:QI (ungt:QI (cc0) (const_int 0))))]
6260 "TARGET_68881 && !TUNE_68060"
6262 cc_status = cc_prev_status;
6266 ;; Basic conditional jump instructions.
6268 (define_insn "beq0_di"
6270 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
6272 (label_ref (match_operand 1 "" ","))
6274 (clobber (match_scratch:SI 2 "=d,d"))]
6278 if (which_alternative == 1)
6279 return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1";
6280 if ((cc_prev_status.value1
6281 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6282 || (cc_prev_status.value2
6283 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6285 cc_status = cc_prev_status;
6288 if (GET_CODE (operands[0]) == REG)
6289 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6291 operands[3] = adjust_address (operands[0], SImode, 4);
6292 if (! ADDRESS_REG_P (operands[0]))
6294 if (reg_overlap_mentioned_p (operands[2], operands[0]))
6296 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6297 return "or%.l %0,%2\;jeq %l1";
6299 return "or%.l %3,%2\;jeq %l1";
6301 return "move%.l %0,%2\;or%.l %3,%2\;jeq %l1";
6303 operands[4] = gen_label_rtx();
6304 if (TARGET_68020 || TARGET_COLDFIRE)
6305 output_asm_insn ("tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1", operands);
6307 output_asm_insn ("cmp%.w #0,%0\;jne %l4\;cmp%.w #0,%3\;jeq %l1", operands);
6308 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6309 CODE_LABEL_NUMBER (operands[4]));
6313 (define_insn "bne0_di"
6315 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
6317 (label_ref (match_operand 1 "" ","))
6319 (clobber (match_scratch:SI 2 "=d,X"))]
6322 if ((cc_prev_status.value1
6323 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6324 || (cc_prev_status.value2
6325 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6327 cc_status = cc_prev_status;
6331 if (GET_CODE (operands[0]) == REG)
6332 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6334 operands[3] = adjust_address (operands[0], SImode, 4);
6335 if (!ADDRESS_REG_P (operands[0]))
6337 if (reg_overlap_mentioned_p (operands[2], operands[0]))
6339 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6340 return "or%.l %0,%2\;jne %l1";
6342 return "or%.l %3,%2\;jne %l1";
6344 return "move%.l %0,%2\;or%.l %3,%2\;jne %l1";
6346 if (TARGET_68020 || TARGET_COLDFIRE)
6347 return "tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1";
6349 return "cmp%.w #0,%0\;jne %l1\;cmp%.w #0,%3\;jne %l1";
6352 (define_insn "bge0_di"
6354 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6356 (label_ref (match_operand 1 "" ""))
6360 if ((cc_prev_status.value1
6361 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6362 || (cc_prev_status.value2
6363 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6365 cc_status = cc_prev_status;
6366 return cc_status.flags & CC_REVERSED ? "jle %l1" : "jpl %l1";
6369 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
6370 output_asm_insn("tst%.l %0", operands);
6373 /* On an address reg, cmpw may replace cmpl. */
6374 output_asm_insn("cmp%.w #0,%0", operands);
6379 (define_insn "blt0_di"
6381 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6383 (label_ref (match_operand 1 "" ""))
6387 if ((cc_prev_status.value1
6388 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6389 || (cc_prev_status.value2
6390 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6392 cc_status = cc_prev_status;
6393 return cc_status.flags & CC_REVERSED ? "jgt %l1" : "jmi %l1";
6396 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
6397 output_asm_insn("tst%.l %0", operands);
6400 /* On an address reg, cmpw may replace cmpl. */
6401 output_asm_insn("cmp%.w #0,%0", operands);
6408 (if_then_else (eq (cc0)
6410 (label_ref (match_operand 0 "" ""))
6414 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
6416 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))
6417 (set_attr "split" "done")])
6421 (if_then_else (ne (cc0)
6423 (label_ref (match_operand 0 "" ""))
6427 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
6429 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))
6430 (set_attr "split" "done")])
6434 (if_then_else (gt (cc0)
6436 (label_ref (match_operand 0 "" ""))
6440 OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0);
6442 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))
6443 (set_attr "split" "done")])
6447 (if_then_else (gtu (cc0)
6449 (label_ref (match_operand 0 "" ""))
6453 [(set_attr "type" "bcc")])
6457 (if_then_else (lt (cc0)
6459 (label_ref (match_operand 0 "" ""))
6463 OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0");
6465 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))
6466 (set_attr "split" "done")])
6470 (if_then_else (ltu (cc0)
6472 (label_ref (match_operand 0 "" ""))
6476 [(set_attr "type" "bcc")])
6480 (if_then_else (ge (cc0)
6482 (label_ref (match_operand 0 "" ""))
6486 OUTPUT_JUMP ("jge %l0", "fjge %l0", "jpl %l0");
6491 (if_then_else (geu (cc0)
6493 (label_ref (match_operand 0 "" ""))
6497 [(set_attr "type" "bcc")])
6501 (if_then_else (le (cc0)
6503 (label_ref (match_operand 0 "" ""))
6507 OUTPUT_JUMP ("jle %l0", "fjle %l0", 0);
6509 [(set_attr "type" "bcc")])
6513 (if_then_else (leu (cc0)
6515 (label_ref (match_operand 0 "" ""))
6519 [(set_attr "type" "bcc")])
6521 (define_insn "bordered"
6523 (if_then_else (ordered (cc0) (const_int 0))
6524 (label_ref (match_operand 0 "" ""))
6528 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6532 (define_insn "bunordered"
6534 (if_then_else (unordered (cc0) (const_int 0))
6535 (label_ref (match_operand 0 "" ""))
6539 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6543 (define_insn "buneq"
6545 (if_then_else (uneq (cc0) (const_int 0))
6546 (label_ref (match_operand 0 "" ""))
6550 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6554 (define_insn "bunge"
6556 (if_then_else (unge (cc0) (const_int 0))
6557 (label_ref (match_operand 0 "" ""))
6561 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6565 (define_insn "bungt"
6567 (if_then_else (ungt (cc0) (const_int 0))
6568 (label_ref (match_operand 0 "" ""))
6572 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6576 (define_insn "bunle"
6578 (if_then_else (unle (cc0) (const_int 0))
6579 (label_ref (match_operand 0 "" ""))
6583 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6587 (define_insn "bunlt"
6589 (if_then_else (unlt (cc0) (const_int 0))
6590 (label_ref (match_operand 0 "" ""))
6594 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6598 (define_insn "bltgt"
6600 (if_then_else (ltgt (cc0) (const_int 0))
6601 (label_ref (match_operand 0 "" ""))
6605 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6609 ;; Negated conditional jump instructions.
6611 (define_insn "*beq_rev"
6613 (if_then_else (eq (cc0)
6616 (label_ref (match_operand 0 "" ""))))]
6619 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
6621 [(set_attr "type" "bcc")])
6623 (define_insn "*bne_rev"
6625 (if_then_else (ne (cc0)
6628 (label_ref (match_operand 0 "" ""))))]
6631 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
6633 [(set_attr "type" "bcc")])
6635 (define_insn "*bgt_rev"
6637 (if_then_else (gt (cc0)
6640 (label_ref (match_operand 0 "" ""))))]
6643 OUTPUT_JUMP ("jle %l0", "fjngt %l0", 0);
6645 [(set_attr "type" "bcc")])
6647 (define_insn "*bgtu_rev"
6649 (if_then_else (gtu (cc0)
6652 (label_ref (match_operand 0 "" ""))))]
6655 [(set_attr "type" "bcc")])
6657 (define_insn "*blt_rev"
6659 (if_then_else (lt (cc0)
6662 (label_ref (match_operand 0 "" ""))))]
6665 OUTPUT_JUMP ("jge %l0", "fjnlt %l0", "jpl %l0");
6667 [(set_attr "type" "bcc")])
6669 (define_insn "*bltu_rev"
6671 (if_then_else (ltu (cc0)
6674 (label_ref (match_operand 0 "" ""))))]
6677 [(set_attr "type" "bcc")])
6679 (define_insn "*bge_rev"
6681 (if_then_else (ge (cc0)
6684 (label_ref (match_operand 0 "" ""))))]
6687 OUTPUT_JUMP ("jlt %l0", "fjnge %l0", "jmi %l0");
6689 [(set_attr "type" "bcc")])
6691 (define_insn "*bgeu_rev"
6693 (if_then_else (geu (cc0)
6696 (label_ref (match_operand 0 "" ""))))]
6699 [(set_attr "type" "bcc")])
6701 (define_insn "*ble_rev"
6703 (if_then_else (le (cc0)
6706 (label_ref (match_operand 0 "" ""))))]
6709 OUTPUT_JUMP ("jgt %l0", "fjnle %l0", 0);
6711 [(set_attr "type" "bcc")])
6713 (define_insn "*bleu_rev"
6715 (if_then_else (leu (cc0)
6718 (label_ref (match_operand 0 "" ""))))]
6721 [(set_attr "type" "bcc")])
6723 (define_insn "*bordered_rev"
6725 (if_then_else (ordered (cc0) (const_int 0))
6727 (label_ref (match_operand 0 "" ""))))]
6730 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6734 (define_insn "*bunordered_rev"
6736 (if_then_else (unordered (cc0) (const_int 0))
6738 (label_ref (match_operand 0 "" ""))))]
6741 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6745 (define_insn "*buneq_rev"
6747 (if_then_else (uneq (cc0) (const_int 0))
6749 (label_ref (match_operand 0 "" ""))))]
6752 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6756 (define_insn "*bunge_rev"
6758 (if_then_else (unge (cc0) (const_int 0))
6760 (label_ref (match_operand 0 "" ""))))]
6763 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6767 (define_insn "*bungt_rev"
6769 (if_then_else (ungt (cc0) (const_int 0))
6771 (label_ref (match_operand 0 "" ""))))]
6774 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6778 (define_insn "*bunle_rev"
6780 (if_then_else (unle (cc0) (const_int 0))
6782 (label_ref (match_operand 0 "" ""))))]
6785 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6789 (define_insn "*bunlt_rev"
6791 (if_then_else (unlt (cc0) (const_int 0))
6793 (label_ref (match_operand 0 "" ""))))]
6796 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6800 (define_insn "*bltgt_rev"
6802 (if_then_else (ltgt (cc0) (const_int 0))
6804 (label_ref (match_operand 0 "" ""))))]
6807 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6811 ;; Unconditional and other jump instructions
6814 (label_ref (match_operand 0 "" "")))]
6817 [(set_attr "type" "bra")])
6819 (define_expand "tablejump"
6820 [(parallel [(set (pc) (match_operand 0 "" ""))
6821 (use (label_ref (match_operand 1 "" "")))])]
6824 #ifdef CASE_VECTOR_PC_RELATIVE
6825 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6826 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6830 ;; Jump to variable address from dispatch table of absolute addresses.
6831 (define_insn "*tablejump_internal"
6832 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6833 (use (label_ref (match_operand 1 "" "")))]
6836 return MOTOROLA ? "jmp (%0)" : "jmp %0@";
6838 [(set_attr "type" "bra")])
6840 ;; Jump to variable address from dispatch table of relative addresses.
6844 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6845 (use (label_ref (match_operand 1 "" "")))]
6848 #ifdef ASM_RETURN_CASE_JUMP
6849 ASM_RETURN_CASE_JUMP;
6851 if (TARGET_COLDFIRE)
6853 if (ADDRESS_REG_P (operands[0]))
6854 return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)";
6856 return "ext%.l %0\;jmp (2,pc,%0.l)";
6858 return "extl %0\;jmp pc@(2,%0:l)";
6861 return MOTOROLA ? "jmp (2,pc,%0.w)" : "jmp pc@(2,%0:w)";
6865 ;; Decrement-and-branch insns.
6866 (define_insn "*dbne_hi"
6869 (ne (match_operand:HI 0 "nonimmediate_operand" "+d*g")
6871 (label_ref (match_operand 1 "" ""))
6874 (plus:HI (match_dup 0)
6879 if (DATA_REG_P (operands[0]))
6880 return "dbra %0,%l1";
6881 if (GET_CODE (operands[0]) == MEM)
6882 return "subq%.w #1,%0\;jcc %l1";
6883 return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1";
6886 (define_insn "*dbne_si"
6889 (ne (match_operand:SI 0 "nonimmediate_operand" "+d*g")
6891 (label_ref (match_operand 1 "" ""))
6894 (plus:SI (match_dup 0)
6899 if (DATA_REG_P (operands[0]))
6900 return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
6901 if (GET_CODE (operands[0]) == MEM)
6902 return "subq%.l #1,%0\;jcc %l1";
6903 return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1";
6906 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6908 (define_insn "*dbge_hi"
6911 (ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am")
6914 (label_ref (match_operand 1 "" ""))
6917 (plus:HI (match_dup 0)
6919 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6922 if (DATA_REG_P (operands[0]))
6923 return "dbra %0,%l1";
6924 if (GET_CODE (operands[0]) == MEM)
6925 return "subq%.w #1,%0\;jcc %l1";
6926 return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1";
6929 (define_expand "decrement_and_branch_until_zero"
6930 [(parallel [(set (pc)
6932 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "")
6935 (label_ref (match_operand 1 "" ""))
6938 (plus:SI (match_dup 0)
6943 (define_insn "*dbge_si"
6946 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am")
6949 (label_ref (match_operand 1 "" ""))
6952 (plus:SI (match_dup 0)
6954 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6957 if (DATA_REG_P (operands[0]))
6958 return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
6959 if (GET_CODE (operands[0]) == MEM)
6960 return "subq%.l #1,%0\;jcc %l1";
6961 return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1";
6964 (define_expand "sibcall"
6965 [(call (match_operand:QI 0 "memory_operand" "")
6966 (match_operand:SI 1 "general_operand" ""))]
6969 operands[0] = m68k_legitimize_sibcall_address (operands[0]);
6972 (define_insn "*sibcall"
6973 [(call (mem:QI (match_operand:SI 0 "sibcall_operand" ""))
6974 (match_operand:SI 1 "general_operand" ""))]
6975 "SIBLING_CALL_P (insn)"
6977 return output_sibcall (operands[0]);
6980 (define_expand "sibcall_value"
6981 [(set (match_operand 0 "" "")
6982 (call (match_operand:QI 1 "memory_operand" "")
6983 (match_operand:SI 2 "general_operand" "")))]
6986 operands[1] = m68k_legitimize_sibcall_address (operands[1]);
6989 (define_insn "*sibcall_value"
6990 [(set (match_operand 0 "" "=rf,rf")
6991 (call (mem:QI (match_operand:SI 1 "sibcall_operand" ""))
6992 (match_operand:SI 2 "general_operand" "")))]
6993 "SIBLING_CALL_P (insn)"
6995 operands[0] = operands[1];
6996 return output_sibcall (operands[0]);
6999 ;; Call subroutine with no return value.
7000 (define_expand "call"
7001 [(call (match_operand:QI 0 "memory_operand" "")
7002 (match_operand:SI 1 "general_operand" ""))]
7003 ;; Operand 1 not really used on the m68000.
7006 operands[0] = m68k_legitimize_call_address (operands[0]);
7009 (define_insn "*call"
7010 [(call (mem:QI (match_operand:SI 0 "call_operand" "a,W"))
7011 (match_operand:SI 1 "general_operand" "g,g"))]
7012 ;; Operand 1 not really used on the m68000.
7013 "!SIBLING_CALL_P (insn)"
7015 return output_call (operands[0]);
7018 ;; Call subroutine, returning value in operand 0
7019 ;; (which must be a hard register).
7020 (define_expand "call_value"
7021 [(set (match_operand 0 "" "")
7022 (call (match_operand:QI 1 "memory_operand" "")
7023 (match_operand:SI 2 "general_operand" "")))]
7024 ;; Operand 2 not really used on the m68000.
7027 operands[1] = m68k_legitimize_call_address (operands[1]);
7030 (define_insn "*non_symbolic_call_value"
7031 [(set (match_operand 0 "" "=rf,rf")
7032 (call (mem:QI (match_operand:SI 1 "non_symbolic_call_operand" "a,W"))
7033 (match_operand:SI 2 "general_operand" "g,g")))]
7034 ;; Operand 2 not really used on the m68000.
7035 "!SIBLING_CALL_P (insn)"
7037 [(set_attr "type" "jsr")
7038 (set_attr "split" "done")
7039 (set_attr "opx" "1")])
7041 (define_insn "*symbolic_call_value_jsr"
7042 [(set (match_operand 0 "" "=rf,rf")
7043 (call (mem:QI (match_operand:SI 1 "symbolic_operand" "a,W"))
7044 (match_operand:SI 2 "general_operand" "g,g")))]
7045 ;; Operand 2 not really used on the m68000.
7046 "!SIBLING_CALL_P (insn) && m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_JSR"
7048 operands[0] = operands[1];
7049 return m68k_symbolic_call;
7051 [(set_attr "type" "jsr")
7052 (set_attr "split" "done")
7053 (set_attr "opx" "1")])
7055 (define_insn "*symbolic_call_value_bsr"
7056 [(set (match_operand 0 "" "=rf,rf")
7057 (call (mem:QI (match_operand:SI 1 "symbolic_operand" "a,W"))
7058 (match_operand:SI 2 "general_operand" "g,g")))]
7059 ;; Operand 2 not really used on the m68000.
7060 "!SIBLING_CALL_P (insn)
7061 && (m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_BSR_C
7062 || m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_BSR_P)"
7064 operands[0] = operands[1];
7065 return m68k_symbolic_call;
7067 [(set_attr "type" "bsr")
7068 (set_attr "split" "done")
7069 (set_attr "opx" "1")])
7071 ;; Call subroutine returning any type.
7073 (define_expand "untyped_call"
7074 [(parallel [(call (match_operand 0 "" "")
7076 (match_operand 1 "" "")
7077 (match_operand 2 "" "")])]
7078 "NEEDS_UNTYPED_CALL"
7082 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7084 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7086 rtx set = XVECEXP (operands[2], 0, i);
7087 emit_move_insn (SET_DEST (set), SET_SRC (set));
7090 /* The optimizer does not know that the call sets the function value
7091 registers we stored in the result block. We avoid problems by
7092 claiming that all hard registers are used and clobbered at this
7094 emit_insn (gen_blockage ());
7099 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7100 ;; all of memory. This blocks insns from being moved across this point.
7102 (define_insn "blockage"
7103 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7111 [(set_attr "type" "nop")])
7113 (define_expand "prologue"
7117 m68k_expand_prologue ();
7121 (define_expand "epilogue"
7125 m68k_expand_epilogue (false);
7129 (define_expand "sibcall_epilogue"
7133 m68k_expand_epilogue (true);
7137 ;; Used for frameless functions which save no regs and allocate no locals.
7138 (define_expand "return"
7140 "m68k_use_return_insn ()"
7143 (define_insn "*return"
7147 switch (m68k_get_function_kind (current_function_decl))
7149 case m68k_fk_interrupt_handler:
7152 case m68k_fk_interrupt_thread:
7156 if (current_function_pops_args)
7158 operands[0] = GEN_INT (current_function_pops_args);
7165 [(set_attr "type" "rts")])
7167 (define_insn "*m68k_store_multiple"
7168 [(match_parallel 0 "" [(match_operand 1 "")])]
7169 "m68k_movem_pattern_p (operands[0], NULL, 0, true)"
7171 return m68k_output_movem (operands, operands[0], 0, true);
7174 (define_insn "*m68k_store_multiple_automod"
7175 [(match_parallel 0 ""
7176 [(set (match_operand:SI 1 "register_operand" "=a")
7177 (plus:SI (match_operand:SI 2 "register_operand" "1")
7178 (match_operand:SI 3 "const_int_operand")))])]
7179 "m68k_movem_pattern_p (operands[0], operands[1], INTVAL (operands[3]), true)"
7181 return m68k_output_movem (operands, operands[0], INTVAL (operands[3]), true);
7184 (define_insn "*m68k_load_multiple"
7185 [(match_parallel 0 "" [(match_operand 1 "")])]
7186 "m68k_movem_pattern_p (operands[0], NULL, 0, false)"
7188 return m68k_output_movem (operands, operands[0], 0, false);
7191 (define_insn "*m68k_load_multiple_automod"
7192 [(match_parallel 0 ""
7193 [(set (match_operand:SI 1 "register_operand" "=a")
7194 (plus:SI (match_operand:SI 2 "register_operand" "1")
7195 (match_operand:SI 3 "const_int_operand")))])]
7196 "m68k_movem_pattern_p (operands[0], operands[1],
7197 INTVAL (operands[3]), false)"
7199 return m68k_output_movem (operands, operands[0],
7200 INTVAL (operands[3]), false);
7203 (define_expand "link"
7205 [(set (match_operand:SI 0 "register_operand")
7206 (plus:SI (reg:SI SP_REG) (const_int -4)))
7209 (set (reg:SI SP_REG)
7210 (plus:SI (reg:SI SP_REG)
7211 (match_operand:SI 1 "const_int_operand")))])]
7212 "TARGET_68020 || INTVAL (operands[1]) >= -0x8004"
7214 operands[2] = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, -4));
7217 (define_insn "*link"
7218 [(set (match_operand:SI 0 "register_operand" "+r")
7219 (plus:SI (reg:SI SP_REG) (const_int -4)))
7220 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
7222 (set (reg:SI SP_REG)
7223 (plus:SI (reg:SI SP_REG)
7224 (match_operand:SI 1 "const_int_operand")))]
7225 "TARGET_68020 || INTVAL (operands[1]) >= -0x8004"
7227 operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
7229 return "link %0,%1";
7230 else if (INTVAL (operands[1]) >= -0x8000)
7231 return "link.w %0,%1";
7233 return "link.l %0,%1";
7236 (define_expand "unlink"
7238 [(set (match_operand:SI 0 "register_operand")
7240 (set (reg:SI SP_REG)
7241 (plus:SI (match_dup 0)
7245 operands[1] = gen_frame_mem (SImode, copy_rtx (operands[0]));
7248 (define_insn "*unlink"
7249 [(set (match_operand:SI 0 "register_operand" "+r")
7250 (mem:SI (match_dup 0)))
7251 (set (reg:SI SP_REG)
7252 (plus:SI (match_dup 0)
7256 [(set_attr "type" "unlk")])
7258 (define_insn "load_got"
7259 [(set (match_operand:SI 0 "register_operand" "=a")
7260 (unspec:SI [(const_int 0)] UNSPEC_GOT))]
7263 if (TARGET_ID_SHARED_LIBRARY)
7265 operands[1] = gen_rtx_REG (Pmode, PIC_REG);
7266 return MOTOROLA ? "move.l %?(%1),%0" : "movel %1@(%?), %0";
7270 if (TARGET_COLDFIRE)
7271 /* Load the full 32-bit PC-relative offset of
7272 _GLOBAL_OFFSET_TABLE_ into the PIC register, then use it to
7273 calculate the absolute value. The offset and "lea"
7274 operation word together occupy 6 bytes. */
7275 return ("move.l #_GLOBAL_OFFSET_TABLE_@GOTPC, %0\n\t"
7276 "lea (-6, %%pc, %0), %0");
7278 return "lea (%%pc, _GLOBAL_OFFSET_TABLE_@GOTPC), %0";
7281 return ("movel #_GLOBAL_OFFSET_TABLE_, %0\n\t"
7282 "lea %%pc@(0,%0:l),%0");
7285 (define_insn "indirect_jump"
7286 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
7289 [(set_attr "type" "jmp")])
7291 ;; This should not be used unless the add/sub insns can't be.
7294 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
7295 (match_operand:QI 1 "address_operand" "p"))]
7299 ;; This is the first machine-dependent peephole optimization.
7300 ;; It is useful when a floating value is returned from a function call
7301 ;; and then is moved into an FP register.
7302 ;; But it is mainly intended to test the support for these optimizations.
7305 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
7306 (set (match_operand:DF 0 "register_operand" "")
7307 (match_operand:DF 1 "register_operand" ""))]
7308 "FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
7309 [(set (mem:SI (reg:SI SP_REG)) (match_dup 1))
7310 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 2))
7311 (set (match_dup 0) (mem:DF (post_inc:SI (reg:SI SP_REG))))]
7312 "split_di(operands + 1, 1, operands + 1, operands + 2);")
7314 ;; Optimize a stack-adjust followed by a push of an argument.
7315 ;; This is said to happen frequently with -msoft-float
7316 ;; when there are consecutive library calls.
7319 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
7320 (set (match_operand:SF 0 "push_operand" "")
7321 (match_operand:SF 1 "general_operand" ""))]
7322 "!reg_mentioned_p (stack_pointer_rtx, operands[0])"
7323 [(set (match_dup 0) (match_dup 1))]
7324 "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);")
7327 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
7328 (match_operand:SI 0 "const_int_operand" "")))
7329 (set (match_operand:SF 1 "push_operand" "")
7330 (match_operand:SF 2 "general_operand" ""))]
7331 "INTVAL (operands[0]) > 4
7332 && !reg_mentioned_p (stack_pointer_rtx, operands[2])"
7333 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 0)))
7334 (set (match_dup 1) (match_dup 2))]
7336 operands[0] = GEN_INT (INTVAL (operands[0]) - 4);
7337 operands[1] = replace_equiv_address (operands[1], stack_pointer_rtx);
7340 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7341 ;; Constant operands need special care, as replacing a "pea X.w" with
7342 ;; "move.l #X,(%sp)" is often not a win.
7344 ;; Already done by the previous csa pass, left as reference.
7346 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
7347 (set (match_operand:SI 0 "push_operand" "")
7348 (match_operand:SI 1 "general_operand" ""))]
7349 "!reg_mentioned_p (stack_pointer_rtx, operands[1])"
7350 [(set (match_dup 0) (match_dup 1))]
7351 "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);")
7353 ;; Try to use moveq, after stack push has been changed into a simple move.
7355 [(match_scratch:SI 2 "d")
7356 (set (match_operand:SI 0 "memory_operand" "")
7357 (match_operand:SI 1 "const_int_operand" ""))]
7358 "GET_CODE (XEXP (operands[0], 0)) != PRE_DEC
7359 && INTVAL (operands[1]) != 0
7360 && IN_RANGE (INTVAL (operands[1]), -0x80, 0x7f)
7361 && !valid_mov3q_const (INTVAL (operands[1]))"
7362 [(set (match_dup 2) (match_dup 1))
7363 (set (match_dup 0) (match_dup 2))])
7365 ;; This sequence adds an instruction, but is two bytes shorter.
7367 [(match_scratch:SI 2 "d")
7368 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 12)))
7369 (set (match_operand:SI 0 "push_operand" "")
7370 (match_operand:SI 1 "const_int_operand" ""))]
7371 "INTVAL (operands[1]) != 0
7372 && IN_RANGE (INTVAL (operands[1]), -0x80, 0x7f)
7373 && !valid_mov3q_const (INTVAL (operands[1]))"
7374 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
7375 (set (match_dup 2) (match_dup 1))
7376 (set (match_dup 0) (match_dup 2))]
7377 "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);")
7379 ;; Changing pea X.w into a move.l is no real win here.
7381 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
7382 (match_operand:SI 0 "const_int_operand" "")))
7383 (set (match_operand:SI 1 "push_operand" "")
7384 (match_operand:SI 2 "general_operand" ""))]
7385 "INTVAL (operands[0]) > 4
7386 && !reg_mentioned_p (stack_pointer_rtx, operands[2])
7387 && !(CONST_INT_P (operands[2]) && INTVAL (operands[2]) != 0
7388 && IN_RANGE (INTVAL (operands[2]), -0x8000, 0x7fff)
7389 && !valid_mov3q_const (INTVAL (operands[2])))"
7390 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 0)))
7391 (set (match_dup 1) (match_dup 2))]
7393 operands[0] = GEN_INT (INTVAL (operands[0]) - 4);
7394 operands[1] = replace_equiv_address (operands[1], stack_pointer_rtx);
7397 ;; Speed up pushing a single byte/two bytes but leaving four bytes of space
7398 ;; (which differs slightly between m680x0 and ColdFire).
7401 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
7402 (set (match_operand:QI 0 "memory_operand" "")
7403 (match_operand:QI 1 "register_operand" ""))]
7404 "!reg_mentioned_p (stack_pointer_rtx, operands[1])
7405 && GET_CODE (XEXP (operands[0], 0)) == PLUS
7406 && rtx_equal_p (XEXP (XEXP (operands[0], 0), 0), stack_pointer_rtx)
7407 && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1))
7408 && INTVAL (XEXP (XEXP (operands[0], 0), 1)) == 3"
7409 [(set (match_dup 0) (match_dup 1))]
7411 rtx addr = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx);
7412 operands[0] = adjust_automodify_address (operands[0], SImode, addr, -3);
7413 operands[1] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
7417 [(set (match_operand:QI 0 "push_operand" "")
7418 (match_operand:QI 1 "register_operand" ""))
7419 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -3)))]
7420 "!reg_mentioned_p (stack_pointer_rtx, operands[1])"
7421 [(set (match_dup 0) (match_dup 1))]
7423 operands[0] = adjust_automodify_address (operands[0], SImode,
7424 XEXP (operands[0], 0), -3);
7425 operands[1] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
7429 [(set (match_operand:HI 0 "push_operand" "")
7430 (match_operand:HI 1 "register_operand" ""))
7431 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))]
7432 "!reg_mentioned_p (stack_pointer_rtx, operands[1])"
7433 [(set (match_dup 0) (match_dup 1))]
7435 operands[0] = adjust_automodify_address (operands[0], SImode,
7436 XEXP (operands[0], 0), -2);
7437 operands[1] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
7440 ;; Optimize a series of strict_low_part assignments
7443 [(set (match_operand:SI 0 "register_operand" "")
7445 (set (strict_low_part (match_operand:HI 1 "register_operand" ""))
7446 (match_operand:HI 2 "general_operand" ""))]
7447 "REGNO (operands[0]) == REGNO (operands[1])
7448 && strict_low_part_peephole_ok (HImode, insn, operands[0])"
7449 [(set (strict_low_part (match_dup 1)) (match_dup 2))]
7453 [(set (match_operand:SI 0 "register_operand" "")
7455 (set (strict_low_part (match_operand:QI 1 "register_operand" ""))
7456 (match_operand:QI 2 "general_operand" ""))]
7457 "REGNO (operands[0]) == REGNO (operands[1])
7458 && strict_low_part_peephole_ok (QImode, insn, operands[0])"
7459 [(set (strict_low_part (match_dup 1)) (match_dup 2))]
7467 ;; jCC label ; abnormal loop termination
7468 ;; dbra dN, loop ; normal loop termination
7476 ;; Which moves the jCC condition outside the inner loop for free.
7480 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7481 [(cc0) (const_int 0)])
7482 (label_ref (match_operand 2 "" ""))
7487 (ne (match_operand:HI 0 "register_operand" "")
7489 (label_ref (match_operand 1 "" ""))
7492 (plus:HI (match_dup 0)
7494 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7497 output_dbcc_and_branch (operands);
7502 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7503 [(cc0) (const_int 0)])
7504 (label_ref (match_operand 2 "" ""))
7509 (ne (match_operand:SI 0 "register_operand" "")
7511 (label_ref (match_operand 1 "" ""))
7514 (plus:SI (match_dup 0)
7516 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7519 output_dbcc_and_branch (operands);
7524 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7525 [(cc0) (const_int 0)])
7526 (label_ref (match_operand 2 "" ""))
7531 (ge (plus:HI (match_operand:HI 0 "register_operand" "")
7534 (label_ref (match_operand 1 "" ""))
7537 (plus:HI (match_dup 0)
7539 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7542 output_dbcc_and_branch (operands);
7547 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7548 [(cc0) (const_int 0)])
7549 (label_ref (match_operand 2 "" ""))
7554 (ge (plus:SI (match_operand:SI 0 "register_operand" "")
7557 (label_ref (match_operand 1 "" ""))
7560 (plus:SI (match_dup 0)
7562 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7565 output_dbcc_and_branch (operands);
7570 (define_insn "extendsfxf2"
7571 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7572 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7575 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7577 if (REGNO (operands[0]) == REGNO (operands[1]))
7579 /* Extending float to double in an fp-reg is a no-op.
7580 NOTICE_UPDATE_CC has already assumed that the
7581 cc will be set. So cancel what it did. */
7582 cc_status = cc_prev_status;
7585 return "f%$move%.x %1,%0";
7587 if (FP_REG_P (operands[0]))
7589 if (FP_REG_P (operands[1]))
7590 return "f%$move%.x %1,%0";
7591 else if (ADDRESS_REG_P (operands[1]))
7592 return "move%.l %1,%-\;f%$move%.s %+,%0";
7593 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7594 return output_move_const_single (operands);
7595 return "f%$move%.s %f1,%0";
7597 return "fmove%.x %f1,%0";
7601 (define_insn "extenddfxf2"
7602 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7604 (match_operand:DF 1 "general_operand" "f,rmE")))]
7607 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7609 if (REGNO (operands[0]) == REGNO (operands[1]))
7611 /* Extending float to double in an fp-reg is a no-op.
7612 NOTICE_UPDATE_CC has already assumed that the
7613 cc will be set. So cancel what it did. */
7614 cc_status = cc_prev_status;
7617 return "fmove%.x %1,%0";
7619 if (FP_REG_P (operands[0]))
7621 if (REG_P (operands[1]))
7624 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7625 output_asm_insn ("move%.l %1,%-", xoperands);
7626 output_asm_insn ("move%.l %1,%-", operands);
7627 return "f%&move%.d %+,%0";
7629 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7630 return output_move_const_double (operands);
7631 return "f%&move%.d %f1,%0";
7633 return "fmove%.x %f1,%0";
7636 (define_insn "truncxfdf2"
7637 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r")
7639 (match_operand:XF 1 "general_operand" "f,f")))]
7642 if (REG_P (operands[0]))
7644 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
7645 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7646 return "move%.l %+,%0";
7648 return "fmove%.d %f1,%0";
7651 (define_insn "truncxfsf2"
7652 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
7654 (match_operand:XF 1 "general_operand" "f")))]
7658 (define_insn "sin<mode>2"
7659 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
7661 [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_SIN))]
7662 "TARGET_68881 && flag_unsafe_math_optimizations"
7664 if (FP_REG_P (operands[1]))
7665 return "fsin%.x %1,%0";
7667 return "fsin%.<FP:prec> %1,%0";
7670 (define_insn "cos<mode>2"
7671 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
7673 [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_COS))]
7674 "TARGET_68881 && flag_unsafe_math_optimizations"
7676 if (FP_REG_P (operands[1]))
7677 return "fcos%.x %1,%0";
7679 return "fcos%.<FP:prec> %1,%0";
7682 ;; Unconditional traps are assumed to have (const_int 1) for the condition.
7684 [(trap_if (const_int 1) (const_int 7))]
7687 [(set_attr "type" "trap")])
7689 (define_expand "conditional_trap"
7690 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
7691 [(cc0) (const_int 0)])
7692 (match_operand:SI 1 "const_int_operand" "I"))]
7695 if (m68k_last_compare_had_fp_operands)
7697 m68k_last_compare_had_fp_operands = 0;
7702 (define_insn "*conditional_trap"
7703 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
7704 [(cc0) (const_int 0)])
7705 (match_operand:SI 1 "const_int_operand" "I"))]
7706 "TARGET_68020 && ! flags_in_68881 ()"
7708 switch (GET_CODE (operands[0]))
7710 case EQ: return "trapeq";
7711 case NE: return "trapne";
7712 case GT: return "trapgt";
7713 case GTU: return "traphi";
7714 case LT: return "traplt";
7715 case LTU: return "trapcs";
7716 case GE: return "trapge";
7717 case GEU: return "trapcc";
7718 case LE: return "traple";
7719 case LEU: return "trapls";
7720 default: gcc_unreachable ();
7724 ;; Instruction that subscribes one word in ColdFire instruction buffer.
7725 ;; This instruction is used within scheduler only and should not appear
7726 ;; in the instruction stream.
7728 [(unspec [(const_int 0)] UNSPEC_IB)]
7731 [(set_attr "type" "ib")])