1 ;; ColdFire V2 DFA description.
2 ;; Copyright (C) 2007 Free Software Foundation, Inc.
3 ;; Contributed by CodeSourcery Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
22 ;; ??? To let genattrtab live, implement this attribute in C.
24 "alu, alu_l, bcc, bra, call, jmp, lea, move, move_l, mul, pea, rts, unlk,
26 (symbol_ref "m68k_sched_attr_type2 (insn)"))
29 (define_automaton "cf_v2_ib")
31 ;; If one of these cpu units is occupied, that means that corresponding
32 ;; word in the buffer is empty.
33 (define_cpu_unit "cf_v2_ib_w0, cf_v2_ib_w1, cf_v2_ib_w2, cf_v2_ib_w3, cf_v2_ib_w4, cf_v2_ib_w5" "cf_v2_ib")
35 (final_presence_set "cf_v2_ib_w1, cf_v2_ib_w2, cf_v2_ib_w3, cf_v2_ib_w4, cf_v2_ib_w5" "cf_v2_ib_w0")
36 (final_presence_set "cf_v2_ib_w2, cf_v2_ib_w3, cf_v2_ib_w4, cf_v2_ib_w5" "cf_v2_ib_w1")
37 (final_presence_set "cf_v2_ib_w3, cf_v2_ib_w4, cf_v2_ib_w5" "cf_v2_ib_w2")
38 (final_presence_set "cf_v2_ib_w4, cf_v2_ib_w5" "cf_v2_ib_w3")
39 (final_presence_set "cf_v2_ib_w5" "cf_v2_ib_w4")
42 (define_reservation "cf_v2_ib1" "cf_v2_ib_w0|cf_v2_ib_w1|cf_v2_ib_w2|cf_v2_ib_w3|cf_v2_ib_w4|cf_v2_ib_w5")
45 (define_reservation "cf_v2_ib2" "(cf_v2_ib_w0+cf_v2_ib_w1)|(cf_v2_ib_w1+cf_v2_ib_w2)|(cf_v2_ib_w2+cf_v2_ib_w3)|(cf_v2_ib_w3+cf_v2_ib_w4)|(cf_v2_ib_w4+cf_v2_ib_w5)")
48 (define_reservation "cf_v2_ib3" "(cf_v2_ib_w0+cf_v2_ib_w1+cf_v2_ib_w2)|(cf_v2_ib_w1+cf_v2_ib_w2+cf_v2_ib_w3)|(cf_v2_ib_w2+cf_v2_ib_w3+cf_v2_ib_w4)|(cf_v2_ib_w3+cf_v2_ib_w4+cf_v2_ib_w5)")
50 ;; Reservation to subscribe 1 word in the instruction buffer. If a given
51 ;; word in the instruction buffer is subscribed, that means it is empty.
52 ;; This reservation is used at the start of each cycle to setup the number
53 ;; of prefetched instruction words in the instruction buffer.
54 ;; At each cycle, given that memory bus is available (i.e. there is no
55 ;; pending memory operation), IFP prefetches two instruction words into IB.
56 (define_insn_reservation "cf_v2_ib" 0
57 (and (eq_attr "cpu" "cf_v2")
58 (eq_attr "type" "ib"))
61 ;; Operand Execution Pipeline
62 (define_automaton "cf_v2_oep")
64 (define_cpu_unit "cf_v2_dsoc, cf_v2_agex" "cf_v2_oep")
66 ;; A memory unit that is reffered to as 'certain hardware resources' in
67 ;; ColdFire reference manuals. This unit remains occupied for two cycles
68 ;; after last dsoc cycle of a store - hence there is a 2 cycle delay between
69 ;; two consecutive stores.
70 (define_automaton "cf_v2_chr")
72 (define_cpu_unit "cf_v2_chr" "cf_v2_chr")
75 (define_automaton "cf_v2_mem")
77 ;; When memory bus is subscribed, that implies that instruction buffer won't
78 ;; get its portion this cycle. To model that we query if cf_v2_mem unit is
79 ;; subscribed and adjust number of prefetched instruction words accordingly.
81 (define_query_cpu_unit "cf_v2_mem" "cf_v2_mem")
83 ;; Register to register move.
85 (define_reservation "cf_v2_move_00"
86 "cf_v2_dsoc+cf_v2_agex")
88 ;; Load from a memory location.
90 (define_reservation "cf_v2_move_10"
91 "cf_v2_dsoc,cf_v2_agex,cf_v2_dsoc+cf_v2_mem,cf_v2_agex")
93 ;; Long load from a memory location.
95 (define_reservation "cf_v2_move_l_10"
96 "cf_v2_dsoc+cf_v2_agex,cf_v2_dsoc+cf_v2_mem,cf_v2_agex")
98 ;; Load from an indexed location.
100 (define_reservation "cf_v2_move_i0"
101 "cf_v2_dsoc,cf_v2_agex,cf_v2_agex,cf_v2_dsoc+cf_v2_mem,cf_v2_agex")
103 ;; Long load from an indexed location.
105 (define_reservation "cf_v2_move_l_i0"
106 "cf_v2_dsoc+cf_v2_agex,cf_v2_agex,cf_v2_dsoc+cf_v2_mem,cf_v2_agex")
108 ;; Store to a memory location.
110 (define_reservation "cf_v2_move_01"
111 "cf_v2_dsoc+cf_v2_agex+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
113 ;; Store to an indexed location.
115 (define_reservation "cf_v2_move_0i"
116 "cf_v2_dsoc+cf_v2_agex,cf_v2_agex+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
118 ;; Load from a memory location and store to a memory location.
120 (define_reservation "cf_v2_move_11"
121 "cf_v2_dsoc,cf_v2_agex,cf_v2_dsoc+cf_v2_agex+cf_v2_mem+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
123 ;; Long load from a memory location and store to a memory location.
125 (define_reservation "cf_v2_move_l_11"
126 "cf_v2_dsoc+cf_v2_agex,cf_v2_dsoc+cf_v2_agex+cf_v2_mem+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
128 ;; Load from an indexed location and store to a memory location.
130 (define_reservation "cf_v2_move_i1"
131 "cf_v2_dsoc,cf_v2_agex,cf_v2_agex,cf_v2_dsoc+cf_v2_agex+cf_v2_mem+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
133 ;; Long load from an indexed location and store to a memory location.
135 (define_reservation "cf_v2_move_l_i1"
136 "cf_v2_dsoc+cf_v2_agex,cf_v2_agex,cf_v2_dsoc+cf_v2_agex+cf_v2_mem+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
138 ;; Load from a memory location and store to an indexed location.
140 (define_reservation "cf_v2_move_1i"
141 "cf_v2_dsoc,cf_v2_agex,cf_v2_dsoc+cf_v2_agex+cf_v2_mem,cf_v2_agex,cf_v2_mem")
143 ;; Long load from a memory location and store to an indexed location.
145 (define_reservation "cf_v2_move_l_1i"
146 "cf_v2_dsoc+cf_v2_agex,cf_v2_dsoc+cf_v2_agex+cf_v2_mem,cf_v2_agex,cf_v2_mem")
148 ;; Lea operation for a memory location.
150 (define_reservation "cf_v2_lea_10"
151 "cf_v2_dsoc+cf_v2_agex")
153 ;; Lea operation for an indexed location.
155 (define_reservation "cf_v2_lea_i0"
156 "cf_v2_dsoc+cf_v2_agex,cf_v2_agex")
158 ;; Pea operation for a memory location.
160 (define_reservation "cf_v2_pea_11"
161 "cf_v2_dsoc+cf_v2_agex,cf_v2_agex+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
163 ;; Pea operation for an indexed location.
165 (define_reservation "cf_v2_pea_i1"
166 "cf_v2_dsoc+cf_v2_agex,cf_v2_agex,cf_v2_agex+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
168 (define_automaton "cf_v2_emac")
170 (define_cpu_unit "cf_v2_emac1,cf_v2_emac2,cf_v2_emac3,cf_v2_emac4"
173 ;; Mul operation with register operands.
175 (define_reservation "cf_v2_mul_00"
176 "cf_v2_dsoc,cf_v2_agex+cf_v2_emac1,cf_v2_emac2,cf_v2_emac3,cf_v2_emac4")
178 ;; Mul operation with implicit load from a memory location.
180 (define_reservation "cf_v2_mul_10"
181 "cf_v2_dsoc,cf_v2_agex,cf_v2_dsoc+cf_v2_mem,cf_v2_agex+cf_v2_emac1,cf_v2_emac2,cf_v2_emac3,cf_v2_emac4")
183 ;; Mul operation with implicit load from an indexed location.
185 (define_reservation "cf_v2_mul_i0"
186 "cf_v2_dsoc,cf_v2_agex,cf_v2_agex,cf_v2_dsoc+cf_v2_mem,cf_v2_agex+cf_v2_emac1,cf_v2_emac2,cf_v2_emac3,cf_v2_emac4")
188 ;; Instruction reservations.
190 ;; Below reservations are simple derivation from the above reservations.
191 ;; Each reservation from the above expands into 3 reservations below - one
192 ;; for each instruction size.
193 ;; A number in the end of reservation's name is the size of the instruction.
195 (define_insn_reservation "cf_v2_move_00_1" 1
196 (and (and (and (eq_attr "cpu" "cf_v2")
197 (eq_attr "type2" "alu,alu_l,move,move_l"))
198 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
199 (eq_attr "op_mem" "00"))
200 "cf_v2_ib1+cf_v2_move_00")
202 (define_insn_reservation "cf_v2_move_00_2" 1
203 (and (and (and (eq_attr "cpu" "cf_v2")
204 (eq_attr "type2" "alu,alu_l,move,move_l"))
205 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
206 (eq_attr "op_mem" "00"))
207 "cf_v2_ib2+cf_v2_move_00")
209 (define_insn_reservation "cf_v2_move_00_3" 1
210 (and (and (and (eq_attr "cpu" "cf_v2")
211 (eq_attr "type2" "alu,alu_l,move,move_l"))
212 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
213 (eq_attr "op_mem" "00"))
214 "cf_v2_ib3+cf_v2_move_00")
216 (define_insn_reservation "cf_v2_move_10_1" 4
217 (and (and (and (eq_attr "cpu" "cf_v2")
218 (eq_attr "type2" "alu_l,move"))
219 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
220 (eq_attr "op_mem" "10"))
221 "cf_v2_ib1+cf_v2_move_10")
223 (define_insn_reservation "cf_v2_move_10_2" 4
224 (and (and (and (eq_attr "cpu" "cf_v2")
225 (eq_attr "type2" "alu_l,move"))
226 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
227 (eq_attr "op_mem" "10"))
228 "cf_v2_ib2+cf_v2_move_10")
230 (define_insn_reservation "cf_v2_move_10_3" 4
231 (and (and (and (eq_attr "cpu" "cf_v2")
232 (eq_attr "type2" "alu_l,move"))
233 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
234 (eq_attr "op_mem" "10"))
235 "cf_v2_ib3+cf_v2_move_10")
237 (define_insn_reservation "cf_v2_move_l_10_1" 3
238 (and (and (and (eq_attr "cpu" "cf_v2")
239 (eq_attr "type2" "move_l"))
240 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
241 (eq_attr "op_mem" "10"))
242 "cf_v2_ib1+cf_v2_move_l_10")
244 (define_insn_reservation "cf_v2_move_l_10_2" 3
245 (and (and (and (eq_attr "cpu" "cf_v2")
246 (eq_attr "type2" "move_l"))
247 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
248 (eq_attr "op_mem" "10"))
249 "cf_v2_ib2+cf_v2_move_l_10")
251 (define_insn_reservation "cf_v2_move_l_10_3" 3
252 (and (and (and (eq_attr "cpu" "cf_v2")
253 (eq_attr "type2" "move_l"))
254 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
255 (eq_attr "op_mem" "10"))
256 "cf_v2_ib3+cf_v2_move_l_10")
258 (define_insn_reservation "cf_v2_move_i0_2" 5
259 (and (and (and (eq_attr "cpu" "cf_v2")
260 (eq_attr "type2" "alu_l,move"))
261 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
262 (eq_attr "op_mem" "i0"))
263 "cf_v2_ib2+cf_v2_move_i0")
265 (define_insn_reservation "cf_v2_move_i0_3" 5
266 (and (and (and (eq_attr "cpu" "cf_v2")
267 (eq_attr "type2" "alu_l,move"))
268 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
269 (eq_attr "op_mem" "i0"))
270 "cf_v2_ib3+cf_v2_move_i0")
272 (define_insn_reservation "cf_v2_move_l_i0_2" 4
273 (and (and (and (eq_attr "cpu" "cf_v2")
274 (eq_attr "type2" "move_l"))
275 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
276 (eq_attr "op_mem" "i0"))
277 "cf_v2_ib2+cf_v2_move_l_i0")
279 (define_insn_reservation "cf_v2_move_l_i0_3" 4
280 (and (and (and (eq_attr "cpu" "cf_v2")
281 (eq_attr "type2" "move_l"))
282 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
283 (eq_attr "op_mem" "i0"))
284 "cf_v2_ib3+cf_v2_move_l_i0")
286 (define_insn_reservation "cf_v2_move_01_1" 0
287 (and (and (and (eq_attr "cpu" "cf_v2")
288 (eq_attr "type2" "alu_l,move,move_l"))
289 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
290 (eq_attr "op_mem" "01"))
291 "cf_v2_ib1+cf_v2_move_01")
293 (define_insn_reservation "cf_v2_move_01_2" 0
294 (and (and (and (eq_attr "cpu" "cf_v2")
295 (eq_attr "type2" "alu_l,move,move_l"))
296 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
297 (eq_attr "op_mem" "01"))
298 "cf_v2_ib2+cf_v2_move_01")
300 (define_insn_reservation "cf_v2_move_01_3" 0
301 (and (and (and (eq_attr "cpu" "cf_v2")
302 (eq_attr "type2" "alu_l,move,move_l"))
303 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
304 (eq_attr "op_mem" "01"))
305 "cf_v2_ib3+cf_v2_move_01")
307 (define_insn_reservation "cf_v2_move_0i_2" 0
308 (and (and (and (eq_attr "cpu" "cf_v2")
309 (eq_attr "type2" "alu_l,move,move_l"))
310 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
311 (eq_attr "op_mem" "0i"))
312 "cf_v2_ib2+cf_v2_move_0i")
314 (define_insn_reservation "cf_v2_move_0i_3" 0
315 (and (and (and (eq_attr "cpu" "cf_v2")
316 (eq_attr "type2" "alu_l,move,move_l"))
317 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
318 (eq_attr "op_mem" "0i"))
319 "cf_v2_ib3+cf_v2_move_0i")
321 (define_insn_reservation "cf_v2_move_11_1" 0
322 (and (and (and (eq_attr "cpu" "cf_v2")
323 (eq_attr "type2" "alu_l,move"))
324 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
325 (eq_attr "op_mem" "11"))
326 "cf_v2_ib1+cf_v2_move_11")
328 (define_insn_reservation "cf_v2_move_11_2" 0
329 (and (and (and (eq_attr "cpu" "cf_v2")
330 (eq_attr "type2" "alu_l,move"))
331 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
332 (eq_attr "op_mem" "11"))
333 "cf_v2_ib2+cf_v2_move_11")
335 (define_insn_reservation "cf_v2_move_11_3" 0
336 (and (and (and (eq_attr "cpu" "cf_v2")
337 (eq_attr "type2" "alu_l,move"))
338 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
339 (eq_attr "op_mem" "11"))
340 "cf_v2_ib3+cf_v2_move_11")
342 (define_insn_reservation "cf_v2_move_l_11_1" 0
343 (and (and (and (eq_attr "cpu" "cf_v2")
344 (eq_attr "type2" "move_l"))
345 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
346 (eq_attr "op_mem" "11"))
347 "cf_v2_ib1+cf_v2_move_l_11")
349 (define_insn_reservation "cf_v2_move_l_11_2" 0
350 (and (and (and (eq_attr "cpu" "cf_v2")
351 (eq_attr "type2" "move_l"))
352 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
353 (eq_attr "op_mem" "11"))
354 "cf_v2_ib2+cf_v2_move_l_11")
356 (define_insn_reservation "cf_v2_move_l_11_3" 0
357 (and (and (and (eq_attr "cpu" "cf_v2")
358 (eq_attr "type2" "move_l"))
359 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
360 (eq_attr "op_mem" "11"))
361 "cf_v2_ib3+cf_v2_move_l_11")
363 (define_insn_reservation "cf_v2_move_i1_2" 0
364 (and (and (and (eq_attr "cpu" "cf_v2")
365 (eq_attr "type2" "alu_l,move"))
366 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
367 (eq_attr "op_mem" "i1"))
368 "cf_v2_ib2+cf_v2_move_i1")
370 (define_insn_reservation "cf_v2_move_i1_3" 0
371 (and (and (and (eq_attr "cpu" "cf_v2")
372 (eq_attr "type2" "alu_l,move"))
373 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
374 (eq_attr "op_mem" "i1"))
375 "cf_v2_ib3+cf_v2_move_i1")
377 (define_insn_reservation "cf_v2_move_l_i1_2" 0
378 (and (and (and (eq_attr "cpu" "cf_v2")
379 (eq_attr "type2" "move_l"))
380 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
381 (eq_attr "op_mem" "i1"))
382 "cf_v2_ib2+cf_v2_move_l_i1")
384 (define_insn_reservation "cf_v2_move_l_i1_3" 0
385 (and (and (and (eq_attr "cpu" "cf_v2")
386 (eq_attr "type2" "move_l"))
387 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
388 (eq_attr "op_mem" "i1"))
389 "cf_v2_ib3+cf_v2_move_l_i1")
391 (define_insn_reservation "cf_v2_move_1i_2" 0
392 (and (and (and (eq_attr "cpu" "cf_v2")
393 (eq_attr "type2" "alu_l,move"))
394 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
395 (eq_attr "op_mem" "1i"))
396 "cf_v2_ib2+cf_v2_move_1i")
398 (define_insn_reservation "cf_v2_move_1i_3" 0
399 (and (and (and (eq_attr "cpu" "cf_v2")
400 (eq_attr "type2" "alu_l,move"))
401 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
402 (eq_attr "op_mem" "1i"))
403 "cf_v2_ib3+cf_v2_move_1i")
405 (define_insn_reservation "cf_v2_move_l_1i_2" 0
406 (and (and (and (eq_attr "cpu" "cf_v2")
407 (eq_attr "type2" "move_l"))
408 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
409 (eq_attr "op_mem" "1i"))
410 "cf_v2_ib2+cf_v2_move_l_1i")
412 (define_insn_reservation "cf_v2_move_l_1i_3" 0
413 (and (and (and (eq_attr "cpu" "cf_v2")
414 (eq_attr "type2" "move_l"))
415 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
416 (eq_attr "op_mem" "1i"))
417 "cf_v2_ib3+cf_v2_move_l_1i")
419 (define_insn_reservation "cf_v2_lea_10_1" 1
420 (and (and (and (eq_attr "cpu" "cf_v2")
421 (eq_attr "type2" "lea"))
422 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
423 (eq_attr "op_mem" "10"))
424 "cf_v2_ib1+cf_v2_lea_10")
426 (define_insn_reservation "cf_v2_lea_10_2" 1
427 (and (and (and (eq_attr "cpu" "cf_v2")
428 (eq_attr "type2" "lea"))
429 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
430 (eq_attr "op_mem" "10"))
431 "cf_v2_ib2+cf_v2_lea_10")
433 (define_insn_reservation "cf_v2_lea_10_3" 1
434 (and (and (and (eq_attr "cpu" "cf_v2")
435 (eq_attr "type2" "lea"))
436 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
437 (eq_attr "op_mem" "10"))
438 "cf_v2_ib3+cf_v2_lea_10")
440 (define_insn_reservation "cf_v2_lea_i0_2" 2
441 (and (and (and (eq_attr "cpu" "cf_v2")
442 (eq_attr "type2" "lea"))
443 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
444 (eq_attr "op_mem" "i0"))
445 "cf_v2_ib2+cf_v2_lea_i0")
447 (define_insn_reservation "cf_v2_lea_i0_3" 2
448 (and (and (and (eq_attr "cpu" "cf_v2")
449 (eq_attr "type2" "lea"))
450 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
451 (eq_attr "op_mem" "i0"))
452 "cf_v2_ib3+cf_v2_lea_i0")
454 (define_insn_reservation "cf_v2_pea_11_1" 0
455 (and (and (and (eq_attr "cpu" "cf_v2")
456 (eq_attr "type2" "pea"))
457 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
458 (eq_attr "op_mem" "11"))
459 "cf_v2_ib1+cf_v2_pea_11")
461 (define_insn_reservation "cf_v2_pea_11_2" 0
462 (and (and (and (eq_attr "cpu" "cf_v2")
463 (eq_attr "type2" "pea"))
464 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
465 (eq_attr "op_mem" "11"))
466 "cf_v2_ib2+cf_v2_pea_11")
468 (define_insn_reservation "cf_v2_pea_11_3" 0
469 (and (and (and (eq_attr "cpu" "cf_v2")
470 (eq_attr "type2" "pea"))
471 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
472 (eq_attr "op_mem" "11"))
473 "cf_v2_ib3+cf_v2_pea_11")
475 (define_insn_reservation "cf_v2_pea_i1_2" 0
476 (and (and (and (eq_attr "cpu" "cf_v2")
477 (eq_attr "type2" "pea"))
478 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
479 (eq_attr "op_mem" "i1"))
480 "cf_v2_ib2+cf_v2_pea_i1")
482 (define_insn_reservation "cf_v2_pea_i1_3" 0
483 (and (and (and (eq_attr "cpu" "cf_v2")
484 (eq_attr "type2" "pea"))
485 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
486 (eq_attr "op_mem" "i1"))
487 "cf_v2_ib3+cf_v2_pea_i1")
489 (define_insn_reservation "cf_v2_mul_00_1" 4
490 (and (and (and (eq_attr "cpu" "cf_v2")
491 (eq_attr "type2" "mul"))
492 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
493 (eq_attr "op_mem" "00"))
494 "cf_v2_ib1+cf_v2_mul_00")
496 (define_insn_reservation "cf_v2_mul_00_2" 4
497 (and (and (and (eq_attr "cpu" "cf_v2")
498 (eq_attr "type2" "mul"))
499 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
500 (eq_attr "op_mem" "00"))
501 "cf_v2_ib2+cf_v2_mul_00")
503 (define_insn_reservation "cf_v2_mul_00_3" 4
504 (and (and (and (eq_attr "cpu" "cf_v2")
505 (eq_attr "type2" "mul"))
506 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
507 (eq_attr "op_mem" "00"))
508 "cf_v2_ib3+cf_v2_mul_00")
510 (define_insn_reservation "cf_v2_mul_10_1" 6
511 (and (and (and (eq_attr "cpu" "cf_v2")
512 (eq_attr "type2" "mul"))
513 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
514 (eq_attr "op_mem" "10"))
515 "cf_v2_ib1+cf_v2_mul_10")
517 (define_insn_reservation "cf_v2_mul_10_2" 6
518 (and (and (and (eq_attr "cpu" "cf_v2")
519 (eq_attr "type2" "mul"))
520 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
521 (eq_attr "op_mem" "10"))
522 "cf_v2_ib2+cf_v2_mul_10")
524 (define_insn_reservation "cf_v2_mul_10_3" 6
525 (and (and (and (eq_attr "cpu" "cf_v2")
526 (eq_attr "type2" "mul"))
527 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
528 (eq_attr "op_mem" "10"))
529 "cf_v2_ib3+cf_v2_mul_10")
531 (define_insn_reservation "cf_v2_mul_i0_2" 7
532 (and (and (and (eq_attr "cpu" "cf_v2")
533 (eq_attr "type2" "mul"))
534 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
535 (eq_attr "op_mem" "i0"))
536 "cf_v2_ib2+cf_v2_mul_i0")
538 (define_insn_reservation "cf_v2_mul_i0_3" 7
539 (and (and (and (eq_attr "cpu" "cf_v2")
540 (eq_attr "type2" "mul"))
541 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
542 (eq_attr "op_mem" "i0"))
543 "cf_v2_ib3+cf_v2_mul_i0")
545 ;; ??? As return reads target address from stack, use a mem-read reservation
547 (define_reservation "cf_v2_rts" "cf_v2_move_10")
549 ;; ??? It's not clear what the core does during these 5 cycles.
550 ;; Luckily, we don't care that much about an insn that won't be moved.
551 (define_insn_reservation "cf_v2_rts_1" 5
552 (and (and (eq_attr "cpu" "cf_v2")
553 (eq_attr "type2" "rts"))
554 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
555 "cf_v2_ib1+cf_v2_rts")
557 ;; Call instructions reservations.
559 ;; ??? It's not clear what reservation is best to use for calls.
560 ;; For now we use mem-write + return reservations to reflect the fact of
561 ;; pushing and poping return address to and from the stack.
563 (define_insn_reservation "cf_v2_call_1" 3
564 (and (and (eq_attr "cpu" "cf_v2")
565 (eq_attr "type2" "call"))
566 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
567 "cf_v2_ib1+cf_v2_move_10,cf_v2_rts")
569 (define_insn_reservation "cf_v2_call_2" 3
570 (and (and (eq_attr "cpu" "cf_v2")
571 (eq_attr "type2" "call"))
572 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
573 "cf_v2_ib2+cf_v2_move_10,cf_v2_rts")
575 (define_insn_reservation "cf_v2_call_3" 3
576 (and (and (eq_attr "cpu" "cf_v2")
577 (eq_attr "type2" "call"))
578 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
579 "cf_v2_ib3+cf_v2_move_10,cf_v2_rts")
581 ;; Branch reservations.
583 ;; ??? Branch reservations are unclear to me so far. Luckily, we don't care
584 ;; ??? that much about branches.
585 (define_reservation "cf_v2_bcc" "cf_v2_move_00")
587 (define_insn_reservation "cf_v2_bcc_1" 2
588 (and (and (eq_attr "cpu" "cf_v2")
589 (eq_attr "type2" "bcc"))
590 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
591 "cf_v2_ib1+cf_v2_bcc")
593 (define_insn_reservation "cf_v2_bcc_2" 2
594 (and (and (eq_attr "cpu" "cf_v2")
595 (eq_attr "type2" "bcc"))
596 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
597 "cf_v2_ib2+cf_v2_bcc")
599 (define_insn_reservation "cf_v2_bcc_3" 2
600 (and (and (eq_attr "cpu" "cf_v2")
601 (eq_attr "type2" "bcc"))
602 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
603 "cf_v2_ib3+cf_v2_bcc")
605 (define_reservation "cf_v2_bra" "cf_v2_move_01")
607 (define_insn_reservation "cf_v2_bra_1" 2
608 (and (and (eq_attr "cpu" "cf_v2")
609 (eq_attr "type2" "bra"))
610 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
611 "cf_v2_ib1+cf_v2_bra")
613 (define_insn_reservation "cf_v2_bra_2" 2
614 (and (and (eq_attr "cpu" "cf_v2")
615 (eq_attr "type2" "bra"))
616 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
617 "cf_v2_ib2+cf_v2_bra")
619 (define_insn_reservation "cf_v2_bra_3" 2
620 (and (and (eq_attr "cpu" "cf_v2")
621 (eq_attr "type2" "bra"))
622 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
623 "cf_v2_ib3+cf_v2_bra")
627 (define_reservation "cf_v2_jmp"
628 "cf_v2_dsoc,cf_v2_agex,cf_v2_dsoc,cf_v2_agex")
630 (define_insn_reservation "cf_v2_jmp_1" 3
631 (and (and (eq_attr "cpu" "cf_v2")
632 (eq_attr "type2" "jmp"))
633 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
634 "cf_v2_ib1+cf_v2_jmp")
636 (define_insn_reservation "cf_v2_jmp_2" 3
637 (and (and (eq_attr "cpu" "cf_v2")
638 (eq_attr "type2" "jmp"))
639 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
640 "cf_v2_ib2+cf_v2_jmp")
642 (define_insn_reservation "cf_v2_jmp_3" 3
643 (and (and (eq_attr "cpu" "cf_v2")
644 (eq_attr "type2" "jmp"))
645 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
646 "cf_v2_ib3+cf_v2_jmp")
648 ;; Misc reservations.
650 (define_insn_reservation "cf_v2_unlk_1" 2
651 (and (and (eq_attr "cpu" "cf_v2")
652 (eq_attr "type2" "unlk"))
653 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
654 "cf_v2_ib1+cf_v2_move_l_10")
656 ;; This automaton is used to gather statistics on insns that need reservations.
657 (define_automaton "cf_v2_guess")
659 (define_query_cpu_unit "cf_v2_guess" "cf_v2_guess")
661 ;; Dummy reservation for instructions that are not handled yet.
663 (define_insn_reservation "cf_v2_guess_1" 1
664 (and (and (eq_attr "cpu" "cf_v2")
665 (eq_attr "guess" "yes"))
666 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
667 "cf_v2_ib1+cf_v2_guess+cf_v2_dsoc+cf_v2_agex")
669 (define_insn_reservation "cf_v2_guess_2" 1
670 (and (and (eq_attr "cpu" "cf_v2")
671 (eq_attr "guess" "yes"))
672 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
673 "cf_v2_ib2+cf_v2_guess+cf_v2_dsoc+cf_v2_agex")
675 (define_insn_reservation "cf_v2_guess_3" 1
676 (and (and (eq_attr "cpu" "cf_v2")
677 (eq_attr "guess" "yes"))
678 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
679 "cf_v2_ib3+cf_v2_guess+cf_v2_dsoc+cf_v2_agex")