gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006, 2007 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24 #include <stdlib.h>
  25
  26 const char *host_detect_local_cpu (int argc, const char **argv);
  27
  28 #ifdef __GNUC__
  29 #include "cpuid.h"
  30
  31 /* Returns parameters that describe L1_ASSOC associative cache of size
  32    L1_SIZEKB with lines of size L1_LINE.  */
  33
  34 static char *
  35 describe_cache (unsigned l1_sizekb, unsigned l1_line,
  36                 unsigned l1_assoc ATTRIBUTE_UNUSED)
  37 {
  38   char size[100], line[100];
  39
  40   /* At the moment, gcc middle-end does not use the information about the
  41      associativity of the cache.  */
  42
  43   sprintf (size, "--param l1-cache-size=%u", l1_sizekb);
  44   sprintf (line, "--param l1-cache-line-size=%u", l1_line);
  45
  46   return concat (size, " ", line, " ", NULL);
  47 }
  48
  49 /* Returns the description of caches for an AMD processor.  */
  50
  51 static char *
  52 detect_caches_amd (unsigned max_ext_level)
  53 {
  54   unsigned eax, ebx, ecx, edx;
  55   unsigned l1_sizekb, l1_line, l1_assoc;
  56
  57   if (max_ext_level < 0x80000005)
  58     return (char *) "";
  59
  60   __cpuid (0x80000005, eax, ebx, ecx, edx);
  61
  62   l1_line = ecx & 0xff;
  63   l1_sizekb = (ecx >> 24) & 0xff;
  64   l1_assoc = (ecx >> 16) & 0xff;
  65
  66   return describe_cache (l1_sizekb, l1_line, l1_assoc);
  67 }
  68
  69 /* Stores the size of the L1 cache and cache line, and the associativity
  70    of the cache according to REG to L1_SIZEKB, L1_LINE and L1_ASSOC.  */
  71
  72 static void
  73 decode_caches_intel (unsigned reg, unsigned *l1_sizekb, unsigned *l1_line,
  74                      unsigned *l1_assoc)
  75 {
  76   unsigned i, val;
  77
  78   if (((reg >> 31) & 1) != 0)
  79     return;
  80
  81   for (i = 0; i < 4; i++)
  82     {
  83       val = reg & 0xff;
  84       reg >>= 8;
  85
  86       switch (val)
  87         {
  88         case 0xa:
  89           *l1_sizekb = 8;
  90           *l1_line = 32;
  91           *l1_assoc = 2;
  92           break;
  93         case 0xc:
  94           *l1_sizekb = 16;
  95           *l1_line = 32;
  96           *l1_assoc = 4;
  97           break;
  98         case 0x2c:
  99           *l1_sizekb = 32;
 100           *l1_line = 64;
 101           *l1_assoc = 8;
 102           break;
 103         case 0x60:
 104           *l1_sizekb = 16;
 105           *l1_line = 64;
 106           *l1_assoc = 8;
 107           break;
 108         case 0x66:
 109           *l1_sizekb = 8;
 110           *l1_line = 64;
 111           *l1_assoc = 4;
 112           break;
 113         case 0x67:
 114           *l1_sizekb = 16;
 115           *l1_line = 64;
 116           *l1_assoc = 4;
 117           break;
 118         case 0x68:
 119           *l1_sizekb = 32;
 120           *l1_line = 64;
 121           *l1_assoc = 4;
 122           break;
 123
 124         default:
 125           break;
 126         }
 127     }
 128 }
 129
 130 /* Returns the description of caches for an intel processor.  */
 131
 132 static char *
 133 detect_caches_intel (unsigned max_level)
 134 {
 135   unsigned eax, ebx, ecx, edx;
 136   unsigned l1_sizekb = 0, l1_line = 0, assoc = 0;
 137
 138   if (max_level < 2)
 139     return (char *) "";
 140
 141   __cpuid (2, eax, ebx, ecx, edx);
 142
 143   decode_caches_intel (eax, &l1_sizekb, &l1_line, &assoc);
 144   decode_caches_intel (ebx, &l1_sizekb, &l1_line, &assoc);
 145   decode_caches_intel (ecx, &l1_sizekb, &l1_line, &assoc);
 146   decode_caches_intel (edx, &l1_sizekb, &l1_line, &assoc);
 147
 148   if (!l1_sizekb)
 149     return (char *) "";
 150
 151   return describe_cache (l1_sizekb, l1_line, assoc);
 152 }
 153
 154 /* This will be called by the spec parser in gcc.c when it sees
 155    a %:local_cpu_detect(args) construct.  Currently it will be called
 156    with either "arch" or "tune" as argument depending on if -march=native
 157    or -mtune=native is to be substituted.
 158
 159    It returns a string containing new command line parameters to be
 160    put at the place of the above two options, depending on what CPU
 161    this is executed.  E.g. "-march=k8" on an AMD64 machine
 162    for -march=native.
 163
 164    ARGC and ARGV are set depending on the actual arguments given
 165    in the spec.  */
 166
 167 const char *host_detect_local_cpu (int argc, const char **argv)
 168 {
 169   enum processor_type processor = PROCESSOR_I386;
 170   const char *cpu = "i386";
 171
 172   const char *cache = "";
 173   const char *options = "";
 174
 175  unsigned int eax, ebx, ecx, edx;
 176
 177   unsigned int max_level, ext_level;
 178   unsigned int vendor;
 179   unsigned int family;
 180
 181   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 182   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 183
 184   /* Extended features */
 185   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 186   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 187
 188   bool arch;
 189
 190   if (argc < 1)
 191     return NULL;
 192
 193   arch = !strcmp (argv[0], "arch");
 194
 195   if (!arch && strcmp (argv[0], "tune"))
 196     return NULL;
 197
 198   max_level = __get_cpuid_max (0, &vendor);
 199   if (max_level < 1)
 200     goto done;
 201
 202   __cpuid (1, eax, ebx, ecx, edx);
 203
 204   /* We don't care for extended family.  */
 205   family = (eax >> 8) & 0x0f;
 206
 207   has_sse3 = ecx & bit_SSE3;
 208   has_ssse3 = ecx & bit_SSSE3;
 209   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 210
 211   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 212   has_cmov = edx & bit_CMOV;
 213   has_mmx = edx & bit_MMX;
 214   has_sse = edx & bit_SSE;
 215   has_sse2 = edx & bit_SSE2;
 216
 217   /* Check cpuid level of extended features.  */
 218   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 219
 220   if (ext_level > 0x80000000)
 221     {
 222       __cpuid (0x80000001, eax, ebx, ecx, edx);
 223
 224       has_lahf_lm = ecx & bit_LAHF_LM;
 225       has_sse4a = ecx & bit_SSE4a;
 226
 227       has_longmode = edx & bit_LM;
 228       has_3dnowp = edx & bit_3DNOWP;
 229       has_3dnow = edx & bit_3DNOW;
 230     }
 231
 232   if (!arch)
 233     {
 234       if (vendor == *(unsigned int*) "Auth")
 235         cache = detect_caches_amd (ext_level);
 236       else if (vendor == *(unsigned int*) "Genu")
 237         cache = detect_caches_intel (max_level);
 238     }
 239
 240   if (vendor == *(unsigned int*) "Auth")
 241     {
 242       processor = PROCESSOR_PENTIUM;
 243
 244       if (has_mmx)
 245         processor = PROCESSOR_K6;
 246       if (has_3dnowp)
 247         processor = PROCESSOR_ATHLON;
 248       if (has_sse2 || has_longmode)
 249         processor = PROCESSOR_K8;
 250       if (has_sse4a)
 251         processor = PROCESSOR_AMDFAM10;
 252     }
 253   else if (vendor == *(unsigned int*) "Geod")
 254     processor = PROCESSOR_GEODE;
 255   else
 256     {
 257       switch (family)
 258         {
 259         case 4:
 260           processor = PROCESSOR_I486;
 261           break;
 262         case 5:
 263           processor = PROCESSOR_PENTIUM;
 264           break;
 265         case 6:
 266           processor = PROCESSOR_PENTIUMPRO;
 267           break;
 268         case 15:
 269           processor = PROCESSOR_PENTIUM4;
 270           break;
 271         default:
 272           /* We have no idea.  */
 273           processor = PROCESSOR_GENERIC32;
 274         }
 275     }
 276
 277   switch (processor)
 278     {
 279     case PROCESSOR_I386:
 280       /* Default.  */
 281       break;
 282     case PROCESSOR_I486:
 283       cpu = "i486";
 284       break;
 285     case PROCESSOR_PENTIUM:
 286       if (arch && has_mmx)
 287         cpu = "pentium-mmx";
 288       else
 289         cpu = "pentium";
 290       break;
 291     case PROCESSOR_PENTIUMPRO:
 292       if (has_longmode)
 293         /* It is Core 2 Duo.  */
 294         cpu = "core2";
 295       else if (arch)
 296         {
 297           if (has_sse3)
 298             /* It is Core Duo.  */
 299             cpu = "prescott";
 300           else if (has_sse2)
 301             /* It is Pentium M.  */
 302             cpu = "pentium-m";
 303           else if (has_sse)
 304             /* It is Pentium III.  */
 305             cpu = "pentium3";
 306           else if (has_mmx)
 307             /* It is Pentium II.  */
 308             cpu = "pentium2";
 309           else
 310             /* Default to Pentium Pro.  */
 311             cpu = "pentiumpro";
 312         }
 313       else
 314         /* For -mtune, we default to -mtune=generic.  */
 315         cpu = "generic";
 316       break;
 317     case PROCESSOR_PENTIUM4:
 318       if (has_sse3)
 319         {
 320           if (has_longmode)
 321             cpu = "nocona";
 322           else
 323             cpu = "prescott";
 324         }
 325       else
 326         cpu = "pentium4";
 327       break;
 328     case PROCESSOR_GEODE:
 329       cpu = "geode";
 330       break;
 331     case PROCESSOR_K6:
 332       if (arch && has_3dnow)
 333         cpu = "k6-3";
 334       else
 335         cpu = "k6";
 336       break;
 337     case PROCESSOR_ATHLON:
 338       if (arch && has_sse)
 339         cpu = "athlon-4";
 340       else
 341         cpu = "athlon";
 342       break;
 343     case PROCESSOR_K8:
 344       if (arch && has_sse3)
 345         cpu = "k8-sse3";
 346       else
 347         cpu = "k8";
 348       break;
 349     case PROCESSOR_AMDFAM10:
 350       cpu = "amdfam10";
 351       break;
 352
 353     default:
 354       /* Use something reasonable.  */
 355       if (arch)
 356         {
 357           if (has_ssse3)
 358             cpu = "core2";
 359           else if (has_sse3)
 360             {
 361               if (has_longmode)
 362                 cpu = "nocona";
 363               else
 364                 cpu = "prescott";
 365             }
 366           else if (has_sse2)
 367             cpu = "pentium4";
 368           else if (has_cmov)
 369             cpu = "pentiumpro";
 370           else if (has_mmx)
 371             cpu = "pentium-mmx";
 372           else if (has_cmpxchg8b)
 373             cpu = "pentium";
 374         }
 375       else
 376         cpu = "generic";
 377     }
 378
 379   if (arch)
 380     {
 381       if (has_cmpxchg16b)
 382         options = concat (options, "-mcx16 ", NULL);
 383       if (has_lahf_lm)
 384         options = concat (options, "-msahf ", NULL);
 385     }
 386
 387 done:
 388   return concat (cache, "-m", argv[0], "=", cpu, " ", options, NULL);
 389 }
 390 #else
 391
 392 /* If we aren't compiling with GCC we just provide a minimal
 393    default value.  */
 394
 395 const char *host_detect_local_cpu (int argc, const char **argv)
 396 {
 397   const char *cpu;
 398   bool arch;
 399
 400   if (argc < 1)
 401     return NULL;
 402
 403   arch = !strcmp (argv[0], "arch");
 404
 405   if (!arch && strcmp (argv[0], "tune"))
 406     return NULL;
 407
 408   if (arch)
 409     {
 410       /* FIXME: i386 is wrong for 64bit compiler.  How can we tell if
 411          we are generating 64bit or 32bit code?  */
 412       cpu = "i386";
 413     }
 414   else
 415     cpu = "generic";
 416
 417   return concat ("-m", argv[0], "=", cpu, NULL);
 418 }
 419 #endif /* __GNUC__ */