1 ;; GCC machine description for CRIS cpu cores.
2 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Axis Communications.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
25 ;; See files "md.texi" and "rtl.def" for documentation on define_insn,
28 ;; The function cris_notice_update_cc in cris.c handles condition code
29 ;; updates for most instructions, helped by the "cc" attribute.
31 ;; There are several instructions that are orthogonal in size, and seems
32 ;; they could be matched by a single pattern without a specified size
33 ;; for the operand that is orthogonal. However, this did not work on
34 ;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a
35 ;; constant is substituted into an operand, the actual mode must be
36 ;; deduced from the pattern. There is reasonable hope that that has been
37 ;; fixed, so FIXME: try again.
39 ;; You will notice that three-operand alternatives ("=r", "r", "!To")
40 ;; are marked with a "!" constraint modifier to avoid being reloaded
41 ;; into. This is because gcc would otherwise prefer to use the constant
42 ;; pool and its offsettable address instead of reloading to an
43 ;; ("=r", "0", "i") alternative. Also, the constant-pool support was not
44 ;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3.
46 ;; All insns that look like (set (...) (plus (...) (reg:SI 8)))
47 ;; get problems when reloading r8 (frame pointer) to r14 + offs (stack
48 ;; pointer). Thus the instructions that get into trouble have specific
49 ;; checks against matching frame_pointer_rtx.
50 ;; ??? But it should be re-checked for gcc > 2.7.2
51 ;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x.
53 ;; FIXME: When PIC, all [rX=rY+S] could be enabled to match
54 ;; [rX=gotless_symbol].
55 ;; The movsi for a gotless symbol could be split (post reload).
60 ;; PLT reference from call expansion: operand 0 is the address,
61 ;; the mode is VOIDmode. Always wrapped in CONST.
62 ;; The value is relative to the GOT.
63 (CRIS_UNSPEC_PLT_GOTREL 0)
65 ;; PLT reference from call expansion: operand 0 is the address,
66 ;; the mode is VOIDmode. Always wrapped in CONST.
67 ;; The value is relative to the PC. It's arch-dependent whether
68 ;; the offset counts from the start or the end of the current item.
69 (CRIS_UNSPEC_PLT_PCREL 1)
71 ;; The address of the global offset table as a source operand.
74 ;; The offset from the global offset table to the operand.
75 (CRIS_UNSPEC_GOTREL 3)
77 ;; The PC-relative offset to the operand. It's arch-dependent whether
78 ;; the offset counts from the start or the end of the current item.
81 ;; The index into the global offset table of a symbol, while
82 ;; also generating a GOT entry for the symbol.
83 (CRIS_UNSPEC_GOTREAD 5)
85 ;; Similar to CRIS_UNSPEC_GOTREAD, but also generating a PLT entry.
86 (CRIS_UNSPEC_PLTGOTREAD 6)
88 ;; Condition for v32 casesi jump, since it needs to have if_then_else
89 ;; form with register as one branch and default label as other.
90 ;; Operand 0 is const_int 0.
91 (CRIS_UNSPEC_CASESI 7)
93 ;; Stack frame deallocation barrier.
94 (CRIS_UNSPEC_FRAME_DEALLOC 8)
96 ;; Swap all 32 bits of the operand; 31 <=> 0, 30 <=> 1...
97 (CRIS_UNSPEC_SWAP_BITS 9)
103 (CRIS_STATIC_CHAIN_REGNUM 7)
110 (CRIS_CC0_REGNUM 19)]
113 ;; We need an attribute to define whether an instruction can be put in
114 ;; a branch-delay slot or not, and whether it has a delay slot.
116 ;; Branches and return instructions have a delay slot, and cannot
117 ;; themselves be put in a delay slot. This has changed *for short
118 ;; branches only* between architecture variants, but the possible win
119 ;; is presumed negligible compared to the added complexity of the machine
120 ;; description: one would have to add always-correct infrastructure to
121 ;; distinguish short branches.
123 ;; Whether an instruction can be put in a delay slot depends on the
124 ;; instruction (all short instructions except jumps and branches)
125 ;; and the addressing mode (must not be prefixed or referring to pc).
126 ;; In short, any "slottable" instruction must be 16 bit and not refer
127 ;; to pc, or alter it.
129 ;; The possible values are "yes", "no", "has_slot", "has_return_slot"
130 ;; and "has_call_slot".
131 ;; Yes/no tells whether the insn is slottable or not. Has_call_slot means
132 ;; that the insn is a call insn, which for CRIS v32 has a delay-slot.
133 ;; Of special concern is that no RTX_FRAME_RELATED insn must go in that
134 ;; call delay slot, as it's located in the address *after* the call insn,
135 ;; and the unwind machinery doesn't know about delay slots.
136 ;; Has_slot means that the insn is a branch insn (which are
137 ;; not considered slottable since that is generally true). Having the
138 ;; seemingly illogical value "has_slot" means we do not have to add
139 ;; another attribute just to say that an insn has a delay-slot, since it
140 ;; also infers that it is not slottable. Better names for the attribute
141 ;; were found to be longer and not add readability to the machine
143 ;; Has_return_slot is similar, for the return insn.
145 ;; The default that is defined here for this attribute is "no", not
146 ;; slottable, not having a delay-slot, so there's no need to worry about
147 ;; it being wrong for non-branch and return instructions.
148 ;; The default could depend on the kind of insn and the addressing
149 ;; mode, but that would need more attributes and hairier, more error
152 ;; There is an extra memory constraint, 'Q', which recognizes an indirect
153 ;; register. The constraints 'Q' and '>' together match all possible
154 ;; memory operands that are slottable.
155 ;; For other operands, you need to check if it has a valid "slottable"
156 ;; quick-immediate operand, where the particular signedness-variation
157 ;; may match the constraints 'I' or 'J'.), and include it in the
158 ;; constraint pattern for the slottable pattern. An alternative using
159 ;; only "r" constraints is most often slottable.
161 (define_attr "slottable" "no,yes,has_slot,has_return_slot,has_call_slot"
164 ;; We also need attributes to sanely determine the condition code
165 ;; state. See cris_notice_update_cc for how this is used.
167 (define_attr "cc" "none,clobber,normal,noov32,rev" (const_string "normal"))
169 ;; At the moment, this attribute is just used to help bb-reorder do its
170 ;; work; the default 0 doesn't help it. Many insns have other lengths,
171 ;; though none are shorter.
172 (define_attr "length" "" (const_int 2))
174 ;; A branch has one delay-slot. The instruction in the
175 ;; delay-slot is always executed, independent of whether the branch is
176 ;; taken or not. Note that besides setting "slottable" to "has_slot",
177 ;; there also has to be a "%#" at the end of a "delayed" instruction
178 ;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can
179 ;; catch it and print a "nop" if necessary. This method was stolen from
182 (define_delay (eq_attr "slottable" "has_slot")
183 [(eq_attr "slottable" "yes") (nil) (nil)])
185 ;; We can't put prologue insns in call-insn delay-slots when
186 ;; DWARF2 unwind info is emitted, because the unwinder matches the
187 ;; address after the insn. It must see the return address of a call at
188 ;; a position at least *one byte after* the insn, or it'll think that
189 ;; the insn hasn't been executed. If the insn is in a delay-slot of a
190 ;; call, it's just *exactly* after the insn.
192 (define_delay (eq_attr "slottable" "has_call_slot")
193 [(and (eq_attr "slottable" "yes")
194 (ior (eq (symbol_ref "RTX_FRAME_RELATED_P (insn)")
196 (eq (symbol_ref "flag_exceptions")
200 ;; The insn in the return insn slot must not be the
201 ;; return-address-register restore. FIXME: Use has_slot and express
202 ;; as a parallel with a use of the return-address-register (currently
203 ;; only SRP). However, this requires an amount of fixing tests for
204 ;; naked RETURN in middle-end.
205 (define_delay (eq_attr "slottable" "has_return_slot")
206 [(and (eq_attr "slottable" "yes")
207 (eq (symbol_ref "dead_or_set_regno_p (insn, CRIS_SRP_REGNUM)")
212 ;; Iterator definitions.
214 ;; For the "usual" pattern size alternatives.
215 (define_mode_iterator BWD [SI HI QI])
216 (define_mode_iterator WD [SI HI])
217 (define_mode_iterator BW [HI QI])
218 (define_mode_attr S [(SI "HI") (HI "QI")])
219 (define_mode_attr s [(SI "hi") (HI "qi")])
220 (define_mode_attr m [(SI ".d") (HI ".w") (QI ".b")])
221 (define_mode_attr mm [(SI ".w") (HI ".b")])
222 (define_mode_attr nbitsm1 [(SI "31") (HI "15") (QI "7")])
224 ;; For the sign_extend+zero_extend variants.
225 (define_code_iterator szext [sign_extend zero_extend])
226 (define_code_attr u [(sign_extend "") (zero_extend "u")])
227 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
229 ;; For the shift variants.
230 (define_code_iterator shift [ashiftrt lshiftrt ashift])
231 (define_code_iterator shiftrt [ashiftrt lshiftrt])
232 (define_code_attr shlr [(ashiftrt "ashr") (lshiftrt "lshr") (ashift "ashl")])
233 (define_code_attr slr [(ashiftrt "asr") (lshiftrt "lsr") (ashift "lsl")])
235 (define_code_iterator ncond [eq ne gtu ltu geu leu])
236 (define_code_iterator ocond [gt le])
237 (define_code_iterator rcond [lt ge])
238 (define_code_attr CC [(eq "eq") (ne "ne") (gt "gt") (gtu "hi") (lt "lt")
239 (ltu "lo") (ge "ge") (geu "hs") (le "le") (leu "ls")])
240 (define_code_attr rCC [(eq "ne") (ne "eq") (gt "le") (gtu "ls") (lt "ge")
241 (ltu "hs") (ge "lt") (geu "lo") (le "gt") (leu "hi")])
242 (define_code_attr oCC [(lt "mi") (ge "pl")])
243 (define_code_attr roCC [(lt "pl") (ge "mi")])
245 ;; Operand and operator predicates.
247 (include "predicates.md")
253 ;; Allow register and offsettable mem operands only; post-increment is
254 ;; not worth the trouble.
256 (define_expand "tstdi"
257 [(set (cc0) (match_operand:DI 0 "nonimmediate_operand"))]
260 if (TARGET_V32 && MEM_P (operands[0]))
261 operands[0] = force_reg (DImode, operands[0]);
264 (define_insn "*tstdi_non_v32"
266 (match_operand:DI 0 "nonimmediate_operand" "r,o"))]
268 "test.d %M0\;ax\;test.d %H0")
270 (define_insn "*tstdi_v32"
272 (match_operand:DI 0 "register_operand" "r"))]
274 "cmpq 0,%M0\;ax\;cmpq 0,%H0")
276 ;; No test insns with side-effect on the mem addressing.
278 ;; See note on cmp-insns with side-effects (or lack of them)
280 ;; Normal named test patterns from SI on.
284 (match_operand:SI 0 "nonimmediate_operand" "r,Q>,m"))]
287 if (which_alternative == 0 && TARGET_V32)
291 [(set_attr "slottable" "yes,yes,no")])
293 (define_expand "tst<mode>"
295 (match_operand:BW 0 "nonimmediate_operand"))]
299 (define_insn "*tst<mode>_cmp"
301 (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m"))]
302 "cris_cc0_user_requires_cmp (insn)"
307 [(set_attr "slottable" "no,yes,no")])
309 (define_insn "*tst<mode>_non_cmp"
311 (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m"))]
312 "!cris_cc0_user_requires_cmp (insn)"
317 [(set_attr "slottable" "yes,yes,no")
318 (set_attr "cc" "noov32,*,*")])
320 ;; It seems that the position of the sign-bit and the fact that 0.0 is
321 ;; all 0-bits would make "tstsf" a straight-forward implementation;
322 ;; either "test.d" it for positive/negative or "btstq 30,r" it for
325 ;; FIXME: Do that some time; check next_cc0_user to determine if
326 ;; zero or negative is tested for.
330 ;; We could optimize the sizes of the immediate operands for various
331 ;; cases, but that is not worth it because of the very little usage of
332 ;; DImode for anything else but a structure/block-mode. Just do the
333 ;; obvious stuff for the straight-forward constraint letters.
335 (define_expand "cmpdi"
337 (compare (match_operand:DI 0 "nonimmediate_operand" "")
338 (match_operand:DI 1 "general_operand" "")))]
341 if (TARGET_V32 && !REG_P (operands[0]))
342 operands[0] = force_reg (DImode, operands[0]);
343 if (TARGET_V32 && MEM_P (operands[1]))
344 operands[1] = force_reg (DImode, operands[1]);
347 (define_insn "*cmpdi_non_v32"
349 (compare (match_operand:DI 0 "nonimmediate_operand" "r,r,r,r,r,r,o")
350 (match_operand:DI 1 "general_operand" "K,I,P,n,r,o,r")))]
353 cmpq %1,%M0\;ax\;cmpq 0,%H0
354 cmpq %1,%M0\;ax\;cmpq -1,%H0
355 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
356 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
357 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
358 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
359 cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1")
361 (define_insn "*cmpdi_v32"
363 (compare (match_operand:DI 0 "register_operand" "r,r,r,r,r")
364 (match_operand:DI 1 "nonmemory_operand" "K,I,P,n,r")))]
367 cmpq %1,%M0\;ax\;cmpq 0,%H0
368 cmpq %1,%M0\;ax\;cmpq -1,%H0
369 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
370 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
371 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0")
373 ;; Note that compare insns with side effect addressing mode (e.g.):
375 ;; cmp.S [rx=ry+i],rz;
376 ;; cmp.S [%3=%1+%2],%0
378 ;; are *not* usable for gcc since the reloader *does not accept*
379 ;; cc0-changing insns with side-effects other than setting the condition
380 ;; codes. The reason is that the reload stage *may* cause another insn to
381 ;; be output after the main instruction, in turn invalidating cc0 for the
382 ;; insn using the test. (This does not apply to the CRIS case, since a
383 ;; reload for output -- move to memory -- does not change the condition
384 ;; code. Unfortunately we have no way to describe that at the moment. I
385 ;; think code would improve being in the order of one percent faster.
387 ;; We have cmps and cmpu (compare reg w. sign/zero extended mem).
388 ;; These are mostly useful for compares in SImode, using 8 or 16-bit
389 ;; constants, but sometimes gcc will find its way to use it for other
390 ;; (memory) operands. Avoid side-effect patterns, though (see above).
392 (define_insn "*cmp_ext<mode>"
395 (match_operand:SI 0 "register_operand" "r,r")
396 (match_operator:SI 2 "cris_extend_operator"
397 [(match_operand:BW 1 "memory_operand" "Q>,m")])))]
400 [(set_attr "slottable" "yes,no")])
402 ;; Swap operands; it seems the canonical look (if any) is not enforced.
404 ;; FIXME: Investigate that.
406 (define_insn "*cmp_swapext<mode>"
409 (match_operator:SI 2 "cris_extend_operator"
410 [(match_operand:BW 0 "memory_operand" "Q>,m")])
411 (match_operand:SI 1 "register_operand" "r,r")))]
414 [(set_attr "slottable" "yes,no")
415 (set_attr "cc" "rev")])
417 ;; The "normal" compare patterns, from SI on. Special-cases with zero
418 ;; should not happen.
423 (match_operand:SI 0 "nonimmediate_operand" "r,r,r, Q>,r,r,m")
424 (match_operand:SI 1 "general_operand" "I,r,Q>,r, P,g,r")))]
434 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")
435 (set_attr "cc" "normal,normal,normal,rev,normal,normal,rev")])
437 (define_insn "cmp<mode>"
439 (compare (match_operand:BW 0 "nonimmediate_operand" "r,r, Q>,r,m")
440 (match_operand:BW 1 "general_operand" "r,Q>,r, g,r")))]
448 [(set_attr "slottable" "yes,yes,yes,no,no")
449 (set_attr "cc" "normal,normal,rev,normal,rev")])
451 ;; Pattern matching the BTST insn.
452 ;; It is useful for "if (i & val)" constructs, where val is an exact
453 ;; power of 2, or if val + 1 is a power of two, where we check for a bunch
454 ;; of zeros starting at bit 0).
456 ;; SImode. This mode is the only one needed, since gcc automatically
457 ;; extends subregs for lower-size modes. FIXME: Add testcase.
461 (match_operand:SI 0 "nonmemory_operand" "r,r,r,r,r,r,n")
462 (match_operand:SI 1 "const_int_operand" "K,n,K,n,K,n,n")
463 (match_operand:SI 2 "nonmemory_operand" "M,M,K,n,r,r,r")))]
464 ;; Either it is a single bit, or consecutive ones starting at 0.
465 ;; The btst ones depend on stuff in NOTICE_UPDATE_CC.
466 "CONST_INT_P (operands[1])
467 && (operands[1] == const1_rtx || operands[2] == const0_rtx)
468 && (REG_S_P (operands[0])
469 || (operands[1] == const1_rtx
470 && REG_S_P (operands[2])
471 && CONST_INT_P (operands[0])
472 && exact_log2 (INTVAL (operands[0])) >= 0))
475 ;; The next-to-last "&&" condition above should be caught by some kind of
476 ;; canonicalization in gcc, but we can easily help with it here.
477 ;; It results from expressions of the type
478 ;; "power_of_2_value & (1 << y)".
480 ;; Since there may be codes with tests in on bits (in constant position)
481 ;; beyond the size of a word, handle that by assuming those bits are 0.
482 ;; GCC should handle that, but it's a matter of easily-added belts while
483 ;; having suspenders.
493 [(set_attr "slottable" "yes")
494 (set_attr "cc" "noov32")])
498 ;; The whole mandatory movdi family is here; expander, "anonymous"
499 ;; recognizer and splitter. We're forced to have a movdi pattern,
500 ;; although GCC should be able to split it up itself. Normally it can,
501 ;; but if other insns have DI operands (as is the case here), reload
502 ;; must be able to generate or match a movdi. many testcases fail at
503 ;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See
504 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00104.html>.
505 ;; However, a patch from Richard Kenner (similar to the cause of
506 ;; discussion at the URL above), indicates otherwise. See
507 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00554.html>.
508 ;; The truth has IMO is not been decided yet, so check from time to
509 ;; time by disabling the movdi patterns.
511 ;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at
512 ;; -O0, we need a movdi as a temporary measure. Here's how things fail:
513 ;; A cmpdi RTX needs reloading (global):
514 ;; (insn 185 326 186 (set (cc0)
515 ;; (compare (mem/f:DI (reg/v:SI 22) 0)
516 ;; (const_int 1 [0x1]))) 4 {cmpdi} (nil)
518 ;; Now, reg 22 is reloaded for input address, and the mem is also moved
519 ;; out of the instruction (into a register), since one of the operands
520 ;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is
521 ;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok
522 ;; wrt. overlap). The bad things happen with the synthesis in
523 ;; emit_move_insn_1; the location where to substitute reg 10 is lost into
524 ;; two new RTX:es, both still having reg 22. Later on, the left-over reg
525 ;; 22 is recognized to have an equivalent in memory which is substituted
526 ;; straight in, and we end up with an unrecognizable insn:
527 ;; (insn 325 324 326 (set (reg:SI 9 r9)
528 ;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8)
529 ;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil)
531 ;; which is the first part of the reloaded synthesized "movdi".
532 ;; The right thing would be to add equivalent replacement locations for
533 ;; insn with pseudos that need more reloading. The question is where.
535 (define_expand "movdi"
536 [(set (match_operand:DI 0 "nonimmediate_operand" "")
537 (match_operand:DI 1 "general_operand" ""))]
540 if (MEM_P (operands[0])
541 && operands[1] != const0_rtx
542 && (!TARGET_V32 || (!REG_P (operands[1]) && can_create_pseudo_p ())))
543 operands[1] = copy_to_mode_reg (DImode, operands[1]);
545 /* Some other ports (as of 2001-09-10 for example mcore and romp) also
546 prefer to split up constants early, like this. The testcase in
547 gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the
548 resulting subreg sets when using the construct from mcore (as of FSF
549 CVS, version -r 1.5), and it believes that the high part (the last one
550 emitted) is the final value. This construct from romp seems more
551 robust, especially considering the head comments from
552 emit_no_conflict_block. */
553 if ((CONST_INT_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
554 && ! reload_completed
555 && ! reload_in_progress)
558 rtx op0 = operands[0];
559 rtx op1 = operands[1];
562 emit_move_insn (operand_subword (op0, 0, 1, DImode),
563 operand_subword (op1, 0, 1, DImode));
564 emit_move_insn (operand_subword (op0, 1, 1, DImode),
565 operand_subword (op1, 1, 1, DImode));
566 insns = get_insns ();
569 emit_no_conflict_block (insns, op0, op1, 0, op1);
574 (define_insn_and_split "*movdi_insn_non_v32"
575 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rx,m")
576 (match_operand:DI 1 "general_operand" "rx,g,rxM"))]
577 "(register_operand (operands[0], DImode)
578 || register_operand (operands[1], DImode)
579 || operands[1] == const0_rtx)
582 "&& reload_completed"
584 "operands[2] = cris_split_movdx (operands);")
586 ;; Overlapping (but non-identical) source memory address and destination
587 ;; register would be a compiler bug, so we don't have to specify that.
588 (define_insn "*movdi_v32"
590 (match_operand:DI 0 "nonimmediate_operand" "=r,rx,&r,>, m,r,x,m")
591 (match_operand:DI 1 "general_operand" "rxi,r>,m, rx,r,m,m,x"))]
594 switch (which_alternative)
596 /* FIXME: 1) Use autoincrement where possible. 2) Have peephole2,
597 particularly for cases where the address register is dead. */
599 if (REGNO (operands[0]) == REGNO (XEXP (operands[1], 0)))
600 return "addq 4,%L1\;move.d %1,%H0\;subq 4,%L1\;move.d %1,%M0";
601 gcc_assert (REGNO (operands[0]) + 1 == REGNO (XEXP (operands[1], 0)));
602 return "move.d [%L1+],%M0\;move.d [%L1],%H0";
604 /* We could do away with the addq if we knew the address-register
605 isn't ACR. If we knew the address-register is dead, we could do
606 away with the subq too. */
607 return "move.d [%L1],%M0\;addq 4,%L1\;move.d [%L1],%H0\;subq 4,%L1";
609 return "move.d %M1,[%L0]\;addq 4,%L0\;move.d %H1,[%L0]\;subq 4,%L0";
611 return "move [%L1],%M0\;addq 4,%L1\;move [%L1],%H0\;subq 4,%L1";
613 return "move %M1,[%L0]\;addq 4,%L0\;move %H1,[%L0]\;subq 4,%L0";
619 ;; The non-split cases clobber cc0 because of their adds and subs.
620 ;; Beware that NOTICE_UPDATE_CC is called before the forced split happens.
621 [(set_attr "cc" "*,*,clobber,*,clobber,clobber,*,*")])
623 ;; Much like "*movdi_insn_non_v32". Overlapping registers and constants
624 ;; is handled so much better in cris_split_movdx.
626 [(set (match_operand:DI 0 "nonimmediate_operand" "")
627 (match_operand:DI 1 "general_operand" ""))]
630 && (!MEM_P (operands[0]) || !REG_P (XEXP (operands[0], 0)))
631 && (!MEM_P (operands[1]) || !REG_P (XEXP (operands[1], 0)))"
633 "operands[2] = cris_split_movdx (operands);")
635 ;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw
636 ;; and move.S1 [rx=ry+i],rz
637 ;; Then movs.S1 and movu.S1 for both modes.
639 ;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx
640 ;; FIXME: These could have anonymous mode for operand 0.
641 ;; FIXME: Special registers' alternatives too.
643 (define_insn "*mov_side<mode>_biap"
644 [(set (match_operand:BW 0 "register_operand" "=r,r")
646 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
647 (match_operand:SI 2 "const_int_operand" "n,n"))
648 (match_operand:SI 3 "register_operand" "r,r"))))
649 (set (match_operand:SI 4 "register_operand" "=*3,r")
650 (plus:SI (mult:SI (match_dup 1)
653 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
656 move<m> [%4=%3+%1%T2],%0")
658 (define_insn "*mov_sidesisf_biap"
659 [(set (match_operand 0 "register_operand" "=r,r,x,x")
661 (mult:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
662 (match_operand:SI 2 "const_int_operand" "n,n,n,n"))
663 (match_operand:SI 3 "register_operand" "r,r,r,r"))))
664 (set (match_operand:SI 4 "register_operand" "=*3,r,*3,r")
665 (plus:SI (mult:SI (match_dup 1)
668 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
669 && cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
672 move.%s0 [%4=%3+%1%T2],%0
674 move [%4=%3+%1%T2],%0")
676 ;; move.S1 [rx=ry+i],rz
677 ;; avoiding move.S1 [ry=ry+i],rz
678 ;; and move.S1 [rz=ry+i],rz
679 ;; Note that "i" is allowed to be a register.
681 (define_insn "*mov_side<mode>"
682 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r")
684 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
685 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r"))))
686 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
687 (plus:SI (match_dup 1)
689 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
691 if ((which_alternative == 0 || which_alternative == 3)
692 && (!CONST_INT_P (operands[2])
693 || INTVAL (operands[2]) > 127
694 || INTVAL (operands[2]) < -128
695 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
696 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
698 if (which_alternative == 4)
699 return "move<m> [%3=%2%S1],%0";
700 return "move<m> [%3=%1%S2],%0";
703 (define_insn "*mov_sidesisf"
704 [(set (match_operand 0 "register_operand" "=r,r,r,x,x,x,r,r,x,x")
707 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,r,r,r,R,R,R,R")
708 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r>Rn,r,>Rn,r,r,r,r"))))
709 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*1,r,r,*2,r,*2,r")
710 (plus:SI (match_dup 1)
712 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
713 && cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
715 if ((which_alternative == 0
716 || which_alternative == 3
717 || which_alternative == 6
718 || which_alternative == 8)
719 && (!CONST_INT_P (operands[2])
720 || INTVAL (operands[2]) > 127
721 || INTVAL (operands[2]) < -128
722 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
723 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
725 if (which_alternative < 3)
726 return "move.%s0 [%3=%1%S2],%0";
727 if (which_alternative == 7)
728 return "move.%s0 [%3=%2%S1],%0";
729 if (which_alternative == 9)
730 return "move [%3=%2%S1],%0";
731 return "move [%3=%1%S2],%0";
734 ;; Other way around; move to memory.
736 ;; Note that the condition (which for side-effect patterns is usually a
737 ;; call to cris_side_effect_mode_ok), isn't consulted for register
738 ;; allocation preferences -- constraints is the method for that. The
739 ;; drawback is that we can't exclude register allocation to cause
740 ;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or
741 ;; rx==rz if we use an earlyclobber modifier for the constraint for rx.
742 ;; Instead of that, we recognize and split the cases where dangerous
743 ;; register combinations are spotted: where a register is set in the
744 ;; side-effect, and used in the main insn. We don't handle the case where
745 ;; the set in the main insn overlaps the set in the side-effect; that case
746 ;; must be handled in gcc. We handle just the case where the set in the
747 ;; side-effect overlaps the input operand of the main insn (i.e. just
751 ;; move.s rz,[ry=rx+rw.S]
753 (define_insn "*mov_side<mode>_biap_mem"
754 [(set (mem:BW (plus:SI
755 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
756 (match_operand:SI 1 "const_int_operand" "n,n,n"))
757 (match_operand:SI 2 "register_operand" "r,r,r")))
758 (match_operand:BW 3 "register_operand" "r,r,r"))
759 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
760 (plus:SI (mult:SI (match_dup 0)
763 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
767 move<m> %3,[%4=%2+%0%T1]")
769 (define_insn "*mov_sidesisf_biap_mem"
771 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r,r,r,r")
772 (match_operand:SI 1 "const_int_operand" "n,n,n,n,n,n"))
773 (match_operand:SI 2 "register_operand" "r,r,r,r,r,r")))
774 (match_operand 3 "register_operand" "r,r,r,x,x,x"))
775 (set (match_operand:SI 4 "register_operand" "=*2,!3,r,*2,!3,r")
776 (plus:SI (mult:SI (match_dup 0)
779 "GET_MODE_SIZE (GET_MODE (operands[3])) == UNITS_PER_WORD
780 && cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
784 move.%s3 %3,[%4=%2+%0%T1]
787 move %3,[%4=%2+%0%T1]")
789 ;; Split for the case above where we're out of luck with register
790 ;; allocation (again, the condition isn't checked for that), and we end up
791 ;; with the set in the side-effect getting the same register as the input
796 [(set (match_operator
799 (mult:SI (match_operand:SI 0 "register_operand" "")
800 (match_operand:SI 1 "const_int_operand" ""))
801 (match_operand:SI 2 "register_operand" ""))])
802 (match_operand 3 "register_operand" ""))
803 (set (match_operand:SI 4 "register_operand" "")
804 (plus:SI (mult:SI (match_dup 0)
807 "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])"
808 [(set (match_dup 5) (match_dup 3))
809 (set (match_dup 4) (match_dup 2))
811 (plus:SI (mult:SI (match_dup 0)
815 = replace_equiv_address (operands[6],
816 gen_rtx_PLUS (SImode,
817 gen_rtx_MULT (SImode,
822 ;; move.s rx,[ry=rz+i]
823 ;; FIXME: These could have anonymous mode for operand 2.
827 (define_insn "*mov_side<mode>_mem"
829 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r,R,R,R")
830 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn,r,r,r")))
831 (match_operand:BW 2 "register_operand" "r,r,r,r,r,r,r"))
832 (set (match_operand:SI 3 "register_operand" "=*0,!*2,r,r,*1,!*2,r")
833 (plus:SI (match_dup 0)
835 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
837 if ((which_alternative == 0 || which_alternative == 4)
838 && (!CONST_INT_P (operands[1])
839 || INTVAL (operands[1]) > 127
840 || INTVAL (operands[1]) < -128
841 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
842 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
844 if (which_alternative == 1 || which_alternative == 5)
846 if (which_alternative == 6)
847 return "move.%s2 %2,[%3=%1%S0]";
848 return "move<m> %2,[%3=%0%S1]";
853 (define_insn "*mov_sidesisf_mem"
857 0 "cris_bdap_operand"
858 "%r, r, r,r, r, r,r, R,R, R,R, R")
860 1 "cris_bdap_operand"
861 "r>Rn,r>Rn,r,>Rn,r>Rn,r,>Rn,r,r, r,r, r")))
862 (match_operand 2 "register_operand"
863 "r, r, r,r, x, x,x, r,r, r,x, x"))
864 (set (match_operand:SI 3 "register_operand"
865 "=*0,!2, r,r, *0, r,r, *1,!*2,r,*1,r")
866 (plus:SI (match_dup 0)
868 "GET_MODE_SIZE (GET_MODE (operands[2])) == UNITS_PER_WORD
869 && cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
871 if ((which_alternative == 0 || which_alternative == 4)
872 && (!CONST_INT_P (operands[1])
873 || INTVAL (operands[1]) > 127
874 || INTVAL (operands[1]) < -128
875 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
876 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
878 if (which_alternative == 1
879 || which_alternative == 7
880 || which_alternative == 8
881 || which_alternative == 10)
883 if (which_alternative < 4)
884 return "move.%s2 %2,[%3=%0%S1]";
885 if (which_alternative == 9)
886 return "move.%s2 %2,[%3=%1%S0]";
887 if (which_alternative == 11)
888 return "move %2,[%3=%1%S0]";
889 return "move %2,[%3=%0%S1]";
892 ;; Like the biap case, a split where the set in the side-effect gets the
893 ;; same register as the input register to the main insn, since the
894 ;; condition isn't checked at register allocation.
898 [(set (match_operator
901 (match_operand:SI 0 "cris_bdap_operand" "")
902 (match_operand:SI 1 "cris_bdap_operand" ""))])
903 (match_operand 2 "register_operand" ""))
904 (set (match_operand:SI 3 "register_operand" "")
905 (plus:SI (match_dup 0) (match_dup 1)))])]
906 "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"
907 [(set (match_dup 4) (match_dup 2))
908 (set (match_dup 3) (match_dup 0))
909 (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))]
912 ;; Clear memory side-effect patterns. It is hard to get to the mode if
913 ;; the MEM was anonymous, so there will be one for each mode.
915 ;; clear.[bwd] [ry=rx+rw.s2]
917 (define_insn "*clear_side<mode>_biap"
918 [(set (mem:BWD (plus:SI
919 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
920 (match_operand:SI 1 "const_int_operand" "n,n"))
921 (match_operand:SI 2 "register_operand" "r,r")))
923 (set (match_operand:SI 3 "register_operand" "=*2,r")
924 (plus:SI (mult:SI (match_dup 0)
927 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
930 clear<m> [%3=%2+%0%T1]")
932 ;; clear.[bwd] [ry=rz+i]
934 (define_insn "*clear_side<mode>"
936 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,R,R")
937 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
939 (set (match_operand:SI 2 "register_operand" "=*0,r,r,*1,r")
940 (plus:SI (match_dup 0)
942 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
944 if ((which_alternative == 0 || which_alternative == 3)
945 && (!CONST_INT_P (operands[1])
946 || INTVAL (operands[1]) > 127
947 || INTVAL (operands[1]) < -128
948 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
949 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
951 if (which_alternative == 4)
952 return "clear<m> [%2=%1%S0]";
953 return "clear<m> [%2=%0%S1]";
956 ;; Normal move patterns from SI on.
958 (define_expand "movsi"
960 (match_operand:SI 0 "nonimmediate_operand" "")
961 (match_operand:SI 1 "cris_general_operand_or_symbol" ""))]
964 /* If the output goes to a MEM, make sure we have zero or a register as
966 if (MEM_P (operands[0])
967 && ! REG_S_P (operands[1])
968 && operands[1] != const0_rtx
969 && can_create_pseudo_p ())
970 operands[1] = force_reg (SImode, operands[1]);
972 /* If we're generating PIC and have an incoming symbol, validize it to a
973 general operand or something that will match a special pattern.
975 FIXME: Do we *have* to recognize anything that would normally be a
976 valid symbol? Can we exclude global PIC addresses with an added
979 && CONSTANT_ADDRESS_P (operands[1])
980 && !cris_valid_pic_const (operands[1], false))
982 enum cris_pic_symbol_type t = cris_pic_symbol_type_of (operands[1]);
984 gcc_assert (t != cris_no_symbol);
986 if (! REG_S_P (operands[0]))
988 /* We must have a register as destination for what we're about to
989 do, and for the patterns we generate. */
990 CRIS_ASSERT (can_create_pseudo_p ());
991 operands[1] = force_reg (SImode, operands[1]);
995 /* FIXME: add a REG_EQUAL (or is it REG_EQUIV) note to the
996 destination register for the symbol. It might not be
997 worth it. Measure. */
998 current_function_uses_pic_offset_table = 1;
999 if (t == cris_rel_symbol)
1001 /* Change a "move.d sym(+offs),rN" into (allocate register rM)
1003 "move.d (const (plus (unspec [sym]
1004 CRIS_UNSPEC_GOTREL) offs)),rM" "add.d rPIC,rM,rN"
1006 "move.d (const (plus (unspec [sym]
1007 CRIS_UNSPEC_PCREL) offs)),rN". */
1008 rtx tem, rm, rn = operands[0];
1009 rtx sym = GET_CODE (operands[1]) != CONST
1010 ? operands[1] : get_related_value (operands[1]);
1011 HOST_WIDE_INT offs = get_integer_term (operands[1]);
1013 gcc_assert (can_create_pseudo_p ());
1017 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
1020 tem = plus_constant (tem, offs);
1022 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
1026 /* We still uses GOT-relative addressing for
1028 current_function_uses_pic_offset_table = 1;
1029 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
1030 CRIS_UNSPEC_GOTREL);
1032 tem = plus_constant (tem, offs);
1033 rm = gen_reg_rtx (Pmode);
1034 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
1035 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
1036 rn, 0, OPTAB_LIB_WIDEN) != rn)
1037 internal_error ("expand_binop failed in movsi gotrel");
1041 else if (t == cris_got_symbol)
1043 /* Change a "move.d sym,rN" into (allocate register rM, rO)
1044 "move.d (const (unspec [sym] CRIS_UNSPEC_GOTREAD)),rM"
1045 "add.d rPIC,rM,rO", "move.d [rO],rN" with
1046 the memory access marked as read-only. */
1047 rtx tem, mem, rm, ro, rn = operands[0];
1048 gcc_assert (can_create_pseudo_p ());
1049 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
1050 CRIS_UNSPEC_GOTREAD);
1051 rm = gen_reg_rtx (Pmode);
1052 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
1053 ro = gen_reg_rtx (Pmode);
1054 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
1055 ro, 0, OPTAB_LIB_WIDEN) != ro)
1056 internal_error ("expand_binop failed in movsi got");
1057 mem = gen_rtx_MEM (Pmode, ro);
1059 /* This MEM doesn't alias anything. Whether it
1060 aliases other same symbols is unimportant. */
1061 set_mem_alias_set (mem, new_alias_set ());
1062 MEM_NOTRAP_P (mem) = 1;
1064 /* We can set the GOT memory read of a non-called symbol
1065 to readonly, but not that of a call symbol, as those
1066 are subject to lazy evaluation and usually have the value
1067 changed from the first call to the second (but
1068 constant thereafter). */
1069 MEM_READONLY_P (mem) = 1;
1070 emit_move_insn (rn, mem);
1075 /* We get here when we have to change something that would
1076 be recognizable if it wasn't PIC. A ``sym'' is ok for
1077 PIC symbols both with and without a GOT entry. And ``sym
1078 + offset'' is ok for local symbols, so the only thing it
1079 could be, is a global symbol with an offset. Check and
1081 rtx reg = gen_reg_rtx (Pmode);
1082 rtx sym = get_related_value (operands[1]);
1083 HOST_WIDE_INT offs = get_integer_term (operands[1]);
1085 gcc_assert (can_create_pseudo_p ()
1086 && t == cris_got_symbol_needing_fixup
1087 && sym != NULL_RTX && offs != 0);
1089 emit_move_insn (reg, sym);
1090 if (expand_binop (SImode, add_optab, reg,
1091 GEN_INT (offs), operands[0], 0,
1092 OPTAB_LIB_WIDEN) != operands[0])
1093 internal_error ("expand_binop failed in movsi got+offs");
1100 (define_insn "*movsi_got_load"
1101 [(set (reg:SI CRIS_GOT_REGNUM) (unspec:SI [(const_int 0)] CRIS_UNSPEC_GOT))]
1105 ? "lapc _GLOBAL_OFFSET_TABLE_,%:"
1106 : "move.d $pc,%:\;sub.d .:GOTOFF,%:";
1108 [(set_attr "cc" "clobber")])
1110 (define_insn "*movsi_internal"
1112 (match_operand:SI 0 "nonimmediate_operand"
1113 "=r,r, r,Q>,r,Q>,g,r,r, r,g,rQ>,x, m,x")
1114 (match_operand:SI 1 "cris_general_operand_or_pic_source"
1115 "r,Q>,M,M, I,r, M,n,!S,g,r,x, rQ>,x,gi"))]
1116 ;; Note that we prefer not to use the S alternative (if for some reason
1117 ;; it competes with others) above, but g matches S.
1120 /* Better to have c-switch here; it is worth it to optimize the size of
1121 move insns. The alternative would be to try to find more constraint
1122 letters. FIXME: Check again. It seems this could shrink a bit. */
1123 switch (which_alternative)
1129 && (GET_CODE (operands[1]) == SYMBOL_REF
1130 || GET_CODE (operands[1]) == LABEL_REF
1131 || GET_CODE (operands[1]) == CONST))
1133 /* FIXME: Express this through (set_attr cc none) instead,
1134 since we can't express the ``none'' at this point. FIXME:
1135 Use lapc for everything except const_int and when next cc0
1136 user would want the flag setting. */
1138 return "lapc %1,%0";
1141 && GET_CODE (operands[1]) == CONST
1142 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
1143 && XINT (XEXP (operands[1], 0), 1) == CRIS_UNSPEC_GOTREAD)
1144 return "movu.w %1,%0";
1151 return "move.d %1,%0";
1157 return "move %d1,%0";
1162 return "clear.d %0";
1164 /* Constants -32..31 except 0. */
1166 return "moveq %1,%0";
1168 /* We can win a little on constants -32768..-33, 32..65535. */
1170 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536)
1172 if (INTVAL (operands[1]) < 256)
1173 return "movu.b %1,%0";
1174 return "movu.w %1,%0";
1176 else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768)
1178 if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128)
1179 return "movs.b %1,%0";
1180 return "movs.w %1,%0";
1182 return "move.d %1,%0";
1186 rtx tem = operands[1];
1187 gcc_assert (GET_CODE (tem) == CONST);
1188 tem = XEXP (tem, 0);
1189 if (GET_CODE (tem) == PLUS
1190 && GET_CODE (XEXP (tem, 0)) == UNSPEC
1191 && (XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL
1192 || XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_PCREL)
1193 && CONST_INT_P (XEXP (tem, 1)))
1194 tem = XEXP (tem, 0);
1195 gcc_assert (GET_CODE (tem) == UNSPEC);
1196 switch (XINT (tem, 1))
1198 case CRIS_UNSPEC_GOTREAD:
1199 case CRIS_UNSPEC_PLTGOTREAD:
1200 /* Using sign-extend mostly to be consistent with the
1201 indexed addressing mode. */
1203 return "movs.w %1,%0";
1204 return "move.d %1,%0";
1206 case CRIS_UNSPEC_GOTREL:
1207 case CRIS_UNSPEC_PLT_GOTREL:
1208 gcc_assert (!TARGET_V32);
1209 return "move.d %1,%0";
1211 case CRIS_UNSPEC_PCREL:
1212 case CRIS_UNSPEC_PLT_PCREL:
1213 gcc_assert (TARGET_V32);
1214 return "lapc %1,%0";
1221 return "BOGUS: %1 to %0";
1224 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no,yes,yes,no,no")
1225 (set_attr "cc" "*,*,*,*,*,*,*,*,*,*,*,none,none,none,none")])
1227 ;; Extend operations with side-effect from mem to register, using
1228 ;; MOVS/MOVU. These are from mem to register only.
1234 ;; FIXME: Can we omit extend to HImode, since GCC should truncate for
1235 ;; HImode by itself? Perhaps use only anonymous modes?
1237 (define_insn "*ext_sideqihi_biap"
1238 [(set (match_operand:HI 0 "register_operand" "=r,r")
1240 5 "cris_extend_operator"
1242 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1243 (match_operand:SI 2 "const_int_operand" "n,n"))
1244 (match_operand:SI 3 "register_operand" "r,r")))]))
1245 (set (match_operand:SI 4 "register_operand" "=*3,r")
1246 (plus:SI (mult:SI (match_dup 1)
1249 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1252 mov%e5.%m5 [%4=%3+%1%T2],%0")
1254 (define_insn "*ext_side<mode>si_biap"
1255 [(set (match_operand:SI 0 "register_operand" "=r,r")
1257 5 "cris_extend_operator"
1259 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1260 (match_operand:SI 2 "const_int_operand" "n,n"))
1261 (match_operand:SI 3 "register_operand" "r,r")))]))
1262 (set (match_operand:SI 4 "register_operand" "=*3,r")
1263 (plus:SI (mult:SI (match_dup 1)
1266 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1269 mov%e5<m> [%4=%3+%1%T2],%0")
1271 ;; Same but [rx=ry+i]
1275 (define_insn "*ext_sideqihi"
1276 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1278 4 "cris_extend_operator"
1280 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
1281 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1282 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
1283 (plus:SI (match_dup 1)
1285 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1287 if ((which_alternative == 0 || which_alternative == 3)
1288 && (!CONST_INT_P (operands[2])
1289 || INTVAL (operands[2]) > 127
1290 || INTVAL (operands[2]) < -128
1291 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1292 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1294 if (which_alternative == 4)
1295 return "mov%e4.%m4 [%3=%2%S1],%0";
1296 return "mov%e4.%m4 [%3=%1%S2],%0";
1299 (define_insn "*ext_side<mode>si"
1300 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
1302 4 "cris_extend_operator"
1304 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
1305 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1306 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
1307 (plus:SI (match_dup 1)
1309 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1311 if ((which_alternative == 0 || which_alternative == 3)
1312 && (!CONST_INT_P (operands[2])
1313 || INTVAL (operands[2]) > 127
1314 || INTVAL (operands[2]) < -128
1315 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1316 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1318 if (which_alternative == 4)
1319 return "mov%e4<m> [%3=%2%S1],%0";
1320 return "mov%e4<m> [%3=%1%S2],%0";
1323 ;; FIXME: See movsi.
1325 (define_insn "movhi"
1327 (match_operand:HI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,r,r,r,g,g,r,r,x")
1328 (match_operand:HI 1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g,x,r"))]
1331 switch (which_alternative)
1338 return "move.w %1,%0";
1341 return "move %1,%0";
1345 return "clear.w %0";
1347 return "moveq %1,%0";
1350 if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128)
1352 if (INTVAL (operands[1]) > 0)
1353 return "movu.b %1,%0";
1354 return "movs.b %1,%0";
1356 return "move.w %1,%0";
1358 return "movEq %b1,%0";
1360 return "BOGUS: %1 to %0";
1363 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no,yes,yes")
1364 (set_attr "cc" "*,*,none,none,*,none,*,clobber,*,none,none,*,none,none")])
1366 (define_insn "movstricthi"
1369 (match_operand:HI 0 "nonimmediate_operand" "+r,r, r,Q>,Q>,g,r,g"))
1370 (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, M,g,r"))]
1381 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1383 (define_expand "reload_in<mode>"
1384 [(set (match_operand:BW 2 "register_operand" "=r")
1385 (match_operand:BW 1 "memory_operand" "m"))
1386 (set (match_operand:BW 0 "register_operand" "=x")
1391 (define_expand "reload_out<mode>"
1392 [(set (match_operand:BW 2 "register_operand" "=&r")
1393 (match_operand:BW 1 "register_operand" "x"))
1394 (set (match_operand:BW 0 "memory_operand" "=m")
1399 (define_insn "movqi"
1400 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,r,g,g,r,r,r,x")
1401 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, I,M,r,O,g,x,r"))]
1416 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no,yes,yes")
1417 (set_attr "cc" "*,*,*,*,*,*,*,*,clobber,*,none,none")])
1419 (define_insn "movstrictqi"
1420 [(set (strict_low_part
1421 (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r, r,Q>,g,g,r"))
1422 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, M,r,g"))]
1433 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1435 ;; The valid "quick" bit-patterns are, except for 0.0, denormalized
1436 ;; values REALLY close to 0, and some NaN:s (I think; their exponent is
1437 ;; all ones); the worthwhile one is "0.0".
1438 ;; It will use clear, so we know ALL types of immediate 0 never change cc.
1440 (define_insn "movsf"
1441 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,g,g,r,r,x,Q>,m,x, x")
1442 (match_operand:SF 1 "general_operand" "r,r, Q>,G,G, G,r,g,x,r,x, x,Q>,g"))]
1459 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no,yes,yes,yes,no,yes,no")])
1461 ;; Movem patterns. Primarily for use in function prologue and epilogue.
1462 ;; The V32 variants have an ordering matching the expectations of the
1463 ;; standard names "load_multiple" and "store_multiple"; pre-v32 movem
1464 ;; store R0 in the highest memory location.
1466 (define_expand "load_multiple"
1467 [(match_operand:SI 0 "register_operand" "")
1468 (match_operand:SI 1 "memory_operand" "")
1469 (match_operand:SI 2 "const_int_operand" "")]
1474 /* Apparently the predicate isn't checked, so we need to do so
1475 manually. Once happened for libstdc++-v3 locale_facets.tcc. */
1476 if (!MEM_P (operands[1]))
1479 indreg = XEXP (operands[1], 0);
1481 if (GET_CODE (indreg) == POST_INC)
1482 indreg = XEXP (indreg, 0);
1484 || GET_CODE (operands[2]) != CONST_INT
1485 || !REG_P (operands[0])
1486 || REGNO (operands[0]) != 0
1487 || INTVAL (operands[2]) > CRIS_SP_REGNUM
1488 || (int) REGNO (indreg) < INTVAL (operands[2]))
1491 emit_insn (cris_gen_movem_load (operands[1], operands[2], 0));
1495 (define_expand "store_multiple"
1496 [(match_operand:SI 0 "memory_operand" "")
1497 (match_operand:SI 1 "register_operand" "")
1498 (match_operand:SI 2 "const_int_operand" "")]
1503 /* See load_multiple. */
1504 if (!MEM_P (operands[0]))
1507 indreg = XEXP (operands[0], 0);
1509 if (GET_CODE (indreg) == POST_INC)
1510 indreg = XEXP (indreg, 0);
1512 || GET_CODE (operands[2]) != CONST_INT
1513 || !REG_P (operands[1])
1514 || REGNO (operands[1]) != 0
1515 || INTVAL (operands[2]) > CRIS_SP_REGNUM
1516 || (int) REGNO (indreg) < INTVAL (operands[2]))
1519 cris_emit_movem_store (operands[0], operands[2], 0, false);
1523 (define_insn "*cris_load_multiple"
1524 [(match_parallel 0 "cris_load_multiple_op"
1525 [(set (match_operand:SI 1 "register_operand" "=r,r")
1526 (match_operand:SI 2 "memory_operand" "Q,m"))])]
1529 [(set_attr "cc" "none")
1530 (set_attr "slottable" "yes,no")
1531 ;; Not true, but setting the length to 0 causes return sequences (ret
1532 ;; movem) to have the cost they had when (return) included the movem
1533 ;; and reduces the performance penalty taken for needing to emit an
1534 ;; epilogue (in turn copied by bb-reorder) instead of return patterns.
1535 ;; FIXME: temporary change until all insn lengths are correctly
1536 ;; described. FIXME: have better target control over bb-reorder.
1537 (set_attr "length" "0")])
1539 (define_insn "*cris_store_multiple"
1540 [(match_parallel 0 "cris_store_multiple_op"
1541 [(set (match_operand:SI 2 "memory_operand" "=Q,m")
1542 (match_operand:SI 1 "register_operand" "r,r"))])]
1545 [(set_attr "cc" "none")
1546 (set_attr "slottable" "yes,no")])
1549 ;; Sign- and zero-extend insns with standard names.
1550 ;; Those for integer source operand are ordered with the widest source
1555 (define_insn "extendsidi2"
1556 [(set (match_operand:DI 0 "register_operand" "=r")
1557 (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
1559 "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0")
1561 (define_insn "extend<mode>di2"
1562 [(set (match_operand:DI 0 "register_operand" "=r")
1563 (sign_extend:DI (match_operand:BW 1 "general_operand" "g")))]
1565 "movs<m> %1,%M0\;smi %H0\;neg.d %H0,%H0")
1567 (define_insn "extend<mode>si2"
1568 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1569 (sign_extend:SI (match_operand:BW 1 "general_operand" "r,Q>,g")))]
1572 [(set_attr "slottable" "yes,yes,no")])
1574 ;; To do a byte->word extension, extend to dword, exept that the top half
1575 ;; of the register will be clobbered. FIXME: Perhaps this is not needed.
1577 (define_insn "extendqihi2"
1578 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1579 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))]
1582 [(set_attr "slottable" "yes,yes,no")])
1585 ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't
1586 ;; specify them here.
1588 (define_insn "zero_extend<mode>si2"
1589 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1591 (match_operand:BW 1 "nonimmediate_operand" "r,Q>,m")))]
1594 [(set_attr "slottable" "yes,yes,no")])
1596 ;; Same comment as sign-extend QImode to HImode above applies.
1598 (define_insn "zero_extendqihi2"
1599 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1601 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))]
1604 [(set_attr "slottable" "yes,yes,no")])
1606 ;; All kinds of arithmetic and logical instructions.
1608 ;; First, anonymous patterns to match addressing modes with
1611 ;; op.S [rx=ry+I],rz; (add, sub, or, and, bound).
1615 (define_insn "*op_side<mode>_biap"
1616 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1618 6 "cris_orthogonal_operator"
1619 [(match_operand:BWD 1 "register_operand" "0,0")
1621 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1622 (match_operand:SI 3 "const_int_operand" "n,n"))
1623 (match_operand:SI 4 "register_operand" "r,r")))]))
1624 (set (match_operand:SI 5 "register_operand" "=*4,r")
1625 (plus:SI (mult:SI (match_dup 2)
1628 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1631 %x6<m> [%5=%4+%2%T3],%0")
1633 ;; [rx=ry+i] ([%4=%2+%3])
1635 (define_insn "*op_side<mode>"
1636 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r")
1638 5 "cris_orthogonal_operator"
1639 [(match_operand:BWD 1 "register_operand" "0,0,0,0,0")
1641 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1642 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1643 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1644 (plus:SI (match_dup 2)
1646 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1648 if ((which_alternative == 0 || which_alternative == 3)
1649 && (!CONST_INT_P (operands[3])
1650 || INTVAL (operands[3]) > 127
1651 || INTVAL (operands[3]) < -128
1652 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1653 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1655 if (which_alternative == 4)
1656 return "%x5.%s0 [%4=%3%S2],%0";
1657 return "%x5<m> [%4=%2%S3],%0";
1660 ;; To match all cases for commutative operations we may have to have the
1661 ;; following pattern for add, or & and. I do not know really, but it does
1662 ;; not break anything.
1664 ;; FIXME: This really ought to be checked.
1666 ;; op.S [rx=ry+I],rz;
1670 (define_insn "*op_swap_side<mode>_biap"
1671 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1673 6 "cris_commutative_orth_op"
1675 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1676 (match_operand:SI 3 "const_int_operand" "n,n"))
1677 (match_operand:SI 4 "register_operand" "r,r")))
1678 (match_operand:BWD 1 "register_operand" "0,0")]))
1679 (set (match_operand:SI 5 "register_operand" "=*4,r")
1680 (plus:SI (mult:SI (match_dup 2)
1683 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1686 %x6<m> [%5=%4+%2%T3],%0")
1688 ;; [rx=ry+i] ([%4=%2+%3])
1689 ;; FIXME: These could have anonymous mode for operand 0.
1693 (define_insn "*op_swap_side<mode>"
1694 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r")
1696 5 "cris_commutative_orth_op"
1698 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1699 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
1700 (match_operand:BWD 1 "register_operand" "0,0,0,0,0")]))
1701 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1702 (plus:SI (match_dup 2)
1704 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1706 if ((which_alternative == 0 || which_alternative == 3)
1707 && (!CONST_INT_P (operands[3])
1708 || INTVAL (operands[3]) > 127
1709 || INTVAL (operands[3]) < -128
1710 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1711 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1713 if (which_alternative == 4)
1714 return "%x5<m> [%4=%3%S2],%0";
1715 return "%x5<m> [%4=%2%S3],%0";
1718 ;; Add operations, standard names.
1720 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1721 ;; output the insn through the 'A' output modifier as "adds.w" and "addq",
1723 (define_expand "adddi3"
1724 [(set (match_operand:DI 0 "register_operand")
1725 (plus:DI (match_operand:DI 1 "register_operand")
1726 (match_operand:DI 2 "general_operand")))]
1729 if (MEM_P (operands[2]) && TARGET_V32)
1730 operands[2] = force_reg (DImode, operands[2]);
1733 (define_insn "*adddi3_non_v32"
1734 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1735 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r")
1736 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1739 addq %2,%M0\;ax\;addq 0,%H0
1740 subq %n2,%M0\;ax\;subq 0,%H0
1741 add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0
1742 add.d %M2,%M0\;ax\;add.d %H2,%H0
1743 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
1745 ; It seems no use allowing a memory operand for this one, because we'd
1746 ; need a scratch register for incrementing the address.
1747 (define_insn "*adddi3_v32"
1748 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1749 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0")
1750 (match_operand:DI 2 "nonmemory_operand" "J,N,P,r,n")))]
1753 addq %2,%M0\;addc 0,%H0
1754 subq %n2,%M0\;ax\;subq 0,%H0
1755 add%e2.%z2 %2,%M0\;addc %H2,%H0
1756 add.d %M2,%M0\;addc %H2,%H0
1757 add.d %M2,%M0\;addc %H2,%H0")
1759 (define_expand "add<mode>3"
1760 [(set (match_operand:BWD 0 "register_operand")
1762 (match_operand:BWD 1 "register_operand")
1763 (match_operand:BWD 2 "general_operand")))]
1767 (define_insn "*addsi3_non_v32"
1768 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r, r,r, r")
1770 (match_operand:SI 1 "register_operand" "%0,0, 0,0,0,0, 0,r, r")
1771 (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,!S,g,!To,0")))]
1773 ;; The last constraint is due to that after reload, the '%' is not
1774 ;; honored, and canonicalization doesn't care about keeping the same
1775 ;; register as in destination. This will happen after insn splitting.
1776 ;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x
1780 switch (which_alternative)
1784 return "add.d %2,%0";
1786 return "addq %2,%0";
1788 return "subq %n2,%0";
1790 /* 'Known value', but not in -63..63.
1791 Check if addu/subu may be used. */
1792 if (INTVAL (operands[2]) > 0)
1794 if (INTVAL (operands[2]) < 256)
1795 return "addu.b %2,%0";
1796 if (INTVAL (operands[2]) < 65536)
1797 return "addu.w %2,%0";
1801 if (INTVAL (operands[2]) >= -255)
1802 return "subu.b %n2,%0";
1803 if (INTVAL (operands[2]) >= -65535)
1804 return "subu.w %n2,%0";
1806 return "add.d %2,%0";
1809 rtx tem = operands[2];
1810 gcc_assert (GET_CODE (tem) == CONST);
1811 tem = XEXP (tem, 0);
1812 if (GET_CODE (tem) == PLUS
1813 && GET_CODE (XEXP (tem, 0)) == UNSPEC
1814 /* We don't allow CRIS_UNSPEC_PCREL here; we can't have a
1815 pc-relative operand in an add insn. */
1816 && XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL
1817 && CONST_INT_P (XEXP (tem, 1)))
1818 tem = XEXP (tem, 0);
1819 gcc_assert (GET_CODE (tem) == UNSPEC);
1820 switch (XINT (tem, 1))
1822 case CRIS_UNSPEC_GOTREAD:
1823 case CRIS_UNSPEC_PLTGOTREAD:
1824 /* Using sign-extend mostly to be consistent with the
1825 indexed addressing mode. */
1827 return "adds.w %2,%0";
1828 return "add.d %2,%0";
1830 case CRIS_UNSPEC_PLT_GOTREL:
1831 case CRIS_UNSPEC_GOTREL:
1832 return "add.d %2,%0";
1838 return "add%u2 %2,%0";
1840 return "add.d %2,%1,%0";
1842 return "add.d %1,%0";
1844 return "BOGUS addsi %2+%1 to %0";
1847 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no,yes")])
1849 ; FIXME: Check what's best: having the three-operand ACR alternative
1850 ; before or after the corresponding-operand2 alternative. Check for
1851 ; *all* insns. FIXME: constant constraint letter for -128..127.
1852 (define_insn "*addsi3_v32"
1853 [(set (match_operand:SI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,!a,r,r,r,!a")
1855 (match_operand:SI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r, 0,0,0,r")
1856 (match_operand:SI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,L,L, P,n,g,g")))]
1872 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no,no,no,no,no")
1873 (set_attr "cc" "*,none,*,none,*,*,none,*,*,*,*,*,none")])
1875 (define_insn "*addhi3_non_v32"
1876 [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r")
1877 (plus:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
1878 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1887 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1888 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1890 (define_insn "*addhi3_v32"
1891 [(set (match_operand:HI 0 "register_operand" "=r, !a,r,!a, r,r,!a,r,!a")
1893 (match_operand:HI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r")
1894 (match_operand:HI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,g,g")))]
1906 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no")
1907 (set_attr "cc" "*,none,*,none,clobber,clobber,none,*,none")])
1909 (define_insn "*addqi3_non_v32"
1910 [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r,r")
1911 (plus:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,0,0,r")
1912 (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))]
1922 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
1923 (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")])
1925 (define_insn "*addqi3_v32"
1926 [(set (match_operand:QI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,r,!a")
1928 (match_operand:QI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,0,r")
1929 (match_operand:QI 2 "general_operand" "r,r, Q>,Q>,J,N,NJ,O,g,g")))]
1942 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,yes,no,no")
1943 (set_attr "cc" "*,none,*,none,clobber,clobber,none,clobber,*,none")])
1947 ;; Note that because of insn canonicalization these will *seldom* but
1948 ;; rarely be used with a known constant as an operand.
1950 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1951 ;; output the insn through the 'D' output modifier as "subs.w" and "subq",
1953 (define_expand "subdi3"
1954 [(set (match_operand:DI 0 "register_operand")
1955 (minus:DI (match_operand:DI 1 "register_operand")
1956 (match_operand:DI 2 "general_operand")))]
1959 if (TARGET_V32 && MEM_P (operands[2]))
1960 operands[2] = force_reg (DImode, operands[2]);
1963 (define_insn "*subdi3_non_v32"
1964 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1965 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r")
1966 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1969 subq %2,%M0\;ax\;subq 0,%H0
1970 addq %n2,%M0\;ax\;addq 0,%H0
1971 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1972 sub.d %M2,%M0\;ax\;sub.d %H2,%H0
1973 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
1975 (define_insn "*subdi3_v32"
1976 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r")
1977 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0")
1978 (match_operand:DI 2 "nonmemory_operand" "J,N,P,r")))]
1981 subq %2,%M0\;ax\;subq 0,%H0
1982 addq %n2,%M0\;ax\;addq 0,%H0
1983 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1984 sub.d %M2,%M0\;ax\;sub.d %H2,%H0")
1986 (define_expand "sub<mode>3"
1987 [(set (match_operand:BWD 0 "register_operand")
1989 (match_operand:BWD 1 "register_operand")
1990 (match_operand:BWD 2 "general_operand")))]
1994 (define_insn "*subsi3_non_v32"
1995 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r,r")
1997 (match_operand:SI 1 "register_operand" "0,0, 0,0,0,0,0,r")
1998 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
2001 ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
2002 ;; But then again, %2 should not be negative.
2013 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
2015 (define_insn "*subsi3_v32"
2016 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
2018 (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0")
2019 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g")))]
2029 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")])
2031 (define_insn "*sub<mode>3_nonv32"
2032 [(set (match_operand:BW 0 "register_operand" "=r,r, r,r,r,r")
2033 (minus:BW (match_operand:BW 1 "register_operand" "0,0, 0,0,0,r")
2034 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g,!To")))]
2043 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2044 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
2046 (define_insn "*sub<mode>3_v32"
2047 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r")
2048 (minus:BW (match_operand:BW 1 "register_operand" "0,0,0,0,0")
2049 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g")))]
2057 [(set_attr "slottable" "yes,yes,yes,yes,no")
2058 (set_attr "cc" "normal,normal,clobber,clobber,normal")])
2060 ;; CRIS has some add/sub-with-sign/zero-extend instructions.
2061 ;; Although these perform sign/zero-extension to SImode, they are
2062 ;; equally applicable for the HImode case.
2063 ;; FIXME: Check; GCC should handle the widening.
2064 ;; Note that these must be located after the normal add/sub patterns,
2065 ;; so not to get constants into any less specific operands.
2067 ;; Extend with add/sub and side-effect.
2069 ;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend
2071 ;; adds/subs/addu/subu bound [rx=ry+rz.S]
2074 ;; FIXME: GCC should widen.
2076 (define_insn "*extopqihi_side_biap"
2077 [(set (match_operand:HI 0 "register_operand" "=r,r")
2079 6 "cris_additive_operand_extend_operator"
2080 [(match_operand:HI 1 "register_operand" "0,0")
2082 7 "cris_extend_operator"
2084 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2085 (match_operand:SI 3 "const_int_operand" "n,n"))
2086 (match_operand:SI 4 "register_operand" "r,r")))])]))
2087 (set (match_operand:SI 5 "register_operand" "=*4,r")
2088 (plus:SI (mult:SI (match_dup 2)
2091 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2094 %x6%e7.%m7 [%5=%4+%2%T3],%0")
2096 (define_insn "*extop<mode>si_side_biap"
2097 [(set (match_operand:SI 0 "register_operand" "=r,r")
2099 6 "cris_operand_extend_operator"
2100 [(match_operand:SI 1 "register_operand" "0,0")
2102 7 "cris_extend_operator"
2104 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2105 (match_operand:SI 3 "const_int_operand" "n,n"))
2106 (match_operand:SI 4 "register_operand" "r,r")))])]))
2107 (set (match_operand:SI 5 "register_operand" "=*4,r")
2108 (plus:SI (mult:SI (match_dup 2)
2111 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
2112 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2115 %x6%e7<m> [%5=%4+%2%T3],%0")
2122 (define_insn "*extopqihi_side"
2123 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
2125 5 "cris_additive_operand_extend_operator"
2126 [(match_operand:HI 1 "register_operand" "0,0,0,0,0")
2128 6 "cris_extend_operator"
2130 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2131 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
2133 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2134 (plus:SI (match_dup 2)
2136 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2138 if ((which_alternative == 0 || which_alternative == 3)
2139 && (!CONST_INT_P (operands[3])
2140 || INTVAL (operands[3]) > 127
2141 || INTVAL (operands[3]) < -128
2142 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2143 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2145 if (which_alternative == 4)
2146 return "%x5%E6.%m6 [%4=%3%S2],%0";
2147 return "%x5%E6.%m6 [%4=%2%S3],%0";
2150 (define_insn "*extop<mode>si_side"
2151 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
2153 5 "cris_operand_extend_operator"
2154 [(match_operand:SI 1 "register_operand" "0,0,0,0,0")
2156 6 "cris_extend_operator"
2158 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2159 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
2161 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2162 (plus:SI (match_dup 2)
2164 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2165 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2167 if ((which_alternative == 0 || which_alternative == 3)
2168 && (!CONST_INT_P (operands[3])
2169 || INTVAL (operands[3]) > 127
2170 || INTVAL (operands[3]) < -128
2171 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2172 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2174 if (which_alternative == 4)
2175 return "%x5%E6<m> [%4=%3%S2],%0";
2176 return "%x5%E6<m> [%4=%2%S3],%0";
2180 ;; As with op.S we may have to add special pattern to match commuted
2181 ;; operands to adds/addu and bound
2183 ;; adds/addu/bound [rx=ry+rz.S]
2186 ;; FIXME: GCC should widen.
2188 (define_insn "*extopqihi_swap_side_biap"
2189 [(set (match_operand:HI 0 "register_operand" "=r,r")
2192 6 "cris_extend_operator"
2194 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2195 (match_operand:SI 3 "const_int_operand" "n,n"))
2196 (match_operand:SI 4 "register_operand" "r,r")))])
2197 (match_operand:HI 1 "register_operand" "0,0")))
2198 (set (match_operand:SI 5 "register_operand" "=*4,r")
2199 (plus:SI (mult:SI (match_dup 2)
2202 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2205 add%e6.b [%5=%4+%2%T3],%0")
2207 (define_insn "*extop<mode>si_swap_side_biap"
2208 [(set (match_operand:SI 0 "register_operand" "=r,r")
2210 7 "cris_plus_or_bound_operator"
2212 6 "cris_extend_operator"
2214 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2215 (match_operand:SI 3 "const_int_operand" "n,n"))
2216 (match_operand:SI 4 "register_operand" "r,r")))])
2217 (match_operand:SI 1 "register_operand" "0,0")]))
2218 (set (match_operand:SI 5 "register_operand" "=*4,r")
2219 (plus:SI (mult:SI (match_dup 2)
2222 "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2223 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2226 %x7%E6<m> [%5=%4+%2%T3],%0")
2229 ;; FIXME: GCC should widen.
2233 (define_insn "*extopqihi_swap_side"
2234 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
2237 5 "cris_extend_operator"
2239 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2240 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
2241 (match_operand:HI 1 "register_operand" "0,0,0,0,0")))
2242 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2243 (plus:SI (match_dup 2)
2245 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2247 if ((which_alternative == 0 || which_alternative == 3)
2248 && (!CONST_INT_P (operands[3])
2249 || INTVAL (operands[3]) > 127
2250 || INTVAL (operands[3]) < -128
2251 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2252 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2254 if (which_alternative == 4)
2255 return "add%e5.b [%4=%3%S2],%0";
2256 return "add%e5.b [%4=%2%S3],%0";
2259 (define_insn "*extop<mode>si_swap_side"
2260 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
2262 6 "cris_plus_or_bound_operator"
2264 5 "cris_extend_operator"
2266 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2267 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
2268 (match_operand:SI 1 "register_operand" "0,0,0,0,0")]))
2269 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2270 (plus:SI (match_dup 2)
2272 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
2273 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2275 if ((which_alternative == 0 || which_alternative == 3)
2276 && (!CONST_INT_P (operands[3])
2277 || INTVAL (operands[3]) > 127
2278 || INTVAL (operands[3]) < -128
2279 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2280 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2282 if (which_alternative == 4)
2283 return \"%x6%E5.%m5 [%4=%3%S2],%0\";
2284 return "%x6%E5<m> [%4=%2%S3],%0";
2287 ;; Extend versions (zero/sign) of normal add/sub (no side-effects).
2290 ;; FIXME: GCC should widen.
2292 (define_insn "*extopqihi_non_v32"
2293 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2295 3 "cris_additive_operand_extend_operator"
2296 [(match_operand:HI 1 "register_operand" "0,0,0,r")
2298 4 "cris_extend_operator"
2299 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2300 "!TARGET_V32 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2301 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2306 %x3%E4.%m4 %2,%1,%0"
2307 [(set_attr "slottable" "yes,yes,no,no")
2308 (set_attr "cc" "clobber")])
2310 (define_insn "*extopqihi_v32"
2311 [(set (match_operand:HI 0 "register_operand" "=r,r")
2313 3 "cris_additive_operand_extend_operator"
2314 [(match_operand:HI 1 "register_operand" "0,0")
2316 4 "cris_extend_operator"
2317 [(match_operand:QI 2 "nonimmediate_operand" "r,m")])]))]
2320 [(set_attr "slottable" "yes")
2321 (set_attr "cc" "clobber")])
2325 (define_insn "*extop<mode>si_non_v32"
2326 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2328 3 "cris_operand_extend_operator"
2329 [(match_operand:SI 1 "register_operand" "0,0,0,r")
2331 4 "cris_extend_operator"
2332 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2334 && (GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2335 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2336 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2342 [(set_attr "slottable" "yes,yes,no,no")])
2344 (define_insn "*extop<mode>si_v32"
2345 [(set (match_operand:SI 0 "register_operand" "=r,r")
2347 3 "cris_additive_operand_extend_operator"
2348 [(match_operand:SI 1 "register_operand" "0,0")
2350 4 "cris_extend_operator"
2351 [(match_operand:BW 2 "nonimmediate_operand" "r,m")])]))]
2354 [(set_attr "slottable" "yes")])
2356 ;; As with the side-effect patterns, may have to have swapped operands for add.
2357 ;; For commutative operands, these are the canonical forms.
2361 (define_insn "*addxqihi_swap_non_v32"
2362 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2365 3 "cris_extend_operator"
2366 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2367 (match_operand:HI 1 "register_operand" "0,0,0,r")))]
2368 "!TARGET_V32 && operands[1] != frame_pointer_rtx"
2374 [(set_attr "slottable" "yes,yes,no,no")
2375 (set_attr "cc" "clobber")])
2377 ;; A case for v32, to catch the "addo" insn in addition to "adds". We
2378 ;; only care to match the canonical form; there should be no other.
2380 (define_insn "*addsbw_v32"
2381 [(set (match_operand:HI 0 "register_operand" "=r,r,!a")
2384 (match_operand:QI 2 "nonimmediate_operand" "r,m,m"))
2385 (match_operand:HI 1 "register_operand" "0,0,r")))]
2391 [(set_attr "slottable" "yes")
2392 (set_attr "cc" "clobber,clobber,none")])
2394 (define_insn "*addubw_v32"
2395 [(set (match_operand:HI 0 "register_operand" "=r,r")
2398 (match_operand:QI 2 "nonimmediate_operand" "r,m"))
2399 (match_operand:HI 1 "register_operand" "0,0")))]
2402 [(set_attr "slottable" "yes")
2403 (set_attr "cc" "clobber")])
2405 (define_insn "*extop<mode>si_swap_non_v32"
2406 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2408 4 "cris_plus_or_bound_operator"
2410 3 "cris_extend_operator"
2411 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])
2412 (match_operand:SI 1 "register_operand" "0,0,0,r")]))]
2414 && (GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND)
2415 && operands[1] != frame_pointer_rtx"
2421 [(set_attr "slottable" "yes,yes,no,no")])
2423 (define_insn "*adds<mode>_v32"
2424 [(set (match_operand:SI 0 "register_operand" "=r,r,!a")
2427 (match_operand:BW 2 "nonimmediate_operand" "r,m,m"))
2428 (match_operand:SI 1 "register_operand" "0,0,r")))]
2434 [(set_attr "slottable" "yes")
2435 (set_attr "cc" "*,*,none")])
2437 (define_insn "*addu<mode>_v32"
2438 [(set (match_operand:SI 0 "register_operand" "=r,r")
2441 (match_operand:BW 2 "nonimmediate_operand" "r,m"))
2442 (match_operand:SI 1 "register_operand" "0,0")))]
2443 "TARGET_V32 && operands[1] != frame_pointer_rtx"
2445 [(set_attr "slottable" "yes")])
2447 (define_insn "*bound<mode>_v32"
2448 [(set (match_operand:SI 0 "register_operand" "=r")
2451 (match_operand:BW 2 "register_operand" "r"))
2452 (match_operand:SI 1 "register_operand" "0")))]
2453 "TARGET_V32 && operands[1] != frame_pointer_rtx"
2455 [(set_attr "slottable" "yes")])
2457 ;; This is the special case when we use what corresponds to the
2458 ;; instruction above in "casesi". Do *not* change it to use the generic
2459 ;; pattern and "REG 15" as pc; I did that and it led to madness and
2460 ;; maintenance problems: Instead of (as imagined) recognizing and removing
2461 ;; or replacing this pattern with something simpler, other variant
2462 ;; patterns were recognized or combined, including some prefix variants
2463 ;; where the value in pc is not that of the next instruction (which means
2464 ;; this instruction actually *is* special and *should* be marked as such).
2465 ;; When switching from the "generic pattern match" approach to this simpler
2466 ;; approach, there were insignificant differences in gcc, ipps and
2467 ;; product code, somehow due to scratching reload behind the ear or
2468 ;; something. Testcase "gcc" looked .01% slower and 4 bytes bigger;
2469 ;; product code became .001% smaller but "looked better". The testcase
2470 ;; "ipps" was just different at register allocation).
2472 ;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this
2473 ;; pattern with the default-label as the else, with the "if" being
2474 ;; index-is-less-than the max number of cases plus one. The default-label
2475 ;; is attached to the end of the case-table at time of output.
2477 (define_insn "*casesi_adds_w"
2480 (ltu (match_operand:SI 0 "register_operand" "r")
2481 (match_operand:SI 1 "const_int_operand" "n"))
2482 (plus:SI (sign_extend:SI
2484 (plus:SI (mult:SI (match_dup 0) (const_int 2))
2487 (label_ref (match_operand 2 "" ""))))
2488 (use (label_ref (match_operand 3 "" "")))]
2489 "!TARGET_V32 && operands[0] != frame_pointer_rtx"
2490 "adds.w [$pc+%0.w],$pc"
2491 [(set_attr "cc" "clobber")])
2493 ;; For V32, we just have a jump, but we need to mark the table as used,
2494 ;; and the jump insn must have the if_then_else form expected by core
2495 ;; GCC. Since we don't want to prolong the lifetime of the original
2496 ;; index value, we compare against "unspec 0". It's a pity we have to
2497 ;; jump through to get the default label in place and to keep the jump
2498 ;; table around. FIXME: Look into it some time.
2500 (define_insn "*casesi_jump_v32"
2503 (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI)
2504 (match_operand:SI 0 "const_int_operand" "n"))
2505 (match_operand:SI 1 "register_operand" "r")
2506 (label_ref (match_operand 2 "" ""))))
2507 (use (label_ref (match_operand 3 "" "")))]
2510 [(set_attr "cc" "clobber")
2511 (set_attr "slottable" "has_slot")])
2513 ;; Multiply instructions.
2515 ;; Sometimes powers of 2 (which are normally canonicalized to a
2516 ;; left-shift) appear here, as a result of address reloading.
2517 ;; As a special, for values 3 and 5, we can match with an addi, so add those.
2519 ;; FIXME: This may be unnecessary now.
2520 ;; Explicitly named for convenience of having a gen_... function.
2522 (define_insn "addi_mul"
2523 [(set (match_operand:SI 0 "register_operand" "=r")
2525 (match_operand:SI 1 "register_operand" "%0")
2526 (match_operand:SI 2 "const_int_operand" "n")))]
2527 "operands[0] != frame_pointer_rtx
2528 && operands[1] != frame_pointer_rtx
2529 && CONST_INT_P (operands[2])
2530 && (INTVAL (operands[2]) == 2
2531 || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3
2532 || INTVAL (operands[2]) == 5)"
2534 if (INTVAL (operands[2]) == 2)
2536 else if (INTVAL (operands[2]) == 4)
2538 else if (INTVAL (operands[2]) == 3)
2539 return "addi %0.w,%0";
2540 else if (INTVAL (operands[2]) == 5)
2541 return "addi %0.d,%0";
2542 return "BAD: adr_mulsi: %0=%1*%2";
2544 [(set_attr "slottable" "yes")
2545 ;; No flags are changed if this insn is "addi", but it does not seem
2546 ;; worth the trouble to distinguish that to the lslq cases.
2547 (set_attr "cc" "clobber")])
2549 ;; The addi insn as it is normally used.
2551 ;; Make the the ACR alternative taste bad enough to not choose it as a
2552 ;; preference to avoid spilling problems (unwind-dw2-fde.c at build).
2553 ;; FIXME: Revisit for new register allocator.
2555 (define_insn "*addi"
2556 [(set (match_operand:SI 0 "register_operand" "=r,!a")
2558 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2559 (match_operand:SI 3 "const_int_operand" "n,n"))
2560 (match_operand:SI 1 "register_operand" "0,r")))]
2561 "operands[0] != frame_pointer_rtx
2562 && operands[1] != frame_pointer_rtx
2563 && CONST_INT_P (operands[3])
2564 && (INTVAL (operands[3]) == 1
2565 || INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)"
2569 [(set_attr "slottable" "yes")
2570 (set_attr "cc" "none")])
2572 ;; The mstep instruction. Probably not useful by itself; it's to
2573 ;; non-linear wrt. the other insns. We used to expand to it, so at least
2576 (define_insn "mstep_shift"
2577 [(set (match_operand:SI 0 "register_operand" "=r")
2579 (lt:SI (cc0) (const_int 0))
2580 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2582 (match_operand:SI 2 "register_operand" "r"))
2583 (ashift:SI (match_operand:SI 3 "register_operand" "0")
2587 [(set_attr "slottable" "yes")])
2589 ;; When illegitimate addresses are legitimized, sometimes gcc forgets
2590 ;; to canonicalize the multiplications.
2592 ;; FIXME: Check gcc > 2.7.2, remove and possibly fix in gcc.
2594 (define_insn "mstep_mul"
2595 [(set (match_operand:SI 0 "register_operand" "=r")
2597 (lt:SI (cc0) (const_int 0))
2598 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2600 (match_operand:SI 2 "register_operand" "r"))
2601 (mult:SI (match_operand:SI 3 "register_operand" "0")
2604 && operands[0] != frame_pointer_rtx
2605 && operands[1] != frame_pointer_rtx
2606 && operands[2] != frame_pointer_rtx
2607 && operands[3] != frame_pointer_rtx"
2609 [(set_attr "slottable" "yes")])
2611 (define_insn "<u>mul<s><mode>3"
2612 [(set (match_operand:WD 0 "register_operand" "=r")
2614 (szext:WD (match_operand:<S> 1 "register_operand" "%0"))
2615 (szext:WD (match_operand:<S> 2 "register_operand" "r"))))
2616 (clobber (match_scratch:SI 3 "=h"))]
2617 "TARGET_HAS_MUL_INSNS"
2618 "%!mul<su><mm> %2,%0"
2619 [(set (attr "slottable")
2620 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
2622 (const_string "yes")))
2623 ;; For umuls.[bwd] it's just N unusable here, but let's be safe.
2624 ;; For muls.b, this really extends to SImode, so cc should be
2625 ;; considered clobbered.
2626 ;; For muls.w, it's just N unusable here, but let's be safe.
2627 (set_attr "cc" "clobber")])
2629 ;; Note that gcc does not make use of such a thing as umulqisi3. It gets
2630 ;; confused and will erroneously use it instead of umulhisi3, failing (at
2631 ;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels.
2632 ;; Inspection of optab code shows that there must be only one widening
2633 ;; multiplication per mode widened to.
2635 (define_insn "mulsi3"
2636 [(set (match_operand:SI 0 "register_operand" "=r")
2637 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2638 (match_operand:SI 2 "register_operand" "r")))
2639 (clobber (match_scratch:SI 3 "=h"))]
2640 "TARGET_HAS_MUL_INSNS"
2642 [(set (attr "slottable")
2643 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
2645 (const_string "yes")))
2646 ;; Just N unusable here, but let's be safe.
2647 (set_attr "cc" "clobber")])
2649 ;; A few multiply variations.
2651 ;; When needed, we can get the high 32 bits from the overflow
2652 ;; register. We don't care to split and optimize these.
2654 ;; Note that cc0 is still valid after the move-from-overflow-register
2655 ;; insn; no special precaution need to be taken in cris_notice_update_cc.
2657 (define_insn "<u>mulsidi3"
2658 [(set (match_operand:DI 0 "register_operand" "=r")
2660 (szext:DI (match_operand:SI 1 "register_operand" "%0"))
2661 (szext:DI (match_operand:SI 2 "register_operand" "r"))))
2662 (clobber (match_scratch:SI 3 "=h"))]
2663 "TARGET_HAS_MUL_INSNS"
2664 "%!mul<su>.d %2,%M0\;move $mof,%H0")
2666 ;; These two patterns may be expressible by other means, perhaps by making
2667 ;; [u]?mulsidi3 a define_expand.
2669 ;; Due to register allocation braindamage, the clobber 1,2 alternatives
2670 ;; cause a move into the clobbered register *before* the insn, then
2671 ;; after the insn, mof is moved too, rather than the clobber assigned
2672 ;; the last mof target. This became apparent when making MOF and SRP
2673 ;; visible registers, with the necessary tweak to smulsi3_highpart.
2674 ;; Because these patterns are used in division by constants, that damage
2675 ;; is visible (ipps regression tests). Therefore the last two
2676 ;; alternatives, "helping" reload to avoid an unnecessary move, but
2677 ;; punished by force of one "?". Check code from "int d (int a) {return
2678 ;; a / 1000;}" and unsigned. FIXME: Comment above was for 3.2, revisit.
2680 (define_insn "<su>mulsi3_highpart"
2681 [(set (match_operand:SI 0 "register_operand" "=h,h,?r,?r")
2685 (szext:DI (match_operand:SI 1 "register_operand" "r,r,0,r"))
2686 (szext:DI (match_operand:SI 2 "register_operand" "r,r,r,0")))
2688 (clobber (match_scratch:SI 3 "=1,2,h,h"))]
2689 "TARGET_HAS_MUL_INSNS"
2693 %!mul<su>.d %2,%1\;move $mof,%0
2694 %!mul<su>.d %1,%2\;move $mof,%0"
2695 [(set_attr "slottable" "yes,yes,no,no")
2696 (set_attr "cc" "clobber")])
2698 ;; Divide and modulus instructions. CRIS only has a step instruction.
2700 (define_insn "dstep_shift"
2701 [(set (match_operand:SI 0 "register_operand" "=r")
2703 (geu:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2705 (match_operand:SI 2 "register_operand" "r"))
2706 (minus:SI (ashift:SI (match_operand:SI 3 "register_operand" "0")
2708 (match_operand:SI 4 "register_operand" "2"))
2709 (ashift:SI (match_operand:SI 5 "register_operand" "0")
2713 [(set_attr "slottable" "yes")
2714 (set_attr "cc" "noov32")])
2716 ;; Here's a variant with mult instead of ashift.
2718 ;; FIXME: This should be investigated. Which one matches through combination?
2720 (define_insn "dstep_mul"
2721 [(set (match_operand:SI 0 "register_operand" "=r")
2723 (geu:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2725 (match_operand:SI 2 "register_operand" "r"))
2726 (minus:SI (mult:SI (match_operand:SI 3 "register_operand" "0")
2728 (match_operand:SI 4 "register_operand" "2"))
2729 (mult:SI (match_operand:SI 5 "register_operand" "0")
2731 "operands[0] != frame_pointer_rtx
2732 && operands[1] != frame_pointer_rtx
2733 && operands[2] != frame_pointer_rtx
2734 && operands[3] != frame_pointer_rtx"
2736 [(set_attr "slottable" "yes")
2737 (set_attr "cc" "noov32")])
2739 ;; Logical operators.
2743 ;; There is no use in defining "anddi3", because gcc can expand this by
2744 ;; itself, and make reasonable code without interference.
2746 ;; If the first operand is memory or a register and is the same as the
2747 ;; second operand, and the third operand is -256 or -65536, we can use
2748 ;; CLEAR instead. Or, if the first operand is a register, and the third
2749 ;; operand is 255 or 65535, we can zero_extend.
2750 ;; GCC isn't smart enough to recognize these cases (yet), and they seem
2751 ;; to be common enough to be worthwhile.
2752 ;; FIXME: This should be made obsolete.
2754 (define_expand "andsi3"
2755 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2756 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2757 (match_operand:SI 2 "general_operand" "")))]
2760 if (! (CONST_INT_P (operands[2])
2761 && (((INTVAL (operands[2]) == -256
2762 || INTVAL (operands[2]) == -65536)
2763 && rtx_equal_p (operands[1], operands[0]))
2764 || ((INTVAL (operands[2]) == 255
2765 || INTVAL (operands[2]) == 65535)
2766 && REG_P (operands[0])))))
2768 /* Make intermediate steps if operand0 is not a register or
2769 operand1 is not a register, and hope that the reload pass will
2770 make something useful out of it. Note that the operands are
2771 *not* canonicalized. For the moment, I chicken out on this,
2772 because all or most ports do not describe 'and' with
2773 canonicalized operands, and I seem to remember magic in reload,
2774 checking that operand1 has constraint '%0', in which case
2775 operand0 and operand1 must have similar predicates.
2776 FIXME: Investigate. */
2777 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
2778 rtx reg1 = operands[1];
2782 emit_move_insn (reg0, reg1);
2786 emit_insn (gen_rtx_SET (SImode, reg0,
2787 gen_rtx_AND (SImode, reg1, operands[2])));
2789 /* Make sure we get the right *final* destination. */
2790 if (! REG_P (operands[0]))
2791 emit_move_insn (operands[0], reg0);
2797 ;; Some special cases of andsi3.
2799 (define_insn "*andsi_movu"
2800 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2801 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q,To")
2802 (match_operand:SI 2 "const_int_operand" "n,n,n")))]
2803 "(INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535)
2804 && !side_effects_p (operands[1])"
2806 [(set_attr "slottable" "yes,yes,no")])
2808 (define_insn "*andsi_clear"
2809 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q,Q,To,To")
2810 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
2811 (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))]
2812 "(INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256)
2813 && !side_effects_p (operands[0])"
2821 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2822 (set_attr "cc" "none")])
2824 ;; This is a catch-all pattern, taking care of everything that was not
2825 ;; matched in the insns above.
2827 ;; Sidenote: the tightening from "nonimmediate_operand" to
2828 ;; "register_operand" for operand 1 actually increased the register
2829 ;; pressure (worse code). That will hopefully change with an
2830 ;; improved reload pass.
2832 (define_insn "*expanded_andsi_non_v32"
2833 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r")
2834 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,r")
2835 (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))]
2843 [(set_attr "slottable" "yes,yes,yes,no,no")])
2845 (define_insn "*expanded_andsi_v32"
2846 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2847 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
2848 (match_operand:SI 2 "general_operand" "I,r,Q>,g")))]
2855 [(set_attr "slottable" "yes,yes,yes,no")
2856 (set_attr "cc" "noov32")])
2858 ;; For both QI and HI we may use the quick patterns. This results in
2859 ;; useless condition codes, but that is used rarely enough for it to
2860 ;; normally be a win (could check ahead for use of cc0, but seems to be
2861 ;; more pain than win).
2863 ;; FIXME: See note for andsi3
2865 (define_expand "andhi3"
2866 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2867 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
2868 (match_operand:HI 2 "general_operand" "")))]
2871 if (! (CONST_INT_P (operands[2])
2872 && (((INTVAL (operands[2]) == -256
2873 || INTVAL (operands[2]) == 65280)
2874 && rtx_equal_p (operands[1], operands[0]))
2875 || (INTVAL (operands[2]) == 255
2876 && REG_P (operands[0])))))
2878 /* See comment for andsi3. */
2879 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (HImode);
2880 rtx reg1 = operands[1];
2884 emit_move_insn (reg0, reg1);
2888 emit_insn (gen_rtx_SET (HImode, reg0,
2889 gen_rtx_AND (HImode, reg1, operands[2])));
2891 /* Make sure we get the right destination. */
2892 if (! REG_P (operands[0]))
2893 emit_move_insn (operands[0], reg0);
2899 ;; Some fast andhi3 special cases.
2901 (define_insn "*andhi_movu"
2902 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
2903 (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q,To")
2905 "!side_effects_p (operands[1])"
2907 [(set_attr "slottable" "yes,yes,no")])
2909 (define_insn "*andhi_clear"
2910 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q,To")
2911 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
2913 "!side_effects_p (operands[0])"
2915 [(set_attr "slottable" "yes,yes,no")
2916 (set_attr "cc" "none")])
2918 ;; Catch-all andhi3 pattern.
2920 (define_insn "*expanded_andhi_non_v32"
2921 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
2922 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
2923 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2925 ;; Sidenote: the tightening from "general_operand" to
2926 ;; "register_operand" for operand 1 actually increased the register
2927 ;; pressure (worse code). That will hopefully change with an
2928 ;; improved reload pass.
2939 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2940 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2942 (define_insn "*expanded_andhi_v32"
2943 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
2944 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
2945 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))]
2954 [(set_attr "slottable" "yes,yes,yes,no,yes,no")
2955 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")])
2957 ;; A strict_low_part pattern.
2959 (define_insn "*andhi_lowpart_non_v32"
2960 [(set (strict_low_part
2961 (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r"))
2962 (and:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
2963 (match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
2972 [(set_attr "slottable" "yes,yes,no,yes,no,no")
2973 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
2975 (define_insn "*andhi_lowpart_v32"
2976 [(set (strict_low_part
2977 (match_operand:HI 0 "register_operand" "=r,r,r,r,r"))
2978 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
2979 (match_operand:HI 2 "general_operand" "r,Q>,L,O,g")))]
2987 [(set_attr "slottable" "yes,yes,no,yes,no")
2988 (set_attr "cc" "noov32,noov32,noov32,clobber,noov32")])
2990 (define_expand "andqi3"
2991 [(set (match_operand:QI 0 "register_operand")
2992 (and:QI (match_operand:QI 1 "register_operand")
2993 (match_operand:QI 2 "general_operand")))]
2997 (define_insn "*andqi3_non_v32"
2998 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
2999 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
3000 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
3009 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
3010 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
3012 (define_insn "*andqi3_v32"
3013 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
3014 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
3015 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))]
3023 [(set_attr "slottable" "yes,yes,yes,yes,no")
3024 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")])
3026 (define_insn "*andqi_lowpart_non_v32"
3027 [(set (strict_low_part
3028 (match_operand:QI 0 "register_operand" "=r,r, r,r,r"))
3029 (and:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,r")
3030 (match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
3038 [(set_attr "slottable" "yes,yes,yes,no,no")
3039 (set_attr "cc" "normal,normal,clobber,normal,normal")])
3041 (define_insn "*andqi_lowpart_v32"
3042 [(set (strict_low_part
3043 (match_operand:QI 0 "register_operand" "=r,r,r,r"))
3044 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
3045 (match_operand:QI 2 "general_operand" "r,Q>,O,g")))]
3052 [(set_attr "slottable" "yes,yes,yes,no")
3053 (set_attr "cc" "noov32,noov32,clobber,noov32")])
3057 ;; Same comment as anddi3 applies here - no need for such a pattern.
3059 ;; It seems there's no need to jump through hoops to get good code such as
3062 (define_expand "ior<mode>3"
3063 [(set (match_operand:BWD 0 "register_operand")
3064 (ior:BWD (match_operand:BWD 1 "register_operand")
3065 (match_operand:BWD 2 "general_operand")))]
3069 (define_insn "*iorsi3_non_v32"
3070 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r,r")
3071 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,0,r")
3072 (match_operand:SI 2 "general_operand" "I, r,Q>,n,g,!To")))]
3081 [(set_attr "slottable" "yes,yes,yes,no,no,no")
3082 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
3084 (define_insn "*iorsi3_v32"
3085 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
3086 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0")
3087 (match_operand:SI 2 "general_operand" "I,r,Q>,n,g")))]
3095 [(set_attr "slottable" "yes,yes,yes,no,no")
3096 (set_attr "cc" "noov32,noov32,noov32,clobber,noov32")])
3098 (define_insn "*iorhi3_non_v32"
3099 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
3100 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
3101 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
3111 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
3112 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
3114 (define_insn "*iorhi3_v32"
3115 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
3116 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
3117 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))]
3126 [(set_attr "slottable" "yes,yes,yes,no,yes,no")
3127 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")])
3129 (define_insn "*iorqi3_non_v32"
3130 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
3131 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
3132 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
3141 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
3142 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
3144 (define_insn "*iorqi3_v32"
3145 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
3146 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
3147 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))]
3155 [(set_attr "slottable" "yes,yes,yes,yes,no")
3156 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")])
3160 ;; See comment about "anddi3" for xordi3 - no need for such a pattern.
3161 ;; FIXME: Do we really need the shorter variants?
3163 (define_insn "xorsi3"
3164 [(set (match_operand:SI 0 "register_operand" "=r")
3165 (xor:SI (match_operand:SI 1 "register_operand" "%0")
3166 (match_operand:SI 2 "register_operand" "r")))]
3169 [(set_attr "slottable" "yes")
3170 (set_attr "cc" "noov32")])
3172 (define_insn "xor<mode>3"
3173 [(set (match_operand:BW 0 "register_operand" "=r")
3174 (xor:BW (match_operand:BW 1 "register_operand" "%0")
3175 (match_operand:BW 2 "register_operand" "r")))]
3178 [(set_attr "slottable" "yes")
3179 (set_attr "cc" "clobber")])
3183 ;; Questionable use, here mostly as a (slightly usable) define_expand
3186 (define_expand "negsf2"
3189 (parallel [(set (match_operand:SF 0 "register_operand" "=r")
3190 (neg:SF (match_operand:SF 1
3191 "register_operand" "0")))
3192 (use (match_dup 2))])]
3195 operands[2] = gen_reg_rtx (SImode);
3196 operands[3] = GEN_INT (1 << 31);
3199 (define_insn "*expanded_negsf2"
3200 [(set (match_operand:SF 0 "register_operand" "=r")
3201 (neg:SF (match_operand:SF 1 "register_operand" "0")))
3202 (use (match_operand:SI 2 "register_operand" "r"))]
3205 [(set_attr "slottable" "yes")])
3207 ;; No "negdi2" although we could make one up that may be faster than
3208 ;; the one in libgcc.
3210 (define_insn "neg<mode>2"
3211 [(set (match_operand:BWD 0 "register_operand" "=r")
3212 (neg:BWD (match_operand:BWD 1 "register_operand" "r")))]
3215 [(set_attr "slottable" "yes")])
3219 ;; See comment on anddi3 - no need for a DImode pattern.
3220 ;; See also xor comment.
3222 (define_insn "one_cmplsi2"
3223 [(set (match_operand:SI 0 "register_operand" "=r")
3224 (not:SI (match_operand:SI 1 "register_operand" "0")))]
3227 [(set_attr "slottable" "yes")
3228 (set_attr "cc" "noov32")])
3230 (define_insn "one_cmpl<mode>2"
3231 [(set (match_operand:BW 0 "register_operand" "=r")
3232 (not:BW (match_operand:BW 1 "register_operand" "0")))]
3235 [(set_attr "slottable" "yes")
3236 (set_attr "cc" "clobber")])
3238 ;; Arithmetic/Logical shift right (and SI left).
3240 (define_insn "<shlr>si3"
3241 [(set (match_operand:SI 0 "register_operand" "=r")
3242 (shift:SI (match_operand:SI 1 "register_operand" "0")
3243 (match_operand:SI 2 "nonmemory_operand" "Kr")))]
3246 if (REG_S_P (operands[2]))
3247 return "<slr>.d %2,%0";
3249 return "<slr>q %2,%0";
3251 [(set_attr "slottable" "yes")
3252 (set_attr "cc" "noov32")])
3254 ;; Since gcc gets lost, and forgets to zero-extend the source (or mask
3255 ;; the destination) when it changes shifts of lower modes into SImode,
3256 ;; it is better to make these expands an anonymous patterns instead of
3257 ;; the more correct define_insns. This occurs when gcc thinks that is
3258 ;; is better to widen to SImode and use immediate shift count.
3260 ;; FIXME: Is this legacy or still true for gcc >= 2.7.2?
3262 ;; FIXME: Can't parametrize sign_extend and zero_extend (before
3263 ;; mentioning "shiftrt"), so we need two patterns.
3264 (define_expand "ashr<mode>3"
3266 (sign_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
3268 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
3269 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
3270 (set (match_operand:BW 0 "general_operand" "")
3271 (subreg:BW (match_dup 5) 0))]
3276 for (i = 3; i < 6; i++)
3277 operands[i] = gen_reg_rtx (SImode);
3280 (define_expand "lshr<mode>3"
3282 (zero_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
3284 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
3285 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
3286 (set (match_operand:BW 0 "general_operand" "")
3287 (subreg:BW (match_dup 5) 0))]
3292 for (i = 3; i < 6; i++)
3293 operands[i] = gen_reg_rtx (SImode);
3296 (define_insn "*expanded_<shlr><mode>"
3297 [(set (match_operand:BW 0 "register_operand" "=r")
3298 (shiftrt:BW (match_operand:BW 1 "register_operand" "0")
3299 (match_operand:BW 2 "register_operand" "r")))]
3302 [(set_attr "slottable" "yes")
3303 (set_attr "cc" "noov32")])
3305 (define_insn "*<shlr><mode>_lowpart"
3306 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
3307 (shiftrt:BW (match_dup 0)
3308 (match_operand:BW 1 "register_operand" "r")))]
3311 [(set_attr "slottable" "yes")
3312 (set_attr "cc" "noov32")])
3314 ;; Arithmetic/logical shift left.
3316 ;; For narrower modes than SI, we can use lslq although it makes cc
3317 ;; unusable. The win is that we do not have to reload the shift-count
3320 (define_insn "ashl<mode>3"
3321 [(set (match_operand:BW 0 "register_operand" "=r,r")
3322 (ashift:BW (match_operand:BW 1 "register_operand" "0,0")
3323 (match_operand:BW 2 "nonmemory_operand" "r,K")))]
3327 (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > <nbitsm1>)
3329 : (CONSTANT_P (operands[2])
3330 ? "lslq %2,%0" : "lsl<m> %2,%0");
3332 [(set_attr "slottable" "yes")
3333 (set_attr "cc" "noov32,clobber")])
3335 ;; A strict_low_part matcher.
3337 (define_insn "*ashl<mode>_lowpart"
3338 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
3339 (ashift:BW (match_dup 0)
3340 (match_operand:HI 1 "register_operand" "r")))]
3343 [(set_attr "slottable" "yes")
3344 (set_attr "cc" "noov32")])
3346 ;; Various strange insns that gcc likes.
3348 ;; Fortunately, it is simple to construct an abssf (although it may not
3349 ;; be very much used in practice).
3351 (define_insn "abssf2"
3352 [(set (match_operand:SF 0 "register_operand" "=r")
3353 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
3355 "lslq 1,%0\;lsrq 1,%0")
3357 (define_insn "abssi2"
3358 [(set (match_operand:SI 0 "register_operand" "=r")
3359 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
3362 [(set_attr "slottable" "yes")
3363 (set_attr "cc" "noov32")])
3365 ;; FIXME: GCC should be able to do these expansions itself.
3367 (define_expand "abs<mode>2"
3369 (sign_extend:SI (match_operand:BW 1 "general_operand" "")))
3370 (set (match_dup 3) (abs:SI (match_dup 2)))
3371 (set (match_operand:BW 0 "register_operand" "")
3372 (subreg:BW (match_dup 3) 0))]
3374 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
3376 (define_insn "clzsi2"
3377 [(set (match_operand:SI 0 "register_operand" "=r")
3378 (clz:SI (match_operand:SI 1 "register_operand" "r")))]
3381 [(set_attr "slottable" "yes")
3382 (set_attr "cc" "noov32")])
3384 (define_insn "bswapsi2"
3385 [(set (match_operand:SI 0 "register_operand" "=r")
3386 (bswap:SI (match_operand:SI 1 "register_operand" "0")))]
3389 [(set_attr "slottable" "yes")
3390 (set_attr "cc" "noov32")])
3392 ;; This instruction swaps all bits in a register.
3393 ;; That means that the most significant bit is put in the place
3394 ;; of the least significant bit, and so on.
3396 (define_insn "cris_swap_bits"
3397 [(set (match_operand:SI 0 "register_operand" "=r")
3398 (unspec:SI [(match_operand:SI 1 "register_operand" "0")]
3399 CRIS_UNSPEC_SWAP_BITS))]
3402 [(set_attr "slottable" "yes")
3403 (set_attr "cc" "noov32")])
3405 ;; Implement ctz using two instructions, one for bit swap and one for clz.
3406 ;; Defines a scratch register to avoid clobbering input.
3408 (define_expand "ctzsi2"
3410 (match_operand:SI 1 "register_operand"))
3412 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_SWAP_BITS))
3413 (set (match_operand:SI 0 "register_operand")
3414 (clz:SI (match_dup 2)))]
3415 "TARGET_HAS_LZ && TARGET_HAS_SWAP"
3416 "operands[2] = gen_reg_rtx (SImode);")
3418 ;; Bound-insn. Defined to be the same as an unsigned minimum, which is an
3419 ;; operation supported by gcc. Used in casesi, but used now and then in
3422 (define_expand "uminsi3"
3423 [(set (match_operand:SI 0 "register_operand" "")
3424 (umin:SI (match_operand:SI 1 "register_operand" "")
3425 (match_operand:SI 2 "general_operand" "")))]
3428 if (MEM_P (operands[2]) && TARGET_V32)
3429 operands[2] = force_reg (SImode, operands[2]);
3432 (define_insn "*uminsi3_non_v32"
3433 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r")
3434 (umin:SI (match_operand:SI 1 "register_operand" "%0,0, 0,r")
3435 (match_operand:SI 2 "general_operand" "r,Q>,g,!To")))]
3438 if (CONST_INT_P (operands[2]))
3440 /* Constant operands are zero-extended, so only 32-bit operands
3442 if (INTVAL (operands[2]) >= 0)
3444 if (INTVAL (operands[2]) < 256)
3445 return "bound.b %2,%0";
3447 if (INTVAL (operands[2]) < 65536)
3448 return "bound.w %2,%0";
3451 else if (which_alternative == 3)
3452 return "bound.d %2,%1,%0";
3454 return "bound.d %2,%0";
3456 [(set_attr "slottable" "yes,yes,no,no")])
3458 (define_insn "*uminsi3_v32"
3459 [(set (match_operand:SI 0 "register_operand" "=r,r")
3460 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
3461 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
3464 if (GET_CODE (operands[2]) == CONST_INT)
3466 /* Constant operands are zero-extended, so only 32-bit operands
3468 if (INTVAL (operands[2]) >= 0)
3470 if (INTVAL (operands[2]) < 256)
3471 return "bound.b %2,%0";
3473 if (INTVAL (operands[2]) < 65536)
3474 return "bound.w %2,%0";
3478 return "bound.d %2,%0";
3480 [(set_attr "slottable" "yes,no")])
3482 ;; Jump and branch insns.
3486 (label_ref (match_operand 0 "" "")))]
3489 [(set_attr "slottable" "has_slot")])
3491 ;; Testcase gcc.c-torture/compile/991213-3.c fails if we allow a constant
3492 ;; here, since the insn is not recognized as an indirect jump by
3493 ;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to
3494 ;; change from general_operand to nonimmediate_operand (at least the docs
3495 ;; should be changed), but then again the pattern is called indirect_jump.
3496 (define_expand "indirect_jump"
3497 [(set (pc) (match_operand:SI 0 "nonimmediate_operand"))]
3500 if (TARGET_V32 && MEM_P (operands[0]))
3501 operands[0] = force_reg (SImode, operands[0]);
3504 (define_insn "*indirect_jump_non_v32"
3505 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
3509 (define_insn "*indirect_jump_v32"
3510 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
3513 [(set_attr "slottable" "has_slot")])
3515 ;; Return insn. Used whenever the epilogue is very simple; if it is only
3516 ;; a single ret or jump [sp+]. No allocated stack space or saved
3517 ;; registers are allowed.
3518 ;; Note that for this pattern, although named, it is ok to check the
3519 ;; context of the insn in the test, not only compiler switches.
3521 (define_expand "return"
3523 "cris_simple_epilogue ()"
3524 "cris_expand_return (cris_return_address_on_stack ()); DONE;")
3526 (define_insn "*return_expanded"
3530 return cris_return_address_on_stack_for_return ()
3531 ? "jump [$sp+]" : "ret%#";
3533 [(set (attr "slottable")
3536 "(cris_return_address_on_stack_for_return ())")
3539 (const_string "has_return_slot")))])
3541 (define_expand "prologue"
3543 "TARGET_PROLOGUE_EPILOGUE"
3544 "cris_expand_prologue (); DONE;")
3546 ;; Note that the (return) from the expander itself is always the last
3547 ;; insn in the epilogue.
3548 (define_expand "epilogue"
3550 "TARGET_PROLOGUE_EPILOGUE"
3551 "cris_expand_epilogue (); DONE;")
3553 ;; Conditional branches.
3555 ;; We suffer from the same overflow-bit-gets-in-the-way problem as
3556 ;; e.g. m68k, so we have to check if overflow bit is set on all "signed"
3559 (define_insn "b<ncond:code>"
3561 (if_then_else (ncond (cc0)
3563 (label_ref (match_operand 0 "" ""))
3567 [(set_attr "slottable" "has_slot")])
3569 (define_insn "b<ocond:code>"
3571 (if_then_else (ocond (cc0)
3573 (label_ref (match_operand 0 "" ""))
3578 (cc_prev_status.flags & CC_NO_OVERFLOW)
3579 ? 0 : "b<CC> %l0%#";
3581 [(set_attr "slottable" "has_slot")])
3583 (define_insn "b<rcond:code>"
3585 (if_then_else (rcond (cc0)
3587 (label_ref (match_operand 0 "" ""))
3592 (cc_prev_status.flags & CC_NO_OVERFLOW)
3593 ? "b<oCC> %l0%#" : "b<CC> %l0%#";
3595 [(set_attr "slottable" "has_slot")])
3597 ;; Reversed anonymous patterns to the ones above, as mandated.
3599 (define_insn "*b<ncond:code>_reversed"
3601 (if_then_else (ncond (cc0)
3604 (label_ref (match_operand 0 "" ""))))]
3607 [(set_attr "slottable" "has_slot")])
3609 (define_insn "*b<ocond:code>_reversed"
3611 (if_then_else (ocond (cc0)
3614 (label_ref (match_operand 0 "" ""))))]
3618 (cc_prev_status.flags & CC_NO_OVERFLOW)
3619 ? 0 : "b<rCC> %l0%#";
3621 [(set_attr "slottable" "has_slot")])
3623 (define_insn "*b<rcond:code>_reversed"
3625 (if_then_else (rcond (cc0)
3628 (label_ref (match_operand 0 "" ""))))]
3632 (cc_prev_status.flags & CC_NO_OVERFLOW)
3633 ? "b<roCC> %l0%#" : "b<rCC> %l0%#";
3635 [(set_attr "slottable" "has_slot")])
3637 ;; Set on condition: sCC.
3639 ;; Like bCC, we have to check the overflow bit for
3640 ;; signed conditions.
3642 (define_insn "s<ncond:code>"
3643 [(set (match_operand:SI 0 "register_operand" "=r")
3644 (ncond:SI (cc0) (const_int 0)))]
3647 [(set_attr "slottable" "yes")
3648 (set_attr "cc" "none")])
3650 (define_insn "s<rcond:code>"
3651 [(set (match_operand:SI 0 "register_operand" "=r")
3652 (rcond:SI (cc0) (const_int 0)))]
3656 (cc_prev_status.flags & CC_NO_OVERFLOW)
3657 ? "s<oCC> %0" : "s<CC> %0";
3659 [(set_attr "slottable" "yes")
3660 (set_attr "cc" "none")])
3662 (define_insn "s<ocond:code>"
3663 [(set (match_operand:SI 0 "register_operand" "=r")
3664 (ocond:SI (cc0) (const_int 0)))]
3668 (cc_prev_status.flags & CC_NO_OVERFLOW)
3671 [(set_attr "slottable" "yes")
3672 (set_attr "cc" "none")])
3676 ;; We need to make these patterns "expand", since the real operand is
3677 ;; hidden in a (mem:QI ) inside operand[0] (call_value: operand[1]),
3678 ;; and cannot be checked if it were a "normal" pattern.
3679 ;; Note that "call" and "call_value" are *always* called with a
3680 ;; mem-operand for operand 0 and 1 respective. What happens for combined
3681 ;; instructions is a different issue.
3683 (define_expand "call"
3684 [(parallel [(call (match_operand:QI 0 "cris_mem_call_operand" "")
3685 (match_operand 1 "general_operand" ""))
3686 (clobber (reg:SI CRIS_SRP_REGNUM))])]
3689 gcc_assert (MEM_P (operands[0]));
3691 cris_expand_pic_call_address (&operands[0]);
3694 ;; Accept *anything* as operand 1. Accept operands for operand 0 in
3695 ;; order of preference.
3697 (define_insn "*expanded_call_non_v32"
3698 [(call (mem:QI (match_operand:SI 0 "general_operand" "r,Q>,g"))
3699 (match_operand 1 "" ""))
3700 (clobber (reg:SI CRIS_SRP_REGNUM))]
3704 (define_insn "*expanded_call_v32"
3707 (match_operand:SI 0 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i"))
3708 (match_operand 1 "" ""))
3709 (clobber (reg:SI CRIS_SRP_REGNUM))]
3716 [(set_attr "slottable" "has_call_slot")])
3718 ;; Parallel when calculating and reusing address of indirect pointer
3719 ;; with simple offset. (Makes most sense with PIC.) It looks a bit
3720 ;; wrong not to have the clobber last, but that's the way combine
3721 ;; generates it (except it doesn' look into the *inner* mem, so this
3722 ;; just matches a peephole2). FIXME: investigate that.
3723 (define_insn "*expanded_call_side"
3726 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r, r,r")
3727 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn"))))
3728 (match_operand 2 "" ""))
3729 (clobber (reg:SI CRIS_SRP_REGNUM))
3730 (set (match_operand:SI 3 "register_operand" "=*0,r,r")
3731 (plus:SI (match_dup 0)
3733 "!TARGET_AVOID_GOTPLT && !TARGET_V32"
3736 (define_expand "call_value"
3737 [(parallel [(set (match_operand 0 "" "")
3738 (call (match_operand:QI 1 "cris_mem_call_operand" "")
3739 (match_operand 2 "" "")))
3740 (clobber (reg:SI CRIS_SRP_REGNUM))])]
3743 gcc_assert (MEM_P (operands[1]));
3745 cris_expand_pic_call_address (&operands[1]);
3748 ;; Accept *anything* as operand 2. The validity other than "general" of
3749 ;; operand 0 will be checked elsewhere. Accept operands for operand 1 in
3750 ;; order of preference (Q includes r, but r is shorter, faster).
3751 ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather
3752 ;; than requiring getting rPIC + sym:PLT into a register.
3754 (define_insn "*expanded_call_value_non_v32"
3755 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
3756 (call (mem:QI (match_operand:SI 1 "general_operand" "r,Q>,g"))
3757 (match_operand 2 "" "")))
3758 (clobber (reg:SI CRIS_SRP_REGNUM))]
3761 [(set_attr "cc" "clobber")])
3763 ;; See similar call special-case.
3764 (define_insn "*expanded_call_value_side"
3765 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
3769 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r, r,r")
3770 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
3771 (match_operand 3 "" "")))
3772 (clobber (reg:SI CRIS_SRP_REGNUM))
3773 (set (match_operand:SI 4 "register_operand" "=*1,r,r")
3774 (plus:SI (match_dup 1)
3776 "!TARGET_AVOID_GOTPLT && !TARGET_V32"
3778 [(set_attr "cc" "clobber")])
3780 (define_insn "*expanded_call_value_v32"
3782 (match_operand 0 "nonimmediate_operand" "=g,g,g,g")
3785 (match_operand:SI 1 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i"))
3786 (match_operand 2 "" "")))
3787 (clobber (reg:SI 16))]
3794 [(set_attr "cc" "clobber")
3795 (set_attr "slottable" "has_call_slot")])
3797 ;; Used in debugging. No use for the direct pattern; unfilled
3798 ;; delayed-branches are taken care of by other means.
3804 [(set_attr "cc" "none")])
3806 ;; We need to stop accesses to the stack after the memory is
3807 ;; deallocated. Unfortunately, reorg doesn't look at naked clobbers,
3808 ;; e.g. (insn ... (clobber (mem:BLK (stack_pointer_rtx)))) and we don't
3809 ;; want to use a naked (unspec_volatile) as that would stop any
3810 ;; scheduling in the epilogue. Hence we model it as a "real" insn that
3811 ;; sets the memory in an unspecified manner. FIXME: Unfortunately it
3812 ;; still has the effect of an unspec_volatile.
3813 (define_insn "cris_frame_deallocated_barrier"
3814 [(set (mem:BLK (reg:SI CRIS_SP_REGNUM))
3815 (unspec:BLK [(const_int 0)] CRIS_UNSPEC_FRAME_DEALLOC))]
3818 [(set_attr "length" "0")])
3820 ;; We expand on casesi so we can use "bound" and "add offset fetched from
3821 ;; a table to pc" (adds.w [pc+%0.w],pc).
3823 ;; Note: if you change the "parallel" (or add anything after it) in
3824 ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END
3825 ;; accordingly, to add the default case at the end of the jump-table.
3827 (define_expand "cris_casesi_non_v32"
3828 [(set (match_dup 5) (match_operand:SI 0 "general_operand" ""))
3830 (minus:SI (match_dup 5)
3831 (match_operand:SI 1 "const_int_operand" "n")))
3833 (umin:SI (match_dup 6)
3834 (match_operand:SI 2 "const_int_operand" "n")))
3838 (ltu (match_dup 7) (match_dup 2))
3839 (plus:SI (sign_extend:SI
3841 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3844 (label_ref (match_operand 4 "" ""))))
3845 (use (label_ref (match_operand 3 "" "")))])]
3848 operands[2] = plus_constant (operands[2], 1);
3849 operands[5] = gen_reg_rtx (SImode);
3850 operands[6] = gen_reg_rtx (SImode);
3851 operands[7] = gen_reg_rtx (SImode);
3854 ;; FIXME: Check effect of not JUMP_TABLES_IN_TEXT_SECTION.
3855 (define_expand "cris_casesi_v32"
3856 [(set (match_dup 5) (match_operand:SI 0 "general_operand"))
3858 (minus:SI (match_dup 5)
3859 (match_operand:SI 1 "const_int_operand")))
3861 (umin:SI (match_dup 6)
3862 (match_operand:SI 2 "const_int_operand")))
3863 (set (match_dup 8) (match_dup 11))
3865 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3868 (plus:SI (sign_extend:SI (mem:HI (match_dup 9)))
3873 (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI) (match_dup 2))
3875 (label_ref (match_operand 4 "" ""))))
3876 (use (label_ref (match_dup 3)))])]
3880 rtx xlabel = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
3881 for (i = 5; i <= 10; i++)
3882 operands[i] = gen_reg_rtx (SImode);
3883 operands[2] = plus_constant (operands[2], 1);
3885 /* Don't forget to decorate labels too, for PIC. */
3886 operands[11] = flag_pic
3887 ? gen_rtx_CONST (Pmode,
3888 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xlabel),
3893 (define_expand "casesi"
3894 [(match_operand:SI 0 "general_operand")
3895 (match_operand:SI 1 "const_int_operand")
3896 (match_operand:SI 2 "const_int_operand")
3897 (match_operand 3 "" "")
3898 (match_operand 4 "" "")]
3902 emit_insn (gen_cris_casesi_v32 (operands[0], operands[1], operands[2],
3903 operands[3], operands[4]));
3905 emit_insn (gen_cris_casesi_non_v32 (operands[0], operands[1], operands[2],
3906 operands[3], operands[4]));
3910 ;; Split-patterns. Some of them have modes unspecified. This
3911 ;; should always be ok; if for no other reason sparc.md has it as
3914 ;; When register_operand is specified for an operand, we can get a
3915 ;; subreg as well (Axis-990331), so don't just assume that REG_P is true
3916 ;; for a register_operand and that REGNO can be used as is. It is best to
3917 ;; guard with REG_P, unless it is worth it to adjust for the subreg case.
3919 ;; op [rx + 0],ry,rz
3920 ;; The index to rx is optimized into zero, and gone.
3922 ;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended,
3923 ;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx].
3927 ;; Lose if rz=ry or rx=rz.
3928 ;; Call this op-extend-split.
3929 ;; Do not match for V32; the addo and addi shouldn't be split
3933 [(set (match_operand 0 "register_operand" "")
3935 4 "cris_operand_extend_operator"
3936 [(match_operand 1 "register_operand" "")
3938 3 "cris_extend_operator"
3939 [(match_operand 2 "memory_operand" "")])]))]
3941 && REG_P (operands[0])
3942 && REG_P (operands[1])
3943 && REGNO (operands[1]) != REGNO (operands[0])
3944 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3945 && REG_P (XEXP (operands[2], 0))
3946 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
3952 (match_op_dup 3 [(match_dup 2)])]))]
3955 ;; As op-extend-split, but recognize and split op [rz],ry,rz into
3958 ;; Do this for plus or bound only, being commutative operations, since we
3959 ;; have swapped the operands.
3960 ;; Call this op-extend-split-rx=rz
3963 [(set (match_operand 0 "register_operand" "")
3965 4 "cris_plus_or_bound_operator"
3966 [(match_operand 1 "register_operand" "")
3968 3 "cris_extend_operator"
3969 [(match_operand 2 "memory_operand" "")])]))]
3971 && REG_P (operands[0])
3972 && REG_P (operands[1])
3973 && REGNO (operands[1]) != REGNO (operands[0])
3974 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3975 && REG_P (XEXP (operands[2], 0))
3976 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
3978 (match_op_dup 3 [(match_dup 2)]))
3985 ;; As the op-extend-split, but swapped operands, and only for
3986 ;; plus or bound, being the commutative extend-operators. FIXME: Why is
3987 ;; this needed? Is it?
3988 ;; Call this op-extend-split-swapped
3991 [(set (match_operand 0 "register_operand" "")
3993 4 "cris_plus_or_bound_operator"
3995 3 "cris_extend_operator"
3996 [(match_operand 2 "memory_operand" "")])
3997 (match_operand 1 "register_operand" "")]))]
3999 && REG_P (operands[0])
4000 && REG_P (operands[1])
4001 && REGNO (operands[1]) != REGNO (operands[0])
4002 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4003 && REG_P (XEXP (operands[2], 0))
4004 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4010 (match_op_dup 3 [(match_dup 2)])]))]
4013 ;; As op-extend-split-rx=rz, but swapped operands, only for plus or
4014 ;; bound. Call this op-extend-split-swapped-rx=rz.
4017 [(set (match_operand 0 "register_operand" "")
4019 4 "cris_plus_or_bound_operator"
4021 3 "cris_extend_operator"
4022 [(match_operand 2 "memory_operand" "")])
4023 (match_operand 1 "register_operand" "")]))]
4025 && REG_P (operands[0])
4026 && REG_P (operands[1])
4027 && REGNO (operands[1]) != REGNO (operands[0])
4028 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4029 && REG_P (XEXP (operands[2], 0))
4030 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4032 (match_op_dup 3 [(match_dup 2)]))
4039 ;; As op-extend-split, but the mem operand is not extended.
4041 ;; op [rx],ry,rz changed into
4044 ;; lose if ry=rz or rx=rz
4045 ;; Call this op-extend.
4048 [(set (match_operand 0 "register_operand" "")
4050 3 "cris_orthogonal_operator"
4051 [(match_operand 1 "register_operand" "")
4052 (match_operand 2 "memory_operand" "")]))]
4054 && REG_P (operands[0])
4055 && REG_P (operands[1])
4056 && REGNO (operands[1]) != REGNO (operands[0])
4057 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4058 && REG_P (XEXP (operands[2], 0))
4059 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4068 ;; As op-extend-split-rx=rz, non-extended.
4069 ;; Call this op-split-rx=rz
4072 [(set (match_operand 0 "register_operand" "")
4074 3 "cris_commutative_orth_op"
4075 [(match_operand 2 "memory_operand" "")
4076 (match_operand 1 "register_operand" "")]))]
4078 && REG_P (operands[0])
4079 && REG_P (operands[1])
4080 && REGNO (operands[1]) != REGNO (operands[0])
4081 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4082 && REG_P (XEXP (operands[2], 0))
4083 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4092 ;; As op-extend-split-swapped, nonextended.
4093 ;; Call this op-split-swapped.
4096 [(set (match_operand 0 "register_operand" "")
4098 3 "cris_commutative_orth_op"
4099 [(match_operand 1 "register_operand" "")
4100 (match_operand 2 "memory_operand" "")]))]
4102 && REG_P (operands[0]) && REG_P (operands[1])
4103 && REGNO (operands[1]) != REGNO (operands[0])
4104 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4105 && REG_P (XEXP (operands[2], 0))
4106 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4115 ;; As op-extend-split-swapped-rx=rz, non-extended.
4116 ;; Call this op-split-swapped-rx=rz.
4119 [(set (match_operand 0 "register_operand" "")
4121 3 "cris_orthogonal_operator"
4122 [(match_operand 2 "memory_operand" "")
4123 (match_operand 1 "register_operand" "")]))]
4125 && REG_P (operands[0]) && REG_P (operands[1])
4126 && REGNO (operands[1]) != REGNO (operands[0])
4127 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4128 && REG_P (XEXP (operands[2], 0))
4129 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4138 ;; Splits for all cases in side-effect insns where (possibly after reload
4139 ;; and register allocation) rx and ry in [rx=ry+i] are equal.
4141 ;; move.S1 [rx=rx+rz.S2],ry
4145 [(set (match_operand 0 "register_operand" "")
4149 (mult:SI (match_operand:SI 1 "register_operand" "")
4150 (match_operand:SI 2 "const_int_operand" ""))
4151 (match_operand:SI 3 "register_operand" ""))]))
4152 (set (match_operand:SI 4 "register_operand" "")
4153 (plus:SI (mult:SI (match_dup 1)
4156 "REG_P (operands[3]) && REG_P (operands[4])
4157 && REGNO (operands[3]) == REGNO (operands[4])"
4158 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4160 (set (match_dup 0) (match_dup 5))]
4161 "operands[5] = replace_equiv_address (operands[6], operands[3]);")
4163 ;; move.S1 [rx=rx+i],ry
4167 [(set (match_operand 0 "register_operand" "")
4170 [(plus:SI (match_operand:SI 1 "cris_bdap_operand" "")
4171 (match_operand:SI 2 "cris_bdap_operand" ""))]))
4172 (set (match_operand:SI 3 "register_operand" "")
4173 (plus:SI (match_dup 1)
4175 "(rtx_equal_p (operands[3], operands[1])
4176 || rtx_equal_p (operands[3], operands[2]))"
4177 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4178 (set (match_dup 0) (match_dup 4))]
4180 operands[4] = replace_equiv_address (operands[5], operands[3]);
4181 cris_order_for_addsi3 (operands, 1);
4184 ;; move.S1 ry,[rx=rx+rz.S2]
4188 [(set (match_operator
4191 (mult:SI (match_operand:SI 0 "register_operand" "")
4192 (match_operand:SI 1 "const_int_operand" ""))
4193 (match_operand:SI 2 "register_operand" ""))])
4194 (match_operand 3 "register_operand" ""))
4195 (set (match_operand:SI 4 "register_operand" "")
4196 (plus:SI (mult:SI (match_dup 0)
4199 "REG_P (operands[2]) && REG_P (operands[4])
4200 && REGNO (operands[4]) == REGNO (operands[2])"
4201 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4203 (set (match_dup 5) (match_dup 3))]
4204 "operands[5] = replace_equiv_address (operands[6], operands[4]);")
4206 ;; move.S1 ry,[rx=rx+i]
4210 [(set (match_operator
4212 [(plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4213 (match_operand:SI 1 "cris_bdap_operand" ""))])
4214 (match_operand 2 "register_operand" ""))
4215 (set (match_operand:SI 3 "register_operand" "")
4216 (plus:SI (match_dup 0)
4218 "(rtx_equal_p (operands[3], operands[0])
4219 || rtx_equal_p (operands[3], operands[1]))"
4220 [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1)))
4221 (set (match_dup 5) (match_dup 2))]
4223 operands[5] = replace_equiv_address (operands[6], operands[3]);
4224 cris_order_for_addsi3 (operands, 0);
4227 ;; clear.[bwd] [rx=rx+rz.S2]
4231 [(set (mem:BWD (plus:SI
4232 (mult:SI (match_operand:SI 0 "register_operand" "")
4233 (match_operand:SI 1 "const_int_operand" ""))
4234 (match_operand:SI 2 "register_operand" "")))
4236 (set (match_operand:SI 3 "register_operand" "")
4237 (plus:SI (mult:SI (match_dup 0)
4240 "REG_P (operands[2]) && REG_P (operands[3])
4241 && REGNO (operands[3]) == REGNO (operands[2])"
4242 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4244 (set (mem:BWD (match_dup 3)) (const_int 0))]
4247 ;; clear.[bwd] [rx=rx+i]
4252 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4253 (match_operand:SI 1 "cris_bdap_operand" "")))
4255 (set (match_operand:SI 2 "register_operand" "")
4256 (plus:SI (match_dup 0)
4258 "(rtx_equal_p (operands[0], operands[2])
4259 || rtx_equal_p (operands[2], operands[1]))"
4260 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4261 (set (mem:BWD (match_dup 2)) (const_int 0))]
4262 "cris_order_for_addsi3 (operands, 0);")
4264 ;; mov(s|u).S1 [rx=rx+rz.S2],ry
4268 [(set (match_operand 0 "register_operand" "")
4270 5 "cris_extend_operator"
4272 (mult:SI (match_operand:SI 1 "register_operand" "")
4273 (match_operand:SI 2 "const_int_operand" ""))
4274 (match_operand:SI 3 "register_operand" "")))]))
4275 (set (match_operand:SI 4 "register_operand" "")
4276 (plus:SI (mult:SI (match_dup 1)
4279 "REG_P (operands[3])
4280 && REG_P (operands[4])
4281 && REGNO (operands[3]) == REGNO (operands[4])"
4282 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4284 (set (match_dup 0) (match_op_dup 5 [(match_dup 6)]))]
4285 "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);")
4287 ;; mov(s|u).S1 [rx=rx+i],ry
4291 [(set (match_operand 0 "register_operand" "")
4293 4 "cris_extend_operator"
4295 (match_operand:SI 1 "cris_bdap_operand" "")
4296 (match_operand:SI 2 "cris_bdap_operand" "")))]))
4297 (set (match_operand:SI 3 "register_operand" "")
4298 (plus:SI (match_dup 1)
4300 "(rtx_equal_p (operands[1], operands[3])
4301 || rtx_equal_p (operands[2], operands[3]))"
4302 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4303 (set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))]
4305 operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]);
4306 cris_order_for_addsi3 (operands, 1);
4309 ;; op.S1 [rx=rx+i],ry
4313 [(set (match_operand 0 "register_operand" "")
4315 5 "cris_orthogonal_operator"
4316 [(match_operand 1 "register_operand" "")
4318 (match_operand:SI 2 "cris_bdap_operand" "")
4319 (match_operand:SI 3 "cris_bdap_operand" "")))]))
4320 (set (match_operand:SI 4 "register_operand" "")
4321 (plus:SI (match_dup 2)
4323 "(rtx_equal_p (operands[4], operands[2])
4324 || rtx_equal_p (operands[4], operands[3]))"
4325 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4326 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))]
4328 operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]);
4329 cris_order_for_addsi3 (operands, 2);
4332 ;; op.S1 [rx=rx+rz.S2],ry
4336 [(set (match_operand 0 "register_operand" "")
4338 6 "cris_orthogonal_operator"
4339 [(match_operand 1 "register_operand" "")
4341 (mult:SI (match_operand:SI 2 "register_operand" "")
4342 (match_operand:SI 3 "const_int_operand" ""))
4343 (match_operand:SI 4 "register_operand" "")))]))
4344 (set (match_operand:SI 5 "register_operand" "")
4345 (plus:SI (mult:SI (match_dup 2)
4348 "REG_P (operands[4])
4349 && REG_P (operands[5])
4350 && REGNO (operands[5]) == REGNO (operands[4])"
4351 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4353 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 7)]))]
4354 "operands[7] = replace_equiv_address (XEXP (operands[6], 1), operands[5]);")
4356 ;; op.S1 [rx=rx+rz.S2],ry (swapped)
4360 [(set (match_operand 0 "register_operand" "")
4362 6 "cris_commutative_orth_op"
4364 (mult:SI (match_operand:SI 2 "register_operand" "")
4365 (match_operand:SI 3 "const_int_operand" ""))
4366 (match_operand:SI 4 "register_operand" "")))
4367 (match_operand 1 "register_operand" "")]))
4368 (set (match_operand:SI 5 "register_operand" "")
4369 (plus:SI (mult:SI (match_dup 2)
4372 "REG_P (operands[4])
4373 && REG_P (operands[5])
4374 && REGNO (operands[5]) == REGNO (operands[4])"
4375 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4377 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4378 "operands[7] = replace_equiv_address (XEXP (operands[6], 0), operands[5]);")
4380 ;; op.S1 [rx=rx+i],ry (swapped)
4384 [(set (match_operand 0 "register_operand" "")
4386 5 "cris_commutative_orth_op"
4388 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4389 (match_operand:SI 3 "cris_bdap_operand" "")))
4390 (match_operand 1 "register_operand" "")]))
4391 (set (match_operand:SI 4 "register_operand" "")
4392 (plus:SI (match_dup 2)
4394 "(rtx_equal_p (operands[4], operands[2])
4395 || rtx_equal_p (operands[4], operands[3]))"
4396 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4397 (set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))]
4399 operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);
4400 cris_order_for_addsi3 (operands, 2);
4403 ;; op(s|u).S1 [rx=rx+rz.S2],ry
4407 [(set (match_operand 0 "register_operand" "")
4409 6 "cris_operand_extend_operator"
4410 [(match_operand 1 "register_operand" "")
4412 7 "cris_extend_operator"
4414 (mult:SI (match_operand:SI 2 "register_operand" "")
4415 (match_operand:SI 3 "const_int_operand" ""))
4416 (match_operand:SI 4 "register_operand" "")))])]))
4417 (set (match_operand:SI 5 "register_operand" "")
4418 (plus:SI (mult:SI (match_dup 2)
4421 "REG_P (operands[4])
4422 && REG_P (operands[5])
4423 && REGNO (operands[5]) == REGNO (operands[4])"
4424 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4426 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 8)]))]
4427 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[7]), GET_MODE (operands[7]),
4428 replace_equiv_address (XEXP (operands[7], 0),
4431 ;; op(s|u).S1 [rx=rx+i],ry
4435 [(set (match_operand 0 "register_operand" "")
4437 5 "cris_operand_extend_operator"
4438 [(match_operand 1 "register_operand" "")
4440 6 "cris_extend_operator"
4442 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4443 (match_operand:SI 3 "cris_bdap_operand" "")
4445 (set (match_operand:SI 4 "register_operand" "")
4446 (plus:SI (match_dup 2)
4448 "(rtx_equal_p (operands[4], operands[2])
4449 || rtx_equal_p (operands[4], operands[3]))"
4450 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4451 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))]
4453 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
4454 replace_equiv_address (XEXP (operands[6], 0),
4456 cris_order_for_addsi3 (operands, 2);
4459 ;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound)
4463 [(set (match_operand 0 "register_operand" "")
4465 7 "cris_plus_or_bound_operator"
4467 6 "cris_extend_operator"
4469 (mult:SI (match_operand:SI 2 "register_operand" "")
4470 (match_operand:SI 3 "const_int_operand" ""))
4471 (match_operand:SI 4 "register_operand" "")))])
4472 (match_operand 1 "register_operand" "")]))
4473 (set (match_operand:SI 5 "register_operand" "")
4474 (plus:SI (mult:SI (match_dup 2)
4477 "REG_P (operands[4]) && REG_P (operands[5])
4478 && REGNO (operands[5]) == REGNO (operands[4])"
4479 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4481 (set (match_dup 0) (match_op_dup 6 [(match_dup 8) (match_dup 1)]))]
4482 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
4483 replace_equiv_address (XEXP (operands[6], 0),
4486 ;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound)
4490 [(set (match_operand 0 "register_operand" "")
4492 6 "cris_plus_or_bound_operator"
4494 5 "cris_extend_operator"
4496 (match_operand:SI 2 "cris_bdap_operand" "")
4497 (match_operand:SI 3 "cris_bdap_operand" "")))])
4498 (match_operand 1 "register_operand" "")]))
4499 (set (match_operand:SI 4 "register_operand" "")
4500 (plus:SI (match_dup 2)
4502 "(rtx_equal_p (operands[4], operands[2])
4503 || rtx_equal_p (operands[4], operands[3]))"
4504 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4505 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4507 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[5]), GET_MODE (operands[5]),
4508 replace_equiv_address (XEXP (operands[5], 0),
4510 cris_order_for_addsi3 (operands, 2);
4513 ;; Splits for addressing prefixes that have no side-effects, so we can
4514 ;; fill a delay slot. Never split if we lose something, though.
4517 ;; move [indirect_ref],rx
4518 ;; where indirect ref = {const, [r+], [r]}, it costs as much as
4519 ;; move indirect_ref,rx
4521 ;; Take care not to allow indirect_ref = register.
4523 ;; We're not allowed to generate copies of registers with different mode
4524 ;; until after reload; copying pseudos upsets reload. CVS as of
4525 ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in
4526 ;; cselib_invalidate_regno.
4528 (define_split ; indir_to_reg_split
4529 [(set (match_operand 0 "register_operand" "")
4530 (match_operand 1 "indirect_operand" ""))]
4532 && REG_P (operands[0])
4533 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4534 && (MEM_P (XEXP (operands[1], 0)) || CONSTANT_P (XEXP (operands[1], 0)))
4535 && REGNO (operands[0]) < CRIS_LAST_GENERAL_REGISTER"
4536 [(set (match_dup 2) (match_dup 4))
4537 (set (match_dup 0) (match_dup 3))]
4538 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4539 operands[3] = replace_equiv_address (operands[1], operands[2]);
4540 operands[4] = XEXP (operands[1], 0);")
4542 ;; As the above, but MOVS and MOVU.
4545 [(set (match_operand 0 "register_operand" "")
4547 4 "cris_extend_operator"
4548 [(match_operand 1 "indirect_operand" "")]))]
4550 && REG_P (operands[0])
4551 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4552 && (MEM_P (XEXP (operands[1], 0))
4553 || CONSTANT_P (XEXP (operands[1], 0)))"
4554 [(set (match_dup 2) (match_dup 5))
4555 (set (match_dup 0) (match_op_dup 4 [(match_dup 3)]))]
4556 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4557 operands[3] = replace_equiv_address (XEXP (operands[4], 0), operands[2]);
4558 operands[5] = XEXP (operands[1], 0);")
4560 ;; Various peephole optimizations.
4562 ;; Watch out: when you exchange one set of instructions for another, the
4563 ;; condition codes setting must be the same, or you have to CC_INIT or
4564 ;; whatever is appropriate, in the pattern before you emit the
4565 ;; assembly text. This is best done here, not in cris_notice_update_cc,
4566 ;; to keep changes local to their cause.
4568 ;; Do not add patterns that you do not know will be matched.
4569 ;; Please also add a self-contained testcase.
4571 ;; We have trouble with and:s and shifts. Maybe something is broken in
4572 ;; gcc? Or it could just be that bit-field insn expansion is a bit
4573 ;; suboptimal when not having extzv insns.
4574 ;; Testcase for the following four peepholes: gcc.dg/cris-peep2-xsrand.c
4576 (define_peephole2 ; asrandb (peephole casesi+31)
4577 [(set (match_operand:SI 0 "register_operand" "")
4578 (ashiftrt:SI (match_dup 0)
4579 (match_operand:SI 1 "const_int_operand" "")))
4581 (and:SI (match_dup 0)
4582 (match_operand 2 "const_int_operand" "")))]
4583 "INTVAL (operands[2]) > 31
4584 && INTVAL (operands[2]) < 255
4585 && INTVAL (operands[1]) > 23
4586 /* Check that the and-operation enables us to use logical-shift. */
4587 && (INTVAL (operands[2])
4588 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
4589 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4590 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
4591 ;; FIXME: CC0 is valid except for the M bit.
4593 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
4594 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
4597 (define_peephole2 ; asrandw (peephole casesi+32)
4598 [(set (match_operand:SI 0 "register_operand" "")
4599 (ashiftrt:SI (match_dup 0)
4600 (match_operand:SI 1 "const_int_operand" "")))
4602 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4603 "INTVAL (operands[2]) > 31
4604 && INTVAL (operands[2]) < 65535
4605 && INTVAL (operands[2]) != 255
4606 && INTVAL (operands[1]) > 15
4607 /* Check that the and-operation enables us to use logical-shift. */
4608 && (INTVAL (operands[2])
4609 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
4610 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4611 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
4612 ;; FIXME: CC0 is valid except for the M bit.
4614 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4615 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
4618 (define_peephole2 ; lsrandb (peephole casesi+33)
4619 [(set (match_operand:SI 0 "register_operand" "")
4620 (lshiftrt:SI (match_dup 0)
4621 (match_operand:SI 1 "const_int_operand" "")))
4623 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4624 "INTVAL (operands[2]) > 31
4625 && INTVAL (operands[2]) < 255
4626 && INTVAL (operands[1]) > 23"
4627 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4628 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
4629 ;; FIXME: CC0 is valid except for the M bit.
4631 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
4632 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
4635 (define_peephole2 ; lsrandw (peephole casesi+34)
4636 [(set (match_operand:SI 0 "register_operand" "")
4637 (lshiftrt:SI (match_dup 0)
4638 (match_operand:SI 1 "const_int_operand" "")))
4640 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4641 "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535
4642 && INTVAL (operands[2]) != 255
4643 && INTVAL (operands[1]) > 15"
4644 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4645 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
4646 ;; FIXME: CC0 is valid except for the M bit.
4648 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4649 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
4657 ;; move [rx=rx+n],ry
4658 ;; when -128 <= n <= 127.
4659 ;; This will reduce the size of the assembler code for n = [-128..127],
4660 ;; and speed up accordingly. Don't match if the previous insn is
4661 ;; (set rx rz) because that combination is matched by another peephole.
4662 ;; No stable test-case.
4664 (define_peephole2 ; moversideqi (peephole casesi+35)
4665 [(set (match_operand:SI 0 "register_operand" "")
4666 (plus:SI (match_operand:SI 1 "register_operand" "")
4667 (match_operand:SI 2 "const_int_operand" "")))
4668 (set (match_operand 3 "register_operand" "")
4669 (match_operator 4 "cris_mem_op" [(match_dup 0)]))]
4670 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
4671 && REGNO (operands[3]) != REGNO (operands[0])
4672 && (BASE_P (operands[1]) || BASE_P (operands[2]))
4673 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4674 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4675 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)
4676 && TARGET_SIDE_EFFECT_PREFIXES"
4678 [(set (match_dup 3) (match_dup 5))
4679 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4680 ;; Checking the previous insn is a bit too awkward for the condition.
4682 rtx prev = prev_nonnote_insn (curr_insn);
4683 if (prev != NULL_RTX)
4685 rtx set = single_set (prev);
4687 && REG_S_P (SET_DEST (set))
4688 && REGNO (SET_DEST (set)) == REGNO (operands[0])
4689 && REG_S_P (SET_SRC (set)))
4693 = replace_equiv_address (operands[4],
4694 gen_rtx_PLUS (SImode,
4695 operands[1], operands[2]));
4698 ;; Vice versa: move ry,[rx=rx+n]
4700 (define_peephole2 ; movemsideqi (peephole casesi+36)
4701 [(set (match_operand:SI 0 "register_operand" "")
4702 (plus:SI (match_operand:SI 1 "register_operand" "")
4703 (match_operand:SI 2 "const_int_operand" "")))
4704 (set (match_operator 3 "cris_mem_op" [(match_dup 0)])
4705 (match_operand 4 "register_operand" ""))]
4706 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
4707 && REGNO (operands[4]) != REGNO (operands[0])
4708 && (BASE_P (operands[1]) || BASE_P (operands[2]))
4709 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4710 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4711 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)
4712 && TARGET_SIDE_EFFECT_PREFIXES"
4714 [(set (match_dup 5) (match_dup 4))
4715 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4717 = replace_equiv_address (operands[3],
4718 gen_rtx_PLUS (SImode,
4719 operands[1], operands[2]));")
4721 ;; As above, change:
4725 ;; op.d [rx=rx+n],ry
4726 ;; Saves when n = [-128..127].
4728 ;; Splitting and joining combinations for side-effect modes are slightly
4729 ;; out of hand. They probably will not save the time they take typing in,
4730 ;; not to mention the bugs that creep in. FIXME: Get rid of as many of
4731 ;; the splits and peepholes as possible.
4732 ;; No stable test-case.
4734 (define_peephole2 ; mover2side (peephole casesi+37)
4735 [(set (match_operand:SI 0 "register_operand" "")
4736 (plus:SI (match_operand:SI 1 "register_operand" "")
4737 (match_operand:SI 2 "const_int_operand" "")))
4738 (set (match_operand 3 "register_operand" "")
4739 (match_operator 4 "cris_orthogonal_operator"
4742 5 "cris_mem_op" [(match_dup 0)])]))]
4743 ;; FIXME: What about DFmode?
4744 ;; Change to GET_MODE_SIZE (GET_MODE (operands[3])) <= UNITS_PER_WORD?
4745 "GET_MODE (operands[3]) != DImode
4746 && REGNO (operands[0]) != REGNO (operands[3])
4747 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4748 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4749 && INTVAL (operands[2]) >= -128
4750 && INTVAL (operands[2]) <= 127
4751 && TARGET_SIDE_EFFECT_PREFIXES"
4753 [(set (match_dup 3) (match_op_dup 4 [(match_dup 3) (match_dup 6)]))
4754 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4756 = replace_equiv_address (operands[5],
4757 gen_rtx_PLUS (SImode,
4758 operands[1], operands[2]));")
4760 ;; Sometimes, for some reason the pattern
4764 ;; will occur. Solve this, and likewise for to-memory.
4765 ;; No stable test-case.
4767 (define_peephole2 ; moverside (peephole casesi+38)
4768 [(set (match_operand:SI 0 "register_operand" "")
4769 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
4771 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
4772 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
4773 (set (match_operand 4 "register_operand" "")
4774 (match_operator 5 "cris_mem_op" [(match_dup 0)]))]
4775 "(rtx_equal_p (operands[2], operands[0])
4776 || rtx_equal_p (operands[3], operands[0]))
4777 && cris_side_effect_mode_ok (PLUS, operands, 0,
4778 (REG_S_P (operands[1])
4780 : (rtx_equal_p (operands[2], operands[0])
4782 (! REG_S_P (operands[1])
4784 : (rtx_equal_p (operands[2], operands[0])
4788 [(set (match_dup 4) (match_dup 6))
4789 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
4792 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
4794 /* Make sure we have canonical RTX so we match the insn pattern -
4795 not a constant in the first operand. We also require the order
4796 (plus reg mem) to match the final pattern. */
4797 if (CONSTANT_P (otherop) || MEM_P (otherop))
4799 operands[7] = operands[1];
4800 operands[8] = otherop;
4804 operands[7] = otherop;
4805 operands[8] = operands[1];
4808 = replace_equiv_address (operands[5],
4809 gen_rtx_PLUS (SImode,
4810 operands[7], operands[8]));
4813 ;; As above but to memory.
4814 ;; FIXME: Split movemside and moverside into variants and prune
4815 ;; the ones that don't trig.
4816 ;; No stable test-case.
4818 (define_peephole2 ; movemside (peephole casesi+39)
4819 [(set (match_operand:SI 0 "register_operand" "")
4820 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
4822 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
4823 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
4824 (set (match_operator 4 "cris_mem_op" [(match_dup 0)])
4825 (match_operand 5 "register_operand" ""))]
4826 "(rtx_equal_p (operands[2], operands[0])
4827 || rtx_equal_p (operands[3], operands[0]))
4828 && cris_side_effect_mode_ok (PLUS, operands, 0,
4829 (REG_S_P (operands[1])
4831 : (rtx_equal_p (operands[2], operands[0])
4833 (! REG_S_P (operands[1])
4835 : (rtx_equal_p (operands[2], operands[0])
4839 [(set (match_dup 6) (match_dup 5))
4840 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
4843 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
4845 /* Make sure we have canonical RTX so we match the insn pattern -
4846 not a constant in the first operand. We also require the order
4847 (plus reg mem) to match the final pattern. */
4848 if (CONSTANT_P (otherop) || MEM_P (otherop))
4850 operands[7] = operands[1];
4851 operands[8] = otherop;
4855 operands[7] = otherop;
4856 operands[8] = operands[1];
4859 = replace_equiv_address (operands[4],
4860 gen_rtx_PLUS (SImode,
4861 operands[7], operands[8]));
4864 ;; Another spotted bad code:
4867 ;; No stable test-case.
4869 (define_peephole2 ; movei (peephole casesi+42)
4870 [(set (match_operand:SI 0 "register_operand" "")
4871 (match_operand:SI 1 "register_operand" ""))
4872 (set (match_operand 2 "register_operand" "")
4873 (match_operator 3 "cris_mem_op" [(match_dup 0)]))]
4874 "REGNO (operands[0]) == REGNO (operands[2])
4875 && (REGNO_REG_CLASS (REGNO (operands[0]))
4876 == REGNO_REG_CLASS (REGNO (operands[1])))
4877 && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD"
4878 [(set (match_dup 2) (match_dup 4))]
4879 "operands[4] = replace_equiv_address (operands[3], operands[1]);")
4881 ;; move.d [r10+16],r9
4884 ;; and.d [r10+16],r12,r9
4885 ;; With generalization of the operation, the size and the addressing mode.
4886 ;; This seems to be the result of a quirk in register allocation
4887 ;; missing the three-operand cases when having different predicates.
4888 ;; Maybe that it matters that it is a commutative operation.
4889 ;; This pattern helps that situation, but there's still the increased
4890 ;; register pressure.
4891 ;; Note that adding the noncommutative variant did not show any matches
4892 ;; in ipps and cc1, so it's not here.
4893 ;; No stable test-case.
4895 (define_peephole2 ; op3 (peephole casesi+44)
4896 [(set (match_operand 0 "register_operand" "")
4900 (match_operand:SI 1 "cris_bdap_biap_operand" "")
4901 (match_operand:SI 2 "cris_bdap_biap_operand" ""))]))
4904 5 "cris_commutative_orth_op"
4905 [(match_operand 3 "register_operand" "")
4906 (match_operand 4 "register_operand" "")]))]
4907 "(rtx_equal_p (operands[3], operands[0])
4908 || rtx_equal_p (operands[4], operands[0]))
4909 && ! rtx_equal_p (operands[3], operands[4])
4910 && (REG_S_P (operands[1]) || REG_S_P (operands[2]))
4911 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD"
4912 [(set (match_dup 0) (match_op_dup 5 [(match_dup 7) (match_dup 6)]))]
4914 = rtx_equal_p (operands[3], operands[0]) ? operands[4] : operands[3];")
4916 ;; I cannot tell GCC (2.1, 2.7.2) how to correctly reload an instruction
4918 ;; and.b some_byte,const,reg_32
4919 ;; where reg_32 is the destination of the "three-address" code optimally.
4921 ;; movu.b some_byte,reg_32
4922 ;; and.b const,reg_32
4923 ;; but is turns into:
4924 ;; move.b some_byte,reg_32
4925 ;; and.d const,reg_32
4927 ;; Testcases: gcc.dg/cris-peep2-andu1.c gcc.dg/cris-peep2-andu2.c
4929 (define_peephole2 ; andu (casesi+45)
4930 [(set (match_operand:SI 0 "register_operand" "")
4931 (match_operand:SI 1 "nonimmediate_operand" ""))
4932 (set (match_operand:SI 2 "register_operand" "")
4933 (and:SI (match_dup 0)
4934 (match_operand:SI 3 "const_int_operand" "")))]
4935 ;; Since the size of the memory access could be made different here,
4936 ;; don't do this for a mem-volatile access.
4937 "REGNO (operands[2]) == REGNO (operands[0])
4938 && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0
4939 && !CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'I')
4940 && !side_effects_p (operands[1])"
4941 ;; FIXME: CC0 valid except for M (i.e. CC_NOT_NEGATIVE).
4942 [(set (match_dup 0) (match_dup 4))
4943 (set (match_dup 5) (match_dup 6))]
4945 enum machine_mode zmode = INTVAL (operands[3]) <= 255 ? QImode : HImode;
4946 enum machine_mode amode
4947 = CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'O') ? SImode : zmode;
4949 = (REG_S_P (operands[1])
4950 ? gen_rtx_REG (zmode, REGNO (operands[1]))
4951 : adjust_address (operands[1], zmode, 0));
4953 = gen_rtx_ZERO_EXTEND (SImode, op1);
4954 operands[5] = gen_rtx_REG (amode, REGNO (operands[0]));
4956 = gen_rtx_AND (amode, gen_rtx_REG (amode, REGNO (operands[0])),
4957 GEN_INT (trunc_int_for_mode (INTVAL (operands[3]),
4959 ? QImode : amode)));
4962 ;; Try and avoid GOTPLT reads escaping a call: transform them into
4963 ;; PLT. Curiously (but thankfully), peepholes for instructions
4964 ;; *without side-effects* that just feed a call (or call_value) are
4965 ;; not matched neither in a build or test-suite, so those patterns are
4968 ;; A "normal" move where we don't check the consumer.
4970 (define_peephole2 ; gotplt-to-plt
4972 (match_operand:SI 0 "register_operand" "")
4976 (reg:SI CRIS_GOT_REGNUM)
4978 (unspec:SI [(match_operand:SI 2 "cris_general_operand_or_symbol" "")]
4979 CRIS_UNSPEC_PLTGOTREAD)))]))]
4981 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
4982 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)"
4983 [(set (match_dup 0) (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL)))
4984 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))]
4987 ;; And one set with a side-effect getting the PLTGOT offset.
4988 ;; First call and call_value variants.
4990 (define_peephole2 ; gotplt-to-plt-side-call
4993 (match_operand:SI 0 "register_operand" "")
4997 (reg:SI CRIS_GOT_REGNUM)
4999 (unspec:SI [(match_operand:SI
5000 2 "cris_general_operand_or_symbol" "")]
5001 CRIS_UNSPEC_PLTGOTREAD)))]))
5002 (set (match_operand:SI 3 "register_operand" "")
5003 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5005 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])
5006 (parallel [(call (mem:QI (match_dup 0))
5007 (match_operand 4 "" ""))
5008 (clobber (reg:SI CRIS_SRP_REGNUM))])]
5010 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5011 && peep2_reg_dead_p (2, operands[0])"
5012 [(parallel [(call (mem:QI (match_dup 1))
5014 (clobber (reg:SI CRIS_SRP_REGNUM))
5016 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5018 (unspec:SI [(match_dup 2)]
5019 CRIS_UNSPEC_PLTGOTREAD))))])]
5022 (define_peephole2 ; gotplt-to-plt-side-call-value
5025 (match_operand:SI 0 "register_operand" "")
5029 (reg:SI CRIS_GOT_REGNUM)
5031 (unspec:SI [(match_operand:SI
5032 2 "cris_general_operand_or_symbol" "")]
5033 CRIS_UNSPEC_PLTGOTREAD)))]))
5034 (set (match_operand:SI 3 "register_operand" "")
5035 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5037 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])
5038 (parallel [(set (match_operand 5 "" "")
5039 (call (mem:QI (match_dup 0))
5040 (match_operand 4 "" "")))
5041 (clobber (reg:SI CRIS_SRP_REGNUM))])]
5043 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5044 && peep2_reg_dead_p (2, operands[0])"
5045 [(parallel [(set (match_dup 5)
5046 (call (mem:QI (match_dup 1))
5048 (clobber (reg:SI CRIS_SRP_REGNUM))
5050 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5052 (unspec:SI [(match_dup 2)]
5053 CRIS_UNSPEC_PLTGOTREAD))))])]
5056 (define_peephole2 ; gotplt-to-plt-side
5059 (match_operand:SI 0 "register_operand" "")
5063 (reg:SI CRIS_GOT_REGNUM)
5065 (unspec:SI [(match_operand:SI
5066 2 "cris_general_operand_or_symbol" "")]
5067 CRIS_UNSPEC_PLTGOTREAD)))]))
5068 (set (match_operand:SI 3 "register_operand" "")
5069 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5071 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])]
5073 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5074 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)"
5076 (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD)))
5077 (set (match_dup 3) (plus:SI (match_dup 3) (reg:SI CRIS_GOT_REGNUM)))
5079 (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL)))
5080 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))]
5085 ;; comment-start: ";; "
5086 ;; eval: (set-syntax-table (copy-sequence (syntax-table)))
5087 ;; eval: (modify-syntax-entry ?[ "(]")
5088 ;; eval: (modify-syntax-entry ?] ")[")
5089 ;; eval: (modify-syntax-entry ?{ "(}")
5090 ;; eval: (modify-syntax-entry ?} "){")
5091 ;; eval: (setq indent-tabs-mode t)