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Merge -r 127928:132243 from trunk
[official-gcc.git] / gcc / config / arm / arm.h
blobf0f0d2dc1dba6302a7762e11818699355e363c81
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 3, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING3. If not see
23 <http://www.gnu.org/licenses/>. */
24
25 #ifndef GCC_ARM_H
26 #define GCC_ARM_H
27
28 #include "config/vxworks-dummy.h"
29
30 /* The architecture define. */
31 extern char arm_arch_name[];
32
33 /* Target CPU builtins. */
34 #define TARGET_CPU_CPP_BUILTINS() \
35 do \
36 { \
37 /* Define __arm__ even when in thumb mode, for \
38 consistency with armcc. */ \
39 builtin_define ("__arm__"); \
40 builtin_define ("__APCS_32__"); \
41 if (TARGET_THUMB) \
42 builtin_define ("__thumb__"); \
43 if (TARGET_THUMB2) \
44 builtin_define ("__thumb2__"); \
45 \
46 if (TARGET_BIG_END) \
47 { \
48 builtin_define ("__ARMEB__"); \
49 if (TARGET_THUMB) \
50 builtin_define ("__THUMBEB__"); \
51 if (TARGET_LITTLE_WORDS) \
52 builtin_define ("__ARMWEL__"); \
53 } \
54 else \
55 { \
56 builtin_define ("__ARMEL__"); \
57 if (TARGET_THUMB) \
58 builtin_define ("__THUMBEL__"); \
59 } \
60 \
61 if (TARGET_SOFT_FLOAT) \
62 builtin_define ("__SOFTFP__"); \
63 \
64 if (TARGET_VFP) \
65 builtin_define ("__VFP_FP__"); \
66 \
67 if (TARGET_NEON) \
68 builtin_define ("__ARM_NEON__"); \
69 \
70 /* Add a define for interworking. \
71 Needed when building libgcc.a. */ \
72 if (arm_cpp_interwork) \
73 builtin_define ("__THUMB_INTERWORK__"); \
74 \
75 builtin_assert ("cpu=arm"); \
76 builtin_assert ("machine=arm"); \
77 \
78 builtin_define (arm_arch_name); \
79 if (arm_arch_cirrus) \
80 builtin_define ("__MAVERICK__"); \
81 if (arm_arch_xscale) \
82 builtin_define ("__XSCALE__"); \
83 if (arm_arch_iwmmxt) \
84 builtin_define ("__IWMMXT__"); \
85 if (TARGET_AAPCS_BASED) \
86 builtin_define ("__ARM_EABI__"); \
87 } while (0)
88
89 /* The various ARM cores. */
90 enum processor_type
91 {
92 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
93 IDENT,
94 #include "arm-cores.def"
95 #undef ARM_CORE
96 /* Used to indicate that no processor has been specified. */
97 arm_none
98 };
99
100 enum target_cpus
101 {
102 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
103 TARGET_CPU_##IDENT,
104 #include "arm-cores.def"
105 #undef ARM_CORE
106 TARGET_CPU_generic
107 };
108
109 /* The processor for which instructions should be scheduled. */
110 extern enum processor_type arm_tune;
111
112 typedef enum arm_cond_code
113 {
114 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
115 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
116 }
117 arm_cc;
118
119 extern arm_cc arm_current_cc;
120
121 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
122
123 extern int arm_target_label;
124 extern int arm_ccfsm_state;
125 extern GTY(()) rtx arm_target_insn;
126 /* Define the information needed to generate branch insns. This is
127 stored from the compare operation. */
128 extern GTY(()) rtx arm_compare_op0;
129 extern GTY(()) rtx arm_compare_op1;
130 /* The label of the current constant pool. */
131 extern rtx pool_vector_label;
132 /* Set to 1 when a return insn is output, this means that the epilogue
133 is not needed. */
134 extern int return_used_this_function;
135 /* Callback to output language specific object attributes. */
136 extern void (*arm_lang_output_object_attributes_hook)(void);
137 \f
138 /* Just in case configure has failed to define anything. */
139 #ifndef TARGET_CPU_DEFAULT
140 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
141 #endif
142
143
144 #undef CPP_SPEC
145 #define CPP_SPEC "%(subtarget_cpp_spec) \
146 %{msoft-float:%{mhard-float: \
147 %e-msoft-float and -mhard_float may not be used together}} \
148 %{mbig-endian:%{mlittle-endian: \
149 %e-mbig-endian and -mlittle-endian may not be used together}}"
150
151 #ifndef CC1_SPEC
152 #define CC1_SPEC ""
153 #endif
154
155 /* This macro defines names of additional specifications to put in the specs
156 that can be used in various specifications like CC1_SPEC. Its definition
157 is an initializer with a subgrouping for each command option.
158
159 Each subgrouping contains a string constant, that defines the
160 specification name, and a string constant that used by the GCC driver
161 program.
162
163 Do not define this macro if it does not need to do anything. */
164 #define EXTRA_SPECS \
165 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
166 SUBTARGET_EXTRA_SPECS
167
168 #ifndef SUBTARGET_EXTRA_SPECS
169 #define SUBTARGET_EXTRA_SPECS
170 #endif
171
172 #ifndef SUBTARGET_CPP_SPEC
173 #define SUBTARGET_CPP_SPEC ""
174 #endif
175 \f
176 /* Run-time Target Specification. */
177 #ifndef TARGET_VERSION
178 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
179 #endif
180
181 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
182 /* Use hardware floating point instructions. */
183 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
184 /* Use hardware floating point calling convention. */
185 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
186 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
187 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
188 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
189 #define TARGET_IWMMXT (arm_arch_iwmmxt)
190 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
191 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
192 #define TARGET_ARM (! TARGET_THUMB)
193 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
194 #define TARGET_BACKTRACE (leaf_function_p () \
195 ? TARGET_TPCS_LEAF_FRAME \
196 : TARGET_TPCS_FRAME)
197 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
198 #define TARGET_AAPCS_BASED \
199 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
200
201 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
202 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
203
204 /* Only 16-bit thumb code. */
205 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
206 /* Arm or Thumb-2 32-bit code. */
207 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
208 /* 32-bit Thumb-2 code. */
209 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
210
211 /* The following two macros concern the ability to execute coprocessor
212 instructions for VFPv3 or NEON. TARGET_VFP3 is currently only ever
213 tested when we know we are generating for VFP hardware; we need to
214 be more careful with TARGET_NEON as noted below. */
215
216 /* FPU is VFPv3 (with twice the number of D registers). Setting the FPU to
217 Neon automatically enables VFPv3 too. */
218 #define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \
219 && (arm_fpu_arch == FPUTYPE_VFP3 \
220 || arm_fpu_arch == FPUTYPE_NEON))
221 /* FPU supports Neon instructions. The setting of this macro gets
222 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
223 and TARGET_HARD_FLOAT to ensure that NEON instructions are
224 available. */
225 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
226 && arm_fp_model == ARM_FP_MODEL_VFP \
227 && arm_fpu_arch == FPUTYPE_NEON)
228
229 /* "DSP" multiply instructions, eg. SMULxy. */
230 #define TARGET_DSP_MULTIPLY \
231 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
232 /* Integer SIMD instructions, and extend-accumulate instructions. */
233 #define TARGET_INT_SIMD \
234 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
235
236 /* We could use unified syntax for arm mode, but for now we just use it
237 for Thumb-2. */
238 #define TARGET_UNIFIED_ASM TARGET_THUMB2
239
240
241 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
242 then TARGET_AAPCS_BASED must be true -- but the converse does not
243 hold. TARGET_BPABI implies the use of the BPABI runtime library,
244 etc., in addition to just the AAPCS calling conventions. */
245 #ifndef TARGET_BPABI
246 #define TARGET_BPABI false
247 #endif
248
249 /* Support for a compile-time default CPU, et cetera. The rules are:
250 --with-arch is ignored if -march or -mcpu are specified.
251 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
252 by --with-arch.
253 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
254 by -march).
255 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
256 specified.
257 --with-fpu is ignored if -mfpu is specified.
258 --with-abi is ignored is -mabi is specified. */
259 #define OPTION_DEFAULT_SPECS \
260 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
261 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
262 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
263 {"float", \
264 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
265 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
266 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
267 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
268
269 /* Which floating point model to use. */
270 enum arm_fp_model
271 {
272 ARM_FP_MODEL_UNKNOWN,
273 /* FPA model (Hardware or software). */
274 ARM_FP_MODEL_FPA,
275 /* Cirrus Maverick floating point model. */
276 ARM_FP_MODEL_MAVERICK,
277 /* VFP floating point model. */
278 ARM_FP_MODEL_VFP
279 };
280
281 extern enum arm_fp_model arm_fp_model;
282
283 /* Which floating point hardware is available. Also update
284 fp_model_for_fpu in arm.c when adding entries to this list. */
285 enum fputype
286 {
287 /* No FP hardware. */
288 FPUTYPE_NONE,
289 /* Full FPA support. */
290 FPUTYPE_FPA,
291 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
292 FPUTYPE_FPA_EMU2,
293 /* Emulated FPA hardware, Issue 3 emulator. */
294 FPUTYPE_FPA_EMU3,
295 /* Cirrus Maverick floating point co-processor. */
296 FPUTYPE_MAVERICK,
297 /* VFP. */
298 FPUTYPE_VFP,
299 /* VFPv3. */
300 FPUTYPE_VFP3,
301 /* Neon. */
302 FPUTYPE_NEON
303 };
304
305 /* Recast the floating point class to be the floating point attribute. */
306 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
307
308 /* What type of floating point to tune for */
309 extern enum fputype arm_fpu_tune;
310
311 /* What type of floating point instructions are available */
312 extern enum fputype arm_fpu_arch;
313
314 enum float_abi_type
315 {
316 ARM_FLOAT_ABI_SOFT,
317 ARM_FLOAT_ABI_SOFTFP,
318 ARM_FLOAT_ABI_HARD
319 };
320
321 extern enum float_abi_type arm_float_abi;
322
323 #ifndef TARGET_DEFAULT_FLOAT_ABI
324 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
325 #endif
326
327 /* Which ABI to use. */
328 enum arm_abi_type
329 {
330 ARM_ABI_APCS,
331 ARM_ABI_ATPCS,
332 ARM_ABI_AAPCS,
333 ARM_ABI_IWMMXT,
334 ARM_ABI_AAPCS_LINUX
335 };
336
337 extern enum arm_abi_type arm_abi;
338
339 #ifndef ARM_DEFAULT_ABI
340 #define ARM_DEFAULT_ABI ARM_ABI_APCS
341 #endif
342
343 /* Which thread pointer access sequence to use. */
344 enum arm_tp_type {
345 TP_AUTO,
346 TP_SOFT,
347 TP_CP15
348 };
349
350 extern enum arm_tp_type target_thread_pointer;
351
352 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
353 extern int arm_arch3m;
354
355 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
356 extern int arm_arch4;
357
358 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
359 extern int arm_arch4t;
360
361 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
362 extern int arm_arch5;
363
364 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
365 extern int arm_arch5e;
366
367 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
368 extern int arm_arch6;
369
370 /* Nonzero if instructions not present in the 'M' profile can be used. */
371 extern int arm_arch_notm;
372
373 /* Nonzero if this chip can benefit from load scheduling. */
374 extern int arm_ld_sched;
375
376 /* Nonzero if generating thumb code. */
377 extern int thumb_code;
378
379 /* Nonzero if this chip is a StrongARM. */
380 extern int arm_tune_strongarm;
381
382 /* Nonzero if this chip is a Cirrus variant. */
383 extern int arm_arch_cirrus;
384
385 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
386 extern int arm_arch_iwmmxt;
387
388 /* Nonzero if this chip is an XScale. */
389 extern int arm_arch_xscale;
390
391 /* Nonzero if tuning for XScale. */
392 extern int arm_tune_xscale;
393
394 /* Nonzero if tuning for stores via the write buffer. */
395 extern int arm_tune_wbuf;
396
397 /* Nonzero if we should define __THUMB_INTERWORK__ in the
398 preprocessor.
399 XXX This is a bit of a hack, it's intended to help work around
400 problems in GLD which doesn't understand that armv5t code is
401 interworking clean. */
402 extern int arm_cpp_interwork;
403
404 /* Nonzero if chip supports Thumb 2. */
405 extern int arm_arch_thumb2;
406
407 /* Nonzero if chip supports integer division instruction. */
408 extern int arm_arch_hwdiv;
409
410 #ifndef TARGET_DEFAULT
411 #define TARGET_DEFAULT (MASK_APCS_FRAME)
412 #endif
413
414 /* The frame pointer register used in gcc has nothing to do with debugging;
415 that is controlled by the APCS-FRAME option. */
416 #define CAN_DEBUG_WITHOUT_FP
417
418 #define OVERRIDE_OPTIONS arm_override_options ()
419
420 /* Nonzero if PIC code requires explicit qualifiers to generate
421 PLT and GOT relocs rather than the assembler doing so implicitly.
422 Subtargets can override these if required. */
423 #ifndef NEED_GOT_RELOC
424 #define NEED_GOT_RELOC 0
425 #endif
426 #ifndef NEED_PLT_RELOC
427 #define NEED_PLT_RELOC 0
428 #endif
429
430 /* Nonzero if we need to refer to the GOT with a PC-relative
431 offset. In other words, generate
432
433 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
434
435 rather than
436
437 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
438
439 The default is true, which matches NetBSD. Subtargets can
440 override this if required. */
441 #ifndef GOT_PCREL
442 #define GOT_PCREL 1
443 #endif
444 \f
445 /* Target machine storage Layout. */
446
447
448 /* Define this macro if it is advisable to hold scalars in registers
449 in a wider mode than that declared by the program. In such cases,
450 the value is constrained to be within the bounds of the declared
451 type, but kept valid in the wider mode. The signedness of the
452 extension may differ from that of the type. */
453
454 /* It is far faster to zero extend chars than to sign extend them */
455
456 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
457 if (GET_MODE_CLASS (MODE) == MODE_INT \
458 && GET_MODE_SIZE (MODE) < 4) \
459 { \
460 if (MODE == QImode) \
461 UNSIGNEDP = 1; \
462 else if (MODE == HImode) \
463 UNSIGNEDP = 1; \
464 (MODE) = SImode; \
465 }
466
467 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
468 if ((GET_MODE_CLASS (MODE) == MODE_INT \
469 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
470 && GET_MODE_SIZE (MODE) < 4) \
471 (MODE) = SImode; \
472
473 /* Define this if most significant bit is lowest numbered
474 in instructions that operate on numbered bit-fields. */
475 #define BITS_BIG_ENDIAN 0
476
477 /* Define this if most significant byte of a word is the lowest numbered.
478 Most ARM processors are run in little endian mode, so that is the default.
479 If you want to have it run-time selectable, change the definition in a
480 cover file to be TARGET_BIG_ENDIAN. */
481 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
482
483 /* Define this if most significant word of a multiword number is the lowest
484 numbered.
485 This is always false, even when in big-endian mode. */
486 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
487
488 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
489 on processor pre-defineds when compiling libgcc2.c. */
490 #if defined(__ARMEB__) && !defined(__ARMWEL__)
491 #define LIBGCC2_WORDS_BIG_ENDIAN 1
492 #else
493 #define LIBGCC2_WORDS_BIG_ENDIAN 0
494 #endif
495
496 /* Define this if most significant word of doubles is the lowest numbered.
497 The rules are different based on whether or not we use FPA-format,
498 VFP-format or some other floating point co-processor's format doubles. */
499 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
500
501 #define UNITS_PER_WORD 4
502
503 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
504 registers when autovectorizing for Neon, at least until multiple vector
505 widths are supported properly by the middle-end. */
506 #define UNITS_PER_SIMD_WORD \
507 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
508
509 /* True if natural alignment is used for doubleword types. */
510 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
511
512 #define DOUBLEWORD_ALIGNMENT 64
513
514 #define PARM_BOUNDARY 32
515
516 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
517
518 #define PREFERRED_STACK_BOUNDARY \
519 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
520
521 #define FUNCTION_BOUNDARY 32
522
523 /* The lowest bit is used to indicate Thumb-mode functions, so the
524 vbit must go into the delta field of pointers to member
525 functions. */
526 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
527
528 #define EMPTY_FIELD_BOUNDARY 32
529
530 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
531
532 /* XXX Blah -- this macro is used directly by libobjc. Since it
533 supports no vector modes, cut out the complexity and fall back
534 on BIGGEST_FIELD_ALIGNMENT. */
535 #ifdef IN_TARGET_LIBS
536 #define BIGGEST_FIELD_ALIGNMENT 64
537 #endif
538
539 /* Make strings word-aligned so strcpy from constants will be faster. */
540 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
541
542 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
543 ((TREE_CODE (EXP) == STRING_CST \
544 && !optimize_size \
545 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
546 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
547
548 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
549 value set in previous versions of this toolchain was 8, which produces more
550 compact structures. The command line option -mstructure_size_boundary=<n>
551 can be used to change this value. For compatibility with the ARM SDK
552 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
553 0020D) page 2-20 says "Structures are aligned on word boundaries".
554 The AAPCS specifies a value of 8. */
555 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
556 extern int arm_structure_size_boundary;
557
558 /* This is the value used to initialize arm_structure_size_boundary. If a
559 particular arm target wants to change the default value it should change
560 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
561 for an example of this. */
562 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
563 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
564 #endif
565
566 /* Nonzero if move instructions will actually fail to work
567 when given unaligned data. */
568 #define STRICT_ALIGNMENT 1
569
570 /* wchar_t is unsigned under the AAPCS. */
571 #ifndef WCHAR_TYPE
572 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
573
574 #define WCHAR_TYPE_SIZE BITS_PER_WORD
575 #endif
576
577 #ifndef SIZE_TYPE
578 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
579 #endif
580
581 #ifndef PTRDIFF_TYPE
582 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
583 #endif
584
585 /* AAPCS requires that structure alignment is affected by bitfields. */
586 #ifndef PCC_BITFIELD_TYPE_MATTERS
587 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
588 #endif
589
590 \f
591 /* Standard register usage. */
592
593 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
594 (S - saved over call).
595
596 r0 * argument word/integer result
597 r1-r3 argument word
598
599 r4-r8 S register variable
600 r9 S (rfp) register variable (real frame pointer)
601
602 r10 F S (sl) stack limit (used by -mapcs-stack-check)
603 r11 F S (fp) argument pointer
604 r12 (ip) temp workspace
605 r13 F S (sp) lower end of current stack frame
606 r14 (lr) link address/workspace
607 r15 F (pc) program counter
608
609 f0 floating point result
610 f1-f3 floating point scratch
611
612 f4-f7 S floating point variable
613
614 cc This is NOT a real register, but is used internally
615 to represent things that use or set the condition
616 codes.
617 sfp This isn't either. It is used during rtl generation
618 since the offset between the frame pointer and the
619 auto's isn't known until after register allocation.
620 afp Nor this, we only need this because of non-local
621 goto. Without it fp appears to be used and the
622 elimination code won't get rid of sfp. It tracks
623 fp exactly at all times.
624
625 *: See CONDITIONAL_REGISTER_USAGE */
626
627 /*
628 mvf0 Cirrus floating point result
629 mvf1-mvf3 Cirrus floating point scratch
630 mvf4-mvf15 S Cirrus floating point variable. */
631
632 /* s0-s15 VFP scratch (aka d0-d7).
633 s16-s31 S VFP variable (aka d8-d15).
634 vfpcc Not a real register. Represents the VFP condition
635 code flags. */
636
637 /* The stack backtrace structure is as follows:
638 fp points to here: | save code pointer | [fp]
639 | return link value | [fp, #-4]
640 | return sp value | [fp, #-8]
641 | return fp value | [fp, #-12]
642 [| saved r10 value |]
643 [| saved r9 value |]
644 [| saved r8 value |]
645 [| saved r7 value |]
646 [| saved r6 value |]
647 [| saved r5 value |]
648 [| saved r4 value |]
649 [| saved r3 value |]
650 [| saved r2 value |]
651 [| saved r1 value |]
652 [| saved r0 value |]
653 [| saved f7 value |] three words
654 [| saved f6 value |] three words
655 [| saved f5 value |] three words
656 [| saved f4 value |] three words
657 r0-r3 are not normally saved in a C function. */
658
659 /* 1 for registers that have pervasive standard uses
660 and are not available for the register allocator. */
661 #define FIXED_REGISTERS \
662 { \
663 0,0,0,0,0,0,0,0, \
664 0,0,0,0,0,1,0,1, \
665 0,0,0,0,0,0,0,0, \
666 1,1,1, \
667 1,1,1,1,1,1,1,1, \
668 1,1,1,1,1,1,1,1, \
669 1,1,1,1,1,1,1,1, \
670 1,1,1,1,1,1,1,1, \
671 1,1,1,1, \
672 1,1,1,1,1,1,1,1, \
673 1,1,1,1,1,1,1,1, \
674 1,1,1,1,1,1,1,1, \
675 1,1,1,1,1,1,1,1, \
676 1,1,1,1,1,1,1,1, \
677 1,1,1,1,1,1,1,1, \
678 1,1,1,1,1,1,1,1, \
679 1,1,1,1,1,1,1,1, \
680 1 \
681 }
682
683 /* 1 for registers not available across function calls.
684 These must include the FIXED_REGISTERS and also any
685 registers that can be used without being saved.
686 The latter must include the registers where values are returned
687 and the register where structure-value addresses are passed.
688 Aside from that, you can include as many other registers as you like.
689 The CC is not preserved over function calls on the ARM 6, so it is
690 easier to assume this for all. SFP is preserved, since FP is. */
691 #define CALL_USED_REGISTERS \
692 { \
693 1,1,1,1,0,0,0,0, \
694 0,0,0,0,1,1,1,1, \
695 1,1,1,1,0,0,0,0, \
696 1,1,1, \
697 1,1,1,1,1,1,1,1, \
698 1,1,1,1,1,1,1,1, \
699 1,1,1,1,1,1,1,1, \
700 1,1,1,1,1,1,1,1, \
701 1,1,1,1, \
702 1,1,1,1,1,1,1,1, \
703 1,1,1,1,1,1,1,1, \
704 1,1,1,1,1,1,1,1, \
705 1,1,1,1,1,1,1,1, \
706 1,1,1,1,1,1,1,1, \
707 1,1,1,1,1,1,1,1, \
708 1,1,1,1,1,1,1,1, \
709 1,1,1,1,1,1,1,1, \
710 1 \
711 }
712
713 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
714 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
715 #endif
716
717 #define CONDITIONAL_REGISTER_USAGE \
718 { \
719 int regno; \
720 \
721 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
722 { \
723 for (regno = FIRST_FPA_REGNUM; \
724 regno <= LAST_FPA_REGNUM; ++regno) \
725 fixed_regs[regno] = call_used_regs[regno] = 1; \
726 } \
727 \
728 if (TARGET_THUMB && optimize_size) \
729 { \
730 /* When optimizing for size, it's better not to use \
731 the HI regs, because of the overhead of stacking \
732 them. */ \
733 /* ??? Is this still true for thumb2? */ \
734 for (regno = FIRST_HI_REGNUM; \
735 regno <= LAST_HI_REGNUM; ++regno) \
736 fixed_regs[regno] = call_used_regs[regno] = 1; \
737 } \
738 \
739 /* The link register can be clobbered by any branch insn, \
740 but we have no way to track that at present, so mark \
741 it as unavailable. */ \
742 if (TARGET_THUMB1) \
743 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
744 \
745 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
746 { \
747 if (TARGET_MAVERICK) \
748 { \
749 for (regno = FIRST_FPA_REGNUM; \
750 regno <= LAST_FPA_REGNUM; ++ regno) \
751 fixed_regs[regno] = call_used_regs[regno] = 1; \
752 for (regno = FIRST_CIRRUS_FP_REGNUM; \
753 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
754 { \
755 fixed_regs[regno] = 0; \
756 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
757 } \
758 } \
759 if (TARGET_VFP) \
760 { \
761 /* VFPv3 registers are disabled when earlier VFP \
762 versions are selected due to the definition of \
763 LAST_VFP_REGNUM. */ \
764 for (regno = FIRST_VFP_REGNUM; \
765 regno <= LAST_VFP_REGNUM; ++ regno) \
766 { \
767 fixed_regs[regno] = 0; \
768 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
769 || regno >= FIRST_VFP_REGNUM + 32; \
770 } \
771 } \
772 } \
773 \
774 if (TARGET_REALLY_IWMMXT) \
775 { \
776 regno = FIRST_IWMMXT_GR_REGNUM; \
777 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
778 and wCG1 as call-preserved registers. The 2002/11/21 \
779 revision changed this so that all wCG registers are \
780 scratch registers. */ \
781 for (regno = FIRST_IWMMXT_GR_REGNUM; \
782 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
783 fixed_regs[regno] = 0; \
784 /* The XScale ABI has wR0 - wR9 as scratch registers, \
785 the rest as call-preserved registers. */ \
786 for (regno = FIRST_IWMMXT_REGNUM; \
787 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
788 { \
789 fixed_regs[regno] = 0; \
790 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
791 } \
792 } \
793 \
794 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
795 { \
796 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
797 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
798 } \
799 else if (TARGET_APCS_STACK) \
800 { \
801 fixed_regs[10] = 1; \
802 call_used_regs[10] = 1; \
803 } \
804 /* -mcaller-super-interworking reserves r11 for calls to \
805 _interwork_r11_call_via_rN(). Making the register global \
806 is an easy way of ensuring that it remains valid for all \
807 calls. */ \
808 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
809 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
810 { \
811 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
812 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
813 if (TARGET_CALLER_INTERWORKING) \
814 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
815 } \
816 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
817 }
818
819 /* These are a couple of extensions to the formats accepted
820 by asm_fprintf:
821 %@ prints out ASM_COMMENT_START
822 %r prints out REGISTER_PREFIX reg_names[arg] */
823 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
824 case '@': \
825 fputs (ASM_COMMENT_START, FILE); \
826 break; \
827 \
828 case 'r': \
829 fputs (REGISTER_PREFIX, FILE); \
830 fputs (reg_names [va_arg (ARGS, int)], FILE); \
831 break;
832
833 /* Round X up to the nearest word. */
834 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
835
836 /* Convert fron bytes to ints. */
837 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
838
839 /* The number of (integer) registers required to hold a quantity of type MODE.
840 Also used for VFP registers. */
841 #define ARM_NUM_REGS(MODE) \
842 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
843
844 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
845 #define ARM_NUM_REGS2(MODE, TYPE) \
846 ARM_NUM_INTS ((MODE) == BLKmode ? \
847 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
848
849 /* The number of (integer) argument register available. */
850 #define NUM_ARG_REGS 4
851
852 /* Return the register number of the N'th (integer) argument. */
853 #define ARG_REGISTER(N) (N - 1)
854
855 /* Specify the registers used for certain standard purposes.
856 The values of these macros are register numbers. */
857
858 /* The number of the last argument register. */
859 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
860
861 /* The numbers of the Thumb register ranges. */
862 #define FIRST_LO_REGNUM 0
863 #define LAST_LO_REGNUM 7
864 #define FIRST_HI_REGNUM 8
865 #define LAST_HI_REGNUM 11
866
867 #ifndef TARGET_UNWIND_INFO
868 /* We use sjlj exceptions for backwards compatibility. */
869 #define MUST_USE_SJLJ_EXCEPTIONS 1
870 #endif
871
872 /* We can generate DWARF2 Unwind info, even though we don't use it. */
873 #define DWARF2_UNWIND_INFO 1
874
875 /* Use r0 and r1 to pass exception handling information. */
876 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
877
878 /* The register that holds the return address in exception handlers. */
879 #define ARM_EH_STACKADJ_REGNUM 2
880 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
881
882 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
883 as an invisible last argument (possible since varargs don't exist in
884 Pascal), so the following is not true. */
885 #define STATIC_CHAIN_REGNUM 12
886
887 /* Define this to be where the real frame pointer is if it is not possible to
888 work out the offset between the frame pointer and the automatic variables
889 until after register allocation has taken place. FRAME_POINTER_REGNUM
890 should point to a special register that we will make sure is eliminated.
891
892 For the Thumb we have another problem. The TPCS defines the frame pointer
893 as r11, and GCC believes that it is always possible to use the frame pointer
894 as base register for addressing purposes. (See comments in
895 find_reloads_address()). But - the Thumb does not allow high registers,
896 including r11, to be used as base address registers. Hence our problem.
897
898 The solution used here, and in the old thumb port is to use r7 instead of
899 r11 as the hard frame pointer and to have special code to generate
900 backtrace structures on the stack (if required to do so via a command line
901 option) using r11. This is the only 'user visible' use of r11 as a frame
902 pointer. */
903 #define ARM_HARD_FRAME_POINTER_REGNUM 11
904 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
905
906 #define HARD_FRAME_POINTER_REGNUM \
907 (TARGET_ARM \
908 ? ARM_HARD_FRAME_POINTER_REGNUM \
909 : THUMB_HARD_FRAME_POINTER_REGNUM)
910
911 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
912
913 /* Register to use for pushing function arguments. */
914 #define STACK_POINTER_REGNUM SP_REGNUM
915
916 /* ARM floating pointer registers. */
917 #define FIRST_FPA_REGNUM 16
918 #define LAST_FPA_REGNUM 23
919 #define IS_FPA_REGNUM(REGNUM) \
920 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
921
922 #define FIRST_IWMMXT_GR_REGNUM 43
923 #define LAST_IWMMXT_GR_REGNUM 46
924 #define FIRST_IWMMXT_REGNUM 47
925 #define LAST_IWMMXT_REGNUM 62
926 #define IS_IWMMXT_REGNUM(REGNUM) \
927 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
928 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
929 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
930
931 /* Base register for access to local variables of the function. */
932 #define FRAME_POINTER_REGNUM 25
933
934 /* Base register for access to arguments of the function. */
935 #define ARG_POINTER_REGNUM 26
936
937 #define FIRST_CIRRUS_FP_REGNUM 27
938 #define LAST_CIRRUS_FP_REGNUM 42
939 #define IS_CIRRUS_REGNUM(REGNUM) \
940 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
941
942 #define FIRST_VFP_REGNUM 63
943 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
944 #define LAST_VFP_REGNUM \
945 (TARGET_VFP3 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
946
947 #define IS_VFP_REGNUM(REGNUM) \
948 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
949
950 /* VFP registers are split into two types: those defined by VFP versions < 3
951 have D registers overlaid on consecutive pairs of S registers. VFP version 3
952 defines 16 new D registers (d16-d31) which, for simplicity and correctness
953 in various parts of the backend, we implement as "fake" single-precision
954 registers (which would be S32-S63, but cannot be used in that way). The
955 following macros define these ranges of registers. */
956 #define LAST_LO_VFP_REGNUM 94
957 #define FIRST_HI_VFP_REGNUM 95
958 #define LAST_HI_VFP_REGNUM 126
959
960 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
961 ((REGNUM) <= LAST_LO_VFP_REGNUM)
962
963 /* DFmode values are only valid in even register pairs. */
964 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
965 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
966
967 /* Neon Quad values must start at a multiple of four registers. */
968 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
969 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
970
971 /* Neon structures of vectors must be in even register pairs and there
972 must be enough registers available. Because of various patterns
973 requiring quad registers, we require them to start at a multiple of
974 four. */
975 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
976 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
977 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
978
979 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
980 /* + 16 Cirrus registers take us up to 43. */
981 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
982 /* VFP (VFP3) adds 32 (64) + 1 more. */
983 #define FIRST_PSEUDO_REGISTER 128
984
985 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
986
987 /* Value should be nonzero if functions must have frame pointers.
988 Zero means the frame pointer need not be set up (and parms may be accessed
989 via the stack pointer) in functions that seem suitable.
990 If we have to have a frame pointer we might as well make use of it.
991 APCS says that the frame pointer does not need to be pushed in leaf
992 functions, or simple tail call functions. */
993
994 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
995 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
996 #endif
997
998 #define FRAME_POINTER_REQUIRED \
999 (current_function_has_nonlocal_label \
1000 || SUBTARGET_FRAME_POINTER_REQUIRED \
1001 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1002
1003 /* Return number of consecutive hard regs needed starting at reg REGNO
1004 to hold something of mode MODE.
1005 This is ordinarily the length in words of a value of mode MODE
1006 but can be less for certain modes in special long registers.
1007
1008 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1009 mode. */
1010 #define HARD_REGNO_NREGS(REGNO, MODE) \
1011 ((TARGET_32BIT \
1012 && REGNO >= FIRST_FPA_REGNUM \
1013 && REGNO != FRAME_POINTER_REGNUM \
1014 && REGNO != ARG_POINTER_REGNUM) \
1015 && !IS_VFP_REGNUM (REGNO) \
1016 ? 1 : ARM_NUM_REGS (MODE))
1017
1018 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1019 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1020 arm_hard_regno_mode_ok ((REGNO), (MODE))
1021
1022 /* Value is 1 if it is a good idea to tie two pseudo registers
1023 when one has mode MODE1 and one has mode MODE2.
1024 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1025 for any hard reg, then this must be 0 for correct output. */
1026 #define MODES_TIEABLE_P(MODE1, MODE2) \
1027 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1028
1029 #define VALID_IWMMXT_REG_MODE(MODE) \
1030 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1031
1032 /* Modes valid for Neon D registers. */
1033 #define VALID_NEON_DREG_MODE(MODE) \
1034 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1035 || (MODE) == V2SFmode || (MODE) == DImode)
1036
1037 /* Modes valid for Neon Q registers. */
1038 #define VALID_NEON_QREG_MODE(MODE) \
1039 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1040 || (MODE) == V4SFmode || (MODE) == V2DImode)
1041
1042 /* Structure modes valid for Neon registers. */
1043 #define VALID_NEON_STRUCT_MODE(MODE) \
1044 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1045 || (MODE) == CImode || (MODE) == XImode)
1046
1047 /* The order in which register should be allocated. It is good to use ip
1048 since no saving is required (though calls clobber it) and it never contains
1049 function parameters. It is quite good to use lr since other calls may
1050 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1051 least likely to contain a function parameter; in addition results are
1052 returned in r0.
1053 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1054 then D8-D15. The reason for doing this is to attempt to reduce register
1055 pressure when both single- and double-precision registers are used in a
1056 function. */
1057
1058 #define REG_ALLOC_ORDER \
1059 { \
1060 3, 2, 1, 0, 12, 14, 4, 5, \
1061 6, 7, 8, 10, 9, 11, 13, 15, \
1062 16, 17, 18, 19, 20, 21, 22, 23, \
1063 27, 28, 29, 30, 31, 32, 33, 34, \
1064 35, 36, 37, 38, 39, 40, 41, 42, \
1065 43, 44, 45, 46, 47, 48, 49, 50, \
1066 51, 52, 53, 54, 55, 56, 57, 58, \
1067 59, 60, 61, 62, \
1068 24, 25, 26, \
1069 95, 96, 97, 98, 99, 100, 101, 102, \
1070 103, 104, 105, 106, 107, 108, 109, 110, \
1071 111, 112, 113, 114, 115, 116, 117, 118, \
1072 119, 120, 121, 122, 123, 124, 125, 126, \
1073 78, 77, 76, 75, 74, 73, 72, 71, \
1074 70, 69, 68, 67, 66, 65, 64, 63, \
1075 79, 80, 81, 82, 83, 84, 85, 86, \
1076 87, 88, 89, 90, 91, 92, 93, 94, \
1077 127 \
1078 }
1079
1080 /* Interrupt functions can only use registers that have already been
1081 saved by the prologue, even if they would normally be
1082 call-clobbered. */
1083 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1084 (! IS_INTERRUPT (cfun->machine->func_type) || \
1085 df_regs_ever_live_p (DST))
1086 \f
1087 /* Register and constant classes. */
1088
1089 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1090 Now that the Thumb is involved it has become more complicated. */
1091 enum reg_class
1092 {
1093 NO_REGS,
1094 FPA_REGS,
1095 CIRRUS_REGS,
1096 VFP_D0_D7_REGS,
1097 VFP_LO_REGS,
1098 VFP_HI_REGS,
1099 VFP_REGS,
1100 IWMMXT_GR_REGS,
1101 IWMMXT_REGS,
1102 LO_REGS,
1103 STACK_REG,
1104 BASE_REGS,
1105 HI_REGS,
1106 CC_REG,
1107 VFPCC_REG,
1108 GENERAL_REGS,
1109 ALL_REGS,
1110 LIM_REG_CLASSES
1111 };
1112
1113 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1114
1115 /* Give names of register classes as strings for dump file. */
1116 #define REG_CLASS_NAMES \
1117 { \
1118 "NO_REGS", \
1119 "FPA_REGS", \
1120 "CIRRUS_REGS", \
1121 "VFP_D0_D7_REGS", \
1122 "VFP_LO_REGS", \
1123 "VFP_HI_REGS", \
1124 "VFP_REGS", \
1125 "IWMMXT_GR_REGS", \
1126 "IWMMXT_REGS", \
1127 "LO_REGS", \
1128 "STACK_REG", \
1129 "BASE_REGS", \
1130 "HI_REGS", \
1131 "CC_REG", \
1132 "VFPCC_REG", \
1133 "GENERAL_REGS", \
1134 "ALL_REGS", \
1135 }
1136
1137 /* Define which registers fit in which classes.
1138 This is an initializer for a vector of HARD_REG_SET
1139 of length N_REG_CLASSES. */
1140 #define REG_CLASS_CONTENTS \
1141 { \
1142 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1143 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1144 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1145 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1146 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1147 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1148 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1149 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1150 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1151 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1152 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1153 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1154 { 0x0000FF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1155 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1156 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1157 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1158 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1159 }
1160
1161 /* Any of the VFP register classes. */
1162 #define IS_VFP_CLASS(X) \
1163 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1164 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1165
1166 /* The same information, inverted:
1167 Return the class number of the smallest class containing
1168 reg number REGNO. This could be a conditional expression
1169 or could index an array. */
1170 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1171
1172 /* The following macro defines cover classes for Integrated Register
1173 Allocator. Cover classes is a set of non-intersected register
1174 classes covering all hard registers used for register allocation
1175 purpose. Any move between two registers of a cover class should be
1176 cheaper than load or store of the registers. The macro value is
1177 array of register classes with LIM_REG_CLASSES used as the end
1178 marker. */
1179
1180 #define IRA_COVER_CLASSES \
1181 { \
1182 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1183 LIM_REG_CLASSES \
1184 }
1185
1186 /* FPA registers can't do subreg as all values are reformatted to internal
1187 precision. VFP registers may only be accessed in the mode they
1188 were set. */
1189 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1190 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1191 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1192 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1193 : 0)
1194
1195 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1196 using r0-r4 for function arguments, r7 for the stack frame and don't
1197 have enough left over to do doubleword arithmetic. */
1198 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1199 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1200 || (CLASS) == CC_REG)
1201
1202 /* The class value for index registers, and the one for base regs. */
1203 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1204 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1205
1206 /* For the Thumb the high registers cannot be used as base registers
1207 when addressing quantities in QI or HI mode; if we don't know the
1208 mode, then we must be conservative. */
1209 #define MODE_BASE_REG_CLASS(MODE) \
1210 (TARGET_32BIT ? GENERAL_REGS : \
1211 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1212
1213 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1214 instead of BASE_REGS. */
1215 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1216
1217 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1218 registers explicitly used in the rtl to be used as spill registers
1219 but prevents the compiler from extending the lifetime of these
1220 registers. */
1221 #define SMALL_REGISTER_CLASSES TARGET_THUMB1
1222
1223 /* Given an rtx X being reloaded into a reg required to be
1224 in class CLASS, return the class of reg to actually use.
1225 In general this is just CLASS, but for the Thumb core registers and
1226 immediate constants we prefer a LO_REGS class or a subset. */
1227 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1228 (TARGET_ARM ? (CLASS) : \
1229 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1230 || (CLASS) == NO_REGS ? LO_REGS : (CLASS)))
1231
1232 /* Must leave BASE_REGS reloads alone */
1233 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1234 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1235 ? ((true_regnum (X) == -1 ? LO_REGS \
1236 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1237 : NO_REGS)) \
1238 : NO_REGS)
1239
1240 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1241 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1242 ? ((true_regnum (X) == -1 ? LO_REGS \
1243 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1244 : NO_REGS)) \
1245 : NO_REGS)
1246
1247 /* Return the register class of a scratch register needed to copy IN into
1248 or out of a register in CLASS in MODE. If it can be done directly,
1249 NO_REGS is returned. */
1250 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1251 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1252 ((TARGET_VFP && TARGET_HARD_FLOAT \
1253 && IS_VFP_CLASS (CLASS)) \
1254 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1255 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1256 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1257 : TARGET_32BIT \
1258 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1259 ? GENERAL_REGS : NO_REGS) \
1260 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1261
1262 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1263 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1264 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1265 ((TARGET_VFP && TARGET_HARD_FLOAT \
1266 && IS_VFP_CLASS (CLASS)) \
1267 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1268 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1269 coproc_secondary_reload_class (MODE, X, TRUE) : \
1270 /* Cannot load constants into Cirrus registers. */ \
1271 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1272 && (CLASS) == CIRRUS_REGS \
1273 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1274 ? GENERAL_REGS : \
1275 (TARGET_32BIT ? \
1276 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1277 && CONSTANT_P (X)) \
1278 ? GENERAL_REGS : \
1279 (((MODE) == HImode && ! arm_arch4 \
1280 && (GET_CODE (X) == MEM \
1281 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1282 && true_regnum (X) == -1))) \
1283 ? GENERAL_REGS : NO_REGS) \
1284 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1285
1286 /* Try a machine-dependent way of reloading an illegitimate address
1287 operand. If we find one, push the reload and jump to WIN. This
1288 macro is used in only one place: `find_reloads_address' in reload.c.
1289
1290 For the ARM, we wish to handle large displacements off a base
1291 register by splitting the addend across a MOV and the mem insn.
1292 This can cut the number of reloads needed. */
1293 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1294 do \
1295 { \
1296 if (GET_CODE (X) == PLUS \
1297 && GET_CODE (XEXP (X, 0)) == REG \
1298 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1299 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1300 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1301 { \
1302 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1303 HOST_WIDE_INT low, high; \
1304 \
1305 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1306 low = ((val & 0xf) ^ 0x8) - 0x8; \
1307 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1308 /* Need to be careful, -256 is not a valid offset. */ \
1309 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1310 else if (MODE == SImode \
1311 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1312 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1313 /* Need to be careful, -4096 is not a valid offset. */ \
1314 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1315 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1316 /* Need to be careful, -256 is not a valid offset. */ \
1317 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1318 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1319 && TARGET_HARD_FLOAT && TARGET_FPA) \
1320 /* Need to be careful, -1024 is not a valid offset. */ \
1321 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1322 else \
1323 break; \
1324 \
1325 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1326 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1327 - (unsigned HOST_WIDE_INT) 0x80000000); \
1328 /* Check for overflow or zero */ \
1329 if (low == 0 || high == 0 || (high + low != val)) \
1330 break; \
1331 \
1332 /* Reload the high part into a base reg; leave the low part \
1333 in the mem. */ \
1334 X = gen_rtx_PLUS (GET_MODE (X), \
1335 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1336 GEN_INT (high)), \
1337 GEN_INT (low)); \
1338 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1339 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1340 VOIDmode, 0, 0, OPNUM, TYPE); \
1341 goto WIN; \
1342 } \
1343 } \
1344 while (0)
1345
1346 /* XXX If an HImode FP+large_offset address is converted to an HImode
1347 SP+large_offset address, then reload won't know how to fix it. It sees
1348 only that SP isn't valid for HImode, and so reloads the SP into an index
1349 register, but the resulting address is still invalid because the offset
1350 is too big. We fix it here instead by reloading the entire address. */
1351 /* We could probably achieve better results by defining PROMOTE_MODE to help
1352 cope with the variances between the Thumb's signed and unsigned byte and
1353 halfword load instructions. */
1354 /* ??? This should be safe for thumb2, but we may be able to do better. */
1355 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1356 do { \
1357 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1358 if (new_x) \
1359 { \
1360 X = new_x; \
1361 goto WIN; \
1362 } \
1363 } while (0)
1364
1365 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1366 if (TARGET_ARM) \
1367 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1368 else \
1369 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1370
1371 /* Return the maximum number of consecutive registers
1372 needed to represent mode MODE in a register of class CLASS.
1373 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1374 #define CLASS_MAX_NREGS(CLASS, MODE) \
1375 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1376
1377 /* If defined, gives a class of registers that cannot be used as the
1378 operand of a SUBREG that changes the mode of the object illegally. */
1379
1380 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1381 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1382 (TARGET_32BIT ? \
1383 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1384 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1385 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 10 : \
1386 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 10 : \
1387 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1388 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1389 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1390 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1391 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1392 2) \
1393 : \
1394 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1395 \f
1396 /* Stack layout; function entry, exit and calling. */
1397
1398 /* Define this if pushing a word on the stack
1399 makes the stack pointer a smaller address. */
1400 #define STACK_GROWS_DOWNWARD 1
1401
1402 /* Define this to nonzero if the nominal address of the stack frame
1403 is at the high-address end of the local variables;
1404 that is, each additional local variable allocated
1405 goes at a more negative offset in the frame. */
1406 #define FRAME_GROWS_DOWNWARD 1
1407
1408 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1409 When present, it is one word in size, and sits at the top of the frame,
1410 between the soft frame pointer and either r7 or r11.
1411
1412 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1413 and only then if some outgoing arguments are passed on the stack. It would
1414 be tempting to also check whether the stack arguments are passed by indirect
1415 calls, but there seems to be no reason in principle why a post-reload pass
1416 couldn't convert a direct call into an indirect one. */
1417 #define CALLER_INTERWORKING_SLOT_SIZE \
1418 (TARGET_CALLER_INTERWORKING \
1419 && current_function_outgoing_args_size != 0 \
1420 ? UNITS_PER_WORD : 0)
1421
1422 /* Offset within stack frame to start allocating local variables at.
1423 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1424 first local allocated. Otherwise, it is the offset to the BEGINNING
1425 of the first local allocated. */
1426 #define STARTING_FRAME_OFFSET 0
1427
1428 /* If we generate an insn to push BYTES bytes,
1429 this says how many the stack pointer really advances by. */
1430 /* The push insns do not do this rounding implicitly.
1431 So don't define this. */
1432 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1433
1434 /* Define this if the maximum size of all the outgoing args is to be
1435 accumulated and pushed during the prologue. The amount can be
1436 found in the variable current_function_outgoing_args_size. */
1437 #define ACCUMULATE_OUTGOING_ARGS 1
1438
1439 /* Offset of first parameter from the argument pointer register value. */
1440 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1441
1442 /* Value is the number of byte of arguments automatically
1443 popped when returning from a subroutine call.
1444 FUNDECL is the declaration node of the function (as a tree),
1445 FUNTYPE is the data type of the function (as a tree),
1446 or for a library call it is an identifier node for the subroutine name.
1447 SIZE is the number of bytes of arguments passed on the stack.
1448
1449 On the ARM, the caller does not pop any of its arguments that were passed
1450 on the stack. */
1451 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1452
1453 /* Define how to find the value returned by a library function
1454 assuming the value has mode MODE. */
1455 #define LIBCALL_VALUE(MODE) \
1456 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1457 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1458 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1459 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1460 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1461 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1462 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1463 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1464 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1465
1466 /* Define how to find the value returned by a function.
1467 VALTYPE is the data type of the value (as a tree).
1468 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1469 otherwise, FUNC is 0. */
1470 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1471 arm_function_value (VALTYPE, FUNC);
1472
1473 /* 1 if N is a possible register number for a function value.
1474 On the ARM, only r0 and f0 can return results. */
1475 /* On a Cirrus chip, mvf0 can return results. */
1476 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1477 ((REGNO) == ARG_REGISTER (1) \
1478 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1479 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1480 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1481 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1482 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1483
1484 /* Amount of memory needed for an untyped call to save all possible return
1485 registers. */
1486 #define APPLY_RESULT_SIZE arm_apply_result_size()
1487
1488 /* How large values are returned */
1489 /* A C expression which can inhibit the returning of certain function values
1490 in registers, based on the type of value. */
1491 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1492
1493 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1494 values must be in memory. On the ARM, they need only do so if larger
1495 than a word, or if they contain elements offset from zero in the struct. */
1496 #define DEFAULT_PCC_STRUCT_RETURN 0
1497
1498 /* These bits describe the different types of function supported
1499 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1500 normal function and an interworked function, for example. Knowing the
1501 type of a function is important for determining its prologue and
1502 epilogue sequences.
1503 Note value 7 is currently unassigned. Also note that the interrupt
1504 function types all have bit 2 set, so that they can be tested for easily.
1505 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1506 machine_function structure is initialized (to zero) func_type will
1507 default to unknown. This will force the first use of arm_current_func_type
1508 to call arm_compute_func_type. */
1509 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1510 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1511 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1512 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1513 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1514 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1515
1516 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1517
1518 /* In addition functions can have several type modifiers,
1519 outlined by these bit masks: */
1520 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1521 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1522 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1523 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1524 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1525
1526 /* Some macros to test these flags. */
1527 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1528 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1529 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1530 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1531 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1532 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1533
1534
1535 /* Structure used to hold the function stack frame layout. Offsets are
1536 relative to the stack pointer on function entry. Positive offsets are
1537 in the direction of stack growth.
1538 Only soft_frame is used in thumb mode. */
1539
1540 typedef struct arm_stack_offsets GTY(())
1541 {
1542 int saved_args; /* ARG_POINTER_REGNUM. */
1543 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1544 int saved_regs;
1545 int soft_frame; /* FRAME_POINTER_REGNUM. */
1546 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1547 int outgoing_args; /* STACK_POINTER_REGNUM. */
1548 }
1549 arm_stack_offsets;
1550
1551 /* A C structure for machine-specific, per-function data.
1552 This is added to the cfun structure. */
1553 typedef struct machine_function GTY(())
1554 {
1555 /* Additional stack adjustment in __builtin_eh_throw. */
1556 rtx eh_epilogue_sp_ofs;
1557 /* Records if LR has to be saved for far jumps. */
1558 int far_jump_used;
1559 /* Records if ARG_POINTER was ever live. */
1560 int arg_pointer_live;
1561 /* Records if the save of LR has been eliminated. */
1562 int lr_save_eliminated;
1563 /* The size of the stack frame. Only valid after reload. */
1564 arm_stack_offsets stack_offsets;
1565 /* Records the type of the current function. */
1566 unsigned long func_type;
1567 /* Record if the function has a variable argument list. */
1568 int uses_anonymous_args;
1569 /* Records if sibcalls are blocked because an argument
1570 register is needed to preserve stack alignment. */
1571 int sibcall_blocked;
1572 /* The PIC register for this function. This might be a pseudo. */
1573 rtx pic_reg;
1574 /* Labels for per-function Thumb call-via stubs. One per potential calling
1575 register. We can never call via LR or PC. We can call via SP if a
1576 trampoline happens to be on the top of the stack. */
1577 rtx call_via[14];
1578 }
1579 machine_function;
1580
1581 /* As in the machine_function, a global set of call-via labels, for code
1582 that is in text_section. */
1583 extern GTY(()) rtx thumb_call_via_label[14];
1584
1585 /* A C type for declaring a variable that is used as the first argument of
1586 `FUNCTION_ARG' and other related values. For some target machines, the
1587 type `int' suffices and can hold the number of bytes of argument so far. */
1588 typedef struct
1589 {
1590 /* This is the number of registers of arguments scanned so far. */
1591 int nregs;
1592 /* This is the number of iWMMXt register arguments scanned so far. */
1593 int iwmmxt_nregs;
1594 int named_count;
1595 int nargs;
1596 int can_split;
1597 } CUMULATIVE_ARGS;
1598
1599 /* Define where to put the arguments to a function.
1600 Value is zero to push the argument on the stack,
1601 or a hard register in which to store the argument.
1602
1603 MODE is the argument's machine mode.
1604 TYPE is the data type of the argument (as a tree).
1605 This is null for libcalls where that information may
1606 not be available.
1607 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1608 the preceding args and about the function being called.
1609 NAMED is nonzero if this argument is a named parameter
1610 (otherwise it is an extra parameter matching an ellipsis).
1611
1612 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1613 other arguments are passed on the stack. If (NAMED == 0) (which happens
1614 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1615 defined), say it is passed in the stack (function_prologue will
1616 indeed make it pass in the stack if necessary). */
1617 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1618 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1619
1620 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1621 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1622
1623 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1624 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1625
1626 /* For AAPCS, padding should never be below the argument. For other ABIs,
1627 * mimic the default. */
1628 #define PAD_VARARGS_DOWN \
1629 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1630
1631 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1632 for a call to a function whose data type is FNTYPE.
1633 For a library call, FNTYPE is 0.
1634 On the ARM, the offset starts at 0. */
1635 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1636 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1637
1638 /* Update the data in CUM to advance over an argument
1639 of mode MODE and data type TYPE.
1640 (TYPE is null for libcalls where that information may not be available.) */
1641 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1642 (CUM).nargs += 1; \
1643 if (arm_vector_mode_supported_p (MODE) \
1644 && (CUM).named_count > (CUM).nargs \
1645 && TARGET_IWMMXT_ABI) \
1646 (CUM).iwmmxt_nregs += 1; \
1647 else \
1648 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1649
1650 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1651 argument with the specified mode and type. If it is not defined,
1652 `PARM_BOUNDARY' is used for all arguments. */
1653 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1654 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1655 ? DOUBLEWORD_ALIGNMENT \
1656 : PARM_BOUNDARY )
1657
1658 /* 1 if N is a possible register number for function argument passing.
1659 On the ARM, r0-r3 are used to pass args. */
1660 #define FUNCTION_ARG_REGNO_P(REGNO) \
1661 (IN_RANGE ((REGNO), 0, 3) \
1662 || (TARGET_IWMMXT_ABI \
1663 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1664
1665 \f
1666 /* If your target environment doesn't prefix user functions with an
1667 underscore, you may wish to re-define this to prevent any conflicts. */
1668 #ifndef ARM_MCOUNT_NAME
1669 #define ARM_MCOUNT_NAME "*mcount"
1670 #endif
1671
1672 /* Call the function profiler with a given profile label. The Acorn
1673 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1674 On the ARM the full profile code will look like:
1675 .data
1676 LP1
1677 .word 0
1678 .text
1679 mov ip, lr
1680 bl mcount
1681 .word LP1
1682
1683 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1684 will output the .text section.
1685
1686 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1687 ``prof'' doesn't seem to mind about this!
1688
1689 Note - this version of the code is designed to work in both ARM and
1690 Thumb modes. */
1691 #ifndef ARM_FUNCTION_PROFILER
1692 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1693 { \
1694 char temp[20]; \
1695 rtx sym; \
1696 \
1697 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1698 IP_REGNUM, LR_REGNUM); \
1699 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1700 fputc ('\n', STREAM); \
1701 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1702 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1703 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1704 }
1705 #endif
1706
1707 #ifdef THUMB_FUNCTION_PROFILER
1708 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1709 if (TARGET_ARM) \
1710 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1711 else \
1712 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1713 #else
1714 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1715 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1716 #endif
1717
1718 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1719 the stack pointer does not matter. The value is tested only in
1720 functions that have frame pointers.
1721 No definition is equivalent to always zero.
1722
1723 On the ARM, the function epilogue recovers the stack pointer from the
1724 frame. */
1725 #define EXIT_IGNORE_STACK 1
1726
1727 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1728
1729 /* Determine if the epilogue should be output as RTL.
1730 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1731 /* This is disabled for Thumb-2 because it will confuse the
1732 conditional insn counter. */
1733 #define USE_RETURN_INSN(ISCOND) \
1734 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1735
1736 /* Definitions for register eliminations.
1737
1738 This is an array of structures. Each structure initializes one pair
1739 of eliminable registers. The "from" register number is given first,
1740 followed by "to". Eliminations of the same "from" register are listed
1741 in order of preference.
1742
1743 We have two registers that can be eliminated on the ARM. First, the
1744 arg pointer register can often be eliminated in favor of the stack
1745 pointer register. Secondly, the pseudo frame pointer register can always
1746 be eliminated; it is replaced with either the stack or the real frame
1747 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1748 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1749
1750 #define ELIMINABLE_REGS \
1751 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1752 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1753 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1754 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1755 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1756 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1757 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1758
1759 /* Given FROM and TO register numbers, say whether this elimination is
1760 allowed. Frame pointer elimination is automatically handled.
1761
1762 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1763 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1764 pointer, we must eliminate FRAME_POINTER_REGNUM into
1765 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1766 ARG_POINTER_REGNUM. */
1767 #define CAN_ELIMINATE(FROM, TO) \
1768 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1769 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1770 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1771 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1772 1)
1773
1774 /* Define the offset between two registers, one to be eliminated, and the
1775 other its replacement, at the start of a routine. */
1776 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1777 if (TARGET_ARM) \
1778 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1779 else \
1780 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1781
1782 /* Special case handling of the location of arguments passed on the stack. */
1783 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1784
1785 /* Initialize data used by insn expanders. This is called from insn_emit,
1786 once for every function before code is generated. */
1787 #define INIT_EXPANDERS arm_init_expanders ()
1788
1789 /* Output assembler code for a block containing the constant parts
1790 of a trampoline, leaving space for the variable parts.
1791
1792 On the ARM, (if r8 is the static chain regnum, and remembering that
1793 referencing pc adds an offset of 8) the trampoline looks like:
1794 ldr r8, [pc, #0]
1795 ldr pc, [pc]
1796 .word static chain value
1797 .word function's address
1798 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1799 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1800 { \
1801 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1802 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1803 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1804 PC_REGNUM, PC_REGNUM); \
1805 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1806 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1807 }
1808
1809 /* The Thumb-2 trampoline is similar to the arm implementation.
1810 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1811 #define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1812 { \
1813 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1814 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1815 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1816 PC_REGNUM, PC_REGNUM); \
1817 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1818 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1819 }
1820
1821 #define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
1822 { \
1823 ASM_OUTPUT_ALIGN(FILE, 2); \
1824 fprintf (FILE, "\t.code\t16\n"); \
1825 fprintf (FILE, ".Ltrampoline_start:\n"); \
1826 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1827 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1828 PC_REGNUM); \
1829 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1830 STATIC_CHAIN_REGNUM); \
1831 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1832 PC_REGNUM); \
1833 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1834 SP_REGNUM); \
1835 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1836 PC_REGNUM); \
1837 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1838 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1839 }
1840
1841 #define TRAMPOLINE_TEMPLATE(FILE) \
1842 if (TARGET_ARM) \
1843 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1844 else if (TARGET_THUMB2) \
1845 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
1846 else \
1847 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1848
1849 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1850 of the address. */
1851 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1852 { \
1853 if (TARGET_THUMB) \
1854 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1855 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1856 } while(0)
1857
1858 /* Length in units of the trampoline for entering a nested function. */
1859 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1860
1861 /* Alignment required for a trampoline in bits. */
1862 #define TRAMPOLINE_ALIGNMENT 32
1863
1864
1865 /* Emit RTL insns to initialize the variable parts of a trampoline.
1866 FNADDR is an RTX for the address of the function's pure code.
1867 CXT is an RTX for the static chain value for the function. */
1868 #ifndef INITIALIZE_TRAMPOLINE
1869 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1870 { \
1871 emit_move_insn (gen_rtx_MEM (SImode, \
1872 plus_constant (TRAMP, \
1873 TARGET_32BIT ? 8 : 12)), \
1874 CXT); \
1875 emit_move_insn (gen_rtx_MEM (SImode, \
1876 plus_constant (TRAMP, \
1877 TARGET_32BIT ? 12 : 16)), \
1878 FNADDR); \
1879 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1880 0, VOIDmode, 2, TRAMP, Pmode, \
1881 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1882 }
1883 #endif
1884
1885 \f
1886 /* Addressing modes, and classification of registers for them. */
1887 #define HAVE_POST_INCREMENT 1
1888 #define HAVE_PRE_INCREMENT TARGET_32BIT
1889 #define HAVE_POST_DECREMENT TARGET_32BIT
1890 #define HAVE_PRE_DECREMENT TARGET_32BIT
1891 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1892 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1893 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1894 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1895
1896 /* Macros to check register numbers against specific register classes. */
1897
1898 /* These assume that REGNO is a hard or pseudo reg number.
1899 They give nonzero only if REGNO is a hard reg of the suitable class
1900 or a pseudo reg currently allocated to a suitable hard reg.
1901 Since they use reg_renumber, they are safe only once reg_renumber
1902 has been allocated, which happens in local-alloc.c. */
1903 #define TEST_REGNO(R, TEST, VALUE) \
1904 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1905
1906 /* Don't allow the pc to be used. */
1907 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1908 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1909 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1910 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1911
1912 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1913 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1914 || (GET_MODE_SIZE (MODE) >= 4 \
1915 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1916
1917 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1918 (TARGET_THUMB1 \
1919 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1920 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1921
1922 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1923 For Thumb, we can not use SP + reg, so reject SP. */
1924 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1925 REGNO_OK_FOR_INDEX_P (X)
1926
1927 /* For ARM code, we don't care about the mode, but for Thumb, the index
1928 must be suitable for use in a QImode load. */
1929 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1930 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1931
1932 /* Maximum number of registers that can appear in a valid memory address.
1933 Shifts in addresses can't be by a register. */
1934 #define MAX_REGS_PER_ADDRESS 2
1935
1936 /* Recognize any constant value that is a valid address. */
1937 /* XXX We can address any constant, eventually... */
1938 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1939 #define CONSTANT_ADDRESS_P(X) \
1940 (GET_CODE (X) == SYMBOL_REF \
1941 && (CONSTANT_POOL_ADDRESS_P (X) \
1942 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1943
1944 /* True if SYMBOL + OFFSET constants must refer to something within
1945 SYMBOL's section. */
1946 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1947
1948 /* Nonzero if the constant value X is a legitimate general operand.
1949 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1950
1951 On the ARM, allow any integer (invalid ones are removed later by insn
1952 patterns), nice doubles and symbol_refs which refer to the function's
1953 constant pool XXX.
1954
1955 When generating pic allow anything. */
1956 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1957
1958 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1959 ( GET_CODE (X) == CONST_INT \
1960 || GET_CODE (X) == CONST_DOUBLE \
1961 || CONSTANT_ADDRESS_P (X) \
1962 || flag_pic)
1963
1964 #define LEGITIMATE_CONSTANT_P(X) \
1965 (!arm_cannot_force_const_mem (X) \
1966 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1967 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1968
1969 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1970 #define SUBTARGET_NAME_ENCODING_LENGTHS
1971 #endif
1972
1973 /* This is a C fragment for the inside of a switch statement.
1974 Each case label should return the number of characters to
1975 be stripped from the start of a function's name, if that
1976 name starts with the indicated character. */
1977 #define ARM_NAME_ENCODING_LENGTHS \
1978 case '*': return 1; \
1979 SUBTARGET_NAME_ENCODING_LENGTHS
1980
1981 /* This is how to output a reference to a user-level label named NAME.
1982 `assemble_name' uses this. */
1983 #undef ASM_OUTPUT_LABELREF
1984 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1985 arm_asm_output_labelref (FILE, NAME)
1986
1987 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1988 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1989 if (TARGET_THUMB2) \
1990 thumb2_asm_output_opcode (STREAM);
1991
1992 /* The EABI specifies that constructors should go in .init_array.
1993 Other targets use .ctors for compatibility. */
1994 #ifndef ARM_EABI_CTORS_SECTION_OP
1995 #define ARM_EABI_CTORS_SECTION_OP \
1996 "\t.section\t.init_array,\"aw\",%init_array"
1997 #endif
1998 #ifndef ARM_EABI_DTORS_SECTION_OP
1999 #define ARM_EABI_DTORS_SECTION_OP \
2000 "\t.section\t.fini_array,\"aw\",%fini_array"
2001 #endif
2002 #define ARM_CTORS_SECTION_OP \
2003 "\t.section\t.ctors,\"aw\",%progbits"
2004 #define ARM_DTORS_SECTION_OP \
2005 "\t.section\t.dtors,\"aw\",%progbits"
2006
2007 /* Define CTORS_SECTION_ASM_OP. */
2008 #undef CTORS_SECTION_ASM_OP
2009 #undef DTORS_SECTION_ASM_OP
2010 #ifndef IN_LIBGCC2
2011 # define CTORS_SECTION_ASM_OP \
2012 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2013 # define DTORS_SECTION_ASM_OP \
2014 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2015 #else /* !defined (IN_LIBGCC2) */
2016 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2017 so we cannot use the definition above. */
2018 # ifdef __ARM_EABI__
2019 /* The .ctors section is not part of the EABI, so we do not define
2020 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2021 from trying to use it. We do define it when doing normal
2022 compilation, as .init_array can be used instead of .ctors. */
2023 /* There is no need to emit begin or end markers when using
2024 init_array; the dynamic linker will compute the size of the
2025 array itself based on special symbols created by the static
2026 linker. However, we do need to arrange to set up
2027 exception-handling here. */
2028 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2029 # define CTOR_LIST_END /* empty */
2030 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2031 # define DTOR_LIST_END /* empty */
2032 # else /* !defined (__ARM_EABI__) */
2033 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2034 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2035 # endif /* !defined (__ARM_EABI__) */
2036 #endif /* !defined (IN_LIBCC2) */
2037
2038 /* True if the operating system can merge entities with vague linkage
2039 (e.g., symbols in COMDAT group) during dynamic linking. */
2040 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2041 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2042 #endif
2043
2044 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2045
2046 #ifdef TARGET_UNWIND_INFO
2047 #define ARM_EABI_UNWIND_TABLES \
2048 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2049 #else
2050 #define ARM_EABI_UNWIND_TABLES 0
2051 #endif
2052
2053 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2054 and check its validity for a certain class.
2055 We have two alternate definitions for each of them.
2056 The usual definition accepts all pseudo regs; the other rejects
2057 them unless they have been allocated suitable hard regs.
2058 The symbol REG_OK_STRICT causes the latter definition to be used.
2059 Thumb-2 has the same restrictions as arm. */
2060 #ifndef REG_OK_STRICT
2061
2062 #define ARM_REG_OK_FOR_BASE_P(X) \
2063 (REGNO (X) <= LAST_ARM_REGNUM \
2064 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2065 || REGNO (X) == FRAME_POINTER_REGNUM \
2066 || REGNO (X) == ARG_POINTER_REGNUM)
2067
2068 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2069 (REGNO (X) <= LAST_LO_REGNUM \
2070 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2071 || (GET_MODE_SIZE (MODE) >= 4 \
2072 && (REGNO (X) == STACK_POINTER_REGNUM \
2073 || (X) == hard_frame_pointer_rtx \
2074 || (X) == arg_pointer_rtx)))
2075
2076 #define REG_STRICT_P 0
2077
2078 #else /* REG_OK_STRICT */
2079
2080 #define ARM_REG_OK_FOR_BASE_P(X) \
2081 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2082
2083 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2084 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2085
2086 #define REG_STRICT_P 1
2087
2088 #endif /* REG_OK_STRICT */
2089
2090 /* Now define some helpers in terms of the above. */
2091
2092 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2093 (TARGET_THUMB1 \
2094 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2095 : ARM_REG_OK_FOR_BASE_P (X))
2096
2097 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2098
2099 /* For 16-bit Thumb, a valid index register is anything that can be used in
2100 a byte load instruction. */
2101 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2102 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2103
2104 /* Nonzero if X is a hard reg that can be used as an index
2105 or if it is a pseudo reg. On the Thumb, the stack pointer
2106 is not suitable. */
2107 #define REG_OK_FOR_INDEX_P(X) \
2108 (TARGET_THUMB1 \
2109 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2110 : ARM_REG_OK_FOR_INDEX_P (X))
2111
2112 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2113 For Thumb, we can not use SP + reg, so reject SP. */
2114 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2115 REG_OK_FOR_INDEX_P (X)
2116 \f
2117 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2118 that is a valid memory address for an instruction.
2119 The MODE argument is the machine mode for the MEM expression
2120 that wants to use this address. */
2121
2122 #define ARM_BASE_REGISTER_RTX_P(X) \
2123 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2124
2125 #define ARM_INDEX_REGISTER_RTX_P(X) \
2126 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2127
2128 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2129 { \
2130 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2131 goto WIN; \
2132 }
2133
2134 #define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2135 { \
2136 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2137 goto WIN; \
2138 }
2139
2140 #define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2141 { \
2142 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2143 goto WIN; \
2144 }
2145
2146 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2147 if (TARGET_ARM) \
2148 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2149 else if (TARGET_THUMB2) \
2150 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2151 else /* if (TARGET_THUMB1) */ \
2152 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2153
2154 \f
2155 /* Try machine-dependent ways of modifying an illegitimate address
2156 to be legitimate. If we find one, return the new, valid address. */
2157 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2158 do { \
2159 X = arm_legitimize_address (X, OLDX, MODE); \
2160 } while (0)
2161
2162 /* ??? Implement LEGITIMIZE_ADDRESS for thumb2. */
2163 #define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2164 do { \
2165 } while (0)
2166
2167 #define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2168 do { \
2169 X = thumb_legitimize_address (X, OLDX, MODE); \
2170 } while (0)
2171
2172 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2173 do { \
2174 if (TARGET_ARM) \
2175 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2176 else if (TARGET_THUMB2) \
2177 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2178 else \
2179 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2180 \
2181 if (memory_address_p (MODE, X)) \
2182 goto WIN; \
2183 } while (0)
2184
2185 /* Go to LABEL if ADDR (a legitimate address expression)
2186 has an effect that depends on the machine mode it is used for. */
2187 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2188 { \
2189 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2190 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2191 goto LABEL; \
2192 }
2193
2194 /* Nothing helpful to do for the Thumb */
2195 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2196 if (TARGET_32BIT) \
2197 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2198 \f
2199
2200 /* Specify the machine mode that this machine uses
2201 for the index in the tablejump instruction. */
2202 #define CASE_VECTOR_MODE Pmode
2203
2204 #define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2
2205
2206 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2207 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2208 : (max >= 0x200) ? HImode \
2209 : QImode)
2210
2211 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2212 unsigned is probably best, but may break some code. */
2213 #ifndef DEFAULT_SIGNED_CHAR
2214 #define DEFAULT_SIGNED_CHAR 0
2215 #endif
2216
2217 /* Max number of bytes we can move from memory to memory
2218 in one reasonably fast instruction. */
2219 #define MOVE_MAX 4
2220
2221 #undef MOVE_RATIO
2222 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2223
2224 /* Define if operations between registers always perform the operation
2225 on the full register even if a narrower mode is specified. */
2226 #define WORD_REGISTER_OPERATIONS
2227
2228 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2229 will either zero-extend or sign-extend. The value of this macro should
2230 be the code that says which one of the two operations is implicitly
2231 done, UNKNOWN if none. */
2232 #define LOAD_EXTEND_OP(MODE) \
2233 (TARGET_THUMB ? ZERO_EXTEND : \
2234 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2235 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2236
2237 /* Nonzero if access to memory by bytes is slow and undesirable. */
2238 #define SLOW_BYTE_ACCESS 0
2239
2240 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2241
2242 /* Immediate shift counts are truncated by the output routines (or was it
2243 the assembler?). Shift counts in a register are truncated by ARM. Note
2244 that the native compiler puts too large (> 32) immediate shift counts
2245 into a register and shifts by the register, letting the ARM decide what
2246 to do instead of doing that itself. */
2247 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2248 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2249 On the arm, Y in a register is used modulo 256 for the shift. Only for
2250 rotates is modulo 32 used. */
2251 /* #define SHIFT_COUNT_TRUNCATED 1 */
2252
2253 /* All integers have the same format so truncation is easy. */
2254 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2255
2256 /* Calling from registers is a massive pain. */
2257 #define NO_FUNCTION_CSE 1
2258
2259 /* The machine modes of pointers and functions */
2260 #define Pmode SImode
2261 #define FUNCTION_MODE Pmode
2262
2263 #define ARM_FRAME_RTX(X) \
2264 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2265 || (X) == arg_pointer_rtx)
2266
2267 /* Moves to and from memory are quite expensive */
2268 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2269 (TARGET_32BIT ? 10 : \
2270 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2271 * (CLASS == LO_REGS ? 1 : 2)))
2272
2273 /* Try to generate sequences that don't involve branches, we can then use
2274 conditional instructions */
2275 #define BRANCH_COST \
2276 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2277 \f
2278 /* Position Independent Code. */
2279 /* We decide which register to use based on the compilation options and
2280 the assembler in use; this is more general than the APCS restriction of
2281 using sb (r9) all the time. */
2282 extern unsigned arm_pic_register;
2283
2284 /* The register number of the register used to address a table of static
2285 data addresses in memory. */
2286 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2287
2288 /* We can't directly access anything that contains a symbol,
2289 nor can we indirect via the constant pool. One exception is
2290 UNSPEC_TLS, which is always PIC. */
2291 #define LEGITIMATE_PIC_OPERAND_P(X) \
2292 (!(symbol_mentioned_p (X) \
2293 || label_mentioned_p (X) \
2294 || (GET_CODE (X) == SYMBOL_REF \
2295 && CONSTANT_POOL_ADDRESS_P (X) \
2296 && (symbol_mentioned_p (get_pool_constant (X)) \
2297 || label_mentioned_p (get_pool_constant (X))))) \
2298 || tls_mentioned_p (X))
2299
2300 /* We need to know when we are making a constant pool; this determines
2301 whether data needs to be in the GOT or can be referenced via a GOT
2302 offset. */
2303 extern int making_const_table;
2304 \f
2305 /* Handle pragmas for compatibility with Intel's compilers. */
2306 /* Also abuse this to register additional C specific EABI attributes. */
2307 #define REGISTER_TARGET_PRAGMAS() do { \
2308 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2309 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2310 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2311 arm_lang_object_attributes_init(); \
2312 } while (0)
2313
2314 /* Condition code information. */
2315 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2316 return the mode to be used for the comparison. */
2317
2318 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2319
2320 #define REVERSIBLE_CC_MODE(MODE) 1
2321
2322 #define REVERSE_CONDITION(CODE,MODE) \
2323 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2324 ? reverse_condition_maybe_unordered (code) \
2325 : reverse_condition (code))
2326
2327 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2328 do \
2329 { \
2330 if (GET_CODE (OP1) == CONST_INT \
2331 && ! (const_ok_for_arm (INTVAL (OP1)) \
2332 || (const_ok_for_arm (- INTVAL (OP1))))) \
2333 { \
2334 rtx const_op = OP1; \
2335 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2336 &const_op); \
2337 OP1 = const_op; \
2338 } \
2339 } \
2340 while (0)
2341
2342 /* The arm5 clz instruction returns 32. */
2343 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2344 \f
2345 #undef ASM_APP_OFF
2346 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2347 TARGET_THUMB2 ? "\t.thumb\n" : "")
2348
2349 /* Output a push or a pop instruction (only used when profiling). */
2350 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2351 do \
2352 { \
2353 if (TARGET_ARM) \
2354 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2355 STACK_POINTER_REGNUM, REGNO); \
2356 else \
2357 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2358 } while (0)
2359
2360
2361 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2362 do \
2363 { \
2364 if (TARGET_ARM) \
2365 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2366 STACK_POINTER_REGNUM, REGNO); \
2367 else \
2368 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2369 } while (0)
2370
2371 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2372 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2373
2374 /* This is how to output a label which precedes a jumptable. Since
2375 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2376 #undef ASM_OUTPUT_CASE_LABEL
2377 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2378 do \
2379 { \
2380 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2381 ASM_OUTPUT_ALIGN (FILE, 2); \
2382 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2383 } \
2384 while (0)
2385
2386 /* Make sure subsequent insns are aligned after a TBB. */
2387 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2388 do \
2389 { \
2390 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2391 ASM_OUTPUT_ALIGN (FILE, 1); \
2392 } \
2393 while (0)
2394
2395 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2396 do \
2397 { \
2398 if (TARGET_THUMB) \
2399 { \
2400 if (is_called_in_ARM_mode (DECL) \
2401 || (TARGET_THUMB1 && current_function_is_thunk)) \
2402 fprintf (STREAM, "\t.code 32\n") ; \
2403 else if (TARGET_THUMB1) \
2404 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2405 else \
2406 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2407 } \
2408 if (TARGET_POKE_FUNCTION_NAME) \
2409 arm_poke_function_name (STREAM, (const char *) NAME); \
2410 } \
2411 while (0)
2412
2413 /* For aliases of functions we use .thumb_set instead. */
2414 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2415 do \
2416 { \
2417 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2418 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2419 \
2420 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2421 { \
2422 fprintf (FILE, "\t.thumb_set "); \
2423 assemble_name (FILE, LABEL1); \
2424 fprintf (FILE, ","); \
2425 assemble_name (FILE, LABEL2); \
2426 fprintf (FILE, "\n"); \
2427 } \
2428 else \
2429 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2430 } \
2431 while (0)
2432
2433 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2434 /* To support -falign-* switches we need to use .p2align so
2435 that alignment directives in code sections will be padded
2436 with no-op instructions, rather than zeroes. */
2437 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2438 if ((LOG) != 0) \
2439 { \
2440 if ((MAX_SKIP) == 0) \
2441 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2442 else \
2443 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2444 (int) (LOG), (int) (MAX_SKIP)); \
2445 }
2446 #endif
2447 \f
2448 /* Add two bytes to the length of conditionally executed Thumb-2
2449 instructions for the IT instruction. */
2450 #define ADJUST_INSN_LENGTH(insn, length) \
2451 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2452 length += 2;
2453
2454 /* Only perform branch elimination (by making instructions conditional) if
2455 we're optimizing. For Thumb-2 check if any IT instructions need
2456 outputting. */
2457 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2458 if (TARGET_ARM && optimize) \
2459 arm_final_prescan_insn (INSN); \
2460 else if (TARGET_THUMB2) \
2461 thumb2_final_prescan_insn (INSN); \
2462 else if (TARGET_THUMB1) \
2463 thumb1_final_prescan_insn (INSN)
2464
2465 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2466 (CODE == '@' || CODE == '|' || CODE == '.' \
2467 || CODE == '(' || CODE == ')' || CODE == '#' \
2468 || (TARGET_32BIT && (CODE == '?')) \
2469 || (TARGET_THUMB2 && (CODE == '!')) \
2470 || (TARGET_THUMB && (CODE == '_')))
2471
2472 /* Output an operand of an instruction. */
2473 #define PRINT_OPERAND(STREAM, X, CODE) \
2474 arm_print_operand (STREAM, X, CODE)
2475
2476 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2477 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2478 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2479 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2480 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2481 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2482 : 0))))
2483
2484 /* Output the address of an operand. */
2485 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2486 { \
2487 int is_minus = GET_CODE (X) == MINUS; \
2488 \
2489 if (GET_CODE (X) == REG) \
2490 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2491 else if (GET_CODE (X) == PLUS || is_minus) \
2492 { \
2493 rtx base = XEXP (X, 0); \
2494 rtx index = XEXP (X, 1); \
2495 HOST_WIDE_INT offset = 0; \
2496 if (GET_CODE (base) != REG) \
2497 { \
2498 /* Ensure that BASE is a register. */ \
2499 /* (one of them must be). */ \
2500 rtx temp = base; \
2501 base = index; \
2502 index = temp; \
2503 } \
2504 switch (GET_CODE (index)) \
2505 { \
2506 case CONST_INT: \
2507 offset = INTVAL (index); \
2508 if (is_minus) \
2509 offset = -offset; \
2510 asm_fprintf (STREAM, "[%r, #%wd]", \
2511 REGNO (base), offset); \
2512 break; \
2513 \
2514 case REG: \
2515 asm_fprintf (STREAM, "[%r, %s%r]", \
2516 REGNO (base), is_minus ? "-" : "", \
2517 REGNO (index)); \
2518 break; \
2519 \
2520 case MULT: \
2521 case ASHIFTRT: \
2522 case LSHIFTRT: \
2523 case ASHIFT: \
2524 case ROTATERT: \
2525 { \
2526 asm_fprintf (STREAM, "[%r, %s%r", \
2527 REGNO (base), is_minus ? "-" : "", \
2528 REGNO (XEXP (index, 0))); \
2529 arm_print_operand (STREAM, index, 'S'); \
2530 fputs ("]", STREAM); \
2531 break; \
2532 } \
2533 \
2534 default: \
2535 gcc_unreachable (); \
2536 } \
2537 } \
2538 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2539 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2540 { \
2541 extern enum machine_mode output_memory_reference_mode; \
2542 \
2543 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2544 \
2545 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2546 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2547 REGNO (XEXP (X, 0)), \
2548 GET_CODE (X) == PRE_DEC ? "-" : "", \
2549 GET_MODE_SIZE (output_memory_reference_mode)); \
2550 else \
2551 asm_fprintf (STREAM, "[%r], #%s%d", \
2552 REGNO (XEXP (X, 0)), \
2553 GET_CODE (X) == POST_DEC ? "-" : "", \
2554 GET_MODE_SIZE (output_memory_reference_mode)); \
2555 } \
2556 else if (GET_CODE (X) == PRE_MODIFY) \
2557 { \
2558 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2559 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2560 asm_fprintf (STREAM, "#%wd]!", \
2561 INTVAL (XEXP (XEXP (X, 1), 1))); \
2562 else \
2563 asm_fprintf (STREAM, "%r]!", \
2564 REGNO (XEXP (XEXP (X, 1), 1))); \
2565 } \
2566 else if (GET_CODE (X) == POST_MODIFY) \
2567 { \
2568 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2569 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2570 asm_fprintf (STREAM, "#%wd", \
2571 INTVAL (XEXP (XEXP (X, 1), 1))); \
2572 else \
2573 asm_fprintf (STREAM, "%r", \
2574 REGNO (XEXP (XEXP (X, 1), 1))); \
2575 } \
2576 else output_addr_const (STREAM, X); \
2577 }
2578
2579 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2580 { \
2581 if (GET_CODE (X) == REG) \
2582 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2583 else if (GET_CODE (X) == POST_INC) \
2584 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2585 else if (GET_CODE (X) == PLUS) \
2586 { \
2587 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2588 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2589 asm_fprintf (STREAM, "[%r, #%wd]", \
2590 REGNO (XEXP (X, 0)), \
2591 INTVAL (XEXP (X, 1))); \
2592 else \
2593 asm_fprintf (STREAM, "[%r, %r]", \
2594 REGNO (XEXP (X, 0)), \
2595 REGNO (XEXP (X, 1))); \
2596 } \
2597 else \
2598 output_addr_const (STREAM, X); \
2599 }
2600
2601 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2602 if (TARGET_32BIT) \
2603 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2604 else \
2605 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2606
2607 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2608 if (arm_output_addr_const_extra (file, x) == FALSE) \
2609 goto fail
2610
2611 /* A C expression whose value is RTL representing the value of the return
2612 address for the frame COUNT steps up from the current frame. */
2613
2614 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2615 arm_return_addr (COUNT, FRAME)
2616
2617 /* Mask of the bits in the PC that contain the real return address
2618 when running in 26-bit mode. */
2619 #define RETURN_ADDR_MASK26 (0x03fffffc)
2620
2621 /* Pick up the return address upon entry to a procedure. Used for
2622 dwarf2 unwind information. This also enables the table driven
2623 mechanism. */
2624 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2625 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2626
2627 /* Used to mask out junk bits from the return address, such as
2628 processor state, interrupt status, condition codes and the like. */
2629 #define MASK_RETURN_ADDR \
2630 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2631 in 26 bit mode, the condition codes must be masked out of the \
2632 return address. This does not apply to ARM6 and later processors \
2633 when running in 32 bit mode. */ \
2634 ((arm_arch4 || TARGET_THUMB) \
2635 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2636 : arm_gen_return_addr_mask ())
2637
2638 \f
2639 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2640 symbolic names defined here (which would require too much duplication).
2641 FIXME? */
2642 enum arm_builtins
2643 {
2644 ARM_BUILTIN_GETWCX,
2645 ARM_BUILTIN_SETWCX,
2646
2647 ARM_BUILTIN_WZERO,
2648
2649 ARM_BUILTIN_WAVG2BR,
2650 ARM_BUILTIN_WAVG2HR,
2651 ARM_BUILTIN_WAVG2B,
2652 ARM_BUILTIN_WAVG2H,
2653
2654 ARM_BUILTIN_WACCB,
2655 ARM_BUILTIN_WACCH,
2656 ARM_BUILTIN_WACCW,
2657
2658 ARM_BUILTIN_WMACS,
2659 ARM_BUILTIN_WMACSZ,
2660 ARM_BUILTIN_WMACU,
2661 ARM_BUILTIN_WMACUZ,
2662
2663 ARM_BUILTIN_WSADB,
2664 ARM_BUILTIN_WSADBZ,
2665 ARM_BUILTIN_WSADH,
2666 ARM_BUILTIN_WSADHZ,
2667
2668 ARM_BUILTIN_WALIGN,
2669
2670 ARM_BUILTIN_TMIA,
2671 ARM_BUILTIN_TMIAPH,
2672 ARM_BUILTIN_TMIABB,
2673 ARM_BUILTIN_TMIABT,
2674 ARM_BUILTIN_TMIATB,
2675 ARM_BUILTIN_TMIATT,
2676
2677 ARM_BUILTIN_TMOVMSKB,
2678 ARM_BUILTIN_TMOVMSKH,
2679 ARM_BUILTIN_TMOVMSKW,
2680
2681 ARM_BUILTIN_TBCSTB,
2682 ARM_BUILTIN_TBCSTH,
2683 ARM_BUILTIN_TBCSTW,
2684
2685 ARM_BUILTIN_WMADDS,
2686 ARM_BUILTIN_WMADDU,
2687
2688 ARM_BUILTIN_WPACKHSS,
2689 ARM_BUILTIN_WPACKWSS,
2690 ARM_BUILTIN_WPACKDSS,
2691 ARM_BUILTIN_WPACKHUS,
2692 ARM_BUILTIN_WPACKWUS,
2693 ARM_BUILTIN_WPACKDUS,
2694
2695 ARM_BUILTIN_WADDB,
2696 ARM_BUILTIN_WADDH,
2697 ARM_BUILTIN_WADDW,
2698 ARM_BUILTIN_WADDSSB,
2699 ARM_BUILTIN_WADDSSH,
2700 ARM_BUILTIN_WADDSSW,
2701 ARM_BUILTIN_WADDUSB,
2702 ARM_BUILTIN_WADDUSH,
2703 ARM_BUILTIN_WADDUSW,
2704 ARM_BUILTIN_WSUBB,
2705 ARM_BUILTIN_WSUBH,
2706 ARM_BUILTIN_WSUBW,
2707 ARM_BUILTIN_WSUBSSB,
2708 ARM_BUILTIN_WSUBSSH,
2709 ARM_BUILTIN_WSUBSSW,
2710 ARM_BUILTIN_WSUBUSB,
2711 ARM_BUILTIN_WSUBUSH,
2712 ARM_BUILTIN_WSUBUSW,
2713
2714 ARM_BUILTIN_WAND,
2715 ARM_BUILTIN_WANDN,
2716 ARM_BUILTIN_WOR,
2717 ARM_BUILTIN_WXOR,
2718
2719 ARM_BUILTIN_WCMPEQB,
2720 ARM_BUILTIN_WCMPEQH,
2721 ARM_BUILTIN_WCMPEQW,
2722 ARM_BUILTIN_WCMPGTUB,
2723 ARM_BUILTIN_WCMPGTUH,
2724 ARM_BUILTIN_WCMPGTUW,
2725 ARM_BUILTIN_WCMPGTSB,
2726 ARM_BUILTIN_WCMPGTSH,
2727 ARM_BUILTIN_WCMPGTSW,
2728
2729 ARM_BUILTIN_TEXTRMSB,
2730 ARM_BUILTIN_TEXTRMSH,
2731 ARM_BUILTIN_TEXTRMSW,
2732 ARM_BUILTIN_TEXTRMUB,
2733 ARM_BUILTIN_TEXTRMUH,
2734 ARM_BUILTIN_TEXTRMUW,
2735 ARM_BUILTIN_TINSRB,
2736 ARM_BUILTIN_TINSRH,
2737 ARM_BUILTIN_TINSRW,
2738
2739 ARM_BUILTIN_WMAXSW,
2740 ARM_BUILTIN_WMAXSH,
2741 ARM_BUILTIN_WMAXSB,
2742 ARM_BUILTIN_WMAXUW,
2743 ARM_BUILTIN_WMAXUH,
2744 ARM_BUILTIN_WMAXUB,
2745 ARM_BUILTIN_WMINSW,
2746 ARM_BUILTIN_WMINSH,
2747 ARM_BUILTIN_WMINSB,
2748 ARM_BUILTIN_WMINUW,
2749 ARM_BUILTIN_WMINUH,
2750 ARM_BUILTIN_WMINUB,
2751
2752 ARM_BUILTIN_WMULUM,
2753 ARM_BUILTIN_WMULSM,
2754 ARM_BUILTIN_WMULUL,
2755
2756 ARM_BUILTIN_PSADBH,
2757 ARM_BUILTIN_WSHUFH,
2758
2759 ARM_BUILTIN_WSLLH,
2760 ARM_BUILTIN_WSLLW,
2761 ARM_BUILTIN_WSLLD,
2762 ARM_BUILTIN_WSRAH,
2763 ARM_BUILTIN_WSRAW,
2764 ARM_BUILTIN_WSRAD,
2765 ARM_BUILTIN_WSRLH,
2766 ARM_BUILTIN_WSRLW,
2767 ARM_BUILTIN_WSRLD,
2768 ARM_BUILTIN_WRORH,
2769 ARM_BUILTIN_WRORW,
2770 ARM_BUILTIN_WRORD,
2771 ARM_BUILTIN_WSLLHI,
2772 ARM_BUILTIN_WSLLWI,
2773 ARM_BUILTIN_WSLLDI,
2774 ARM_BUILTIN_WSRAHI,
2775 ARM_BUILTIN_WSRAWI,
2776 ARM_BUILTIN_WSRADI,
2777 ARM_BUILTIN_WSRLHI,
2778 ARM_BUILTIN_WSRLWI,
2779 ARM_BUILTIN_WSRLDI,
2780 ARM_BUILTIN_WRORHI,
2781 ARM_BUILTIN_WRORWI,
2782 ARM_BUILTIN_WRORDI,
2783
2784 ARM_BUILTIN_WUNPCKIHB,
2785 ARM_BUILTIN_WUNPCKIHH,
2786 ARM_BUILTIN_WUNPCKIHW,
2787 ARM_BUILTIN_WUNPCKILB,
2788 ARM_BUILTIN_WUNPCKILH,
2789 ARM_BUILTIN_WUNPCKILW,
2790
2791 ARM_BUILTIN_WUNPCKEHSB,
2792 ARM_BUILTIN_WUNPCKEHSH,
2793 ARM_BUILTIN_WUNPCKEHSW,
2794 ARM_BUILTIN_WUNPCKEHUB,
2795 ARM_BUILTIN_WUNPCKEHUH,
2796 ARM_BUILTIN_WUNPCKEHUW,
2797 ARM_BUILTIN_WUNPCKELSB,
2798 ARM_BUILTIN_WUNPCKELSH,
2799 ARM_BUILTIN_WUNPCKELSW,
2800 ARM_BUILTIN_WUNPCKELUB,
2801 ARM_BUILTIN_WUNPCKELUH,
2802 ARM_BUILTIN_WUNPCKELUW,
2803
2804 ARM_BUILTIN_THREAD_POINTER,
2805
2806 ARM_BUILTIN_NEON_BASE,
2807
2808 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2809 };
2810
2811 /* Do not emit .note.GNU-stack by default. */
2812 #ifndef NEED_INDICATE_EXEC_STACK
2813 #define NEED_INDICATE_EXEC_STACK 0
2814 #endif
2815
2816 #endif /* ! GCC_ARM_H */
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