gcc/testsuite/gcc.target/i386/vect-addsub.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-O2 -ftree-vectorize -msse4 -mtune=generic" } */
   3
   4 /* We need SSE4 so the backend recognizes a { 0, 5, 2, 7 } constant
   5    permutation as supported as the vectorizer wants to generate
   6
   7      vect__6.10_24 = vect__3.6_20 - vect__5.9_23;
   8      vect__6.11_25 = vect__3.6_20 + vect__5.9_23;
   9      _26 = VEC_PERM_EXPR <vect__6.10_24, vect__6.11_25, { 0, 5, 2, 7 }>;
  10
  11    See also the ??? comment about using and/andn/or in expand_vec_perm_blend
  12    for non-SSE4 targets.  */
  13
  14 void testf (float * __restrict__ p, float * __restrict q)
  15 {
  16   p[0] = p[0] - q[0];
  17   p[1] = p[1] + q[1];
  18   p[2] = p[2] - q[2];
  19   p[3] = p[3] + q[3];
  20 }
  21
  22 /* { dg-final { scan-assembler "addsubps" } } */