gcc/testsuite/gcc.target/i386/pr82361-1.c

   1 /* PR target/82361 */
   2 /* { dg-do compile { target lp64 } } */
   3 /* { dg-options "-O2 -mtune=generic -masm=att -mno-8bit-idiv" } */
   4 /* We should be able to optimize all %eax to %rax zero extensions, because
   5    div and idiv instructions with 32-bit operands zero-extend both results.   */
   6 /* { dg-final { scan-assembler-not "movl\t%eax, %eax" } } */
   7 /* FIXME: We are still not able to optimize the modulo in f1/f2, only manage
   8    one.  */
   9 /* { dg-final { scan-assembler-times "movl\t%edx, %edx" 2 } } */
  10
  11 void
  12 f1 (unsigned int a, unsigned int b)
  13 {
  14   unsigned long long c = a / b;
  15   unsigned long long d = a % b;
  16   asm volatile ("" : : "r" (c), "r" (d));
  17 }
  18
  19 void
  20 f2 (int a, int b)
  21 {
  22   unsigned long long c = (unsigned int) (a / b);
  23   unsigned long long d = (unsigned int) (a % b);
  24   asm volatile ("" : : "r" (c), "r" (d));
  25 }
  26
  27 void
  28 f3 (unsigned int a, unsigned int b)
  29 {
  30   unsigned long long c = a / b;
  31   asm volatile ("" : : "r" (c));
  32 }
  33
  34 void
  35 f4 (int a, int b)
  36 {
  37   unsigned long long c = (unsigned int) (a / b);
  38   asm volatile ("" : : "r" (c));
  39 }
  40
  41 void
  42 f5 (unsigned int a, unsigned int b)
  43 {
  44   unsigned long long d = a % b;
  45   asm volatile ("" : : "r" (d));
  46 }
  47
  48 void
  49 f6 (int a, int b)
  50 {
  51   unsigned long long d = (unsigned int) (a % b);
  52   asm volatile ("" : : "r" (d));
  53 }