gcc/testsuite/gcc.target/aarch64/sve/slp_3.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=scalable" } */
   3
   4 #include <stdint.h>
   5
   6 #define VEC_PERM(TYPE)                                          \
   7 TYPE __attribute__ ((noinline, noclone))                        \
   8 vec_slp_##TYPE (TYPE *restrict a, int n)                        \
   9 {                                                               \
  10   for (int i = 0; i < n; ++i)                                   \
  11     {                                                           \
  12       a[i * 4] += 41;                                           \
  13       a[i * 4 + 1] += 25;                                       \
  14       a[i * 4 + 2] += 31;                                       \
  15       a[i * 4 + 3] += 62;                                       \
  16     }                                                           \
  17 }
  18
  19 #define TEST_ALL(T)                             \
  20   T (int8_t)                                    \
  21   T (uint8_t)                                   \
  22   T (int16_t)                                   \
  23   T (uint16_t)                                  \
  24   T (int32_t)                                   \
  25   T (uint32_t)                                  \
  26   T (int64_t)                                   \
  27   T (uint64_t)                                  \
  28   T (_Float16)                                  \
  29   T (float)                                     \
  30   T (double)
  31
  32 TEST_ALL (VEC_PERM)
  33
  34 /* 1 for each 8-bit type.  */
  35 /* { dg-final { scan-assembler-times {\tld1rw\tz[0-9]+\.s, } 2 } } */
  36 /* 1 for each 16-bit type and 4 for double.  */
  37 /* { dg-final { scan-assembler-times {\tld1rd\tz[0-9]+\.d, } 7 } } */
  38 /* 1 for each 32-bit type.  */
  39 /* { dg-final { scan-assembler-times {\tld1rqw\tz[0-9]+\.s, } 3 } } */
  40 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #41\n} 2 } } */
  41 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #25\n} 2 } } */
  42 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #31\n} 2 } } */
  43 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #62\n} 2 } } */
  44 /* The 64-bit types need:
  45
  46       ZIP1 ZIP1 (2 ZIP2s optimized away)
  47       ZIP1 ZIP2.  */
  48 /* { dg-final { scan-assembler-times {\tzip1\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 9 } } */
  49 /* { dg-final { scan-assembler-times {\tzip2\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */
  50
  51 /* The loop should be fully-masked.  The 64-bit types need two loads
  52    and stores each.  */
  53 /* { dg-final { scan-assembler-times {\tld1b\t} 2 } } */
  54 /* { dg-final { scan-assembler-times {\tst1b\t} 2 } } */
  55 /* { dg-final { scan-assembler-times {\tld1h\t} 3 } } */
  56 /* { dg-final { scan-assembler-times {\tst1h\t} 3 } } */
  57 /* { dg-final { scan-assembler-times {\tld1w\t} 3 } } */
  58 /* { dg-final { scan-assembler-times {\tst1w\t} 3 } } */
  59 /* { dg-final { scan-assembler-times {\tld1d\t} 6 } } */
  60 /* { dg-final { scan-assembler-times {\tst1d\t} 6 } } */
  61 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.b} 4 } } */
  62 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.h} 6 } } */
  63 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.s} 6 } } */
  64 /* { dg-final { scan-assembler-times {\twhilelo\tp[0-7]\.d} 12 } } */
  65 /* { dg-final { scan-assembler-not {\tldr} } } */
  66 /* { dg-final { scan-assembler-not {\tstr} } } */
  67
  68 /* { dg-final { scan-assembler-not {\tuqdec[bhw]\t} } } */
  69 /* { dg-final { scan-assembler-times {\tuqdecd\t} 3 } } */