1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2014 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
35 #include "stringpool.h"
36 #include "stor-layout.h"
38 #include "print-tree.h"
46 #include "basic-block.h"
47 #include "diagnostic-core.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
58 #include "sched-int.h"
59 #include "pointer-set.h"
60 #include "hash-table.h"
62 #include "basic-block.h"
63 #include "tree-ssa-alias.h"
64 #include "internal-fn.h"
65 #include "gimple-fold.h"
67 #include "gimple-expr.h"
71 #include "gimple-iterator.h"
72 #include "gimple-walk.h"
75 #include "tm-constrs.h"
78 #include "tree-vectorizer.h"
81 #include "target-globals.h"
84 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
87 #include "gstab.h" /* for N_SLINE */
90 #ifndef TARGET_NO_PROTOTYPE
91 #define TARGET_NO_PROTOTYPE 0
94 #define min(A,B) ((A) < (B) ? (A) : (B))
95 #define max(A,B) ((A) > (B) ? (A) : (B))
97 /* Structure used to define the rs6000 stack */
98 typedef struct rs6000_stack
{
99 int reload_completed
; /* stack info won't change from here on */
100 int first_gp_reg_save
; /* first callee saved GP register used */
101 int first_fp_reg_save
; /* first callee saved FP register used */
102 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
103 int lr_save_p
; /* true if the link reg needs to be saved */
104 int cr_save_p
; /* true if the CR reg needs to be saved */
105 unsigned int vrsave_mask
; /* mask of vec registers to save */
106 int push_p
; /* true if we need to allocate stack space */
107 int calls_p
; /* true if the function makes any calls */
108 int world_save_p
; /* true if we're saving *everything*:
109 r13-r31, cr, f14-f31, vrsave, v20-v31 */
110 enum rs6000_abi abi
; /* which ABI to use */
111 int gp_save_offset
; /* offset to save GP regs from initial SP */
112 int fp_save_offset
; /* offset to save FP regs from initial SP */
113 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
114 int lr_save_offset
; /* offset to save LR from initial SP */
115 int cr_save_offset
; /* offset to save CR from initial SP */
116 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
117 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
118 int varargs_save_offset
; /* offset to save the varargs registers */
119 int ehrd_offset
; /* offset to EH return data */
120 int ehcr_offset
; /* offset to EH CR field data */
121 int reg_size
; /* register size (4 or 8) */
122 HOST_WIDE_INT vars_size
; /* variable save area size */
123 int parm_size
; /* outgoing parameter size */
124 int save_size
; /* save area size */
125 int fixed_size
; /* fixed size of stack frame */
126 int gp_size
; /* size of saved GP registers */
127 int fp_size
; /* size of saved FP registers */
128 int altivec_size
; /* size of saved AltiVec registers */
129 int cr_size
; /* size to hold CR if not in save_size */
130 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
131 int altivec_padding_size
; /* size of altivec alignment padding if
133 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
134 int spe_padding_size
;
135 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
136 int spe_64bit_regs_used
;
140 /* A C structure for machine-specific, per-function data.
141 This is added to the cfun structure. */
142 typedef struct GTY(()) machine_function
144 /* Some local-dynamic symbol. */
145 const char *some_ld_name
;
146 /* Whether the instruction chain has been scanned already. */
147 int insn_chain_scanned_p
;
148 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
149 int ra_needs_full_frame
;
150 /* Flags if __builtin_return_address (0) was used. */
152 /* Cache lr_save_p after expansion of builtin_eh_return. */
154 /* Whether we need to save the TOC to the reserved stack location in the
155 function prologue. */
156 bool save_toc_in_prologue
;
157 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
158 varargs save area. */
159 HOST_WIDE_INT varargs_save_offset
;
160 /* Temporary stack slot to use for SDmode copies. This slot is
161 64-bits wide and is allocated early enough so that the offset
162 does not overflow the 16-bit load/store offset field. */
163 rtx sdmode_stack_slot
;
164 /* Flag if r2 setup is needed with ELFv2 ABI. */
165 bool r2_setup_needed
;
168 /* Support targetm.vectorize.builtin_mask_for_load. */
169 static GTY(()) tree altivec_builtin_mask_for_load
;
171 /* Set to nonzero once AIX common-mode calls have been defined. */
172 static GTY(()) int common_mode_defined
;
174 /* Label number of label created for -mrelocatable, to call to so we can
175 get the address of the GOT section */
176 static int rs6000_pic_labelno
;
179 /* Counter for labels which are to be placed in .fixup. */
180 int fixuplabelno
= 0;
183 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
186 /* Specify the machine mode that pointers have. After generation of rtl, the
187 compiler makes no further distinction between pointers and any other objects
188 of this machine mode. The type is unsigned since not all things that
189 include rs6000.h also include machmode.h. */
190 unsigned rs6000_pmode
;
192 /* Width in bits of a pointer. */
193 unsigned rs6000_pointer_size
;
195 #ifdef HAVE_AS_GNU_ATTRIBUTE
196 /* Flag whether floating point values have been passed/returned. */
197 static bool rs6000_passes_float
;
198 /* Flag whether vector values have been passed/returned. */
199 static bool rs6000_passes_vector
;
200 /* Flag whether small (<= 8 byte) structures have been returned. */
201 static bool rs6000_returns_struct
;
204 /* Value is TRUE if register/mode pair is acceptable. */
205 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
207 /* Maximum number of registers needed for a given register class and mode. */
208 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
210 /* How many registers are needed for a given register and mode. */
211 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
213 /* Map register number to register class. */
214 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
216 static int dbg_cost_ctrl
;
218 /* Built in types. */
219 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
220 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
222 /* Flag to say the TOC is initialized */
224 char toc_label_name
[10];
226 /* Cached value of rs6000_variable_issue. This is cached in
227 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
228 static short cached_can_issue_more
;
230 static GTY(()) section
*read_only_data_section
;
231 static GTY(()) section
*private_data_section
;
232 static GTY(()) section
*tls_data_section
;
233 static GTY(()) section
*tls_private_data_section
;
234 static GTY(()) section
*read_only_private_data_section
;
235 static GTY(()) section
*sdata2_section
;
236 static GTY(()) section
*toc_section
;
238 struct builtin_description
240 const HOST_WIDE_INT mask
;
241 const enum insn_code icode
;
242 const char *const name
;
243 const enum rs6000_builtins code
;
246 /* Describe the vector unit used for modes. */
247 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
248 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
250 /* Register classes for various constraints that are based on the target
252 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
254 /* Describe the alignment of a vector. */
255 int rs6000_vector_align
[NUM_MACHINE_MODES
];
257 /* Map selected modes to types for builtins. */
258 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
260 /* What modes to automatically generate reciprocal divide estimate (fre) and
261 reciprocal sqrt (frsqrte) for. */
262 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
264 /* Masks to determine which reciprocal esitmate instructions to generate
266 enum rs6000_recip_mask
{
267 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
268 RECIP_DF_DIV
= 0x002,
269 RECIP_V4SF_DIV
= 0x004,
270 RECIP_V2DF_DIV
= 0x008,
272 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
273 RECIP_DF_RSQRT
= 0x020,
274 RECIP_V4SF_RSQRT
= 0x040,
275 RECIP_V2DF_RSQRT
= 0x080,
277 /* Various combination of flags for -mrecip=xxx. */
279 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
280 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
281 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
283 RECIP_HIGH_PRECISION
= RECIP_ALL
,
285 /* On low precision machines like the power5, don't enable double precision
286 reciprocal square root estimate, since it isn't accurate enough. */
287 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
290 /* -mrecip options. */
293 const char *string
; /* option name */
294 unsigned int mask
; /* mask bits to set */
295 } recip_options
[] = {
296 { "all", RECIP_ALL
},
297 { "none", RECIP_NONE
},
298 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
300 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
301 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
302 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
303 | RECIP_V2DF_RSQRT
) },
304 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
305 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
308 /* Pointer to function (in rs6000-c.c) that can define or undefine target
309 macros that have changed. Languages that don't support the preprocessor
310 don't link in rs6000-c.c, so we can't call it directly. */
311 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
313 /* Simplfy register classes into simpler classifications. We assume
314 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
315 check for standard register classes (gpr/floating/altivec/vsx) and
316 floating/vector classes (float/altivec/vsx). */
318 enum rs6000_reg_type
{
331 /* Map register class to register type. */
332 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
334 /* First/last register type for the 'normal' register types (i.e. general
335 purpose, floating point, altivec, and VSX registers). */
336 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
338 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
341 /* Register classes we care about in secondary reload or go if legitimate
342 address. We only need to worry about GPR, FPR, and Altivec registers here,
343 along an ANY field that is the OR of the 3 register classes. */
345 enum rs6000_reload_reg_type
{
346 RELOAD_REG_GPR
, /* General purpose registers. */
347 RELOAD_REG_FPR
, /* Traditional floating point regs. */
348 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
349 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
353 /* For setting up register classes, loop through the 3 register classes mapping
354 into real registers, and skip the ANY class, which is just an OR of the
356 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
357 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
359 /* Map reload register type to a register in the register class. */
360 struct reload_reg_map_type
{
361 const char *name
; /* Register class name. */
362 int reg
; /* Register in the register class. */
365 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
366 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
367 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
368 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
369 { "Any", -1 }, /* RELOAD_REG_ANY. */
372 /* Mask bits for each register class, indexed per mode. Historically the
373 compiler has been more restrictive which types can do PRE_MODIFY instead of
374 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
375 typedef unsigned char addr_mask_type
;
377 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
378 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
379 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
380 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
381 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
382 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
384 /* Register type masks based on the type, of valid addressing modes. */
385 struct rs6000_reg_addr
{
386 enum insn_code reload_load
; /* INSN to reload for loading. */
387 enum insn_code reload_store
; /* INSN to reload for storing. */
388 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
389 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
390 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
391 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
394 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
396 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
398 mode_supports_pre_incdec_p (enum machine_mode mode
)
400 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
404 /* Helper function to say whether a mode supports PRE_MODIFY. */
406 mode_supports_pre_modify_p (enum machine_mode mode
)
408 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
413 /* Target cpu costs. */
415 struct processor_costs
{
416 const int mulsi
; /* cost of SImode multiplication. */
417 const int mulsi_const
; /* cost of SImode multiplication by constant. */
418 const int mulsi_const9
; /* cost of SImode mult by short constant. */
419 const int muldi
; /* cost of DImode multiplication. */
420 const int divsi
; /* cost of SImode division. */
421 const int divdi
; /* cost of DImode division. */
422 const int fp
; /* cost of simple SFmode and DFmode insns. */
423 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
424 const int sdiv
; /* cost of SFmode division (fdivs). */
425 const int ddiv
; /* cost of DFmode division (fdiv). */
426 const int cache_line_size
; /* cache line size in bytes. */
427 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
428 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
429 const int simultaneous_prefetches
; /* number of parallel prefetch
433 const struct processor_costs
*rs6000_cost
;
435 /* Processor costs (relative to an add) */
437 /* Instruction size costs on 32bit processors. */
439 struct processor_costs size32_cost
= {
440 COSTS_N_INSNS (1), /* mulsi */
441 COSTS_N_INSNS (1), /* mulsi_const */
442 COSTS_N_INSNS (1), /* mulsi_const9 */
443 COSTS_N_INSNS (1), /* muldi */
444 COSTS_N_INSNS (1), /* divsi */
445 COSTS_N_INSNS (1), /* divdi */
446 COSTS_N_INSNS (1), /* fp */
447 COSTS_N_INSNS (1), /* dmul */
448 COSTS_N_INSNS (1), /* sdiv */
449 COSTS_N_INSNS (1), /* ddiv */
456 /* Instruction size costs on 64bit processors. */
458 struct processor_costs size64_cost
= {
459 COSTS_N_INSNS (1), /* mulsi */
460 COSTS_N_INSNS (1), /* mulsi_const */
461 COSTS_N_INSNS (1), /* mulsi_const9 */
462 COSTS_N_INSNS (1), /* muldi */
463 COSTS_N_INSNS (1), /* divsi */
464 COSTS_N_INSNS (1), /* divdi */
465 COSTS_N_INSNS (1), /* fp */
466 COSTS_N_INSNS (1), /* dmul */
467 COSTS_N_INSNS (1), /* sdiv */
468 COSTS_N_INSNS (1), /* ddiv */
475 /* Instruction costs on RS64A processors. */
477 struct processor_costs rs64a_cost
= {
478 COSTS_N_INSNS (20), /* mulsi */
479 COSTS_N_INSNS (12), /* mulsi_const */
480 COSTS_N_INSNS (8), /* mulsi_const9 */
481 COSTS_N_INSNS (34), /* muldi */
482 COSTS_N_INSNS (65), /* divsi */
483 COSTS_N_INSNS (67), /* divdi */
484 COSTS_N_INSNS (4), /* fp */
485 COSTS_N_INSNS (4), /* dmul */
486 COSTS_N_INSNS (31), /* sdiv */
487 COSTS_N_INSNS (31), /* ddiv */
488 128, /* cache line size */
494 /* Instruction costs on MPCCORE processors. */
496 struct processor_costs mpccore_cost
= {
497 COSTS_N_INSNS (2), /* mulsi */
498 COSTS_N_INSNS (2), /* mulsi_const */
499 COSTS_N_INSNS (2), /* mulsi_const9 */
500 COSTS_N_INSNS (2), /* muldi */
501 COSTS_N_INSNS (6), /* divsi */
502 COSTS_N_INSNS (6), /* divdi */
503 COSTS_N_INSNS (4), /* fp */
504 COSTS_N_INSNS (5), /* dmul */
505 COSTS_N_INSNS (10), /* sdiv */
506 COSTS_N_INSNS (17), /* ddiv */
507 32, /* cache line size */
513 /* Instruction costs on PPC403 processors. */
515 struct processor_costs ppc403_cost
= {
516 COSTS_N_INSNS (4), /* mulsi */
517 COSTS_N_INSNS (4), /* mulsi_const */
518 COSTS_N_INSNS (4), /* mulsi_const9 */
519 COSTS_N_INSNS (4), /* muldi */
520 COSTS_N_INSNS (33), /* divsi */
521 COSTS_N_INSNS (33), /* divdi */
522 COSTS_N_INSNS (11), /* fp */
523 COSTS_N_INSNS (11), /* dmul */
524 COSTS_N_INSNS (11), /* sdiv */
525 COSTS_N_INSNS (11), /* ddiv */
526 32, /* cache line size */
532 /* Instruction costs on PPC405 processors. */
534 struct processor_costs ppc405_cost
= {
535 COSTS_N_INSNS (5), /* mulsi */
536 COSTS_N_INSNS (4), /* mulsi_const */
537 COSTS_N_INSNS (3), /* mulsi_const9 */
538 COSTS_N_INSNS (5), /* muldi */
539 COSTS_N_INSNS (35), /* divsi */
540 COSTS_N_INSNS (35), /* divdi */
541 COSTS_N_INSNS (11), /* fp */
542 COSTS_N_INSNS (11), /* dmul */
543 COSTS_N_INSNS (11), /* sdiv */
544 COSTS_N_INSNS (11), /* ddiv */
545 32, /* cache line size */
551 /* Instruction costs on PPC440 processors. */
553 struct processor_costs ppc440_cost
= {
554 COSTS_N_INSNS (3), /* mulsi */
555 COSTS_N_INSNS (2), /* mulsi_const */
556 COSTS_N_INSNS (2), /* mulsi_const9 */
557 COSTS_N_INSNS (3), /* muldi */
558 COSTS_N_INSNS (34), /* divsi */
559 COSTS_N_INSNS (34), /* divdi */
560 COSTS_N_INSNS (5), /* fp */
561 COSTS_N_INSNS (5), /* dmul */
562 COSTS_N_INSNS (19), /* sdiv */
563 COSTS_N_INSNS (33), /* ddiv */
564 32, /* cache line size */
570 /* Instruction costs on PPC476 processors. */
572 struct processor_costs ppc476_cost
= {
573 COSTS_N_INSNS (4), /* mulsi */
574 COSTS_N_INSNS (4), /* mulsi_const */
575 COSTS_N_INSNS (4), /* mulsi_const9 */
576 COSTS_N_INSNS (4), /* muldi */
577 COSTS_N_INSNS (11), /* divsi */
578 COSTS_N_INSNS (11), /* divdi */
579 COSTS_N_INSNS (6), /* fp */
580 COSTS_N_INSNS (6), /* dmul */
581 COSTS_N_INSNS (19), /* sdiv */
582 COSTS_N_INSNS (33), /* ddiv */
583 32, /* l1 cache line size */
589 /* Instruction costs on PPC601 processors. */
591 struct processor_costs ppc601_cost
= {
592 COSTS_N_INSNS (5), /* mulsi */
593 COSTS_N_INSNS (5), /* mulsi_const */
594 COSTS_N_INSNS (5), /* mulsi_const9 */
595 COSTS_N_INSNS (5), /* muldi */
596 COSTS_N_INSNS (36), /* divsi */
597 COSTS_N_INSNS (36), /* divdi */
598 COSTS_N_INSNS (4), /* fp */
599 COSTS_N_INSNS (5), /* dmul */
600 COSTS_N_INSNS (17), /* sdiv */
601 COSTS_N_INSNS (31), /* ddiv */
602 32, /* cache line size */
608 /* Instruction costs on PPC603 processors. */
610 struct processor_costs ppc603_cost
= {
611 COSTS_N_INSNS (5), /* mulsi */
612 COSTS_N_INSNS (3), /* mulsi_const */
613 COSTS_N_INSNS (2), /* mulsi_const9 */
614 COSTS_N_INSNS (5), /* muldi */
615 COSTS_N_INSNS (37), /* divsi */
616 COSTS_N_INSNS (37), /* divdi */
617 COSTS_N_INSNS (3), /* fp */
618 COSTS_N_INSNS (4), /* dmul */
619 COSTS_N_INSNS (18), /* sdiv */
620 COSTS_N_INSNS (33), /* ddiv */
621 32, /* cache line size */
627 /* Instruction costs on PPC604 processors. */
629 struct processor_costs ppc604_cost
= {
630 COSTS_N_INSNS (4), /* mulsi */
631 COSTS_N_INSNS (4), /* mulsi_const */
632 COSTS_N_INSNS (4), /* mulsi_const9 */
633 COSTS_N_INSNS (4), /* muldi */
634 COSTS_N_INSNS (20), /* divsi */
635 COSTS_N_INSNS (20), /* divdi */
636 COSTS_N_INSNS (3), /* fp */
637 COSTS_N_INSNS (3), /* dmul */
638 COSTS_N_INSNS (18), /* sdiv */
639 COSTS_N_INSNS (32), /* ddiv */
640 32, /* cache line size */
646 /* Instruction costs on PPC604e processors. */
648 struct processor_costs ppc604e_cost
= {
649 COSTS_N_INSNS (2), /* mulsi */
650 COSTS_N_INSNS (2), /* mulsi_const */
651 COSTS_N_INSNS (2), /* mulsi_const9 */
652 COSTS_N_INSNS (2), /* muldi */
653 COSTS_N_INSNS (20), /* divsi */
654 COSTS_N_INSNS (20), /* divdi */
655 COSTS_N_INSNS (3), /* fp */
656 COSTS_N_INSNS (3), /* dmul */
657 COSTS_N_INSNS (18), /* sdiv */
658 COSTS_N_INSNS (32), /* ddiv */
659 32, /* cache line size */
665 /* Instruction costs on PPC620 processors. */
667 struct processor_costs ppc620_cost
= {
668 COSTS_N_INSNS (5), /* mulsi */
669 COSTS_N_INSNS (4), /* mulsi_const */
670 COSTS_N_INSNS (3), /* mulsi_const9 */
671 COSTS_N_INSNS (7), /* muldi */
672 COSTS_N_INSNS (21), /* divsi */
673 COSTS_N_INSNS (37), /* divdi */
674 COSTS_N_INSNS (3), /* fp */
675 COSTS_N_INSNS (3), /* dmul */
676 COSTS_N_INSNS (18), /* sdiv */
677 COSTS_N_INSNS (32), /* ddiv */
678 128, /* cache line size */
684 /* Instruction costs on PPC630 processors. */
686 struct processor_costs ppc630_cost
= {
687 COSTS_N_INSNS (5), /* mulsi */
688 COSTS_N_INSNS (4), /* mulsi_const */
689 COSTS_N_INSNS (3), /* mulsi_const9 */
690 COSTS_N_INSNS (7), /* muldi */
691 COSTS_N_INSNS (21), /* divsi */
692 COSTS_N_INSNS (37), /* divdi */
693 COSTS_N_INSNS (3), /* fp */
694 COSTS_N_INSNS (3), /* dmul */
695 COSTS_N_INSNS (17), /* sdiv */
696 COSTS_N_INSNS (21), /* ddiv */
697 128, /* cache line size */
703 /* Instruction costs on Cell processor. */
704 /* COSTS_N_INSNS (1) ~ one add. */
706 struct processor_costs ppccell_cost
= {
707 COSTS_N_INSNS (9/2)+2, /* mulsi */
708 COSTS_N_INSNS (6/2), /* mulsi_const */
709 COSTS_N_INSNS (6/2), /* mulsi_const9 */
710 COSTS_N_INSNS (15/2)+2, /* muldi */
711 COSTS_N_INSNS (38/2), /* divsi */
712 COSTS_N_INSNS (70/2), /* divdi */
713 COSTS_N_INSNS (10/2), /* fp */
714 COSTS_N_INSNS (10/2), /* dmul */
715 COSTS_N_INSNS (74/2), /* sdiv */
716 COSTS_N_INSNS (74/2), /* ddiv */
717 128, /* cache line size */
723 /* Instruction costs on PPC750 and PPC7400 processors. */
725 struct processor_costs ppc750_cost
= {
726 COSTS_N_INSNS (5), /* mulsi */
727 COSTS_N_INSNS (3), /* mulsi_const */
728 COSTS_N_INSNS (2), /* mulsi_const9 */
729 COSTS_N_INSNS (5), /* muldi */
730 COSTS_N_INSNS (17), /* divsi */
731 COSTS_N_INSNS (17), /* divdi */
732 COSTS_N_INSNS (3), /* fp */
733 COSTS_N_INSNS (3), /* dmul */
734 COSTS_N_INSNS (17), /* sdiv */
735 COSTS_N_INSNS (31), /* ddiv */
736 32, /* cache line size */
742 /* Instruction costs on PPC7450 processors. */
744 struct processor_costs ppc7450_cost
= {
745 COSTS_N_INSNS (4), /* mulsi */
746 COSTS_N_INSNS (3), /* mulsi_const */
747 COSTS_N_INSNS (3), /* mulsi_const9 */
748 COSTS_N_INSNS (4), /* muldi */
749 COSTS_N_INSNS (23), /* divsi */
750 COSTS_N_INSNS (23), /* divdi */
751 COSTS_N_INSNS (5), /* fp */
752 COSTS_N_INSNS (5), /* dmul */
753 COSTS_N_INSNS (21), /* sdiv */
754 COSTS_N_INSNS (35), /* ddiv */
755 32, /* cache line size */
761 /* Instruction costs on PPC8540 processors. */
763 struct processor_costs ppc8540_cost
= {
764 COSTS_N_INSNS (4), /* mulsi */
765 COSTS_N_INSNS (4), /* mulsi_const */
766 COSTS_N_INSNS (4), /* mulsi_const9 */
767 COSTS_N_INSNS (4), /* muldi */
768 COSTS_N_INSNS (19), /* divsi */
769 COSTS_N_INSNS (19), /* divdi */
770 COSTS_N_INSNS (4), /* fp */
771 COSTS_N_INSNS (4), /* dmul */
772 COSTS_N_INSNS (29), /* sdiv */
773 COSTS_N_INSNS (29), /* ddiv */
774 32, /* cache line size */
777 1, /* prefetch streams /*/
780 /* Instruction costs on E300C2 and E300C3 cores. */
782 struct processor_costs ppce300c2c3_cost
= {
783 COSTS_N_INSNS (4), /* mulsi */
784 COSTS_N_INSNS (4), /* mulsi_const */
785 COSTS_N_INSNS (4), /* mulsi_const9 */
786 COSTS_N_INSNS (4), /* muldi */
787 COSTS_N_INSNS (19), /* divsi */
788 COSTS_N_INSNS (19), /* divdi */
789 COSTS_N_INSNS (3), /* fp */
790 COSTS_N_INSNS (4), /* dmul */
791 COSTS_N_INSNS (18), /* sdiv */
792 COSTS_N_INSNS (33), /* ddiv */
796 1, /* prefetch streams /*/
799 /* Instruction costs on PPCE500MC processors. */
801 struct processor_costs ppce500mc_cost
= {
802 COSTS_N_INSNS (4), /* mulsi */
803 COSTS_N_INSNS (4), /* mulsi_const */
804 COSTS_N_INSNS (4), /* mulsi_const9 */
805 COSTS_N_INSNS (4), /* muldi */
806 COSTS_N_INSNS (14), /* divsi */
807 COSTS_N_INSNS (14), /* divdi */
808 COSTS_N_INSNS (8), /* fp */
809 COSTS_N_INSNS (10), /* dmul */
810 COSTS_N_INSNS (36), /* sdiv */
811 COSTS_N_INSNS (66), /* ddiv */
812 64, /* cache line size */
815 1, /* prefetch streams /*/
818 /* Instruction costs on PPCE500MC64 processors. */
820 struct processor_costs ppce500mc64_cost
= {
821 COSTS_N_INSNS (4), /* mulsi */
822 COSTS_N_INSNS (4), /* mulsi_const */
823 COSTS_N_INSNS (4), /* mulsi_const9 */
824 COSTS_N_INSNS (4), /* muldi */
825 COSTS_N_INSNS (14), /* divsi */
826 COSTS_N_INSNS (14), /* divdi */
827 COSTS_N_INSNS (4), /* fp */
828 COSTS_N_INSNS (10), /* dmul */
829 COSTS_N_INSNS (36), /* sdiv */
830 COSTS_N_INSNS (66), /* ddiv */
831 64, /* cache line size */
834 1, /* prefetch streams /*/
837 /* Instruction costs on PPCE5500 processors. */
839 struct processor_costs ppce5500_cost
= {
840 COSTS_N_INSNS (5), /* mulsi */
841 COSTS_N_INSNS (5), /* mulsi_const */
842 COSTS_N_INSNS (4), /* mulsi_const9 */
843 COSTS_N_INSNS (5), /* muldi */
844 COSTS_N_INSNS (14), /* divsi */
845 COSTS_N_INSNS (14), /* divdi */
846 COSTS_N_INSNS (7), /* fp */
847 COSTS_N_INSNS (10), /* dmul */
848 COSTS_N_INSNS (36), /* sdiv */
849 COSTS_N_INSNS (66), /* ddiv */
850 64, /* cache line size */
853 1, /* prefetch streams /*/
856 /* Instruction costs on PPCE6500 processors. */
858 struct processor_costs ppce6500_cost
= {
859 COSTS_N_INSNS (5), /* mulsi */
860 COSTS_N_INSNS (5), /* mulsi_const */
861 COSTS_N_INSNS (4), /* mulsi_const9 */
862 COSTS_N_INSNS (5), /* muldi */
863 COSTS_N_INSNS (14), /* divsi */
864 COSTS_N_INSNS (14), /* divdi */
865 COSTS_N_INSNS (7), /* fp */
866 COSTS_N_INSNS (10), /* dmul */
867 COSTS_N_INSNS (36), /* sdiv */
868 COSTS_N_INSNS (66), /* ddiv */
869 64, /* cache line size */
872 1, /* prefetch streams /*/
875 /* Instruction costs on AppliedMicro Titan processors. */
877 struct processor_costs titan_cost
= {
878 COSTS_N_INSNS (5), /* mulsi */
879 COSTS_N_INSNS (5), /* mulsi_const */
880 COSTS_N_INSNS (5), /* mulsi_const9 */
881 COSTS_N_INSNS (5), /* muldi */
882 COSTS_N_INSNS (18), /* divsi */
883 COSTS_N_INSNS (18), /* divdi */
884 COSTS_N_INSNS (10), /* fp */
885 COSTS_N_INSNS (10), /* dmul */
886 COSTS_N_INSNS (46), /* sdiv */
887 COSTS_N_INSNS (72), /* ddiv */
888 32, /* cache line size */
891 1, /* prefetch streams /*/
894 /* Instruction costs on POWER4 and POWER5 processors. */
896 struct processor_costs power4_cost
= {
897 COSTS_N_INSNS (3), /* mulsi */
898 COSTS_N_INSNS (2), /* mulsi_const */
899 COSTS_N_INSNS (2), /* mulsi_const9 */
900 COSTS_N_INSNS (4), /* muldi */
901 COSTS_N_INSNS (18), /* divsi */
902 COSTS_N_INSNS (34), /* divdi */
903 COSTS_N_INSNS (3), /* fp */
904 COSTS_N_INSNS (3), /* dmul */
905 COSTS_N_INSNS (17), /* sdiv */
906 COSTS_N_INSNS (17), /* ddiv */
907 128, /* cache line size */
910 8, /* prefetch streams /*/
913 /* Instruction costs on POWER6 processors. */
915 struct processor_costs power6_cost
= {
916 COSTS_N_INSNS (8), /* mulsi */
917 COSTS_N_INSNS (8), /* mulsi_const */
918 COSTS_N_INSNS (8), /* mulsi_const9 */
919 COSTS_N_INSNS (8), /* muldi */
920 COSTS_N_INSNS (22), /* divsi */
921 COSTS_N_INSNS (28), /* divdi */
922 COSTS_N_INSNS (3), /* fp */
923 COSTS_N_INSNS (3), /* dmul */
924 COSTS_N_INSNS (13), /* sdiv */
925 COSTS_N_INSNS (16), /* ddiv */
926 128, /* cache line size */
929 16, /* prefetch streams */
932 /* Instruction costs on POWER7 processors. */
934 struct processor_costs power7_cost
= {
935 COSTS_N_INSNS (2), /* mulsi */
936 COSTS_N_INSNS (2), /* mulsi_const */
937 COSTS_N_INSNS (2), /* mulsi_const9 */
938 COSTS_N_INSNS (2), /* muldi */
939 COSTS_N_INSNS (18), /* divsi */
940 COSTS_N_INSNS (34), /* divdi */
941 COSTS_N_INSNS (3), /* fp */
942 COSTS_N_INSNS (3), /* dmul */
943 COSTS_N_INSNS (13), /* sdiv */
944 COSTS_N_INSNS (16), /* ddiv */
945 128, /* cache line size */
948 12, /* prefetch streams */
951 /* Instruction costs on POWER8 processors. */
953 struct processor_costs power8_cost
= {
954 COSTS_N_INSNS (3), /* mulsi */
955 COSTS_N_INSNS (3), /* mulsi_const */
956 COSTS_N_INSNS (3), /* mulsi_const9 */
957 COSTS_N_INSNS (3), /* muldi */
958 COSTS_N_INSNS (19), /* divsi */
959 COSTS_N_INSNS (35), /* divdi */
960 COSTS_N_INSNS (3), /* fp */
961 COSTS_N_INSNS (3), /* dmul */
962 COSTS_N_INSNS (14), /* sdiv */
963 COSTS_N_INSNS (17), /* ddiv */
964 128, /* cache line size */
967 12, /* prefetch streams */
970 /* Instruction costs on POWER A2 processors. */
972 struct processor_costs ppca2_cost
= {
973 COSTS_N_INSNS (16), /* mulsi */
974 COSTS_N_INSNS (16), /* mulsi_const */
975 COSTS_N_INSNS (16), /* mulsi_const9 */
976 COSTS_N_INSNS (16), /* muldi */
977 COSTS_N_INSNS (22), /* divsi */
978 COSTS_N_INSNS (28), /* divdi */
979 COSTS_N_INSNS (3), /* fp */
980 COSTS_N_INSNS (3), /* dmul */
981 COSTS_N_INSNS (59), /* sdiv */
982 COSTS_N_INSNS (72), /* ddiv */
986 16, /* prefetch streams */
990 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
991 #undef RS6000_BUILTIN_1
992 #undef RS6000_BUILTIN_2
993 #undef RS6000_BUILTIN_3
994 #undef RS6000_BUILTIN_A
995 #undef RS6000_BUILTIN_D
996 #undef RS6000_BUILTIN_E
997 #undef RS6000_BUILTIN_H
998 #undef RS6000_BUILTIN_P
999 #undef RS6000_BUILTIN_Q
1000 #undef RS6000_BUILTIN_S
1001 #undef RS6000_BUILTIN_X
1003 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1004 { NAME, ICODE, MASK, ATTR },
1006 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1007 { NAME, ICODE, MASK, ATTR },
1009 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1010 { NAME, ICODE, MASK, ATTR },
1012 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1013 { NAME, ICODE, MASK, ATTR },
1015 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1016 { NAME, ICODE, MASK, ATTR },
1018 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
1019 { NAME, ICODE, MASK, ATTR },
1021 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1022 { NAME, ICODE, MASK, ATTR },
1024 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1025 { NAME, ICODE, MASK, ATTR },
1027 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1028 { NAME, ICODE, MASK, ATTR },
1030 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
1031 { NAME, ICODE, MASK, ATTR },
1033 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1034 { NAME, ICODE, MASK, ATTR },
1036 struct rs6000_builtin_info_type
{
1038 const enum insn_code icode
;
1039 const HOST_WIDE_INT mask
;
1040 const unsigned attr
;
1043 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1045 #include "rs6000-builtin.def"
1048 #undef RS6000_BUILTIN_1
1049 #undef RS6000_BUILTIN_2
1050 #undef RS6000_BUILTIN_3
1051 #undef RS6000_BUILTIN_A
1052 #undef RS6000_BUILTIN_D
1053 #undef RS6000_BUILTIN_E
1054 #undef RS6000_BUILTIN_H
1055 #undef RS6000_BUILTIN_P
1056 #undef RS6000_BUILTIN_Q
1057 #undef RS6000_BUILTIN_S
1058 #undef RS6000_BUILTIN_X
1060 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1061 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
1064 static bool rs6000_debug_legitimate_address_p (enum machine_mode
, rtx
, bool);
1065 static bool spe_func_has_64bit_regs_p (void);
1066 static struct machine_function
* rs6000_init_machine_status (void);
1067 static int rs6000_ra_ever_killed (void);
1068 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1069 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1070 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1071 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
1072 static void rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
);
1073 static int rs6000_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
1074 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
1075 static int rs6000_debug_address_cost (rtx
, enum machine_mode
, addr_space_t
,
1077 static int rs6000_debug_adjust_cost (rtx
, rtx
, rtx
, int);
1078 static bool is_microcoded_insn (rtx
);
1079 static bool is_nonpipeline_insn (rtx
);
1080 static bool is_cracked_insn (rtx
);
1081 static bool is_load_insn (rtx
, rtx
*);
1082 static bool is_store_insn (rtx
, rtx
*);
1083 static bool set_to_load_agen (rtx
,rtx
);
1084 static bool insn_terminates_group_p (rtx
, enum group_termination
);
1085 static bool insn_must_be_first_in_group (rtx
);
1086 static bool insn_must_be_last_in_group (rtx
);
1087 static void altivec_init_builtins (void);
1088 static tree
builtin_function_type (enum machine_mode
, enum machine_mode
,
1089 enum machine_mode
, enum machine_mode
,
1090 enum rs6000_builtins
, const char *name
);
1091 static void rs6000_common_init_builtins (void);
1092 static void paired_init_builtins (void);
1093 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1094 static void spe_init_builtins (void);
1095 static void htm_init_builtins (void);
1096 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1097 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1098 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1099 static rs6000_stack_t
*rs6000_stack_info (void);
1100 static void is_altivec_return_reg (rtx
, void *);
1101 int easy_vector_constant (rtx
, enum machine_mode
);
1102 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, enum machine_mode
);
1103 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1104 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
1105 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
1106 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1109 static void macho_branch_islands (void);
1111 static rtx
rs6000_legitimize_reload_address (rtx
, enum machine_mode
, int, int,
1113 static rtx
rs6000_debug_legitimize_reload_address (rtx
, enum machine_mode
, int,
1115 static bool rs6000_mode_dependent_address (const_rtx
);
1116 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1117 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1118 enum machine_mode
, rtx
);
1119 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1122 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1123 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1125 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1127 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1130 static bool rs6000_cannot_change_mode_class (enum machine_mode
,
1133 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode
,
1136 static bool rs6000_save_toc_in_prologue_p (void);
1138 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, enum machine_mode
, int, int,
1140 = rs6000_legitimize_reload_address
;
1142 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1143 = rs6000_mode_dependent_address
;
1145 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1146 enum machine_mode
, rtx
)
1147 = rs6000_secondary_reload_class
;
1149 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1150 = rs6000_preferred_reload_class
;
1152 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1154 = rs6000_secondary_memory_needed
;
1156 bool (*rs6000_cannot_change_mode_class_ptr
) (enum machine_mode
,
1159 = rs6000_cannot_change_mode_class
;
1161 const int INSN_NOT_AVAILABLE
= -1;
1163 static void rs6000_print_isa_options (FILE *, int, const char *,
1165 static void rs6000_print_builtin_options (FILE *, int, const char *,
1168 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1169 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1170 enum rs6000_reg_type
,
1172 secondary_reload_info
*,
1175 /* Hash table stuff for keeping track of TOC entries. */
1177 struct GTY(()) toc_hash_struct
1179 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1180 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1182 enum machine_mode key_mode
;
1186 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
1188 /* Hash table to keep track of the argument types for builtin functions. */
1190 struct GTY(()) builtin_hash_struct
1193 enum machine_mode mode
[4]; /* return value + 3 arguments. */
1194 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1197 static GTY ((param_is (struct builtin_hash_struct
))) htab_t builtin_hash_table
;
1200 /* Default register names. */
1201 char rs6000_reg_names
[][8] =
1203 "0", "1", "2", "3", "4", "5", "6", "7",
1204 "8", "9", "10", "11", "12", "13", "14", "15",
1205 "16", "17", "18", "19", "20", "21", "22", "23",
1206 "24", "25", "26", "27", "28", "29", "30", "31",
1207 "0", "1", "2", "3", "4", "5", "6", "7",
1208 "8", "9", "10", "11", "12", "13", "14", "15",
1209 "16", "17", "18", "19", "20", "21", "22", "23",
1210 "24", "25", "26", "27", "28", "29", "30", "31",
1211 "mq", "lr", "ctr","ap",
1212 "0", "1", "2", "3", "4", "5", "6", "7",
1214 /* AltiVec registers. */
1215 "0", "1", "2", "3", "4", "5", "6", "7",
1216 "8", "9", "10", "11", "12", "13", "14", "15",
1217 "16", "17", "18", "19", "20", "21", "22", "23",
1218 "24", "25", "26", "27", "28", "29", "30", "31",
1220 /* SPE registers. */
1221 "spe_acc", "spefscr",
1222 /* Soft frame pointer. */
1224 /* HTM SPR registers. */
1225 "tfhar", "tfiar", "texasr"
1228 #ifdef TARGET_REGNAMES
1229 static const char alt_reg_names
[][8] =
1231 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1232 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1233 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1234 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1235 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1236 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1237 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1238 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1239 "mq", "lr", "ctr", "ap",
1240 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1242 /* AltiVec registers. */
1243 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1244 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1245 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1246 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1248 /* SPE registers. */
1249 "spe_acc", "spefscr",
1250 /* Soft frame pointer. */
1252 /* HTM SPR registers. */
1253 "tfhar", "tfiar", "texasr"
1257 /* Table of valid machine attributes. */
1259 static const struct attribute_spec rs6000_attribute_table
[] =
1261 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1262 affects_type_identity } */
1263 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1265 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1267 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1269 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1271 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1273 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1274 SUBTARGET_ATTRIBUTE_TABLE
,
1276 { NULL
, 0, 0, false, false, false, NULL
, false }
1279 #ifndef TARGET_PROFILE_KERNEL
1280 #define TARGET_PROFILE_KERNEL 0
1283 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1284 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1286 /* Initialize the GCC target structure. */
1287 #undef TARGET_ATTRIBUTE_TABLE
1288 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1289 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1290 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1291 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1292 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1294 #undef TARGET_ASM_ALIGNED_DI_OP
1295 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1297 /* Default unaligned ops are only provided for ELF. Find the ops needed
1298 for non-ELF systems. */
1299 #ifndef OBJECT_FORMAT_ELF
1301 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1303 #undef TARGET_ASM_UNALIGNED_HI_OP
1304 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1305 #undef TARGET_ASM_UNALIGNED_SI_OP
1306 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1307 #undef TARGET_ASM_UNALIGNED_DI_OP
1308 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1311 #undef TARGET_ASM_UNALIGNED_HI_OP
1312 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1313 #undef TARGET_ASM_UNALIGNED_SI_OP
1314 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1315 #undef TARGET_ASM_UNALIGNED_DI_OP
1316 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1317 #undef TARGET_ASM_ALIGNED_DI_OP
1318 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1322 /* This hook deals with fixups for relocatable code and DI-mode objects
1324 #undef TARGET_ASM_INTEGER
1325 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1327 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1328 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1329 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1332 #undef TARGET_SET_UP_BY_PROLOGUE
1333 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1335 #undef TARGET_HAVE_TLS
1336 #define TARGET_HAVE_TLS HAVE_AS_TLS
1338 #undef TARGET_CANNOT_FORCE_CONST_MEM
1339 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1341 #undef TARGET_DELEGITIMIZE_ADDRESS
1342 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1344 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1345 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1347 #undef TARGET_ASM_FUNCTION_PROLOGUE
1348 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1349 #undef TARGET_ASM_FUNCTION_EPILOGUE
1350 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1352 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1353 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1355 #undef TARGET_LEGITIMIZE_ADDRESS
1356 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1358 #undef TARGET_SCHED_VARIABLE_ISSUE
1359 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1361 #undef TARGET_SCHED_ISSUE_RATE
1362 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1363 #undef TARGET_SCHED_ADJUST_COST
1364 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1365 #undef TARGET_SCHED_ADJUST_PRIORITY
1366 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1367 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1368 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1369 #undef TARGET_SCHED_INIT
1370 #define TARGET_SCHED_INIT rs6000_sched_init
1371 #undef TARGET_SCHED_FINISH
1372 #define TARGET_SCHED_FINISH rs6000_sched_finish
1373 #undef TARGET_SCHED_REORDER
1374 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1375 #undef TARGET_SCHED_REORDER2
1376 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1378 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1379 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1381 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1382 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1384 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1385 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1386 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1387 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1388 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1389 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1390 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1391 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1393 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1394 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1395 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1396 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1397 rs6000_builtin_support_vector_misalignment
1398 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1399 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1400 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1401 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1402 rs6000_builtin_vectorization_cost
1403 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1404 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1405 rs6000_preferred_simd_mode
1406 #undef TARGET_VECTORIZE_INIT_COST
1407 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1408 #undef TARGET_VECTORIZE_ADD_STMT_COST
1409 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1410 #undef TARGET_VECTORIZE_FINISH_COST
1411 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1412 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1413 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1415 #undef TARGET_INIT_BUILTINS
1416 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1417 #undef TARGET_BUILTIN_DECL
1418 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1420 #undef TARGET_EXPAND_BUILTIN
1421 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1423 #undef TARGET_MANGLE_TYPE
1424 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1426 #undef TARGET_INIT_LIBFUNCS
1427 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1430 #undef TARGET_BINDS_LOCAL_P
1431 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1434 #undef TARGET_MS_BITFIELD_LAYOUT_P
1435 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1437 #undef TARGET_ASM_OUTPUT_MI_THUNK
1438 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1440 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1441 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1443 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1444 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1446 #undef TARGET_REGISTER_MOVE_COST
1447 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1448 #undef TARGET_MEMORY_MOVE_COST
1449 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1450 #undef TARGET_RTX_COSTS
1451 #define TARGET_RTX_COSTS rs6000_rtx_costs
1452 #undef TARGET_ADDRESS_COST
1453 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1455 #undef TARGET_DWARF_REGISTER_SPAN
1456 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1458 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1459 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1461 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1462 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1464 /* On rs6000, function arguments are promoted, as are function return
1466 #undef TARGET_PROMOTE_FUNCTION_MODE
1467 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1469 #undef TARGET_RETURN_IN_MEMORY
1470 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1472 #undef TARGET_RETURN_IN_MSB
1473 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1475 #undef TARGET_SETUP_INCOMING_VARARGS
1476 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1478 /* Always strict argument naming on rs6000. */
1479 #undef TARGET_STRICT_ARGUMENT_NAMING
1480 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1481 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1482 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1483 #undef TARGET_SPLIT_COMPLEX_ARG
1484 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1485 #undef TARGET_MUST_PASS_IN_STACK
1486 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1487 #undef TARGET_PASS_BY_REFERENCE
1488 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1489 #undef TARGET_ARG_PARTIAL_BYTES
1490 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1491 #undef TARGET_FUNCTION_ARG_ADVANCE
1492 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1493 #undef TARGET_FUNCTION_ARG
1494 #define TARGET_FUNCTION_ARG rs6000_function_arg
1495 #undef TARGET_FUNCTION_ARG_BOUNDARY
1496 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1498 #undef TARGET_BUILD_BUILTIN_VA_LIST
1499 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1501 #undef TARGET_EXPAND_BUILTIN_VA_START
1502 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1504 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1505 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1507 #undef TARGET_EH_RETURN_FILTER_MODE
1508 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1510 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1511 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1513 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1514 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1516 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1517 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1519 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1520 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1522 #undef TARGET_OPTION_OVERRIDE
1523 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1525 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1526 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1527 rs6000_builtin_vectorized_function
1530 #undef TARGET_STACK_PROTECT_FAIL
1531 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1534 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1535 The PowerPC architecture requires only weak consistency among
1536 processors--that is, memory accesses between processors need not be
1537 sequentially consistent and memory accesses among processors can occur
1538 in any order. The ability to order memory accesses weakly provides
1539 opportunities for more efficient use of the system bus. Unless a
1540 dependency exists, the 604e allows read operations to precede store
1542 #undef TARGET_RELAXED_ORDERING
1543 #define TARGET_RELAXED_ORDERING true
1546 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1547 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1550 /* Use a 32-bit anchor range. This leads to sequences like:
1552 addis tmp,anchor,high
1555 where tmp itself acts as an anchor, and can be shared between
1556 accesses to the same 64k page. */
1557 #undef TARGET_MIN_ANCHOR_OFFSET
1558 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1559 #undef TARGET_MAX_ANCHOR_OFFSET
1560 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1561 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1562 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1563 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1564 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1566 #undef TARGET_BUILTIN_RECIPROCAL
1567 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1569 #undef TARGET_EXPAND_TO_RTL_HOOK
1570 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1572 #undef TARGET_INSTANTIATE_DECLS
1573 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1575 #undef TARGET_SECONDARY_RELOAD
1576 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1578 #undef TARGET_LEGITIMATE_ADDRESS_P
1579 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1581 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1582 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1585 #define TARGET_LRA_P rs6000_lra_p
1587 #undef TARGET_CAN_ELIMINATE
1588 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1590 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1591 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1593 #undef TARGET_TRAMPOLINE_INIT
1594 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1596 #undef TARGET_FUNCTION_VALUE
1597 #define TARGET_FUNCTION_VALUE rs6000_function_value
1599 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1600 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1602 #undef TARGET_OPTION_SAVE
1603 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1605 #undef TARGET_OPTION_RESTORE
1606 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1608 #undef TARGET_OPTION_PRINT
1609 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1611 #undef TARGET_CAN_INLINE_P
1612 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1614 #undef TARGET_SET_CURRENT_FUNCTION
1615 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1617 #undef TARGET_LEGITIMATE_CONSTANT_P
1618 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1620 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1621 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1623 #undef TARGET_CAN_USE_DOLOOP_P
1624 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1627 /* Processor table. */
1630 const char *const name
; /* Canonical processor name. */
1631 const enum processor_type processor
; /* Processor type enum value. */
1632 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1635 static struct rs6000_ptt
const processor_target_table
[] =
1637 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1638 #include "rs6000-cpus.def"
1642 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1646 rs6000_cpu_name_lookup (const char *name
)
1652 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1653 if (! strcmp (name
, processor_target_table
[i
].name
))
1661 /* Return number of consecutive hard regs needed starting at reg REGNO
1662 to hold something of mode MODE.
1663 This is ordinarily the length in words of a value of mode MODE
1664 but can be less for certain modes in special long registers.
1666 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1667 scalar instructions. The upper 32 bits are only available to the
1670 POWER and PowerPC GPRs hold 32 bits worth;
1671 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1674 rs6000_hard_regno_nregs_internal (int regno
, enum machine_mode mode
)
1676 unsigned HOST_WIDE_INT reg_size
;
1678 /* TF/TD modes are special in that they always take 2 registers. */
1679 if (FP_REGNO_P (regno
))
1680 reg_size
= ((VECTOR_MEM_VSX_P (mode
) && mode
!= TDmode
&& mode
!= TFmode
)
1681 ? UNITS_PER_VSX_WORD
1682 : UNITS_PER_FP_WORD
);
1684 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1685 reg_size
= UNITS_PER_SPE_WORD
;
1687 else if (ALTIVEC_REGNO_P (regno
))
1688 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1690 /* The value returned for SCmode in the E500 double case is 2 for
1691 ABI compatibility; storing an SCmode value in a single register
1692 would require function_arg and rs6000_spe_function_arg to handle
1693 SCmode so as to pass the value correctly in a pair of
1695 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1696 && !DECIMAL_FLOAT_MODE_P (mode
))
1697 reg_size
= UNITS_PER_FP_WORD
;
1700 reg_size
= UNITS_PER_WORD
;
1702 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1705 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1708 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1710 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1712 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1713 register combinations, and use PTImode where we need to deal with quad
1714 word memory operations. Don't allow quad words in the argument or frame
1715 pointer registers, just registers 0..31. */
1716 if (mode
== PTImode
)
1717 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1718 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1719 && ((regno
& 1) == 0));
1721 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1722 implementations. Don't allow an item to be split between a FP register
1723 and an Altivec register. Allow TImode in all VSX registers if the user
1725 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
1726 && (VECTOR_MEM_VSX_P (mode
)
1727 || (TARGET_VSX_SCALAR_FLOAT
&& mode
== SFmode
)
1728 || (TARGET_VSX_SCALAR_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
1729 || (TARGET_VSX_TIMODE
&& mode
== TImode
)
1730 || (TARGET_VADDUQM
&& mode
== V1TImode
)))
1732 if (FP_REGNO_P (regno
))
1733 return FP_REGNO_P (last_regno
);
1735 if (ALTIVEC_REGNO_P (regno
))
1737 if (mode
== SFmode
&& !TARGET_UPPER_REGS_SF
)
1740 if ((mode
== DFmode
|| mode
== DImode
) && !TARGET_UPPER_REGS_DF
)
1743 return ALTIVEC_REGNO_P (last_regno
);
1747 /* The GPRs can hold any mode, but values bigger than one register
1748 cannot go past R31. */
1749 if (INT_REGNO_P (regno
))
1750 return INT_REGNO_P (last_regno
);
1752 /* The float registers (except for VSX vector modes) can only hold floating
1753 modes and DImode. */
1754 if (FP_REGNO_P (regno
))
1756 if (SCALAR_FLOAT_MODE_P (mode
)
1757 && (mode
!= TDmode
|| (regno
% 2) == 0)
1758 && FP_REGNO_P (last_regno
))
1761 if (GET_MODE_CLASS (mode
) == MODE_INT
1762 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1765 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1766 && PAIRED_VECTOR_MODE (mode
))
1772 /* The CR register can only hold CC modes. */
1773 if (CR_REGNO_P (regno
))
1774 return GET_MODE_CLASS (mode
) == MODE_CC
;
1776 if (CA_REGNO_P (regno
))
1777 return mode
== BImode
;
1779 /* AltiVec only in AldyVec registers. */
1780 if (ALTIVEC_REGNO_P (regno
))
1781 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
1782 || mode
== V1TImode
);
1784 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1785 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1788 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1789 and it must be able to fit within the register set. */
1791 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1794 /* Print interesting facts about registers. */
1796 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1800 for (r
= first_regno
; r
<= last_regno
; ++r
)
1802 const char *comma
= "";
1805 if (first_regno
== last_regno
)
1806 fprintf (stderr
, "%s:\t", reg_name
);
1808 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1811 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1812 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1816 fprintf (stderr
, ",\n\t");
1821 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1822 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1823 rs6000_hard_regno_nregs
[m
][r
]);
1825 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1830 if (call_used_regs
[r
])
1834 fprintf (stderr
, ",\n\t");
1839 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1847 fprintf (stderr
, ",\n\t");
1852 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1858 fprintf (stderr
, ",\n\t");
1862 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
1863 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
1868 fprintf (stderr
, ",\n\t");
1872 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1877 rs6000_debug_vector_unit (enum rs6000_vector v
)
1883 case VECTOR_NONE
: ret
= "none"; break;
1884 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
1885 case VECTOR_VSX
: ret
= "vsx"; break;
1886 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
1887 case VECTOR_PAIRED
: ret
= "paired"; break;
1888 case VECTOR_SPE
: ret
= "spe"; break;
1889 case VECTOR_OTHER
: ret
= "other"; break;
1890 default: ret
= "unknown"; break;
1896 /* Print the address masks in a human readble fashion. */
1898 rs6000_debug_print_mode (ssize_t m
)
1902 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
1903 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
1905 addr_mask_type mask
= reg_addr
[m
].addr_mask
[rc
];
1907 " %s: %c%c%c%c%c%c",
1908 reload_reg_map
[rc
].name
,
1909 (mask
& RELOAD_REG_VALID
) != 0 ? 'v' : ' ',
1910 (mask
& RELOAD_REG_MULTIPLE
) != 0 ? 'm' : ' ',
1911 (mask
& RELOAD_REG_INDEXED
) != 0 ? 'i' : ' ',
1912 (mask
& RELOAD_REG_OFFSET
) != 0 ? 'o' : ' ',
1913 (mask
& RELOAD_REG_PRE_INCDEC
) != 0 ? '+' : ' ',
1914 (mask
& RELOAD_REG_PRE_MODIFY
) != 0 ? '+' : ' ');
1917 if (rs6000_vector_unit
[m
] != VECTOR_NONE
1918 || rs6000_vector_mem
[m
] != VECTOR_NONE
1919 || (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
1920 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
))
1923 " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c",
1924 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
1925 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]),
1926 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
1927 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*');
1930 fputs ("\n", stderr
);
1933 #define DEBUG_FMT_ID "%-32s= "
1934 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
1935 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1936 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
1938 /* Print various interesting information with -mdebug=reg. */
1940 rs6000_debug_reg_global (void)
1942 static const char *const tf
[2] = { "false", "true" };
1943 const char *nl
= (const char *)0;
1946 char costly_num
[20];
1948 char flags_buffer
[40];
1949 const char *costly_str
;
1950 const char *nop_str
;
1951 const char *trace_str
;
1952 const char *abi_str
;
1953 const char *cmodel_str
;
1954 struct cl_target_option cl_opts
;
1956 /* Modes we want tieable information on. */
1957 static const enum machine_mode print_tieable_modes
[] = {
1993 /* Virtual regs we are interested in. */
1994 const static struct {
1995 int regno
; /* register number. */
1996 const char *name
; /* register name. */
1997 } virtual_regs
[] = {
1998 { STACK_POINTER_REGNUM
, "stack pointer:" },
1999 { TOC_REGNUM
, "toc: " },
2000 { STATIC_CHAIN_REGNUM
, "static chain: " },
2001 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
2002 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
2003 { ARG_POINTER_REGNUM
, "arg pointer: " },
2004 { FRAME_POINTER_REGNUM
, "frame pointer:" },
2005 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
2006 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
2007 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
2008 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
2009 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
2010 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
2011 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
2012 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
2013 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2016 fputs ("\nHard register information:\n", stderr
);
2017 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2018 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2019 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2022 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2023 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2024 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2025 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2026 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2027 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2028 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
2029 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
2031 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2032 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2033 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2037 "d reg_class = %s\n"
2038 "f reg_class = %s\n"
2039 "v reg_class = %s\n"
2040 "wa reg_class = %s\n"
2041 "wd reg_class = %s\n"
2042 "wf reg_class = %s\n"
2043 "wg reg_class = %s\n"
2044 "wl reg_class = %s\n"
2045 "wm reg_class = %s\n"
2046 "wr reg_class = %s\n"
2047 "ws reg_class = %s\n"
2048 "wt reg_class = %s\n"
2049 "wu reg_class = %s\n"
2050 "wv reg_class = %s\n"
2051 "ww reg_class = %s\n"
2052 "wx reg_class = %s\n"
2053 "wy reg_class = %s\n"
2054 "wz reg_class = %s\n"
2056 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2057 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2058 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2059 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2060 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2061 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2062 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2063 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2064 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2065 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2066 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2067 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2068 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2069 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2070 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2071 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2072 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2073 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]]);
2076 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2077 rs6000_debug_print_mode (m
);
2079 fputs ("\n", stderr
);
2081 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2083 enum machine_mode mode1
= print_tieable_modes
[m1
];
2084 bool first_time
= true;
2086 nl
= (const char *)0;
2087 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2089 enum machine_mode mode2
= print_tieable_modes
[m2
];
2090 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
2094 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2099 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2104 fputs ("\n", stderr
);
2110 if (rs6000_recip_control
)
2112 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2114 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2115 if (rs6000_recip_bits
[m
])
2118 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2120 (RS6000_RECIP_AUTO_RE_P (m
)
2122 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2123 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2125 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2128 fputs ("\n", stderr
);
2131 if (rs6000_cpu_index
>= 0)
2133 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2135 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2137 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2138 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2141 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2143 if (rs6000_tune_index
>= 0)
2145 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2147 = processor_target_table
[rs6000_tune_index
].target_enable
;
2149 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2150 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2153 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2155 cl_target_option_save (&cl_opts
, &global_options
);
2156 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2159 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2160 rs6000_isa_flags_explicit
);
2162 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2163 rs6000_builtin_mask
);
2165 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2167 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2168 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2170 switch (rs6000_sched_costly_dep
)
2172 case max_dep_latency
:
2173 costly_str
= "max_dep_latency";
2177 costly_str
= "no_dep_costly";
2180 case all_deps_costly
:
2181 costly_str
= "all_deps_costly";
2184 case true_store_to_load_dep_costly
:
2185 costly_str
= "true_store_to_load_dep_costly";
2188 case store_to_load_dep_costly
:
2189 costly_str
= "store_to_load_dep_costly";
2193 costly_str
= costly_num
;
2194 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2198 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2200 switch (rs6000_sched_insert_nops
)
2202 case sched_finish_regroup_exact
:
2203 nop_str
= "sched_finish_regroup_exact";
2206 case sched_finish_pad_groups
:
2207 nop_str
= "sched_finish_pad_groups";
2210 case sched_finish_none
:
2211 nop_str
= "sched_finish_none";
2216 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2220 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2222 switch (rs6000_sdata
)
2229 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2233 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2237 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2242 switch (rs6000_traceback
)
2244 case traceback_default
: trace_str
= "default"; break;
2245 case traceback_none
: trace_str
= "none"; break;
2246 case traceback_part
: trace_str
= "part"; break;
2247 case traceback_full
: trace_str
= "full"; break;
2248 default: trace_str
= "unknown"; break;
2251 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2253 switch (rs6000_current_cmodel
)
2255 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2256 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2257 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2258 default: cmodel_str
= "unknown"; break;
2261 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2263 switch (rs6000_current_abi
)
2265 case ABI_NONE
: abi_str
= "none"; break;
2266 case ABI_AIX
: abi_str
= "aix"; break;
2267 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2268 case ABI_V4
: abi_str
= "V4"; break;
2269 case ABI_DARWIN
: abi_str
= "darwin"; break;
2270 default: abi_str
= "unknown"; break;
2273 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2275 if (rs6000_altivec_abi
)
2276 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2279 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2281 if (rs6000_darwin64_abi
)
2282 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2284 if (rs6000_float_gprs
)
2285 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2287 fprintf (stderr
, DEBUG_FMT_S
, "fprs",
2288 (TARGET_FPRS
? "true" : "false"));
2290 fprintf (stderr
, DEBUG_FMT_S
, "single_float",
2291 (TARGET_SINGLE_FLOAT
? "true" : "false"));
2293 fprintf (stderr
, DEBUG_FMT_S
, "double_float",
2294 (TARGET_DOUBLE_FLOAT
? "true" : "false"));
2296 fprintf (stderr
, DEBUG_FMT_S
, "soft_float",
2297 (TARGET_SOFT_FLOAT
? "true" : "false"));
2299 fprintf (stderr
, DEBUG_FMT_S
, "e500_single",
2300 (TARGET_E500_SINGLE
? "true" : "false"));
2302 fprintf (stderr
, DEBUG_FMT_S
, "e500_double",
2303 (TARGET_E500_DOUBLE
? "true" : "false"));
2305 if (TARGET_LINK_STACK
)
2306 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2308 if (targetm
.lra_p ())
2309 fprintf (stderr
, DEBUG_FMT_S
, "lra", "true");
2311 if (TARGET_P8_FUSION
)
2312 fprintf (stderr
, DEBUG_FMT_S
, "p8 fusion",
2313 (TARGET_P8_FUSION_SIGN
) ? "zero+sign" : "zero");
2315 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2316 TARGET_SECURE_PLT
? "secure" : "bss");
2317 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2318 aix_struct_return
? "aix" : "sysv");
2319 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2320 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2321 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2322 tf
[!!rs6000_align_branch_targets
]);
2323 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2324 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2325 rs6000_long_double_type_size
);
2326 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2327 (int)rs6000_sched_restricted_insns_priority
);
2328 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2330 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2331 (int)RS6000_BUILTIN_COUNT
);
2334 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit scalar element",
2335 (int)VECTOR_ELEMENT_SCALAR_64BIT
);
2339 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2340 legitimate address support to figure out the appropriate addressing to
2344 rs6000_setup_reg_addr_masks (void)
2346 ssize_t rc
, reg
, m
, nregs
;
2347 addr_mask_type any_addr_mask
, addr_mask
;
2349 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2351 enum machine_mode m2
= (enum machine_mode
)m
;
2353 /* SDmode is special in that we want to access it only via REG+REG
2354 addressing on power7 and above, since we want to use the LFIWZX and
2355 STFIWZX instructions to load it. */
2356 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2359 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2362 reg
= reload_reg_map
[rc
].reg
;
2364 /* Can mode values go in the GPR/FPR/Altivec registers? */
2365 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2367 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2368 addr_mask
|= RELOAD_REG_VALID
;
2370 /* Indicate if the mode takes more than 1 physical register. If
2371 it takes a single register, indicate it can do REG+REG
2373 if (nregs
> 1 || m
== BLKmode
)
2374 addr_mask
|= RELOAD_REG_MULTIPLE
;
2376 addr_mask
|= RELOAD_REG_INDEXED
;
2378 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2379 addressing. Restrict addressing on SPE for 64-bit types
2380 because of the SUBREG hackery used to address 64-bit floats in
2381 '32-bit' GPRs. To simplify secondary reload, don't allow
2382 update forms on scalar floating point types that can go in the
2386 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2387 && GET_MODE_SIZE (m2
) <= 8
2388 && !VECTOR_MODE_P (m2
)
2389 && !COMPLEX_MODE_P (m2
)
2391 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (m2
) == 8)
2392 && !(m2
== DFmode
&& TARGET_UPPER_REGS_DF
)
2393 && !(m2
== SFmode
&& TARGET_UPPER_REGS_SF
))
2395 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2397 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2398 we don't allow PRE_MODIFY for some multi-register
2403 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2407 if (TARGET_POWERPC64
)
2408 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2414 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2420 /* GPR and FPR registers can do REG+OFFSET addressing, except
2421 possibly for SDmode. */
2422 if ((addr_mask
!= 0) && !indexed_only_p
2423 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
))
2424 addr_mask
|= RELOAD_REG_OFFSET
;
2426 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2427 any_addr_mask
|= addr_mask
;
2430 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2435 /* Initialize the various global tables that are based on register size. */
2437 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2443 /* Precalculate REGNO_REG_CLASS. */
2444 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2445 for (r
= 1; r
< 32; ++r
)
2446 rs6000_regno_regclass
[r
] = BASE_REGS
;
2448 for (r
= 32; r
< 64; ++r
)
2449 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2451 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2452 rs6000_regno_regclass
[r
] = NO_REGS
;
2454 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2455 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2457 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2458 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2459 rs6000_regno_regclass
[r
] = CR_REGS
;
2461 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2462 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2463 rs6000_regno_regclass
[CA_REGNO
] = CA_REGS
;
2464 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2465 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2466 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2467 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2468 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2469 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2470 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2471 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2472 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2474 /* Precalculate register class to simpler reload register class. We don't
2475 need all of the register classes that are combinations of different
2476 classes, just the simple ones that have constraint letters. */
2477 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2478 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2480 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2481 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2482 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2483 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2484 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2485 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2486 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2487 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2488 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2489 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2490 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2491 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2495 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2496 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2500 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2501 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2504 /* Precalculate the valid memory formats as well as the vector information,
2505 this must be set up before the rs6000_hard_regno_nregs_internal calls
2507 gcc_assert ((int)VECTOR_NONE
== 0);
2508 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
2509 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
2511 gcc_assert ((int)CODE_FOR_nothing
== 0);
2512 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
2514 gcc_assert ((int)NO_REGS
== 0);
2515 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
2517 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2518 believes it can use native alignment or still uses 128-bit alignment. */
2519 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2530 /* V2DF mode, VSX only. */
2533 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2534 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2535 rs6000_vector_align
[V2DFmode
] = align64
;
2538 /* V4SF mode, either VSX or Altivec. */
2541 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2542 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2543 rs6000_vector_align
[V4SFmode
] = align32
;
2545 else if (TARGET_ALTIVEC
)
2547 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2548 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2549 rs6000_vector_align
[V4SFmode
] = align32
;
2552 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2556 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2557 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2558 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2559 rs6000_vector_align
[V4SImode
] = align32
;
2560 rs6000_vector_align
[V8HImode
] = align32
;
2561 rs6000_vector_align
[V16QImode
] = align32
;
2565 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2566 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2567 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2571 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2572 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2573 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2577 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2578 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2581 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2582 rs6000_vector_unit
[V2DImode
]
2583 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2584 rs6000_vector_align
[V2DImode
] = align64
;
2586 rs6000_vector_mem
[V1TImode
] = VECTOR_VSX
;
2587 rs6000_vector_unit
[V1TImode
]
2588 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2589 rs6000_vector_align
[V1TImode
] = 128;
2592 /* DFmode, see if we want to use the VSX unit. */
2593 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2595 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2596 rs6000_vector_mem
[DFmode
]
2597 = (TARGET_UPPER_REGS_DF
? VECTOR_VSX
: VECTOR_NONE
);
2598 rs6000_vector_align
[DFmode
] = align64
;
2601 /* Allow TImode in VSX register and set the VSX memory macros. */
2602 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
2604 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
2605 rs6000_vector_align
[TImode
] = align64
;
2608 /* TODO add SPE and paired floating point vector support. */
2610 /* Register class constraints for the constraints that depend on compile
2611 switches. When the VSX code was added, different constraints were added
2612 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
2613 of the VSX registers are used. The register classes for scalar floating
2614 point types is set, based on whether we allow that type into the upper
2615 (Altivec) registers. GCC has register classes to target the Altivec
2616 registers for load/store operations, to select using a VSX memory
2617 operation instead of the traditional floating point operation. The
2620 d - Register class to use with traditional DFmode instructions.
2621 f - Register class to use with traditional SFmode instructions.
2622 v - Altivec register.
2623 wa - Any VSX register.
2624 wd - Preferred register class for V2DFmode.
2625 wf - Preferred register class for V4SFmode.
2626 wg - Float register for power6x move insns.
2627 wl - Float register if we can do 32-bit signed int loads.
2628 wm - VSX register for ISA 2.07 direct move operations.
2629 wr - GPR if 64-bit mode is permitted.
2630 ws - Register class to do ISA 2.06 DF operations.
2631 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
2632 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
2633 wt - VSX register for TImode in VSX registers.
2634 ww - Register class to do SF conversions in with VSX operations.
2635 wx - Float register if we can do 32-bit int stores.
2636 wy - Register class to do ISA 2.07 SF operations.
2637 wz - Float register if we can do 32-bit unsigned int loads. */
2639 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2640 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
;
2642 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2643 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
;
2647 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2648 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
;
2649 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
;
2651 if (TARGET_VSX_TIMODE
)
2652 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
;
2654 if (TARGET_UPPER_REGS_DF
)
2656 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
;
2657 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
2660 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = FLOAT_REGS
;
2663 /* Add conditional constraints based on various options, to allow us to
2664 collapse multiple insn patterns. */
2666 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2669 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
2672 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
;
2674 if (TARGET_DIRECT_MOVE
)
2675 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
2677 if (TARGET_POWERPC64
)
2678 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
2680 if (TARGET_P8_VECTOR
&& TARGET_UPPER_REGS_SF
)
2682 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
2683 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
2684 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
2686 else if (TARGET_P8_VECTOR
)
2688 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = FLOAT_REGS
;
2689 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2691 else if (TARGET_VSX
)
2692 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2695 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
;
2698 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
;
2700 /* Set up the reload helper and direct move functions. */
2701 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2705 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
2706 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
2707 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
2708 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
2709 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
2710 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
2711 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
2712 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
2713 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_di_store
;
2714 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_di_load
;
2715 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
2716 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
2717 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
2718 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
2719 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2721 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
2722 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
2723 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
2724 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
2726 if (TARGET_P8_VECTOR
)
2728 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
2729 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
2730 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
2731 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
2733 if (TARGET_VSX_TIMODE
)
2735 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
2736 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
2738 if (TARGET_DIRECT_MOVE
)
2740 if (TARGET_POWERPC64
)
2742 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
2743 reg_addr
[V1TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv1ti
;
2744 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
2745 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
2746 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
2747 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
2748 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
2749 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
2750 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
2752 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
2753 reg_addr
[V1TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv1ti
;
2754 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
2755 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
2756 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
2757 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
2758 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
2759 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
2760 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
2764 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
2765 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
2766 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
2772 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
2773 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
2774 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
2775 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
2776 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
2777 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
2778 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
2779 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
2780 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_si_store
;
2781 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_si_load
;
2782 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
2783 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
2784 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
2785 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
2786 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2788 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
2789 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
2790 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
2791 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
2793 if (TARGET_P8_VECTOR
)
2795 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
2796 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
2797 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
2798 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
2800 if (TARGET_VSX_TIMODE
)
2802 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
2803 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
2808 /* Precalculate HARD_REGNO_NREGS. */
2809 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2810 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2811 rs6000_hard_regno_nregs
[m
][r
]
2812 = rs6000_hard_regno_nregs_internal (r
, (enum machine_mode
)m
);
2814 /* Precalculate HARD_REGNO_MODE_OK. */
2815 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2816 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2817 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
)m
))
2818 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2820 /* Precalculate CLASS_MAX_NREGS sizes. */
2821 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2825 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2826 reg_size
= UNITS_PER_VSX_WORD
;
2828 else if (c
== ALTIVEC_REGS
)
2829 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2831 else if (c
== FLOAT_REGS
)
2832 reg_size
= UNITS_PER_FP_WORD
;
2835 reg_size
= UNITS_PER_WORD
;
2837 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2839 enum machine_mode m2
= (enum machine_mode
)m
;
2840 int reg_size2
= reg_size
;
2842 /* TFmode/TDmode always takes 2 registers, even in VSX. */
2843 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
)
2844 && (m
== TDmode
|| m
== TFmode
))
2845 reg_size2
= UNITS_PER_FP_WORD
;
2847 rs6000_class_max_nregs
[m
][c
]
2848 = (GET_MODE_SIZE (m2
) + reg_size2
- 1) / reg_size2
;
2852 if (TARGET_E500_DOUBLE
)
2853 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
2855 /* Calculate which modes to automatically generate code to use a the
2856 reciprocal divide and square root instructions. In the future, possibly
2857 automatically generate the instructions even if the user did not specify
2858 -mrecip. The older machines double precision reciprocal sqrt estimate is
2859 not accurate enough. */
2860 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
2862 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2864 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2865 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2866 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2867 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2868 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2870 if (TARGET_FRSQRTES
)
2871 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2873 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2874 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2875 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2876 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2877 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2879 if (rs6000_recip_control
)
2881 if (!flag_finite_math_only
)
2882 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2883 if (flag_trapping_math
)
2884 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2885 if (!flag_reciprocal_math
)
2886 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2887 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
2889 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
2890 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
2891 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2893 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
2894 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
2895 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2897 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
2898 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
2899 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2901 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
2902 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
2903 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2905 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
2906 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
2907 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2909 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
2910 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
2911 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2913 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
2914 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
2915 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2917 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
2918 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
2919 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2923 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2924 legitimate address support to figure out the appropriate addressing to
2926 rs6000_setup_reg_addr_masks ();
2928 if (global_init_p
|| TARGET_DEBUG_TARGET
)
2930 if (TARGET_DEBUG_REG
)
2931 rs6000_debug_reg_global ();
2933 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
2935 "SImode variable mult cost = %d\n"
2936 "SImode constant mult cost = %d\n"
2937 "SImode short constant mult cost = %d\n"
2938 "DImode multipliciation cost = %d\n"
2939 "SImode division cost = %d\n"
2940 "DImode division cost = %d\n"
2941 "Simple fp operation cost = %d\n"
2942 "DFmode multiplication cost = %d\n"
2943 "SFmode division cost = %d\n"
2944 "DFmode division cost = %d\n"
2945 "cache line size = %d\n"
2946 "l1 cache size = %d\n"
2947 "l2 cache size = %d\n"
2948 "simultaneous prefetches = %d\n"
2951 rs6000_cost
->mulsi_const
,
2952 rs6000_cost
->mulsi_const9
,
2960 rs6000_cost
->cache_line_size
,
2961 rs6000_cost
->l1_cache_size
,
2962 rs6000_cost
->l2_cache_size
,
2963 rs6000_cost
->simultaneous_prefetches
);
2968 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2971 darwin_rs6000_override_options (void)
2973 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2975 rs6000_altivec_abi
= 1;
2976 TARGET_ALTIVEC_VRSAVE
= 1;
2977 rs6000_current_abi
= ABI_DARWIN
;
2979 if (DEFAULT_ABI
== ABI_DARWIN
2981 darwin_one_byte_bool
= 1;
2983 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
2985 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
2986 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2990 rs6000_default_long_calls
= 1;
2991 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
2994 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2996 if (!flag_mkernel
&& !flag_apple_kext
2998 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
2999 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3001 /* Unless the user (not the configurer) has explicitly overridden
3002 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3003 G4 unless targeting the kernel. */
3006 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
3007 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
3008 && ! global_options_set
.x_rs6000_cpu_index
)
3010 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3015 /* If not otherwise specified by a target, make 'long double' equivalent to
3018 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3019 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3022 /* Return the builtin mask of the various options used that could affect which
3023 builtins were used. In the past we used target_flags, but we've run out of
3024 bits, and some options like SPE and PAIRED are no longer in
3028 rs6000_builtin_mask_calculate (void)
3030 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
3031 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
3032 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
3033 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
3034 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
3035 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
3036 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
3037 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
3038 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
3039 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
3040 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
3041 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
3042 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0)
3043 | ((TARGET_DFP
) ? RS6000_BTM_DFP
: 0)
3044 | ((TARGET_HARD_FLOAT
) ? RS6000_BTM_HARD_FLOAT
: 0)
3045 | ((TARGET_LONG_DOUBLE_128
) ? RS6000_BTM_LDBL128
: 0));
3048 /* Override command line options. Mostly we process the processor type and
3049 sometimes adjust other TARGET_ options. */
3052 rs6000_option_override_internal (bool global_init_p
)
3055 bool have_cpu
= false;
3057 /* The default cpu requested at configure time, if any. */
3058 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
3060 HOST_WIDE_INT set_masks
;
3063 struct cl_target_option
*main_target_opt
3064 = ((global_init_p
|| target_option_default_node
== NULL
)
3065 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3067 /* Remember the explicit arguments. */
3069 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3071 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3072 library functions, so warn about it. The flag may be useful for
3073 performance studies from time to time though, so don't disable it
3075 if (global_options_set
.x_rs6000_alignment_flags
3076 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3077 && DEFAULT_ABI
== ABI_DARWIN
3079 warning (0, "-malign-power is not supported for 64-bit Darwin;"
3080 " it is incompatible with the installed C and C++ libraries");
3082 /* Numerous experiment shows that IRA based loop pressure
3083 calculation works better for RTL loop invariant motion on targets
3084 with enough (>= 32) registers. It is an expensive optimization.
3085 So it is on only for peak performance. */
3086 if (optimize
>= 3 && global_init_p
3087 && !global_options_set
.x_flag_ira_loop_pressure
)
3088 flag_ira_loop_pressure
= 1;
3090 /* Set the pointer size. */
3093 rs6000_pmode
= (int)DImode
;
3094 rs6000_pointer_size
= 64;
3098 rs6000_pmode
= (int)SImode
;
3099 rs6000_pointer_size
= 32;
3102 /* Some OSs don't support saving the high part of 64-bit registers on context
3103 switch. Other OSs don't support saving Altivec registers. On those OSs,
3104 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3105 if the user wants either, the user must explicitly specify them and we
3106 won't interfere with the user's specification. */
3108 set_masks
= POWERPC_MASKS
;
3109 #ifdef OS_MISSING_POWERPC64
3110 if (OS_MISSING_POWERPC64
)
3111 set_masks
&= ~OPTION_MASK_POWERPC64
;
3113 #ifdef OS_MISSING_ALTIVEC
3114 if (OS_MISSING_ALTIVEC
)
3115 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
3118 /* Don't override by the processor default if given explicitly. */
3119 set_masks
&= ~rs6000_isa_flags_explicit
;
3121 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3122 the cpu in a target attribute or pragma, but did not specify a tuning
3123 option, use the cpu for the tuning option rather than the option specified
3124 with -mtune on the command line. Process a '--with-cpu' configuration
3125 request as an implicit --cpu. */
3126 if (rs6000_cpu_index
>= 0)
3128 cpu_index
= rs6000_cpu_index
;
3131 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3133 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3136 else if (implicit_cpu
)
3138 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
3143 const char *default_cpu
= (TARGET_POWERPC64
? "powerpc64" : "powerpc");
3144 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3148 gcc_assert (cpu_index
>= 0);
3150 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3151 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3152 with those from the cpu, except for options that were explicitly set. If
3153 we don't have a cpu, do not override the target bits set in
3157 rs6000_isa_flags
&= ~set_masks
;
3158 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3162 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3163 & ~rs6000_isa_flags_explicit
);
3165 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3166 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3167 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3168 to using rs6000_isa_flags, we need to do the initialization here. */
3170 rs6000_isa_flags
|= (TARGET_DEFAULT
& ~rs6000_isa_flags_explicit
);
3172 if (rs6000_tune_index
>= 0)
3173 tune_index
= rs6000_tune_index
;
3175 rs6000_tune_index
= tune_index
= cpu_index
;
3179 enum processor_type tune_proc
3180 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3183 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3184 if (processor_target_table
[i
].processor
== tune_proc
)
3186 rs6000_tune_index
= tune_index
= i
;
3191 gcc_assert (tune_index
>= 0);
3192 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
3194 /* Pick defaults for SPE related control flags. Do this early to make sure
3195 that the TARGET_ macros are representative ASAP. */
3197 int spe_capable_cpu
=
3198 (rs6000_cpu
== PROCESSOR_PPC8540
3199 || rs6000_cpu
== PROCESSOR_PPC8548
);
3201 if (!global_options_set
.x_rs6000_spe_abi
)
3202 rs6000_spe_abi
= spe_capable_cpu
;
3204 if (!global_options_set
.x_rs6000_spe
)
3205 rs6000_spe
= spe_capable_cpu
;
3207 if (!global_options_set
.x_rs6000_float_gprs
)
3209 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
3210 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
3214 if (global_options_set
.x_rs6000_spe_abi
3217 error ("not configured for SPE ABI");
3219 if (global_options_set
.x_rs6000_spe
3222 error ("not configured for SPE instruction set");
3224 if (main_target_opt
!= NULL
3225 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
3226 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
3227 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
3228 error ("target attribute or pragma changes SPE ABI");
3230 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3231 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3232 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3235 error ("AltiVec not supported in this target");
3237 error ("SPE not supported in this target");
3239 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
3242 error ("SPE not supported in this target");
3245 /* Disable Cell microcode if we are optimizing for the Cell
3246 and not optimizing for size. */
3247 if (rs6000_gen_cell_microcode
== -1)
3248 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
3251 /* If we are optimizing big endian systems for space and it's OK to
3252 use instructions that would be microcoded on the Cell, use the
3253 load/store multiple and string instructions. */
3254 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
3255 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
3256 | OPTION_MASK_STRING
);
3258 /* Don't allow -mmultiple or -mstring on little endian systems
3259 unless the cpu is a 750, because the hardware doesn't support the
3260 instructions used in little endian mode, and causes an alignment
3261 trap. The 750 does not cause an alignment trap (except when the
3262 target is unaligned). */
3264 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
3266 if (TARGET_MULTIPLE
)
3268 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3269 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3270 warning (0, "-mmultiple is not supported on little endian systems");
3275 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3276 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
3277 warning (0, "-mstring is not supported on little endian systems");
3281 /* If little-endian, default to -mstrict-align on older processors.
3282 Testing for htm matches power8 and later. */
3283 if (!BYTES_BIG_ENDIAN
3284 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
3285 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
3287 /* -maltivec={le,be} implies -maltivec. */
3288 if (rs6000_altivec_element_order
!= 0)
3289 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3291 /* Disallow -maltivec=le in big endian mode for now. This is not
3292 known to be useful for anyone. */
3293 if (BYTES_BIG_ENDIAN
&& rs6000_altivec_element_order
== 1)
3295 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
3296 rs6000_altivec_element_order
= 0;
3299 /* Add some warnings for VSX. */
3302 const char *msg
= NULL
;
3303 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
3304 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
3306 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3307 msg
= N_("-mvsx requires hardware floating point");
3310 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3311 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3314 else if (TARGET_PAIRED_FLOAT
)
3315 msg
= N_("-mvsx and -mpaired are incompatible");
3316 else if (TARGET_AVOID_XFORM
> 0)
3317 msg
= N_("-mvsx needs indexed addressing");
3318 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
3319 & OPTION_MASK_ALTIVEC
))
3321 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3322 msg
= N_("-mvsx and -mno-altivec are incompatible");
3324 msg
= N_("-mno-altivec disables vsx");
3330 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3331 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3335 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3336 the -mcpu setting to enable options that conflict. */
3337 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
3338 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
3339 | OPTION_MASK_ALTIVEC
3340 | OPTION_MASK_VSX
)) != 0)
3341 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
3342 | OPTION_MASK_DIRECT_MOVE
)
3343 & ~rs6000_isa_flags_explicit
);
3345 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3346 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
3348 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3349 unless the user explicitly used the -mno-<option> to disable the code. */
3350 if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
3351 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3352 else if (TARGET_VSX
)
3353 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3354 else if (TARGET_POPCNTD
)
3355 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3356 else if (TARGET_DFP
)
3357 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3358 else if (TARGET_CMPB
)
3359 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3360 else if (TARGET_FPRND
)
3361 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
3362 else if (TARGET_POPCNTB
)
3363 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
3364 else if (TARGET_ALTIVEC
)
3365 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
3367 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
3369 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
3370 error ("-mcrypto requires -maltivec");
3371 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
3374 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
3376 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
3377 error ("-mdirect-move requires -mvsx");
3378 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
3381 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
3383 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3384 error ("-mpower8-vector requires -maltivec");
3385 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3388 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
3390 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3391 error ("-mpower8-vector requires -mvsx");
3392 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3395 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
3397 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
3398 error ("-mvsx-timode requires -mvsx");
3399 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
3402 if (TARGET_DFP
&& !TARGET_HARD_FLOAT
)
3404 if (rs6000_isa_flags_explicit
& OPTION_MASK_DFP
)
3405 error ("-mhard-dfp requires -mhard-float");
3406 rs6000_isa_flags
&= ~OPTION_MASK_DFP
;
3409 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
3410 silently turn off quad memory mode. */
3411 if ((TARGET_QUAD_MEMORY
|| TARGET_QUAD_MEMORY_ATOMIC
) && !TARGET_POWERPC64
)
3413 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3414 warning (0, N_("-mquad-memory requires 64-bit mode"));
3416 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) != 0)
3417 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
3419 rs6000_isa_flags
&= ~(OPTION_MASK_QUAD_MEMORY
3420 | OPTION_MASK_QUAD_MEMORY_ATOMIC
);
3423 /* Non-atomic quad memory load/store are disabled for little endian, since
3424 the words are reversed, but atomic operations can still be done by
3425 swapping the words. */
3426 if (TARGET_QUAD_MEMORY
&& !WORDS_BIG_ENDIAN
)
3428 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3429 warning (0, N_("-mquad-memory is not available in little endian mode"));
3431 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
3434 /* Assume if the user asked for normal quad memory instructions, they want
3435 the atomic versions as well, unless they explicity told us not to use quad
3436 word atomic instructions. */
3437 if (TARGET_QUAD_MEMORY
3438 && !TARGET_QUAD_MEMORY_ATOMIC
3439 && ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) == 0))
3440 rs6000_isa_flags
|= OPTION_MASK_QUAD_MEMORY_ATOMIC
;
3442 /* Enable power8 fusion if we are tuning for power8, even if we aren't
3443 generating power8 instructions. */
3444 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
3445 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
3446 & OPTION_MASK_P8_FUSION
);
3448 /* Power8 does not fuse sign extended loads with the addis. If we are
3449 optimizing at high levels for speed, convert a sign extended load into a
3450 zero extending load, and an explicit sign extension. */
3451 if (TARGET_P8_FUSION
3452 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
3453 && optimize_function_for_speed_p (cfun
)
3455 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
3457 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3458 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
3460 /* E500mc does "better" if we inline more aggressively. Respect the
3461 user's opinion, though. */
3462 if (rs6000_block_move_inline_limit
== 0
3463 && (rs6000_cpu
== PROCESSOR_PPCE500MC
3464 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3465 || rs6000_cpu
== PROCESSOR_PPCE5500
3466 || rs6000_cpu
== PROCESSOR_PPCE6500
))
3467 rs6000_block_move_inline_limit
= 128;
3469 /* store_one_arg depends on expand_block_move to handle at least the
3470 size of reg_parm_stack_space. */
3471 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
3472 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
3476 /* If the appropriate debug option is enabled, replace the target hooks
3477 with debug versions that call the real version and then prints
3478 debugging information. */
3479 if (TARGET_DEBUG_COST
)
3481 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
3482 targetm
.address_cost
= rs6000_debug_address_cost
;
3483 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
3486 if (TARGET_DEBUG_ADDR
)
3488 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
3489 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
3490 rs6000_secondary_reload_class_ptr
3491 = rs6000_debug_secondary_reload_class
;
3492 rs6000_secondary_memory_needed_ptr
3493 = rs6000_debug_secondary_memory_needed
;
3494 rs6000_cannot_change_mode_class_ptr
3495 = rs6000_debug_cannot_change_mode_class
;
3496 rs6000_preferred_reload_class_ptr
3497 = rs6000_debug_preferred_reload_class
;
3498 rs6000_legitimize_reload_address_ptr
3499 = rs6000_debug_legitimize_reload_address
;
3500 rs6000_mode_dependent_address_ptr
3501 = rs6000_debug_mode_dependent_address
;
3504 if (rs6000_veclibabi_name
)
3506 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
3507 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
3510 error ("unknown vectorization library ABI type (%s) for "
3511 "-mveclibabi= switch", rs6000_veclibabi_name
);
3517 if (!global_options_set
.x_rs6000_long_double_type_size
)
3519 if (main_target_opt
!= NULL
3520 && (main_target_opt
->x_rs6000_long_double_type_size
3521 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
3522 error ("target attribute or pragma changes long double size");
3524 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
3527 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
3528 if (!global_options_set
.x_rs6000_ieeequad
)
3529 rs6000_ieeequad
= 1;
3532 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
3533 target attribute or pragma which automatically enables both options,
3534 unless the altivec ABI was set. This is set by default for 64-bit, but
3536 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3537 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
3538 & ~rs6000_isa_flags_explicit
);
3540 /* Enable Altivec ABI for AIX -maltivec. */
3541 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
3543 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3544 error ("target attribute or pragma changes AltiVec ABI");
3546 rs6000_altivec_abi
= 1;
3549 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
3550 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
3551 be explicitly overridden in either case. */
3554 if (!global_options_set
.x_rs6000_altivec_abi
3555 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
3557 if (main_target_opt
!= NULL
&&
3558 !main_target_opt
->x_rs6000_altivec_abi
)
3559 error ("target attribute or pragma changes AltiVec ABI");
3561 rs6000_altivec_abi
= 1;
3565 /* Set the Darwin64 ABI as default for 64-bit Darwin.
3566 So far, the only darwin64 targets are also MACH-O. */
3568 && DEFAULT_ABI
== ABI_DARWIN
3571 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
3572 error ("target attribute or pragma changes darwin64 ABI");
3575 rs6000_darwin64_abi
= 1;
3576 /* Default to natural alignment, for better performance. */
3577 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
3581 /* Place FP constants in the constant pool instead of TOC
3582 if section anchors enabled. */
3583 if (flag_section_anchors
3584 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
3585 TARGET_NO_FP_IN_TOC
= 1;
3587 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3588 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
3590 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3591 SUBTARGET_OVERRIDE_OPTIONS
;
3593 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3594 SUBSUBTARGET_OVERRIDE_OPTIONS
;
3596 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
3597 SUB3TARGET_OVERRIDE_OPTIONS
;
3600 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3601 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
3603 /* For the E500 family of cores, reset the single/double FP flags to let us
3604 check that they remain constant across attributes or pragmas. Also,
3605 clear a possible request for string instructions, not supported and which
3606 we might have silently queried above for -Os.
3608 For other families, clear ISEL in case it was set implicitly.
3613 case PROCESSOR_PPC8540
:
3614 case PROCESSOR_PPC8548
:
3615 case PROCESSOR_PPCE500MC
:
3616 case PROCESSOR_PPCE500MC64
:
3617 case PROCESSOR_PPCE5500
:
3618 case PROCESSOR_PPCE6500
:
3620 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
3621 rs6000_double_float
= TARGET_E500_DOUBLE
;
3623 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3629 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
3630 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
3635 if (main_target_opt
)
3637 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
3638 error ("target attribute or pragma changes single precision floating "
3640 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
3641 error ("target attribute or pragma changes double precision floating "
3645 /* Detect invalid option combinations with E500. */
3648 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
3649 && rs6000_cpu
!= PROCESSOR_POWER5
3650 && rs6000_cpu
!= PROCESSOR_POWER6
3651 && rs6000_cpu
!= PROCESSOR_POWER7
3652 && rs6000_cpu
!= PROCESSOR_POWER8
3653 && rs6000_cpu
!= PROCESSOR_PPCA2
3654 && rs6000_cpu
!= PROCESSOR_CELL
3655 && rs6000_cpu
!= PROCESSOR_PPC476
);
3656 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
3657 || rs6000_cpu
== PROCESSOR_POWER5
3658 || rs6000_cpu
== PROCESSOR_POWER7
3659 || rs6000_cpu
== PROCESSOR_POWER8
);
3660 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
3661 || rs6000_cpu
== PROCESSOR_POWER5
3662 || rs6000_cpu
== PROCESSOR_POWER6
3663 || rs6000_cpu
== PROCESSOR_POWER7
3664 || rs6000_cpu
== PROCESSOR_POWER8
3665 || rs6000_cpu
== PROCESSOR_PPCE500MC
3666 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3667 || rs6000_cpu
== PROCESSOR_PPCE5500
3668 || rs6000_cpu
== PROCESSOR_PPCE6500
);
3670 /* Allow debug switches to override the above settings. These are set to -1
3671 in rs6000.opt to indicate the user hasn't directly set the switch. */
3672 if (TARGET_ALWAYS_HINT
>= 0)
3673 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
3675 if (TARGET_SCHED_GROUPS
>= 0)
3676 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
3678 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
3679 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
3681 rs6000_sched_restricted_insns_priority
3682 = (rs6000_sched_groups
? 1 : 0);
3684 /* Handle -msched-costly-dep option. */
3685 rs6000_sched_costly_dep
3686 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
3688 if (rs6000_sched_costly_dep_str
)
3690 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
3691 rs6000_sched_costly_dep
= no_dep_costly
;
3692 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
3693 rs6000_sched_costly_dep
= all_deps_costly
;
3694 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
3695 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
3696 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
3697 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
3699 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
3700 atoi (rs6000_sched_costly_dep_str
));
3703 /* Handle -minsert-sched-nops option. */
3704 rs6000_sched_insert_nops
3705 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
3707 if (rs6000_sched_insert_nops_str
)
3709 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
3710 rs6000_sched_insert_nops
= sched_finish_none
;
3711 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
3712 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
3713 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
3714 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
3716 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
3717 atoi (rs6000_sched_insert_nops_str
));
3722 #ifdef TARGET_REGNAMES
3723 /* If the user desires alternate register names, copy in the
3724 alternate names now. */
3725 if (TARGET_REGNAMES
)
3726 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
3729 /* Set aix_struct_return last, after the ABI is determined.
3730 If -maix-struct-return or -msvr4-struct-return was explicitly
3731 used, don't override with the ABI default. */
3732 if (!global_options_set
.x_aix_struct_return
)
3733 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
3736 /* IBM XL compiler defaults to unsigned bitfields. */
3737 if (TARGET_XL_COMPAT
)
3738 flag_signed_bitfields
= 0;
3741 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
3742 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
3745 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
3747 /* We can only guarantee the availability of DI pseudo-ops when
3748 assembling for 64-bit targets. */
3751 targetm
.asm_out
.aligned_op
.di
= NULL
;
3752 targetm
.asm_out
.unaligned_op
.di
= NULL
;
3756 /* Set branch target alignment, if not optimizing for size. */
3759 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3760 aligned 8byte to avoid misprediction by the branch predictor. */
3761 if (rs6000_cpu
== PROCESSOR_TITAN
3762 || rs6000_cpu
== PROCESSOR_CELL
)
3764 if (align_functions
<= 0)
3765 align_functions
= 8;
3766 if (align_jumps
<= 0)
3768 if (align_loops
<= 0)
3771 if (rs6000_align_branch_targets
)
3773 if (align_functions
<= 0)
3774 align_functions
= 16;
3775 if (align_jumps
<= 0)
3777 if (align_loops
<= 0)
3779 can_override_loop_align
= 1;
3783 if (align_jumps_max_skip
<= 0)
3784 align_jumps_max_skip
= 15;
3785 if (align_loops_max_skip
<= 0)
3786 align_loops_max_skip
= 15;
3789 /* Arrange to save and restore machine status around nested functions. */
3790 init_machine_status
= rs6000_init_machine_status
;
3792 /* We should always be splitting complex arguments, but we can't break
3793 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3794 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
3795 targetm
.calls
.split_complex_arg
= NULL
;
3798 /* Initialize rs6000_cost with the appropriate target costs. */
3800 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
3804 case PROCESSOR_RS64A
:
3805 rs6000_cost
= &rs64a_cost
;
3808 case PROCESSOR_MPCCORE
:
3809 rs6000_cost
= &mpccore_cost
;
3812 case PROCESSOR_PPC403
:
3813 rs6000_cost
= &ppc403_cost
;
3816 case PROCESSOR_PPC405
:
3817 rs6000_cost
= &ppc405_cost
;
3820 case PROCESSOR_PPC440
:
3821 rs6000_cost
= &ppc440_cost
;
3824 case PROCESSOR_PPC476
:
3825 rs6000_cost
= &ppc476_cost
;
3828 case PROCESSOR_PPC601
:
3829 rs6000_cost
= &ppc601_cost
;
3832 case PROCESSOR_PPC603
:
3833 rs6000_cost
= &ppc603_cost
;
3836 case PROCESSOR_PPC604
:
3837 rs6000_cost
= &ppc604_cost
;
3840 case PROCESSOR_PPC604e
:
3841 rs6000_cost
= &ppc604e_cost
;
3844 case PROCESSOR_PPC620
:
3845 rs6000_cost
= &ppc620_cost
;
3848 case PROCESSOR_PPC630
:
3849 rs6000_cost
= &ppc630_cost
;
3852 case PROCESSOR_CELL
:
3853 rs6000_cost
= &ppccell_cost
;
3856 case PROCESSOR_PPC750
:
3857 case PROCESSOR_PPC7400
:
3858 rs6000_cost
= &ppc750_cost
;
3861 case PROCESSOR_PPC7450
:
3862 rs6000_cost
= &ppc7450_cost
;
3865 case PROCESSOR_PPC8540
:
3866 case PROCESSOR_PPC8548
:
3867 rs6000_cost
= &ppc8540_cost
;
3870 case PROCESSOR_PPCE300C2
:
3871 case PROCESSOR_PPCE300C3
:
3872 rs6000_cost
= &ppce300c2c3_cost
;
3875 case PROCESSOR_PPCE500MC
:
3876 rs6000_cost
= &ppce500mc_cost
;
3879 case PROCESSOR_PPCE500MC64
:
3880 rs6000_cost
= &ppce500mc64_cost
;
3883 case PROCESSOR_PPCE5500
:
3884 rs6000_cost
= &ppce5500_cost
;
3887 case PROCESSOR_PPCE6500
:
3888 rs6000_cost
= &ppce6500_cost
;
3891 case PROCESSOR_TITAN
:
3892 rs6000_cost
= &titan_cost
;
3895 case PROCESSOR_POWER4
:
3896 case PROCESSOR_POWER5
:
3897 rs6000_cost
= &power4_cost
;
3900 case PROCESSOR_POWER6
:
3901 rs6000_cost
= &power6_cost
;
3904 case PROCESSOR_POWER7
:
3905 rs6000_cost
= &power7_cost
;
3908 case PROCESSOR_POWER8
:
3909 rs6000_cost
= &power8_cost
;
3912 case PROCESSOR_PPCA2
:
3913 rs6000_cost
= &ppca2_cost
;
3922 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
3923 rs6000_cost
->simultaneous_prefetches
,
3924 global_options
.x_param_values
,
3925 global_options_set
.x_param_values
);
3926 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
3927 global_options
.x_param_values
,
3928 global_options_set
.x_param_values
);
3929 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
3930 rs6000_cost
->cache_line_size
,
3931 global_options
.x_param_values
,
3932 global_options_set
.x_param_values
);
3933 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
3934 global_options
.x_param_values
,
3935 global_options_set
.x_param_values
);
3937 /* Increase loop peeling limits based on performance analysis. */
3938 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
3939 global_options
.x_param_values
,
3940 global_options_set
.x_param_values
);
3941 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
3942 global_options
.x_param_values
,
3943 global_options_set
.x_param_values
);
3945 /* If using typedef char *va_list, signal that
3946 __builtin_va_start (&ap, 0) can be optimized to
3947 ap = __builtin_next_arg (0). */
3948 if (DEFAULT_ABI
!= ABI_V4
)
3949 targetm
.expand_builtin_va_start
= NULL
;
3952 /* Set up single/double float flags.
3953 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3954 then set both flags. */
3955 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
3956 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
3957 rs6000_single_float
= rs6000_double_float
= 1;
3959 /* If not explicitly specified via option, decide whether to generate indexed
3960 load/store instructions. */
3961 if (TARGET_AVOID_XFORM
== -1)
3962 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3963 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3964 need indexed accesses and the type used is the scalar type of the element
3965 being loaded or stored. */
3966 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
3967 && !TARGET_ALTIVEC
);
3969 /* Set the -mrecip options. */
3970 if (rs6000_recip_name
)
3972 char *p
= ASTRDUP (rs6000_recip_name
);
3974 unsigned int mask
, i
;
3977 while ((q
= strtok (p
, ",")) != NULL
)
3988 if (!strcmp (q
, "default"))
3989 mask
= ((TARGET_RECIP_PRECISION
)
3990 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
3993 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
3994 if (!strcmp (q
, recip_options
[i
].string
))
3996 mask
= recip_options
[i
].mask
;
4000 if (i
== ARRAY_SIZE (recip_options
))
4002 error ("unknown option for -mrecip=%s", q
);
4010 rs6000_recip_control
&= ~mask
;
4012 rs6000_recip_control
|= mask
;
4016 /* Set the builtin mask of the various options used that could affect which
4017 builtins were used. In the past we used target_flags, but we've run out
4018 of bits, and some options like SPE and PAIRED are no longer in
4020 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
4021 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
4024 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX
", ",
4025 rs6000_builtin_mask
);
4026 rs6000_print_builtin_options (stderr
, 0, NULL
, rs6000_builtin_mask
);
4029 /* Initialize all of the registers. */
4030 rs6000_init_hard_regno_mode_ok (global_init_p
);
4032 /* Save the initial options in case the user does function specific options */
4034 target_option_default_node
= target_option_current_node
4035 = build_target_option_node (&global_options
);
4037 /* If not explicitly specified via option, decide whether to generate the
4038 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4039 if (TARGET_LINK_STACK
== -1)
4040 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
4045 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4046 define the target cpu type. */
4049 rs6000_option_override (void)
4051 (void) rs6000_option_override_internal (true);
4055 /* Implement targetm.vectorize.builtin_mask_for_load. */
4057 rs6000_builtin_mask_for_load (void)
4059 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4060 return altivec_builtin_mask_for_load
;
4065 /* Implement LOOP_ALIGN. */
4067 rs6000_loop_align (rtx label
)
4072 /* Don't override loop alignment if -falign-loops was specified. */
4073 if (!can_override_loop_align
)
4074 return align_loops_log
;
4076 bb
= BLOCK_FOR_INSN (label
);
4077 ninsns
= num_loop_insns(bb
->loop_father
);
4079 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4080 if (ninsns
> 4 && ninsns
<= 8
4081 && (rs6000_cpu
== PROCESSOR_POWER4
4082 || rs6000_cpu
== PROCESSOR_POWER5
4083 || rs6000_cpu
== PROCESSOR_POWER6
4084 || rs6000_cpu
== PROCESSOR_POWER7
4085 || rs6000_cpu
== PROCESSOR_POWER8
))
4088 return align_loops_log
;
4091 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
4093 rs6000_loop_align_max_skip (rtx label
)
4095 return (1 << rs6000_loop_align (label
)) - 1;
4098 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4099 after applying N number of iterations. This routine does not determine
4100 how may iterations are required to reach desired alignment. */
4103 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
4110 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
4113 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
4123 /* Assuming that all other types are naturally aligned. CHECKME! */
4128 /* Return true if the vector misalignment factor is supported by the
4131 rs6000_builtin_support_vector_misalignment (enum machine_mode mode
,
4138 /* Return if movmisalign pattern is not supported for this mode. */
4139 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
4142 if (misalignment
== -1)
4144 /* Misalignment factor is unknown at compile time but we know
4145 it's word aligned. */
4146 if (rs6000_vector_alignment_reachable (type
, is_packed
))
4148 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
4150 if (element_size
== 64 || element_size
== 32)
4157 /* VSX supports word-aligned vector. */
4158 if (misalignment
% 4 == 0)
4164 /* Implement targetm.vectorize.builtin_vectorization_cost. */
4166 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
4167 tree vectype
, int misalign
)
4172 switch (type_of_cost
)
4182 case cond_branch_not_taken
:
4191 case vec_promote_demote
:
4197 case cond_branch_taken
:
4200 case unaligned_load
:
4201 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4203 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4205 /* Double word aligned. */
4213 /* Double word aligned. */
4217 /* Unknown misalignment. */
4230 /* Misaligned loads are not supported. */
4235 case unaligned_store
:
4236 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4238 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4240 /* Double word aligned. */
4248 /* Double word aligned. */
4252 /* Unknown misalignment. */
4265 /* Misaligned stores are not supported. */
4271 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4272 elem_type
= TREE_TYPE (vectype
);
4273 /* 32-bit vectors loaded into registers are stored as double
4274 precision, so we need n/2 converts in addition to the usual
4275 n/2 merges to construct a vector of short floats from them. */
4276 if (SCALAR_FLOAT_TYPE_P (elem_type
)
4277 && TYPE_PRECISION (elem_type
) == 32)
4278 return elements
+ 1;
4280 return elements
/ 2 + 1;
4287 /* Implement targetm.vectorize.preferred_simd_mode. */
4289 static enum machine_mode
4290 rs6000_preferred_simd_mode (enum machine_mode mode
)
4299 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4325 if (TARGET_PAIRED_FLOAT
4331 typedef struct _rs6000_cost_data
4333 struct loop
*loop_info
;
4337 /* Test for likely overcommitment of vector hardware resources. If a
4338 loop iteration is relatively large, and too large a percentage of
4339 instructions in the loop are vectorized, the cost model may not
4340 adequately reflect delays from unavailable vector resources.
4341 Penalize the loop body cost for this case. */
4344 rs6000_density_test (rs6000_cost_data
*data
)
4346 const int DENSITY_PCT_THRESHOLD
= 85;
4347 const int DENSITY_SIZE_THRESHOLD
= 70;
4348 const int DENSITY_PENALTY
= 10;
4349 struct loop
*loop
= data
->loop_info
;
4350 basic_block
*bbs
= get_loop_body (loop
);
4351 int nbbs
= loop
->num_nodes
;
4352 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
4355 for (i
= 0; i
< nbbs
; i
++)
4357 basic_block bb
= bbs
[i
];
4358 gimple_stmt_iterator gsi
;
4360 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
4362 gimple stmt
= gsi_stmt (gsi
);
4363 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
4365 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
4366 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
4372 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
4374 if (density_pct
> DENSITY_PCT_THRESHOLD
4375 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
4377 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
4378 if (dump_enabled_p ())
4379 dump_printf_loc (MSG_NOTE
, vect_location
,
4380 "density %d%%, cost %d exceeds threshold, penalizing "
4381 "loop body cost by %d%%", density_pct
,
4382 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
4386 /* Implement targetm.vectorize.init_cost. */
4389 rs6000_init_cost (struct loop
*loop_info
)
4391 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
4392 data
->loop_info
= loop_info
;
4393 data
->cost
[vect_prologue
] = 0;
4394 data
->cost
[vect_body
] = 0;
4395 data
->cost
[vect_epilogue
] = 0;
4399 /* Implement targetm.vectorize.add_stmt_cost. */
4402 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
4403 struct _stmt_vec_info
*stmt_info
, int misalign
,
4404 enum vect_cost_model_location where
)
4406 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4407 unsigned retval
= 0;
4409 if (flag_vect_cost_model
)
4411 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
4412 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
4414 /* Statements in an inner loop relative to the loop being
4415 vectorized are weighted more heavily. The value here is
4416 arbitrary and could potentially be improved with analysis. */
4417 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
4418 count
*= 50; /* FIXME. */
4420 retval
= (unsigned) (count
* stmt_cost
);
4421 cost_data
->cost
[where
] += retval
;
4427 /* Implement targetm.vectorize.finish_cost. */
4430 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
4431 unsigned *body_cost
, unsigned *epilogue_cost
)
4433 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4435 if (cost_data
->loop_info
)
4436 rs6000_density_test (cost_data
);
4438 *prologue_cost
= cost_data
->cost
[vect_prologue
];
4439 *body_cost
= cost_data
->cost
[vect_body
];
4440 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
4443 /* Implement targetm.vectorize.destroy_cost_data. */
4446 rs6000_destroy_cost_data (void *data
)
4451 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
4452 library with vectorized intrinsics. */
4455 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
4458 const char *suffix
= NULL
;
4459 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
4462 enum machine_mode el_mode
, in_mode
;
4465 /* Libmass is suitable for unsafe math only as it does not correctly support
4466 parts of IEEE with the required precision such as denormals. Only support
4467 it if we have VSX to use the simd d2 or f4 functions.
4468 XXX: Add variable length support. */
4469 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
4472 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4473 n
= TYPE_VECTOR_SUBPARTS (type_out
);
4474 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4475 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4476 if (el_mode
!= in_mode
4480 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4482 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4485 case BUILT_IN_ATAN2
:
4486 case BUILT_IN_HYPOT
:
4492 case BUILT_IN_ACOSH
:
4494 case BUILT_IN_ASINH
:
4496 case BUILT_IN_ATANH
:
4504 case BUILT_IN_EXPM1
:
4505 case BUILT_IN_LGAMMA
:
4506 case BUILT_IN_LOG10
:
4507 case BUILT_IN_LOG1P
:
4515 bdecl
= builtin_decl_implicit (fn
);
4516 suffix
= "d2"; /* pow -> powd2 */
4517 if (el_mode
!= DFmode
4523 case BUILT_IN_ATAN2F
:
4524 case BUILT_IN_HYPOTF
:
4529 case BUILT_IN_ACOSF
:
4530 case BUILT_IN_ACOSHF
:
4531 case BUILT_IN_ASINF
:
4532 case BUILT_IN_ASINHF
:
4533 case BUILT_IN_ATANF
:
4534 case BUILT_IN_ATANHF
:
4535 case BUILT_IN_CBRTF
:
4537 case BUILT_IN_COSHF
:
4539 case BUILT_IN_ERFCF
:
4540 case BUILT_IN_EXP2F
:
4542 case BUILT_IN_EXPM1F
:
4543 case BUILT_IN_LGAMMAF
:
4544 case BUILT_IN_LOG10F
:
4545 case BUILT_IN_LOG1PF
:
4546 case BUILT_IN_LOG2F
:
4549 case BUILT_IN_SINHF
:
4550 case BUILT_IN_SQRTF
:
4552 case BUILT_IN_TANHF
:
4553 bdecl
= builtin_decl_implicit (fn
);
4554 suffix
= "4"; /* powf -> powf4 */
4555 if (el_mode
!= SFmode
4568 gcc_assert (suffix
!= NULL
);
4569 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
4573 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
4574 strcat (name
, suffix
);
4577 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
4578 else if (n_args
== 2)
4579 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
4583 /* Build a function declaration for the vectorized function. */
4584 new_fndecl
= build_decl (BUILTINS_LOCATION
,
4585 FUNCTION_DECL
, get_identifier (name
), fntype
);
4586 TREE_PUBLIC (new_fndecl
) = 1;
4587 DECL_EXTERNAL (new_fndecl
) = 1;
4588 DECL_IS_NOVOPS (new_fndecl
) = 1;
4589 TREE_READONLY (new_fndecl
) = 1;
4594 /* Returns a function decl for a vectorized version of the builtin function
4595 with builtin function code FN and the result vector type TYPE, or NULL_TREE
4596 if it is not available. */
4599 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
4602 enum machine_mode in_mode
, out_mode
;
4605 if (TARGET_DEBUG_BUILTIN
)
4606 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
4607 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
4608 GET_MODE_NAME (TYPE_MODE (type_out
)),
4609 GET_MODE_NAME (TYPE_MODE (type_in
)));
4611 if (TREE_CODE (type_out
) != VECTOR_TYPE
4612 || TREE_CODE (type_in
) != VECTOR_TYPE
4613 || !TARGET_VECTORIZE_BUILTINS
)
4616 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4617 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
4618 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4619 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4621 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4623 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4626 case BUILT_IN_CLZIMAX
:
4627 case BUILT_IN_CLZLL
:
4630 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4632 if (out_mode
== QImode
&& out_n
== 16)
4633 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZB
];
4634 else if (out_mode
== HImode
&& out_n
== 8)
4635 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZH
];
4636 else if (out_mode
== SImode
&& out_n
== 4)
4637 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZW
];
4638 else if (out_mode
== DImode
&& out_n
== 2)
4639 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZD
];
4642 case BUILT_IN_COPYSIGN
:
4643 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4644 && out_mode
== DFmode
&& out_n
== 2
4645 && in_mode
== DFmode
&& in_n
== 2)
4646 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
4648 case BUILT_IN_COPYSIGNF
:
4649 if (out_mode
!= SFmode
|| out_n
!= 4
4650 || in_mode
!= SFmode
|| in_n
!= 4)
4652 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4653 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
4654 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4655 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
4657 case BUILT_IN_POPCOUNTIMAX
:
4658 case BUILT_IN_POPCOUNTLL
:
4659 case BUILT_IN_POPCOUNTL
:
4660 case BUILT_IN_POPCOUNT
:
4661 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4663 if (out_mode
== QImode
&& out_n
== 16)
4664 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTB
];
4665 else if (out_mode
== HImode
&& out_n
== 8)
4666 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTH
];
4667 else if (out_mode
== SImode
&& out_n
== 4)
4668 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTW
];
4669 else if (out_mode
== DImode
&& out_n
== 2)
4670 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTD
];
4674 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4675 && out_mode
== DFmode
&& out_n
== 2
4676 && in_mode
== DFmode
&& in_n
== 2)
4677 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
4679 case BUILT_IN_SQRTF
:
4680 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4681 && out_mode
== SFmode
&& out_n
== 4
4682 && in_mode
== SFmode
&& in_n
== 4)
4683 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
4686 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4687 && out_mode
== DFmode
&& out_n
== 2
4688 && in_mode
== DFmode
&& in_n
== 2)
4689 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
4691 case BUILT_IN_CEILF
:
4692 if (out_mode
!= SFmode
|| out_n
!= 4
4693 || in_mode
!= SFmode
|| in_n
!= 4)
4695 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4696 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
4697 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4698 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
4700 case BUILT_IN_FLOOR
:
4701 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4702 && out_mode
== DFmode
&& out_n
== 2
4703 && in_mode
== DFmode
&& in_n
== 2)
4704 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
4706 case BUILT_IN_FLOORF
:
4707 if (out_mode
!= SFmode
|| out_n
!= 4
4708 || in_mode
!= SFmode
|| in_n
!= 4)
4710 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4711 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
4712 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4713 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
4716 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4717 && out_mode
== DFmode
&& out_n
== 2
4718 && in_mode
== DFmode
&& in_n
== 2)
4719 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
4722 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4723 && out_mode
== SFmode
&& out_n
== 4
4724 && in_mode
== SFmode
&& in_n
== 4)
4725 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
4726 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
4727 && out_mode
== SFmode
&& out_n
== 4
4728 && in_mode
== SFmode
&& in_n
== 4)
4729 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
4731 case BUILT_IN_TRUNC
:
4732 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4733 && out_mode
== DFmode
&& out_n
== 2
4734 && in_mode
== DFmode
&& in_n
== 2)
4735 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
4737 case BUILT_IN_TRUNCF
:
4738 if (out_mode
!= SFmode
|| out_n
!= 4
4739 || in_mode
!= SFmode
|| in_n
!= 4)
4741 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4742 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
4743 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4744 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
4746 case BUILT_IN_NEARBYINT
:
4747 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4748 && flag_unsafe_math_optimizations
4749 && out_mode
== DFmode
&& out_n
== 2
4750 && in_mode
== DFmode
&& in_n
== 2)
4751 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
4753 case BUILT_IN_NEARBYINTF
:
4754 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4755 && flag_unsafe_math_optimizations
4756 && out_mode
== SFmode
&& out_n
== 4
4757 && in_mode
== SFmode
&& in_n
== 4)
4758 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
4761 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4762 && !flag_trapping_math
4763 && out_mode
== DFmode
&& out_n
== 2
4764 && in_mode
== DFmode
&& in_n
== 2)
4765 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
4767 case BUILT_IN_RINTF
:
4768 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4769 && !flag_trapping_math
4770 && out_mode
== SFmode
&& out_n
== 4
4771 && in_mode
== SFmode
&& in_n
== 4)
4772 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
4779 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
4781 enum rs6000_builtins fn
4782 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
4785 case RS6000_BUILTIN_RSQRTF
:
4786 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4787 && out_mode
== SFmode
&& out_n
== 4
4788 && in_mode
== SFmode
&& in_n
== 4)
4789 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
4791 case RS6000_BUILTIN_RSQRT
:
4792 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4793 && out_mode
== DFmode
&& out_n
== 2
4794 && in_mode
== DFmode
&& in_n
== 2)
4795 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
4797 case RS6000_BUILTIN_RECIPF
:
4798 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4799 && out_mode
== SFmode
&& out_n
== 4
4800 && in_mode
== SFmode
&& in_n
== 4)
4801 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
4803 case RS6000_BUILTIN_RECIP
:
4804 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4805 && out_mode
== DFmode
&& out_n
== 2
4806 && in_mode
== DFmode
&& in_n
== 2)
4807 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
4814 /* Generate calls to libmass if appropriate. */
4815 if (rs6000_veclib_handler
)
4816 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
4821 /* Default CPU string for rs6000*_file_start functions. */
4822 static const char *rs6000_default_cpu
;
4824 /* Do anything needed at the start of the asm file. */
4827 rs6000_file_start (void)
4830 const char *start
= buffer
;
4831 FILE *file
= asm_out_file
;
4833 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
4835 default_file_start ();
4837 if (flag_verbose_asm
)
4839 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
4841 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
4843 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
4847 if (global_options_set
.x_rs6000_cpu_index
)
4849 fprintf (file
, "%s -mcpu=%s", start
,
4850 processor_target_table
[rs6000_cpu_index
].name
);
4854 if (global_options_set
.x_rs6000_tune_index
)
4856 fprintf (file
, "%s -mtune=%s", start
,
4857 processor_target_table
[rs6000_tune_index
].name
);
4861 if (PPC405_ERRATUM77
)
4863 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
4867 #ifdef USING_ELFOS_H
4868 switch (rs6000_sdata
)
4870 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
4871 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
4872 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
4873 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
4876 if (rs6000_sdata
&& g_switch_value
)
4878 fprintf (file
, "%s -G %d", start
,
4888 if (DEFAULT_ABI
== ABI_ELFv2
)
4889 fprintf (file
, "\t.abiversion 2\n");
4891 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
4892 || (TARGET_ELF
&& flag_pic
== 2))
4894 switch_to_section (toc_section
);
4895 switch_to_section (text_section
);
4900 /* Return nonzero if this function is known to have a null epilogue. */
4903 direct_return (void)
4905 if (reload_completed
)
4907 rs6000_stack_t
*info
= rs6000_stack_info ();
4909 if (info
->first_gp_reg_save
== 32
4910 && info
->first_fp_reg_save
== 64
4911 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
4912 && ! info
->lr_save_p
4913 && ! info
->cr_save_p
4914 && info
->vrsave_mask
== 0
4922 /* Return the number of instructions it takes to form a constant in an
4923 integer register. */
4926 num_insns_constant_wide (HOST_WIDE_INT value
)
4928 /* signed constant loadable with addi */
4929 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
4932 /* constant loadable with addis */
4933 else if ((value
& 0xffff) == 0
4934 && (value
>> 31 == -1 || value
>> 31 == 0))
4937 else if (TARGET_POWERPC64
)
4939 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4940 HOST_WIDE_INT high
= value
>> 31;
4942 if (high
== 0 || high
== -1)
4948 return num_insns_constant_wide (high
) + 1;
4950 return num_insns_constant_wide (low
) + 1;
4952 return (num_insns_constant_wide (high
)
4953 + num_insns_constant_wide (low
) + 1);
4961 num_insns_constant (rtx op
, enum machine_mode mode
)
4963 HOST_WIDE_INT low
, high
;
4965 switch (GET_CODE (op
))
4968 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
4969 && mask64_operand (op
, mode
))
4972 return num_insns_constant_wide (INTVAL (op
));
4974 case CONST_WIDE_INT
:
4977 int ins
= CONST_WIDE_INT_NUNITS (op
) - 1;
4978 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (op
); i
++)
4979 ins
+= num_insns_constant_wide (CONST_WIDE_INT_ELT (op
, i
));
4984 if (mode
== SFmode
|| mode
== SDmode
)
4989 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4990 if (DECIMAL_FLOAT_MODE_P (mode
))
4991 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
4993 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4994 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
5000 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
5001 if (DECIMAL_FLOAT_MODE_P (mode
))
5002 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
5004 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
5005 high
= l
[WORDS_BIG_ENDIAN
== 0];
5006 low
= l
[WORDS_BIG_ENDIAN
!= 0];
5009 return (num_insns_constant_wide (low
)
5010 + num_insns_constant_wide (high
));
5013 if ((high
== 0 && low
>= 0)
5014 || (high
== -1 && low
< 0))
5015 return num_insns_constant_wide (low
);
5017 else if (mask64_operand (op
, mode
))
5021 return num_insns_constant_wide (high
) + 1;
5024 return (num_insns_constant_wide (high
)
5025 + num_insns_constant_wide (low
) + 1);
5033 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5034 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5035 corresponding element of the vector, but for V4SFmode and V2SFmode,
5036 the corresponding "float" is interpreted as an SImode integer. */
5039 const_vector_elt_as_int (rtx op
, unsigned int elt
)
5043 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5044 gcc_assert (GET_MODE (op
) != V2DImode
5045 && GET_MODE (op
) != V2DFmode
);
5047 tmp
= CONST_VECTOR_ELT (op
, elt
);
5048 if (GET_MODE (op
) == V4SFmode
5049 || GET_MODE (op
) == V2SFmode
)
5050 tmp
= gen_lowpart (SImode
, tmp
);
5051 return INTVAL (tmp
);
5054 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5055 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5056 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5057 all items are set to the same value and contain COPIES replicas of the
5058 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5059 operand and the others are set to the value of the operand's msb. */
5062 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
5064 enum machine_mode mode
= GET_MODE (op
);
5065 enum machine_mode inner
= GET_MODE_INNER (mode
);
5073 HOST_WIDE_INT splat_val
;
5074 HOST_WIDE_INT msb_val
;
5076 if (mode
== V2DImode
|| mode
== V2DFmode
|| mode
== V1TImode
)
5079 nunits
= GET_MODE_NUNITS (mode
);
5080 bitsize
= GET_MODE_BITSIZE (inner
);
5081 mask
= GET_MODE_MASK (inner
);
5083 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5085 msb_val
= val
>= 0 ? 0 : -1;
5087 /* Construct the value to be splatted, if possible. If not, return 0. */
5088 for (i
= 2; i
<= copies
; i
*= 2)
5090 HOST_WIDE_INT small_val
;
5092 small_val
= splat_val
>> bitsize
;
5094 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
5096 splat_val
= small_val
;
5099 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5100 if (EASY_VECTOR_15 (splat_val
))
5103 /* Also check if we can splat, and then add the result to itself. Do so if
5104 the value is positive, of if the splat instruction is using OP's mode;
5105 for splat_val < 0, the splat and the add should use the same mode. */
5106 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
5107 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
5110 /* Also check if are loading up the most significant bit which can be done by
5111 loading up -1 and shifting the value left by -1. */
5112 else if (EASY_VECTOR_MSB (splat_val
, inner
))
5118 /* Check if VAL is present in every STEP-th element, and the
5119 other elements are filled with its most significant bit. */
5120 for (i
= 1; i
< nunits
; ++i
)
5122 HOST_WIDE_INT desired_val
;
5123 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
5124 if ((i
& (step
- 1)) == 0)
5127 desired_val
= msb_val
;
5129 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
5137 /* Return true if OP is of the given MODE and can be synthesized
5138 with a vspltisb, vspltish or vspltisw. */
5141 easy_altivec_constant (rtx op
, enum machine_mode mode
)
5143 unsigned step
, copies
;
5145 if (mode
== VOIDmode
)
5146 mode
= GET_MODE (op
);
5147 else if (mode
!= GET_MODE (op
))
5150 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
5152 if (mode
== V2DFmode
)
5153 return zero_constant (op
, mode
);
5155 else if (mode
== V2DImode
)
5157 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
5158 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
5161 if (zero_constant (op
, mode
))
5164 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
5165 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
5171 /* V1TImode is a special container for TImode. Ignore for now. */
5172 else if (mode
== V1TImode
)
5175 /* Start with a vspltisw. */
5176 step
= GET_MODE_NUNITS (mode
) / 4;
5179 if (vspltis_constant (op
, step
, copies
))
5182 /* Then try with a vspltish. */
5188 if (vspltis_constant (op
, step
, copies
))
5191 /* And finally a vspltisb. */
5197 if (vspltis_constant (op
, step
, copies
))
5203 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
5204 result is OP. Abort if it is not possible. */
5207 gen_easy_altivec_constant (rtx op
)
5209 enum machine_mode mode
= GET_MODE (op
);
5210 int nunits
= GET_MODE_NUNITS (mode
);
5211 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5212 unsigned step
= nunits
/ 4;
5213 unsigned copies
= 1;
5215 /* Start with a vspltisw. */
5216 if (vspltis_constant (op
, step
, copies
))
5217 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
5219 /* Then try with a vspltish. */
5225 if (vspltis_constant (op
, step
, copies
))
5226 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
5228 /* And finally a vspltisb. */
5234 if (vspltis_constant (op
, step
, copies
))
5235 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
5241 output_vec_const_move (rtx
*operands
)
5244 enum machine_mode mode
;
5249 mode
= GET_MODE (dest
);
5253 if (zero_constant (vec
, mode
))
5254 return "xxlxor %x0,%x0,%x0";
5256 if ((mode
== V2DImode
|| mode
== V1TImode
)
5257 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
5258 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
5259 return "vspltisw %0,-1";
5265 if (zero_constant (vec
, mode
))
5266 return "vxor %0,%0,%0";
5268 splat_vec
= gen_easy_altivec_constant (vec
);
5269 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
5270 operands
[1] = XEXP (splat_vec
, 0);
5271 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
5274 switch (GET_MODE (splat_vec
))
5277 return "vspltisw %0,%1";
5280 return "vspltish %0,%1";
5283 return "vspltisb %0,%1";
5290 gcc_assert (TARGET_SPE
);
5292 /* Vector constant 0 is handled as a splitter of V2SI, and in the
5293 pattern of V1DI, V4HI, and V2SF.
5295 FIXME: We should probably return # and add post reload
5296 splitters for these, but this way is so easy ;-). */
5297 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
5298 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
5299 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
5300 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
5302 return "li %0,%1\n\tevmergelo %0,%0,%0";
5304 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
5307 /* Initialize TARGET of vector PAIRED to VALS. */
5310 paired_expand_vector_init (rtx target
, rtx vals
)
5312 enum machine_mode mode
= GET_MODE (target
);
5313 int n_elts
= GET_MODE_NUNITS (mode
);
5315 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
5318 for (i
= 0; i
< n_elts
; ++i
)
5320 x
= XVECEXP (vals
, 0, i
);
5321 if (!CONSTANT_P (x
))
5326 /* Load from constant pool. */
5327 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
5333 /* The vector is initialized only with non-constants. */
5334 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
5335 XVECEXP (vals
, 0, 1));
5337 emit_move_insn (target
, new_rtx
);
5341 /* One field is non-constant and the other one is a constant. Load the
5342 constant from the constant pool and use ps_merge instruction to
5343 construct the whole vector. */
5344 op1
= XVECEXP (vals
, 0, 0);
5345 op2
= XVECEXP (vals
, 0, 1);
5347 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
5349 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
5350 emit_move_insn (tmp
, constant_op
);
5352 if (CONSTANT_P (op1
))
5353 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
5355 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
5357 emit_move_insn (target
, new_rtx
);
5361 paired_expand_vector_move (rtx operands
[])
5363 rtx op0
= operands
[0], op1
= operands
[1];
5365 emit_move_insn (op0
, op1
);
5368 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
5369 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
5370 operands for the relation operation COND. This is a recursive
5374 paired_emit_vector_compare (enum rtx_code rcode
,
5375 rtx dest
, rtx op0
, rtx op1
,
5376 rtx cc_op0
, rtx cc_op1
)
5378 rtx tmp
= gen_reg_rtx (V2SFmode
);
5381 gcc_assert (TARGET_PAIRED_FLOAT
);
5382 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
5388 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5392 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5393 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
5397 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
5400 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5403 tmp1
= gen_reg_rtx (V2SFmode
);
5404 max
= gen_reg_rtx (V2SFmode
);
5405 min
= gen_reg_rtx (V2SFmode
);
5406 gen_reg_rtx (V2SFmode
);
5408 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5409 emit_insn (gen_selv2sf4
5410 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5411 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
5412 emit_insn (gen_selv2sf4
5413 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5414 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
5415 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
5418 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5421 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5424 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5427 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5430 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5439 /* Emit vector conditional expression.
5440 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
5441 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
5444 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
5445 rtx cond
, rtx cc_op0
, rtx cc_op1
)
5447 enum rtx_code rcode
= GET_CODE (cond
);
5449 if (!TARGET_PAIRED_FLOAT
)
5452 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
5457 /* Initialize vector TARGET to VALS. */
5460 rs6000_expand_vector_init (rtx target
, rtx vals
)
5462 enum machine_mode mode
= GET_MODE (target
);
5463 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5464 int n_elts
= GET_MODE_NUNITS (mode
);
5465 int n_var
= 0, one_var
= -1;
5466 bool all_same
= true, all_const_zero
= true;
5470 for (i
= 0; i
< n_elts
; ++i
)
5472 x
= XVECEXP (vals
, 0, i
);
5473 if (!CONSTANT_P (x
))
5474 ++n_var
, one_var
= i
;
5475 else if (x
!= CONST0_RTX (inner_mode
))
5476 all_const_zero
= false;
5478 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
5484 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
5485 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
5486 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
5488 /* Zero register. */
5489 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5490 gen_rtx_XOR (mode
, target
, target
)));
5493 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
5495 /* Splat immediate. */
5496 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
5501 /* Load from constant pool. */
5502 emit_move_insn (target
, const_vec
);
5507 /* Double word values on VSX can use xxpermdi or lxvdsx. */
5508 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5510 rtx op0
= XVECEXP (vals
, 0, 0);
5511 rtx op1
= XVECEXP (vals
, 0, 1);
5514 if (!MEM_P (op0
) && !REG_P (op0
))
5515 op0
= force_reg (inner_mode
, op0
);
5516 if (mode
== V2DFmode
)
5517 emit_insn (gen_vsx_splat_v2df (target
, op0
));
5519 emit_insn (gen_vsx_splat_v2di (target
, op0
));
5523 op0
= force_reg (inner_mode
, op0
);
5524 op1
= force_reg (inner_mode
, op1
);
5525 if (mode
== V2DFmode
)
5526 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
5528 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
5533 /* With single precision floating point on VSX, know that internally single
5534 precision is actually represented as a double, and either make 2 V2DF
5535 vectors, and convert these vectors to single precision, or do one
5536 conversion, and splat the result to the other elements. */
5537 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
5541 rtx freg
= gen_reg_rtx (V4SFmode
);
5542 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5543 rtx cvt
= ((TARGET_XSCVDPSPN
)
5544 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
5545 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
5548 emit_insn (gen_vsx_xxspltw_v4sf_direct (target
, freg
, const0_rtx
));
5552 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
5553 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
5554 rtx flt_even
= gen_reg_rtx (V4SFmode
);
5555 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
5556 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5557 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
5558 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
5559 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
5561 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
5562 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
5563 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
5564 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
5565 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
5570 /* Store value to stack temp. Load vector element. Splat. However, splat
5571 of 64-bit items is not supported on Altivec. */
5572 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
5574 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5575 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
5576 XVECEXP (vals
, 0, 0));
5577 x
= gen_rtx_UNSPEC (VOIDmode
,
5578 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5579 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5581 gen_rtx_SET (VOIDmode
,
5584 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
5585 gen_rtx_PARALLEL (VOIDmode
,
5586 gen_rtvec (1, const0_rtx
)));
5587 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5588 gen_rtx_VEC_DUPLICATE (mode
, x
)));
5592 /* One field is non-constant. Load constant then overwrite
5596 rtx copy
= copy_rtx (vals
);
5598 /* Load constant part of vector, substitute neighboring value for
5600 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
5601 rs6000_expand_vector_init (target
, copy
);
5603 /* Insert variable. */
5604 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
5608 /* Construct the vector in memory one field at a time
5609 and load the whole vector. */
5610 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5611 for (i
= 0; i
< n_elts
; i
++)
5612 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
5613 i
* GET_MODE_SIZE (inner_mode
)),
5614 XVECEXP (vals
, 0, i
));
5615 emit_move_insn (target
, mem
);
5618 /* Set field ELT of TARGET to VAL. */
5621 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
5623 enum machine_mode mode
= GET_MODE (target
);
5624 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5625 rtx reg
= gen_reg_rtx (mode
);
5627 int width
= GET_MODE_SIZE (inner_mode
);
5630 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5632 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
5633 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
5634 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
5638 /* Simplify setting single element vectors like V1TImode. */
5639 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (inner_mode
) && elt
== 0)
5641 emit_move_insn (target
, gen_lowpart (mode
, val
));
5645 /* Load single variable value. */
5646 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5647 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
5648 x
= gen_rtx_UNSPEC (VOIDmode
,
5649 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5650 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5652 gen_rtx_SET (VOIDmode
,
5656 /* Linear sequence. */
5657 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
5658 for (i
= 0; i
< 16; ++i
)
5659 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
5661 /* Set permute mask to insert element into target. */
5662 for (i
= 0; i
< width
; ++i
)
5663 XVECEXP (mask
, 0, elt
*width
+ i
)
5664 = GEN_INT (i
+ 0x10);
5665 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
5667 if (BYTES_BIG_ENDIAN
)
5668 x
= gen_rtx_UNSPEC (mode
,
5669 gen_rtvec (3, target
, reg
,
5670 force_reg (V16QImode
, x
)),
5674 /* Invert selector. We prefer to generate VNAND on P8 so
5675 that future fusion opportunities can kick in, but must
5676 generate VNOR elsewhere. */
5677 rtx notx
= gen_rtx_NOT (V16QImode
, force_reg (V16QImode
, x
));
5678 rtx iorx
= (TARGET_P8_VECTOR
5679 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
5680 : gen_rtx_AND (V16QImode
, notx
, notx
));
5681 rtx tmp
= gen_reg_rtx (V16QImode
);
5682 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, iorx
));
5684 /* Permute with operands reversed and adjusted selector. */
5685 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
5689 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
5692 /* Extract field ELT from VEC into TARGET. */
5695 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
5697 enum machine_mode mode
= GET_MODE (vec
);
5698 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5701 if (VECTOR_MEM_VSX_P (mode
))
5708 gcc_assert (elt
== 0 && inner_mode
== TImode
);
5709 emit_move_insn (target
, gen_lowpart (TImode
, vec
));
5712 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
5715 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
5718 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
5723 /* Allocate mode-sized buffer. */
5724 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5726 emit_move_insn (mem
, vec
);
5728 /* Add offset to field within buffer matching vector element. */
5729 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
5731 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
5734 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
5735 implement ANDing by the mask IN. */
5737 build_mask64_2_operands (rtx in
, rtx
*out
)
5739 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
5742 gcc_assert (GET_CODE (in
) == CONST_INT
);
5747 /* Assume c initially something like 0x00fff000000fffff. The idea
5748 is to rotate the word so that the middle ^^^^^^ group of zeros
5749 is at the MS end and can be cleared with an rldicl mask. We then
5750 rotate back and clear off the MS ^^ group of zeros with a
5752 c
= ~c
; /* c == 0xff000ffffff00000 */
5753 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
5754 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
5755 c
= ~c
; /* c == 0x00fff000000fffff */
5756 c
&= -lsb
; /* c == 0x00fff00000000000 */
5757 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5758 c
= ~c
; /* c == 0xff000fffffffffff */
5759 c
&= -lsb
; /* c == 0xff00000000000000 */
5761 while ((lsb
>>= 1) != 0)
5762 shift
++; /* shift == 44 on exit from loop */
5763 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
5764 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
5765 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
5769 /* Assume c initially something like 0xff000f0000000000. The idea
5770 is to rotate the word so that the ^^^ middle group of zeros
5771 is at the LS end and can be cleared with an rldicr mask. We then
5772 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
5774 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
5775 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
5776 c
= ~c
; /* c == 0x00fff0ffffffffff */
5777 c
&= -lsb
; /* c == 0x00fff00000000000 */
5778 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5779 c
= ~c
; /* c == 0xff000fffffffffff */
5780 c
&= -lsb
; /* c == 0xff00000000000000 */
5782 while ((lsb
>>= 1) != 0)
5783 shift
++; /* shift == 44 on exit from loop */
5784 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
5785 m1
>>= shift
; /* m1 == 0x0000000000000fff */
5786 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
5789 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
5790 masks will be all 1's. We are guaranteed more than one transition. */
5791 out
[0] = GEN_INT (64 - shift
);
5792 out
[1] = GEN_INT (m1
);
5793 out
[2] = GEN_INT (shift
);
5794 out
[3] = GEN_INT (m2
);
5797 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
5800 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
5802 if (TARGET_E500_DOUBLE
)
5804 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
5805 subreg:TI and reg:TF. Decimal float modes are like integer
5806 modes (only low part of each register used) for this
5808 if (GET_CODE (op
) == SUBREG
5809 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
5810 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
5811 && REG_P (SUBREG_REG (op
))
5812 && (GET_MODE (SUBREG_REG (op
)) == DFmode
5813 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
5816 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
5818 if (GET_CODE (op
) == SUBREG
5819 && (mode
== DFmode
|| mode
== TFmode
)
5820 && REG_P (SUBREG_REG (op
))
5821 && (GET_MODE (SUBREG_REG (op
)) == DImode
5822 || GET_MODE (SUBREG_REG (op
)) == TImode
5823 || GET_MODE (SUBREG_REG (op
)) == PTImode
5824 || GET_MODE (SUBREG_REG (op
)) == DDmode
5825 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
5830 && GET_CODE (op
) == SUBREG
5832 && REG_P (SUBREG_REG (op
))
5833 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
5839 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
5840 selects whether the alignment is abi mandated, optional, or
5841 both abi and optional alignment. */
5844 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
5846 if (how
!= align_opt
)
5848 if (TREE_CODE (type
) == VECTOR_TYPE
)
5850 if ((TARGET_SPE
&& SPE_VECTOR_MODE (TYPE_MODE (type
)))
5851 || (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
))))
5856 else if (align
< 128)
5859 else if (TARGET_E500_DOUBLE
5860 && TREE_CODE (type
) == REAL_TYPE
5861 && TYPE_MODE (type
) == DFmode
)
5868 if (how
!= align_abi
)
5870 if (TREE_CODE (type
) == ARRAY_TYPE
5871 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
5873 if (align
< BITS_PER_WORD
)
5874 align
= BITS_PER_WORD
;
5881 /* AIX increases natural record alignment to doubleword if the first
5882 field is an FP double while the FP fields remain word aligned. */
5885 rs6000_special_round_type_align (tree type
, unsigned int computed
,
5886 unsigned int specified
)
5888 unsigned int align
= MAX (computed
, specified
);
5889 tree field
= TYPE_FIELDS (type
);
5891 /* Skip all non field decls */
5892 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5893 field
= DECL_CHAIN (field
);
5895 if (field
!= NULL
&& field
!= type
)
5897 type
= TREE_TYPE (field
);
5898 while (TREE_CODE (type
) == ARRAY_TYPE
)
5899 type
= TREE_TYPE (type
);
5901 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
5902 align
= MAX (align
, 64);
5908 /* Darwin increases record alignment to the natural alignment of
5912 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
5913 unsigned int specified
)
5915 unsigned int align
= MAX (computed
, specified
);
5917 if (TYPE_PACKED (type
))
5920 /* Find the first field, looking down into aggregates. */
5922 tree field
= TYPE_FIELDS (type
);
5923 /* Skip all non field decls */
5924 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5925 field
= DECL_CHAIN (field
);
5928 /* A packed field does not contribute any extra alignment. */
5929 if (DECL_PACKED (field
))
5931 type
= TREE_TYPE (field
);
5932 while (TREE_CODE (type
) == ARRAY_TYPE
)
5933 type
= TREE_TYPE (type
);
5934 } while (AGGREGATE_TYPE_P (type
));
5936 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
5937 align
= MAX (align
, TYPE_ALIGN (type
));
5942 /* Return 1 for an operand in small memory on V.4/eabi. */
5945 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
5946 enum machine_mode mode ATTRIBUTE_UNUSED
)
5951 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
5954 if (DEFAULT_ABI
!= ABI_V4
)
5957 /* Vector and float memory instructions have a limited offset on the
5958 SPE, so using a vector or float variable directly as an operand is
5961 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
5964 if (GET_CODE (op
) == SYMBOL_REF
)
5967 else if (GET_CODE (op
) != CONST
5968 || GET_CODE (XEXP (op
, 0)) != PLUS
5969 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
5970 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
5975 rtx sum
= XEXP (op
, 0);
5976 HOST_WIDE_INT summand
;
5978 /* We have to be careful here, because it is the referenced address
5979 that must be 32k from _SDA_BASE_, not just the symbol. */
5980 summand
= INTVAL (XEXP (sum
, 1));
5981 if (summand
< 0 || summand
> g_switch_value
)
5984 sym_ref
= XEXP (sum
, 0);
5987 return SYMBOL_REF_SMALL_P (sym_ref
);
5993 /* Return true if either operand is a general purpose register. */
5996 gpr_or_gpr_p (rtx op0
, rtx op1
)
5998 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
5999 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
6002 /* Return true if this is a move direct operation between GPR registers and
6003 floating point/VSX registers. */
6006 direct_move_p (rtx op0
, rtx op1
)
6010 if (!REG_P (op0
) || !REG_P (op1
))
6013 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
6016 regno0
= REGNO (op0
);
6017 regno1
= REGNO (op1
);
6018 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
6021 if (INT_REGNO_P (regno0
))
6022 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
6024 else if (INT_REGNO_P (regno1
))
6026 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
6029 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
6036 /* Return true if this is a load or store quad operation. This function does
6037 not handle the atomic quad memory instructions. */
6040 quad_load_store_p (rtx op0
, rtx op1
)
6044 if (!TARGET_QUAD_MEMORY
)
6047 else if (REG_P (op0
) && MEM_P (op1
))
6048 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
6049 && quad_memory_operand (op1
, GET_MODE (op1
))
6050 && !reg_overlap_mentioned_p (op0
, op1
));
6052 else if (MEM_P (op0
) && REG_P (op1
))
6053 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
6054 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
6059 if (TARGET_DEBUG_ADDR
)
6061 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
6062 ret
? "true" : "false");
6063 debug_rtx (gen_rtx_SET (VOIDmode
, op0
, op1
));
6069 /* Given an address, return a constant offset term if one exists. */
6072 address_offset (rtx op
)
6074 if (GET_CODE (op
) == PRE_INC
6075 || GET_CODE (op
) == PRE_DEC
)
6077 else if (GET_CODE (op
) == PRE_MODIFY
6078 || GET_CODE (op
) == LO_SUM
)
6081 if (GET_CODE (op
) == CONST
)
6084 if (GET_CODE (op
) == PLUS
)
6087 if (CONST_INT_P (op
))
6093 /* Return true if the MEM operand is a memory operand suitable for use
6094 with a (full width, possibly multiple) gpr load/store. On
6095 powerpc64 this means the offset must be divisible by 4.
6096 Implements 'Y' constraint.
6098 Accept direct, indexed, offset, lo_sum and tocref. Since this is
6099 a constraint function we know the operand has satisfied a suitable
6100 memory predicate. Also accept some odd rtl generated by reload
6101 (see rs6000_legitimize_reload_address for various forms). It is
6102 important that reload rtl be accepted by appropriate constraints
6103 but not by the operand predicate.
6105 Offsetting a lo_sum should not be allowed, except where we know by
6106 alignment that a 32k boundary is not crossed, but see the ???
6107 comment in rs6000_legitimize_reload_address. Note that by
6108 "offsetting" here we mean a further offset to access parts of the
6109 MEM. It's fine to have a lo_sum where the inner address is offset
6110 from a sym, since the same sym+offset will appear in the high part
6111 of the address calculation. */
6114 mem_operand_gpr (rtx op
, enum machine_mode mode
)
6116 unsigned HOST_WIDE_INT offset
;
6118 rtx addr
= XEXP (op
, 0);
6120 op
= address_offset (addr
);
6124 offset
= INTVAL (op
);
6125 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
6128 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
6132 if (GET_CODE (addr
) == LO_SUM
)
6133 /* For lo_sum addresses, we must allow any offset except one that
6134 causes a wrap, so test only the low 16 bits. */
6135 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
6137 return offset
+ 0x8000 < 0x10000u
- extra
;
6140 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
6143 reg_offset_addressing_ok_p (enum machine_mode mode
)
6155 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
6156 TImode is not a vector mode, if we want to use the VSX registers to
6157 move it around, we need to restrict ourselves to reg+reg
6159 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
6167 /* Paired vector modes. Only reg+reg addressing is valid. */
6168 if (TARGET_PAIRED_FLOAT
)
6173 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
6174 addressing for the LFIWZX and STFIWX instructions. */
6175 if (TARGET_NO_SDMODE_STACK
)
6187 virtual_stack_registers_memory_p (rtx op
)
6191 if (GET_CODE (op
) == REG
)
6192 regnum
= REGNO (op
);
6194 else if (GET_CODE (op
) == PLUS
6195 && GET_CODE (XEXP (op
, 0)) == REG
6196 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6197 regnum
= REGNO (XEXP (op
, 0));
6202 return (regnum
>= FIRST_VIRTUAL_REGISTER
6203 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
6206 /* Return true if a MODE sized memory accesses to OP plus OFFSET
6207 is known to not straddle a 32k boundary. */
6210 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
6211 enum machine_mode mode
)
6214 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
6216 if (GET_CODE (op
) != SYMBOL_REF
)
6219 dsize
= GET_MODE_SIZE (mode
);
6220 decl
= SYMBOL_REF_DECL (op
);
6226 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
6227 replacing memory addresses with an anchor plus offset. We
6228 could find the decl by rummaging around in the block->objects
6229 VEC for the given offset but that seems like too much work. */
6230 dalign
= BITS_PER_UNIT
;
6231 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
6232 && SYMBOL_REF_ANCHOR_P (op
)
6233 && SYMBOL_REF_BLOCK (op
) != NULL
)
6235 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
6237 dalign
= block
->alignment
;
6238 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
6240 else if (CONSTANT_POOL_ADDRESS_P (op
))
6242 /* It would be nice to have get_pool_align().. */
6243 enum machine_mode cmode
= get_pool_mode (op
);
6245 dalign
= GET_MODE_ALIGNMENT (cmode
);
6248 else if (DECL_P (decl
))
6250 dalign
= DECL_ALIGN (decl
);
6254 /* Allow BLKmode when the entire object is known to not
6255 cross a 32k boundary. */
6256 if (!DECL_SIZE_UNIT (decl
))
6259 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
6262 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
6266 return dalign
/ BITS_PER_UNIT
>= dsize
;
6271 type
= TREE_TYPE (decl
);
6273 dalign
= TYPE_ALIGN (type
);
6274 if (CONSTANT_CLASS_P (decl
))
6275 dalign
= CONSTANT_ALIGNMENT (decl
, dalign
);
6277 dalign
= DATA_ALIGNMENT (decl
, dalign
);
6281 /* BLKmode, check the entire object. */
6282 if (TREE_CODE (decl
) == STRING_CST
)
6283 dsize
= TREE_STRING_LENGTH (decl
);
6284 else if (TYPE_SIZE_UNIT (type
)
6285 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
6286 dsize
= tree_to_uhwi (TYPE_SIZE_UNIT (type
));
6292 return dalign
/ BITS_PER_UNIT
>= dsize
;
6296 /* Find how many bits of the alignment we know for this access. */
6297 mask
= dalign
/ BITS_PER_UNIT
- 1;
6298 lsb
= offset
& -offset
;
6302 return dalign
>= dsize
;
6306 constant_pool_expr_p (rtx op
)
6310 split_const (op
, &base
, &offset
);
6311 return (GET_CODE (base
) == SYMBOL_REF
6312 && CONSTANT_POOL_ADDRESS_P (base
)
6313 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
6316 static const_rtx tocrel_base
, tocrel_offset
;
6318 /* Return true if OP is a toc pointer relative address (the output
6319 of create_TOC_reference). If STRICT, do not match high part or
6320 non-split -mcmodel=large/medium toc pointer relative addresses. */
6323 toc_relative_expr_p (const_rtx op
, bool strict
)
6328 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6330 /* Only match the low part. */
6331 if (GET_CODE (op
) == LO_SUM
6332 && REG_P (XEXP (op
, 0))
6333 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
6340 tocrel_offset
= const0_rtx
;
6341 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
6343 tocrel_base
= XEXP (op
, 0);
6344 tocrel_offset
= XEXP (op
, 1);
6347 return (GET_CODE (tocrel_base
) == UNSPEC
6348 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
6351 /* Return true if X is a constant pool address, and also for cmodel=medium
6352 if X is a toc-relative address known to be offsettable within MODE. */
6355 legitimate_constant_pool_address_p (const_rtx x
, enum machine_mode mode
,
6358 return (toc_relative_expr_p (x
, strict
)
6359 && (TARGET_CMODEL
!= CMODEL_MEDIUM
6360 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
6362 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
6363 INTVAL (tocrel_offset
), mode
)));
6367 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
6369 return (DEFAULT_ABI
== ABI_V4
6370 && !flag_pic
&& !TARGET_TOC
6371 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
6372 && small_data_operand (x
, mode
));
6375 /* SPE offset addressing is limited to 5-bits worth of double words. */
6376 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
6379 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
,
6380 bool strict
, bool worst_case
)
6382 unsigned HOST_WIDE_INT offset
;
6385 if (GET_CODE (x
) != PLUS
)
6387 if (!REG_P (XEXP (x
, 0)))
6389 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6391 if (!reg_offset_addressing_ok_p (mode
))
6392 return virtual_stack_registers_memory_p (x
);
6393 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
6395 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6398 offset
= INTVAL (XEXP (x
, 1));
6406 /* SPE vector modes. */
6407 return SPE_CONST_OFFSET_OK (offset
);
6412 /* On e500v2, we may have:
6414 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
6416 Which gets addressed with evldd instructions. */
6417 if (TARGET_E500_DOUBLE
)
6418 return SPE_CONST_OFFSET_OK (offset
);
6420 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
6422 if (VECTOR_MEM_VSX_P (mode
))
6427 if (!TARGET_POWERPC64
)
6429 else if (offset
& 3)
6434 if (TARGET_E500_DOUBLE
)
6435 return (SPE_CONST_OFFSET_OK (offset
)
6436 && SPE_CONST_OFFSET_OK (offset
+ 8));
6445 if (!TARGET_POWERPC64
)
6447 else if (offset
& 3)
6456 return offset
< 0x10000 - extra
;
6460 legitimate_indexed_address_p (rtx x
, int strict
)
6464 if (GET_CODE (x
) != PLUS
)
6470 /* Recognize the rtl generated by reload which we know will later be
6471 replaced with proper base and index regs. */
6473 && reload_in_progress
6474 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
6478 return (REG_P (op0
) && REG_P (op1
)
6479 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
6480 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
6481 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
6482 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
6486 avoiding_indexed_address_p (enum machine_mode mode
)
6488 /* Avoid indexed addressing for modes that have non-indexed
6489 load/store instruction forms. */
6490 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
6494 legitimate_indirect_address_p (rtx x
, int strict
)
6496 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
6500 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
6502 if (!TARGET_MACHO
|| !flag_pic
6503 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
6507 if (GET_CODE (x
) != LO_SUM
)
6509 if (GET_CODE (XEXP (x
, 0)) != REG
)
6511 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
6515 return CONSTANT_P (x
);
6519 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
6521 if (GET_CODE (x
) != LO_SUM
)
6523 if (GET_CODE (XEXP (x
, 0)) != REG
)
6525 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6527 /* Restrict addressing for DI because of our SUBREG hackery. */
6528 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6532 if (TARGET_ELF
|| TARGET_MACHO
)
6536 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
6538 /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
6539 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
6540 recognizes some LO_SUM addresses as valid although this
6541 function says opposite. In most cases, LRA through different
6542 transformations can generate correct code for address reloads.
6543 It can not manage only some LO_SUM cases. So we need to add
6544 code analogous to one in rs6000_legitimize_reload_address for
6545 LOW_SUM here saying that some addresses are still valid. */
6546 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
6547 && small_toc_ref (x
, VOIDmode
));
6548 if (TARGET_TOC
&& ! large_toc_ok
)
6550 if (GET_MODE_NUNITS (mode
) != 1)
6552 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6553 && !(/* ??? Assume floating point reg based on mode? */
6554 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
6555 && (mode
== DFmode
|| mode
== DDmode
)))
6558 return CONSTANT_P (x
) || large_toc_ok
;
6565 /* Try machine-dependent ways of modifying an illegitimate address
6566 to be legitimate. If we find one, return the new, valid address.
6567 This is used from only one place: `memory_address' in explow.c.
6569 OLDX is the address as it was before break_out_memory_refs was
6570 called. In some cases it is useful to look at this to decide what
6573 It is always safe for this function to do nothing. It exists to
6574 recognize opportunities to optimize the output.
6576 On RS/6000, first check for the sum of a register with a constant
6577 integer that is out of range. If so, generate code to add the
6578 constant with the low-order 16 bits masked to the register and force
6579 this result into another register (this can be done with `cau').
6580 Then generate an address of REG+(CONST&0xffff), allowing for the
6581 possibility of bit 16 being a one.
6583 Then check for the sum of a register and something not constant, try to
6584 load the other things into a register and return the sum. */
6587 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
6588 enum machine_mode mode
)
6592 if (!reg_offset_addressing_ok_p (mode
))
6594 if (virtual_stack_registers_memory_p (x
))
6597 /* In theory we should not be seeing addresses of the form reg+0,
6598 but just in case it is generated, optimize it away. */
6599 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
6600 return force_reg (Pmode
, XEXP (x
, 0));
6602 /* For TImode with load/store quad, restrict addresses to just a single
6603 pointer, so it works with both GPRs and VSX registers. */
6604 /* Make sure both operands are registers. */
6605 else if (GET_CODE (x
) == PLUS
6606 && (mode
!= TImode
|| !TARGET_QUAD_MEMORY
))
6607 return gen_rtx_PLUS (Pmode
,
6608 force_reg (Pmode
, XEXP (x
, 0)),
6609 force_reg (Pmode
, XEXP (x
, 1)));
6611 return force_reg (Pmode
, x
);
6613 if (GET_CODE (x
) == SYMBOL_REF
)
6615 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
6617 return rs6000_legitimize_tls_address (x
, model
);
6627 /* As in legitimate_offset_address_p we do not assume
6628 worst-case. The mode here is just a hint as to the registers
6629 used. A TImode is usually in gprs, but may actually be in
6630 fprs. Leave worst-case scenario for reload to handle via
6631 insn constraints. PTImode is only GPRs. */
6638 if (GET_CODE (x
) == PLUS
6639 && GET_CODE (XEXP (x
, 0)) == REG
6640 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6641 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
6643 && !(SPE_VECTOR_MODE (mode
)
6644 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
6646 HOST_WIDE_INT high_int
, low_int
;
6648 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
6649 if (low_int
>= 0x8000 - extra
)
6651 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
6652 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6653 GEN_INT (high_int
)), 0);
6654 return plus_constant (Pmode
, sum
, low_int
);
6656 else if (GET_CODE (x
) == PLUS
6657 && GET_CODE (XEXP (x
, 0)) == REG
6658 && GET_CODE (XEXP (x
, 1)) != CONST_INT
6659 && GET_MODE_NUNITS (mode
) == 1
6660 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6661 || (/* ??? Assume floating point reg based on mode? */
6662 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6663 && (mode
== DFmode
|| mode
== DDmode
)))
6664 && !avoiding_indexed_address_p (mode
))
6666 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6667 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
6669 else if (SPE_VECTOR_MODE (mode
)
6670 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
6674 /* We accept [reg + reg] and [reg + OFFSET]. */
6676 if (GET_CODE (x
) == PLUS
)
6678 rtx op1
= XEXP (x
, 0);
6679 rtx op2
= XEXP (x
, 1);
6682 op1
= force_reg (Pmode
, op1
);
6684 if (GET_CODE (op2
) != REG
6685 && (GET_CODE (op2
) != CONST_INT
6686 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
6687 || (GET_MODE_SIZE (mode
) > 8
6688 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
6689 op2
= force_reg (Pmode
, op2
);
6691 /* We can't always do [reg + reg] for these, because [reg +
6692 reg + offset] is not a legitimate addressing mode. */
6693 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
6695 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
6696 return force_reg (Pmode
, y
);
6701 return force_reg (Pmode
, x
);
6703 else if ((TARGET_ELF
6705 || !MACHO_DYNAMIC_NO_PIC_P
6711 && GET_CODE (x
) != CONST_INT
6712 && GET_CODE (x
) != CONST_WIDE_INT
6713 && GET_CODE (x
) != CONST_DOUBLE
6715 && GET_MODE_NUNITS (mode
) == 1
6716 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6717 || (/* ??? Assume floating point reg based on mode? */
6718 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6719 && (mode
== DFmode
|| mode
== DDmode
))))
6721 rtx reg
= gen_reg_rtx (Pmode
);
6723 emit_insn (gen_elf_high (reg
, x
));
6725 emit_insn (gen_macho_high (reg
, x
));
6726 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
6729 && GET_CODE (x
) == SYMBOL_REF
6730 && constant_pool_expr_p (x
)
6731 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
6732 return create_TOC_reference (x
, NULL_RTX
);
6737 /* Debug version of rs6000_legitimize_address. */
6739 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
6745 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
6746 insns
= get_insns ();
6752 "\nrs6000_legitimize_address: mode %s, old code %s, "
6753 "new code %s, modified\n",
6754 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
6755 GET_RTX_NAME (GET_CODE (ret
)));
6757 fprintf (stderr
, "Original address:\n");
6760 fprintf (stderr
, "oldx:\n");
6763 fprintf (stderr
, "New address:\n");
6768 fprintf (stderr
, "Insns added:\n");
6769 debug_rtx_list (insns
, 20);
6775 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
6776 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
6787 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6788 We need to emit DTP-relative relocations. */
6790 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
6792 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6797 fputs ("\t.long\t", file
);
6800 fputs (DOUBLE_INT_ASM_OP
, file
);
6805 output_addr_const (file
, x
);
6806 fputs ("@dtprel+0x8000", file
);
6809 /* Return true if X is a symbol that refers to real (rather than emulated)
6813 rs6000_real_tls_symbol_ref_p (rtx x
)
6815 return (GET_CODE (x
) == SYMBOL_REF
6816 && SYMBOL_REF_TLS_MODEL (x
) >= TLS_MODEL_REAL
);
6819 /* In the name of slightly smaller debug output, and to cater to
6820 general assembler lossage, recognize various UNSPEC sequences
6821 and turn them back into a direct symbol reference. */
6824 rs6000_delegitimize_address (rtx orig_x
)
6828 orig_x
= delegitimize_mem_from_attrs (orig_x
);
6834 if (TARGET_CMODEL
!= CMODEL_SMALL
6835 && GET_CODE (y
) == LO_SUM
)
6839 if (GET_CODE (y
) == PLUS
6840 && GET_MODE (y
) == Pmode
6841 && CONST_INT_P (XEXP (y
, 1)))
6843 offset
= XEXP (y
, 1);
6847 if (GET_CODE (y
) == UNSPEC
6848 && XINT (y
, 1) == UNSPEC_TOCREL
)
6850 #ifdef ENABLE_CHECKING
6851 if (REG_P (XVECEXP (y
, 0, 1))
6852 && REGNO (XVECEXP (y
, 0, 1)) == TOC_REGISTER
)
6856 else if (GET_CODE (XVECEXP (y
, 0, 1)) == DEBUG_EXPR
)
6858 /* Weirdness alert. df_note_compute can replace r2 with a
6859 debug_expr when this unspec is in a debug_insn.
6860 Seen in gcc.dg/pr51957-1.c */
6868 y
= XVECEXP (y
, 0, 0);
6871 /* Do not associate thread-local symbols with the original
6872 constant pool symbol. */
6874 && GET_CODE (y
) == SYMBOL_REF
6875 && CONSTANT_POOL_ADDRESS_P (y
)
6876 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y
)))
6880 if (offset
!= NULL_RTX
)
6881 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
6882 if (!MEM_P (orig_x
))
6885 return replace_equiv_address_nv (orig_x
, y
);
6889 && GET_CODE (orig_x
) == LO_SUM
6890 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
6892 y
= XEXP (XEXP (orig_x
, 1), 0);
6893 if (GET_CODE (y
) == UNSPEC
6894 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
6895 return XVECEXP (y
, 0, 0);
6901 /* Return true if X shouldn't be emitted into the debug info.
6902 The linker doesn't like .toc section references from
6903 .debug_* sections, so reject .toc section symbols. */
6906 rs6000_const_not_ok_for_debug_p (rtx x
)
6908 if (GET_CODE (x
) == SYMBOL_REF
6909 && CONSTANT_POOL_ADDRESS_P (x
))
6911 rtx c
= get_pool_constant (x
);
6912 enum machine_mode cmode
= get_pool_mode (x
);
6913 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
6920 /* Construct the SYMBOL_REF for the tls_get_addr function. */
6922 static GTY(()) rtx rs6000_tls_symbol
;
6924 rs6000_tls_get_addr (void)
6926 if (!rs6000_tls_symbol
)
6927 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
6929 return rs6000_tls_symbol
;
6932 /* Construct the SYMBOL_REF for TLS GOT references. */
6934 static GTY(()) rtx rs6000_got_symbol
;
6936 rs6000_got_sym (void)
6938 if (!rs6000_got_symbol
)
6940 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
6941 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
6942 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
6945 return rs6000_got_symbol
;
6948 /* AIX Thread-Local Address support. */
6951 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
6953 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
6957 name
= XSTR (addr
, 0);
6958 /* Append TLS CSECT qualifier, unless the symbol already is qualified
6959 or the symbol will be in TLS private data section. */
6960 if (name
[strlen (name
) - 1] != ']'
6961 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
6962 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
6964 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
6965 strcpy (tlsname
, name
);
6967 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
6968 tlsaddr
= copy_rtx (addr
);
6969 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
6974 /* Place addr into TOC constant pool. */
6975 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
6977 /* Output the TOC entry and create the MEM referencing the value. */
6978 if (constant_pool_expr_p (XEXP (sym
, 0))
6979 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
6981 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
6982 mem
= gen_const_mem (Pmode
, tocref
);
6983 set_mem_alias_set (mem
, get_TOC_alias_set ());
6988 /* Use global-dynamic for local-dynamic. */
6989 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
6990 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
6992 /* Create new TOC reference for @m symbol. */
6993 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
6994 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
6995 strcpy (tlsname
, "*LCM");
6996 strcat (tlsname
, name
+ 3);
6997 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
6998 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
6999 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
7000 rtx modmem
= gen_const_mem (Pmode
, tocref
);
7001 set_mem_alias_set (modmem
, get_TOC_alias_set ());
7003 rtx modreg
= gen_reg_rtx (Pmode
);
7004 emit_insn (gen_rtx_SET (VOIDmode
, modreg
, modmem
));
7006 tmpreg
= gen_reg_rtx (Pmode
);
7007 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
7009 dest
= gen_reg_rtx (Pmode
);
7011 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
7013 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
7016 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
7017 else if (TARGET_32BIT
)
7019 tlsreg
= gen_reg_rtx (SImode
);
7020 emit_insn (gen_tls_get_tpointer (tlsreg
));
7023 tlsreg
= gen_rtx_REG (DImode
, 13);
7025 /* Load the TOC value into temporary register. */
7026 tmpreg
= gen_reg_rtx (Pmode
);
7027 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
7028 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
7029 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
7031 /* Add TOC symbol value to TLS pointer. */
7032 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
7037 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
7038 this (thread-local) address. */
7041 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
7046 return rs6000_legitimize_tls_address_aix (addr
, model
);
7048 dest
= gen_reg_rtx (Pmode
);
7049 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
7055 tlsreg
= gen_rtx_REG (Pmode
, 13);
7056 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
7060 tlsreg
= gen_rtx_REG (Pmode
, 2);
7061 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
7065 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
7069 tmp
= gen_reg_rtx (Pmode
);
7072 tlsreg
= gen_rtx_REG (Pmode
, 13);
7073 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
7077 tlsreg
= gen_rtx_REG (Pmode
, 2);
7078 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
7082 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
7084 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
7089 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
7091 /* We currently use relocations like @got@tlsgd for tls, which
7092 means the linker will handle allocation of tls entries, placing
7093 them in the .got section. So use a pointer to the .got section,
7094 not one to secondary TOC sections used by 64-bit -mminimal-toc,
7095 or to secondary GOT sections used by 32-bit -fPIC. */
7097 got
= gen_rtx_REG (Pmode
, 2);
7101 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
7104 rtx gsym
= rs6000_got_sym ();
7105 got
= gen_reg_rtx (Pmode
);
7107 rs6000_emit_move (got
, gsym
, Pmode
);
7112 tmp1
= gen_reg_rtx (Pmode
);
7113 tmp2
= gen_reg_rtx (Pmode
);
7114 mem
= gen_const_mem (Pmode
, tmp1
);
7115 lab
= gen_label_rtx ();
7116 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
7117 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
7118 if (TARGET_LINK_STACK
)
7119 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
7120 emit_move_insn (tmp2
, mem
);
7121 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
7122 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
7127 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
7129 tga
= rs6000_tls_get_addr ();
7130 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
7131 1, const0_rtx
, Pmode
);
7133 r3
= gen_rtx_REG (Pmode
, 3);
7134 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7137 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
7139 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
7141 else if (DEFAULT_ABI
== ABI_V4
)
7142 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
7145 call_insn
= last_call_insn ();
7146 PATTERN (call_insn
) = insn
;
7147 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7148 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7149 pic_offset_table_rtx
);
7151 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
7153 tga
= rs6000_tls_get_addr ();
7154 tmp1
= gen_reg_rtx (Pmode
);
7155 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
7156 1, const0_rtx
, Pmode
);
7158 r3
= gen_rtx_REG (Pmode
, 3);
7159 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7162 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
7164 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
7166 else if (DEFAULT_ABI
== ABI_V4
)
7167 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
7170 call_insn
= last_call_insn ();
7171 PATTERN (call_insn
) = insn
;
7172 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7173 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7174 pic_offset_table_rtx
);
7176 if (rs6000_tls_size
== 16)
7179 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
7181 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
7183 else if (rs6000_tls_size
== 32)
7185 tmp2
= gen_reg_rtx (Pmode
);
7187 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
7189 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
7192 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
7194 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
7198 tmp2
= gen_reg_rtx (Pmode
);
7200 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
7202 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
7204 insn
= gen_rtx_SET (Pmode
, dest
,
7205 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
7211 /* IE, or 64-bit offset LE. */
7212 tmp2
= gen_reg_rtx (Pmode
);
7214 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
7216 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
7219 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
7221 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
7229 /* Return 1 if X contains a thread-local symbol. */
7232 rs6000_tls_referenced_p (rtx x
)
7234 if (! TARGET_HAVE_TLS
)
7237 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
7240 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
7243 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
7245 if (GET_CODE (x
) == HIGH
7246 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
7249 /* A TLS symbol in the TOC cannot contain a sum. */
7250 if (GET_CODE (x
) == CONST
7251 && GET_CODE (XEXP (x
, 0)) == PLUS
7252 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
7253 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
7256 /* Do not place an ELF TLS symbol in the constant pool. */
7257 return TARGET_ELF
&& rs6000_tls_referenced_p (x
);
7260 /* Return 1 if *X is a thread-local symbol. This is the same as
7261 rs6000_tls_symbol_ref except for the type of the unused argument. */
7264 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
7266 return RS6000_SYMBOL_REF_TLS_P (*x
);
7269 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
7270 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
7271 can be addressed relative to the toc pointer. */
7274 use_toc_relative_ref (rtx sym
)
7276 return ((constant_pool_expr_p (sym
)
7277 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
7278 get_pool_mode (sym
)))
7279 || (TARGET_CMODEL
== CMODEL_MEDIUM
7280 && SYMBOL_REF_LOCAL_P (sym
)));
7283 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
7284 replace the input X, or the original X if no replacement is called for.
7285 The output parameter *WIN is 1 if the calling macro should goto WIN,
7288 For RS/6000, we wish to handle large displacements off a base
7289 register by splitting the addend across an addiu/addis and the mem insn.
7290 This cuts number of extra insns needed from 3 to 1.
7292 On Darwin, we use this to generate code for floating point constants.
7293 A movsf_low is generated so we wind up with 2 instructions rather than 3.
7294 The Darwin code is inside #if TARGET_MACHO because only then are the
7295 machopic_* functions defined. */
7297 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7298 int opnum
, int type
,
7299 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
7301 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7303 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
7304 DFmode/DImode MEM. */
7307 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
7308 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
7309 reg_offset_p
= false;
7311 /* We must recognize output that we have already generated ourselves. */
7312 if (GET_CODE (x
) == PLUS
7313 && GET_CODE (XEXP (x
, 0)) == PLUS
7314 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7315 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7316 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7318 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7319 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7320 opnum
, (enum reload_type
) type
);
7325 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
7326 if (GET_CODE (x
) == LO_SUM
7327 && GET_CODE (XEXP (x
, 0)) == HIGH
)
7329 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7330 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7331 opnum
, (enum reload_type
) type
);
7337 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
7338 && GET_CODE (x
) == LO_SUM
7339 && GET_CODE (XEXP (x
, 0)) == PLUS
7340 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
7341 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
7342 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
7343 && machopic_operand_p (XEXP (x
, 1)))
7345 /* Result of previous invocation of this function on Darwin
7346 floating point constant. */
7347 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7348 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7349 opnum
, (enum reload_type
) type
);
7355 if (TARGET_CMODEL
!= CMODEL_SMALL
7357 && small_toc_ref (x
, VOIDmode
))
7359 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
7360 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
7361 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7362 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7363 opnum
, (enum reload_type
) type
);
7368 if (GET_CODE (x
) == PLUS
7369 && GET_CODE (XEXP (x
, 0)) == REG
7370 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
7371 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
7372 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7374 && !SPE_VECTOR_MODE (mode
)
7375 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
7376 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
7378 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
7379 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
7381 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7383 /* Check for 32-bit overflow. */
7384 if (high
+ low
!= val
)
7390 /* Reload the high part into a base reg; leave the low part
7391 in the mem directly. */
7393 x
= gen_rtx_PLUS (GET_MODE (x
),
7394 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
7398 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7399 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7400 opnum
, (enum reload_type
) type
);
7405 if (GET_CODE (x
) == SYMBOL_REF
7407 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
7408 && !SPE_VECTOR_MODE (mode
)
7410 && DEFAULT_ABI
== ABI_DARWIN
7411 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
7412 && machopic_symbol_defined_p (x
)
7414 && DEFAULT_ABI
== ABI_V4
7417 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
7418 The same goes for DImode without 64-bit gprs and DFmode and DDmode
7420 ??? Assume floating point reg based on mode? This assumption is
7421 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
7422 where reload ends up doing a DFmode load of a constant from
7423 mem using two gprs. Unfortunately, at this point reload
7424 hasn't yet selected regs so poking around in reload data
7425 won't help and even if we could figure out the regs reliably,
7426 we'd still want to allow this transformation when the mem is
7427 naturally aligned. Since we say the address is good here, we
7428 can't disable offsets from LO_SUMs in mem_operand_gpr.
7429 FIXME: Allow offset from lo_sum for other modes too, when
7430 mem is sufficiently aligned. */
7433 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
7435 && (mode
!= DImode
|| TARGET_POWERPC64
)
7436 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
7437 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
7442 rtx offset
= machopic_gen_offset (x
);
7443 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7444 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
7445 gen_rtx_HIGH (Pmode
, offset
)), offset
);
7449 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7450 gen_rtx_HIGH (Pmode
, x
), x
);
7452 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7453 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7454 opnum
, (enum reload_type
) type
);
7459 /* Reload an offset address wrapped by an AND that represents the
7460 masking of the lower bits. Strip the outer AND and let reload
7461 convert the offset address into an indirect address. For VSX,
7462 force reload to create the address with an AND in a separate
7463 register, because we can't guarantee an altivec register will
7465 if (VECTOR_MEM_ALTIVEC_P (mode
)
7466 && GET_CODE (x
) == AND
7467 && GET_CODE (XEXP (x
, 0)) == PLUS
7468 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7469 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7470 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7471 && INTVAL (XEXP (x
, 1)) == -16)
7480 && GET_CODE (x
) == SYMBOL_REF
7481 && use_toc_relative_ref (x
))
7483 x
= create_TOC_reference (x
, NULL_RTX
);
7484 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7485 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7486 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7487 opnum
, (enum reload_type
) type
);
7495 /* Debug version of rs6000_legitimize_reload_address. */
7497 rs6000_debug_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7498 int opnum
, int type
,
7499 int ind_levels
, int *win
)
7501 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
7504 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
7505 "type = %d, ind_levels = %d, win = %d, original addr:\n",
7506 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
7510 fprintf (stderr
, "Same address returned\n");
7512 fprintf (stderr
, "NULL returned\n");
7515 fprintf (stderr
, "New address:\n");
7522 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
7523 that is a valid memory address for an instruction.
7524 The MODE argument is the machine mode for the MEM expression
7525 that wants to use this address.
7527 On the RS/6000, there are four valid address: a SYMBOL_REF that
7528 refers to a constant pool entry of an address (or the sum of it
7529 plus a constant), a short (16-bit signed) constant plus a register,
7530 the sum of two registers, or a register indirect, possibly with an
7531 auto-increment. For DFmode, DDmode and DImode with a constant plus
7532 register, we must ensure that both words are addressable or PowerPC64
7533 with offset word aligned.
7535 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
7536 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
7537 because adjacent memory cells are accessed by adding word-sized offsets
7538 during assembly output. */
7540 rs6000_legitimate_address_p (enum machine_mode mode
, rtx x
, bool reg_ok_strict
)
7542 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7544 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
7545 if (VECTOR_MEM_ALTIVEC_P (mode
)
7546 && GET_CODE (x
) == AND
7547 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7548 && INTVAL (XEXP (x
, 1)) == -16)
7551 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
7553 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
7556 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
7557 && mode_supports_pre_incdec_p (mode
)
7558 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
7560 if (virtual_stack_registers_memory_p (x
))
7562 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
7565 && legitimate_constant_pool_address_p (x
, mode
,
7566 reg_ok_strict
|| lra_in_progress
))
7568 /* For TImode, if we have load/store quad and TImode in VSX registers, only
7569 allow register indirect addresses. This will allow the values to go in
7570 either GPRs or VSX registers without reloading. The vector types would
7571 tend to go into VSX registers, so we allow REG+REG, while TImode seems
7572 somewhat split, in that some uses are GPR based, and some VSX based. */
7573 if (mode
== TImode
&& TARGET_QUAD_MEMORY
&& TARGET_VSX_TIMODE
)
7575 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
7578 && GET_CODE (x
) == PLUS
7579 && GET_CODE (XEXP (x
, 0)) == REG
7580 && (XEXP (x
, 0) == virtual_stack_vars_rtx
7581 || XEXP (x
, 0) == arg_pointer_rtx
)
7582 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7584 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
7588 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7590 || (mode
!= DFmode
&& mode
!= DDmode
)
7591 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
7592 && (TARGET_POWERPC64
|| mode
!= DImode
)
7593 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
7595 && !avoiding_indexed_address_p (mode
)
7596 && legitimate_indexed_address_p (x
, reg_ok_strict
))
7598 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
7599 && mode_supports_pre_modify_p (mode
)
7600 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
7601 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
7602 reg_ok_strict
, false)
7603 || (!avoiding_indexed_address_p (mode
)
7604 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
7605 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
7607 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
7612 /* Debug version of rs6000_legitimate_address_p. */
7614 rs6000_debug_legitimate_address_p (enum machine_mode mode
, rtx x
,
7617 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
7619 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
7620 "strict = %d, reload = %s, code = %s\n",
7621 ret
? "true" : "false",
7622 GET_MODE_NAME (mode
),
7626 : (reload_in_progress
? "progress" : "before")),
7627 GET_RTX_NAME (GET_CODE (x
)));
7633 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
7636 rs6000_mode_dependent_address_p (const_rtx addr
,
7637 addr_space_t as ATTRIBUTE_UNUSED
)
7639 return rs6000_mode_dependent_address_ptr (addr
);
7642 /* Go to LABEL if ADDR (a legitimate address expression)
7643 has an effect that depends on the machine mode it is used for.
7645 On the RS/6000 this is true of all integral offsets (since AltiVec
7646 and VSX modes don't allow them) or is a pre-increment or decrement.
7648 ??? Except that due to conceptual problems in offsettable_address_p
7649 we can't really report the problems of integral offsets. So leave
7650 this assuming that the adjustable offset must be valid for the
7651 sub-words of a TFmode operand, which is what we had before. */
7654 rs6000_mode_dependent_address (const_rtx addr
)
7656 switch (GET_CODE (addr
))
7659 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
7660 is considered a legitimate address before reload, so there
7661 are no offset restrictions in that case. Note that this
7662 condition is safe in strict mode because any address involving
7663 virtual_stack_vars_rtx or arg_pointer_rtx would already have
7664 been rejected as illegitimate. */
7665 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
7666 && XEXP (addr
, 0) != arg_pointer_rtx
7667 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
7669 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
7670 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
7675 /* Anything in the constant pool is sufficiently aligned that
7676 all bytes have the same high part address. */
7677 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
7679 /* Auto-increment cases are now treated generically in recog.c. */
7681 return TARGET_UPDATE
;
7683 /* AND is only allowed in Altivec loads. */
7694 /* Debug version of rs6000_mode_dependent_address. */
7696 rs6000_debug_mode_dependent_address (const_rtx addr
)
7698 bool ret
= rs6000_mode_dependent_address (addr
);
7700 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
7701 ret
? "true" : "false");
7707 /* Implement FIND_BASE_TERM. */
7710 rs6000_find_base_term (rtx op
)
7715 if (GET_CODE (base
) == CONST
)
7716 base
= XEXP (base
, 0);
7717 if (GET_CODE (base
) == PLUS
)
7718 base
= XEXP (base
, 0);
7719 if (GET_CODE (base
) == UNSPEC
)
7720 switch (XINT (base
, 1))
7723 case UNSPEC_MACHOPIC_OFFSET
:
7724 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
7725 for aliasing purposes. */
7726 return XVECEXP (base
, 0, 0);
7732 /* More elaborate version of recog's offsettable_memref_p predicate
7733 that works around the ??? note of rs6000_mode_dependent_address.
7734 In particular it accepts
7736 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
7738 in 32-bit mode, that the recog predicate rejects. */
7741 rs6000_offsettable_memref_p (rtx op
, enum machine_mode reg_mode
)
7748 /* First mimic offsettable_memref_p. */
7749 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
7752 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
7753 the latter predicate knows nothing about the mode of the memory
7754 reference and, therefore, assumes that it is the largest supported
7755 mode (TFmode). As a consequence, legitimate offsettable memory
7756 references are rejected. rs6000_legitimate_offset_address_p contains
7757 the correct logic for the PLUS case of rs6000_mode_dependent_address,
7758 at least with a little bit of help here given that we know the
7759 actual registers used. */
7760 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
7761 || GET_MODE_SIZE (reg_mode
) == 4);
7762 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
7766 /* Change register usage conditional on target flags. */
7768 rs6000_conditional_register_usage (void)
7772 if (TARGET_DEBUG_TARGET
)
7773 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
7775 /* Set MQ register fixed (already call_used) so that it will not be
7779 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
7781 fixed_regs
[13] = call_used_regs
[13]
7782 = call_really_used_regs
[13] = 1;
7784 /* Conditionally disable FPRs. */
7785 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
7786 for (i
= 32; i
< 64; i
++)
7787 fixed_regs
[i
] = call_used_regs
[i
]
7788 = call_really_used_regs
[i
] = 1;
7790 /* The TOC register is not killed across calls in a way that is
7791 visible to the compiler. */
7792 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7793 call_really_used_regs
[2] = 0;
7795 if (DEFAULT_ABI
== ABI_V4
7796 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7798 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7800 if (DEFAULT_ABI
== ABI_V4
7801 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7803 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7804 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7805 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7807 if (DEFAULT_ABI
== ABI_DARWIN
7808 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
7809 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7810 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7811 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7813 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
7814 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7815 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7819 global_regs
[SPEFSCR_REGNO
] = 1;
7820 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
7821 registers in prologues and epilogues. We no longer use r14
7822 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
7823 pool for link-compatibility with older versions of GCC. Once
7824 "old" code has died out, we can return r14 to the allocation
7827 = call_used_regs
[14]
7828 = call_really_used_regs
[14] = 1;
7831 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
7833 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
7834 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7835 call_really_used_regs
[VRSAVE_REGNO
] = 1;
7838 if (TARGET_ALTIVEC
|| TARGET_VSX
)
7839 global_regs
[VSCR_REGNO
] = 1;
7841 if (TARGET_ALTIVEC_ABI
)
7843 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
7844 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7846 /* AIX reserves VR20:31 in non-extended ABI mode. */
7848 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
7849 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7854 /* Output insns to set DEST equal to the constant SOURCE as a series of
7855 lis, ori and shl instructions and return TRUE. */
7858 rs6000_emit_set_const (rtx dest
, rtx source
)
7860 enum machine_mode mode
= GET_MODE (dest
);
7861 rtx temp
, insn
, set
;
7864 gcc_checking_assert (CONST_INT_P (source
));
7865 c
= INTVAL (source
);
7870 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
7874 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
7876 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (temp
),
7877 GEN_INT (c
& ~(HOST_WIDE_INT
) 0xffff)));
7878 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
7879 gen_rtx_IOR (SImode
, copy_rtx (temp
),
7880 GEN_INT (c
& 0xffff))));
7884 if (!TARGET_POWERPC64
)
7888 hi
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
== 0,
7890 lo
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
7892 emit_move_insn (hi
, GEN_INT (c
>> 32));
7893 c
= ((c
& 0xffffffff) ^ 0x80000000) - 0x80000000;
7894 emit_move_insn (lo
, GEN_INT (c
));
7897 rs6000_emit_set_long_const (dest
, c
);
7904 insn
= get_last_insn ();
7905 set
= single_set (insn
);
7906 if (! CONSTANT_P (SET_SRC (set
)))
7907 set_unique_reg_note (insn
, REG_EQUAL
, GEN_INT (c
));
7912 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
7913 Output insns to set DEST equal to the constant C as a series of
7914 lis, ori and shl instructions. */
7917 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c
)
7920 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
7930 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
7931 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
7932 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
7934 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
7935 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
7937 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
7939 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
7940 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
7942 emit_move_insn (dest
,
7943 gen_rtx_IOR (DImode
, copy_rtx (temp
),
7946 else if (ud3
== 0 && ud4
== 0)
7948 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
7950 gcc_assert (ud2
& 0x8000);
7951 emit_move_insn (copy_rtx (temp
),
7952 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
7954 emit_move_insn (copy_rtx (temp
),
7955 gen_rtx_IOR (DImode
, copy_rtx (temp
),
7957 emit_move_insn (dest
,
7958 gen_rtx_ZERO_EXTEND (DImode
,
7959 gen_lowpart (SImode
,
7962 else if ((ud4
== 0xffff && (ud3
& 0x8000))
7963 || (ud4
== 0 && ! (ud3
& 0x8000)))
7965 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
7967 emit_move_insn (copy_rtx (temp
),
7968 GEN_INT (((ud3
<< 16) ^ 0x80000000) - 0x80000000));
7970 emit_move_insn (copy_rtx (temp
),
7971 gen_rtx_IOR (DImode
, copy_rtx (temp
),
7973 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
7974 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
7977 emit_move_insn (dest
,
7978 gen_rtx_IOR (DImode
, copy_rtx (temp
),
7983 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
7985 emit_move_insn (copy_rtx (temp
),
7986 GEN_INT (((ud4
<< 16) ^ 0x80000000) - 0x80000000));
7988 emit_move_insn (copy_rtx (temp
),
7989 gen_rtx_IOR (DImode
, copy_rtx (temp
),
7992 emit_move_insn (ud2
!= 0 || ud1
!= 0 ? copy_rtx (temp
) : dest
,
7993 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
7996 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
7997 gen_rtx_IOR (DImode
, copy_rtx (temp
),
7998 GEN_INT (ud2
<< 16)));
8000 emit_move_insn (dest
,
8001 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8006 /* Helper for the following. Get rid of [r+r] memory refs
8007 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
8010 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
8012 if (reload_in_progress
)
8015 if (GET_CODE (operands
[0]) == MEM
8016 && GET_CODE (XEXP (operands
[0], 0)) != REG
8017 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
8018 GET_MODE (operands
[0]), false))
8020 = replace_equiv_address (operands
[0],
8021 copy_addr_to_reg (XEXP (operands
[0], 0)));
8023 if (GET_CODE (operands
[1]) == MEM
8024 && GET_CODE (XEXP (operands
[1], 0)) != REG
8025 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
8026 GET_MODE (operands
[1]), false))
8028 = replace_equiv_address (operands
[1],
8029 copy_addr_to_reg (XEXP (operands
[1], 0)));
8032 /* Generate a vector of constants to permute MODE for a little-endian
8033 storage operation by swapping the two halves of a vector. */
8035 rs6000_const_vec (enum machine_mode mode
)
8063 v
= rtvec_alloc (subparts
);
8065 for (i
= 0; i
< subparts
/ 2; ++i
)
8066 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
8067 for (i
= subparts
/ 2; i
< subparts
; ++i
)
8068 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
8073 /* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
8074 for a VSX load or store operation. */
8076 rs6000_gen_le_vsx_permute (rtx source
, enum machine_mode mode
)
8078 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
8079 return gen_rtx_VEC_SELECT (mode
, source
, par
);
8082 /* Emit a little-endian load from vector memory location SOURCE to VSX
8083 register DEST in mode MODE. The load is done with two permuting
8084 insn's that represent an lxvd2x and xxpermdi. */
8086 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, enum machine_mode mode
)
8088 rtx tmp
, permute_mem
, permute_reg
;
8090 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8092 if (mode
== TImode
|| mode
== V1TImode
)
8095 dest
= gen_lowpart (V2DImode
, dest
);
8096 source
= adjust_address (source
, V2DImode
, 0);
8099 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
8100 permute_mem
= rs6000_gen_le_vsx_permute (source
, mode
);
8101 permute_reg
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8102 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_mem
));
8103 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_reg
));
8106 /* Emit a little-endian store to vector memory location DEST from VSX
8107 register SOURCE in mode MODE. The store is done with two permuting
8108 insn's that represent an xxpermdi and an stxvd2x. */
8110 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, enum machine_mode mode
)
8112 rtx tmp
, permute_src
, permute_tmp
;
8114 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8116 if (mode
== TImode
|| mode
== V1TImode
)
8119 dest
= adjust_address (dest
, V2DImode
, 0);
8120 source
= gen_lowpart (V2DImode
, source
);
8123 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
8124 permute_src
= rs6000_gen_le_vsx_permute (source
, mode
);
8125 permute_tmp
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8126 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_src
));
8127 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_tmp
));
8130 /* Emit a sequence representing a little-endian VSX load or store,
8131 moving data from SOURCE to DEST in mode MODE. This is done
8132 separately from rs6000_emit_move to ensure it is called only
8133 during expand. LE VSX loads and stores introduced later are
8134 handled with a split. The expand-time RTL generation allows
8135 us to optimize away redundant pairs of register-permutes. */
8137 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, enum machine_mode mode
)
8139 gcc_assert (!BYTES_BIG_ENDIAN
8140 && VECTOR_MEM_VSX_P (mode
)
8141 && !gpr_or_gpr_p (dest
, source
)
8142 && (MEM_P (source
) ^ MEM_P (dest
)));
8146 gcc_assert (REG_P (dest
) || GET_CODE (dest
) == SUBREG
);
8147 rs6000_emit_le_vsx_load (dest
, source
, mode
);
8151 if (!REG_P (source
))
8152 source
= force_reg (mode
, source
);
8153 rs6000_emit_le_vsx_store (dest
, source
, mode
);
8157 /* Emit a move from SOURCE to DEST in mode MODE. */
8159 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
8163 operands
[1] = source
;
8165 if (TARGET_DEBUG_ADDR
)
8168 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
8169 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
8170 GET_MODE_NAME (mode
),
8173 can_create_pseudo_p ());
8175 fprintf (stderr
, "source:\n");
8179 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
8180 if (CONST_WIDE_INT_P (operands
[1])
8181 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8183 /* This should be fixed with the introduction of CONST_WIDE_INT. */
8187 /* Check if GCC is setting up a block move that will end up using FP
8188 registers as temporaries. We must make sure this is acceptable. */
8189 if (GET_CODE (operands
[0]) == MEM
8190 && GET_CODE (operands
[1]) == MEM
8192 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
8193 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
8194 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
8195 ? 32 : MEM_ALIGN (operands
[0])))
8196 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
8198 : MEM_ALIGN (operands
[1]))))
8199 && ! MEM_VOLATILE_P (operands
[0])
8200 && ! MEM_VOLATILE_P (operands
[1]))
8202 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
8203 adjust_address (operands
[1], SImode
, 0));
8204 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
8205 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
8209 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
8210 && !gpc_reg_operand (operands
[1], mode
))
8211 operands
[1] = force_reg (mode
, operands
[1]);
8213 /* Recognize the case where operand[1] is a reference to thread-local
8214 data and load its address to a register. */
8215 if (rs6000_tls_referenced_p (operands
[1]))
8217 enum tls_model model
;
8218 rtx tmp
= operands
[1];
8221 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
8223 addend
= XEXP (XEXP (tmp
, 0), 1);
8224 tmp
= XEXP (XEXP (tmp
, 0), 0);
8227 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
8228 model
= SYMBOL_REF_TLS_MODEL (tmp
);
8229 gcc_assert (model
!= 0);
8231 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
8234 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
8235 tmp
= force_operand (tmp
, operands
[0]);
8240 /* Handle the case where reload calls us with an invalid address. */
8241 if (reload_in_progress
&& mode
== Pmode
8242 && (! general_operand (operands
[1], mode
)
8243 || ! nonimmediate_operand (operands
[0], mode
)))
8246 /* 128-bit constant floating-point values on Darwin should really be
8247 loaded as two parts. */
8248 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
8249 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
8251 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
8252 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
8254 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
8255 GET_MODE_SIZE (DFmode
)),
8256 simplify_gen_subreg (DFmode
, operands
[1], mode
,
8257 GET_MODE_SIZE (DFmode
)),
8262 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
8263 cfun
->machine
->sdmode_stack_slot
=
8264 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
8269 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
8270 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
8271 && (REG_P (operands
[1])
8272 || (GET_CODE (operands
[1]) == SUBREG
8273 && REG_P (SUBREG_REG (operands
[1])))))
8275 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
8276 ? SUBREG_REG (operands
[1]) : operands
[1]);
8279 if (regno
>= FIRST_PSEUDO_REGISTER
)
8281 cl
= reg_preferred_class (regno
);
8282 gcc_assert (cl
!= NO_REGS
);
8283 regno
= ira_class_hard_regs
[cl
][0];
8285 if (FP_REGNO_P (regno
))
8287 if (GET_MODE (operands
[0]) != DDmode
)
8288 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
8289 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
8291 else if (INT_REGNO_P (regno
))
8292 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8299 && (REG_P (operands
[0])
8300 || (GET_CODE (operands
[0]) == SUBREG
8301 && REG_P (SUBREG_REG (operands
[0]))))
8302 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
8303 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
8305 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
8306 ? SUBREG_REG (operands
[0]) : operands
[0]);
8309 if (regno
>= FIRST_PSEUDO_REGISTER
)
8311 cl
= reg_preferred_class (regno
);
8312 gcc_assert (cl
!= NO_REGS
);
8313 regno
= ira_class_hard_regs
[cl
][0];
8315 if (FP_REGNO_P (regno
))
8317 if (GET_MODE (operands
[1]) != DDmode
)
8318 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
8319 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
8321 else if (INT_REGNO_P (regno
))
8322 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8328 if (reload_in_progress
8330 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8331 && MEM_P (operands
[0])
8332 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
8333 && REG_P (operands
[1]))
8335 if (FP_REGNO_P (REGNO (operands
[1])))
8337 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
8338 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8339 emit_insn (gen_movsd_store (mem
, operands
[1]));
8341 else if (INT_REGNO_P (REGNO (operands
[1])))
8343 rtx mem
= operands
[0];
8344 if (BYTES_BIG_ENDIAN
)
8345 mem
= adjust_address_nv (mem
, mode
, 4);
8346 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8347 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
8353 if (reload_in_progress
8355 && REG_P (operands
[0])
8356 && MEM_P (operands
[1])
8357 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8358 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
8360 if (FP_REGNO_P (REGNO (operands
[0])))
8362 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
8363 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8364 emit_insn (gen_movsd_load (operands
[0], mem
));
8366 else if (INT_REGNO_P (REGNO (operands
[0])))
8368 rtx mem
= operands
[1];
8369 if (BYTES_BIG_ENDIAN
)
8370 mem
= adjust_address_nv (mem
, mode
, 4);
8371 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8372 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
8379 /* FIXME: In the long term, this switch statement should go away
8380 and be replaced by a sequence of tests based on things like
8386 if (CONSTANT_P (operands
[1])
8387 && GET_CODE (operands
[1]) != CONST_INT
)
8388 operands
[1] = force_const_mem (mode
, operands
[1]);
8393 rs6000_eliminate_indexed_memrefs (operands
);
8400 if (CONSTANT_P (operands
[1])
8401 && ! easy_fp_constant (operands
[1], mode
))
8402 operands
[1] = force_const_mem (mode
, operands
[1]);
8416 if (CONSTANT_P (operands
[1])
8417 && !easy_vector_constant (operands
[1], mode
))
8418 operands
[1] = force_const_mem (mode
, operands
[1]);
8423 /* Use default pattern for address of ELF small data */
8426 && DEFAULT_ABI
== ABI_V4
8427 && (GET_CODE (operands
[1]) == SYMBOL_REF
8428 || GET_CODE (operands
[1]) == CONST
)
8429 && small_data_operand (operands
[1], mode
))
8431 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8435 if (DEFAULT_ABI
== ABI_V4
8436 && mode
== Pmode
&& mode
== SImode
8437 && flag_pic
== 1 && got_operand (operands
[1], mode
))
8439 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
8443 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
8447 && CONSTANT_P (operands
[1])
8448 && GET_CODE (operands
[1]) != HIGH
8449 && GET_CODE (operands
[1]) != CONST_INT
)
8451 rtx target
= (!can_create_pseudo_p ()
8453 : gen_reg_rtx (mode
));
8455 /* If this is a function address on -mcall-aixdesc,
8456 convert it to the address of the descriptor. */
8457 if (DEFAULT_ABI
== ABI_AIX
8458 && GET_CODE (operands
[1]) == SYMBOL_REF
8459 && XSTR (operands
[1], 0)[0] == '.')
8461 const char *name
= XSTR (operands
[1], 0);
8463 while (*name
== '.')
8465 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
8466 CONSTANT_POOL_ADDRESS_P (new_ref
)
8467 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
8468 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
8469 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
8470 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
8471 operands
[1] = new_ref
;
8474 if (DEFAULT_ABI
== ABI_DARWIN
)
8477 if (MACHO_DYNAMIC_NO_PIC_P
)
8479 /* Take care of any required data indirection. */
8480 operands
[1] = rs6000_machopic_legitimize_pic_address (
8481 operands
[1], mode
, operands
[0]);
8482 if (operands
[0] != operands
[1])
8483 emit_insn (gen_rtx_SET (VOIDmode
,
8484 operands
[0], operands
[1]));
8488 emit_insn (gen_macho_high (target
, operands
[1]));
8489 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
8493 emit_insn (gen_elf_high (target
, operands
[1]));
8494 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
8498 /* If this is a SYMBOL_REF that refers to a constant pool entry,
8499 and we have put it in the TOC, we just need to make a TOC-relative
8502 && GET_CODE (operands
[1]) == SYMBOL_REF
8503 && use_toc_relative_ref (operands
[1]))
8504 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
8505 else if (mode
== Pmode
8506 && CONSTANT_P (operands
[1])
8507 && GET_CODE (operands
[1]) != HIGH
8508 && ((GET_CODE (operands
[1]) != CONST_INT
8509 && ! easy_fp_constant (operands
[1], mode
))
8510 || (GET_CODE (operands
[1]) == CONST_INT
8511 && (num_insns_constant (operands
[1], mode
)
8512 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
8513 || (GET_CODE (operands
[0]) == REG
8514 && FP_REGNO_P (REGNO (operands
[0]))))
8515 && !toc_relative_expr_p (operands
[1], false)
8516 && (TARGET_CMODEL
== CMODEL_SMALL
8517 || can_create_pseudo_p ()
8518 || (REG_P (operands
[0])
8519 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
8523 /* Darwin uses a special PIC legitimizer. */
8524 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
8527 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
8529 if (operands
[0] != operands
[1])
8530 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8535 /* If we are to limit the number of things we put in the TOC and
8536 this is a symbol plus a constant we can add in one insn,
8537 just put the symbol in the TOC and add the constant. Don't do
8538 this if reload is in progress. */
8539 if (GET_CODE (operands
[1]) == CONST
8540 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
8541 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
8542 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
8543 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
8544 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
8545 && ! side_effects_p (operands
[0]))
8548 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
8549 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
8551 sym
= force_reg (mode
, sym
);
8552 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
8556 operands
[1] = force_const_mem (mode
, operands
[1]);
8559 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
8560 && constant_pool_expr_p (XEXP (operands
[1], 0))
8561 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
8562 get_pool_constant (XEXP (operands
[1], 0)),
8563 get_pool_mode (XEXP (operands
[1], 0))))
8565 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
8567 operands
[1] = gen_const_mem (mode
, tocref
);
8568 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
8574 if (!VECTOR_MEM_VSX_P (TImode
))
8575 rs6000_eliminate_indexed_memrefs (operands
);
8579 rs6000_eliminate_indexed_memrefs (operands
);
8583 fatal_insn ("bad move", gen_rtx_SET (VOIDmode
, dest
, source
));
8586 /* Above, we may have called force_const_mem which may have returned
8587 an invalid address. If we can, fix this up; otherwise, reload will
8588 have to deal with it. */
8589 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
8590 operands
[1] = validize_mem (operands
[1]);
8593 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8596 /* Return true if a structure, union or array containing FIELD should be
8597 accessed using `BLKMODE'.
8599 For the SPE, simd types are V2SI, and gcc can be tempted to put the
8600 entire thing in a DI and use subregs to access the internals.
8601 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
8602 back-end. Because a single GPR can hold a V2SI, but not a DI, the
8603 best thing to do is set structs to BLKmode and avoid Severe Tire
8606 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
8607 fit into 1, whereas DI still needs two. */
8610 rs6000_member_type_forces_blk (const_tree field
, enum machine_mode mode
)
8612 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
8613 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
8616 /* Nonzero if we can use a floating-point register to pass this arg. */
8617 #define USE_FP_FOR_ARG_P(CUM,MODE) \
8618 (SCALAR_FLOAT_MODE_P (MODE) \
8619 && (CUM)->fregno <= FP_ARG_MAX_REG \
8620 && TARGET_HARD_FLOAT && TARGET_FPRS)
8622 /* Nonzero if we can use an AltiVec register to pass this arg. */
8623 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
8624 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
8625 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
8626 && TARGET_ALTIVEC_ABI \
8629 /* Walk down the type tree of TYPE counting consecutive base elements.
8630 If *MODEP is VOIDmode, then set it to the first valid floating point
8631 or vector type. If a non-floating point or vector type is found, or
8632 if a floating point or vector type that doesn't match a non-VOIDmode
8633 *MODEP is found, then return -1, otherwise return the count in the
8637 rs6000_aggregate_candidate (const_tree type
, enum machine_mode
*modep
)
8639 enum machine_mode mode
;
8642 switch (TREE_CODE (type
))
8645 mode
= TYPE_MODE (type
);
8646 if (!SCALAR_FLOAT_MODE_P (mode
))
8649 if (*modep
== VOIDmode
)
8658 mode
= TYPE_MODE (TREE_TYPE (type
));
8659 if (!SCALAR_FLOAT_MODE_P (mode
))
8662 if (*modep
== VOIDmode
)
8671 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
8674 /* Use V4SImode as representative of all 128-bit vector types. */
8675 size
= int_size_in_bytes (type
);
8685 if (*modep
== VOIDmode
)
8688 /* Vector modes are considered to be opaque: two vectors are
8689 equivalent for the purposes of being homogeneous aggregates
8690 if they are the same size. */
8699 tree index
= TYPE_DOMAIN (type
);
8701 /* Can't handle incomplete types nor sizes that are not
8703 if (!COMPLETE_TYPE_P (type
)
8704 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
8707 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
8710 || !TYPE_MAX_VALUE (index
)
8711 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
8712 || !TYPE_MIN_VALUE (index
)
8713 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
8717 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
8718 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
8720 /* There must be no padding. */
8721 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
8733 /* Can't handle incomplete types nor sizes that are not
8735 if (!COMPLETE_TYPE_P (type
)
8736 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
8739 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8741 if (TREE_CODE (field
) != FIELD_DECL
)
8744 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8750 /* There must be no padding. */
8751 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
8758 case QUAL_UNION_TYPE
:
8760 /* These aren't very interesting except in a degenerate case. */
8765 /* Can't handle incomplete types nor sizes that are not
8767 if (!COMPLETE_TYPE_P (type
)
8768 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
8770 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8772 if (TREE_CODE (field
) != FIELD_DECL
)
8775 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8778 count
= count
> sub_count
? count
: sub_count
;
8781 /* There must be no padding. */
8782 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
8795 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
8796 float or vector aggregate that shall be passed in FP/vector registers
8797 according to the ELFv2 ABI, return the homogeneous element mode in
8798 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
8800 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
8803 rs6000_discover_homogeneous_aggregate (enum machine_mode mode
, const_tree type
,
8804 enum machine_mode
*elt_mode
,
8807 /* Note that we do not accept complex types at the top level as
8808 homogeneous aggregates; these types are handled via the
8809 targetm.calls.split_complex_arg mechanism. Complex types
8810 can be elements of homogeneous aggregates, however. */
8811 if (DEFAULT_ABI
== ABI_ELFv2
&& type
&& AGGREGATE_TYPE_P (type
))
8813 enum machine_mode field_mode
= VOIDmode
;
8814 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
8816 if (field_count
> 0)
8818 int n_regs
= (SCALAR_FLOAT_MODE_P (field_mode
)?
8819 (GET_MODE_SIZE (field_mode
) + 7) >> 3 : 1);
8821 /* The ELFv2 ABI allows homogeneous aggregates to occupy
8822 up to AGGR_ARG_NUM_REG registers. */
8823 if (field_count
* n_regs
<= AGGR_ARG_NUM_REG
)
8826 *elt_mode
= field_mode
;
8828 *n_elts
= field_count
;
8841 /* Return a nonzero value to say to return the function value in
8842 memory, just as large structures are always returned. TYPE will be
8843 the data type of the value, and FNTYPE will be the type of the
8844 function doing the returning, or @code{NULL} for libcalls.
8846 The AIX ABI for the RS/6000 specifies that all structures are
8847 returned in memory. The Darwin ABI does the same.
8849 For the Darwin 64 Bit ABI, a function result can be returned in
8850 registers or in memory, depending on the size of the return data
8851 type. If it is returned in registers, the value occupies the same
8852 registers as it would if it were the first and only function
8853 argument. Otherwise, the function places its result in memory at
8854 the location pointed to by GPR3.
8856 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
8857 but a draft put them in memory, and GCC used to implement the draft
8858 instead of the final standard. Therefore, aix_struct_return
8859 controls this instead of DEFAULT_ABI; V.4 targets needing backward
8860 compatibility can change DRAFT_V4_STRUCT_RET to override the
8861 default, and -m switches get the final word. See
8862 rs6000_option_override_internal for more details.
8864 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
8865 long double support is enabled. These values are returned in memory.
8867 int_size_in_bytes returns -1 for variable size objects, which go in
8868 memory always. The cast to unsigned makes -1 > 8. */
8871 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
8873 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
8875 && rs6000_darwin64_abi
8876 && TREE_CODE (type
) == RECORD_TYPE
8877 && int_size_in_bytes (type
) > 0)
8879 CUMULATIVE_ARGS valcum
;
8883 valcum
.fregno
= FP_ARG_MIN_REG
;
8884 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
8885 /* Do a trial code generation as if this were going to be passed
8886 as an argument; if any part goes in memory, we return NULL. */
8887 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
8890 /* Otherwise fall through to more conventional ABI rules. */
8893 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
8894 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
8898 /* The ELFv2 ABI returns aggregates up to 16B in registers */
8899 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
8900 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
8903 if (AGGREGATE_TYPE_P (type
)
8904 && (aix_struct_return
8905 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
8908 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8909 modes only exist for GCC vector types if -maltivec. */
8910 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
8911 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
8914 /* Return synthetic vectors in memory. */
8915 if (TREE_CODE (type
) == VECTOR_TYPE
8916 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
8918 static bool warned_for_return_big_vectors
= false;
8919 if (!warned_for_return_big_vectors
)
8921 warning (0, "GCC vector returned by reference: "
8922 "non-standard ABI extension with no compatibility guarantee");
8923 warned_for_return_big_vectors
= true;
8928 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
8934 /* Specify whether values returned in registers should be at the most
8935 significant end of a register. We want aggregates returned by
8936 value to match the way aggregates are passed to functions. */
8939 rs6000_return_in_msb (const_tree valtype
)
8941 return (DEFAULT_ABI
== ABI_ELFv2
8943 && AGGREGATE_TYPE_P (valtype
)
8944 && FUNCTION_ARG_PADDING (TYPE_MODE (valtype
), valtype
) == upward
);
8947 #ifdef HAVE_AS_GNU_ATTRIBUTE
8948 /* Return TRUE if a call to function FNDECL may be one that
8949 potentially affects the function calling ABI of the object file. */
8952 call_ABI_of_interest (tree fndecl
)
8954 if (cgraph_state
== CGRAPH_STATE_EXPANSION
)
8956 struct cgraph_node
*c_node
;
8958 /* Libcalls are always interesting. */
8959 if (fndecl
== NULL_TREE
)
8962 /* Any call to an external function is interesting. */
8963 if (DECL_EXTERNAL (fndecl
))
8966 /* Interesting functions that we are emitting in this object file. */
8967 c_node
= cgraph_get_node (fndecl
);
8968 c_node
= cgraph_function_or_thunk_node (c_node
, NULL
);
8969 return !cgraph_only_called_directly_p (c_node
);
8975 /* Initialize a variable CUM of type CUMULATIVE_ARGS
8976 for a call to a function whose data type is FNTYPE.
8977 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
8979 For incoming args we set the number of arguments in the prototype large
8980 so we never return a PARALLEL. */
8983 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
8984 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
8985 int libcall
, int n_named_args
,
8986 tree fndecl ATTRIBUTE_UNUSED
,
8987 enum machine_mode return_mode ATTRIBUTE_UNUSED
)
8989 static CUMULATIVE_ARGS zero_cumulative
;
8991 *cum
= zero_cumulative
;
8993 cum
->fregno
= FP_ARG_MIN_REG
;
8994 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
8995 cum
->prototype
= (fntype
&& prototype_p (fntype
));
8996 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
8997 ? CALL_LIBCALL
: CALL_NORMAL
);
8998 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
8999 cum
->stdarg
= stdarg_p (fntype
);
9001 cum
->nargs_prototype
= 0;
9002 if (incoming
|| cum
->prototype
)
9003 cum
->nargs_prototype
= n_named_args
;
9005 /* Check for a longcall attribute. */
9006 if ((!fntype
&& rs6000_default_long_calls
)
9008 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
9009 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
9010 cum
->call_cookie
|= CALL_LONG
;
9012 if (TARGET_DEBUG_ARG
)
9014 fprintf (stderr
, "\ninit_cumulative_args:");
9017 tree ret_type
= TREE_TYPE (fntype
);
9018 fprintf (stderr
, " ret code = %s,",
9019 get_tree_code_name (TREE_CODE (ret_type
)));
9022 if (cum
->call_cookie
& CALL_LONG
)
9023 fprintf (stderr
, " longcall,");
9025 fprintf (stderr
, " proto = %d, nargs = %d\n",
9026 cum
->prototype
, cum
->nargs_prototype
);
9029 #ifdef HAVE_AS_GNU_ATTRIBUTE
9030 if (DEFAULT_ABI
== ABI_V4
)
9032 cum
->escapes
= call_ABI_of_interest (fndecl
);
9039 return_type
= TREE_TYPE (fntype
);
9040 return_mode
= TYPE_MODE (return_type
);
9043 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
9045 if (return_type
!= NULL
)
9047 if (TREE_CODE (return_type
) == RECORD_TYPE
9048 && TYPE_TRANSPARENT_AGGR (return_type
))
9050 return_type
= TREE_TYPE (first_field (return_type
));
9051 return_mode
= TYPE_MODE (return_type
);
9053 if (AGGREGATE_TYPE_P (return_type
)
9054 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
9056 rs6000_returns_struct
= true;
9058 if (SCALAR_FLOAT_MODE_P (return_mode
))
9059 rs6000_passes_float
= true;
9060 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
9061 || SPE_VECTOR_MODE (return_mode
))
9062 rs6000_passes_vector
= true;
9069 && TARGET_ALTIVEC_ABI
9070 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
9072 error ("cannot return value in vector register because"
9073 " altivec instructions are disabled, use -maltivec"
9078 /* Return true if TYPE must be passed on the stack and not in registers. */
9081 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
9083 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
9084 return must_pass_in_stack_var_size (mode
, type
);
9086 return must_pass_in_stack_var_size_or_pad (mode
, type
);
9089 /* If defined, a C expression which determines whether, and in which
9090 direction, to pad out an argument with extra space. The value
9091 should be of type `enum direction': either `upward' to pad above
9092 the argument, `downward' to pad below, or `none' to inhibit
9095 For the AIX ABI structs are always stored left shifted in their
9099 function_arg_padding (enum machine_mode mode
, const_tree type
)
9101 #ifndef AGGREGATE_PADDING_FIXED
9102 #define AGGREGATE_PADDING_FIXED 0
9104 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
9105 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
9108 if (!AGGREGATE_PADDING_FIXED
)
9110 /* GCC used to pass structures of the same size as integer types as
9111 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
9112 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
9113 passed padded downward, except that -mstrict-align further
9114 muddied the water in that multi-component structures of 2 and 4
9115 bytes in size were passed padded upward.
9117 The following arranges for best compatibility with previous
9118 versions of gcc, but removes the -mstrict-align dependency. */
9119 if (BYTES_BIG_ENDIAN
)
9121 HOST_WIDE_INT size
= 0;
9123 if (mode
== BLKmode
)
9125 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
9126 size
= int_size_in_bytes (type
);
9129 size
= GET_MODE_SIZE (mode
);
9131 if (size
== 1 || size
== 2 || size
== 4)
9137 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
9139 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
9143 /* Fall back to the default. */
9144 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
9147 /* If defined, a C expression that gives the alignment boundary, in bits,
9148 of an argument with the specified mode and type. If it is not defined,
9149 PARM_BOUNDARY is used for all arguments.
9151 V.4 wants long longs and doubles to be double word aligned. Just
9152 testing the mode size is a boneheaded way to do this as it means
9153 that other types such as complex int are also double word aligned.
9154 However, we're stuck with this because changing the ABI might break
9155 existing library interfaces.
9157 Doubleword align SPE vectors.
9158 Quadword align Altivec/VSX vectors.
9159 Quadword align large synthetic vector types. */
9162 rs6000_function_arg_boundary (enum machine_mode mode
, const_tree type
)
9164 enum machine_mode elt_mode
;
9167 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9169 if (DEFAULT_ABI
== ABI_V4
9170 && (GET_MODE_SIZE (mode
) == 8
9171 || (TARGET_HARD_FLOAT
9173 && (mode
== TFmode
|| mode
== TDmode
))))
9175 else if (SPE_VECTOR_MODE (mode
)
9176 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9177 && int_size_in_bytes (type
) >= 8
9178 && int_size_in_bytes (type
) < 16))
9180 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9181 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9182 && int_size_in_bytes (type
) >= 16))
9184 else if (((TARGET_MACHO
&& rs6000_darwin64_abi
)
9185 || DEFAULT_ABI
== ABI_ELFv2
9186 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
9188 && type
&& TYPE_ALIGN (type
) > 64)
9191 return PARM_BOUNDARY
;
9194 /* The offset in words to the start of the parameter save area. */
9197 rs6000_parm_offset (void)
9199 return (DEFAULT_ABI
== ABI_V4
? 2
9200 : DEFAULT_ABI
== ABI_ELFv2
? 4
9204 /* For a function parm of MODE and TYPE, return the starting word in
9205 the parameter area. NWORDS of the parameter area are already used. */
9208 rs6000_parm_start (enum machine_mode mode
, const_tree type
,
9209 unsigned int nwords
)
9213 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
9214 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
9217 /* Compute the size (in words) of a function argument. */
9219 static unsigned long
9220 rs6000_arg_size (enum machine_mode mode
, const_tree type
)
9224 if (mode
!= BLKmode
)
9225 size
= GET_MODE_SIZE (mode
);
9227 size
= int_size_in_bytes (type
);
9230 return (size
+ 3) >> 2;
9232 return (size
+ 7) >> 3;
9235 /* Use this to flush pending int fields. */
9238 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
9239 HOST_WIDE_INT bitpos
, int final
)
9241 unsigned int startbit
, endbit
;
9242 int intregs
, intoffset
;
9243 enum machine_mode mode
;
9245 /* Handle the situations where a float is taking up the first half
9246 of the GPR, and the other half is empty (typically due to
9247 alignment restrictions). We can detect this by a 8-byte-aligned
9248 int field, or by seeing that this is the final flush for this
9249 argument. Count the word and continue on. */
9250 if (cum
->floats_in_gpr
== 1
9251 && (cum
->intoffset
% 64 == 0
9252 || (cum
->intoffset
== -1 && final
)))
9255 cum
->floats_in_gpr
= 0;
9258 if (cum
->intoffset
== -1)
9261 intoffset
= cum
->intoffset
;
9262 cum
->intoffset
= -1;
9263 cum
->floats_in_gpr
= 0;
9265 if (intoffset
% BITS_PER_WORD
!= 0)
9267 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9269 if (mode
== BLKmode
)
9271 /* We couldn't find an appropriate mode, which happens,
9272 e.g., in packed structs when there are 3 bytes to load.
9273 Back intoffset back to the beginning of the word in this
9275 intoffset
= intoffset
& -BITS_PER_WORD
;
9279 startbit
= intoffset
& -BITS_PER_WORD
;
9280 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9281 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9282 cum
->words
+= intregs
;
9283 /* words should be unsigned. */
9284 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
9286 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
9291 /* The darwin64 ABI calls for us to recurse down through structs,
9292 looking for elements passed in registers. Unfortunately, we have
9293 to track int register count here also because of misalignments
9294 in powerpc alignment mode. */
9297 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
9299 HOST_WIDE_INT startbitpos
)
9303 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9304 if (TREE_CODE (f
) == FIELD_DECL
)
9306 HOST_WIDE_INT bitpos
= startbitpos
;
9307 tree ftype
= TREE_TYPE (f
);
9308 enum machine_mode mode
;
9309 if (ftype
== error_mark_node
)
9311 mode
= TYPE_MODE (ftype
);
9313 if (DECL_SIZE (f
) != 0
9314 && tree_fits_uhwi_p (bit_position (f
)))
9315 bitpos
+= int_bit_position (f
);
9317 /* ??? FIXME: else assume zero offset. */
9319 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9320 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
9321 else if (USE_FP_FOR_ARG_P (cum
, mode
))
9323 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9324 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9325 cum
->fregno
+= n_fpregs
;
9326 /* Single-precision floats present a special problem for
9327 us, because they are smaller than an 8-byte GPR, and so
9328 the structure-packing rules combined with the standard
9329 varargs behavior mean that we want to pack float/float
9330 and float/int combinations into a single register's
9331 space. This is complicated by the arg advance flushing,
9332 which works on arbitrarily large groups of int-type
9336 if (cum
->floats_in_gpr
== 1)
9338 /* Two floats in a word; count the word and reset
9341 cum
->floats_in_gpr
= 0;
9343 else if (bitpos
% 64 == 0)
9345 /* A float at the beginning of an 8-byte word;
9346 count it and put off adjusting cum->words until
9347 we see if a arg advance flush is going to do it
9349 cum
->floats_in_gpr
++;
9353 /* The float is at the end of a word, preceded
9354 by integer fields, so the arg advance flush
9355 just above has already set cum->words and
9356 everything is taken care of. */
9360 cum
->words
+= n_fpregs
;
9362 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9364 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9368 else if (cum
->intoffset
== -1)
9369 cum
->intoffset
= bitpos
;
9373 /* Check for an item that needs to be considered specially under the darwin 64
9374 bit ABI. These are record types where the mode is BLK or the structure is
9377 rs6000_darwin64_struct_check_p (enum machine_mode mode
, const_tree type
)
9379 return rs6000_darwin64_abi
9380 && ((mode
== BLKmode
9381 && TREE_CODE (type
) == RECORD_TYPE
9382 && int_size_in_bytes (type
) > 0)
9383 || (type
&& TREE_CODE (type
) == RECORD_TYPE
9384 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
9387 /* Update the data in CUM to advance over an argument
9388 of mode MODE and data type TYPE.
9389 (TYPE is null for libcalls where that information may not be available.)
9391 Note that for args passed by reference, function_arg will be called
9392 with MODE and TYPE set to that of the pointer to the arg, not the arg
9396 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9397 const_tree type
, bool named
, int depth
)
9399 enum machine_mode elt_mode
;
9402 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9404 /* Only tick off an argument if we're not recursing. */
9406 cum
->nargs_prototype
--;
9408 #ifdef HAVE_AS_GNU_ATTRIBUTE
9409 if (DEFAULT_ABI
== ABI_V4
9412 if (SCALAR_FLOAT_MODE_P (mode
))
9413 rs6000_passes_float
= true;
9414 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
9415 rs6000_passes_vector
= true;
9416 else if (SPE_VECTOR_MODE (mode
)
9418 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9419 rs6000_passes_vector
= true;
9423 if (TARGET_ALTIVEC_ABI
9424 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9425 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9426 && int_size_in_bytes (type
) == 16)))
9430 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
9432 cum
->vregno
+= n_elts
;
9434 if (!TARGET_ALTIVEC
)
9435 error ("cannot pass argument in vector register because"
9436 " altivec instructions are disabled, use -maltivec"
9439 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
9440 even if it is going to be passed in a vector register.
9441 Darwin does the same for variable-argument functions. */
9442 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9444 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
9454 /* Vector parameters must be 16-byte aligned. In 32-bit
9455 mode this means we need to take into account the offset
9456 to the parameter save area. In 64-bit mode, they just
9457 have to start on an even word, since the parameter save
9458 area is 16-byte aligned. */
9460 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
9462 align
= cum
->words
& 1;
9463 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
9465 if (TARGET_DEBUG_ARG
)
9467 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
9469 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
9470 cum
->nargs_prototype
, cum
->prototype
,
9471 GET_MODE_NAME (mode
));
9475 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
9477 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9480 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9482 int size
= int_size_in_bytes (type
);
9483 /* Variable sized types have size == -1 and are
9484 treated as if consisting entirely of ints.
9485 Pad to 16 byte boundary if needed. */
9486 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9487 && (cum
->words
% 2) != 0)
9489 /* For varargs, we can just go up by the size of the struct. */
9491 cum
->words
+= (size
+ 7) / 8;
9494 /* It is tempting to say int register count just goes up by
9495 sizeof(type)/8, but this is wrong in a case such as
9496 { int; double; int; } [powerpc alignment]. We have to
9497 grovel through the fields for these too. */
9499 cum
->floats_in_gpr
= 0;
9500 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
9501 rs6000_darwin64_record_arg_advance_flush (cum
,
9502 size
* BITS_PER_UNIT
, 1);
9504 if (TARGET_DEBUG_ARG
)
9506 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
9507 cum
->words
, TYPE_ALIGN (type
), size
);
9509 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
9510 cum
->nargs_prototype
, cum
->prototype
,
9511 GET_MODE_NAME (mode
));
9514 else if (DEFAULT_ABI
== ABI_V4
)
9516 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9517 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
9518 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
9519 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
9520 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
9522 /* _Decimal128 must use an even/odd register pair. This assumes
9523 that the register number is odd when fregno is odd. */
9524 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9527 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
9528 <= FP_ARG_V4_MAX_REG
)
9529 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
9532 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
9533 if (mode
== DFmode
|| mode
== TFmode
9534 || mode
== DDmode
|| mode
== TDmode
)
9535 cum
->words
+= cum
->words
& 1;
9536 cum
->words
+= rs6000_arg_size (mode
, type
);
9541 int n_words
= rs6000_arg_size (mode
, type
);
9542 int gregno
= cum
->sysv_gregno
;
9544 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
9545 (r7,r8) or (r9,r10). As does any other 2 word item such
9546 as complex int due to a historical mistake. */
9548 gregno
+= (1 - gregno
) & 1;
9550 /* Multi-reg args are not split between registers and stack. */
9551 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9553 /* Long long and SPE vectors are aligned on the stack.
9554 So are other 2 word items such as complex int due to
9555 a historical mistake. */
9557 cum
->words
+= cum
->words
& 1;
9558 cum
->words
+= n_words
;
9561 /* Note: continuing to accumulate gregno past when we've started
9562 spilling to the stack indicates the fact that we've started
9563 spilling to the stack to expand_builtin_saveregs. */
9564 cum
->sysv_gregno
= gregno
+ n_words
;
9567 if (TARGET_DEBUG_ARG
)
9569 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9570 cum
->words
, cum
->fregno
);
9571 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
9572 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
9573 fprintf (stderr
, "mode = %4s, named = %d\n",
9574 GET_MODE_NAME (mode
), named
);
9579 int n_words
= rs6000_arg_size (mode
, type
);
9580 int start_words
= cum
->words
;
9581 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
9583 cum
->words
= align_words
+ n_words
;
9585 if (SCALAR_FLOAT_MODE_P (elt_mode
)
9586 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9588 /* _Decimal128 must be passed in an even/odd float register pair.
9589 This assumes that the register number is odd when fregno is
9591 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9593 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
9596 if (TARGET_DEBUG_ARG
)
9598 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9599 cum
->words
, cum
->fregno
);
9600 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
9601 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
9602 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
9603 named
, align_words
- start_words
, depth
);
9609 rs6000_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
9610 const_tree type
, bool named
)
9612 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
9617 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
9624 r1
= gen_rtx_REG (DImode
, gregno
);
9625 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9626 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
9630 r1
= gen_rtx_REG (DImode
, gregno
);
9631 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9632 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9633 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9634 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
9637 r1
= gen_rtx_REG (DImode
, gregno
);
9638 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9639 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9640 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9641 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
9642 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
9643 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
9644 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
9645 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
9652 /* Determine where to put a SIMD argument on the SPE. */
9654 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9657 int gregno
= cum
->sysv_gregno
;
9659 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
9660 are passed and returned in a pair of GPRs for ABI compatibility. */
9661 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
9662 || mode
== DCmode
|| mode
== TCmode
))
9664 int n_words
= rs6000_arg_size (mode
, type
);
9666 /* Doubles go in an odd/even register pair (r5/r6, etc). */
9668 gregno
+= (1 - gregno
) & 1;
9670 /* Multi-reg args are not split between registers and stack. */
9671 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9674 return spe_build_register_parallel (mode
, gregno
);
9678 int n_words
= rs6000_arg_size (mode
, type
);
9680 /* SPE vectors are put in odd registers. */
9681 if (n_words
== 2 && (gregno
& 1) == 0)
9684 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
9687 enum machine_mode m
= SImode
;
9689 r1
= gen_rtx_REG (m
, gregno
);
9690 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
9691 r2
= gen_rtx_REG (m
, gregno
+ 1);
9692 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
9693 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
9700 if (gregno
<= GP_ARG_MAX_REG
)
9701 return gen_rtx_REG (mode
, gregno
);
9707 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
9708 structure between cum->intoffset and bitpos to integer registers. */
9711 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
9712 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
9714 enum machine_mode mode
;
9716 unsigned int startbit
, endbit
;
9717 int this_regno
, intregs
, intoffset
;
9720 if (cum
->intoffset
== -1)
9723 intoffset
= cum
->intoffset
;
9724 cum
->intoffset
= -1;
9726 /* If this is the trailing part of a word, try to only load that
9727 much into the register. Otherwise load the whole register. Note
9728 that in the latter case we may pick up unwanted bits. It's not a
9729 problem at the moment but may wish to revisit. */
9731 if (intoffset
% BITS_PER_WORD
!= 0)
9733 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9735 if (mode
== BLKmode
)
9737 /* We couldn't find an appropriate mode, which happens,
9738 e.g., in packed structs when there are 3 bytes to load.
9739 Back intoffset back to the beginning of the word in this
9741 intoffset
= intoffset
& -BITS_PER_WORD
;
9748 startbit
= intoffset
& -BITS_PER_WORD
;
9749 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9750 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9751 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
9753 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
9756 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
9760 intoffset
/= BITS_PER_UNIT
;
9763 regno
= GP_ARG_MIN_REG
+ this_regno
;
9764 reg
= gen_rtx_REG (mode
, regno
);
9766 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
9769 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
9773 while (intregs
> 0);
9776 /* Recursive workhorse for the following. */
9779 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
9780 HOST_WIDE_INT startbitpos
, rtx rvec
[],
9785 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9786 if (TREE_CODE (f
) == FIELD_DECL
)
9788 HOST_WIDE_INT bitpos
= startbitpos
;
9789 tree ftype
= TREE_TYPE (f
);
9790 enum machine_mode mode
;
9791 if (ftype
== error_mark_node
)
9793 mode
= TYPE_MODE (ftype
);
9795 if (DECL_SIZE (f
) != 0
9796 && tree_fits_uhwi_p (bit_position (f
)))
9797 bitpos
+= int_bit_position (f
);
9799 /* ??? FIXME: else assume zero offset. */
9801 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9802 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
9803 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
9805 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9809 case SCmode
: mode
= SFmode
; break;
9810 case DCmode
: mode
= DFmode
; break;
9811 case TCmode
: mode
= TFmode
; break;
9815 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9816 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
9818 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
9819 && (mode
== TFmode
|| mode
== TDmode
));
9820 /* Long double or _Decimal128 split over regs and memory. */
9821 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
9825 = gen_rtx_EXPR_LIST (VOIDmode
,
9826 gen_rtx_REG (mode
, cum
->fregno
++),
9827 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9828 if (mode
== TFmode
|| mode
== TDmode
)
9831 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9833 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9835 = gen_rtx_EXPR_LIST (VOIDmode
,
9836 gen_rtx_REG (mode
, cum
->vregno
++),
9837 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9839 else if (cum
->intoffset
== -1)
9840 cum
->intoffset
= bitpos
;
9844 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
9845 the register(s) to be used for each field and subfield of a struct
9846 being passed by value, along with the offset of where the
9847 register's value may be found in the block. FP fields go in FP
9848 register, vector fields go in vector registers, and everything
9849 else goes in int registers, packed as in memory.
9851 This code is also used for function return values. RETVAL indicates
9852 whether this is the case.
9854 Much of this is taken from the SPARC V9 port, which has a similar
9855 calling convention. */
9858 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
9859 bool named
, bool retval
)
9861 rtx rvec
[FIRST_PSEUDO_REGISTER
];
9862 int k
= 1, kbase
= 1;
9863 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
9864 /* This is a copy; modifications are not visible to our caller. */
9865 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
9866 CUMULATIVE_ARGS
*cum
= ©_cum
;
9868 /* Pad to 16 byte boundary if needed. */
9869 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9870 && (cum
->words
% 2) != 0)
9877 /* Put entries into rvec[] for individual FP and vector fields, and
9878 for the chunks of memory that go in int regs. Note we start at
9879 element 1; 0 is reserved for an indication of using memory, and
9880 may or may not be filled in below. */
9881 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
9882 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
9884 /* If any part of the struct went on the stack put all of it there.
9885 This hack is because the generic code for
9886 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
9887 parts of the struct are not at the beginning. */
9891 return NULL_RTX
; /* doesn't go in registers at all */
9893 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9895 if (k
> 1 || cum
->use_stack
)
9896 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
9901 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
9904 rs6000_mixed_function_arg (enum machine_mode mode
, const_tree type
,
9909 rtx rvec
[GP_ARG_NUM_REG
+ 1];
9911 if (align_words
>= GP_ARG_NUM_REG
)
9914 n_units
= rs6000_arg_size (mode
, type
);
9916 /* Optimize the simple case where the arg fits in one gpr, except in
9917 the case of BLKmode due to assign_parms assuming that registers are
9918 BITS_PER_WORD wide. */
9920 || (n_units
== 1 && mode
!= BLKmode
))
9921 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9924 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
9925 /* Not all of the arg fits in gprs. Say that it goes in memory too,
9926 using a magic NULL_RTX component.
9927 This is not strictly correct. Only some of the arg belongs in
9928 memory, not all of it. However, the normal scheme using
9929 function_arg_partial_nregs can result in unusual subregs, eg.
9930 (subreg:SI (reg:DF) 4), which are not handled well. The code to
9931 store the whole arg to memory is often more efficient than code
9932 to store pieces, and we know that space is available in the right
9933 place for the whole arg. */
9934 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9939 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
9940 rtx off
= GEN_INT (i
++ * 4);
9941 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9943 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
9945 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9948 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
9949 but must also be copied into the parameter save area starting at
9950 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
9951 to the GPRs and/or memory. Return the number of elements used. */
9954 rs6000_psave_function_arg (enum machine_mode mode
, const_tree type
,
9955 int align_words
, rtx
*rvec
)
9959 if (align_words
< GP_ARG_NUM_REG
)
9961 int n_words
= rs6000_arg_size (mode
, type
);
9963 if (align_words
+ n_words
> GP_ARG_NUM_REG
9965 || (TARGET_32BIT
&& TARGET_POWERPC64
))
9967 /* If this is partially on the stack, then we only
9968 include the portion actually in registers here. */
9969 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
9972 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
9974 /* Not all of the arg fits in gprs. Say that it goes in memory
9975 too, using a magic NULL_RTX component. Also see comment in
9976 rs6000_mixed_function_arg for why the normal
9977 function_arg_partial_nregs scheme doesn't work in this case. */
9978 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9983 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
9984 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
9985 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9987 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
9991 /* The whole arg fits in gprs. */
9992 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9993 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
9998 /* It's entirely in memory. */
9999 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10005 /* RVEC is a vector of K components of an argument of mode MODE.
10006 Construct the final function_arg return value from it. */
10009 rs6000_finish_function_arg (enum machine_mode mode
, rtx
*rvec
, int k
)
10011 gcc_assert (k
>= 1);
10013 /* Avoid returning a PARALLEL in the trivial cases. */
10016 if (XEXP (rvec
[0], 0) == NULL_RTX
)
10019 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
10020 return XEXP (rvec
[0], 0);
10023 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
10026 /* Determine where to put an argument to a function.
10027 Value is zero to push the argument on the stack,
10028 or a hard register in which to store the argument.
10030 MODE is the argument's machine mode.
10031 TYPE is the data type of the argument (as a tree).
10032 This is null for libcalls where that information may
10034 CUM is a variable of type CUMULATIVE_ARGS which gives info about
10035 the preceding args and about the function being called. It is
10036 not modified in this routine.
10037 NAMED is nonzero if this argument is a named parameter
10038 (otherwise it is an extra parameter matching an ellipsis).
10040 On RS/6000 the first eight words of non-FP are normally in registers
10041 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
10042 Under V.4, the first 8 FP args are in registers.
10044 If this is floating-point and no prototype is specified, we use
10045 both an FP and integer register (or possibly FP reg and stack). Library
10046 functions (when CALL_LIBCALL is set) always have the proper types for args,
10047 so we can pass the FP value just in one register. emit_library_function
10048 doesn't support PARALLEL anyway.
10050 Note that for args passed by reference, function_arg will be called
10051 with MODE and TYPE set to that of the pointer to the arg, not the arg
10055 rs6000_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
10056 const_tree type
, bool named
)
10058 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10059 enum rs6000_abi abi
= DEFAULT_ABI
;
10060 enum machine_mode elt_mode
;
10063 /* Return a marker to indicate whether CR1 needs to set or clear the
10064 bit that V.4 uses to say fp args were passed in registers.
10065 Assume that we don't need the marker for software floating point,
10066 or compiler generated library calls. */
10067 if (mode
== VOIDmode
)
10070 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
10072 || (cum
->nargs_prototype
< 0
10073 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
10075 /* For the SPE, we need to crxor CR6 always. */
10076 if (TARGET_SPE_ABI
)
10077 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
10078 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
10079 return GEN_INT (cum
->call_cookie
10080 | ((cum
->fregno
== FP_ARG_MIN_REG
)
10081 ? CALL_V4_SET_FP_ARGS
10082 : CALL_V4_CLEAR_FP_ARGS
));
10085 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
10088 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10090 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10092 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
10093 if (rslt
!= NULL_RTX
)
10095 /* Else fall through to usual handling. */
10098 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10100 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10104 /* Do we also need to pass this argument in the parameter
10106 if (TARGET_64BIT
&& ! cum
->prototype
)
10108 int align_words
= (cum
->words
+ 1) & ~1;
10109 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10112 /* Describe where this argument goes in the vector registers. */
10113 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
10115 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
10116 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10117 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10120 return rs6000_finish_function_arg (mode
, rvec
, k
);
10122 else if (TARGET_ALTIVEC_ABI
10123 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
10124 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
10125 && int_size_in_bytes (type
) == 16)))
10127 if (named
|| abi
== ABI_V4
)
10131 /* Vector parameters to varargs functions under AIX or Darwin
10132 get passed in memory and possibly also in GPRs. */
10133 int align
, align_words
, n_words
;
10134 enum machine_mode part_mode
;
10136 /* Vector parameters must be 16-byte aligned. In 32-bit
10137 mode this means we need to take into account the offset
10138 to the parameter save area. In 64-bit mode, they just
10139 have to start on an even word, since the parameter save
10140 area is 16-byte aligned. */
10142 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
10144 align
= cum
->words
& 1;
10145 align_words
= cum
->words
+ align
;
10147 /* Out of registers? Memory, then. */
10148 if (align_words
>= GP_ARG_NUM_REG
)
10151 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10152 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10154 /* The vector value goes in GPRs. Only the part of the
10155 value in GPRs is reported here. */
10157 n_words
= rs6000_arg_size (mode
, type
);
10158 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
10159 /* Fortunately, there are only two possibilities, the value
10160 is either wholly in GPRs or half in GPRs and half not. */
10161 part_mode
= DImode
;
10163 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
10166 else if (TARGET_SPE_ABI
&& TARGET_SPE
10167 && (SPE_VECTOR_MODE (mode
)
10168 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
10171 || mode
== TCmode
))))
10172 return rs6000_spe_function_arg (cum
, mode
, type
);
10174 else if (abi
== ABI_V4
)
10176 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10177 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
10178 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
10179 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
10180 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
10182 /* _Decimal128 must use an even/odd register pair. This assumes
10183 that the register number is odd when fregno is odd. */
10184 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10187 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
10188 <= FP_ARG_V4_MAX_REG
)
10189 return gen_rtx_REG (mode
, cum
->fregno
);
10195 int n_words
= rs6000_arg_size (mode
, type
);
10196 int gregno
= cum
->sysv_gregno
;
10198 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
10199 (r7,r8) or (r9,r10). As does any other 2 word item such
10200 as complex int due to a historical mistake. */
10202 gregno
+= (1 - gregno
) & 1;
10204 /* Multi-reg args are not split between registers and stack. */
10205 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10208 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10209 return rs6000_mixed_function_arg (mode
, type
,
10210 gregno
- GP_ARG_MIN_REG
);
10211 return gen_rtx_REG (mode
, gregno
);
10216 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10218 /* _Decimal128 must be passed in an even/odd float register pair.
10219 This assumes that the register number is odd when fregno is odd. */
10220 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10223 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10225 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10228 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10230 /* Do we also need to pass this argument in the parameter
10232 if (type
&& (cum
->nargs_prototype
<= 0
10233 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10234 && TARGET_XL_COMPAT
10235 && align_words
>= GP_ARG_NUM_REG
)))
10236 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10238 /* Describe where this argument goes in the fprs. */
10239 for (i
= 0; i
< n_elts
10240 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
10242 /* Check if the argument is split over registers and memory.
10243 This can only ever happen for long double or _Decimal128;
10244 complex types are handled via split_complex_arg. */
10245 enum machine_mode fmode
= elt_mode
;
10246 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
10248 gcc_assert (fmode
== TFmode
|| fmode
== TDmode
);
10249 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
10252 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
10253 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10254 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10257 return rs6000_finish_function_arg (mode
, rvec
, k
);
10259 else if (align_words
< GP_ARG_NUM_REG
)
10261 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10262 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10264 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10271 /* For an arg passed partly in registers and partly in memory, this is
10272 the number of bytes passed in registers. For args passed entirely in
10273 registers or entirely in memory, zero. When an arg is described by a
10274 PARALLEL, perhaps using more than one register type, this function
10275 returns the number of bytes used by the first element of the PARALLEL. */
10278 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
10279 tree type
, bool named
)
10281 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10282 bool passed_in_gprs
= true;
10285 enum machine_mode elt_mode
;
10288 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10290 if (DEFAULT_ABI
== ABI_V4
)
10293 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10295 /* If we are passing this arg in the fixed parameter save area
10296 (gprs or memory) as well as VRs, we do not use the partial
10297 bytes mechanism; instead, rs6000_function_arg will return a
10298 PARALLEL including a memory element as necessary. */
10299 if (TARGET_64BIT
&& ! cum
->prototype
)
10302 /* Otherwise, we pass in VRs only. Check for partial copies. */
10303 passed_in_gprs
= false;
10304 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
10305 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
10308 /* In this complicated case we just disable the partial_nregs code. */
10309 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10312 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10314 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10316 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10318 /* If we are passing this arg in the fixed parameter save area
10319 (gprs or memory) as well as FPRs, we do not use the partial
10320 bytes mechanism; instead, rs6000_function_arg will return a
10321 PARALLEL including a memory element as necessary. */
10323 && (cum
->nargs_prototype
<= 0
10324 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10325 && TARGET_XL_COMPAT
10326 && align_words
>= GP_ARG_NUM_REG
)))
10329 /* Otherwise, we pass in FPRs only. Check for partial copies. */
10330 passed_in_gprs
= false;
10331 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
10332 ret
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
10333 * MIN (8, GET_MODE_SIZE (elt_mode
)));
10337 && align_words
< GP_ARG_NUM_REG
10338 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
10339 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
10341 if (ret
!= 0 && TARGET_DEBUG_ARG
)
10342 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
10347 /* A C expression that indicates when an argument must be passed by
10348 reference. If nonzero for an argument, a copy of that argument is
10349 made in memory and a pointer to the argument is passed instead of
10350 the argument itself. The pointer is passed in whatever way is
10351 appropriate for passing a pointer to that type.
10353 Under V.4, aggregates and long double are passed by reference.
10355 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
10356 reference unless the AltiVec vector extension ABI is in force.
10358 As an extension to all ABIs, variable sized types are passed by
10362 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
10363 enum machine_mode mode
, const_tree type
,
10364 bool named ATTRIBUTE_UNUSED
)
10366 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
10368 if (TARGET_DEBUG_ARG
)
10369 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
10376 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
10378 if (TARGET_DEBUG_ARG
)
10379 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
10383 if (int_size_in_bytes (type
) < 0)
10385 if (TARGET_DEBUG_ARG
)
10386 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
10390 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10391 modes only exist for GCC vector types if -maltivec. */
10392 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
10394 if (TARGET_DEBUG_ARG
)
10395 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
10399 /* Pass synthetic vectors in memory. */
10400 if (TREE_CODE (type
) == VECTOR_TYPE
10401 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
10403 static bool warned_for_pass_big_vectors
= false;
10404 if (TARGET_DEBUG_ARG
)
10405 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
10406 if (!warned_for_pass_big_vectors
)
10408 warning (0, "GCC vector passed by reference: "
10409 "non-standard ABI extension with no compatibility guarantee");
10410 warned_for_pass_big_vectors
= true;
10418 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
10419 already processes. Return true if the parameter must be passed
10420 (fully or partially) on the stack. */
10423 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
10425 enum machine_mode mode
;
10429 /* Catch errors. */
10430 if (type
== NULL
|| type
== error_mark_node
)
10433 /* Handle types with no storage requirement. */
10434 if (TYPE_MODE (type
) == VOIDmode
)
10437 /* Handle complex types. */
10438 if (TREE_CODE (type
) == COMPLEX_TYPE
)
10439 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
10440 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
10442 /* Handle transparent aggregates. */
10443 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
10444 && TYPE_TRANSPARENT_AGGR (type
))
10445 type
= TREE_TYPE (first_field (type
));
10447 /* See if this arg was passed by invisible reference. */
10448 if (pass_by_reference (get_cumulative_args (args_so_far
),
10449 TYPE_MODE (type
), type
, true))
10450 type
= build_pointer_type (type
);
10452 /* Find mode as it is passed by the ABI. */
10453 unsignedp
= TYPE_UNSIGNED (type
);
10454 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
10456 /* If we must pass in stack, we need a stack. */
10457 if (rs6000_must_pass_in_stack (mode
, type
))
10460 /* If there is no incoming register, we need a stack. */
10461 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
10462 if (entry_parm
== NULL
)
10465 /* Likewise if we need to pass both in registers and on the stack. */
10466 if (GET_CODE (entry_parm
) == PARALLEL
10467 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
10470 /* Also true if we're partially in registers and partially not. */
10471 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
10474 /* Update info on where next arg arrives in registers. */
10475 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
10479 /* Return true if FUN has no prototype, has a variable argument
10480 list, or passes any parameter in memory. */
10483 rs6000_function_parms_need_stack (tree fun
, bool incoming
)
10485 tree fntype
, result
;
10486 CUMULATIVE_ARGS args_so_far_v
;
10487 cumulative_args_t args_so_far
;
10490 /* Must be a libcall, all of which only use reg parms. */
10495 fntype
= TREE_TYPE (fun
);
10497 /* Varargs functions need the parameter save area. */
10498 if ((!incoming
&& !prototype_p (fntype
)) || stdarg_p (fntype
))
10501 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fntype
, NULL_RTX
);
10502 args_so_far
= pack_cumulative_args (&args_so_far_v
);
10504 /* When incoming, we will have been passed the function decl.
10505 It is necessary to use the decl to handle K&R style functions,
10506 where TYPE_ARG_TYPES may not be available. */
10509 gcc_assert (DECL_P (fun
));
10510 result
= DECL_RESULT (fun
);
10513 result
= TREE_TYPE (fntype
);
10515 if (result
&& aggregate_value_p (result
, fntype
))
10517 if (!TYPE_P (result
))
10518 result
= TREE_TYPE (result
);
10519 result
= build_pointer_type (result
);
10520 rs6000_parm_needs_stack (args_so_far
, result
);
10527 for (parm
= DECL_ARGUMENTS (fun
);
10528 parm
&& parm
!= void_list_node
;
10529 parm
= TREE_CHAIN (parm
))
10530 if (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (parm
)))
10535 function_args_iterator args_iter
;
10538 FOREACH_FUNCTION_ARGS (fntype
, arg_type
, args_iter
)
10539 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
10546 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
10547 usually a constant depending on the ABI. However, in the ELFv2 ABI
10548 the register parameter area is optional when calling a function that
10549 has a prototype is scope, has no variable argument list, and passes
10550 all parameters in registers. */
10553 rs6000_reg_parm_stack_space (tree fun
, bool incoming
)
10555 int reg_parm_stack_space
;
10557 switch (DEFAULT_ABI
)
10560 reg_parm_stack_space
= 0;
10565 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10569 /* ??? Recomputing this every time is a bit expensive. Is there
10570 a place to cache this information? */
10571 if (rs6000_function_parms_need_stack (fun
, incoming
))
10572 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10574 reg_parm_stack_space
= 0;
10578 return reg_parm_stack_space
;
10582 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
10585 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
10590 for (i
= 0; i
< nregs
; i
++)
10592 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
10593 if (reload_completed
)
10595 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
10598 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
10599 i
* GET_MODE_SIZE (reg_mode
));
10602 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
10606 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
10610 /* Perform any needed actions needed for a function that is receiving a
10611 variable number of arguments.
10615 MODE and TYPE are the mode and type of the current parameter.
10617 PRETEND_SIZE is a variable that should be set to the amount of stack
10618 that must be pushed by the prolog to pretend that our caller pushed
10621 Normally, this macro will push all remaining incoming registers on the
10622 stack and set PRETEND_SIZE to the length of the registers pushed. */
10625 setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
10626 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
10629 CUMULATIVE_ARGS next_cum
;
10630 int reg_size
= TARGET_32BIT
? 4 : 8;
10631 rtx save_area
= NULL_RTX
, mem
;
10632 int first_reg_offset
;
10633 alias_set_type set
;
10635 /* Skip the last named argument. */
10636 next_cum
= *get_cumulative_args (cum
);
10637 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
10639 if (DEFAULT_ABI
== ABI_V4
)
10641 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
10645 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
10646 HOST_WIDE_INT offset
= 0;
10648 /* Try to optimize the size of the varargs save area.
10649 The ABI requires that ap.reg_save_area is doubleword
10650 aligned, but we don't need to allocate space for all
10651 the bytes, only those to which we actually will save
10653 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
10654 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
10655 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10656 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10657 && cfun
->va_list_fpr_size
)
10660 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
10661 * UNITS_PER_FP_WORD
;
10662 if (cfun
->va_list_fpr_size
10663 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10664 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
10666 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10667 * UNITS_PER_FP_WORD
;
10671 offset
= -((first_reg_offset
* reg_size
) & ~7);
10672 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
10674 gpr_reg_num
= cfun
->va_list_gpr_size
;
10675 if (reg_size
== 4 && (first_reg_offset
& 1))
10678 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
10681 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
10682 * UNITS_PER_FP_WORD
10683 - (int) (GP_ARG_NUM_REG
* reg_size
);
10685 if (gpr_size
+ fpr_size
)
10688 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
10689 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
10690 reg_save_area
= XEXP (reg_save_area
, 0);
10691 if (GET_CODE (reg_save_area
) == PLUS
)
10693 gcc_assert (XEXP (reg_save_area
, 0)
10694 == virtual_stack_vars_rtx
);
10695 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
10696 offset
+= INTVAL (XEXP (reg_save_area
, 1));
10699 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
10702 cfun
->machine
->varargs_save_offset
= offset
;
10703 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
10708 first_reg_offset
= next_cum
.words
;
10709 save_area
= virtual_incoming_args_rtx
;
10711 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
10712 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
10715 set
= get_varargs_alias_set ();
10716 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
10717 && cfun
->va_list_gpr_size
)
10719 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
10721 if (va_list_gpr_counter_field
)
10722 /* V4 va_list_gpr_size counts number of registers needed. */
10723 n_gpr
= cfun
->va_list_gpr_size
;
10725 /* char * va_list instead counts number of bytes needed. */
10726 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
10731 mem
= gen_rtx_MEM (BLKmode
,
10732 plus_constant (Pmode
, save_area
,
10733 first_reg_offset
* reg_size
));
10734 MEM_NOTRAP_P (mem
) = 1;
10735 set_mem_alias_set (mem
, set
);
10736 set_mem_align (mem
, BITS_PER_WORD
);
10738 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
10742 /* Save FP registers if needed. */
10743 if (DEFAULT_ABI
== ABI_V4
10744 && TARGET_HARD_FLOAT
&& TARGET_FPRS
10746 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10747 && cfun
->va_list_fpr_size
)
10749 int fregno
= next_cum
.fregno
, nregs
;
10750 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
10751 rtx lab
= gen_label_rtx ();
10752 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
10753 * UNITS_PER_FP_WORD
);
10756 (gen_rtx_SET (VOIDmode
,
10758 gen_rtx_IF_THEN_ELSE (VOIDmode
,
10759 gen_rtx_NE (VOIDmode
, cr1
,
10761 gen_rtx_LABEL_REF (VOIDmode
, lab
),
10765 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
10766 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
10768 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10770 plus_constant (Pmode
, save_area
, off
));
10771 MEM_NOTRAP_P (mem
) = 1;
10772 set_mem_alias_set (mem
, set
);
10773 set_mem_align (mem
, GET_MODE_ALIGNMENT (
10774 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10775 ? DFmode
: SFmode
));
10776 emit_move_insn (mem
, gen_rtx_REG (
10777 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10778 ? DFmode
: SFmode
, fregno
));
10785 /* Create the va_list data type. */
10788 rs6000_build_builtin_va_list (void)
10790 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
10792 /* For AIX, prefer 'char *' because that's what the system
10793 header files like. */
10794 if (DEFAULT_ABI
!= ABI_V4
)
10795 return build_pointer_type (char_type_node
);
10797 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
10798 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
10799 get_identifier ("__va_list_tag"), record
);
10801 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
10802 unsigned_char_type_node
);
10803 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
10804 unsigned_char_type_node
);
10805 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
10806 every user file. */
10807 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10808 get_identifier ("reserved"), short_unsigned_type_node
);
10809 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10810 get_identifier ("overflow_arg_area"),
10812 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10813 get_identifier ("reg_save_area"),
10816 va_list_gpr_counter_field
= f_gpr
;
10817 va_list_fpr_counter_field
= f_fpr
;
10819 DECL_FIELD_CONTEXT (f_gpr
) = record
;
10820 DECL_FIELD_CONTEXT (f_fpr
) = record
;
10821 DECL_FIELD_CONTEXT (f_res
) = record
;
10822 DECL_FIELD_CONTEXT (f_ovf
) = record
;
10823 DECL_FIELD_CONTEXT (f_sav
) = record
;
10825 TYPE_STUB_DECL (record
) = type_decl
;
10826 TYPE_NAME (record
) = type_decl
;
10827 TYPE_FIELDS (record
) = f_gpr
;
10828 DECL_CHAIN (f_gpr
) = f_fpr
;
10829 DECL_CHAIN (f_fpr
) = f_res
;
10830 DECL_CHAIN (f_res
) = f_ovf
;
10831 DECL_CHAIN (f_ovf
) = f_sav
;
10833 layout_type (record
);
10835 /* The correct type is an array type of one element. */
10836 return build_array_type (record
, build_index_type (size_zero_node
));
10839 /* Implement va_start. */
10842 rs6000_va_start (tree valist
, rtx nextarg
)
10844 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
10845 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10846 tree gpr
, fpr
, ovf
, sav
, t
;
10848 /* Only SVR4 needs something special. */
10849 if (DEFAULT_ABI
!= ABI_V4
)
10851 std_expand_builtin_va_start (valist
, nextarg
);
10855 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
10856 f_fpr
= DECL_CHAIN (f_gpr
);
10857 f_res
= DECL_CHAIN (f_fpr
);
10858 f_ovf
= DECL_CHAIN (f_res
);
10859 f_sav
= DECL_CHAIN (f_ovf
);
10861 valist
= build_simple_mem_ref (valist
);
10862 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
10863 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
10865 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
10867 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
10870 /* Count number of gp and fp argument registers used. */
10871 words
= crtl
->args
.info
.words
;
10872 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
10874 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
10877 if (TARGET_DEBUG_ARG
)
10878 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
10879 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
10880 words
, n_gpr
, n_fpr
);
10882 if (cfun
->va_list_gpr_size
)
10884 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
10885 build_int_cst (NULL_TREE
, n_gpr
));
10886 TREE_SIDE_EFFECTS (t
) = 1;
10887 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10890 if (cfun
->va_list_fpr_size
)
10892 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
10893 build_int_cst (NULL_TREE
, n_fpr
));
10894 TREE_SIDE_EFFECTS (t
) = 1;
10895 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10897 #ifdef HAVE_AS_GNU_ATTRIBUTE
10898 if (call_ABI_of_interest (cfun
->decl
))
10899 rs6000_passes_float
= true;
10903 /* Find the overflow area. */
10904 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
10906 t
= fold_build_pointer_plus_hwi (t
, words
* UNITS_PER_WORD
);
10907 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
10908 TREE_SIDE_EFFECTS (t
) = 1;
10909 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10911 /* If there were no va_arg invocations, don't set up the register
10913 if (!cfun
->va_list_gpr_size
10914 && !cfun
->va_list_fpr_size
10915 && n_gpr
< GP_ARG_NUM_REG
10916 && n_fpr
< FP_ARG_V4_MAX_REG
)
10919 /* Find the register save area. */
10920 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
10921 if (cfun
->machine
->varargs_save_offset
)
10922 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
10923 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
10924 TREE_SIDE_EFFECTS (t
) = 1;
10925 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10928 /* Implement va_arg. */
10931 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
10932 gimple_seq
*post_p
)
10934 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10935 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
10936 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
10937 tree lab_false
, lab_over
, addr
;
10939 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
10943 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
10945 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
10946 return build_va_arg_indirect_ref (t
);
10949 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
10950 earlier version of gcc, with the property that it always applied alignment
10951 adjustments to the va-args (even for zero-sized types). The cheapest way
10952 to deal with this is to replicate the effect of the part of
10953 std_gimplify_va_arg_expr that carries out the align adjust, for the case
10955 We don't need to check for pass-by-reference because of the test above.
10956 We can return a simplifed answer, since we know there's no offset to add. */
10959 && rs6000_darwin64_abi
)
10960 || DEFAULT_ABI
== ABI_ELFv2
10961 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
10962 && integer_zerop (TYPE_SIZE (type
)))
10964 unsigned HOST_WIDE_INT align
, boundary
;
10965 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
10966 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
10967 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
10968 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
10969 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
10970 boundary
/= BITS_PER_UNIT
;
10971 if (boundary
> align
)
10974 /* This updates arg ptr by the amount that would be necessary
10975 to align the zero-sized (but not zero-alignment) item. */
10976 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10977 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
10978 gimplify_and_add (t
, pre_p
);
10980 t
= fold_convert (sizetype
, valist_tmp
);
10981 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10982 fold_convert (TREE_TYPE (valist
),
10983 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
10984 size_int (-boundary
))));
10985 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
10986 gimplify_and_add (t
, pre_p
);
10988 /* Since it is zero-sized there's no increment for the item itself. */
10989 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
10990 return build_va_arg_indirect_ref (valist_tmp
);
10993 if (DEFAULT_ABI
!= ABI_V4
)
10995 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
10997 tree elem_type
= TREE_TYPE (type
);
10998 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
10999 int elem_size
= GET_MODE_SIZE (elem_mode
);
11001 if (elem_size
< UNITS_PER_WORD
)
11003 tree real_part
, imag_part
;
11004 gimple_seq post
= NULL
;
11006 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
11008 /* Copy the value into a temporary, lest the formal temporary
11009 be reused out from under us. */
11010 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
11011 gimple_seq_add_seq (pre_p
, post
);
11013 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
11016 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
11020 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
11023 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
11024 f_fpr
= DECL_CHAIN (f_gpr
);
11025 f_res
= DECL_CHAIN (f_fpr
);
11026 f_ovf
= DECL_CHAIN (f_res
);
11027 f_sav
= DECL_CHAIN (f_ovf
);
11029 valist
= build_va_arg_indirect_ref (valist
);
11030 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11031 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
11033 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
11035 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
11038 size
= int_size_in_bytes (type
);
11039 rsize
= (size
+ 3) / 4;
11042 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
11043 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
11044 || (TARGET_DOUBLE_FLOAT
11045 && (TYPE_MODE (type
) == DFmode
11046 || TYPE_MODE (type
) == TFmode
11047 || TYPE_MODE (type
) == SDmode
11048 || TYPE_MODE (type
) == DDmode
11049 || TYPE_MODE (type
) == TDmode
))))
11051 /* FP args go in FP registers, if present. */
11053 n_reg
= (size
+ 7) / 8;
11054 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
11055 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
11056 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
11061 /* Otherwise into GP registers. */
11070 /* Pull the value out of the saved registers.... */
11073 addr
= create_tmp_var (ptr_type_node
, "addr");
11075 /* AltiVec vectors never go in registers when -mabi=altivec. */
11076 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
11080 lab_false
= create_artificial_label (input_location
);
11081 lab_over
= create_artificial_label (input_location
);
11083 /* Long long and SPE vectors are aligned in the registers.
11084 As are any other 2 gpr item such as complex int due to a
11085 historical mistake. */
11087 if (n_reg
== 2 && reg
== gpr
)
11090 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11091 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
11092 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
11093 unshare_expr (reg
), u
);
11095 /* _Decimal128 is passed in even/odd fpr pairs; the stored
11096 reg number is 0 for f1, so we want to make it odd. */
11097 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
11099 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11100 build_int_cst (TREE_TYPE (reg
), 1));
11101 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
11104 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
11105 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
11106 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
11107 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
11108 gimplify_and_add (t
, pre_p
);
11112 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
11114 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11115 build_int_cst (TREE_TYPE (reg
), n_reg
));
11116 u
= fold_convert (sizetype
, u
);
11117 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
11118 t
= fold_build_pointer_plus (t
, u
);
11120 /* _Decimal32 varargs are located in the second word of the 64-bit
11121 FP register for 32-bit binaries. */
11122 if (!TARGET_POWERPC64
11123 && TARGET_HARD_FLOAT
&& TARGET_FPRS
11124 && TYPE_MODE (type
) == SDmode
)
11125 t
= fold_build_pointer_plus_hwi (t
, size
);
11127 gimplify_assign (addr
, t
, pre_p
);
11129 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
11131 stmt
= gimple_build_label (lab_false
);
11132 gimple_seq_add_stmt (pre_p
, stmt
);
11134 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
11136 /* Ensure that we don't find any more args in regs.
11137 Alignment has taken care of for special cases. */
11138 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
11142 /* ... otherwise out of the overflow area. */
11144 /* Care for on-stack alignment if needed. */
11148 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
11149 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
11150 build_int_cst (TREE_TYPE (t
), -align
));
11152 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
11154 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
11156 t
= fold_build_pointer_plus_hwi (t
, size
);
11157 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
11161 stmt
= gimple_build_label (lab_over
);
11162 gimple_seq_add_stmt (pre_p
, stmt
);
11165 if (STRICT_ALIGNMENT
11166 && (TYPE_ALIGN (type
)
11167 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
11169 /* The value (of type complex double, for example) may not be
11170 aligned in memory in the saved registers, so copy via a
11171 temporary. (This is the same code as used for SPARC.) */
11172 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
11173 tree dest_addr
= build_fold_addr_expr (tmp
);
11175 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
11176 3, dest_addr
, addr
, size_int (rsize
* 4));
11178 gimplify_and_add (copy
, pre_p
);
11182 addr
= fold_convert (ptrtype
, addr
);
11183 return build_va_arg_indirect_ref (addr
);
11189 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
11192 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
11193 const char *attr_string
= "";
11195 gcc_assert (name
!= NULL
);
11196 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
11198 if (rs6000_builtin_decls
[(int)code
])
11199 fatal_error ("internal error: builtin function %s already processed", name
);
11201 rs6000_builtin_decls
[(int)code
] = t
=
11202 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
11204 /* Set any special attributes. */
11205 if ((classify
& RS6000_BTC_CONST
) != 0)
11207 /* const function, function only depends on the inputs. */
11208 TREE_READONLY (t
) = 1;
11209 TREE_NOTHROW (t
) = 1;
11210 attr_string
= ", pure";
11212 else if ((classify
& RS6000_BTC_PURE
) != 0)
11214 /* pure function, function can read global memory, but does not set any
11216 DECL_PURE_P (t
) = 1;
11217 TREE_NOTHROW (t
) = 1;
11218 attr_string
= ", const";
11220 else if ((classify
& RS6000_BTC_FP
) != 0)
11222 /* Function is a math function. If rounding mode is on, then treat the
11223 function as not reading global memory, but it can have arbitrary side
11224 effects. If it is off, then assume the function is a const function.
11225 This mimics the ATTR_MATHFN_FPROUNDING attribute in
11226 builtin-attribute.def that is used for the math functions. */
11227 TREE_NOTHROW (t
) = 1;
11228 if (flag_rounding_math
)
11230 DECL_PURE_P (t
) = 1;
11231 DECL_IS_NOVOPS (t
) = 1;
11232 attr_string
= ", fp, pure";
11236 TREE_READONLY (t
) = 1;
11237 attr_string
= ", fp, const";
11240 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
11241 gcc_unreachable ();
11243 if (TARGET_DEBUG_BUILTIN
)
11244 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
11245 (int)code
, name
, attr_string
);
11248 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
11250 #undef RS6000_BUILTIN_1
11251 #undef RS6000_BUILTIN_2
11252 #undef RS6000_BUILTIN_3
11253 #undef RS6000_BUILTIN_A
11254 #undef RS6000_BUILTIN_D
11255 #undef RS6000_BUILTIN_E
11256 #undef RS6000_BUILTIN_H
11257 #undef RS6000_BUILTIN_P
11258 #undef RS6000_BUILTIN_Q
11259 #undef RS6000_BUILTIN_S
11260 #undef RS6000_BUILTIN_X
11262 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11263 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11264 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
11265 { MASK, ICODE, NAME, ENUM },
11267 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11268 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11269 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11270 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11271 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11272 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11273 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11274 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11276 static const struct builtin_description bdesc_3arg
[] =
11278 #include "rs6000-builtin.def"
11281 /* DST operations: void foo (void *, const int, const char). */
11283 #undef RS6000_BUILTIN_1
11284 #undef RS6000_BUILTIN_2
11285 #undef RS6000_BUILTIN_3
11286 #undef RS6000_BUILTIN_A
11287 #undef RS6000_BUILTIN_D
11288 #undef RS6000_BUILTIN_E
11289 #undef RS6000_BUILTIN_H
11290 #undef RS6000_BUILTIN_P
11291 #undef RS6000_BUILTIN_Q
11292 #undef RS6000_BUILTIN_S
11293 #undef RS6000_BUILTIN_X
11295 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11296 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11297 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11298 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11299 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
11300 { MASK, ICODE, NAME, ENUM },
11302 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11303 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11304 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11305 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11306 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11307 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11309 static const struct builtin_description bdesc_dst
[] =
11311 #include "rs6000-builtin.def"
11314 /* Simple binary operations: VECc = foo (VECa, VECb). */
11316 #undef RS6000_BUILTIN_1
11317 #undef RS6000_BUILTIN_2
11318 #undef RS6000_BUILTIN_3
11319 #undef RS6000_BUILTIN_A
11320 #undef RS6000_BUILTIN_D
11321 #undef RS6000_BUILTIN_E
11322 #undef RS6000_BUILTIN_H
11323 #undef RS6000_BUILTIN_P
11324 #undef RS6000_BUILTIN_Q
11325 #undef RS6000_BUILTIN_S
11326 #undef RS6000_BUILTIN_X
11328 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11329 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
11330 { MASK, ICODE, NAME, ENUM },
11332 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11333 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11334 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11335 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11336 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11337 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11338 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11339 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11340 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11342 static const struct builtin_description bdesc_2arg
[] =
11344 #include "rs6000-builtin.def"
11347 #undef RS6000_BUILTIN_1
11348 #undef RS6000_BUILTIN_2
11349 #undef RS6000_BUILTIN_3
11350 #undef RS6000_BUILTIN_A
11351 #undef RS6000_BUILTIN_D
11352 #undef RS6000_BUILTIN_E
11353 #undef RS6000_BUILTIN_H
11354 #undef RS6000_BUILTIN_P
11355 #undef RS6000_BUILTIN_Q
11356 #undef RS6000_BUILTIN_S
11357 #undef RS6000_BUILTIN_X
11359 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11360 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11361 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11362 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11363 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11364 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11365 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11366 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
11367 { MASK, ICODE, NAME, ENUM },
11369 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11370 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11371 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11373 /* AltiVec predicates. */
11375 static const struct builtin_description bdesc_altivec_preds
[] =
11377 #include "rs6000-builtin.def"
11380 /* SPE predicates. */
11381 #undef RS6000_BUILTIN_1
11382 #undef RS6000_BUILTIN_2
11383 #undef RS6000_BUILTIN_3
11384 #undef RS6000_BUILTIN_A
11385 #undef RS6000_BUILTIN_D
11386 #undef RS6000_BUILTIN_E
11387 #undef RS6000_BUILTIN_H
11388 #undef RS6000_BUILTIN_P
11389 #undef RS6000_BUILTIN_Q
11390 #undef RS6000_BUILTIN_S
11391 #undef RS6000_BUILTIN_X
11393 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11394 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11395 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11396 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11397 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11398 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11399 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11400 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11401 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11402 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
11403 { MASK, ICODE, NAME, ENUM },
11405 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11407 static const struct builtin_description bdesc_spe_predicates
[] =
11409 #include "rs6000-builtin.def"
11412 /* SPE evsel predicates. */
11413 #undef RS6000_BUILTIN_1
11414 #undef RS6000_BUILTIN_2
11415 #undef RS6000_BUILTIN_3
11416 #undef RS6000_BUILTIN_A
11417 #undef RS6000_BUILTIN_D
11418 #undef RS6000_BUILTIN_E
11419 #undef RS6000_BUILTIN_H
11420 #undef RS6000_BUILTIN_P
11421 #undef RS6000_BUILTIN_Q
11422 #undef RS6000_BUILTIN_S
11423 #undef RS6000_BUILTIN_X
11425 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11426 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11427 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11428 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11429 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11430 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
11431 { MASK, ICODE, NAME, ENUM },
11433 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11434 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11435 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11436 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11437 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11439 static const struct builtin_description bdesc_spe_evsel
[] =
11441 #include "rs6000-builtin.def"
11444 /* PAIRED predicates. */
11445 #undef RS6000_BUILTIN_1
11446 #undef RS6000_BUILTIN_2
11447 #undef RS6000_BUILTIN_3
11448 #undef RS6000_BUILTIN_A
11449 #undef RS6000_BUILTIN_D
11450 #undef RS6000_BUILTIN_E
11451 #undef RS6000_BUILTIN_H
11452 #undef RS6000_BUILTIN_P
11453 #undef RS6000_BUILTIN_Q
11454 #undef RS6000_BUILTIN_S
11455 #undef RS6000_BUILTIN_X
11457 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11458 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11459 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11460 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11461 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11462 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11463 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11464 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11465 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
11466 { MASK, ICODE, NAME, ENUM },
11468 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11469 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11471 static const struct builtin_description bdesc_paired_preds
[] =
11473 #include "rs6000-builtin.def"
11476 /* ABS* operations. */
11478 #undef RS6000_BUILTIN_1
11479 #undef RS6000_BUILTIN_2
11480 #undef RS6000_BUILTIN_3
11481 #undef RS6000_BUILTIN_A
11482 #undef RS6000_BUILTIN_D
11483 #undef RS6000_BUILTIN_E
11484 #undef RS6000_BUILTIN_H
11485 #undef RS6000_BUILTIN_P
11486 #undef RS6000_BUILTIN_Q
11487 #undef RS6000_BUILTIN_S
11488 #undef RS6000_BUILTIN_X
11490 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11491 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11492 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11493 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
11494 { MASK, ICODE, NAME, ENUM },
11496 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11497 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11498 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11499 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11500 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11501 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11502 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11504 static const struct builtin_description bdesc_abs
[] =
11506 #include "rs6000-builtin.def"
11509 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
11512 #undef RS6000_BUILTIN_1
11513 #undef RS6000_BUILTIN_2
11514 #undef RS6000_BUILTIN_3
11515 #undef RS6000_BUILTIN_A
11516 #undef RS6000_BUILTIN_D
11517 #undef RS6000_BUILTIN_E
11518 #undef RS6000_BUILTIN_H
11519 #undef RS6000_BUILTIN_P
11520 #undef RS6000_BUILTIN_Q
11521 #undef RS6000_BUILTIN_S
11522 #undef RS6000_BUILTIN_X
11524 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
11525 { MASK, ICODE, NAME, ENUM },
11527 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11528 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11529 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11530 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11531 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11532 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11533 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11534 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11535 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11536 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11538 static const struct builtin_description bdesc_1arg
[] =
11540 #include "rs6000-builtin.def"
11543 /* HTM builtins. */
11544 #undef RS6000_BUILTIN_1
11545 #undef RS6000_BUILTIN_2
11546 #undef RS6000_BUILTIN_3
11547 #undef RS6000_BUILTIN_A
11548 #undef RS6000_BUILTIN_D
11549 #undef RS6000_BUILTIN_E
11550 #undef RS6000_BUILTIN_H
11551 #undef RS6000_BUILTIN_P
11552 #undef RS6000_BUILTIN_Q
11553 #undef RS6000_BUILTIN_S
11554 #undef RS6000_BUILTIN_X
11556 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11557 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11558 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11559 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11560 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11561 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11562 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
11563 { MASK, ICODE, NAME, ENUM },
11565 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11566 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11567 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11568 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11570 static const struct builtin_description bdesc_htm
[] =
11572 #include "rs6000-builtin.def"
11575 #undef RS6000_BUILTIN_1
11576 #undef RS6000_BUILTIN_2
11577 #undef RS6000_BUILTIN_3
11578 #undef RS6000_BUILTIN_A
11579 #undef RS6000_BUILTIN_D
11580 #undef RS6000_BUILTIN_E
11581 #undef RS6000_BUILTIN_H
11582 #undef RS6000_BUILTIN_P
11583 #undef RS6000_BUILTIN_Q
11584 #undef RS6000_BUILTIN_S
11586 /* Return true if a builtin function is overloaded. */
11588 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
11590 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
11593 /* Expand an expression EXP that calls a builtin without arguments. */
11595 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
11598 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11600 if (icode
== CODE_FOR_nothing
)
11601 /* Builtin not supported on this processor. */
11605 || GET_MODE (target
) != tmode
11606 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11607 target
= gen_reg_rtx (tmode
);
11609 pat
= GEN_FCN (icode
) (target
);
11619 rs6000_expand_mtfsf_builtin (enum insn_code icode
, tree exp
)
11622 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11623 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11624 rtx op0
= expand_normal (arg0
);
11625 rtx op1
= expand_normal (arg1
);
11626 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
11627 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
11629 if (icode
== CODE_FOR_nothing
)
11630 /* Builtin not supported on this processor. */
11633 /* If we got invalid arguments bail out before generating bad rtl. */
11634 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11637 if (GET_CODE (op0
) != CONST_INT
11638 || INTVAL (op0
) > 255
11639 || INTVAL (op0
) < 0)
11641 error ("argument 1 must be an 8-bit field value");
11645 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11646 op0
= copy_to_mode_reg (mode0
, op0
);
11648 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
11649 op1
= copy_to_mode_reg (mode1
, op1
);
11651 pat
= GEN_FCN (icode
) (op0
, op1
);
11661 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11664 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11665 rtx op0
= expand_normal (arg0
);
11666 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11667 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11669 if (icode
== CODE_FOR_nothing
)
11670 /* Builtin not supported on this processor. */
11673 /* If we got invalid arguments bail out before generating bad rtl. */
11674 if (arg0
== error_mark_node
)
11677 if (icode
== CODE_FOR_altivec_vspltisb
11678 || icode
== CODE_FOR_altivec_vspltish
11679 || icode
== CODE_FOR_altivec_vspltisw
11680 || icode
== CODE_FOR_spe_evsplatfi
11681 || icode
== CODE_FOR_spe_evsplati
)
11683 /* Only allow 5-bit *signed* literals. */
11684 if (GET_CODE (op0
) != CONST_INT
11685 || INTVAL (op0
) > 15
11686 || INTVAL (op0
) < -16)
11688 error ("argument 1 must be a 5-bit signed literal");
11694 || GET_MODE (target
) != tmode
11695 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11696 target
= gen_reg_rtx (tmode
);
11698 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11699 op0
= copy_to_mode_reg (mode0
, op0
);
11701 pat
= GEN_FCN (icode
) (target
, op0
);
11710 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
11712 rtx pat
, scratch1
, scratch2
;
11713 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11714 rtx op0
= expand_normal (arg0
);
11715 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11716 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11718 /* If we have invalid arguments, bail out before generating bad rtl. */
11719 if (arg0
== error_mark_node
)
11723 || GET_MODE (target
) != tmode
11724 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11725 target
= gen_reg_rtx (tmode
);
11727 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11728 op0
= copy_to_mode_reg (mode0
, op0
);
11730 scratch1
= gen_reg_rtx (mode0
);
11731 scratch2
= gen_reg_rtx (mode0
);
11733 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
11742 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11745 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11746 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11747 rtx op0
= expand_normal (arg0
);
11748 rtx op1
= expand_normal (arg1
);
11749 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11750 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11751 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11753 if (icode
== CODE_FOR_nothing
)
11754 /* Builtin not supported on this processor. */
11757 /* If we got invalid arguments bail out before generating bad rtl. */
11758 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11761 if (icode
== CODE_FOR_altivec_vcfux
11762 || icode
== CODE_FOR_altivec_vcfsx
11763 || icode
== CODE_FOR_altivec_vctsxs
11764 || icode
== CODE_FOR_altivec_vctuxs
11765 || icode
== CODE_FOR_altivec_vspltb
11766 || icode
== CODE_FOR_altivec_vsplth
11767 || icode
== CODE_FOR_altivec_vspltw
11768 || icode
== CODE_FOR_spe_evaddiw
11769 || icode
== CODE_FOR_spe_evldd
11770 || icode
== CODE_FOR_spe_evldh
11771 || icode
== CODE_FOR_spe_evldw
11772 || icode
== CODE_FOR_spe_evlhhesplat
11773 || icode
== CODE_FOR_spe_evlhhossplat
11774 || icode
== CODE_FOR_spe_evlhhousplat
11775 || icode
== CODE_FOR_spe_evlwhe
11776 || icode
== CODE_FOR_spe_evlwhos
11777 || icode
== CODE_FOR_spe_evlwhou
11778 || icode
== CODE_FOR_spe_evlwhsplat
11779 || icode
== CODE_FOR_spe_evlwwsplat
11780 || icode
== CODE_FOR_spe_evrlwi
11781 || icode
== CODE_FOR_spe_evslwi
11782 || icode
== CODE_FOR_spe_evsrwis
11783 || icode
== CODE_FOR_spe_evsubifw
11784 || icode
== CODE_FOR_spe_evsrwiu
)
11786 /* Only allow 5-bit unsigned literals. */
11788 if (TREE_CODE (arg1
) != INTEGER_CST
11789 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
11791 error ("argument 2 must be a 5-bit unsigned literal");
11797 || GET_MODE (target
) != tmode
11798 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11799 target
= gen_reg_rtx (tmode
);
11801 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11802 op0
= copy_to_mode_reg (mode0
, op0
);
11803 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11804 op1
= copy_to_mode_reg (mode1
, op1
);
11806 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11815 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11818 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
11819 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11820 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11821 rtx op0
= expand_normal (arg0
);
11822 rtx op1
= expand_normal (arg1
);
11823 enum machine_mode tmode
= SImode
;
11824 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11825 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11828 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
11830 error ("argument 1 of __builtin_altivec_predicate must be a constant");
11834 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
11836 gcc_assert (mode0
== mode1
);
11838 /* If we have invalid arguments, bail out before generating bad rtl. */
11839 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11843 || GET_MODE (target
) != tmode
11844 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11845 target
= gen_reg_rtx (tmode
);
11847 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11848 op0
= copy_to_mode_reg (mode0
, op0
);
11849 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11850 op1
= copy_to_mode_reg (mode1
, op1
);
11852 scratch
= gen_reg_rtx (mode0
);
11854 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11859 /* The vec_any* and vec_all* predicates use the same opcodes for two
11860 different operations, but the bits in CR6 will be different
11861 depending on what information we want. So we have to play tricks
11862 with CR6 to get the right bits out.
11864 If you think this is disgusting, look at the specs for the
11865 AltiVec predicates. */
11867 switch (cr6_form_int
)
11870 emit_insn (gen_cr6_test_for_zero (target
));
11873 emit_insn (gen_cr6_test_for_zero_reverse (target
));
11876 emit_insn (gen_cr6_test_for_lt (target
));
11879 emit_insn (gen_cr6_test_for_lt_reverse (target
));
11882 error ("argument 1 of __builtin_altivec_predicate is out of range");
11890 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
11893 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11894 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11895 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11896 enum machine_mode mode0
= Pmode
;
11897 enum machine_mode mode1
= Pmode
;
11898 rtx op0
= expand_normal (arg0
);
11899 rtx op1
= expand_normal (arg1
);
11901 if (icode
== CODE_FOR_nothing
)
11902 /* Builtin not supported on this processor. */
11905 /* If we got invalid arguments bail out before generating bad rtl. */
11906 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11910 || GET_MODE (target
) != tmode
11911 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11912 target
= gen_reg_rtx (tmode
);
11914 op1
= copy_to_mode_reg (mode1
, op1
);
11916 if (op0
== const0_rtx
)
11918 addr
= gen_rtx_MEM (tmode
, op1
);
11922 op0
= copy_to_mode_reg (mode0
, op0
);
11923 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
11926 pat
= GEN_FCN (icode
) (target
, addr
);
11935 /* Return a constant vector for use as a little-endian permute control vector
11936 to reverse the order of elements of the given vector mode. */
11938 swap_selector_for_mode (enum machine_mode mode
)
11940 /* These are little endian vectors, so their elements are reversed
11941 from what you would normally expect for a permute control vector. */
11942 unsigned int swap2
[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
11943 unsigned int swap4
[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
11944 unsigned int swap8
[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
11945 unsigned int swap16
[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
11946 unsigned int *swaparray
, i
;
11963 swaparray
= swap16
;
11966 gcc_unreachable ();
11969 for (i
= 0; i
< 16; ++i
)
11970 perm
[i
] = GEN_INT (swaparray
[i
]);
11972 return force_reg (V16QImode
, gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
)));
11975 /* Generate code for an "lvx", "lvxl", or "lve*x" built-in for a little endian target
11976 with -maltivec=be specified. Issue the load followed by an element-reversing
11979 altivec_expand_lvx_be (rtx op0
, rtx op1
, enum machine_mode mode
, unsigned unspec
)
11981 rtx tmp
= gen_reg_rtx (mode
);
11982 rtx load
= gen_rtx_SET (VOIDmode
, tmp
, op1
);
11983 rtx lvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
11984 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, load
, lvx
));
11985 rtx sel
= swap_selector_for_mode (mode
);
11986 rtx vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, tmp
, tmp
, sel
), UNSPEC_VPERM
);
11988 gcc_assert (REG_P (op0
));
11990 emit_insn (gen_rtx_SET (VOIDmode
, op0
, vperm
));
11993 /* Generate code for a "stvx" or "stvxl" built-in for a little endian target
11994 with -maltivec=be specified. Issue the store preceded by an element-reversing
11997 altivec_expand_stvx_be (rtx op0
, rtx op1
, enum machine_mode mode
, unsigned unspec
)
11999 rtx tmp
= gen_reg_rtx (mode
);
12000 rtx store
= gen_rtx_SET (VOIDmode
, op0
, tmp
);
12001 rtx stvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
12002 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, store
, stvx
));
12003 rtx sel
= swap_selector_for_mode (mode
);
12006 gcc_assert (REG_P (op1
));
12007 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
12008 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, vperm
));
12012 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
12013 specified. Issue the store preceded by an element-reversing permute. */
12015 altivec_expand_stvex_be (rtx op0
, rtx op1
, enum machine_mode mode
, unsigned unspec
)
12017 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
12018 rtx tmp
= gen_reg_rtx (mode
);
12019 rtx stvx
= gen_rtx_UNSPEC (inner_mode
, gen_rtvec (1, tmp
), unspec
);
12020 rtx sel
= swap_selector_for_mode (mode
);
12023 gcc_assert (REG_P (op1
));
12024 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
12025 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, vperm
));
12026 emit_insn (gen_rtx_SET (VOIDmode
, op0
, stvx
));
12030 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
12033 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12034 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12035 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12036 enum machine_mode mode0
= Pmode
;
12037 enum machine_mode mode1
= Pmode
;
12038 rtx op0
= expand_normal (arg0
);
12039 rtx op1
= expand_normal (arg1
);
12041 if (icode
== CODE_FOR_nothing
)
12042 /* Builtin not supported on this processor. */
12045 /* If we got invalid arguments bail out before generating bad rtl. */
12046 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12050 || GET_MODE (target
) != tmode
12051 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12052 target
= gen_reg_rtx (tmode
);
12054 op1
= copy_to_mode_reg (mode1
, op1
);
12056 if (op0
== const0_rtx
)
12058 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
12062 op0
= copy_to_mode_reg (mode0
, op0
);
12063 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
12066 pat
= GEN_FCN (icode
) (target
, addr
);
12076 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
12078 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12079 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12080 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12081 rtx op0
= expand_normal (arg0
);
12082 rtx op1
= expand_normal (arg1
);
12083 rtx op2
= expand_normal (arg2
);
12085 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
12086 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
12087 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
12089 /* Invalid arguments. Bail before doing anything stoopid! */
12090 if (arg0
== error_mark_node
12091 || arg1
== error_mark_node
12092 || arg2
== error_mark_node
)
12095 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
12096 op0
= copy_to_mode_reg (mode2
, op0
);
12097 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
12098 op1
= copy_to_mode_reg (mode0
, op1
);
12099 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
12100 op2
= copy_to_mode_reg (mode1
, op2
);
12102 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
12109 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
12111 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12112 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12113 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12114 rtx op0
= expand_normal (arg0
);
12115 rtx op1
= expand_normal (arg1
);
12116 rtx op2
= expand_normal (arg2
);
12118 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12119 enum machine_mode mode1
= Pmode
;
12120 enum machine_mode mode2
= Pmode
;
12122 /* Invalid arguments. Bail before doing anything stoopid! */
12123 if (arg0
== error_mark_node
12124 || arg1
== error_mark_node
12125 || arg2
== error_mark_node
)
12128 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
12129 op0
= copy_to_mode_reg (tmode
, op0
);
12131 op2
= copy_to_mode_reg (mode2
, op2
);
12133 if (op1
== const0_rtx
)
12135 addr
= gen_rtx_MEM (tmode
, op2
);
12139 op1
= copy_to_mode_reg (mode1
, op1
);
12140 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
12143 pat
= GEN_FCN (icode
) (addr
, op0
);
12150 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
12152 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12153 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12154 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12155 rtx op0
= expand_normal (arg0
);
12156 rtx op1
= expand_normal (arg1
);
12157 rtx op2
= expand_normal (arg2
);
12159 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12160 enum machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
12161 enum machine_mode mode1
= Pmode
;
12162 enum machine_mode mode2
= Pmode
;
12164 /* Invalid arguments. Bail before doing anything stoopid! */
12165 if (arg0
== error_mark_node
12166 || arg1
== error_mark_node
12167 || arg2
== error_mark_node
)
12170 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
12171 op0
= copy_to_mode_reg (smode
, op0
);
12173 op2
= copy_to_mode_reg (mode2
, op2
);
12175 if (op1
== const0_rtx
)
12177 addr
= gen_rtx_MEM (tmode
, op2
);
12181 op1
= copy_to_mode_reg (mode1
, op1
);
12182 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
12185 pat
= GEN_FCN (icode
) (addr
, op0
);
12191 /* Return the appropriate SPR number associated with the given builtin. */
12192 static inline HOST_WIDE_INT
12193 htm_spr_num (enum rs6000_builtins code
)
12195 if (code
== HTM_BUILTIN_GET_TFHAR
12196 || code
== HTM_BUILTIN_SET_TFHAR
)
12198 else if (code
== HTM_BUILTIN_GET_TFIAR
12199 || code
== HTM_BUILTIN_SET_TFIAR
)
12201 else if (code
== HTM_BUILTIN_GET_TEXASR
12202 || code
== HTM_BUILTIN_SET_TEXASR
)
12204 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
12205 || code
== HTM_BUILTIN_SET_TEXASRU
);
12206 return TEXASRU_SPR
;
12209 /* Return the appropriate SPR regno associated with the given builtin. */
12210 static inline HOST_WIDE_INT
12211 htm_spr_regno (enum rs6000_builtins code
)
12213 if (code
== HTM_BUILTIN_GET_TFHAR
12214 || code
== HTM_BUILTIN_SET_TFHAR
)
12215 return TFHAR_REGNO
;
12216 else if (code
== HTM_BUILTIN_GET_TFIAR
12217 || code
== HTM_BUILTIN_SET_TFIAR
)
12218 return TFIAR_REGNO
;
12219 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
12220 || code
== HTM_BUILTIN_SET_TEXASR
12221 || code
== HTM_BUILTIN_GET_TEXASRU
12222 || code
== HTM_BUILTIN_SET_TEXASRU
);
12223 return TEXASR_REGNO
;
12226 /* Return the correct ICODE value depending on whether we are
12227 setting or reading the HTM SPRs. */
12228 static inline enum insn_code
12229 rs6000_htm_spr_icode (bool nonvoid
)
12232 return (TARGET_64BIT
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
12234 return (TARGET_64BIT
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
12237 /* Expand the HTM builtin in EXP and store the result in TARGET.
12238 Store true in *EXPANDEDP if we found a builtin to expand. */
12240 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
12242 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12243 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
12244 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12245 const struct builtin_description
*d
;
12248 *expandedp
= false;
12250 /* Expand the HTM builtins. */
12252 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
12253 if (d
->code
== fcode
)
12255 rtx op
[MAX_HTM_OPERANDS
], pat
;
12258 call_expr_arg_iterator iter
;
12259 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
12260 enum insn_code icode
= d
->icode
;
12262 if (attr
& RS6000_BTC_SPR
)
12263 icode
= rs6000_htm_spr_icode (nonvoid
);
12267 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12269 || GET_MODE (target
) != tmode
12270 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12271 target
= gen_reg_rtx (tmode
);
12272 op
[nopnds
++] = target
;
12275 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
12277 const struct insn_operand_data
*insn_op
;
12279 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
12282 insn_op
= &insn_data
[icode
].operand
[nopnds
];
12284 op
[nopnds
] = expand_normal (arg
);
12286 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
12288 if (!strcmp (insn_op
->constraint
, "n"))
12290 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
12291 if (!CONST_INT_P (op
[nopnds
]))
12292 error ("argument %d must be an unsigned literal", arg_num
);
12294 error ("argument %d is an unsigned literal that is "
12295 "out of range", arg_num
);
12298 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
12304 /* Handle the builtins for extended mnemonics. These accept
12305 no arguments, but map to builtins that take arguments. */
12308 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
12309 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
12310 op
[nopnds
++] = GEN_INT (1);
12311 #ifdef ENABLE_CHECKING
12312 attr
|= RS6000_BTC_UNARY
;
12315 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
12316 op
[nopnds
++] = GEN_INT (0);
12317 #ifdef ENABLE_CHECKING
12318 attr
|= RS6000_BTC_UNARY
;
12325 /* If this builtin accesses SPRs, then pass in the appropriate
12326 SPR number and SPR regno as the last two operands. */
12327 if (attr
& RS6000_BTC_SPR
)
12329 op
[nopnds
++] = gen_rtx_CONST_INT (Pmode
, htm_spr_num (fcode
));
12330 op
[nopnds
++] = gen_rtx_REG (Pmode
, htm_spr_regno (fcode
));
12333 #ifdef ENABLE_CHECKING
12334 int expected_nopnds
= 0;
12335 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
12336 expected_nopnds
= 1;
12337 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
12338 expected_nopnds
= 2;
12339 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
12340 expected_nopnds
= 3;
12341 if (!(attr
& RS6000_BTC_VOID
))
12342 expected_nopnds
+= 1;
12343 if (attr
& RS6000_BTC_SPR
)
12344 expected_nopnds
+= 2;
12346 gcc_assert (nopnds
== expected_nopnds
&& nopnds
<= MAX_HTM_OPERANDS
);
12352 pat
= GEN_FCN (icode
) (op
[0]);
12355 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
12358 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
12361 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
12364 gcc_unreachable ();
12380 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12383 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12384 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12385 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12386 rtx op0
= expand_normal (arg0
);
12387 rtx op1
= expand_normal (arg1
);
12388 rtx op2
= expand_normal (arg2
);
12389 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12390 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12391 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12392 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
12394 if (icode
== CODE_FOR_nothing
)
12395 /* Builtin not supported on this processor. */
12398 /* If we got invalid arguments bail out before generating bad rtl. */
12399 if (arg0
== error_mark_node
12400 || arg1
== error_mark_node
12401 || arg2
== error_mark_node
)
12404 /* Check and prepare argument depending on the instruction code.
12406 Note that a switch statement instead of the sequence of tests
12407 would be incorrect as many of the CODE_FOR values could be
12408 CODE_FOR_nothing and that would yield multiple alternatives
12409 with identical values. We'd never reach here at runtime in
12411 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
12412 || icode
== CODE_FOR_altivec_vsldoi_v4si
12413 || icode
== CODE_FOR_altivec_vsldoi_v8hi
12414 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
12416 /* Only allow 4-bit unsigned literals. */
12418 if (TREE_CODE (arg2
) != INTEGER_CST
12419 || TREE_INT_CST_LOW (arg2
) & ~0xf)
12421 error ("argument 3 must be a 4-bit unsigned literal");
12425 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
12426 || icode
== CODE_FOR_vsx_xxpermdi_v2di
12427 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
12428 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
12429 || icode
== CODE_FOR_vsx_xxsldwi_v4si
12430 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
12431 || icode
== CODE_FOR_vsx_xxsldwi_v2di
12432 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
12434 /* Only allow 2-bit unsigned literals. */
12436 if (TREE_CODE (arg2
) != INTEGER_CST
12437 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12439 error ("argument 3 must be a 2-bit unsigned literal");
12443 else if (icode
== CODE_FOR_vsx_set_v2df
12444 || icode
== CODE_FOR_vsx_set_v2di
12445 || icode
== CODE_FOR_bcdadd
12446 || icode
== CODE_FOR_bcdadd_lt
12447 || icode
== CODE_FOR_bcdadd_eq
12448 || icode
== CODE_FOR_bcdadd_gt
12449 || icode
== CODE_FOR_bcdsub
12450 || icode
== CODE_FOR_bcdsub_lt
12451 || icode
== CODE_FOR_bcdsub_eq
12452 || icode
== CODE_FOR_bcdsub_gt
)
12454 /* Only allow 1-bit unsigned literals. */
12456 if (TREE_CODE (arg2
) != INTEGER_CST
12457 || TREE_INT_CST_LOW (arg2
) & ~0x1)
12459 error ("argument 3 must be a 1-bit unsigned literal");
12463 else if (icode
== CODE_FOR_dfp_ddedpd_dd
12464 || icode
== CODE_FOR_dfp_ddedpd_td
)
12466 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
12468 if (TREE_CODE (arg0
) != INTEGER_CST
12469 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12471 error ("argument 1 must be 0 or 2");
12475 else if (icode
== CODE_FOR_dfp_denbcd_dd
12476 || icode
== CODE_FOR_dfp_denbcd_td
)
12478 /* Only allow 1-bit unsigned literals. */
12480 if (TREE_CODE (arg0
) != INTEGER_CST
12481 || TREE_INT_CST_LOW (arg0
) & ~0x1)
12483 error ("argument 1 must be a 1-bit unsigned literal");
12487 else if (icode
== CODE_FOR_dfp_dscli_dd
12488 || icode
== CODE_FOR_dfp_dscli_td
12489 || icode
== CODE_FOR_dfp_dscri_dd
12490 || icode
== CODE_FOR_dfp_dscri_td
)
12492 /* Only allow 6-bit unsigned literals. */
12494 if (TREE_CODE (arg1
) != INTEGER_CST
12495 || TREE_INT_CST_LOW (arg1
) & ~0x3f)
12497 error ("argument 2 must be a 6-bit unsigned literal");
12501 else if (icode
== CODE_FOR_crypto_vshasigmaw
12502 || icode
== CODE_FOR_crypto_vshasigmad
)
12504 /* Check whether the 2nd and 3rd arguments are integer constants and in
12505 range and prepare arguments. */
12507 if (TREE_CODE (arg1
) != INTEGER_CST
|| wi::geu_p (arg1
, 2))
12509 error ("argument 2 must be 0 or 1");
12514 if (TREE_CODE (arg2
) != INTEGER_CST
|| wi::geu_p (arg1
, 16))
12516 error ("argument 3 must be in the range 0..15");
12522 || GET_MODE (target
) != tmode
12523 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12524 target
= gen_reg_rtx (tmode
);
12526 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12527 op0
= copy_to_mode_reg (mode0
, op0
);
12528 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12529 op1
= copy_to_mode_reg (mode1
, op1
);
12530 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12531 op2
= copy_to_mode_reg (mode2
, op2
);
12533 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
12534 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
12536 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12544 /* Expand the lvx builtins. */
12546 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
12548 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12549 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12551 enum machine_mode tmode
, mode0
;
12553 enum insn_code icode
;
12557 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
12558 icode
= CODE_FOR_vector_altivec_load_v16qi
;
12560 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
12561 icode
= CODE_FOR_vector_altivec_load_v8hi
;
12563 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
12564 icode
= CODE_FOR_vector_altivec_load_v4si
;
12566 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
12567 icode
= CODE_FOR_vector_altivec_load_v4sf
;
12569 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
12570 icode
= CODE_FOR_vector_altivec_load_v2df
;
12572 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
12573 icode
= CODE_FOR_vector_altivec_load_v2di
;
12574 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti
:
12575 icode
= CODE_FOR_vector_altivec_load_v1ti
;
12578 *expandedp
= false;
12584 arg0
= CALL_EXPR_ARG (exp
, 0);
12585 op0
= expand_normal (arg0
);
12586 tmode
= insn_data
[icode
].operand
[0].mode
;
12587 mode0
= insn_data
[icode
].operand
[1].mode
;
12590 || GET_MODE (target
) != tmode
12591 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12592 target
= gen_reg_rtx (tmode
);
12594 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12595 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12597 pat
= GEN_FCN (icode
) (target
, op0
);
12604 /* Expand the stvx builtins. */
12606 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12609 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12610 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12612 enum machine_mode mode0
, mode1
;
12614 enum insn_code icode
;
12618 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
12619 icode
= CODE_FOR_vector_altivec_store_v16qi
;
12621 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
12622 icode
= CODE_FOR_vector_altivec_store_v8hi
;
12624 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
12625 icode
= CODE_FOR_vector_altivec_store_v4si
;
12627 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
12628 icode
= CODE_FOR_vector_altivec_store_v4sf
;
12630 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
12631 icode
= CODE_FOR_vector_altivec_store_v2df
;
12633 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
12634 icode
= CODE_FOR_vector_altivec_store_v2di
;
12635 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti
:
12636 icode
= CODE_FOR_vector_altivec_store_v1ti
;
12639 *expandedp
= false;
12643 arg0
= CALL_EXPR_ARG (exp
, 0);
12644 arg1
= CALL_EXPR_ARG (exp
, 1);
12645 op0
= expand_normal (arg0
);
12646 op1
= expand_normal (arg1
);
12647 mode0
= insn_data
[icode
].operand
[0].mode
;
12648 mode1
= insn_data
[icode
].operand
[1].mode
;
12650 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12651 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12652 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
12653 op1
= copy_to_mode_reg (mode1
, op1
);
12655 pat
= GEN_FCN (icode
) (op0
, op1
);
12663 /* Expand the dst builtins. */
12665 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12668 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12669 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12670 tree arg0
, arg1
, arg2
;
12671 enum machine_mode mode0
, mode1
;
12672 rtx pat
, op0
, op1
, op2
;
12673 const struct builtin_description
*d
;
12676 *expandedp
= false;
12678 /* Handle DST variants. */
12680 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
12681 if (d
->code
== fcode
)
12683 arg0
= CALL_EXPR_ARG (exp
, 0);
12684 arg1
= CALL_EXPR_ARG (exp
, 1);
12685 arg2
= CALL_EXPR_ARG (exp
, 2);
12686 op0
= expand_normal (arg0
);
12687 op1
= expand_normal (arg1
);
12688 op2
= expand_normal (arg2
);
12689 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
12690 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
12692 /* Invalid arguments, bail out before generating bad rtl. */
12693 if (arg0
== error_mark_node
12694 || arg1
== error_mark_node
12695 || arg2
== error_mark_node
)
12700 if (TREE_CODE (arg2
) != INTEGER_CST
12701 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12703 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
12707 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
12708 op0
= copy_to_mode_reg (Pmode
, op0
);
12709 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
12710 op1
= copy_to_mode_reg (mode1
, op1
);
12712 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
12722 /* Expand vec_init builtin. */
12724 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
12726 enum machine_mode tmode
= TYPE_MODE (type
);
12727 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
12728 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
12730 gcc_assert (VECTOR_MODE_P (tmode
));
12731 gcc_assert (n_elt
== call_expr_nargs (exp
));
12733 if (!target
|| !register_operand (target
, tmode
))
12734 target
= gen_reg_rtx (tmode
);
12736 /* If we have a vector compromised of a single element, such as V1TImode, do
12737 the initialization directly. */
12738 if (n_elt
== 1 && GET_MODE_SIZE (tmode
) == GET_MODE_SIZE (inner_mode
))
12740 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, 0));
12741 emit_move_insn (target
, gen_lowpart (tmode
, x
));
12745 rtvec v
= rtvec_alloc (n_elt
);
12747 for (i
= 0; i
< n_elt
; ++i
)
12749 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
12750 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
12753 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
12759 /* Return the integer constant in ARG. Constrain it to be in the range
12760 of the subparts of VEC_TYPE; issue an error if not. */
12763 get_element_number (tree vec_type
, tree arg
)
12765 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
12767 if (!tree_fits_uhwi_p (arg
)
12768 || (elt
= tree_to_uhwi (arg
), elt
> max
))
12770 error ("selector must be an integer constant in the range 0..%wi", max
);
12777 /* Expand vec_set builtin. */
12779 altivec_expand_vec_set_builtin (tree exp
)
12781 enum machine_mode tmode
, mode1
;
12782 tree arg0
, arg1
, arg2
;
12786 arg0
= CALL_EXPR_ARG (exp
, 0);
12787 arg1
= CALL_EXPR_ARG (exp
, 1);
12788 arg2
= CALL_EXPR_ARG (exp
, 2);
12790 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
12791 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
12792 gcc_assert (VECTOR_MODE_P (tmode
));
12794 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
12795 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
12796 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
12798 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
12799 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
12801 op0
= force_reg (tmode
, op0
);
12802 op1
= force_reg (mode1
, op1
);
12804 rs6000_expand_vector_set (op0
, op1
, elt
);
12809 /* Expand vec_ext builtin. */
12811 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
12813 enum machine_mode tmode
, mode0
;
12818 arg0
= CALL_EXPR_ARG (exp
, 0);
12819 arg1
= CALL_EXPR_ARG (exp
, 1);
12821 op0
= expand_normal (arg0
);
12822 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
12824 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
12825 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
12826 gcc_assert (VECTOR_MODE_P (mode0
));
12828 op0
= force_reg (mode0
, op0
);
12830 if (optimize
|| !target
|| !register_operand (target
, tmode
))
12831 target
= gen_reg_rtx (tmode
);
12833 rs6000_expand_vector_extract (target
, op0
, elt
);
12838 /* Expand the builtin in EXP and store the result in TARGET. Store
12839 true in *EXPANDEDP if we found a builtin to expand. */
12841 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
12843 const struct builtin_description
*d
;
12845 enum insn_code icode
;
12846 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12849 enum machine_mode tmode
, mode0
;
12850 enum rs6000_builtins fcode
12851 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12853 if (rs6000_overloaded_builtin_p (fcode
))
12856 error ("unresolved overload for Altivec builtin %qF", fndecl
);
12858 /* Given it is invalid, just generate a normal call. */
12859 return expand_call (exp
, target
, false);
12862 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
12866 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
12870 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
12878 case ALTIVEC_BUILTIN_STVX_V2DF
:
12879 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df
, exp
);
12880 case ALTIVEC_BUILTIN_STVX_V2DI
:
12881 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di
, exp
);
12882 case ALTIVEC_BUILTIN_STVX_V4SF
:
12883 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf
, exp
);
12884 case ALTIVEC_BUILTIN_STVX
:
12885 case ALTIVEC_BUILTIN_STVX_V4SI
:
12886 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
12887 case ALTIVEC_BUILTIN_STVX_V8HI
:
12888 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi
, exp
);
12889 case ALTIVEC_BUILTIN_STVX_V16QI
:
12890 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi
, exp
);
12891 case ALTIVEC_BUILTIN_STVEBX
:
12892 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
12893 case ALTIVEC_BUILTIN_STVEHX
:
12894 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
12895 case ALTIVEC_BUILTIN_STVEWX
:
12896 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
12897 case ALTIVEC_BUILTIN_STVXL_V2DF
:
12898 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df
, exp
);
12899 case ALTIVEC_BUILTIN_STVXL_V2DI
:
12900 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di
, exp
);
12901 case ALTIVEC_BUILTIN_STVXL_V4SF
:
12902 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf
, exp
);
12903 case ALTIVEC_BUILTIN_STVXL
:
12904 case ALTIVEC_BUILTIN_STVXL_V4SI
:
12905 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si
, exp
);
12906 case ALTIVEC_BUILTIN_STVXL_V8HI
:
12907 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi
, exp
);
12908 case ALTIVEC_BUILTIN_STVXL_V16QI
:
12909 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi
, exp
);
12911 case ALTIVEC_BUILTIN_STVLX
:
12912 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
12913 case ALTIVEC_BUILTIN_STVLXL
:
12914 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
12915 case ALTIVEC_BUILTIN_STVRX
:
12916 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
12917 case ALTIVEC_BUILTIN_STVRXL
:
12918 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
12920 case VSX_BUILTIN_STXVD2X_V1TI
:
12921 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti
, exp
);
12922 case VSX_BUILTIN_STXVD2X_V2DF
:
12923 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
12924 case VSX_BUILTIN_STXVD2X_V2DI
:
12925 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
12926 case VSX_BUILTIN_STXVW4X_V4SF
:
12927 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
12928 case VSX_BUILTIN_STXVW4X_V4SI
:
12929 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
12930 case VSX_BUILTIN_STXVW4X_V8HI
:
12931 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
12932 case VSX_BUILTIN_STXVW4X_V16QI
:
12933 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
12935 case ALTIVEC_BUILTIN_MFVSCR
:
12936 icode
= CODE_FOR_altivec_mfvscr
;
12937 tmode
= insn_data
[icode
].operand
[0].mode
;
12940 || GET_MODE (target
) != tmode
12941 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12942 target
= gen_reg_rtx (tmode
);
12944 pat
= GEN_FCN (icode
) (target
);
12950 case ALTIVEC_BUILTIN_MTVSCR
:
12951 icode
= CODE_FOR_altivec_mtvscr
;
12952 arg0
= CALL_EXPR_ARG (exp
, 0);
12953 op0
= expand_normal (arg0
);
12954 mode0
= insn_data
[icode
].operand
[0].mode
;
12956 /* If we got invalid arguments bail out before generating bad rtl. */
12957 if (arg0
== error_mark_node
)
12960 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12961 op0
= copy_to_mode_reg (mode0
, op0
);
12963 pat
= GEN_FCN (icode
) (op0
);
12968 case ALTIVEC_BUILTIN_DSSALL
:
12969 emit_insn (gen_altivec_dssall ());
12972 case ALTIVEC_BUILTIN_DSS
:
12973 icode
= CODE_FOR_altivec_dss
;
12974 arg0
= CALL_EXPR_ARG (exp
, 0);
12976 op0
= expand_normal (arg0
);
12977 mode0
= insn_data
[icode
].operand
[0].mode
;
12979 /* If we got invalid arguments bail out before generating bad rtl. */
12980 if (arg0
== error_mark_node
)
12983 if (TREE_CODE (arg0
) != INTEGER_CST
12984 || TREE_INT_CST_LOW (arg0
) & ~0x3)
12986 error ("argument to dss must be a 2-bit unsigned literal");
12990 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12991 op0
= copy_to_mode_reg (mode0
, op0
);
12993 emit_insn (gen_altivec_dss (op0
));
12996 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
12997 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
12998 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
12999 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
13000 case VSX_BUILTIN_VEC_INIT_V2DF
:
13001 case VSX_BUILTIN_VEC_INIT_V2DI
:
13002 case VSX_BUILTIN_VEC_INIT_V1TI
:
13003 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
13005 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
13006 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
13007 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
13008 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
13009 case VSX_BUILTIN_VEC_SET_V2DF
:
13010 case VSX_BUILTIN_VEC_SET_V2DI
:
13011 case VSX_BUILTIN_VEC_SET_V1TI
:
13012 return altivec_expand_vec_set_builtin (exp
);
13014 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
13015 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
13016 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
13017 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
13018 case VSX_BUILTIN_VEC_EXT_V2DF
:
13019 case VSX_BUILTIN_VEC_EXT_V2DI
:
13020 case VSX_BUILTIN_VEC_EXT_V1TI
:
13021 return altivec_expand_vec_ext_builtin (exp
, target
);
13025 /* Fall through. */
13028 /* Expand abs* operations. */
13030 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
13031 if (d
->code
== fcode
)
13032 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
13034 /* Expand the AltiVec predicates. */
13035 d
= bdesc_altivec_preds
;
13036 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
13037 if (d
->code
== fcode
)
13038 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
13040 /* LV* are funky. We initialized them differently. */
13043 case ALTIVEC_BUILTIN_LVSL
:
13044 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
13045 exp
, target
, false);
13046 case ALTIVEC_BUILTIN_LVSR
:
13047 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
13048 exp
, target
, false);
13049 case ALTIVEC_BUILTIN_LVEBX
:
13050 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
13051 exp
, target
, false);
13052 case ALTIVEC_BUILTIN_LVEHX
:
13053 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
13054 exp
, target
, false);
13055 case ALTIVEC_BUILTIN_LVEWX
:
13056 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
13057 exp
, target
, false);
13058 case ALTIVEC_BUILTIN_LVXL_V2DF
:
13059 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df
,
13060 exp
, target
, false);
13061 case ALTIVEC_BUILTIN_LVXL_V2DI
:
13062 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di
,
13063 exp
, target
, false);
13064 case ALTIVEC_BUILTIN_LVXL_V4SF
:
13065 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf
,
13066 exp
, target
, false);
13067 case ALTIVEC_BUILTIN_LVXL
:
13068 case ALTIVEC_BUILTIN_LVXL_V4SI
:
13069 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si
,
13070 exp
, target
, false);
13071 case ALTIVEC_BUILTIN_LVXL_V8HI
:
13072 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi
,
13073 exp
, target
, false);
13074 case ALTIVEC_BUILTIN_LVXL_V16QI
:
13075 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi
,
13076 exp
, target
, false);
13077 case ALTIVEC_BUILTIN_LVX_V2DF
:
13078 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df
,
13079 exp
, target
, false);
13080 case ALTIVEC_BUILTIN_LVX_V2DI
:
13081 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di
,
13082 exp
, target
, false);
13083 case ALTIVEC_BUILTIN_LVX_V4SF
:
13084 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf
,
13085 exp
, target
, false);
13086 case ALTIVEC_BUILTIN_LVX
:
13087 case ALTIVEC_BUILTIN_LVX_V4SI
:
13088 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
13089 exp
, target
, false);
13090 case ALTIVEC_BUILTIN_LVX_V8HI
:
13091 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi
,
13092 exp
, target
, false);
13093 case ALTIVEC_BUILTIN_LVX_V16QI
:
13094 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi
,
13095 exp
, target
, false);
13096 case ALTIVEC_BUILTIN_LVLX
:
13097 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
13098 exp
, target
, true);
13099 case ALTIVEC_BUILTIN_LVLXL
:
13100 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
13101 exp
, target
, true);
13102 case ALTIVEC_BUILTIN_LVRX
:
13103 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
13104 exp
, target
, true);
13105 case ALTIVEC_BUILTIN_LVRXL
:
13106 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
13107 exp
, target
, true);
13108 case VSX_BUILTIN_LXVD2X_V1TI
:
13109 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti
,
13110 exp
, target
, false);
13111 case VSX_BUILTIN_LXVD2X_V2DF
:
13112 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
13113 exp
, target
, false);
13114 case VSX_BUILTIN_LXVD2X_V2DI
:
13115 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
13116 exp
, target
, false);
13117 case VSX_BUILTIN_LXVW4X_V4SF
:
13118 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
13119 exp
, target
, false);
13120 case VSX_BUILTIN_LXVW4X_V4SI
:
13121 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
13122 exp
, target
, false);
13123 case VSX_BUILTIN_LXVW4X_V8HI
:
13124 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
13125 exp
, target
, false);
13126 case VSX_BUILTIN_LXVW4X_V16QI
:
13127 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
13128 exp
, target
, false);
13132 /* Fall through. */
13135 *expandedp
= false;
13139 /* Expand the builtin in EXP and store the result in TARGET. Store
13140 true in *EXPANDEDP if we found a builtin to expand. */
13142 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
13144 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13145 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13146 const struct builtin_description
*d
;
13153 case PAIRED_BUILTIN_STX
:
13154 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
13155 case PAIRED_BUILTIN_LX
:
13156 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
13159 /* Fall through. */
13162 /* Expand the paired predicates. */
13163 d
= bdesc_paired_preds
;
13164 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
13165 if (d
->code
== fcode
)
13166 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
13168 *expandedp
= false;
13172 /* Binops that need to be initialized manually, but can be expanded
13173 automagically by rs6000_expand_binop_builtin. */
13174 static const struct builtin_description bdesc_2arg_spe
[] =
13176 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
13177 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
13178 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
13179 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
13180 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
13181 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
13182 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
13183 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
13184 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
13185 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
13186 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
13187 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
13188 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
13189 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
13190 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
13191 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
13192 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
13193 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
13194 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
13195 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
13196 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
13197 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
13200 /* Expand the builtin in EXP and store the result in TARGET. Store
13201 true in *EXPANDEDP if we found a builtin to expand.
13203 This expands the SPE builtins that are not simple unary and binary
13206 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
13208 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13210 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13211 enum insn_code icode
;
13212 enum machine_mode tmode
, mode0
;
13214 const struct builtin_description
*d
;
13219 /* Syntax check for a 5-bit unsigned immediate. */
13222 case SPE_BUILTIN_EVSTDD
:
13223 case SPE_BUILTIN_EVSTDH
:
13224 case SPE_BUILTIN_EVSTDW
:
13225 case SPE_BUILTIN_EVSTWHE
:
13226 case SPE_BUILTIN_EVSTWHO
:
13227 case SPE_BUILTIN_EVSTWWE
:
13228 case SPE_BUILTIN_EVSTWWO
:
13229 arg1
= CALL_EXPR_ARG (exp
, 2);
13230 if (TREE_CODE (arg1
) != INTEGER_CST
13231 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
13233 error ("argument 2 must be a 5-bit unsigned literal");
13241 /* The evsplat*i instructions are not quite generic. */
13244 case SPE_BUILTIN_EVSPLATFI
:
13245 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
13247 case SPE_BUILTIN_EVSPLATI
:
13248 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
13254 d
= bdesc_2arg_spe
;
13255 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
13256 if (d
->code
== fcode
)
13257 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
13259 d
= bdesc_spe_predicates
;
13260 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
13261 if (d
->code
== fcode
)
13262 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
13264 d
= bdesc_spe_evsel
;
13265 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
13266 if (d
->code
== fcode
)
13267 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
13271 case SPE_BUILTIN_EVSTDDX
:
13272 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
13273 case SPE_BUILTIN_EVSTDHX
:
13274 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
13275 case SPE_BUILTIN_EVSTDWX
:
13276 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
13277 case SPE_BUILTIN_EVSTWHEX
:
13278 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
13279 case SPE_BUILTIN_EVSTWHOX
:
13280 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
13281 case SPE_BUILTIN_EVSTWWEX
:
13282 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
13283 case SPE_BUILTIN_EVSTWWOX
:
13284 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
13285 case SPE_BUILTIN_EVSTDD
:
13286 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
13287 case SPE_BUILTIN_EVSTDH
:
13288 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
13289 case SPE_BUILTIN_EVSTDW
:
13290 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
13291 case SPE_BUILTIN_EVSTWHE
:
13292 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
13293 case SPE_BUILTIN_EVSTWHO
:
13294 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
13295 case SPE_BUILTIN_EVSTWWE
:
13296 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
13297 case SPE_BUILTIN_EVSTWWO
:
13298 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
13299 case SPE_BUILTIN_MFSPEFSCR
:
13300 icode
= CODE_FOR_spe_mfspefscr
;
13301 tmode
= insn_data
[icode
].operand
[0].mode
;
13304 || GET_MODE (target
) != tmode
13305 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13306 target
= gen_reg_rtx (tmode
);
13308 pat
= GEN_FCN (icode
) (target
);
13313 case SPE_BUILTIN_MTSPEFSCR
:
13314 icode
= CODE_FOR_spe_mtspefscr
;
13315 arg0
= CALL_EXPR_ARG (exp
, 0);
13316 op0
= expand_normal (arg0
);
13317 mode0
= insn_data
[icode
].operand
[0].mode
;
13319 if (arg0
== error_mark_node
)
13322 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13323 op0
= copy_to_mode_reg (mode0
, op0
);
13325 pat
= GEN_FCN (icode
) (op0
);
13333 *expandedp
= false;
13338 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13340 rtx pat
, scratch
, tmp
;
13341 tree form
= CALL_EXPR_ARG (exp
, 0);
13342 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13343 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13344 rtx op0
= expand_normal (arg0
);
13345 rtx op1
= expand_normal (arg1
);
13346 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13347 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13349 enum rtx_code code
;
13351 if (TREE_CODE (form
) != INTEGER_CST
)
13353 error ("argument 1 of __builtin_paired_predicate must be a constant");
13357 form_int
= TREE_INT_CST_LOW (form
);
13359 gcc_assert (mode0
== mode1
);
13361 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13365 || GET_MODE (target
) != SImode
13366 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13367 target
= gen_reg_rtx (SImode
);
13368 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13369 op0
= copy_to_mode_reg (mode0
, op0
);
13370 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13371 op1
= copy_to_mode_reg (mode1
, op1
);
13373 scratch
= gen_reg_rtx (CCFPmode
);
13375 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13397 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
13400 error ("argument 1 of __builtin_paired_predicate is out of range");
13404 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
13405 emit_move_insn (target
, tmp
);
13410 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13412 rtx pat
, scratch
, tmp
;
13413 tree form
= CALL_EXPR_ARG (exp
, 0);
13414 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13415 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13416 rtx op0
= expand_normal (arg0
);
13417 rtx op1
= expand_normal (arg1
);
13418 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13419 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13421 enum rtx_code code
;
13423 if (TREE_CODE (form
) != INTEGER_CST
)
13425 error ("argument 1 of __builtin_spe_predicate must be a constant");
13429 form_int
= TREE_INT_CST_LOW (form
);
13431 gcc_assert (mode0
== mode1
);
13433 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13437 || GET_MODE (target
) != SImode
13438 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13439 target
= gen_reg_rtx (SImode
);
13441 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13442 op0
= copy_to_mode_reg (mode0
, op0
);
13443 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13444 op1
= copy_to_mode_reg (mode1
, op1
);
13446 scratch
= gen_reg_rtx (CCmode
);
13448 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13453 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
13454 _lower_. We use one compare, but look in different bits of the
13455 CR for each variant.
13457 There are 2 elements in each SPE simd type (upper/lower). The CR
13458 bits are set as follows:
13460 BIT0 | BIT 1 | BIT 2 | BIT 3
13461 U | L | (U | L) | (U & L)
13463 So, for an "all" relationship, BIT 3 would be set.
13464 For an "any" relationship, BIT 2 would be set. Etc.
13466 Following traditional nomenclature, these bits map to:
13468 BIT0 | BIT 1 | BIT 2 | BIT 3
13471 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
13476 /* All variant. OV bit. */
13478 /* We need to get to the OV bit, which is the ORDERED bit. We
13479 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
13480 that's ugly and will make validate_condition_mode die.
13481 So let's just use another pattern. */
13482 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
13484 /* Any variant. EQ bit. */
13488 /* Upper variant. LT bit. */
13492 /* Lower variant. GT bit. */
13497 error ("argument 1 of __builtin_spe_predicate is out of range");
13501 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
13502 emit_move_insn (target
, tmp
);
13507 /* The evsel builtins look like this:
13509 e = __builtin_spe_evsel_OP (a, b, c, d);
13511 and work like this:
13513 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
13514 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
13518 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
13521 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13522 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13523 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13524 tree arg3
= CALL_EXPR_ARG (exp
, 3);
13525 rtx op0
= expand_normal (arg0
);
13526 rtx op1
= expand_normal (arg1
);
13527 rtx op2
= expand_normal (arg2
);
13528 rtx op3
= expand_normal (arg3
);
13529 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13530 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13532 gcc_assert (mode0
== mode1
);
13534 if (arg0
== error_mark_node
|| arg1
== error_mark_node
13535 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
13539 || GET_MODE (target
) != mode0
13540 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
13541 target
= gen_reg_rtx (mode0
);
13543 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13544 op0
= copy_to_mode_reg (mode0
, op0
);
13545 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13546 op1
= copy_to_mode_reg (mode0
, op1
);
13547 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
13548 op2
= copy_to_mode_reg (mode0
, op2
);
13549 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
13550 op3
= copy_to_mode_reg (mode0
, op3
);
13552 /* Generate the compare. */
13553 scratch
= gen_reg_rtx (CCmode
);
13554 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13559 if (mode0
== V2SImode
)
13560 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
13562 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
13567 /* Raise an error message for a builtin function that is called without the
13568 appropriate target options being set. */
13571 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
13573 size_t uns_fncode
= (size_t)fncode
;
13574 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
13575 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
13577 gcc_assert (name
!= NULL
);
13578 if ((fnmask
& RS6000_BTM_CELL
) != 0)
13579 error ("Builtin function %s is only valid for the cell processor", name
);
13580 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
13581 error ("Builtin function %s requires the -mvsx option", name
);
13582 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
13583 error ("Builtin function %s requires the -mhtm option", name
);
13584 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
13585 error ("Builtin function %s requires the -maltivec option", name
);
13586 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
13587 error ("Builtin function %s requires the -mpaired option", name
);
13588 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
13589 error ("Builtin function %s requires the -mspe option", name
);
13590 else if ((fnmask
& (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
13591 == (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
13592 error ("Builtin function %s requires the -mhard-dfp and"
13593 " -mpower8-vector options", name
);
13594 else if ((fnmask
& RS6000_BTM_DFP
) != 0)
13595 error ("Builtin function %s requires the -mhard-dfp option", name
);
13596 else if ((fnmask
& RS6000_BTM_P8_VECTOR
) != 0)
13597 error ("Builtin function %s requires the -mpower8-vector option", name
);
13598 else if ((fnmask
& (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
13599 == (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
13600 error ("Builtin function %s requires the -mhard-float and"
13601 " -mlong-double-128 options", name
);
13602 else if ((fnmask
& RS6000_BTM_HARD_FLOAT
) != 0)
13603 error ("Builtin function %s requires the -mhard-float option", name
);
13605 error ("Builtin function %s is not supported with the current options",
13609 /* Expand an expression EXP that calls a built-in function,
13610 with result going to TARGET if that's convenient
13611 (and in mode MODE if that's convenient).
13612 SUBTARGET may be used as the target for computing one of EXP's operands.
13613 IGNORE is nonzero if the value is to be ignored. */
13616 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13617 enum machine_mode mode ATTRIBUTE_UNUSED
,
13618 int ignore ATTRIBUTE_UNUSED
)
13620 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13621 enum rs6000_builtins fcode
13622 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
13623 size_t uns_fcode
= (size_t)fcode
;
13624 const struct builtin_description
*d
;
13628 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
13629 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
13631 if (TARGET_DEBUG_BUILTIN
)
13633 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
13634 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
13635 const char *name2
= ((icode
!= CODE_FOR_nothing
)
13636 ? get_insn_name ((int)icode
)
13640 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
13642 default: name3
= "unknown"; break;
13643 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
13644 case RS6000_BTC_UNARY
: name3
= "unary"; break;
13645 case RS6000_BTC_BINARY
: name3
= "binary"; break;
13646 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
13647 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
13648 case RS6000_BTC_ABS
: name3
= "abs"; break;
13649 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
13650 case RS6000_BTC_DST
: name3
= "dst"; break;
13655 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
13656 (name1
) ? name1
: "---", fcode
,
13657 (name2
) ? name2
: "---", (int)icode
,
13659 func_valid_p
? "" : ", not valid");
13664 rs6000_invalid_builtin (fcode
);
13666 /* Given it is invalid, just generate a normal call. */
13667 return expand_call (exp
, target
, ignore
);
13672 case RS6000_BUILTIN_RECIP
:
13673 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
13675 case RS6000_BUILTIN_RECIPF
:
13676 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
13678 case RS6000_BUILTIN_RSQRTF
:
13679 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
13681 case RS6000_BUILTIN_RSQRT
:
13682 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
13684 case POWER7_BUILTIN_BPERMD
:
13685 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
13686 ? CODE_FOR_bpermd_di
13687 : CODE_FOR_bpermd_si
), exp
, target
);
13689 case RS6000_BUILTIN_GET_TB
:
13690 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
13693 case RS6000_BUILTIN_MFTB
:
13694 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
13695 ? CODE_FOR_rs6000_mftb_di
13696 : CODE_FOR_rs6000_mftb_si
),
13699 case RS6000_BUILTIN_MFFS
:
13700 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs
, target
);
13702 case RS6000_BUILTIN_MTFSF
:
13703 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf
, exp
);
13705 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
13706 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
13708 int icode
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr
13709 : (int) CODE_FOR_altivec_lvsl
);
13710 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13711 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
13715 gcc_assert (TARGET_ALTIVEC
);
13717 arg
= CALL_EXPR_ARG (exp
, 0);
13718 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
13719 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
13720 addr
= memory_address (mode
, op
);
13721 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
13725 /* For the load case need to negate the address. */
13726 op
= gen_reg_rtx (GET_MODE (addr
));
13727 emit_insn (gen_rtx_SET (VOIDmode
, op
,
13728 gen_rtx_NEG (GET_MODE (addr
), addr
)));
13730 op
= gen_rtx_MEM (mode
, op
);
13733 || GET_MODE (target
) != tmode
13734 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13735 target
= gen_reg_rtx (tmode
);
13737 /*pat = gen_altivec_lvsr (target, op);*/
13738 pat
= GEN_FCN (icode
) (target
, op
);
13746 case ALTIVEC_BUILTIN_VCFUX
:
13747 case ALTIVEC_BUILTIN_VCFSX
:
13748 case ALTIVEC_BUILTIN_VCTUXS
:
13749 case ALTIVEC_BUILTIN_VCTSXS
:
13750 /* FIXME: There's got to be a nicer way to handle this case than
13751 constructing a new CALL_EXPR. */
13752 if (call_expr_nargs (exp
) == 1)
13754 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
13755 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
13763 if (TARGET_ALTIVEC
)
13765 ret
= altivec_expand_builtin (exp
, target
, &success
);
13772 ret
= spe_expand_builtin (exp
, target
, &success
);
13777 if (TARGET_PAIRED_FLOAT
)
13779 ret
= paired_expand_builtin (exp
, target
, &success
);
13786 ret
= htm_expand_builtin (exp
, target
, &success
);
13792 unsigned attr
= rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
;
13793 gcc_assert (attr
== RS6000_BTC_UNARY
13794 || attr
== RS6000_BTC_BINARY
13795 || attr
== RS6000_BTC_TERNARY
);
13797 /* Handle simple unary operations. */
13799 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
13800 if (d
->code
== fcode
)
13801 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
13803 /* Handle simple binary operations. */
13805 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13806 if (d
->code
== fcode
)
13807 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
13809 /* Handle simple ternary operations. */
13811 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
13812 if (d
->code
== fcode
)
13813 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
13815 gcc_unreachable ();
13819 rs6000_init_builtins (void)
13823 enum machine_mode mode
;
13825 if (TARGET_DEBUG_BUILTIN
)
13826 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
13827 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
13828 (TARGET_SPE
) ? ", spe" : "",
13829 (TARGET_ALTIVEC
) ? ", altivec" : "",
13830 (TARGET_VSX
) ? ", vsx" : "");
13832 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
13833 V2SF_type_node
= build_vector_type (float_type_node
, 2);
13834 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
13835 V2DF_type_node
= build_vector_type (double_type_node
, 2);
13836 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
13837 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
13838 V4SF_type_node
= build_vector_type (float_type_node
, 4);
13839 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
13840 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
13842 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
13843 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
13844 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
13845 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
13847 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
13848 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
13849 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
13850 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
13852 /* We use V1TI mode as a special container to hold __int128_t items that
13853 must live in VSX registers. */
13854 if (intTI_type_node
)
13856 V1TI_type_node
= build_vector_type (intTI_type_node
, 1);
13857 unsigned_V1TI_type_node
= build_vector_type (unsigned_intTI_type_node
, 1);
13860 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
13861 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
13862 'vector unsigned short'. */
13864 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
13865 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
13866 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
13867 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
13868 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
13870 long_integer_type_internal_node
= long_integer_type_node
;
13871 long_unsigned_type_internal_node
= long_unsigned_type_node
;
13872 long_long_integer_type_internal_node
= long_long_integer_type_node
;
13873 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
13874 intQI_type_internal_node
= intQI_type_node
;
13875 uintQI_type_internal_node
= unsigned_intQI_type_node
;
13876 intHI_type_internal_node
= intHI_type_node
;
13877 uintHI_type_internal_node
= unsigned_intHI_type_node
;
13878 intSI_type_internal_node
= intSI_type_node
;
13879 uintSI_type_internal_node
= unsigned_intSI_type_node
;
13880 intDI_type_internal_node
= intDI_type_node
;
13881 uintDI_type_internal_node
= unsigned_intDI_type_node
;
13882 intTI_type_internal_node
= intTI_type_node
;
13883 uintTI_type_internal_node
= unsigned_intTI_type_node
;
13884 float_type_internal_node
= float_type_node
;
13885 double_type_internal_node
= double_type_node
;
13886 long_double_type_internal_node
= long_double_type_node
;
13887 dfloat64_type_internal_node
= dfloat64_type_node
;
13888 dfloat128_type_internal_node
= dfloat128_type_node
;
13889 void_type_internal_node
= void_type_node
;
13891 /* Initialize the modes for builtin_function_type, mapping a machine mode to
13893 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
13894 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
13895 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
13896 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
13897 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
13898 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
13899 builtin_mode_to_type
[TImode
][0] = intTI_type_node
;
13900 builtin_mode_to_type
[TImode
][1] = unsigned_intTI_type_node
;
13901 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
13902 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
13903 builtin_mode_to_type
[TFmode
][0] = long_double_type_node
;
13904 builtin_mode_to_type
[DDmode
][0] = dfloat64_type_node
;
13905 builtin_mode_to_type
[TDmode
][0] = dfloat128_type_node
;
13906 builtin_mode_to_type
[V1TImode
][0] = V1TI_type_node
;
13907 builtin_mode_to_type
[V1TImode
][1] = unsigned_V1TI_type_node
;
13908 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
13909 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
13910 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
13911 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
13912 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
13913 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
13914 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
13915 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
13916 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
13917 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
13918 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
13919 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
13920 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
13922 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
13923 TYPE_NAME (bool_char_type_node
) = tdecl
;
13925 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
13926 TYPE_NAME (bool_short_type_node
) = tdecl
;
13928 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
13929 TYPE_NAME (bool_int_type_node
) = tdecl
;
13931 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
13932 TYPE_NAME (pixel_type_node
) = tdecl
;
13934 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
13935 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
13936 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
13937 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
13938 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
13940 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
13941 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
13943 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
13944 TYPE_NAME (V16QI_type_node
) = tdecl
;
13946 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
13947 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
13949 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
13950 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
13952 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
13953 TYPE_NAME (V8HI_type_node
) = tdecl
;
13955 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
13956 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
13958 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
13959 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
13961 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
13962 TYPE_NAME (V4SI_type_node
) = tdecl
;
13964 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
13965 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
13967 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
13968 TYPE_NAME (V4SF_type_node
) = tdecl
;
13970 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
13971 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
13973 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
13974 TYPE_NAME (V2DF_type_node
) = tdecl
;
13976 if (TARGET_POWERPC64
)
13978 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
13979 TYPE_NAME (V2DI_type_node
) = tdecl
;
13981 tdecl
= add_builtin_type ("__vector unsigned long",
13982 unsigned_V2DI_type_node
);
13983 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
13985 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
13986 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
13990 tdecl
= add_builtin_type ("__vector long long", V2DI_type_node
);
13991 TYPE_NAME (V2DI_type_node
) = tdecl
;
13993 tdecl
= add_builtin_type ("__vector unsigned long long",
13994 unsigned_V2DI_type_node
);
13995 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
13997 tdecl
= add_builtin_type ("__vector __bool long long",
13998 bool_V2DI_type_node
);
13999 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
14002 if (V1TI_type_node
)
14004 tdecl
= add_builtin_type ("__vector __int128", V1TI_type_node
);
14005 TYPE_NAME (V1TI_type_node
) = tdecl
;
14007 tdecl
= add_builtin_type ("__vector unsigned __int128",
14008 unsigned_V1TI_type_node
);
14009 TYPE_NAME (unsigned_V1TI_type_node
) = tdecl
;
14012 /* Paired and SPE builtins are only available if you build a compiler with
14013 the appropriate options, so only create those builtins with the
14014 appropriate compiler option. Create Altivec and VSX builtins on machines
14015 with at least the general purpose extensions (970 and newer) to allow the
14016 use of the target attribute. */
14017 if (TARGET_PAIRED_FLOAT
)
14018 paired_init_builtins ();
14020 spe_init_builtins ();
14021 if (TARGET_EXTRA_BUILTINS
)
14022 altivec_init_builtins ();
14024 htm_init_builtins ();
14026 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
14027 rs6000_common_init_builtins ();
14029 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
14030 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
14031 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
14033 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
14034 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
14035 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
14037 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
14038 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
14039 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
14041 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
14042 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
14043 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
14045 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
14046 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
14047 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
14048 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
14050 ftype
= build_function_type_list (unsigned_intDI_type_node
,
14052 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
14055 ftype
= build_function_type_list (unsigned_intDI_type_node
,
14058 ftype
= build_function_type_list (unsigned_intSI_type_node
,
14060 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
14062 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
14063 def_builtin ("__builtin_mffs", ftype
, RS6000_BUILTIN_MFFS
);
14065 ftype
= build_function_type_list (void_type_node
,
14066 intSI_type_node
, double_type_node
,
14068 def_builtin ("__builtin_mtfsf", ftype
, RS6000_BUILTIN_MTFSF
);
14071 /* AIX libm provides clog as __clog. */
14072 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
14073 set_user_assembler_name (tdecl
, "__clog");
14076 #ifdef SUBTARGET_INIT_BUILTINS
14077 SUBTARGET_INIT_BUILTINS
;
14081 /* Returns the rs6000 builtin decl for CODE. */
14084 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
14086 HOST_WIDE_INT fnmask
;
14088 if (code
>= RS6000_BUILTIN_COUNT
)
14089 return error_mark_node
;
14091 fnmask
= rs6000_builtin_info
[code
].mask
;
14092 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
14094 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
14095 return error_mark_node
;
14098 return rs6000_builtin_decls
[code
];
14102 spe_init_builtins (void)
14104 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
14105 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
14106 const struct builtin_description
*d
;
14109 tree v2si_ftype_4_v2si
14110 = build_function_type_list (opaque_V2SI_type_node
,
14111 opaque_V2SI_type_node
,
14112 opaque_V2SI_type_node
,
14113 opaque_V2SI_type_node
,
14114 opaque_V2SI_type_node
,
14117 tree v2sf_ftype_4_v2sf
14118 = build_function_type_list (opaque_V2SF_type_node
,
14119 opaque_V2SF_type_node
,
14120 opaque_V2SF_type_node
,
14121 opaque_V2SF_type_node
,
14122 opaque_V2SF_type_node
,
14125 tree int_ftype_int_v2si_v2si
14126 = build_function_type_list (integer_type_node
,
14128 opaque_V2SI_type_node
,
14129 opaque_V2SI_type_node
,
14132 tree int_ftype_int_v2sf_v2sf
14133 = build_function_type_list (integer_type_node
,
14135 opaque_V2SF_type_node
,
14136 opaque_V2SF_type_node
,
14139 tree void_ftype_v2si_puint_int
14140 = build_function_type_list (void_type_node
,
14141 opaque_V2SI_type_node
,
14146 tree void_ftype_v2si_puint_char
14147 = build_function_type_list (void_type_node
,
14148 opaque_V2SI_type_node
,
14153 tree void_ftype_v2si_pv2si_int
14154 = build_function_type_list (void_type_node
,
14155 opaque_V2SI_type_node
,
14156 opaque_p_V2SI_type_node
,
14160 tree void_ftype_v2si_pv2si_char
14161 = build_function_type_list (void_type_node
,
14162 opaque_V2SI_type_node
,
14163 opaque_p_V2SI_type_node
,
14167 tree void_ftype_int
14168 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
14170 tree int_ftype_void
14171 = build_function_type_list (integer_type_node
, NULL_TREE
);
14173 tree v2si_ftype_pv2si_int
14174 = build_function_type_list (opaque_V2SI_type_node
,
14175 opaque_p_V2SI_type_node
,
14179 tree v2si_ftype_puint_int
14180 = build_function_type_list (opaque_V2SI_type_node
,
14185 tree v2si_ftype_pushort_int
14186 = build_function_type_list (opaque_V2SI_type_node
,
14191 tree v2si_ftype_signed_char
14192 = build_function_type_list (opaque_V2SI_type_node
,
14193 signed_char_type_node
,
14196 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
14198 /* Initialize irregular SPE builtins. */
14200 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
14201 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
14202 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
14203 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
14204 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
14205 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
14206 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
14207 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
14208 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
14209 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
14210 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
14211 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
14212 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
14213 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
14214 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
14215 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
14216 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
14217 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
14220 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
14221 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
14222 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
14223 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
14224 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
14225 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
14226 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
14227 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
14228 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
14229 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
14230 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
14231 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
14232 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
14233 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
14234 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
14235 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
14236 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
14237 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
14238 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
14239 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
14240 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
14241 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
14244 d
= bdesc_spe_predicates
;
14245 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
14249 switch (insn_data
[d
->icode
].operand
[1].mode
)
14252 type
= int_ftype_int_v2si_v2si
;
14255 type
= int_ftype_int_v2sf_v2sf
;
14258 gcc_unreachable ();
14261 def_builtin (d
->name
, type
, d
->code
);
14264 /* Evsel predicates. */
14265 d
= bdesc_spe_evsel
;
14266 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
14270 switch (insn_data
[d
->icode
].operand
[1].mode
)
14273 type
= v2si_ftype_4_v2si
;
14276 type
= v2sf_ftype_4_v2sf
;
14279 gcc_unreachable ();
14282 def_builtin (d
->name
, type
, d
->code
);
14287 paired_init_builtins (void)
14289 const struct builtin_description
*d
;
14292 tree int_ftype_int_v2sf_v2sf
14293 = build_function_type_list (integer_type_node
,
14298 tree pcfloat_type_node
=
14299 build_pointer_type (build_qualified_type
14300 (float_type_node
, TYPE_QUAL_CONST
));
14302 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
14303 long_integer_type_node
,
14306 tree void_ftype_v2sf_long_pcfloat
=
14307 build_function_type_list (void_type_node
,
14309 long_integer_type_node
,
14314 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
14315 PAIRED_BUILTIN_LX
);
14318 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
14319 PAIRED_BUILTIN_STX
);
14322 d
= bdesc_paired_preds
;
14323 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
14327 if (TARGET_DEBUG_BUILTIN
)
14328 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
14329 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
14330 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
14332 switch (insn_data
[d
->icode
].operand
[1].mode
)
14335 type
= int_ftype_int_v2sf_v2sf
;
14338 gcc_unreachable ();
14341 def_builtin (d
->name
, type
, d
->code
);
14346 altivec_init_builtins (void)
14348 const struct builtin_description
*d
;
14353 tree pvoid_type_node
= build_pointer_type (void_type_node
);
14355 tree pcvoid_type_node
14356 = build_pointer_type (build_qualified_type (void_type_node
,
14359 tree int_ftype_opaque
14360 = build_function_type_list (integer_type_node
,
14361 opaque_V4SI_type_node
, NULL_TREE
);
14362 tree opaque_ftype_opaque
14363 = build_function_type_list (integer_type_node
, NULL_TREE
);
14364 tree opaque_ftype_opaque_int
14365 = build_function_type_list (opaque_V4SI_type_node
,
14366 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
14367 tree opaque_ftype_opaque_opaque_int
14368 = build_function_type_list (opaque_V4SI_type_node
,
14369 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
14370 integer_type_node
, NULL_TREE
);
14371 tree int_ftype_int_opaque_opaque
14372 = build_function_type_list (integer_type_node
,
14373 integer_type_node
, opaque_V4SI_type_node
,
14374 opaque_V4SI_type_node
, NULL_TREE
);
14375 tree int_ftype_int_v4si_v4si
14376 = build_function_type_list (integer_type_node
,
14377 integer_type_node
, V4SI_type_node
,
14378 V4SI_type_node
, NULL_TREE
);
14379 tree int_ftype_int_v2di_v2di
14380 = build_function_type_list (integer_type_node
,
14381 integer_type_node
, V2DI_type_node
,
14382 V2DI_type_node
, NULL_TREE
);
14383 tree void_ftype_v4si
14384 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
14385 tree v8hi_ftype_void
14386 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
14387 tree void_ftype_void
14388 = build_function_type_list (void_type_node
, NULL_TREE
);
14389 tree void_ftype_int
14390 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
14392 tree opaque_ftype_long_pcvoid
14393 = build_function_type_list (opaque_V4SI_type_node
,
14394 long_integer_type_node
, pcvoid_type_node
,
14396 tree v16qi_ftype_long_pcvoid
14397 = build_function_type_list (V16QI_type_node
,
14398 long_integer_type_node
, pcvoid_type_node
,
14400 tree v8hi_ftype_long_pcvoid
14401 = build_function_type_list (V8HI_type_node
,
14402 long_integer_type_node
, pcvoid_type_node
,
14404 tree v4si_ftype_long_pcvoid
14405 = build_function_type_list (V4SI_type_node
,
14406 long_integer_type_node
, pcvoid_type_node
,
14408 tree v4sf_ftype_long_pcvoid
14409 = build_function_type_list (V4SF_type_node
,
14410 long_integer_type_node
, pcvoid_type_node
,
14412 tree v2df_ftype_long_pcvoid
14413 = build_function_type_list (V2DF_type_node
,
14414 long_integer_type_node
, pcvoid_type_node
,
14416 tree v2di_ftype_long_pcvoid
14417 = build_function_type_list (V2DI_type_node
,
14418 long_integer_type_node
, pcvoid_type_node
,
14421 tree void_ftype_opaque_long_pvoid
14422 = build_function_type_list (void_type_node
,
14423 opaque_V4SI_type_node
, long_integer_type_node
,
14424 pvoid_type_node
, NULL_TREE
);
14425 tree void_ftype_v4si_long_pvoid
14426 = build_function_type_list (void_type_node
,
14427 V4SI_type_node
, long_integer_type_node
,
14428 pvoid_type_node
, NULL_TREE
);
14429 tree void_ftype_v16qi_long_pvoid
14430 = build_function_type_list (void_type_node
,
14431 V16QI_type_node
, long_integer_type_node
,
14432 pvoid_type_node
, NULL_TREE
);
14433 tree void_ftype_v8hi_long_pvoid
14434 = build_function_type_list (void_type_node
,
14435 V8HI_type_node
, long_integer_type_node
,
14436 pvoid_type_node
, NULL_TREE
);
14437 tree void_ftype_v4sf_long_pvoid
14438 = build_function_type_list (void_type_node
,
14439 V4SF_type_node
, long_integer_type_node
,
14440 pvoid_type_node
, NULL_TREE
);
14441 tree void_ftype_v2df_long_pvoid
14442 = build_function_type_list (void_type_node
,
14443 V2DF_type_node
, long_integer_type_node
,
14444 pvoid_type_node
, NULL_TREE
);
14445 tree void_ftype_v2di_long_pvoid
14446 = build_function_type_list (void_type_node
,
14447 V2DI_type_node
, long_integer_type_node
,
14448 pvoid_type_node
, NULL_TREE
);
14449 tree int_ftype_int_v8hi_v8hi
14450 = build_function_type_list (integer_type_node
,
14451 integer_type_node
, V8HI_type_node
,
14452 V8HI_type_node
, NULL_TREE
);
14453 tree int_ftype_int_v16qi_v16qi
14454 = build_function_type_list (integer_type_node
,
14455 integer_type_node
, V16QI_type_node
,
14456 V16QI_type_node
, NULL_TREE
);
14457 tree int_ftype_int_v4sf_v4sf
14458 = build_function_type_list (integer_type_node
,
14459 integer_type_node
, V4SF_type_node
,
14460 V4SF_type_node
, NULL_TREE
);
14461 tree int_ftype_int_v2df_v2df
14462 = build_function_type_list (integer_type_node
,
14463 integer_type_node
, V2DF_type_node
,
14464 V2DF_type_node
, NULL_TREE
);
14465 tree v2di_ftype_v2di
14466 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
14467 tree v4si_ftype_v4si
14468 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
14469 tree v8hi_ftype_v8hi
14470 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
14471 tree v16qi_ftype_v16qi
14472 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
14473 tree v4sf_ftype_v4sf
14474 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
14475 tree v2df_ftype_v2df
14476 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
14477 tree void_ftype_pcvoid_int_int
14478 = build_function_type_list (void_type_node
,
14479 pcvoid_type_node
, integer_type_node
,
14480 integer_type_node
, NULL_TREE
);
14482 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
14483 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
14484 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
14485 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
14486 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
14487 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
14488 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
14489 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
14490 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
14491 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
14492 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid
,
14493 ALTIVEC_BUILTIN_LVXL_V2DF
);
14494 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid
,
14495 ALTIVEC_BUILTIN_LVXL_V2DI
);
14496 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid
,
14497 ALTIVEC_BUILTIN_LVXL_V4SF
);
14498 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid
,
14499 ALTIVEC_BUILTIN_LVXL_V4SI
);
14500 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid
,
14501 ALTIVEC_BUILTIN_LVXL_V8HI
);
14502 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid
,
14503 ALTIVEC_BUILTIN_LVXL_V16QI
);
14504 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
14505 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid
,
14506 ALTIVEC_BUILTIN_LVX_V2DF
);
14507 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid
,
14508 ALTIVEC_BUILTIN_LVX_V2DI
);
14509 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid
,
14510 ALTIVEC_BUILTIN_LVX_V4SF
);
14511 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid
,
14512 ALTIVEC_BUILTIN_LVX_V4SI
);
14513 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid
,
14514 ALTIVEC_BUILTIN_LVX_V8HI
);
14515 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid
,
14516 ALTIVEC_BUILTIN_LVX_V16QI
);
14517 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
14518 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid
,
14519 ALTIVEC_BUILTIN_STVX_V2DF
);
14520 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid
,
14521 ALTIVEC_BUILTIN_STVX_V2DI
);
14522 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid
,
14523 ALTIVEC_BUILTIN_STVX_V4SF
);
14524 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid
,
14525 ALTIVEC_BUILTIN_STVX_V4SI
);
14526 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid
,
14527 ALTIVEC_BUILTIN_STVX_V8HI
);
14528 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid
,
14529 ALTIVEC_BUILTIN_STVX_V16QI
);
14530 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
14531 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
14532 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid
,
14533 ALTIVEC_BUILTIN_STVXL_V2DF
);
14534 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid
,
14535 ALTIVEC_BUILTIN_STVXL_V2DI
);
14536 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid
,
14537 ALTIVEC_BUILTIN_STVXL_V4SF
);
14538 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid
,
14539 ALTIVEC_BUILTIN_STVXL_V4SI
);
14540 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid
,
14541 ALTIVEC_BUILTIN_STVXL_V8HI
);
14542 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid
,
14543 ALTIVEC_BUILTIN_STVXL_V16QI
);
14544 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
14545 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
14546 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
14547 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
14548 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
14549 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
14550 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
14551 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
14552 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
14553 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
14554 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
14555 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
14556 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
14557 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
14558 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
14559 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
14561 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
14562 VSX_BUILTIN_LXVD2X_V2DF
);
14563 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
14564 VSX_BUILTIN_LXVD2X_V2DI
);
14565 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
14566 VSX_BUILTIN_LXVW4X_V4SF
);
14567 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
14568 VSX_BUILTIN_LXVW4X_V4SI
);
14569 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
14570 VSX_BUILTIN_LXVW4X_V8HI
);
14571 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
14572 VSX_BUILTIN_LXVW4X_V16QI
);
14573 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
14574 VSX_BUILTIN_STXVD2X_V2DF
);
14575 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
14576 VSX_BUILTIN_STXVD2X_V2DI
);
14577 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
14578 VSX_BUILTIN_STXVW4X_V4SF
);
14579 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
14580 VSX_BUILTIN_STXVW4X_V4SI
);
14581 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
14582 VSX_BUILTIN_STXVW4X_V8HI
);
14583 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
14584 VSX_BUILTIN_STXVW4X_V16QI
);
14585 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
14586 VSX_BUILTIN_VEC_LD
);
14587 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
14588 VSX_BUILTIN_VEC_ST
);
14590 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
14591 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
14592 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
14594 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
14595 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
14596 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
14597 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
14598 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
14599 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
14600 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
14601 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
14602 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
14603 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
14604 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
14605 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
14607 /* Cell builtins. */
14608 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
14609 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
14610 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
14611 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
14613 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
14614 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
14615 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
14616 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
14618 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
14619 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
14620 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
14621 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
14623 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
14624 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
14625 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
14626 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
14628 /* Add the DST variants. */
14630 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
14631 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
14633 /* Initialize the predicates. */
14634 d
= bdesc_altivec_preds
;
14635 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
14637 enum machine_mode mode1
;
14640 if (rs6000_overloaded_builtin_p (d
->code
))
14643 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
14648 type
= int_ftype_int_opaque_opaque
;
14651 type
= int_ftype_int_v2di_v2di
;
14654 type
= int_ftype_int_v4si_v4si
;
14657 type
= int_ftype_int_v8hi_v8hi
;
14660 type
= int_ftype_int_v16qi_v16qi
;
14663 type
= int_ftype_int_v4sf_v4sf
;
14666 type
= int_ftype_int_v2df_v2df
;
14669 gcc_unreachable ();
14672 def_builtin (d
->name
, type
, d
->code
);
14675 /* Initialize the abs* operators. */
14677 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
14679 enum machine_mode mode0
;
14682 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
14687 type
= v2di_ftype_v2di
;
14690 type
= v4si_ftype_v4si
;
14693 type
= v8hi_ftype_v8hi
;
14696 type
= v16qi_ftype_v16qi
;
14699 type
= v4sf_ftype_v4sf
;
14702 type
= v2df_ftype_v2df
;
14705 gcc_unreachable ();
14708 def_builtin (d
->name
, type
, d
->code
);
14711 /* Initialize target builtin that implements
14712 targetm.vectorize.builtin_mask_for_load. */
14714 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
14715 v16qi_ftype_long_pcvoid
,
14716 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
14717 BUILT_IN_MD
, NULL
, NULL_TREE
);
14718 TREE_READONLY (decl
) = 1;
14719 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
14720 altivec_builtin_mask_for_load
= decl
;
14722 /* Access to the vec_init patterns. */
14723 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
14724 integer_type_node
, integer_type_node
,
14725 integer_type_node
, NULL_TREE
);
14726 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
14728 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
14729 short_integer_type_node
,
14730 short_integer_type_node
,
14731 short_integer_type_node
,
14732 short_integer_type_node
,
14733 short_integer_type_node
,
14734 short_integer_type_node
,
14735 short_integer_type_node
, NULL_TREE
);
14736 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
14738 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
14739 char_type_node
, char_type_node
,
14740 char_type_node
, char_type_node
,
14741 char_type_node
, char_type_node
,
14742 char_type_node
, char_type_node
,
14743 char_type_node
, char_type_node
,
14744 char_type_node
, char_type_node
,
14745 char_type_node
, char_type_node
,
14746 char_type_node
, NULL_TREE
);
14747 def_builtin ("__builtin_vec_init_v16qi", ftype
,
14748 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
14750 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
14751 float_type_node
, float_type_node
,
14752 float_type_node
, NULL_TREE
);
14753 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
14755 /* VSX builtins. */
14756 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
14757 double_type_node
, NULL_TREE
);
14758 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
14760 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
14761 intDI_type_node
, NULL_TREE
);
14762 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
14764 /* Access to the vec_set patterns. */
14765 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
14767 integer_type_node
, NULL_TREE
);
14768 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
14770 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
14772 integer_type_node
, NULL_TREE
);
14773 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
14775 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
14777 integer_type_node
, NULL_TREE
);
14778 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
14780 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
14782 integer_type_node
, NULL_TREE
);
14783 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
14785 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
14787 integer_type_node
, NULL_TREE
);
14788 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
14790 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
14792 integer_type_node
, NULL_TREE
);
14793 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
14795 /* Access to the vec_extract patterns. */
14796 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
14797 integer_type_node
, NULL_TREE
);
14798 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
14800 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
14801 integer_type_node
, NULL_TREE
);
14802 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
14804 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
14805 integer_type_node
, NULL_TREE
);
14806 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
14808 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
14809 integer_type_node
, NULL_TREE
);
14810 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
14812 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
14813 integer_type_node
, NULL_TREE
);
14814 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
14816 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
14817 integer_type_node
, NULL_TREE
);
14818 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
14821 if (V1TI_type_node
)
14823 tree v1ti_ftype_long_pcvoid
14824 = build_function_type_list (V1TI_type_node
,
14825 long_integer_type_node
, pcvoid_type_node
,
14827 tree void_ftype_v1ti_long_pvoid
14828 = build_function_type_list (void_type_node
,
14829 V1TI_type_node
, long_integer_type_node
,
14830 pvoid_type_node
, NULL_TREE
);
14831 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid
,
14832 VSX_BUILTIN_LXVD2X_V1TI
);
14833 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid
,
14834 VSX_BUILTIN_STXVD2X_V1TI
);
14835 ftype
= build_function_type_list (V1TI_type_node
, intTI_type_node
,
14836 NULL_TREE
, NULL_TREE
);
14837 def_builtin ("__builtin_vec_init_v1ti", ftype
, VSX_BUILTIN_VEC_INIT_V1TI
);
14838 ftype
= build_function_type_list (V1TI_type_node
, V1TI_type_node
,
14840 integer_type_node
, NULL_TREE
);
14841 def_builtin ("__builtin_vec_set_v1ti", ftype
, VSX_BUILTIN_VEC_SET_V1TI
);
14842 ftype
= build_function_type_list (intTI_type_node
, V1TI_type_node
,
14843 integer_type_node
, NULL_TREE
);
14844 def_builtin ("__builtin_vec_ext_v1ti", ftype
, VSX_BUILTIN_VEC_EXT_V1TI
);
14850 htm_init_builtins (void)
14852 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
14853 const struct builtin_description
*d
;
14857 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
14859 tree op
[MAX_HTM_OPERANDS
], type
;
14860 HOST_WIDE_INT mask
= d
->mask
;
14861 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
14862 bool void_func
= (attr
& RS6000_BTC_VOID
);
14863 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
14865 tree argtype
= (attr
& RS6000_BTC_SPR
) ? long_unsigned_type_node
14866 : unsigned_type_node
;
14868 if ((mask
& builtin_mask
) != mask
)
14870 if (TARGET_DEBUG_BUILTIN
)
14871 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
14877 if (TARGET_DEBUG_BUILTIN
)
14878 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
14879 (long unsigned) i
);
14883 op
[nopnds
++] = (void_func
) ? void_type_node
: argtype
;
14885 if (attr_args
== RS6000_BTC_UNARY
)
14886 op
[nopnds
++] = argtype
;
14887 else if (attr_args
== RS6000_BTC_BINARY
)
14889 op
[nopnds
++] = argtype
;
14890 op
[nopnds
++] = argtype
;
14892 else if (attr_args
== RS6000_BTC_TERNARY
)
14894 op
[nopnds
++] = argtype
;
14895 op
[nopnds
++] = argtype
;
14896 op
[nopnds
++] = argtype
;
14902 type
= build_function_type_list (op
[0], NULL_TREE
);
14905 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
14908 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
14911 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
14915 gcc_unreachable ();
14918 def_builtin (d
->name
, type
, d
->code
);
14922 /* Hash function for builtin functions with up to 3 arguments and a return
14925 builtin_hash_function (const void *hash_entry
)
14929 const struct builtin_hash_struct
*bh
=
14930 (const struct builtin_hash_struct
*) hash_entry
;
14932 for (i
= 0; i
< 4; i
++)
14934 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
14935 ret
= (ret
* 2) + bh
->uns_p
[i
];
14941 /* Compare builtin hash entries H1 and H2 for equivalence. */
14943 builtin_hash_eq (const void *h1
, const void *h2
)
14945 const struct builtin_hash_struct
*p1
= (const struct builtin_hash_struct
*) h1
;
14946 const struct builtin_hash_struct
*p2
= (const struct builtin_hash_struct
*) h2
;
14948 return ((p1
->mode
[0] == p2
->mode
[0])
14949 && (p1
->mode
[1] == p2
->mode
[1])
14950 && (p1
->mode
[2] == p2
->mode
[2])
14951 && (p1
->mode
[3] == p2
->mode
[3])
14952 && (p1
->uns_p
[0] == p2
->uns_p
[0])
14953 && (p1
->uns_p
[1] == p2
->uns_p
[1])
14954 && (p1
->uns_p
[2] == p2
->uns_p
[2])
14955 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
14958 /* Map types for builtin functions with an explicit return type and up to 3
14959 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
14960 of the argument. */
14962 builtin_function_type (enum machine_mode mode_ret
, enum machine_mode mode_arg0
,
14963 enum machine_mode mode_arg1
, enum machine_mode mode_arg2
,
14964 enum rs6000_builtins builtin
, const char *name
)
14966 struct builtin_hash_struct h
;
14967 struct builtin_hash_struct
*h2
;
14971 tree ret_type
= NULL_TREE
;
14972 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
14974 /* Create builtin_hash_table. */
14975 if (builtin_hash_table
== NULL
)
14976 builtin_hash_table
= htab_create_ggc (1500, builtin_hash_function
,
14977 builtin_hash_eq
, NULL
);
14979 h
.type
= NULL_TREE
;
14980 h
.mode
[0] = mode_ret
;
14981 h
.mode
[1] = mode_arg0
;
14982 h
.mode
[2] = mode_arg1
;
14983 h
.mode
[3] = mode_arg2
;
14989 /* If the builtin is a type that produces unsigned results or takes unsigned
14990 arguments, and it is returned as a decl for the vectorizer (such as
14991 widening multiplies, permute), make sure the arguments and return value
14992 are type correct. */
14995 /* unsigned 1 argument functions. */
14996 case CRYPTO_BUILTIN_VSBOX
:
14997 case P8V_BUILTIN_VGBBD
:
14998 case MISC_BUILTIN_CDTBCD
:
14999 case MISC_BUILTIN_CBCDTD
:
15004 /* unsigned 2 argument functions. */
15005 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
15006 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
15007 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
15008 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
15009 case CRYPTO_BUILTIN_VCIPHER
:
15010 case CRYPTO_BUILTIN_VCIPHERLAST
:
15011 case CRYPTO_BUILTIN_VNCIPHER
:
15012 case CRYPTO_BUILTIN_VNCIPHERLAST
:
15013 case CRYPTO_BUILTIN_VPMSUMB
:
15014 case CRYPTO_BUILTIN_VPMSUMH
:
15015 case CRYPTO_BUILTIN_VPMSUMW
:
15016 case CRYPTO_BUILTIN_VPMSUMD
:
15017 case CRYPTO_BUILTIN_VPMSUM
:
15018 case MISC_BUILTIN_ADDG6S
:
15019 case MISC_BUILTIN_DIVWEU
:
15020 case MISC_BUILTIN_DIVWEUO
:
15021 case MISC_BUILTIN_DIVDEU
:
15022 case MISC_BUILTIN_DIVDEUO
:
15028 /* unsigned 3 argument functions. */
15029 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
15030 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
15031 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
15032 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
15033 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
15034 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
15035 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
15036 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
15037 case VSX_BUILTIN_VPERM_16QI_UNS
:
15038 case VSX_BUILTIN_VPERM_8HI_UNS
:
15039 case VSX_BUILTIN_VPERM_4SI_UNS
:
15040 case VSX_BUILTIN_VPERM_2DI_UNS
:
15041 case VSX_BUILTIN_XXSEL_16QI_UNS
:
15042 case VSX_BUILTIN_XXSEL_8HI_UNS
:
15043 case VSX_BUILTIN_XXSEL_4SI_UNS
:
15044 case VSX_BUILTIN_XXSEL_2DI_UNS
:
15045 case CRYPTO_BUILTIN_VPERMXOR
:
15046 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
15047 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
15048 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
15049 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
15050 case CRYPTO_BUILTIN_VSHASIGMAW
:
15051 case CRYPTO_BUILTIN_VSHASIGMAD
:
15052 case CRYPTO_BUILTIN_VSHASIGMA
:
15059 /* signed permute functions with unsigned char mask. */
15060 case ALTIVEC_BUILTIN_VPERM_16QI
:
15061 case ALTIVEC_BUILTIN_VPERM_8HI
:
15062 case ALTIVEC_BUILTIN_VPERM_4SI
:
15063 case ALTIVEC_BUILTIN_VPERM_4SF
:
15064 case ALTIVEC_BUILTIN_VPERM_2DI
:
15065 case ALTIVEC_BUILTIN_VPERM_2DF
:
15066 case VSX_BUILTIN_VPERM_16QI
:
15067 case VSX_BUILTIN_VPERM_8HI
:
15068 case VSX_BUILTIN_VPERM_4SI
:
15069 case VSX_BUILTIN_VPERM_4SF
:
15070 case VSX_BUILTIN_VPERM_2DI
:
15071 case VSX_BUILTIN_VPERM_2DF
:
15075 /* unsigned args, signed return. */
15076 case VSX_BUILTIN_XVCVUXDDP_UNS
:
15077 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
15081 /* signed args, unsigned return. */
15082 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
15083 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
15084 case MISC_BUILTIN_UNPACK_TD
:
15085 case MISC_BUILTIN_UNPACK_V1TI
:
15089 /* unsigned arguments for 128-bit pack instructions. */
15090 case MISC_BUILTIN_PACK_TD
:
15091 case MISC_BUILTIN_PACK_V1TI
:
15100 /* Figure out how many args are present. */
15101 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
15105 fatal_error ("internal error: builtin function %s had no type", name
);
15107 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
15108 if (!ret_type
&& h
.uns_p
[0])
15109 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
15112 fatal_error ("internal error: builtin function %s had an unexpected "
15113 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
15115 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
15116 arg_type
[i
] = NULL_TREE
;
15118 for (i
= 0; i
< num_args
; i
++)
15120 int m
= (int) h
.mode
[i
+1];
15121 int uns_p
= h
.uns_p
[i
+1];
15123 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
15124 if (!arg_type
[i
] && uns_p
)
15125 arg_type
[i
] = builtin_mode_to_type
[m
][0];
15128 fatal_error ("internal error: builtin function %s, argument %d "
15129 "had unexpected argument type %s", name
, i
,
15130 GET_MODE_NAME (m
));
15133 found
= htab_find_slot (builtin_hash_table
, &h
, INSERT
);
15134 if (*found
== NULL
)
15136 h2
= ggc_alloc
<builtin_hash_struct
> ();
15138 *found
= (void *)h2
;
15140 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
15141 arg_type
[2], NULL_TREE
);
15144 return ((struct builtin_hash_struct
*)(*found
))->type
;
15148 rs6000_common_init_builtins (void)
15150 const struct builtin_description
*d
;
15153 tree opaque_ftype_opaque
= NULL_TREE
;
15154 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
15155 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
15156 tree v2si_ftype_qi
= NULL_TREE
;
15157 tree v2si_ftype_v2si_qi
= NULL_TREE
;
15158 tree v2si_ftype_int_qi
= NULL_TREE
;
15159 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
15161 if (!TARGET_PAIRED_FLOAT
)
15163 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
15164 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
15167 /* Paired and SPE builtins are only available if you build a compiler with
15168 the appropriate options, so only create those builtins with the
15169 appropriate compiler option. Create Altivec and VSX builtins on machines
15170 with at least the general purpose extensions (970 and newer) to allow the
15171 use of the target attribute.. */
15173 if (TARGET_EXTRA_BUILTINS
)
15174 builtin_mask
|= RS6000_BTM_COMMON
;
15176 /* Add the ternary operators. */
15178 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
15181 HOST_WIDE_INT mask
= d
->mask
;
15183 if ((mask
& builtin_mask
) != mask
)
15185 if (TARGET_DEBUG_BUILTIN
)
15186 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
15190 if (rs6000_overloaded_builtin_p (d
->code
))
15192 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
15193 type
= opaque_ftype_opaque_opaque_opaque
15194 = build_function_type_list (opaque_V4SI_type_node
,
15195 opaque_V4SI_type_node
,
15196 opaque_V4SI_type_node
,
15197 opaque_V4SI_type_node
,
15202 enum insn_code icode
= d
->icode
;
15205 if (TARGET_DEBUG_BUILTIN
)
15206 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
15212 if (icode
== CODE_FOR_nothing
)
15214 if (TARGET_DEBUG_BUILTIN
)
15215 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
15221 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
15222 insn_data
[icode
].operand
[1].mode
,
15223 insn_data
[icode
].operand
[2].mode
,
15224 insn_data
[icode
].operand
[3].mode
,
15228 def_builtin (d
->name
, type
, d
->code
);
15231 /* Add the binary operators. */
15233 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
15235 enum machine_mode mode0
, mode1
, mode2
;
15237 HOST_WIDE_INT mask
= d
->mask
;
15239 if ((mask
& builtin_mask
) != mask
)
15241 if (TARGET_DEBUG_BUILTIN
)
15242 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
15246 if (rs6000_overloaded_builtin_p (d
->code
))
15248 if (! (type
= opaque_ftype_opaque_opaque
))
15249 type
= opaque_ftype_opaque_opaque
15250 = build_function_type_list (opaque_V4SI_type_node
,
15251 opaque_V4SI_type_node
,
15252 opaque_V4SI_type_node
,
15257 enum insn_code icode
= d
->icode
;
15260 if (TARGET_DEBUG_BUILTIN
)
15261 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
15267 if (icode
== CODE_FOR_nothing
)
15269 if (TARGET_DEBUG_BUILTIN
)
15270 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
15276 mode0
= insn_data
[icode
].operand
[0].mode
;
15277 mode1
= insn_data
[icode
].operand
[1].mode
;
15278 mode2
= insn_data
[icode
].operand
[2].mode
;
15280 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
15282 if (! (type
= v2si_ftype_v2si_qi
))
15283 type
= v2si_ftype_v2si_qi
15284 = build_function_type_list (opaque_V2SI_type_node
,
15285 opaque_V2SI_type_node
,
15290 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
15291 && mode2
== QImode
)
15293 if (! (type
= v2si_ftype_int_qi
))
15294 type
= v2si_ftype_int_qi
15295 = build_function_type_list (opaque_V2SI_type_node
,
15302 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
15306 def_builtin (d
->name
, type
, d
->code
);
15309 /* Add the simple unary operators. */
15311 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
15313 enum machine_mode mode0
, mode1
;
15315 HOST_WIDE_INT mask
= d
->mask
;
15317 if ((mask
& builtin_mask
) != mask
)
15319 if (TARGET_DEBUG_BUILTIN
)
15320 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
15324 if (rs6000_overloaded_builtin_p (d
->code
))
15326 if (! (type
= opaque_ftype_opaque
))
15327 type
= opaque_ftype_opaque
15328 = build_function_type_list (opaque_V4SI_type_node
,
15329 opaque_V4SI_type_node
,
15334 enum insn_code icode
= d
->icode
;
15337 if (TARGET_DEBUG_BUILTIN
)
15338 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
15344 if (icode
== CODE_FOR_nothing
)
15346 if (TARGET_DEBUG_BUILTIN
)
15347 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
15353 mode0
= insn_data
[icode
].operand
[0].mode
;
15354 mode1
= insn_data
[icode
].operand
[1].mode
;
15356 if (mode0
== V2SImode
&& mode1
== QImode
)
15358 if (! (type
= v2si_ftype_qi
))
15359 type
= v2si_ftype_qi
15360 = build_function_type_list (opaque_V2SI_type_node
,
15366 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
15370 def_builtin (d
->name
, type
, d
->code
);
15375 rs6000_init_libfuncs (void)
15377 if (!TARGET_IEEEQUAD
)
15378 /* AIX/Darwin/64-bit Linux quad floating point routines. */
15379 if (!TARGET_XL_COMPAT
)
15381 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
15382 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
15383 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
15384 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
15386 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
15388 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
15389 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
15390 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
15391 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
15392 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
15393 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
15394 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
15396 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
15397 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
15398 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
15399 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
15400 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
15401 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
15402 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
15403 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
15406 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
15407 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
15411 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
15412 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
15413 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
15414 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
15418 /* 32-bit SVR4 quad floating point routines. */
15420 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
15421 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
15422 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
15423 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
15424 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
15425 if (TARGET_PPC_GPOPT
)
15426 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
15428 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
15429 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
15430 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
15431 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
15432 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
15433 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
15435 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
15436 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
15437 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
15438 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
15439 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
15440 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
15441 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
15442 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
15447 /* Expand a block clear operation, and return 1 if successful. Return 0
15448 if we should let the compiler generate normal code.
15450 operands[0] is the destination
15451 operands[1] is the length
15452 operands[3] is the alignment */
15455 expand_block_clear (rtx operands
[])
15457 rtx orig_dest
= operands
[0];
15458 rtx bytes_rtx
= operands
[1];
15459 rtx align_rtx
= operands
[3];
15460 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
15461 HOST_WIDE_INT align
;
15462 HOST_WIDE_INT bytes
;
15467 /* If this is not a fixed size move, just call memcpy */
15471 /* This must be a fixed size alignment */
15472 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
15473 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
15475 /* Anything to clear? */
15476 bytes
= INTVAL (bytes_rtx
);
15480 /* Use the builtin memset after a point, to avoid huge code bloat.
15481 When optimize_size, avoid any significant code bloat; calling
15482 memset is about 4 instructions, so allow for one instruction to
15483 load zero and three to do clearing. */
15484 if (TARGET_ALTIVEC
&& align
>= 128)
15486 else if (TARGET_POWERPC64
&& (align
>= 64 || !STRICT_ALIGNMENT
))
15488 else if (TARGET_SPE
&& align
>= 64)
15493 if (optimize_size
&& bytes
> 3 * clear_step
)
15495 if (! optimize_size
&& bytes
> 8 * clear_step
)
15498 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
15500 enum machine_mode mode
= BLKmode
;
15503 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
15508 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
15513 else if (bytes
>= 8 && TARGET_POWERPC64
15514 && (align
>= 64 || !STRICT_ALIGNMENT
))
15518 if (offset
== 0 && align
< 64)
15522 /* If the address form is reg+offset with offset not a
15523 multiple of four, reload into reg indirect form here
15524 rather than waiting for reload. This way we get one
15525 reload, not one per store. */
15526 addr
= XEXP (orig_dest
, 0);
15527 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
15528 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15529 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
15531 addr
= copy_addr_to_reg (addr
);
15532 orig_dest
= replace_equiv_address (orig_dest
, addr
);
15536 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
15537 { /* move 4 bytes */
15541 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
15542 { /* move 2 bytes */
15546 else /* move 1 byte at a time */
15552 dest
= adjust_address (orig_dest
, mode
, offset
);
15554 emit_move_insn (dest
, CONST0_RTX (mode
));
15561 /* Expand a block move operation, and return 1 if successful. Return 0
15562 if we should let the compiler generate normal code.
15564 operands[0] is the destination
15565 operands[1] is the source
15566 operands[2] is the length
15567 operands[3] is the alignment */
15569 #define MAX_MOVE_REG 4
15572 expand_block_move (rtx operands
[])
15574 rtx orig_dest
= operands
[0];
15575 rtx orig_src
= operands
[1];
15576 rtx bytes_rtx
= operands
[2];
15577 rtx align_rtx
= operands
[3];
15578 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
15583 rtx stores
[MAX_MOVE_REG
];
15586 /* If this is not a fixed size move, just call memcpy */
15590 /* This must be a fixed size alignment */
15591 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
15592 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
15594 /* Anything to move? */
15595 bytes
= INTVAL (bytes_rtx
);
15599 if (bytes
> rs6000_block_move_inline_limit
)
15602 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
15605 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
15606 rtx (*mov
) (rtx
, rtx
);
15608 enum machine_mode mode
= BLKmode
;
15611 /* Altivec first, since it will be faster than a string move
15612 when it applies, and usually not significantly larger. */
15613 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
15617 gen_func
.mov
= gen_movv4si
;
15619 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
15623 gen_func
.mov
= gen_movv2si
;
15625 else if (TARGET_STRING
15626 && bytes
> 24 /* move up to 32 bytes at a time */
15632 && ! fixed_regs
[10]
15633 && ! fixed_regs
[11]
15634 && ! fixed_regs
[12])
15636 move_bytes
= (bytes
> 32) ? 32 : bytes
;
15637 gen_func
.movmemsi
= gen_movmemsi_8reg
;
15639 else if (TARGET_STRING
15640 && bytes
> 16 /* move up to 24 bytes at a time */
15646 && ! fixed_regs
[10])
15648 move_bytes
= (bytes
> 24) ? 24 : bytes
;
15649 gen_func
.movmemsi
= gen_movmemsi_6reg
;
15651 else if (TARGET_STRING
15652 && bytes
> 8 /* move up to 16 bytes at a time */
15656 && ! fixed_regs
[8])
15658 move_bytes
= (bytes
> 16) ? 16 : bytes
;
15659 gen_func
.movmemsi
= gen_movmemsi_4reg
;
15661 else if (bytes
>= 8 && TARGET_POWERPC64
15662 && (align
>= 64 || !STRICT_ALIGNMENT
))
15666 gen_func
.mov
= gen_movdi
;
15667 if (offset
== 0 && align
< 64)
15671 /* If the address form is reg+offset with offset not a
15672 multiple of four, reload into reg indirect form here
15673 rather than waiting for reload. This way we get one
15674 reload, not one per load and/or store. */
15675 addr
= XEXP (orig_dest
, 0);
15676 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
15677 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15678 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
15680 addr
= copy_addr_to_reg (addr
);
15681 orig_dest
= replace_equiv_address (orig_dest
, addr
);
15683 addr
= XEXP (orig_src
, 0);
15684 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
15685 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15686 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
15688 addr
= copy_addr_to_reg (addr
);
15689 orig_src
= replace_equiv_address (orig_src
, addr
);
15693 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
15694 { /* move up to 8 bytes at a time */
15695 move_bytes
= (bytes
> 8) ? 8 : bytes
;
15696 gen_func
.movmemsi
= gen_movmemsi_2reg
;
15698 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
15699 { /* move 4 bytes */
15702 gen_func
.mov
= gen_movsi
;
15704 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
15705 { /* move 2 bytes */
15708 gen_func
.mov
= gen_movhi
;
15710 else if (TARGET_STRING
&& bytes
> 1)
15711 { /* move up to 4 bytes at a time */
15712 move_bytes
= (bytes
> 4) ? 4 : bytes
;
15713 gen_func
.movmemsi
= gen_movmemsi_1reg
;
15715 else /* move 1 byte at a time */
15719 gen_func
.mov
= gen_movqi
;
15722 src
= adjust_address (orig_src
, mode
, offset
);
15723 dest
= adjust_address (orig_dest
, mode
, offset
);
15725 if (mode
!= BLKmode
)
15727 rtx tmp_reg
= gen_reg_rtx (mode
);
15729 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
15730 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
15733 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
15736 for (i
= 0; i
< num_reg
; i
++)
15737 emit_insn (stores
[i
]);
15741 if (mode
== BLKmode
)
15743 /* Move the address into scratch registers. The movmemsi
15744 patterns require zero offset. */
15745 if (!REG_P (XEXP (src
, 0)))
15747 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
15748 src
= replace_equiv_address (src
, src_reg
);
15750 set_mem_size (src
, move_bytes
);
15752 if (!REG_P (XEXP (dest
, 0)))
15754 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
15755 dest
= replace_equiv_address (dest
, dest_reg
);
15757 set_mem_size (dest
, move_bytes
);
15759 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
15760 GEN_INT (move_bytes
& 31),
15769 /* Return a string to perform a load_multiple operation.
15770 operands[0] is the vector.
15771 operands[1] is the source address.
15772 operands[2] is the first destination register. */
15775 rs6000_output_load_multiple (rtx operands
[3])
15777 /* We have to handle the case where the pseudo used to contain the address
15778 is assigned to one of the output registers. */
15780 int words
= XVECLEN (operands
[0], 0);
15783 if (XVECLEN (operands
[0], 0) == 1)
15784 return "lwz %2,0(%1)";
15786 for (i
= 0; i
< words
; i
++)
15787 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
15788 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
15792 xop
[0] = GEN_INT (4 * (words
-1));
15793 xop
[1] = operands
[1];
15794 xop
[2] = operands
[2];
15795 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
15800 xop
[0] = GEN_INT (4 * (words
-1));
15801 xop
[1] = operands
[1];
15802 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
15803 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
15808 for (j
= 0; j
< words
; j
++)
15811 xop
[0] = GEN_INT (j
* 4);
15812 xop
[1] = operands
[1];
15813 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
15814 output_asm_insn ("lwz %2,%0(%1)", xop
);
15816 xop
[0] = GEN_INT (i
* 4);
15817 xop
[1] = operands
[1];
15818 output_asm_insn ("lwz %1,%0(%1)", xop
);
15823 return "lswi %2,%1,%N0";
15827 /* A validation routine: say whether CODE, a condition code, and MODE
15828 match. The other alternatives either don't make sense or should
15829 never be generated. */
15832 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
15834 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
15835 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
15836 && GET_MODE_CLASS (mode
) == MODE_CC
);
15838 /* These don't make sense. */
15839 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
15840 || mode
!= CCUNSmode
);
15842 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
15843 || mode
== CCUNSmode
);
15845 gcc_assert (mode
== CCFPmode
15846 || (code
!= ORDERED
&& code
!= UNORDERED
15847 && code
!= UNEQ
&& code
!= LTGT
15848 && code
!= UNGT
&& code
!= UNLT
15849 && code
!= UNGE
&& code
!= UNLE
));
15851 /* These should never be generated except for
15852 flag_finite_math_only. */
15853 gcc_assert (mode
!= CCFPmode
15854 || flag_finite_math_only
15855 || (code
!= LE
&& code
!= GE
15856 && code
!= UNEQ
&& code
!= LTGT
15857 && code
!= UNGT
&& code
!= UNLT
));
15859 /* These are invalid; the information is not there. */
15860 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
15864 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
15865 mask required to convert the result of a rotate insn into a shift
15866 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
15869 includes_lshift_p (rtx shiftop
, rtx andop
)
15871 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
15873 shift_mask
<<= INTVAL (shiftop
);
15875 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
15878 /* Similar, but for right shift. */
15881 includes_rshift_p (rtx shiftop
, rtx andop
)
15883 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
15885 shift_mask
>>= INTVAL (shiftop
);
15887 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
15890 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
15891 to perform a left shift. It must have exactly SHIFTOP least
15892 significant 0's, then one or more 1's, then zero or more 0's. */
15895 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
15897 if (GET_CODE (andop
) == CONST_INT
)
15899 HOST_WIDE_INT c
, lsb
, shift_mask
;
15901 c
= INTVAL (andop
);
15902 if (c
== 0 || c
== ~0)
15906 shift_mask
<<= INTVAL (shiftop
);
15908 /* Find the least significant one bit. */
15911 /* It must coincide with the LSB of the shift mask. */
15912 if (-lsb
!= shift_mask
)
15915 /* Invert to look for the next transition (if any). */
15918 /* Remove the low group of ones (originally low group of zeros). */
15921 /* Again find the lsb, and check we have all 1's above. */
15929 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
15930 to perform a left shift. It must have SHIFTOP or more least
15931 significant 0's, with the remainder of the word 1's. */
15934 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
15936 if (GET_CODE (andop
) == CONST_INT
)
15938 HOST_WIDE_INT c
, lsb
, shift_mask
;
15941 shift_mask
<<= INTVAL (shiftop
);
15942 c
= INTVAL (andop
);
15944 /* Find the least significant one bit. */
15947 /* It must be covered by the shift mask.
15948 This test also rejects c == 0. */
15949 if ((lsb
& shift_mask
) == 0)
15952 /* Check we have all 1's above the transition, and reject all 1's. */
15953 return c
== -lsb
&& lsb
!= 1;
15959 /* Return 1 if operands will generate a valid arguments to rlwimi
15960 instruction for insert with right shift in 64-bit mode. The mask may
15961 not start on the first bit or stop on the last bit because wrap-around
15962 effects of instruction do not correspond to semantics of RTL insn. */
15965 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
15967 if (INTVAL (startop
) > 32
15968 && INTVAL (startop
) < 64
15969 && INTVAL (sizeop
) > 1
15970 && INTVAL (sizeop
) + INTVAL (startop
) < 64
15971 && INTVAL (shiftop
) > 0
15972 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
15973 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
15979 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
15980 for lfq and stfq insns iff the registers are hard registers. */
15983 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
15985 /* We might have been passed a SUBREG. */
15986 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
15989 /* We might have been passed non floating point registers. */
15990 if (!FP_REGNO_P (REGNO (reg1
))
15991 || !FP_REGNO_P (REGNO (reg2
)))
15994 return (REGNO (reg1
) == REGNO (reg2
) - 1);
15997 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
15998 addr1 and addr2 must be in consecutive memory locations
15999 (addr2 == addr1 + 8). */
16002 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
16005 unsigned int reg1
, reg2
;
16006 int offset1
, offset2
;
16008 /* The mems cannot be volatile. */
16009 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
16012 addr1
= XEXP (mem1
, 0);
16013 addr2
= XEXP (mem2
, 0);
16015 /* Extract an offset (if used) from the first addr. */
16016 if (GET_CODE (addr1
) == PLUS
)
16018 /* If not a REG, return zero. */
16019 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
16023 reg1
= REGNO (XEXP (addr1
, 0));
16024 /* The offset must be constant! */
16025 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
16027 offset1
= INTVAL (XEXP (addr1
, 1));
16030 else if (GET_CODE (addr1
) != REG
)
16034 reg1
= REGNO (addr1
);
16035 /* This was a simple (mem (reg)) expression. Offset is 0. */
16039 /* And now for the second addr. */
16040 if (GET_CODE (addr2
) == PLUS
)
16042 /* If not a REG, return zero. */
16043 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
16047 reg2
= REGNO (XEXP (addr2
, 0));
16048 /* The offset must be constant. */
16049 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
16051 offset2
= INTVAL (XEXP (addr2
, 1));
16054 else if (GET_CODE (addr2
) != REG
)
16058 reg2
= REGNO (addr2
);
16059 /* This was a simple (mem (reg)) expression. Offset is 0. */
16063 /* Both of these must have the same base register. */
16067 /* The offset for the second addr must be 8 more than the first addr. */
16068 if (offset2
!= offset1
+ 8)
16071 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
16078 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
16080 static bool eliminated
= false;
16083 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
16084 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
16087 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
16088 gcc_assert (mem
!= NULL_RTX
);
16092 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
16093 cfun
->machine
->sdmode_stack_slot
= mem
;
16099 if (TARGET_DEBUG_ADDR
)
16101 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
16102 GET_MODE_NAME (mode
));
16104 fprintf (stderr
, "\tNULL_RTX\n");
16112 /* Return the mode to be used for memory when a secondary memory
16113 location is needed. For SDmode values we need to use DDmode, in
16114 all other cases we can use the same mode. */
16116 rs6000_secondary_memory_needed_mode (enum machine_mode mode
)
16118 if (lra_in_progress
&& mode
== SDmode
)
16124 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
16126 /* Don't walk into types. */
16127 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
16129 *walk_subtrees
= 0;
16133 switch (TREE_CODE (*tp
))
16142 case VIEW_CONVERT_EXPR
:
16143 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
16153 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
16154 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
16155 only work on the traditional altivec registers, note if an altivec register
16158 static enum rs6000_reg_type
16159 register_to_reg_type (rtx reg
, bool *is_altivec
)
16161 HOST_WIDE_INT regno
;
16162 enum reg_class rclass
;
16164 if (GET_CODE (reg
) == SUBREG
)
16165 reg
= SUBREG_REG (reg
);
16168 return NO_REG_TYPE
;
16170 regno
= REGNO (reg
);
16171 if (regno
>= FIRST_PSEUDO_REGISTER
)
16173 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
16174 return PSEUDO_REG_TYPE
;
16176 regno
= true_regnum (reg
);
16177 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16178 return PSEUDO_REG_TYPE
;
16181 gcc_assert (regno
>= 0);
16183 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
16184 *is_altivec
= true;
16186 rclass
= rs6000_regno_regclass
[regno
];
16187 return reg_class_to_reg_type
[(int)rclass
];
16190 /* Helper function for rs6000_secondary_reload to return true if a move to a
16191 different register classe is really a simple move. */
16194 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
16195 enum rs6000_reg_type from_type
,
16196 enum machine_mode mode
)
16200 /* Add support for various direct moves available. In this function, we only
16201 look at cases where we don't need any extra registers, and one or more
16202 simple move insns are issued. At present, 32-bit integers are not allowed
16203 in FPR/VSX registers. Single precision binary floating is not a simple
16204 move because we need to convert to the single precision memory layout.
16205 The 4-byte SDmode can be moved. */
16206 size
= GET_MODE_SIZE (mode
);
16207 if (TARGET_DIRECT_MOVE
16208 && ((mode
== SDmode
) || (TARGET_POWERPC64
&& size
== 8))
16209 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16210 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
16213 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
16214 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
16215 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
16218 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
16219 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
16220 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
16226 /* Power8 helper function for rs6000_secondary_reload, handle all of the
16227 special direct moves that involve allocating an extra register, return the
16228 insn code of the helper function if there is such a function or
16229 CODE_FOR_nothing if not. */
16232 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
16233 enum rs6000_reg_type from_type
,
16234 enum machine_mode mode
,
16235 secondary_reload_info
*sri
,
16239 enum insn_code icode
= CODE_FOR_nothing
;
16241 int size
= GET_MODE_SIZE (mode
);
16243 if (TARGET_POWERPC64
)
16247 /* Handle moving 128-bit values from GPRs to VSX point registers on
16248 power8 when running in 64-bit mode using XXPERMDI to glue the two
16249 64-bit values back together. */
16250 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
16252 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
16253 icode
= reg_addr
[mode
].reload_vsx_gpr
;
16256 /* Handle moving 128-bit values from VSX point registers to GPRs on
16257 power8 when running in 64-bit mode using XXPERMDI to get access to the
16258 bottom 64-bit value. */
16259 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16261 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
16262 icode
= reg_addr
[mode
].reload_gpr_vsx
;
16266 else if (mode
== SFmode
)
16268 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16270 cost
= 3; /* xscvdpspn, mfvsrd, and. */
16271 icode
= reg_addr
[mode
].reload_gpr_vsx
;
16274 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
16276 cost
= 2; /* mtvsrz, xscvspdpn. */
16277 icode
= reg_addr
[mode
].reload_vsx_gpr
;
16282 if (TARGET_POWERPC64
&& size
== 16)
16284 /* Handle moving 128-bit values from GPRs to VSX point registers on
16285 power8 when running in 64-bit mode using XXPERMDI to glue the two
16286 64-bit values back together. */
16287 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
16289 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
16290 icode
= reg_addr
[mode
].reload_vsx_gpr
;
16293 /* Handle moving 128-bit values from VSX point registers to GPRs on
16294 power8 when running in 64-bit mode using XXPERMDI to get access to the
16295 bottom 64-bit value. */
16296 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
16298 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
16299 icode
= reg_addr
[mode
].reload_gpr_vsx
;
16303 else if (!TARGET_POWERPC64
&& size
== 8)
16305 /* Handle moving 64-bit values from GPRs to floating point registers on
16306 power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
16307 values back together. Altivec register classes must be handled
16308 specially since a different instruction is used, and the secondary
16309 reload support requires a single instruction class in the scratch
16310 register constraint. However, right now TFmode is not allowed in
16311 Altivec registers, so the pattern will never match. */
16312 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
16314 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
16315 icode
= reg_addr
[mode
].reload_fpr_gpr
;
16319 if (icode
!= CODE_FOR_nothing
)
16324 sri
->icode
= icode
;
16325 sri
->extra_cost
= cost
;
16332 /* Return whether a move between two register classes can be done either
16333 directly (simple move) or via a pattern that uses a single extra temporary
16334 (using power8's direct move in this case. */
16337 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
16338 enum rs6000_reg_type from_type
,
16339 enum machine_mode mode
,
16340 secondary_reload_info
*sri
,
16343 /* Fall back to load/store reloads if either type is not a register. */
16344 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
16347 /* If we haven't allocated registers yet, assume the move can be done for the
16348 standard register types. */
16349 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
16350 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
16351 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
16354 /* Moves to the same set of registers is a simple move for non-specialized
16356 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
16359 /* Check whether a simple move can be done directly. */
16360 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
16364 sri
->icode
= CODE_FOR_nothing
;
16365 sri
->extra_cost
= 0;
16370 /* Now check if we can do it in a few steps. */
16371 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
16375 /* Inform reload about cases where moving X with a mode MODE to a register in
16376 RCLASS requires an extra scratch or immediate register. Return the class
16377 needed for the immediate register.
16379 For VSX and Altivec, we may need a register to convert sp+offset into
16382 For misaligned 64-bit gpr loads and stores we need a register to
16383 convert an offset address to indirect. */
16386 rs6000_secondary_reload (bool in_p
,
16388 reg_class_t rclass_i
,
16389 enum machine_mode mode
,
16390 secondary_reload_info
*sri
)
16392 enum reg_class rclass
= (enum reg_class
) rclass_i
;
16393 reg_class_t ret
= ALL_REGS
;
16394 enum insn_code icode
;
16395 bool default_p
= false;
16397 sri
->icode
= CODE_FOR_nothing
;
16399 ? reg_addr
[mode
].reload_load
16400 : reg_addr
[mode
].reload_store
);
16402 if (REG_P (x
) || register_operand (x
, mode
))
16404 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
16405 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
16406 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
16410 enum rs6000_reg_type exchange
= to_type
;
16411 to_type
= from_type
;
16412 from_type
= exchange
;
16415 /* Can we do a direct move of some sort? */
16416 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
16419 icode
= (enum insn_code
)sri
->icode
;
16425 /* Handle vector moves with reload helper functions. */
16426 if (ret
== ALL_REGS
&& icode
!= CODE_FOR_nothing
)
16429 sri
->icode
= CODE_FOR_nothing
;
16430 sri
->extra_cost
= 0;
16432 if (GET_CODE (x
) == MEM
)
16434 rtx addr
= XEXP (x
, 0);
16436 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
16437 an extra register in that case, but it would need an extra
16438 register if the addressing is reg+reg or (reg+reg)&(-16). Special
16439 case load/store quad. */
16440 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
16442 if (TARGET_POWERPC64
&& TARGET_QUAD_MEMORY
16443 && GET_MODE_SIZE (mode
) == 16
16444 && quad_memory_operand (x
, mode
))
16446 sri
->icode
= icode
;
16447 sri
->extra_cost
= 2;
16450 else if (!legitimate_indirect_address_p (addr
, false)
16451 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16454 sri
->icode
= icode
;
16455 /* account for splitting the loads, and converting the
16456 address from reg+reg to reg. */
16457 sri
->extra_cost
= (((TARGET_64BIT
) ? 3 : 5)
16458 + ((GET_CODE (addr
) == AND
) ? 1 : 0));
16461 /* Allow scalar loads to/from the traditional floating point
16462 registers, even if VSX memory is set. */
16463 else if ((rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
16464 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
16465 && (legitimate_indirect_address_p (addr
, false)
16466 || legitimate_indirect_address_p (addr
, false)
16467 || rs6000_legitimate_offset_address_p (mode
, addr
,
16471 /* Loads to and stores from vector registers can only do reg+reg
16472 addressing. Altivec registers can also do (reg+reg)&(-16). Allow
16473 scalar modes loading up the traditional floating point registers
16474 to use offset addresses. */
16475 else if (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
16476 || rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
16478 if (!VECTOR_MEM_ALTIVEC_P (mode
)
16479 && GET_CODE (addr
) == AND
16480 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16481 && INTVAL (XEXP (addr
, 1)) == -16
16482 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
16483 || legitimate_indexed_address_p (XEXP (addr
, 0), false)))
16485 sri
->icode
= icode
;
16486 sri
->extra_cost
= ((GET_CODE (XEXP (addr
, 0)) == PLUS
)
16489 else if (!legitimate_indirect_address_p (addr
, false)
16490 && (rclass
== NO_REGS
16491 || !legitimate_indexed_address_p (addr
, false)))
16493 sri
->icode
= icode
;
16494 sri
->extra_cost
= 1;
16497 icode
= CODE_FOR_nothing
;
16499 /* Any other loads, including to pseudo registers which haven't been
16500 assigned to a register yet, default to require a scratch
16504 sri
->icode
= icode
;
16505 sri
->extra_cost
= 2;
16508 else if (REG_P (x
))
16510 int regno
= true_regnum (x
);
16512 icode
= CODE_FOR_nothing
;
16513 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16517 enum reg_class xclass
= REGNO_REG_CLASS (regno
);
16518 enum rs6000_reg_type rtype1
= reg_class_to_reg_type
[(int)rclass
];
16519 enum rs6000_reg_type rtype2
= reg_class_to_reg_type
[(int)xclass
];
16521 /* If memory is needed, use default_secondary_reload to create the
16523 if (rtype1
!= rtype2
|| !IS_STD_REG_TYPE (rtype1
))
16532 else if (TARGET_POWERPC64
16533 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
16535 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
16537 rtx addr
= XEXP (x
, 0);
16538 rtx off
= address_offset (addr
);
16540 if (off
!= NULL_RTX
)
16542 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
16543 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
16545 /* We need a secondary reload when our legitimate_address_p
16546 says the address is good (as otherwise the entire address
16547 will be reloaded), and the offset is not a multiple of
16548 four or we have an address wrap. Address wrap will only
16549 occur for LO_SUMs since legitimate_offset_address_p
16550 rejects addresses for 16-byte mems that will wrap. */
16551 if (GET_CODE (addr
) == LO_SUM
16552 ? (1 /* legitimate_address_p allows any offset for lo_sum */
16553 && ((offset
& 3) != 0
16554 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
16555 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
16556 && (offset
& 3) != 0))
16559 sri
->icode
= CODE_FOR_reload_di_load
;
16561 sri
->icode
= CODE_FOR_reload_di_store
;
16562 sri
->extra_cost
= 2;
16571 else if (!TARGET_POWERPC64
16572 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
16574 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
16576 rtx addr
= XEXP (x
, 0);
16577 rtx off
= address_offset (addr
);
16579 if (off
!= NULL_RTX
)
16581 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
16582 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
16584 /* We need a secondary reload when our legitimate_address_p
16585 says the address is good (as otherwise the entire address
16586 will be reloaded), and we have a wrap.
16588 legitimate_lo_sum_address_p allows LO_SUM addresses to
16589 have any offset so test for wrap in the low 16 bits.
16591 legitimate_offset_address_p checks for the range
16592 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
16593 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
16594 [0x7ff4,0x7fff] respectively, so test for the
16595 intersection of these ranges, [0x7ffc,0x7fff] and
16596 [0x7ff4,0x7ff7] respectively.
16598 Note that the address we see here may have been
16599 manipulated by legitimize_reload_address. */
16600 if (GET_CODE (addr
) == LO_SUM
16601 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
16602 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
16605 sri
->icode
= CODE_FOR_reload_si_load
;
16607 sri
->icode
= CODE_FOR_reload_si_store
;
16608 sri
->extra_cost
= 2;
16621 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
16623 gcc_assert (ret
!= ALL_REGS
);
16625 if (TARGET_DEBUG_ADDR
)
16628 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
16630 reg_class_names
[ret
],
16631 in_p
? "true" : "false",
16632 reg_class_names
[rclass
],
16633 GET_MODE_NAME (mode
));
16636 fprintf (stderr
, ", default secondary reload");
16638 if (sri
->icode
!= CODE_FOR_nothing
)
16639 fprintf (stderr
, ", reload func = %s, extra cost = %d\n",
16640 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
16642 fprintf (stderr
, "\n");
16650 /* Better tracing for rs6000_secondary_reload_inner. */
16653 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
16658 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
16660 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
16661 store_p
? "store" : "load");
16664 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
16666 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
16668 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
16669 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
16673 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
16676 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
16677 gcc_unreachable ();
16680 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
16681 to SP+reg addressing. */
16684 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
16686 int regno
= true_regnum (reg
);
16687 enum machine_mode mode
= GET_MODE (reg
);
16688 enum reg_class rclass
;
16690 rtx and_op2
= NULL_RTX
;
16693 rtx scratch_or_premodify
= scratch
;
16697 if (TARGET_DEBUG_ADDR
)
16698 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
16700 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16701 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16703 if (GET_CODE (mem
) != MEM
)
16704 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16706 rclass
= REGNO_REG_CLASS (regno
);
16707 addr
= find_replacement (&XEXP (mem
, 0));
16711 /* GPRs can handle reg + small constant, all other addresses need to use
16712 the scratch register. */
16715 if (GET_CODE (addr
) == AND
)
16717 and_op2
= XEXP (addr
, 1);
16718 addr
= find_replacement (&XEXP (addr
, 0));
16721 if (GET_CODE (addr
) == PRE_MODIFY
)
16723 scratch_or_premodify
= find_replacement (&XEXP (addr
, 0));
16724 if (!REG_P (scratch_or_premodify
))
16725 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16727 addr
= find_replacement (&XEXP (addr
, 1));
16728 if (GET_CODE (addr
) != PLUS
)
16729 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16732 if (GET_CODE (addr
) == PLUS
16733 && (and_op2
!= NULL_RTX
16734 || !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16737 /* find_replacement already recurses into both operands of
16738 PLUS so we don't need to call it here. */
16739 addr_op1
= XEXP (addr
, 0);
16740 addr_op2
= XEXP (addr
, 1);
16741 if (!legitimate_indirect_address_p (addr_op1
, false))
16742 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16744 if (!REG_P (addr_op2
)
16745 && (GET_CODE (addr_op2
) != CONST_INT
16746 || !satisfies_constraint_I (addr_op2
)))
16748 if (TARGET_DEBUG_ADDR
)
16751 "\nMove plus addr to register %s, mode = %s: ",
16752 rs6000_reg_names
[REGNO (scratch
)],
16753 GET_MODE_NAME (mode
));
16754 debug_rtx (addr_op2
);
16756 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
16757 addr_op2
= scratch
;
16760 emit_insn (gen_rtx_SET (VOIDmode
,
16761 scratch_or_premodify
,
16762 gen_rtx_PLUS (Pmode
,
16766 addr
= scratch_or_premodify
;
16767 scratch_or_premodify
= scratch
;
16769 else if (!legitimate_indirect_address_p (addr
, false)
16770 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16773 if (TARGET_DEBUG_ADDR
)
16775 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
16776 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
16777 GET_MODE_NAME (mode
));
16780 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16781 addr
= scratch_or_premodify
;
16782 scratch_or_premodify
= scratch
;
16786 /* Float registers can do offset+reg addressing for scalar types. */
16788 if (legitimate_indirect_address_p (addr
, false) /* reg */
16789 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
16790 || ((GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
16791 && and_op2
== NULL_RTX
16792 && scratch_or_premodify
== scratch
16793 && rs6000_legitimate_offset_address_p (mode
, addr
, false, false)))
16796 /* If this isn't a legacy floating point load/store, fall through to the
16799 /* VSX/Altivec registers can only handle reg+reg addressing. Move other
16800 addresses into a scratch register. */
16804 /* With float regs, we need to handle the AND ourselves, since we can't
16805 use the Altivec instruction with an implicit AND -16. Allow scalar
16806 loads to float registers to use reg+offset even if VSX. */
16807 if (GET_CODE (addr
) == AND
16808 && (rclass
!= ALTIVEC_REGS
|| GET_MODE_SIZE (mode
) != 16
16809 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
16810 || INTVAL (XEXP (addr
, 1)) != -16
16811 || !VECTOR_MEM_ALTIVEC_P (mode
)))
16813 and_op2
= XEXP (addr
, 1);
16814 addr
= find_replacement (&XEXP (addr
, 0));
16817 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
16818 as the address later. */
16819 if (GET_CODE (addr
) == PRE_MODIFY
16820 && ((ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
16821 && (rclass
!= FLOAT_REGS
16822 || (GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)))
16823 || and_op2
!= NULL_RTX
16824 || !legitimate_indexed_address_p (XEXP (addr
, 1), false)))
16826 scratch_or_premodify
= find_replacement (&XEXP (addr
, 0));
16827 if (!legitimate_indirect_address_p (scratch_or_premodify
, false))
16828 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16830 addr
= find_replacement (&XEXP (addr
, 1));
16831 if (GET_CODE (addr
) != PLUS
)
16832 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16835 if (legitimate_indirect_address_p (addr
, false) /* reg */
16836 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
16837 || (GET_CODE (addr
) == AND
/* Altivec memory */
16838 && rclass
== ALTIVEC_REGS
16839 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16840 && INTVAL (XEXP (addr
, 1)) == -16
16841 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
16842 || legitimate_indexed_address_p (XEXP (addr
, 0), false))))
16845 else if (GET_CODE (addr
) == PLUS
)
16847 addr_op1
= XEXP (addr
, 0);
16848 addr_op2
= XEXP (addr
, 1);
16849 if (!REG_P (addr_op1
))
16850 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16852 if (TARGET_DEBUG_ADDR
)
16854 fprintf (stderr
, "\nMove plus addr to register %s, mode = %s: ",
16855 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
16856 debug_rtx (addr_op2
);
16858 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
16859 emit_insn (gen_rtx_SET (VOIDmode
,
16860 scratch_or_premodify
,
16861 gen_rtx_PLUS (Pmode
,
16864 addr
= scratch_or_premodify
;
16865 scratch_or_premodify
= scratch
;
16868 else if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == CONST
16869 || GET_CODE (addr
) == CONST_INT
|| GET_CODE (addr
) == LO_SUM
16872 if (TARGET_DEBUG_ADDR
)
16874 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
16875 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
16876 GET_MODE_NAME (mode
));
16880 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16881 addr
= scratch_or_premodify
;
16882 scratch_or_premodify
= scratch
;
16886 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16891 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16894 /* If the original address involved a pre-modify that we couldn't use the VSX
16895 memory instruction with update, and we haven't taken care of already,
16896 store the address in the pre-modify register and use that as the
16898 if (scratch_or_premodify
!= scratch
&& scratch_or_premodify
!= addr
)
16900 emit_insn (gen_rtx_SET (VOIDmode
, scratch_or_premodify
, addr
));
16901 addr
= scratch_or_premodify
;
16904 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
16905 memory instruction, recreate the AND now, including the clobber which is
16906 generated by the general ANDSI3/ANDDI3 patterns for the
16907 andi. instruction. */
16908 if (and_op2
!= NULL_RTX
)
16910 if (! legitimate_indirect_address_p (addr
, false))
16912 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, addr
));
16916 if (TARGET_DEBUG_ADDR
)
16918 fprintf (stderr
, "\nAnd addr to register %s, mode = %s: ",
16919 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
16920 debug_rtx (and_op2
);
16923 and_rtx
= gen_rtx_SET (VOIDmode
,
16925 gen_rtx_AND (Pmode
,
16929 cc_clobber
= gen_rtx_CLOBBER (CCmode
, gen_rtx_SCRATCH (CCmode
));
16930 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
16931 gen_rtvec (2, and_rtx
, cc_clobber
)));
16935 /* Adjust the address if it changed. */
16936 if (addr
!= XEXP (mem
, 0))
16938 mem
= replace_equiv_address_nv (mem
, addr
);
16939 if (TARGET_DEBUG_ADDR
)
16940 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
16943 /* Now create the move. */
16945 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
16947 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
16952 /* Convert reloads involving 64-bit gprs and misaligned offset
16953 addressing, or multiple 32-bit gprs and offsets that are too large,
16954 to use indirect addressing. */
16957 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
16959 int regno
= true_regnum (reg
);
16960 enum reg_class rclass
;
16962 rtx scratch_or_premodify
= scratch
;
16964 if (TARGET_DEBUG_ADDR
)
16966 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
16967 store_p
? "store" : "load");
16968 fprintf (stderr
, "reg:\n");
16970 fprintf (stderr
, "mem:\n");
16972 fprintf (stderr
, "scratch:\n");
16973 debug_rtx (scratch
);
16976 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
16977 gcc_assert (GET_CODE (mem
) == MEM
);
16978 rclass
= REGNO_REG_CLASS (regno
);
16979 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
16980 addr
= XEXP (mem
, 0);
16982 if (GET_CODE (addr
) == PRE_MODIFY
)
16984 scratch_or_premodify
= XEXP (addr
, 0);
16985 gcc_assert (REG_P (scratch_or_premodify
));
16986 addr
= XEXP (addr
, 1);
16988 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
16990 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16992 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
16994 /* Now create the move. */
16996 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
16998 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
17003 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
17004 this function has any SDmode references. If we are on a power7 or later, we
17005 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
17006 can load/store the value. */
17009 rs6000_alloc_sdmode_stack_slot (void)
17013 gimple_stmt_iterator gsi
;
17015 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
17016 /* We use a different approach for dealing with the secondary
17021 if (TARGET_NO_SDMODE_STACK
)
17024 FOR_EACH_BB_FN (bb
, cfun
)
17025 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
17027 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
17030 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
17031 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
17037 /* Check for any SDmode parameters of the function. */
17038 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
17040 if (TREE_TYPE (t
) == error_mark_node
)
17043 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
17044 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
17046 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
17047 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
17055 rs6000_instantiate_decls (void)
17057 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
17058 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
17061 /* Given an rtx X being reloaded into a reg required to be
17062 in class CLASS, return the class of reg to actually use.
17063 In general this is just CLASS; but on some machines
17064 in some cases it is preferable to use a more restrictive class.
17066 On the RS/6000, we have to return NO_REGS when we want to reload a
17067 floating-point CONST_DOUBLE to force it to be copied to memory.
17069 We also don't want to reload integer values into floating-point
17070 registers if we can at all help it. In fact, this can
17071 cause reload to die, if it tries to generate a reload of CTR
17072 into a FP register and discovers it doesn't have the memory location
17075 ??? Would it be a good idea to have reload do the converse, that is
17076 try to reload floating modes into FP registers if possible?
17079 static enum reg_class
17080 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
17082 enum machine_mode mode
= GET_MODE (x
);
17084 if (TARGET_VSX
&& x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
17087 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
17088 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
17089 && easy_vector_constant (x
, mode
))
17090 return ALTIVEC_REGS
;
17092 if ((CONSTANT_P (x
) || GET_CODE (x
) == PLUS
))
17094 if (reg_class_subset_p (GENERAL_REGS
, rclass
))
17095 return GENERAL_REGS
;
17096 if (reg_class_subset_p (BASE_REGS
, rclass
))
17101 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
17102 return GENERAL_REGS
;
17104 /* For VSX, prefer the traditional registers for 64-bit values because we can
17105 use the non-VSX loads. Prefer the Altivec registers if Altivec is
17106 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
17107 prefer Altivec loads.. */
17108 if (rclass
== VSX_REGS
)
17110 if (GET_MODE_SIZE (mode
) <= 8)
17113 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
)
17114 || mode
== V1TImode
)
17115 return ALTIVEC_REGS
;
17123 /* Debug version of rs6000_preferred_reload_class. */
17124 static enum reg_class
17125 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
17127 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
17130 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
17132 reg_class_names
[ret
], reg_class_names
[rclass
],
17133 GET_MODE_NAME (GET_MODE (x
)));
17139 /* If we are copying between FP or AltiVec registers and anything else, we need
17140 a memory location. The exception is when we are targeting ppc64 and the
17141 move to/from fpr to gpr instructions are available. Also, under VSX, you
17142 can copy vector registers from the FP register set to the Altivec register
17143 set and vice versa. */
17146 rs6000_secondary_memory_needed (enum reg_class from_class
,
17147 enum reg_class to_class
,
17148 enum machine_mode mode
)
17150 enum rs6000_reg_type from_type
, to_type
;
17151 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
17152 || (to_class
== ALTIVEC_REGS
));
17154 /* If a simple/direct move is available, we don't need secondary memory */
17155 from_type
= reg_class_to_reg_type
[(int)from_class
];
17156 to_type
= reg_class_to_reg_type
[(int)to_class
];
17158 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
17159 (secondary_reload_info
*)0, altivec_p
))
17162 /* If we have a floating point or vector register class, we need to use
17163 memory to transfer the data. */
17164 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
17170 /* Debug version of rs6000_secondary_memory_needed. */
17172 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
17173 enum reg_class to_class
,
17174 enum machine_mode mode
)
17176 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
17179 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
17180 "to_class = %s, mode = %s\n",
17181 ret
? "true" : "false",
17182 reg_class_names
[from_class
],
17183 reg_class_names
[to_class
],
17184 GET_MODE_NAME (mode
));
17189 /* Return the register class of a scratch register needed to copy IN into
17190 or out of a register in RCLASS in MODE. If it can be done directly,
17191 NO_REGS is returned. */
17193 static enum reg_class
17194 rs6000_secondary_reload_class (enum reg_class rclass
, enum machine_mode mode
,
17199 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
17201 && MACHOPIC_INDIRECT
17205 /* We cannot copy a symbolic operand directly into anything
17206 other than BASE_REGS for TARGET_ELF. So indicate that a
17207 register from BASE_REGS is needed as an intermediate
17210 On Darwin, pic addresses require a load from memory, which
17211 needs a base register. */
17212 if (rclass
!= BASE_REGS
17213 && (GET_CODE (in
) == SYMBOL_REF
17214 || GET_CODE (in
) == HIGH
17215 || GET_CODE (in
) == LABEL_REF
17216 || GET_CODE (in
) == CONST
))
17220 if (GET_CODE (in
) == REG
)
17222 regno
= REGNO (in
);
17223 if (regno
>= FIRST_PSEUDO_REGISTER
)
17225 regno
= true_regnum (in
);
17226 if (regno
>= FIRST_PSEUDO_REGISTER
)
17230 else if (GET_CODE (in
) == SUBREG
)
17232 regno
= true_regnum (in
);
17233 if (regno
>= FIRST_PSEUDO_REGISTER
)
17239 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
17241 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
17242 || (regno
>= 0 && INT_REGNO_P (regno
)))
17245 /* Constants, memory, and FP registers can go into FP registers. */
17246 if ((regno
== -1 || FP_REGNO_P (regno
))
17247 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
17248 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
17250 /* Memory, and FP/altivec registers can go into fp/altivec registers under
17251 VSX. However, for scalar variables, use the traditional floating point
17252 registers so that we can use offset+register addressing. */
17254 && (regno
== -1 || VSX_REGNO_P (regno
))
17255 && VSX_REG_CLASS_P (rclass
))
17257 if (GET_MODE_SIZE (mode
) < 16)
17263 /* Memory, and AltiVec registers can go into AltiVec registers. */
17264 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
17265 && rclass
== ALTIVEC_REGS
)
17268 /* We can copy among the CR registers. */
17269 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
17270 && regno
>= 0 && CR_REGNO_P (regno
))
17273 /* Otherwise, we need GENERAL_REGS. */
17274 return GENERAL_REGS
;
17277 /* Debug version of rs6000_secondary_reload_class. */
17278 static enum reg_class
17279 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
17280 enum machine_mode mode
, rtx in
)
17282 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
17284 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
17285 "mode = %s, input rtx:\n",
17286 reg_class_names
[ret
], reg_class_names
[rclass
],
17287 GET_MODE_NAME (mode
));
17293 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
17296 rs6000_cannot_change_mode_class (enum machine_mode from
,
17297 enum machine_mode to
,
17298 enum reg_class rclass
)
17300 unsigned from_size
= GET_MODE_SIZE (from
);
17301 unsigned to_size
= GET_MODE_SIZE (to
);
17303 if (from_size
!= to_size
)
17305 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
17307 if (reg_classes_intersect_p (xclass
, rclass
))
17309 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
17310 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
17312 /* Don't allow 64-bit types to overlap with 128-bit types that take a
17313 single register under VSX because the scalar part of the register
17314 is in the upper 64-bits, and not the lower 64-bits. Types like
17315 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
17316 IEEE floating point can't overlap, and neither can small
17319 if (TARGET_IEEEQUAD
&& (to
== TFmode
|| from
== TFmode
))
17322 /* TDmode in floating-mode registers must always go into a register
17323 pair with the most significant word in the even-numbered register
17324 to match ISA requirements. In little-endian mode, this does not
17325 match subreg numbering, so we cannot allow subregs. */
17326 if (!BYTES_BIG_ENDIAN
&& (to
== TDmode
|| from
== TDmode
))
17329 if (from_size
< 8 || to_size
< 8)
17332 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
17335 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
17344 if (TARGET_E500_DOUBLE
17345 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
17346 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
17347 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
17348 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
17349 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
17352 /* Since the VSX register set includes traditional floating point registers
17353 and altivec registers, just check for the size being different instead of
17354 trying to check whether the modes are vector modes. Otherwise it won't
17355 allow say DF and DI to change classes. For types like TFmode and TDmode
17356 that take 2 64-bit registers, rather than a single 128-bit register, don't
17357 allow subregs of those types to other 128 bit types. */
17358 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
17360 unsigned num_regs
= (from_size
+ 15) / 16;
17361 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
17362 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
17365 return (from_size
!= 8 && from_size
!= 16);
17368 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
17369 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
17372 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
17373 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
17379 /* Debug version of rs6000_cannot_change_mode_class. */
17381 rs6000_debug_cannot_change_mode_class (enum machine_mode from
,
17382 enum machine_mode to
,
17383 enum reg_class rclass
)
17385 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
17388 "rs6000_cannot_change_mode_class, return %s, from = %s, "
17389 "to = %s, rclass = %s\n",
17390 ret
? "true" : "false",
17391 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
17392 reg_class_names
[rclass
]);
17397 /* Return a string to do a move operation of 128 bits of data. */
17400 rs6000_output_move_128bit (rtx operands
[])
17402 rtx dest
= operands
[0];
17403 rtx src
= operands
[1];
17404 enum machine_mode mode
= GET_MODE (dest
);
17407 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
17408 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
17412 dest_regno
= REGNO (dest
);
17413 dest_gpr_p
= INT_REGNO_P (dest_regno
);
17414 dest_fp_p
= FP_REGNO_P (dest_regno
);
17415 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
17416 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
17421 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
17426 src_regno
= REGNO (src
);
17427 src_gpr_p
= INT_REGNO_P (src_regno
);
17428 src_fp_p
= FP_REGNO_P (src_regno
);
17429 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
17430 src_vsx_p
= src_fp_p
| src_vmx_p
;
17435 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
17438 /* Register moves. */
17439 if (dest_regno
>= 0 && src_regno
>= 0)
17446 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
17450 else if (TARGET_VSX
&& dest_vsx_p
)
17453 return "xxlor %x0,%x1,%x1";
17455 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
17459 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
17460 return "vor %0,%1,%1";
17462 else if (dest_fp_p
&& src_fp_p
)
17467 else if (dest_regno
>= 0 && MEM_P (src
))
17471 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
17477 else if (TARGET_ALTIVEC
&& dest_vmx_p
17478 && altivec_indexed_or_indirect_operand (src
, mode
))
17479 return "lvx %0,%y1";
17481 else if (TARGET_VSX
&& dest_vsx_p
)
17483 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
17484 return "lxvw4x %x0,%y1";
17486 return "lxvd2x %x0,%y1";
17489 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
17490 return "lvx %0,%y1";
17492 else if (dest_fp_p
)
17497 else if (src_regno
>= 0 && MEM_P (dest
))
17501 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
17502 return "stq %1,%0";
17507 else if (TARGET_ALTIVEC
&& src_vmx_p
17508 && altivec_indexed_or_indirect_operand (src
, mode
))
17509 return "stvx %1,%y0";
17511 else if (TARGET_VSX
&& src_vsx_p
)
17513 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
17514 return "stxvw4x %x1,%y0";
17516 return "stxvd2x %x1,%y0";
17519 else if (TARGET_ALTIVEC
&& src_vmx_p
)
17520 return "stvx %1,%y0";
17527 else if (dest_regno
>= 0
17528 && (GET_CODE (src
) == CONST_INT
17529 || GET_CODE (src
) == CONST_WIDE_INT
17530 || GET_CODE (src
) == CONST_DOUBLE
17531 || GET_CODE (src
) == CONST_VECTOR
))
17536 else if (TARGET_VSX
&& dest_vsx_p
&& zero_constant (src
, mode
))
17537 return "xxlxor %x0,%x0,%x0";
17539 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
17540 return output_vec_const_move (operands
);
17543 if (TARGET_DEBUG_ADDR
)
17545 fprintf (stderr
, "\n===== Bad 128 bit move:\n");
17546 debug_rtx (gen_rtx_SET (VOIDmode
, dest
, src
));
17549 gcc_unreachable ();
17552 /* Validate a 128-bit move. */
17554 rs6000_move_128bit_ok_p (rtx operands
[])
17556 enum machine_mode mode
= GET_MODE (operands
[0]);
17557 return (gpc_reg_operand (operands
[0], mode
)
17558 || gpc_reg_operand (operands
[1], mode
));
17561 /* Return true if a 128-bit move needs to be split. */
17563 rs6000_split_128bit_ok_p (rtx operands
[])
17565 if (!reload_completed
)
17568 if (!gpr_or_gpr_p (operands
[0], operands
[1]))
17571 if (quad_load_store_p (operands
[0], operands
[1]))
17578 /* Given a comparison operation, return the bit number in CCR to test. We
17579 know this is a valid comparison.
17581 SCC_P is 1 if this is for an scc. That means that %D will have been
17582 used instead of %C, so the bits will be in different places.
17584 Return -1 if OP isn't a valid comparison for some reason. */
17587 ccr_bit (rtx op
, int scc_p
)
17589 enum rtx_code code
= GET_CODE (op
);
17590 enum machine_mode cc_mode
;
17595 if (!COMPARISON_P (op
))
17598 reg
= XEXP (op
, 0);
17600 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
17602 cc_mode
= GET_MODE (reg
);
17603 cc_regnum
= REGNO (reg
);
17604 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
17606 validate_condition_mode (code
, cc_mode
);
17608 /* When generating a sCOND operation, only positive conditions are
17611 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
17612 || code
== GTU
|| code
== LTU
);
17617 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
17619 return base_bit
+ 2;
17620 case GT
: case GTU
: case UNLE
:
17621 return base_bit
+ 1;
17622 case LT
: case LTU
: case UNGE
:
17624 case ORDERED
: case UNORDERED
:
17625 return base_bit
+ 3;
17628 /* If scc, we will have done a cror to put the bit in the
17629 unordered position. So test that bit. For integer, this is ! LT
17630 unless this is an scc insn. */
17631 return scc_p
? base_bit
+ 3 : base_bit
;
17634 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
17637 gcc_unreachable ();
17641 /* Return the GOT register. */
17644 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
17646 /* The second flow pass currently (June 1999) can't update
17647 regs_ever_live without disturbing other parts of the compiler, so
17648 update it here to make the prolog/epilogue code happy. */
17649 if (!can_create_pseudo_p ()
17650 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
17651 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
17653 crtl
->uses_pic_offset_table
= 1;
17655 return pic_offset_table_rtx
;
17658 static rs6000_stack_t stack_info
;
17660 /* Function to init struct machine_function.
17661 This will be called, via a pointer variable,
17662 from push_function_context. */
17664 static struct machine_function
*
17665 rs6000_init_machine_status (void)
17667 stack_info
.reload_completed
= 0;
17668 return ggc_cleared_alloc
<machine_function
> ();
17671 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
17674 extract_MB (rtx op
)
17677 unsigned long val
= INTVAL (op
);
17679 /* If the high bit is zero, the value is the first 1 bit we find
17681 if ((val
& 0x80000000) == 0)
17683 gcc_assert (val
& 0xffffffff);
17686 while (((val
<<= 1) & 0x80000000) == 0)
17691 /* If the high bit is set and the low bit is not, or the mask is all
17692 1's, the value is zero. */
17693 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
17696 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17699 while (((val
>>= 1) & 1) != 0)
17706 extract_ME (rtx op
)
17709 unsigned long val
= INTVAL (op
);
17711 /* If the low bit is zero, the value is the first 1 bit we find from
17713 if ((val
& 1) == 0)
17715 gcc_assert (val
& 0xffffffff);
17718 while (((val
>>= 1) & 1) == 0)
17724 /* If the low bit is set and the high bit is not, or the mask is all
17725 1's, the value is 31. */
17726 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
17729 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17732 while (((val
<<= 1) & 0x80000000) != 0)
17738 /* Locate some local-dynamic symbol still in use by this function
17739 so that we can print its name in some tls_ld pattern. */
17741 static const char *
17742 rs6000_get_some_local_dynamic_name (void)
17746 if (cfun
->machine
->some_ld_name
)
17747 return cfun
->machine
->some_ld_name
;
17749 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
17751 && for_each_rtx (&PATTERN (insn
),
17752 rs6000_get_some_local_dynamic_name_1
, 0))
17753 return cfun
->machine
->some_ld_name
;
17755 gcc_unreachable ();
17758 /* Helper function for rs6000_get_some_local_dynamic_name. */
17761 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
17765 if (GET_CODE (x
) == SYMBOL_REF
)
17767 const char *str
= XSTR (x
, 0);
17768 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
17770 cfun
->machine
->some_ld_name
= str
;
17778 /* Write out a function code label. */
17781 rs6000_output_function_entry (FILE *file
, const char *fname
)
17783 if (fname
[0] != '.')
17785 switch (DEFAULT_ABI
)
17788 gcc_unreachable ();
17794 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
17804 RS6000_OUTPUT_BASENAME (file
, fname
);
17807 /* Print an operand. Recognize special options, documented below. */
17810 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
17811 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
17813 #define SMALL_DATA_RELOC "sda21"
17814 #define SMALL_DATA_REG 0
17818 print_operand (FILE *file
, rtx x
, int code
)
17821 unsigned HOST_WIDE_INT uval
;
17825 /* %a is output_address. */
17828 /* If constant, low-order 16 bits of constant, unsigned.
17829 Otherwise, write normally. */
17831 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
17833 print_operand (file
, x
, 0);
17837 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
17838 for 64-bit mask direction. */
17839 putc (((INTVAL (x
) & 1) == 0 ? 'r' : 'l'), file
);
17842 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
17846 /* Like 'J' but get to the GT bit only. */
17847 gcc_assert (REG_P (x
));
17849 /* Bit 1 is GT bit. */
17850 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
17852 /* Add one for shift count in rlinm for scc. */
17853 fprintf (file
, "%d", i
+ 1);
17857 /* X is a CR register. Print the number of the EQ bit of the CR */
17858 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17859 output_operand_lossage ("invalid %%E value");
17861 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
17865 /* X is a CR register. Print the shift count needed to move it
17866 to the high-order four bits. */
17867 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17868 output_operand_lossage ("invalid %%f value");
17870 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
17874 /* Similar, but print the count for the rotate in the opposite
17876 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17877 output_operand_lossage ("invalid %%F value");
17879 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
17883 /* X is a constant integer. If it is negative, print "m",
17884 otherwise print "z". This is to make an aze or ame insn. */
17885 if (GET_CODE (x
) != CONST_INT
)
17886 output_operand_lossage ("invalid %%G value");
17887 else if (INTVAL (x
) >= 0)
17894 /* If constant, output low-order five bits. Otherwise, write
17897 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
17899 print_operand (file
, x
, 0);
17903 /* If constant, output low-order six bits. Otherwise, write
17906 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
17908 print_operand (file
, x
, 0);
17912 /* Print `i' if this is a constant, else nothing. */
17918 /* Write the bit number in CCR for jump. */
17919 i
= ccr_bit (x
, 0);
17921 output_operand_lossage ("invalid %%j code");
17923 fprintf (file
, "%d", i
);
17927 /* Similar, but add one for shift count in rlinm for scc and pass
17928 scc flag to `ccr_bit'. */
17929 i
= ccr_bit (x
, 1);
17931 output_operand_lossage ("invalid %%J code");
17933 /* If we want bit 31, write a shift count of zero, not 32. */
17934 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
17938 /* X must be a constant. Write the 1's complement of the
17941 output_operand_lossage ("invalid %%k value");
17943 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
17947 /* X must be a symbolic constant on ELF. Write an
17948 expression suitable for an 'addi' that adds in the low 16
17949 bits of the MEM. */
17950 if (GET_CODE (x
) == CONST
)
17952 if (GET_CODE (XEXP (x
, 0)) != PLUS
17953 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
17954 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
17955 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
17956 output_operand_lossage ("invalid %%K value");
17958 print_operand_address (file
, x
);
17959 fputs ("@l", file
);
17962 /* %l is output_asm_label. */
17965 /* Write second word of DImode or DFmode reference. Works on register
17966 or non-indexed memory only. */
17968 fputs (reg_names
[REGNO (x
) + 1], file
);
17969 else if (MEM_P (x
))
17971 /* Handle possible auto-increment. Since it is pre-increment and
17972 we have already done it, we can just use an offset of word. */
17973 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17974 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17975 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
17977 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17978 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
17981 output_address (XEXP (adjust_address_nv (x
, SImode
,
17985 if (small_data_operand (x
, GET_MODE (x
)))
17986 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17987 reg_names
[SMALL_DATA_REG
]);
17992 /* MB value for a mask operand. */
17993 if (! mask_operand (x
, SImode
))
17994 output_operand_lossage ("invalid %%m value");
17996 fprintf (file
, "%d", extract_MB (x
));
18000 /* ME value for a mask operand. */
18001 if (! mask_operand (x
, SImode
))
18002 output_operand_lossage ("invalid %%M value");
18004 fprintf (file
, "%d", extract_ME (x
));
18007 /* %n outputs the negative of its operand. */
18010 /* Write the number of elements in the vector times 4. */
18011 if (GET_CODE (x
) != PARALLEL
)
18012 output_operand_lossage ("invalid %%N value");
18014 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
18018 /* Similar, but subtract 1 first. */
18019 if (GET_CODE (x
) != PARALLEL
)
18020 output_operand_lossage ("invalid %%O value");
18022 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
18026 /* X is a CONST_INT that is a power of two. Output the logarithm. */
18029 || (i
= exact_log2 (INTVAL (x
))) < 0)
18030 output_operand_lossage ("invalid %%p value");
18032 fprintf (file
, "%d", i
);
18036 /* The operand must be an indirect memory reference. The result
18037 is the register name. */
18038 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
18039 || REGNO (XEXP (x
, 0)) >= 32)
18040 output_operand_lossage ("invalid %%P value");
18042 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
18046 /* This outputs the logical code corresponding to a boolean
18047 expression. The expression may have one or both operands
18048 negated (if one, only the first one). For condition register
18049 logical operations, it will also treat the negated
18050 CR codes as NOTs, but not handle NOTs of them. */
18052 const char *const *t
= 0;
18054 enum rtx_code code
= GET_CODE (x
);
18055 static const char * const tbl
[3][3] = {
18056 { "and", "andc", "nor" },
18057 { "or", "orc", "nand" },
18058 { "xor", "eqv", "xor" } };
18062 else if (code
== IOR
)
18064 else if (code
== XOR
)
18067 output_operand_lossage ("invalid %%q value");
18069 if (GET_CODE (XEXP (x
, 0)) != NOT
)
18073 if (GET_CODE (XEXP (x
, 1)) == NOT
)
18084 if (! TARGET_MFCRF
)
18090 /* X is a CR register. Print the mask for `mtcrf'. */
18091 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
18092 output_operand_lossage ("invalid %%R value");
18094 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
18098 /* Low 5 bits of 32 - value */
18100 output_operand_lossage ("invalid %%s value");
18102 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
18106 /* PowerPC64 mask position. All 0's is excluded.
18107 CONST_INT 32-bit mask is considered sign-extended so any
18108 transition must occur within the CONST_INT, not on the boundary. */
18109 if (! mask64_operand (x
, DImode
))
18110 output_operand_lossage ("invalid %%S value");
18114 if (uval
& 1) /* Clear Left */
18116 #if HOST_BITS_PER_WIDE_INT > 64
18117 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
18121 else /* Clear Right */
18124 #if HOST_BITS_PER_WIDE_INT > 64
18125 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
18131 gcc_assert (i
>= 0);
18132 fprintf (file
, "%d", i
);
18136 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
18137 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
18139 /* Bit 3 is OV bit. */
18140 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
18142 /* If we want bit 31, write a shift count of zero, not 32. */
18143 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
18147 /* Print the symbolic name of a branch target register. */
18148 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
18149 && REGNO (x
) != CTR_REGNO
))
18150 output_operand_lossage ("invalid %%T value");
18151 else if (REGNO (x
) == LR_REGNO
)
18152 fputs ("lr", file
);
18154 fputs ("ctr", file
);
18158 /* High-order 16 bits of constant for use in unsigned operand. */
18160 output_operand_lossage ("invalid %%u value");
18162 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
18163 (INTVAL (x
) >> 16) & 0xffff);
18167 /* High-order 16 bits of constant for use in signed operand. */
18169 output_operand_lossage ("invalid %%v value");
18171 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
18172 (INTVAL (x
) >> 16) & 0xffff);
18176 /* Print `u' if this has an auto-increment or auto-decrement. */
18178 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
18179 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
18180 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
18185 /* Print the trap code for this operand. */
18186 switch (GET_CODE (x
))
18189 fputs ("eq", file
); /* 4 */
18192 fputs ("ne", file
); /* 24 */
18195 fputs ("lt", file
); /* 16 */
18198 fputs ("le", file
); /* 20 */
18201 fputs ("gt", file
); /* 8 */
18204 fputs ("ge", file
); /* 12 */
18207 fputs ("llt", file
); /* 2 */
18210 fputs ("lle", file
); /* 6 */
18213 fputs ("lgt", file
); /* 1 */
18216 fputs ("lge", file
); /* 5 */
18219 gcc_unreachable ();
18224 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
18227 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
18228 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
18230 print_operand (file
, x
, 0);
18234 /* MB value for a PowerPC64 rldic operand. */
18235 i
= clz_hwi (INTVAL (x
));
18237 fprintf (file
, "%d", i
);
18241 /* X is a FPR or Altivec register used in a VSX context. */
18242 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
18243 output_operand_lossage ("invalid %%x value");
18246 int reg
= REGNO (x
);
18247 int vsx_reg
= (FP_REGNO_P (reg
)
18249 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
18251 #ifdef TARGET_REGNAMES
18252 if (TARGET_REGNAMES
)
18253 fprintf (file
, "%%vs%d", vsx_reg
);
18256 fprintf (file
, "%d", vsx_reg
);
18262 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
18263 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
18264 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
18269 /* Like 'L', for third word of TImode/PTImode */
18271 fputs (reg_names
[REGNO (x
) + 2], file
);
18272 else if (MEM_P (x
))
18274 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
18275 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18276 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
18277 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18278 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
18280 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
18281 if (small_data_operand (x
, GET_MODE (x
)))
18282 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18283 reg_names
[SMALL_DATA_REG
]);
18288 /* X is a SYMBOL_REF. Write out the name preceded by a
18289 period and without any trailing data in brackets. Used for function
18290 names. If we are configured for System V (or the embedded ABI) on
18291 the PowerPC, do not emit the period, since those systems do not use
18292 TOCs and the like. */
18293 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
18295 /* For macho, check to see if we need a stub. */
18298 const char *name
= XSTR (x
, 0);
18300 if (darwin_emit_branch_islands
18301 && MACHOPIC_INDIRECT
18302 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
18303 name
= machopic_indirection_name (x
, /*stub_p=*/true);
18305 assemble_name (file
, name
);
18307 else if (!DOT_SYMBOLS
)
18308 assemble_name (file
, XSTR (x
, 0));
18310 rs6000_output_function_entry (file
, XSTR (x
, 0));
18314 /* Like 'L', for last word of TImode/PTImode. */
18316 fputs (reg_names
[REGNO (x
) + 3], file
);
18317 else if (MEM_P (x
))
18319 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
18320 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18321 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
18322 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18323 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
18325 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
18326 if (small_data_operand (x
, GET_MODE (x
)))
18327 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18328 reg_names
[SMALL_DATA_REG
]);
18332 /* Print AltiVec or SPE memory operand. */
18337 gcc_assert (MEM_P (x
));
18341 /* Ugly hack because %y is overloaded. */
18342 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
18343 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
18344 || GET_MODE (x
) == TFmode
18345 || GET_MODE (x
) == TImode
18346 || GET_MODE (x
) == PTImode
))
18348 /* Handle [reg]. */
18351 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
18354 /* Handle [reg+UIMM]. */
18355 else if (GET_CODE (tmp
) == PLUS
&&
18356 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
18360 gcc_assert (REG_P (XEXP (tmp
, 0)));
18362 x
= INTVAL (XEXP (tmp
, 1));
18363 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
18367 /* Fall through. Must be [reg+reg]. */
18369 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
18370 && GET_CODE (tmp
) == AND
18371 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
18372 && INTVAL (XEXP (tmp
, 1)) == -16)
18373 tmp
= XEXP (tmp
, 0);
18374 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
18375 && GET_CODE (tmp
) == PRE_MODIFY
)
18376 tmp
= XEXP (tmp
, 1);
18378 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
18381 if (!GET_CODE (tmp
) == PLUS
18382 || !REG_P (XEXP (tmp
, 0))
18383 || !REG_P (XEXP (tmp
, 1)))
18385 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
18389 if (REGNO (XEXP (tmp
, 0)) == 0)
18390 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
18391 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
18393 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
18394 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
18401 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
18402 else if (MEM_P (x
))
18404 /* We need to handle PRE_INC and PRE_DEC here, since we need to
18405 know the width from the mode. */
18406 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
18407 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
18408 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
18409 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18410 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
18411 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
18412 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18413 output_address (XEXP (XEXP (x
, 0), 1));
18415 output_address (XEXP (x
, 0));
18419 if (toc_relative_expr_p (x
, false))
18420 /* This hack along with a corresponding hack in
18421 rs6000_output_addr_const_extra arranges to output addends
18422 where the assembler expects to find them. eg.
18423 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
18424 without this hack would be output as "x@toc+4". We
18426 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
18428 output_addr_const (file
, x
);
18433 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
18437 output_operand_lossage ("invalid %%xn code");
18441 /* Print the address of an operand. */
18444 print_operand_address (FILE *file
, rtx x
)
18447 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
18448 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
18449 || GET_CODE (x
) == LABEL_REF
)
18451 output_addr_const (file
, x
);
18452 if (small_data_operand (x
, GET_MODE (x
)))
18453 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18454 reg_names
[SMALL_DATA_REG
]);
18456 gcc_assert (!TARGET_TOC
);
18458 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
18459 && REG_P (XEXP (x
, 1)))
18461 if (REGNO (XEXP (x
, 0)) == 0)
18462 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
18463 reg_names
[ REGNO (XEXP (x
, 0)) ]);
18465 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
18466 reg_names
[ REGNO (XEXP (x
, 1)) ]);
18468 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
18469 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
18470 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
18471 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
18473 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
18474 && CONSTANT_P (XEXP (x
, 1)))
18476 fprintf (file
, "lo16(");
18477 output_addr_const (file
, XEXP (x
, 1));
18478 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
18482 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
18483 && CONSTANT_P (XEXP (x
, 1)))
18485 output_addr_const (file
, XEXP (x
, 1));
18486 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
18489 else if (toc_relative_expr_p (x
, false))
18491 /* This hack along with a corresponding hack in
18492 rs6000_output_addr_const_extra arranges to output addends
18493 where the assembler expects to find them. eg.
18495 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
18496 without this hack would be output as "x@toc+8@l(9)". We
18497 want "x+8@toc@l(9)". */
18498 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
18499 if (GET_CODE (x
) == LO_SUM
)
18500 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
18502 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
18505 gcc_unreachable ();
18508 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
18511 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
18513 if (GET_CODE (x
) == UNSPEC
)
18514 switch (XINT (x
, 1))
18516 case UNSPEC_TOCREL
:
18517 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
18518 && REG_P (XVECEXP (x
, 0, 1))
18519 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
18520 output_addr_const (file
, XVECEXP (x
, 0, 0));
18521 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
18523 if (INTVAL (tocrel_offset
) >= 0)
18524 fprintf (file
, "+");
18525 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
18527 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
18530 assemble_name (file
, toc_label_name
);
18532 else if (TARGET_ELF
)
18533 fputs ("@toc", file
);
18537 case UNSPEC_MACHOPIC_OFFSET
:
18538 output_addr_const (file
, XVECEXP (x
, 0, 0));
18540 machopic_output_function_base_name (file
);
18547 /* Target hook for assembling integer objects. The PowerPC version has
18548 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
18549 is defined. It also needs to handle DI-mode objects on 64-bit
18553 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
18555 #ifdef RELOCATABLE_NEEDS_FIXUP
18556 /* Special handling for SI values. */
18557 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
18559 static int recurse
= 0;
18561 /* For -mrelocatable, we mark all addresses that need to be fixed up in
18562 the .fixup section. Since the TOC section is already relocated, we
18563 don't need to mark it here. We used to skip the text section, but it
18564 should never be valid for relocated addresses to be placed in the text
18566 if (TARGET_RELOCATABLE
18567 && in_section
!= toc_section
18569 && !CONST_SCALAR_INT_P (x
)
18575 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
18577 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
18578 fprintf (asm_out_file
, "\t.long\t(");
18579 output_addr_const (asm_out_file
, x
);
18580 fprintf (asm_out_file
, ")@fixup\n");
18581 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
18582 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
18583 fprintf (asm_out_file
, "\t.long\t");
18584 assemble_name (asm_out_file
, buf
);
18585 fprintf (asm_out_file
, "\n\t.previous\n");
18589 /* Remove initial .'s to turn a -mcall-aixdesc function
18590 address into the address of the descriptor, not the function
18592 else if (GET_CODE (x
) == SYMBOL_REF
18593 && XSTR (x
, 0)[0] == '.'
18594 && DEFAULT_ABI
== ABI_AIX
)
18596 const char *name
= XSTR (x
, 0);
18597 while (*name
== '.')
18600 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
18604 #endif /* RELOCATABLE_NEEDS_FIXUP */
18605 return default_assemble_integer (x
, size
, aligned_p
);
18608 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
18609 /* Emit an assembler directive to set symbol visibility for DECL to
18610 VISIBILITY_TYPE. */
18613 rs6000_assemble_visibility (tree decl
, int vis
)
18618 /* Functions need to have their entry point symbol visibility set as
18619 well as their descriptor symbol visibility. */
18620 if (DEFAULT_ABI
== ABI_AIX
18622 && TREE_CODE (decl
) == FUNCTION_DECL
)
18624 static const char * const visibility_types
[] = {
18625 NULL
, "internal", "hidden", "protected"
18628 const char *name
, *type
;
18630 name
= ((* targetm
.strip_name_encoding
)
18631 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
18632 type
= visibility_types
[vis
];
18634 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
18635 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
18638 default_assemble_visibility (decl
, vis
);
18643 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
18645 /* Reversal of FP compares takes care -- an ordered compare
18646 becomes an unordered compare and vice versa. */
18647 if (mode
== CCFPmode
18648 && (!flag_finite_math_only
18649 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
18650 || code
== UNEQ
|| code
== LTGT
))
18651 return reverse_condition_maybe_unordered (code
);
18653 return reverse_condition (code
);
18656 /* Generate a compare for CODE. Return a brand-new rtx that
18657 represents the result of the compare. */
18660 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
18662 enum machine_mode comp_mode
;
18663 rtx compare_result
;
18664 enum rtx_code code
= GET_CODE (cmp
);
18665 rtx op0
= XEXP (cmp
, 0);
18666 rtx op1
= XEXP (cmp
, 1);
18668 if (FLOAT_MODE_P (mode
))
18669 comp_mode
= CCFPmode
;
18670 else if (code
== GTU
|| code
== LTU
18671 || code
== GEU
|| code
== LEU
)
18672 comp_mode
= CCUNSmode
;
18673 else if ((code
== EQ
|| code
== NE
)
18674 && unsigned_reg_p (op0
)
18675 && (unsigned_reg_p (op1
)
18676 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
18677 /* These are unsigned values, perhaps there will be a later
18678 ordering compare that can be shared with this one. */
18679 comp_mode
= CCUNSmode
;
18681 comp_mode
= CCmode
;
18683 /* If we have an unsigned compare, make sure we don't have a signed value as
18685 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
18686 && INTVAL (op1
) < 0)
18688 op0
= copy_rtx_if_shared (op0
);
18689 op1
= force_reg (GET_MODE (op0
), op1
);
18690 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
18693 /* First, the compare. */
18694 compare_result
= gen_reg_rtx (comp_mode
);
18696 /* E500 FP compare instructions on the GPRs. Yuck! */
18697 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
18698 && FLOAT_MODE_P (mode
))
18700 rtx cmp
, or_result
, compare_result2
;
18701 enum machine_mode op_mode
= GET_MODE (op0
);
18704 if (op_mode
== VOIDmode
)
18705 op_mode
= GET_MODE (op1
);
18707 /* First reverse the condition codes that aren't directly supported. */
18715 code
= reverse_condition_maybe_unordered (code
);
18728 gcc_unreachable ();
18731 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
18732 This explains the following mess. */
18740 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18741 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
18742 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
18746 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18747 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
18748 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
18752 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18753 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
18754 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
18758 gcc_unreachable ();
18767 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18768 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
18769 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
18773 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18774 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
18775 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
18779 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18780 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
18781 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
18785 gcc_unreachable ();
18794 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18795 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
18796 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
18800 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18801 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
18802 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
18806 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18807 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
18808 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
18812 gcc_unreachable ();
18817 gcc_unreachable ();
18820 /* Synthesize LE and GE from LT/GT || EQ. */
18821 if (code
== LE
|| code
== GE
)
18825 compare_result2
= gen_reg_rtx (CCFPmode
);
18831 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18832 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
18833 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
18837 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18838 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
18839 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
18843 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18844 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
18845 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
18849 gcc_unreachable ();
18854 /* OR them together. */
18855 or_result
= gen_reg_rtx (CCFPmode
);
18856 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
18858 compare_result
= or_result
;
18861 code
= reverse_p
? NE
: EQ
;
18867 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
18868 CLOBBERs to match cmptf_internal2 pattern. */
18869 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
18870 && GET_MODE (op0
) == TFmode
18871 && !TARGET_IEEEQUAD
18872 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
18873 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
18875 gen_rtx_SET (VOIDmode
,
18877 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
18878 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18879 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18880 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18881 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18882 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18883 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18884 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18885 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18886 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
18887 else if (GET_CODE (op1
) == UNSPEC
18888 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
18890 rtx op1b
= XVECEXP (op1
, 0, 0);
18891 comp_mode
= CCEQmode
;
18892 compare_result
= gen_reg_rtx (CCEQmode
);
18894 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
18896 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
18899 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
18900 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
18903 /* Some kinds of FP comparisons need an OR operation;
18904 under flag_finite_math_only we don't bother. */
18905 if (FLOAT_MODE_P (mode
)
18906 && !flag_finite_math_only
18907 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
18908 && (code
== LE
|| code
== GE
18909 || code
== UNEQ
|| code
== LTGT
18910 || code
== UNGT
|| code
== UNLT
))
18912 enum rtx_code or1
, or2
;
18913 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
18914 rtx or_result
= gen_reg_rtx (CCEQmode
);
18918 case LE
: or1
= LT
; or2
= EQ
; break;
18919 case GE
: or1
= GT
; or2
= EQ
; break;
18920 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
18921 case LTGT
: or1
= LT
; or2
= GT
; break;
18922 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
18923 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
18924 default: gcc_unreachable ();
18926 validate_condition_mode (or1
, comp_mode
);
18927 validate_condition_mode (or2
, comp_mode
);
18928 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
18929 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
18930 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
18931 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
18933 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
18935 compare_result
= or_result
;
18939 validate_condition_mode (code
, GET_MODE (compare_result
));
18941 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
18945 /* Emit the RTL for an sISEL pattern. */
18948 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
18950 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
18954 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
18957 enum machine_mode op_mode
;
18958 enum rtx_code cond_code
;
18959 rtx result
= operands
[0];
18961 if (TARGET_ISEL
&& (mode
== SImode
|| mode
== DImode
))
18963 rs6000_emit_sISEL (mode
, operands
);
18967 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
18968 cond_code
= GET_CODE (condition_rtx
);
18970 if (FLOAT_MODE_P (mode
)
18971 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
18975 PUT_MODE (condition_rtx
, SImode
);
18976 t
= XEXP (condition_rtx
, 0);
18978 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
18980 if (cond_code
== NE
)
18981 emit_insn (gen_e500_flip_gt_bit (t
, t
));
18983 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
18987 if (cond_code
== NE
18988 || cond_code
== GE
|| cond_code
== LE
18989 || cond_code
== GEU
|| cond_code
== LEU
18990 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
18992 rtx not_result
= gen_reg_rtx (CCEQmode
);
18993 rtx not_op
, rev_cond_rtx
;
18994 enum machine_mode cc_mode
;
18996 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
18998 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
18999 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
19000 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
19001 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
19002 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
19005 op_mode
= GET_MODE (XEXP (operands
[1], 0));
19006 if (op_mode
== VOIDmode
)
19007 op_mode
= GET_MODE (XEXP (operands
[1], 1));
19009 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
19011 PUT_MODE (condition_rtx
, DImode
);
19012 convert_move (result
, condition_rtx
, 0);
19016 PUT_MODE (condition_rtx
, SImode
);
19017 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
19021 /* Emit a branch of kind CODE to location LOC. */
19024 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
19026 rtx condition_rtx
, loc_ref
;
19028 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
19029 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
19030 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
19031 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
19032 loc_ref
, pc_rtx
)));
19035 /* Return the string to output a conditional branch to LABEL, which is
19036 the operand template of the label, or NULL if the branch is really a
19037 conditional return.
19039 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
19040 condition code register and its mode specifies what kind of
19041 comparison we made.
19043 REVERSED is nonzero if we should reverse the sense of the comparison.
19045 INSN is the insn. */
19048 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
19050 static char string
[64];
19051 enum rtx_code code
= GET_CODE (op
);
19052 rtx cc_reg
= XEXP (op
, 0);
19053 enum machine_mode mode
= GET_MODE (cc_reg
);
19054 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
19055 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
19056 int really_reversed
= reversed
^ need_longbranch
;
19062 validate_condition_mode (code
, mode
);
19064 /* Work out which way this really branches. We could use
19065 reverse_condition_maybe_unordered here always but this
19066 makes the resulting assembler clearer. */
19067 if (really_reversed
)
19069 /* Reversal of FP compares takes care -- an ordered compare
19070 becomes an unordered compare and vice versa. */
19071 if (mode
== CCFPmode
)
19072 code
= reverse_condition_maybe_unordered (code
);
19074 code
= reverse_condition (code
);
19077 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
19079 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
19084 /* Opposite of GT. */
19093 gcc_unreachable ();
19099 /* Not all of these are actually distinct opcodes, but
19100 we distinguish them for clarity of the resulting assembler. */
19101 case NE
: case LTGT
:
19102 ccode
= "ne"; break;
19103 case EQ
: case UNEQ
:
19104 ccode
= "eq"; break;
19106 ccode
= "ge"; break;
19107 case GT
: case GTU
: case UNGT
:
19108 ccode
= "gt"; break;
19110 ccode
= "le"; break;
19111 case LT
: case LTU
: case UNLT
:
19112 ccode
= "lt"; break;
19113 case UNORDERED
: ccode
= "un"; break;
19114 case ORDERED
: ccode
= "nu"; break;
19115 case UNGE
: ccode
= "nl"; break;
19116 case UNLE
: ccode
= "ng"; break;
19118 gcc_unreachable ();
19121 /* Maybe we have a guess as to how likely the branch is. */
19123 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
19124 if (note
!= NULL_RTX
)
19126 /* PROB is the difference from 50%. */
19127 int prob
= XINT (note
, 0) - REG_BR_PROB_BASE
/ 2;
19129 /* Only hint for highly probable/improbable branches on newer
19130 cpus as static prediction overrides processor dynamic
19131 prediction. For older cpus we may as well always hint, but
19132 assume not taken for branches that are very close to 50% as a
19133 mispredicted taken branch is more expensive than a
19134 mispredicted not-taken branch. */
19135 if (rs6000_always_hint
19136 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
19137 && br_prob_note_reliable_p (note
)))
19139 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
19140 && ((prob
> 0) ^ need_longbranch
))
19148 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
19150 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
19152 /* We need to escape any '%' characters in the reg_names string.
19153 Assume they'd only be the first character.... */
19154 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
19156 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
19160 /* If the branch distance was too far, we may have to use an
19161 unconditional branch to go the distance. */
19162 if (need_longbranch
)
19163 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
19165 s
+= sprintf (s
, ",%s", label
);
19171 /* Return the string to flip the GT bit on a CR. */
19173 output_e500_flip_gt_bit (rtx dst
, rtx src
)
19175 static char string
[64];
19178 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
19179 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
19182 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
19183 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
19185 sprintf (string
, "crnot %d,%d", a
, b
);
19189 /* Return insn for VSX or Altivec comparisons. */
19192 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
19195 enum machine_mode mode
= GET_MODE (op0
);
19203 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
19213 mask
= gen_reg_rtx (mode
);
19214 emit_insn (gen_rtx_SET (VOIDmode
,
19216 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
19223 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
19224 DMODE is expected destination mode. This is a recursive function. */
19227 rs6000_emit_vector_compare (enum rtx_code rcode
,
19229 enum machine_mode dmode
)
19232 bool swap_operands
= false;
19233 bool try_again
= false;
19235 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
19236 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
19238 /* See if the comparison works as is. */
19239 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
19247 swap_operands
= true;
19252 swap_operands
= true;
19260 /* Invert condition and try again.
19261 e.g., A != B becomes ~(A==B). */
19263 enum rtx_code rev_code
;
19264 enum insn_code nor_code
;
19267 rev_code
= reverse_condition_maybe_unordered (rcode
);
19268 if (rev_code
== UNKNOWN
)
19271 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
19272 if (nor_code
== CODE_FOR_nothing
)
19275 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
19279 mask
= gen_reg_rtx (dmode
);
19280 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
19288 /* Try GT/GTU/LT/LTU OR EQ */
19291 enum insn_code ior_code
;
19292 enum rtx_code new_code
;
19313 gcc_unreachable ();
19316 ior_code
= optab_handler (ior_optab
, dmode
);
19317 if (ior_code
== CODE_FOR_nothing
)
19320 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
19324 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
19328 mask
= gen_reg_rtx (dmode
);
19329 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
19347 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
19352 /* You only get two chances. */
19356 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
19357 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
19358 operands for the relation operation COND. */
19361 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
19362 rtx cond
, rtx cc_op0
, rtx cc_op1
)
19364 enum machine_mode dest_mode
= GET_MODE (dest
);
19365 enum machine_mode mask_mode
= GET_MODE (cc_op0
);
19366 enum rtx_code rcode
= GET_CODE (cond
);
19367 enum machine_mode cc_mode
= CCmode
;
19371 bool invert_move
= false;
19373 if (VECTOR_UNIT_NONE_P (dest_mode
))
19376 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
19377 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
19381 /* Swap operands if we can, and fall back to doing the operation as
19382 specified, and doing a NOR to invert the test. */
19388 /* Invert condition and try again.
19389 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
19390 invert_move
= true;
19391 rcode
= reverse_condition_maybe_unordered (rcode
);
19392 if (rcode
== UNKNOWN
)
19396 /* Mark unsigned tests with CCUNSmode. */
19401 cc_mode
= CCUNSmode
;
19408 /* Get the vector mask for the given relational operations. */
19409 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
19417 op_true
= op_false
;
19421 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
19422 CONST0_RTX (dest_mode
));
19423 emit_insn (gen_rtx_SET (VOIDmode
,
19425 gen_rtx_IF_THEN_ELSE (dest_mode
,
19432 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
19433 operands of the last comparison is nonzero/true, FALSE_COND if it
19434 is zero/false. Return 0 if the hardware has no such operation. */
19437 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
19439 enum rtx_code code
= GET_CODE (op
);
19440 rtx op0
= XEXP (op
, 0);
19441 rtx op1
= XEXP (op
, 1);
19442 REAL_VALUE_TYPE c1
;
19443 enum machine_mode compare_mode
= GET_MODE (op0
);
19444 enum machine_mode result_mode
= GET_MODE (dest
);
19446 bool is_against_zero
;
19448 /* These modes should always match. */
19449 if (GET_MODE (op1
) != compare_mode
19450 /* In the isel case however, we can use a compare immediate, so
19451 op1 may be a small constant. */
19452 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
19454 if (GET_MODE (true_cond
) != result_mode
)
19456 if (GET_MODE (false_cond
) != result_mode
)
19459 /* Don't allow using floating point comparisons for integer results for
19461 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
19464 /* First, work out if the hardware can do this at all, or
19465 if it's too slow.... */
19466 if (!FLOAT_MODE_P (compare_mode
))
19469 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
19472 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
19473 && SCALAR_FLOAT_MODE_P (compare_mode
))
19476 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
19478 /* A floating-point subtract might overflow, underflow, or produce
19479 an inexact result, thus changing the floating-point flags, so it
19480 can't be generated if we care about that. It's safe if one side
19481 of the construct is zero, since then no subtract will be
19483 if (SCALAR_FLOAT_MODE_P (compare_mode
)
19484 && flag_trapping_math
&& ! is_against_zero
)
19487 /* Eliminate half of the comparisons by switching operands, this
19488 makes the remaining code simpler. */
19489 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
19490 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
19492 code
= reverse_condition_maybe_unordered (code
);
19494 true_cond
= false_cond
;
19498 /* UNEQ and LTGT take four instructions for a comparison with zero,
19499 it'll probably be faster to use a branch here too. */
19500 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
19503 if (GET_CODE (op1
) == CONST_DOUBLE
)
19504 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
19506 /* We're going to try to implement comparisons by performing
19507 a subtract, then comparing against zero. Unfortunately,
19508 Inf - Inf is NaN which is not zero, and so if we don't
19509 know that the operand is finite and the comparison
19510 would treat EQ different to UNORDERED, we can't do it. */
19511 if (HONOR_INFINITIES (compare_mode
)
19512 && code
!= GT
&& code
!= UNGE
19513 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
19514 /* Constructs of the form (a OP b ? a : b) are safe. */
19515 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
19516 || (! rtx_equal_p (op0
, true_cond
)
19517 && ! rtx_equal_p (op1
, true_cond
))))
19520 /* At this point we know we can use fsel. */
19522 /* Reduce the comparison to a comparison against zero. */
19523 if (! is_against_zero
)
19525 temp
= gen_reg_rtx (compare_mode
);
19526 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19527 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
19529 op1
= CONST0_RTX (compare_mode
);
19532 /* If we don't care about NaNs we can reduce some of the comparisons
19533 down to faster ones. */
19534 if (! HONOR_NANS (compare_mode
))
19540 true_cond
= false_cond
;
19553 /* Now, reduce everything down to a GE. */
19560 temp
= gen_reg_rtx (compare_mode
);
19561 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
19566 temp
= gen_reg_rtx (compare_mode
);
19567 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
19572 temp
= gen_reg_rtx (compare_mode
);
19573 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19574 gen_rtx_NEG (compare_mode
,
19575 gen_rtx_ABS (compare_mode
, op0
))));
19580 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
19581 temp
= gen_reg_rtx (result_mode
);
19582 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19583 gen_rtx_IF_THEN_ELSE (result_mode
,
19584 gen_rtx_GE (VOIDmode
,
19586 true_cond
, false_cond
)));
19587 false_cond
= true_cond
;
19590 temp
= gen_reg_rtx (compare_mode
);
19591 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
19596 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
19597 temp
= gen_reg_rtx (result_mode
);
19598 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
19599 gen_rtx_IF_THEN_ELSE (result_mode
,
19600 gen_rtx_GE (VOIDmode
,
19602 true_cond
, false_cond
)));
19603 true_cond
= false_cond
;
19606 temp
= gen_reg_rtx (compare_mode
);
19607 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
19612 gcc_unreachable ();
19615 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
19616 gen_rtx_IF_THEN_ELSE (result_mode
,
19617 gen_rtx_GE (VOIDmode
,
19619 true_cond
, false_cond
)));
19623 /* Same as above, but for ints (isel). */
19626 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
19628 rtx condition_rtx
, cr
;
19629 enum machine_mode mode
= GET_MODE (dest
);
19630 enum rtx_code cond_code
;
19631 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
19634 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
19637 /* We still have to do the compare, because isel doesn't do a
19638 compare, it just looks at the CRx bits set by a previous compare
19640 condition_rtx
= rs6000_generate_compare (op
, mode
);
19641 cond_code
= GET_CODE (condition_rtx
);
19642 cr
= XEXP (condition_rtx
, 0);
19643 signedp
= GET_MODE (cr
) == CCmode
;
19645 isel_func
= (mode
== SImode
19646 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
19647 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
19651 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
19652 /* isel handles these directly. */
19656 /* We need to swap the sense of the comparison. */
19659 true_cond
= false_cond
;
19661 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
19666 false_cond
= force_reg (mode
, false_cond
);
19667 if (true_cond
!= const0_rtx
)
19668 true_cond
= force_reg (mode
, true_cond
);
19670 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
19676 output_isel (rtx
*operands
)
19678 enum rtx_code code
;
19680 code
= GET_CODE (operands
[1]);
19682 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
19684 gcc_assert (GET_CODE (operands
[2]) == REG
19685 && GET_CODE (operands
[3]) == REG
);
19686 PUT_CODE (operands
[1], reverse_condition (code
));
19687 return "isel %0,%3,%2,%j1";
19690 return "isel %0,%2,%3,%j1";
19694 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
19696 enum machine_mode mode
= GET_MODE (op0
);
19700 /* VSX/altivec have direct min/max insns. */
19701 if ((code
== SMAX
|| code
== SMIN
)
19702 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
19703 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
19705 emit_insn (gen_rtx_SET (VOIDmode
,
19707 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
19711 if (code
== SMAX
|| code
== SMIN
)
19716 if (code
== SMAX
|| code
== UMAX
)
19717 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19718 op0
, op1
, mode
, 0);
19720 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19721 op1
, op0
, mode
, 0);
19722 gcc_assert (target
);
19723 if (target
!= dest
)
19724 emit_move_insn (dest
, target
);
19727 /* A subroutine of the atomic operation splitters. Jump to LABEL if
19728 COND is true. Mark the jump as unlikely to be taken. */
19731 emit_unlikely_jump (rtx cond
, rtx label
)
19733 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
19736 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
19737 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
19738 add_int_reg_note (x
, REG_BR_PROB
, very_unlikely
);
19741 /* A subroutine of the atomic operation splitters. Emit a load-locked
19742 instruction in MODE. For QI/HImode, possibly use a pattern than includes
19743 the zero_extend operation. */
19746 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
19748 rtx (*fn
) (rtx
, rtx
) = NULL
;
19753 fn
= gen_load_lockedqi
;
19756 fn
= gen_load_lockedhi
;
19759 if (GET_MODE (mem
) == QImode
)
19760 fn
= gen_load_lockedqi_si
;
19761 else if (GET_MODE (mem
) == HImode
)
19762 fn
= gen_load_lockedhi_si
;
19764 fn
= gen_load_lockedsi
;
19767 fn
= gen_load_lockeddi
;
19770 fn
= gen_load_lockedti
;
19773 gcc_unreachable ();
19775 emit_insn (fn (reg
, mem
));
19778 /* A subroutine of the atomic operation splitters. Emit a store-conditional
19779 instruction in MODE. */
19782 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
19784 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
19789 fn
= gen_store_conditionalqi
;
19792 fn
= gen_store_conditionalhi
;
19795 fn
= gen_store_conditionalsi
;
19798 fn
= gen_store_conditionaldi
;
19801 fn
= gen_store_conditionalti
;
19804 gcc_unreachable ();
19807 /* Emit sync before stwcx. to address PPC405 Erratum. */
19808 if (PPC405_ERRATUM77
)
19809 emit_insn (gen_hwsync ());
19811 emit_insn (fn (res
, mem
, val
));
19814 /* Expand barriers before and after a load_locked/store_cond sequence. */
19817 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
19819 rtx addr
= XEXP (mem
, 0);
19820 int strict_p
= (reload_in_progress
|| reload_completed
);
19822 if (!legitimate_indirect_address_p (addr
, strict_p
)
19823 && !legitimate_indexed_address_p (addr
, strict_p
))
19825 addr
= force_reg (Pmode
, addr
);
19826 mem
= replace_equiv_address_nv (mem
, addr
);
19831 case MEMMODEL_RELAXED
:
19832 case MEMMODEL_CONSUME
:
19833 case MEMMODEL_ACQUIRE
:
19835 case MEMMODEL_RELEASE
:
19836 case MEMMODEL_ACQ_REL
:
19837 emit_insn (gen_lwsync ());
19839 case MEMMODEL_SEQ_CST
:
19840 emit_insn (gen_hwsync ());
19843 gcc_unreachable ();
19849 rs6000_post_atomic_barrier (enum memmodel model
)
19853 case MEMMODEL_RELAXED
:
19854 case MEMMODEL_CONSUME
:
19855 case MEMMODEL_RELEASE
:
19857 case MEMMODEL_ACQUIRE
:
19858 case MEMMODEL_ACQ_REL
:
19859 case MEMMODEL_SEQ_CST
:
19860 emit_insn (gen_isync ());
19863 gcc_unreachable ();
19867 /* A subroutine of the various atomic expanders. For sub-word operations,
19868 we must adjust things to operate on SImode. Given the original MEM,
19869 return a new aligned memory. Also build and return the quantities by
19870 which to shift and mask. */
19873 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
19875 rtx addr
, align
, shift
, mask
, mem
;
19876 HOST_WIDE_INT shift_mask
;
19877 enum machine_mode mode
= GET_MODE (orig_mem
);
19879 /* For smaller modes, we have to implement this via SImode. */
19880 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
19882 addr
= XEXP (orig_mem
, 0);
19883 addr
= force_reg (GET_MODE (addr
), addr
);
19885 /* Aligned memory containing subword. Generate a new memory. We
19886 do not want any of the existing MEM_ATTR data, as we're now
19887 accessing memory outside the original object. */
19888 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
19889 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19890 mem
= gen_rtx_MEM (SImode
, align
);
19891 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
19892 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
19893 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
19895 /* Shift amount for subword relative to aligned word. */
19896 shift
= gen_reg_rtx (SImode
);
19897 addr
= gen_lowpart (SImode
, addr
);
19898 emit_insn (gen_rlwinm (shift
, addr
, GEN_INT (3), GEN_INT (shift_mask
)));
19899 if (WORDS_BIG_ENDIAN
)
19900 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
19901 shift
, 1, OPTAB_LIB_WIDEN
);
19904 /* Mask for insertion. */
19905 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
19906 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19912 /* A subroutine of the various atomic expanders. For sub-word operands,
19913 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
19916 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
19920 x
= gen_reg_rtx (SImode
);
19921 emit_insn (gen_rtx_SET (VOIDmode
, x
,
19922 gen_rtx_AND (SImode
,
19923 gen_rtx_NOT (SImode
, mask
),
19926 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
19931 /* A subroutine of the various atomic expanders. For sub-word operands,
19932 extract WIDE to NARROW via SHIFT. */
19935 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
19937 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
19938 wide
, 1, OPTAB_LIB_WIDEN
);
19939 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
19942 /* Expand an atomic compare and swap operation. */
19945 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
19947 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
19948 rtx label1
, label2
, x
, mask
, shift
;
19949 enum machine_mode mode
, orig_mode
;
19950 enum memmodel mod_s
, mod_f
;
19953 boolval
= operands
[0];
19954 retval
= operands
[1];
19956 oldval
= operands
[3];
19957 newval
= operands
[4];
19958 is_weak
= (INTVAL (operands
[5]) != 0);
19959 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
19960 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
19961 orig_mode
= mode
= GET_MODE (mem
);
19963 mask
= shift
= NULL_RTX
;
19964 if (mode
== QImode
|| mode
== HImode
)
19966 /* Before power8, we didn't have access to lbarx/lharx, so generate a
19967 lwarx and shift/mask operations. With power8, we need to do the
19968 comparison in SImode, but the store is still done in QI/HImode. */
19969 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
19971 if (!TARGET_SYNC_HI_QI
)
19973 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19975 /* Shift and mask OLDVAL into position with the word. */
19976 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
19977 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19979 /* Shift and mask NEWVAL into position within the word. */
19980 newval
= convert_modes (SImode
, mode
, newval
, 1);
19981 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
19982 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19985 /* Prepare to adjust the return value. */
19986 retval
= gen_reg_rtx (SImode
);
19989 else if (reg_overlap_mentioned_p (retval
, oldval
))
19990 oldval
= copy_to_reg (oldval
);
19992 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
19997 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19998 emit_label (XEXP (label1
, 0));
20000 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
20002 emit_load_locked (mode
, retval
, mem
);
20007 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
20008 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20011 cond
= gen_reg_rtx (CCmode
);
20012 /* If we have TImode, synthesize a comparison. */
20013 if (mode
!= TImode
)
20014 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
20017 rtx xor1_result
= gen_reg_rtx (DImode
);
20018 rtx xor2_result
= gen_reg_rtx (DImode
);
20019 rtx or_result
= gen_reg_rtx (DImode
);
20020 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
20021 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
20022 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
20023 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
20025 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
20026 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
20027 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
20028 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
20031 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
20033 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20034 emit_unlikely_jump (x
, label2
);
20038 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
20040 emit_store_conditional (orig_mode
, cond
, mem
, x
);
20044 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20045 emit_unlikely_jump (x
, label1
);
20048 if (mod_f
!= MEMMODEL_RELAXED
)
20049 emit_label (XEXP (label2
, 0));
20051 rs6000_post_atomic_barrier (mod_s
);
20053 if (mod_f
== MEMMODEL_RELAXED
)
20054 emit_label (XEXP (label2
, 0));
20057 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
20058 else if (mode
!= GET_MODE (operands
[1]))
20059 convert_move (operands
[1], retval
, 1);
20061 /* In all cases, CR0 contains EQ on success, and NE on failure. */
20062 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
20063 emit_insn (gen_rtx_SET (VOIDmode
, boolval
, x
));
20066 /* Expand an atomic exchange operation. */
20069 rs6000_expand_atomic_exchange (rtx operands
[])
20071 rtx retval
, mem
, val
, cond
;
20072 enum machine_mode mode
;
20073 enum memmodel model
;
20074 rtx label
, x
, mask
, shift
;
20076 retval
= operands
[0];
20079 model
= (enum memmodel
) INTVAL (operands
[3]);
20080 mode
= GET_MODE (mem
);
20082 mask
= shift
= NULL_RTX
;
20083 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
20085 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
20087 /* Shift and mask VAL into position with the word. */
20088 val
= convert_modes (SImode
, mode
, val
, 1);
20089 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
20090 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20092 /* Prepare to adjust the return value. */
20093 retval
= gen_reg_rtx (SImode
);
20097 mem
= rs6000_pre_atomic_barrier (mem
, model
);
20099 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
20100 emit_label (XEXP (label
, 0));
20102 emit_load_locked (mode
, retval
, mem
);
20106 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
20108 cond
= gen_reg_rtx (CCmode
);
20109 emit_store_conditional (mode
, cond
, mem
, x
);
20111 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20112 emit_unlikely_jump (x
, label
);
20114 rs6000_post_atomic_barrier (model
);
20117 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
20120 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
20121 to perform. MEM is the memory on which to operate. VAL is the second
20122 operand of the binary operator. BEFORE and AFTER are optional locations to
20123 return the value of MEM either before of after the operation. MODEL_RTX
20124 is a CONST_INT containing the memory model to use. */
20127 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
20128 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
20130 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
20131 enum machine_mode mode
= GET_MODE (mem
);
20132 enum machine_mode store_mode
= mode
;
20133 rtx label
, x
, cond
, mask
, shift
;
20134 rtx before
= orig_before
, after
= orig_after
;
20136 mask
= shift
= NULL_RTX
;
20137 /* On power8, we want to use SImode for the operation. On previous systems,
20138 use the operation in a subword and shift/mask to get the proper byte or
20140 if (mode
== QImode
|| mode
== HImode
)
20142 if (TARGET_SYNC_HI_QI
)
20144 val
= convert_modes (SImode
, mode
, val
, 1);
20146 /* Prepare to adjust the return value. */
20147 before
= gen_reg_rtx (SImode
);
20149 after
= gen_reg_rtx (SImode
);
20154 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
20156 /* Shift and mask VAL into position with the word. */
20157 val
= convert_modes (SImode
, mode
, val
, 1);
20158 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
20159 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20165 /* We've already zero-extended VAL. That is sufficient to
20166 make certain that it does not affect other bits. */
20171 /* If we make certain that all of the other bits in VAL are
20172 set, that will be sufficient to not affect other bits. */
20173 x
= gen_rtx_NOT (SImode
, mask
);
20174 x
= gen_rtx_IOR (SImode
, x
, val
);
20175 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
20182 /* These will all affect bits outside the field and need
20183 adjustment via MASK within the loop. */
20187 gcc_unreachable ();
20190 /* Prepare to adjust the return value. */
20191 before
= gen_reg_rtx (SImode
);
20193 after
= gen_reg_rtx (SImode
);
20194 store_mode
= mode
= SImode
;
20198 mem
= rs6000_pre_atomic_barrier (mem
, model
);
20200 label
= gen_label_rtx ();
20201 emit_label (label
);
20202 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
20204 if (before
== NULL_RTX
)
20205 before
= gen_reg_rtx (mode
);
20207 emit_load_locked (mode
, before
, mem
);
20211 x
= expand_simple_binop (mode
, AND
, before
, val
,
20212 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20213 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
20217 after
= expand_simple_binop (mode
, code
, before
, val
,
20218 after
, 1, OPTAB_LIB_WIDEN
);
20224 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
20225 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20226 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
20228 else if (store_mode
!= mode
)
20229 x
= convert_modes (store_mode
, mode
, x
, 1);
20231 cond
= gen_reg_rtx (CCmode
);
20232 emit_store_conditional (store_mode
, cond
, mem
, x
);
20234 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20235 emit_unlikely_jump (x
, label
);
20237 rs6000_post_atomic_barrier (model
);
20241 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
20242 then do the calcuations in a SImode register. */
20244 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
20246 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
20248 else if (store_mode
!= mode
)
20250 /* QImode/HImode on machines with lbarx/lharx where we do the native
20251 operation and then do the calcuations in a SImode register. */
20253 convert_move (orig_before
, before
, 1);
20255 convert_move (orig_after
, after
, 1);
20257 else if (orig_after
&& after
!= orig_after
)
20258 emit_move_insn (orig_after
, after
);
20261 /* Emit instructions to move SRC to DST. Called by splitters for
20262 multi-register moves. It will emit at most one instruction for
20263 each register that is accessed; that is, it won't emit li/lis pairs
20264 (or equivalent for 64-bit code). One of SRC or DST must be a hard
20268 rs6000_split_multireg_move (rtx dst
, rtx src
)
20270 /* The register number of the first register being moved. */
20272 /* The mode that is to be moved. */
20273 enum machine_mode mode
;
20274 /* The mode that the move is being done in, and its size. */
20275 enum machine_mode reg_mode
;
20277 /* The number of registers that will be moved. */
20280 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
20281 mode
= GET_MODE (dst
);
20282 nregs
= hard_regno_nregs
[reg
][mode
];
20283 if (FP_REGNO_P (reg
))
20284 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
20285 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
20286 else if (ALTIVEC_REGNO_P (reg
))
20287 reg_mode
= V16QImode
;
20288 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
20291 reg_mode
= word_mode
;
20292 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
20294 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
20296 /* TDmode residing in FP registers is special, since the ISA requires that
20297 the lower-numbered word of a register pair is always the most significant
20298 word, even in little-endian mode. This does not match the usual subreg
20299 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
20300 the appropriate constituent registers "by hand" in little-endian mode.
20302 Note we do not need to check for destructive overlap here since TDmode
20303 can only reside in even/odd register pairs. */
20304 if (FP_REGNO_P (reg
) && DECIMAL_FLOAT_MODE_P (mode
) && !BYTES_BIG_ENDIAN
)
20309 for (i
= 0; i
< nregs
; i
++)
20311 if (REG_P (src
) && FP_REGNO_P (REGNO (src
)))
20312 p_src
= gen_rtx_REG (reg_mode
, REGNO (src
) + nregs
- 1 - i
);
20314 p_src
= simplify_gen_subreg (reg_mode
, src
, mode
,
20315 i
* reg_mode_size
);
20317 if (REG_P (dst
) && FP_REGNO_P (REGNO (dst
)))
20318 p_dst
= gen_rtx_REG (reg_mode
, REGNO (dst
) + nregs
- 1 - i
);
20320 p_dst
= simplify_gen_subreg (reg_mode
, dst
, mode
,
20321 i
* reg_mode_size
);
20323 emit_insn (gen_rtx_SET (VOIDmode
, p_dst
, p_src
));
20329 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
20331 /* Move register range backwards, if we might have destructive
20334 for (i
= nregs
- 1; i
>= 0; i
--)
20335 emit_insn (gen_rtx_SET (VOIDmode
,
20336 simplify_gen_subreg (reg_mode
, dst
, mode
,
20337 i
* reg_mode_size
),
20338 simplify_gen_subreg (reg_mode
, src
, mode
,
20339 i
* reg_mode_size
)));
20345 bool used_update
= false;
20346 rtx restore_basereg
= NULL_RTX
;
20348 if (MEM_P (src
) && INT_REGNO_P (reg
))
20352 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
20353 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
20356 breg
= XEXP (XEXP (src
, 0), 0);
20357 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
20358 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
20359 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
20360 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
20361 src
= replace_equiv_address (src
, breg
);
20363 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
20365 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
20367 rtx basereg
= XEXP (XEXP (src
, 0), 0);
20370 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
20371 emit_insn (gen_rtx_SET (VOIDmode
, ndst
,
20372 gen_rtx_MEM (reg_mode
, XEXP (src
, 0))));
20373 used_update
= true;
20376 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
20377 XEXP (XEXP (src
, 0), 1)));
20378 src
= replace_equiv_address (src
, basereg
);
20382 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
20383 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
20384 src
= replace_equiv_address (src
, basereg
);
20388 breg
= XEXP (src
, 0);
20389 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
20390 breg
= XEXP (breg
, 0);
20392 /* If the base register we are using to address memory is
20393 also a destination reg, then change that register last. */
20395 && REGNO (breg
) >= REGNO (dst
)
20396 && REGNO (breg
) < REGNO (dst
) + nregs
)
20397 j
= REGNO (breg
) - REGNO (dst
);
20399 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
20403 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
20404 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
20407 breg
= XEXP (XEXP (dst
, 0), 0);
20408 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
20409 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
20410 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
20412 /* We have to update the breg before doing the store.
20413 Use store with update, if available. */
20417 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
20418 emit_insn (TARGET_32BIT
20419 ? (TARGET_POWERPC64
20420 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
20421 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
20422 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
20423 used_update
= true;
20426 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
20427 dst
= replace_equiv_address (dst
, breg
);
20429 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
20430 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
20432 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
20434 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
20437 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
20438 emit_insn (gen_rtx_SET (VOIDmode
,
20439 gen_rtx_MEM (reg_mode
, XEXP (dst
, 0)), nsrc
));
20440 used_update
= true;
20443 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
20444 XEXP (XEXP (dst
, 0), 1)));
20445 dst
= replace_equiv_address (dst
, basereg
);
20449 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
20450 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
20451 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
20453 && REG_P (offsetreg
)
20454 && REGNO (basereg
) != REGNO (offsetreg
));
20455 if (REGNO (basereg
) == 0)
20457 rtx tmp
= offsetreg
;
20458 offsetreg
= basereg
;
20461 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
20462 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
20463 dst
= replace_equiv_address (dst
, basereg
);
20466 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
20467 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
20470 for (i
= 0; i
< nregs
; i
++)
20472 /* Calculate index to next subword. */
20477 /* If compiler already emitted move of first word by
20478 store with update, no need to do anything. */
20479 if (j
== 0 && used_update
)
20482 emit_insn (gen_rtx_SET (VOIDmode
,
20483 simplify_gen_subreg (reg_mode
, dst
, mode
,
20484 j
* reg_mode_size
),
20485 simplify_gen_subreg (reg_mode
, src
, mode
,
20486 j
* reg_mode_size
)));
20488 if (restore_basereg
!= NULL_RTX
)
20489 emit_insn (restore_basereg
);
20494 /* This page contains routines that are used to determine what the
20495 function prologue and epilogue code will do and write them out. */
20500 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
20503 /* Return the first fixed-point register that is required to be
20504 saved. 32 if none. */
20507 first_reg_to_save (void)
20511 /* Find lowest numbered live register. */
20512 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
20513 if (save_reg_p (first_reg
))
20516 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
20517 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
20518 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
20519 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
20520 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
20521 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
20525 && crtl
->uses_pic_offset_table
20526 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
20527 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
20533 /* Similar, for FP regs. */
20536 first_fp_reg_to_save (void)
20540 /* Find lowest numbered live register. */
20541 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
20542 if (save_reg_p (first_reg
))
20548 /* Similar, for AltiVec regs. */
20551 first_altivec_reg_to_save (void)
20555 /* Stack frame remains as is unless we are in AltiVec ABI. */
20556 if (! TARGET_ALTIVEC_ABI
)
20557 return LAST_ALTIVEC_REGNO
+ 1;
20559 /* On Darwin, the unwind routines are compiled without
20560 TARGET_ALTIVEC, and use save_world to save/restore the
20561 altivec registers when necessary. */
20562 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
20563 && ! TARGET_ALTIVEC
)
20564 return FIRST_ALTIVEC_REGNO
+ 20;
20566 /* Find lowest numbered live register. */
20567 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20568 if (save_reg_p (i
))
20574 /* Return a 32-bit mask of the AltiVec registers we need to set in
20575 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
20576 the 32-bit word is 0. */
20578 static unsigned int
20579 compute_vrsave_mask (void)
20581 unsigned int i
, mask
= 0;
20583 /* On Darwin, the unwind routines are compiled without
20584 TARGET_ALTIVEC, and use save_world to save/restore the
20585 call-saved altivec registers when necessary. */
20586 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
20587 && ! TARGET_ALTIVEC
)
20590 /* First, find out if we use _any_ altivec registers. */
20591 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
20592 if (df_regs_ever_live_p (i
))
20593 mask
|= ALTIVEC_REG_BIT (i
);
20598 /* Next, remove the argument registers from the set. These must
20599 be in the VRSAVE mask set by the caller, so we don't need to add
20600 them in again. More importantly, the mask we compute here is
20601 used to generate CLOBBERs in the set_vrsave insn, and we do not
20602 wish the argument registers to die. */
20603 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
20604 mask
&= ~ALTIVEC_REG_BIT (i
);
20606 /* Similarly, remove the return value from the set. */
20609 diddle_return_value (is_altivec_return_reg
, &yes
);
20611 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
20617 /* For a very restricted set of circumstances, we can cut down the
20618 size of prologues/epilogues by calling our own save/restore-the-world
20622 compute_save_world_info (rs6000_stack_t
*info_ptr
)
20624 info_ptr
->world_save_p
= 1;
20625 info_ptr
->world_save_p
20626 = (WORLD_SAVE_P (info_ptr
)
20627 && DEFAULT_ABI
== ABI_DARWIN
20628 && !cfun
->has_nonlocal_label
20629 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
20630 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
20631 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
20632 && info_ptr
->cr_save_p
);
20634 /* This will not work in conjunction with sibcalls. Make sure there
20635 are none. (This check is expensive, but seldom executed.) */
20636 if (WORLD_SAVE_P (info_ptr
))
20639 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
20640 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
20642 info_ptr
->world_save_p
= 0;
20647 if (WORLD_SAVE_P (info_ptr
))
20649 /* Even if we're not touching VRsave, make sure there's room on the
20650 stack for it, if it looks like we're calling SAVE_WORLD, which
20651 will attempt to save it. */
20652 info_ptr
->vrsave_size
= 4;
20654 /* If we are going to save the world, we need to save the link register too. */
20655 info_ptr
->lr_save_p
= 1;
20657 /* "Save" the VRsave register too if we're saving the world. */
20658 if (info_ptr
->vrsave_mask
== 0)
20659 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
20661 /* Because the Darwin register save/restore routines only handle
20662 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
20664 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
20665 && (info_ptr
->first_altivec_reg_save
20666 >= FIRST_SAVED_ALTIVEC_REGNO
));
20673 is_altivec_return_reg (rtx reg
, void *xyes
)
20675 bool *yes
= (bool *) xyes
;
20676 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
20681 /* Look for user-defined global regs in the range FIRST to LAST-1.
20682 We should not restore these, and so cannot use lmw or out-of-line
20683 restore functions if there are any. We also can't save them
20684 (well, emit frame notes for them), because frame unwinding during
20685 exception handling will restore saved registers. */
20688 global_regs_p (unsigned first
, unsigned last
)
20690 while (first
< last
)
20691 if (global_regs
[first
++])
20696 /* Determine the strategy for savings/restoring registers. */
20699 SAVRES_MULTIPLE
= 0x1,
20700 SAVE_INLINE_FPRS
= 0x2,
20701 SAVE_INLINE_GPRS
= 0x4,
20702 REST_INLINE_FPRS
= 0x8,
20703 REST_INLINE_GPRS
= 0x10,
20704 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
20705 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
20706 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
20707 SAVE_INLINE_VRS
= 0x100,
20708 REST_INLINE_VRS
= 0x200
20712 rs6000_savres_strategy (rs6000_stack_t
*info
,
20713 bool using_static_chain_p
)
20718 if (TARGET_MULTIPLE
20719 && !TARGET_POWERPC64
20720 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
20721 && info
->first_gp_reg_save
< 31
20722 && !global_regs_p (info
->first_gp_reg_save
, 32))
20723 strategy
|= SAVRES_MULTIPLE
;
20725 if (crtl
->calls_eh_return
20726 || cfun
->machine
->ra_need_lr
)
20727 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
20728 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
20729 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20731 if (info
->first_fp_reg_save
== 64
20732 /* The out-of-line FP routines use double-precision stores;
20733 we can't use those routines if we don't have such stores. */
20734 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
20735 || global_regs_p (info
->first_fp_reg_save
, 64))
20736 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20738 if (info
->first_gp_reg_save
== 32
20739 || (!(strategy
& SAVRES_MULTIPLE
)
20740 && global_regs_p (info
->first_gp_reg_save
, 32)))
20741 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20743 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
20744 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
20745 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20747 /* Define cutoff for using out-of-line functions to save registers. */
20748 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
20750 if (!optimize_size
)
20752 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20753 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20754 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20758 /* Prefer out-of-line restore if it will exit. */
20759 if (info
->first_fp_reg_save
> 61)
20760 strategy
|= SAVE_INLINE_FPRS
;
20761 if (info
->first_gp_reg_save
> 29)
20763 if (info
->first_fp_reg_save
== 64)
20764 strategy
|= SAVE_INLINE_GPRS
;
20766 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20768 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
20769 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20772 else if (DEFAULT_ABI
== ABI_DARWIN
)
20774 if (info
->first_fp_reg_save
> 60)
20775 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20776 if (info
->first_gp_reg_save
> 29)
20777 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20778 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20782 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
20783 if (info
->first_fp_reg_save
> 61)
20784 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20785 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20786 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20789 /* Don't bother to try to save things out-of-line if r11 is occupied
20790 by the static chain. It would require too much fiddling and the
20791 static chain is rarely used anyway. FPRs are saved w.r.t the stack
20792 pointer on Darwin, and AIX uses r1 or r12. */
20793 if (using_static_chain_p
20794 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
20795 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
20797 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20799 /* We can only use the out-of-line routines to restore if we've
20800 saved all the registers from first_fp_reg_save in the prologue.
20801 Otherwise, we risk loading garbage. */
20802 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
20806 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
20807 if (!save_reg_p (i
))
20809 strategy
|= REST_INLINE_FPRS
;
20814 /* If we are going to use store multiple, then don't even bother
20815 with the out-of-line routines, since the store-multiple
20816 instruction will always be smaller. */
20817 if ((strategy
& SAVRES_MULTIPLE
))
20818 strategy
|= SAVE_INLINE_GPRS
;
20820 /* info->lr_save_p isn't yet set if the only reason lr needs to be
20821 saved is an out-of-line save or restore. Set up the value for
20822 the next test (excluding out-of-line gpr restore). */
20823 lr_save_p
= (info
->lr_save_p
20824 || !(strategy
& SAVE_INLINE_GPRS
)
20825 || !(strategy
& SAVE_INLINE_FPRS
)
20826 || !(strategy
& SAVE_INLINE_VRS
)
20827 || !(strategy
& REST_INLINE_FPRS
)
20828 || !(strategy
& REST_INLINE_VRS
));
20830 /* The situation is more complicated with load multiple. We'd
20831 prefer to use the out-of-line routines for restores, since the
20832 "exit" out-of-line routines can handle the restore of LR and the
20833 frame teardown. However if doesn't make sense to use the
20834 out-of-line routine if that is the only reason we'd need to save
20835 LR, and we can't use the "exit" out-of-line gpr restore if we
20836 have saved some fprs; In those cases it is advantageous to use
20837 load multiple when available. */
20838 if ((strategy
& SAVRES_MULTIPLE
)
20840 || info
->first_fp_reg_save
!= 64))
20841 strategy
|= REST_INLINE_GPRS
;
20843 /* Saving CR interferes with the exit routines used on the SPE, so
20846 && info
->spe_64bit_regs_used
20847 && info
->cr_save_p
)
20848 strategy
|= REST_INLINE_GPRS
;
20850 /* We can only use load multiple or the out-of-line routines to
20851 restore if we've used store multiple or out-of-line routines
20852 in the prologue, i.e. if we've saved all the registers from
20853 first_gp_reg_save. Otherwise, we risk loading garbage. */
20854 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
20855 == SAVE_INLINE_GPRS
)
20859 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
20860 if (!save_reg_p (i
))
20862 strategy
|= REST_INLINE_GPRS
;
20867 if (TARGET_ELF
&& TARGET_64BIT
)
20869 if (!(strategy
& SAVE_INLINE_FPRS
))
20870 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
20871 else if (!(strategy
& SAVE_INLINE_GPRS
)
20872 && info
->first_fp_reg_save
== 64)
20873 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
20875 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
20876 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
20878 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
20879 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
20884 /* Calculate the stack information for the current function. This is
20885 complicated by having two separate calling sequences, the AIX calling
20886 sequence and the V.4 calling sequence.
20888 AIX (and Darwin/Mac OS X) stack frames look like:
20890 SP----> +---------------------------------------+
20891 | back chain to caller | 0 0
20892 +---------------------------------------+
20893 | saved CR | 4 8 (8-11)
20894 +---------------------------------------+
20896 +---------------------------------------+
20897 | reserved for compilers | 12 24
20898 +---------------------------------------+
20899 | reserved for binders | 16 32
20900 +---------------------------------------+
20901 | saved TOC pointer | 20 40
20902 +---------------------------------------+
20903 | Parameter save area (P) | 24 48
20904 +---------------------------------------+
20905 | Alloca space (A) | 24+P etc.
20906 +---------------------------------------+
20907 | Local variable space (L) | 24+P+A
20908 +---------------------------------------+
20909 | Float/int conversion temporary (X) | 24+P+A+L
20910 +---------------------------------------+
20911 | Save area for AltiVec registers (W) | 24+P+A+L+X
20912 +---------------------------------------+
20913 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
20914 +---------------------------------------+
20915 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
20916 +---------------------------------------+
20917 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
20918 +---------------------------------------+
20919 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
20920 +---------------------------------------+
20921 old SP->| back chain to caller's caller |
20922 +---------------------------------------+
20924 The required alignment for AIX configurations is two words (i.e., 8
20927 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
20929 SP----> +---------------------------------------+
20930 | Back chain to caller | 0
20931 +---------------------------------------+
20932 | Save area for CR | 8
20933 +---------------------------------------+
20935 +---------------------------------------+
20936 | Saved TOC pointer | 24
20937 +---------------------------------------+
20938 | Parameter save area (P) | 32
20939 +---------------------------------------+
20940 | Alloca space (A) | 32+P
20941 +---------------------------------------+
20942 | Local variable space (L) | 32+P+A
20943 +---------------------------------------+
20944 | Save area for AltiVec registers (W) | 32+P+A+L
20945 +---------------------------------------+
20946 | AltiVec alignment padding (Y) | 32+P+A+L+W
20947 +---------------------------------------+
20948 | Save area for GP registers (G) | 32+P+A+L+W+Y
20949 +---------------------------------------+
20950 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
20951 +---------------------------------------+
20952 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
20953 +---------------------------------------+
20956 V.4 stack frames look like:
20958 SP----> +---------------------------------------+
20959 | back chain to caller | 0
20960 +---------------------------------------+
20961 | caller's saved LR | 4
20962 +---------------------------------------+
20963 | Parameter save area (P) | 8
20964 +---------------------------------------+
20965 | Alloca space (A) | 8+P
20966 +---------------------------------------+
20967 | Varargs save area (V) | 8+P+A
20968 +---------------------------------------+
20969 | Local variable space (L) | 8+P+A+V
20970 +---------------------------------------+
20971 | Float/int conversion temporary (X) | 8+P+A+V+L
20972 +---------------------------------------+
20973 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
20974 +---------------------------------------+
20975 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
20976 +---------------------------------------+
20977 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
20978 +---------------------------------------+
20979 | SPE: area for 64-bit GP registers |
20980 +---------------------------------------+
20981 | SPE alignment padding |
20982 +---------------------------------------+
20983 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
20984 +---------------------------------------+
20985 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
20986 +---------------------------------------+
20987 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
20988 +---------------------------------------+
20989 old SP->| back chain to caller's caller |
20990 +---------------------------------------+
20992 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
20993 given. (But note below and in sysv4.h that we require only 8 and
20994 may round up the size of our stack frame anyways. The historical
20995 reason is early versions of powerpc-linux which didn't properly
20996 align the stack at program startup. A happy side-effect is that
20997 -mno-eabi libraries can be used with -meabi programs.)
20999 The EABI configuration defaults to the V.4 layout. However,
21000 the stack alignment requirements may differ. If -mno-eabi is not
21001 given, the required stack alignment is 8 bytes; if -mno-eabi is
21002 given, the required alignment is 16 bytes. (But see V.4 comment
21005 #ifndef ABI_STACK_BOUNDARY
21006 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
21009 static rs6000_stack_t
*
21010 rs6000_stack_info (void)
21012 rs6000_stack_t
*info_ptr
= &stack_info
;
21013 int reg_size
= TARGET_32BIT
? 4 : 8;
21018 HOST_WIDE_INT non_fixed_size
;
21019 bool using_static_chain_p
;
21021 if (reload_completed
&& info_ptr
->reload_completed
)
21024 memset (info_ptr
, 0, sizeof (*info_ptr
));
21025 info_ptr
->reload_completed
= reload_completed
;
21029 /* Cache value so we don't rescan instruction chain over and over. */
21030 if (cfun
->machine
->insn_chain_scanned_p
== 0)
21031 cfun
->machine
->insn_chain_scanned_p
21032 = spe_func_has_64bit_regs_p () + 1;
21033 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
21036 /* Select which calling sequence. */
21037 info_ptr
->abi
= DEFAULT_ABI
;
21039 /* Calculate which registers need to be saved & save area size. */
21040 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
21041 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
21042 even if it currently looks like we won't. Reload may need it to
21043 get at a constant; if so, it will have already created a constant
21044 pool entry for it. */
21045 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
21046 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
21047 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
21048 && crtl
->uses_const_pool
21049 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
21050 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
21052 first_gp
= info_ptr
->first_gp_reg_save
;
21054 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
21056 /* For the SPE, we have an additional upper 32-bits on each GPR.
21057 Ideally we should save the entire 64-bits only when the upper
21058 half is used in SIMD instructions. Since we only record
21059 registers live (not the size they are used in), this proves
21060 difficult because we'd have to traverse the instruction chain at
21061 the right time, taking reload into account. This is a real pain,
21062 so we opt to save the GPRs in 64-bits always if but one register
21063 gets used in 64-bits. Otherwise, all the registers in the frame
21064 get saved in 32-bits.
21066 So... since when we save all GPRs (except the SP) in 64-bits, the
21067 traditional GP save area will be empty. */
21068 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
21069 info_ptr
->gp_size
= 0;
21071 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
21072 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
21074 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
21075 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
21076 - info_ptr
->first_altivec_reg_save
);
21078 /* Does this function call anything? */
21079 info_ptr
->calls_p
= (! crtl
->is_leaf
21080 || cfun
->machine
->ra_needs_full_frame
);
21082 /* Determine if we need to save the condition code registers. */
21083 if (df_regs_ever_live_p (CR2_REGNO
)
21084 || df_regs_ever_live_p (CR3_REGNO
)
21085 || df_regs_ever_live_p (CR4_REGNO
))
21087 info_ptr
->cr_save_p
= 1;
21088 if (DEFAULT_ABI
== ABI_V4
)
21089 info_ptr
->cr_size
= reg_size
;
21092 /* If the current function calls __builtin_eh_return, then we need
21093 to allocate stack space for registers that will hold data for
21094 the exception handler. */
21095 if (crtl
->calls_eh_return
)
21098 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
21101 /* SPE saves EH registers in 64-bits. */
21102 ehrd_size
= i
* (TARGET_SPE_ABI
21103 && info_ptr
->spe_64bit_regs_used
!= 0
21104 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
21109 /* In the ELFv2 ABI, we also need to allocate space for separate
21110 CR field save areas if the function calls __builtin_eh_return. */
21111 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
21113 /* This hard-codes that we have three call-saved CR fields. */
21114 ehcr_size
= 3 * reg_size
;
21115 /* We do *not* use the regular CR save mechanism. */
21116 info_ptr
->cr_save_p
= 0;
21121 /* Determine various sizes. */
21122 info_ptr
->reg_size
= reg_size
;
21123 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
21124 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
21125 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
21126 TARGET_ALTIVEC
? 16 : 8);
21127 if (FRAME_GROWS_DOWNWARD
)
21128 info_ptr
->vars_size
21129 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
21130 + info_ptr
->parm_size
,
21131 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
21132 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
21133 + info_ptr
->parm_size
);
21135 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
21136 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
21138 info_ptr
->spe_gp_size
= 0;
21140 if (TARGET_ALTIVEC_ABI
)
21141 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
21143 info_ptr
->vrsave_mask
= 0;
21145 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
21146 info_ptr
->vrsave_size
= 4;
21148 info_ptr
->vrsave_size
= 0;
21150 compute_save_world_info (info_ptr
);
21152 /* Calculate the offsets. */
21153 switch (DEFAULT_ABI
)
21157 gcc_unreachable ();
21162 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
21163 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
21165 if (TARGET_ALTIVEC_ABI
)
21167 info_ptr
->vrsave_save_offset
21168 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
21170 /* Align stack so vector save area is on a quadword boundary.
21171 The padding goes above the vectors. */
21172 if (info_ptr
->altivec_size
!= 0)
21173 info_ptr
->altivec_padding_size
21174 = info_ptr
->vrsave_save_offset
& 0xF;
21176 info_ptr
->altivec_padding_size
= 0;
21178 info_ptr
->altivec_save_offset
21179 = info_ptr
->vrsave_save_offset
21180 - info_ptr
->altivec_padding_size
21181 - info_ptr
->altivec_size
;
21182 gcc_assert (info_ptr
->altivec_size
== 0
21183 || info_ptr
->altivec_save_offset
% 16 == 0);
21185 /* Adjust for AltiVec case. */
21186 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
21189 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
21191 info_ptr
->ehcr_offset
= info_ptr
->ehrd_offset
- ehcr_size
;
21192 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
21193 info_ptr
->lr_save_offset
= 2*reg_size
;
21197 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
21198 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
21199 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
21201 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
21203 /* Align stack so SPE GPR save area is aligned on a
21204 double-word boundary. */
21205 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
21206 info_ptr
->spe_padding_size
21207 = 8 - (-info_ptr
->cr_save_offset
% 8);
21209 info_ptr
->spe_padding_size
= 0;
21211 info_ptr
->spe_gp_save_offset
21212 = info_ptr
->cr_save_offset
21213 - info_ptr
->spe_padding_size
21214 - info_ptr
->spe_gp_size
;
21216 /* Adjust for SPE case. */
21217 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
21219 else if (TARGET_ALTIVEC_ABI
)
21221 info_ptr
->vrsave_save_offset
21222 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
21224 /* Align stack so vector save area is on a quadword boundary. */
21225 if (info_ptr
->altivec_size
!= 0)
21226 info_ptr
->altivec_padding_size
21227 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
21229 info_ptr
->altivec_padding_size
= 0;
21231 info_ptr
->altivec_save_offset
21232 = info_ptr
->vrsave_save_offset
21233 - info_ptr
->altivec_padding_size
21234 - info_ptr
->altivec_size
;
21236 /* Adjust for AltiVec case. */
21237 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
21240 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
21241 info_ptr
->ehrd_offset
-= ehrd_size
;
21242 info_ptr
->lr_save_offset
= reg_size
;
21246 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
21247 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
21248 + info_ptr
->gp_size
21249 + info_ptr
->altivec_size
21250 + info_ptr
->altivec_padding_size
21251 + info_ptr
->spe_gp_size
21252 + info_ptr
->spe_padding_size
21255 + info_ptr
->cr_size
21256 + info_ptr
->vrsave_size
,
21259 non_fixed_size
= (info_ptr
->vars_size
21260 + info_ptr
->parm_size
21261 + info_ptr
->save_size
);
21263 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
21264 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
21266 /* Determine if we need to save the link register. */
21267 if (info_ptr
->calls_p
21268 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21270 && !TARGET_PROFILE_KERNEL
)
21271 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
21272 #ifdef TARGET_RELOCATABLE
21273 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
21275 || rs6000_ra_ever_killed ())
21276 info_ptr
->lr_save_p
= 1;
21278 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
21279 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
21280 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
21281 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
21282 using_static_chain_p
);
21284 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
21285 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
21286 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
21287 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
21288 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
21289 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
21290 info_ptr
->lr_save_p
= 1;
21292 if (info_ptr
->lr_save_p
)
21293 df_set_regs_ever_live (LR_REGNO
, true);
21295 /* Determine if we need to allocate any stack frame:
21297 For AIX we need to push the stack if a frame pointer is needed
21298 (because the stack might be dynamically adjusted), if we are
21299 debugging, if we make calls, or if the sum of fp_save, gp_save,
21300 and local variables are more than the space needed to save all
21301 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
21302 + 18*8 = 288 (GPR13 reserved).
21304 For V.4 we don't have the stack cushion that AIX uses, but assume
21305 that the debugger can handle stackless frames. */
21307 if (info_ptr
->calls_p
)
21308 info_ptr
->push_p
= 1;
21310 else if (DEFAULT_ABI
== ABI_V4
)
21311 info_ptr
->push_p
= non_fixed_size
!= 0;
21313 else if (frame_pointer_needed
)
21314 info_ptr
->push_p
= 1;
21316 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
21317 info_ptr
->push_p
= 1;
21320 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
21322 /* Zero offsets if we're not saving those registers. */
21323 if (info_ptr
->fp_size
== 0)
21324 info_ptr
->fp_save_offset
= 0;
21326 if (info_ptr
->gp_size
== 0)
21327 info_ptr
->gp_save_offset
= 0;
21329 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
21330 info_ptr
->altivec_save_offset
= 0;
21332 /* Zero VRSAVE offset if not saved and restored. */
21333 if (! TARGET_ALTIVEC_VRSAVE
|| info_ptr
->vrsave_mask
== 0)
21334 info_ptr
->vrsave_save_offset
= 0;
21336 if (! TARGET_SPE_ABI
21337 || info_ptr
->spe_64bit_regs_used
== 0
21338 || info_ptr
->spe_gp_size
== 0)
21339 info_ptr
->spe_gp_save_offset
= 0;
21341 if (! info_ptr
->lr_save_p
)
21342 info_ptr
->lr_save_offset
= 0;
21344 if (! info_ptr
->cr_save_p
)
21345 info_ptr
->cr_save_offset
= 0;
21350 /* Return true if the current function uses any GPRs in 64-bit SIMD
21354 spe_func_has_64bit_regs_p (void)
21358 /* Functions that save and restore all the call-saved registers will
21359 need to save/restore the registers in 64-bits. */
21360 if (crtl
->calls_eh_return
21361 || cfun
->calls_setjmp
21362 || crtl
->has_nonlocal_goto
)
21365 insns
= get_insns ();
21367 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
21373 /* FIXME: This should be implemented with attributes...
21375 (set_attr "spe64" "true")....then,
21376 if (get_spe64(insn)) return true;
21378 It's the only reliable way to do the stuff below. */
21380 i
= PATTERN (insn
);
21381 if (GET_CODE (i
) == SET
)
21383 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
21385 if (SPE_VECTOR_MODE (mode
))
21387 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
21397 debug_stack_info (rs6000_stack_t
*info
)
21399 const char *abi_string
;
21402 info
= rs6000_stack_info ();
21404 fprintf (stderr
, "\nStack information for function %s:\n",
21405 ((current_function_decl
&& DECL_NAME (current_function_decl
))
21406 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
21411 default: abi_string
= "Unknown"; break;
21412 case ABI_NONE
: abi_string
= "NONE"; break;
21413 case ABI_AIX
: abi_string
= "AIX"; break;
21414 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
21415 case ABI_DARWIN
: abi_string
= "Darwin"; break;
21416 case ABI_V4
: abi_string
= "V.4"; break;
21419 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
21421 if (TARGET_ALTIVEC_ABI
)
21422 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
21424 if (TARGET_SPE_ABI
)
21425 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
21427 if (info
->first_gp_reg_save
!= 32)
21428 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
21430 if (info
->first_fp_reg_save
!= 64)
21431 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
21433 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
21434 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
21435 info
->first_altivec_reg_save
);
21437 if (info
->lr_save_p
)
21438 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
21440 if (info
->cr_save_p
)
21441 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
21443 if (info
->vrsave_mask
)
21444 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
21447 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
21450 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
21452 if (info
->gp_save_offset
)
21453 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
21455 if (info
->fp_save_offset
)
21456 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
21458 if (info
->altivec_save_offset
)
21459 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
21460 info
->altivec_save_offset
);
21462 if (info
->spe_gp_save_offset
)
21463 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
21464 info
->spe_gp_save_offset
);
21466 if (info
->vrsave_save_offset
)
21467 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
21468 info
->vrsave_save_offset
);
21470 if (info
->lr_save_offset
)
21471 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
21473 if (info
->cr_save_offset
)
21474 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
21476 if (info
->varargs_save_offset
)
21477 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
21479 if (info
->total_size
)
21480 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
21483 if (info
->vars_size
)
21484 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
21487 if (info
->parm_size
)
21488 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
21490 if (info
->fixed_size
)
21491 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
21494 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
21496 if (info
->spe_gp_size
)
21497 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
21500 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
21502 if (info
->altivec_size
)
21503 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
21505 if (info
->vrsave_size
)
21506 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
21508 if (info
->altivec_padding_size
)
21509 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
21510 info
->altivec_padding_size
);
21512 if (info
->spe_padding_size
)
21513 fprintf (stderr
, "\tspe_padding_size = %5d\n",
21514 info
->spe_padding_size
);
21517 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
21519 if (info
->save_size
)
21520 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
21522 if (info
->reg_size
!= 4)
21523 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
21525 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
21527 fprintf (stderr
, "\n");
21531 rs6000_return_addr (int count
, rtx frame
)
21533 /* Currently we don't optimize very well between prolog and body
21534 code and for PIC code the code can be actually quite bad, so
21535 don't try to be too clever here. */
21537 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
21539 cfun
->machine
->ra_needs_full_frame
= 1;
21546 plus_constant (Pmode
,
21548 (gen_rtx_MEM (Pmode
,
21549 memory_address (Pmode
, frame
))),
21550 RETURN_ADDRESS_OFFSET
)));
21553 cfun
->machine
->ra_need_lr
= 1;
21554 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
21557 /* Say whether a function is a candidate for sibcall handling or not. */
21560 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
21565 fntype
= TREE_TYPE (decl
);
21567 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
21569 /* We can't do it if the called function has more vector parameters
21570 than the current function; there's nowhere to put the VRsave code. */
21571 if (TARGET_ALTIVEC_ABI
21572 && TARGET_ALTIVEC_VRSAVE
21573 && !(decl
&& decl
== current_function_decl
))
21575 function_args_iterator args_iter
;
21579 /* Functions with vector parameters are required to have a
21580 prototype, so the argument type info must be available
21582 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
21583 if (TREE_CODE (type
) == VECTOR_TYPE
21584 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
21587 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
21588 if (TREE_CODE (type
) == VECTOR_TYPE
21589 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
21596 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
21597 functions, because the callee may have a different TOC pointer to
21598 the caller and there's no way to ensure we restore the TOC when
21599 we return. With the secure-plt SYSV ABI we can't make non-local
21600 calls when -fpic/PIC because the plt call stubs use r30. */
21601 if (DEFAULT_ABI
== ABI_DARWIN
21602 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21604 && !DECL_EXTERNAL (decl
)
21605 && (*targetm
.binds_local_p
) (decl
))
21606 || (DEFAULT_ABI
== ABI_V4
21607 && (!TARGET_SECURE_PLT
21610 && (*targetm
.binds_local_p
) (decl
)))))
21612 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
21614 if (!lookup_attribute ("longcall", attr_list
)
21615 || lookup_attribute ("shortcall", attr_list
))
21623 rs6000_ra_ever_killed (void)
21629 if (cfun
->is_thunk
)
21632 if (cfun
->machine
->lr_save_state
)
21633 return cfun
->machine
->lr_save_state
- 1;
21635 /* regs_ever_live has LR marked as used if any sibcalls are present,
21636 but this should not force saving and restoring in the
21637 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
21638 clobbers LR, so that is inappropriate. */
21640 /* Also, the prologue can generate a store into LR that
21641 doesn't really count, like this:
21644 bcl to set PIC register
21648 When we're called from the epilogue, we need to avoid counting
21649 this as a store. */
21651 push_topmost_sequence ();
21652 top
= get_insns ();
21653 pop_topmost_sequence ();
21654 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
21656 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
21662 if (!SIBLING_CALL_P (insn
))
21665 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
21667 else if (set_of (reg
, insn
) != NULL_RTX
21668 && !prologue_epilogue_contains (insn
))
21675 /* Emit instructions needed to load the TOC register.
21676 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
21677 a constant pool; or for SVR4 -fpic. */
21680 rs6000_emit_load_toc_table (int fromprolog
)
21683 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
21685 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
21688 rtx lab
, tmp1
, tmp2
, got
;
21690 lab
= gen_label_rtx ();
21691 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
21692 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21694 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
21696 got
= rs6000_got_sym ();
21697 tmp1
= tmp2
= dest
;
21700 tmp1
= gen_reg_rtx (Pmode
);
21701 tmp2
= gen_reg_rtx (Pmode
);
21703 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
21704 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
21705 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
21706 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
21708 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
21710 emit_insn (gen_load_toc_v4_pic_si ());
21711 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21713 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
21716 rtx temp0
= (fromprolog
21717 ? gen_rtx_REG (Pmode
, 0)
21718 : gen_reg_rtx (Pmode
));
21724 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
21725 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21727 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
21728 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21730 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
21731 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21732 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
21738 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
21739 lab
= gen_label_rtx ();
21740 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
21741 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21742 if (TARGET_LINK_STACK
)
21743 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
21744 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
21746 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
21748 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
21750 /* This is for AIX code running in non-PIC ELF32. */
21753 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
21754 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21756 emit_insn (gen_elf_high (dest
, realsym
));
21757 emit_insn (gen_elf_low (dest
, dest
, realsym
));
21761 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
21764 emit_insn (gen_load_toc_aix_si (dest
));
21766 emit_insn (gen_load_toc_aix_di (dest
));
21770 /* Emit instructions to restore the link register after determining where
21771 its value has been stored. */
21774 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
21776 rs6000_stack_t
*info
= rs6000_stack_info ();
21779 operands
[0] = source
;
21780 operands
[1] = scratch
;
21782 if (info
->lr_save_p
)
21784 rtx frame_rtx
= stack_pointer_rtx
;
21785 HOST_WIDE_INT sp_offset
= 0;
21788 if (frame_pointer_needed
21789 || cfun
->calls_alloca
21790 || info
->total_size
> 32767)
21792 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
21793 emit_move_insn (operands
[1], tmp
);
21794 frame_rtx
= operands
[1];
21796 else if (info
->push_p
)
21797 sp_offset
= info
->total_size
;
21799 tmp
= plus_constant (Pmode
, frame_rtx
,
21800 info
->lr_save_offset
+ sp_offset
);
21801 tmp
= gen_frame_mem (Pmode
, tmp
);
21802 emit_move_insn (tmp
, operands
[0]);
21805 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
21807 /* Freeze lr_save_p. We've just emitted rtl that depends on the
21808 state of lr_save_p so any change from here on would be a bug. In
21809 particular, stop rs6000_ra_ever_killed from considering the SET
21810 of lr we may have added just above. */
21811 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
21814 static GTY(()) alias_set_type set
= -1;
21817 get_TOC_alias_set (void)
21820 set
= new_alias_set ();
21824 /* This returns nonzero if the current function uses the TOC. This is
21825 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
21826 is generated by the ABI_V4 load_toc_* patterns. */
21833 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
21836 rtx pat
= PATTERN (insn
);
21839 if (GET_CODE (pat
) == PARALLEL
)
21840 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
21842 rtx sub
= XVECEXP (pat
, 0, i
);
21843 if (GET_CODE (sub
) == USE
)
21845 sub
= XEXP (sub
, 0);
21846 if (GET_CODE (sub
) == UNSPEC
21847 && XINT (sub
, 1) == UNSPEC_TOC
)
21857 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
21859 rtx tocrel
, tocreg
, hi
;
21861 if (TARGET_DEBUG_ADDR
)
21863 if (GET_CODE (symbol
) == SYMBOL_REF
)
21864 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
21868 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
21869 GET_RTX_NAME (GET_CODE (symbol
)));
21870 debug_rtx (symbol
);
21874 if (!can_create_pseudo_p ())
21875 df_set_regs_ever_live (TOC_REGISTER
, true);
21877 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
21878 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
21879 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
21882 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
21883 if (largetoc_reg
!= NULL
)
21885 emit_move_insn (largetoc_reg
, hi
);
21888 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
21891 /* Issue assembly directives that create a reference to the given DWARF
21892 FRAME_TABLE_LABEL from the current function section. */
21894 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
21896 fprintf (asm_out_file
, "\t.ref %s\n",
21897 (* targetm
.strip_name_encoding
) (frame_table_label
));
21900 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
21901 and the change to the stack pointer. */
21904 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
21911 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21912 if (hard_frame_needed
)
21913 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
21914 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
21915 || (hard_frame_needed
21916 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
21919 p
= rtvec_alloc (i
);
21922 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
21923 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, const0_rtx
);
21926 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
21929 /* Emit the correct code for allocating stack space, as insns.
21930 If COPY_REG, make sure a copy of the old frame is left there.
21931 The generated code may use hard register 0 as a temporary. */
21934 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
21937 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21938 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
21939 rtx todec
= gen_int_mode (-size
, Pmode
);
21942 if (INTVAL (todec
) != -size
)
21944 warning (0, "stack frame too large");
21945 emit_insn (gen_trap ());
21949 if (crtl
->limit_stack
)
21951 if (REG_P (stack_limit_rtx
)
21952 && REGNO (stack_limit_rtx
) > 1
21953 && REGNO (stack_limit_rtx
) <= 31)
21955 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
21956 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
21959 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
21961 && DEFAULT_ABI
== ABI_V4
)
21963 rtx toload
= gen_rtx_CONST (VOIDmode
,
21964 gen_rtx_PLUS (Pmode
,
21968 emit_insn (gen_elf_high (tmp_reg
, toload
));
21969 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
21970 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
21974 warning (0, "stack limit expression is not supported");
21980 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
21982 emit_move_insn (copy_reg
, stack_reg
);
21987 /* Need a note here so that try_split doesn't get confused. */
21988 if (get_last_insn () == NULL_RTX
)
21989 emit_note (NOTE_INSN_DELETED
);
21990 insn
= emit_move_insn (tmp_reg
, todec
);
21991 try_split (PATTERN (insn
), insn
, 0);
21995 insn
= emit_insn (TARGET_32BIT
21996 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
21998 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
21999 todec
, stack_reg
));
22000 /* Since we didn't use gen_frame_mem to generate the MEM, grab
22001 it now and set the alias set/attributes. The above gen_*_update
22002 calls will generate a PARALLEL with the MEM set being the first
22004 par
= PATTERN (insn
);
22005 gcc_assert (GET_CODE (par
) == PARALLEL
);
22006 set
= XVECEXP (par
, 0, 0);
22007 gcc_assert (GET_CODE (set
) == SET
);
22008 mem
= SET_DEST (set
);
22009 gcc_assert (MEM_P (mem
));
22010 MEM_NOTRAP_P (mem
) = 1;
22011 set_mem_alias_set (mem
, get_frame_alias_set ());
22013 RTX_FRAME_RELATED_P (insn
) = 1;
22014 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
22015 gen_rtx_SET (VOIDmode
, stack_reg
,
22016 gen_rtx_PLUS (Pmode
, stack_reg
,
22017 GEN_INT (-size
))));
22020 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
22022 #if PROBE_INTERVAL > 32768
22023 #error Cannot use indexed addressing mode for stack probing
22026 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
22027 inclusive. These are offsets from the current stack pointer. */
22030 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
22032 /* See if we have a constant small number of probes to generate. If so,
22033 that's the easy case. */
22034 if (first
+ size
<= 32768)
22038 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
22039 it exceeds SIZE. If only one probe is needed, this will not
22040 generate any code. Then probe at FIRST + SIZE. */
22041 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
22042 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
22045 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
22049 /* Otherwise, do the same as above, but in a loop. Note that we must be
22050 extra careful with variables wrapping around because we might be at
22051 the very top (or the very bottom) of the address space and we have
22052 to be able to handle this case properly; in particular, we use an
22053 equality test for the loop condition. */
22056 HOST_WIDE_INT rounded_size
;
22057 rtx r12
= gen_rtx_REG (Pmode
, 12);
22058 rtx r0
= gen_rtx_REG (Pmode
, 0);
22060 /* Sanity check for the addressing mode we're going to use. */
22061 gcc_assert (first
<= 32768);
22063 /* Step 1: round SIZE to the previous multiple of the interval. */
22065 rounded_size
= size
& -PROBE_INTERVAL
;
22068 /* Step 2: compute initial and final value of the loop counter. */
22070 /* TEST_ADDR = SP + FIRST. */
22071 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
22072 plus_constant (Pmode
, stack_pointer_rtx
,
22075 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
22076 if (rounded_size
> 32768)
22078 emit_move_insn (r0
, GEN_INT (-rounded_size
));
22079 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
22080 gen_rtx_PLUS (Pmode
, r12
, r0
)));
22083 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
22084 plus_constant (Pmode
, r12
, -rounded_size
)));
22087 /* Step 3: the loop
22089 while (TEST_ADDR != LAST_ADDR)
22091 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
22095 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
22096 until it is equal to ROUNDED_SIZE. */
22099 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
22101 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
22104 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
22105 that SIZE is equal to ROUNDED_SIZE. */
22107 if (size
!= rounded_size
)
22108 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
22112 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
22113 absolute addresses. */
22116 output_probe_stack_range (rtx reg1
, rtx reg2
)
22118 static int labelno
= 0;
22119 char loop_lab
[32], end_lab
[32];
22122 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
22123 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
22125 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
22127 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
22131 output_asm_insn ("cmpd 0,%0,%1", xops
);
22133 output_asm_insn ("cmpw 0,%0,%1", xops
);
22135 fputs ("\tbeq 0,", asm_out_file
);
22136 assemble_name_raw (asm_out_file
, end_lab
);
22137 fputc ('\n', asm_out_file
);
22139 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
22140 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
22141 output_asm_insn ("addi %0,%0,%1", xops
);
22143 /* Probe at TEST_ADDR and branch. */
22144 xops
[1] = gen_rtx_REG (Pmode
, 0);
22145 output_asm_insn ("stw %1,0(%0)", xops
);
22146 fprintf (asm_out_file
, "\tb ");
22147 assemble_name_raw (asm_out_file
, loop_lab
);
22148 fputc ('\n', asm_out_file
);
22150 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
22155 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
22156 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
22157 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
22158 deduce these equivalences by itself so it wasn't necessary to hold
22159 its hand so much. Don't be tempted to always supply d2_f_d_e with
22160 the actual cfa register, ie. r31 when we are using a hard frame
22161 pointer. That fails when saving regs off r1, and sched moves the
22162 r31 setup past the reg saves. */
22165 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
22166 rtx reg2
, rtx rreg
, rtx split_reg
)
22170 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
22172 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
22175 gcc_checking_assert (val
== 0);
22176 real
= PATTERN (insn
);
22177 if (GET_CODE (real
) == PARALLEL
)
22178 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
22179 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
22181 rtx set
= XVECEXP (real
, 0, i
);
22183 RTX_FRAME_RELATED_P (set
) = 1;
22185 RTX_FRAME_RELATED_P (insn
) = 1;
22189 /* copy_rtx will not make unique copies of registers, so we need to
22190 ensure we don't have unwanted sharing here. */
22192 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
22195 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
22197 real
= copy_rtx (PATTERN (insn
));
22199 if (reg2
!= NULL_RTX
)
22200 real
= replace_rtx (real
, reg2
, rreg
);
22202 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
22203 gcc_checking_assert (val
== 0);
22205 real
= replace_rtx (real
, reg
,
22206 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
22207 STACK_POINTER_REGNUM
),
22210 /* We expect that 'real' is either a SET or a PARALLEL containing
22211 SETs (and possibly other stuff). In a PARALLEL, all the SETs
22212 are important so they all have to be marked RTX_FRAME_RELATED_P. */
22214 if (GET_CODE (real
) == SET
)
22218 temp
= simplify_rtx (SET_SRC (set
));
22220 SET_SRC (set
) = temp
;
22221 temp
= simplify_rtx (SET_DEST (set
));
22223 SET_DEST (set
) = temp
;
22224 if (GET_CODE (SET_DEST (set
)) == MEM
)
22226 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
22228 XEXP (SET_DEST (set
), 0) = temp
;
22235 gcc_assert (GET_CODE (real
) == PARALLEL
);
22236 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
22237 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
22239 rtx set
= XVECEXP (real
, 0, i
);
22241 temp
= simplify_rtx (SET_SRC (set
));
22243 SET_SRC (set
) = temp
;
22244 temp
= simplify_rtx (SET_DEST (set
));
22246 SET_DEST (set
) = temp
;
22247 if (GET_CODE (SET_DEST (set
)) == MEM
)
22249 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
22251 XEXP (SET_DEST (set
), 0) = temp
;
22253 RTX_FRAME_RELATED_P (set
) = 1;
22257 /* If a store insn has been split into multiple insns, the
22258 true source register is given by split_reg. */
22259 if (split_reg
!= NULL_RTX
)
22260 real
= gen_rtx_SET (VOIDmode
, SET_DEST (real
), split_reg
);
22262 RTX_FRAME_RELATED_P (insn
) = 1;
22263 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
22268 /* Returns an insn that has a vrsave set operation with the
22269 appropriate CLOBBERs. */
22272 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
22275 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
22276 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
22279 = gen_rtx_SET (VOIDmode
,
22281 gen_rtx_UNSPEC_VOLATILE (SImode
,
22282 gen_rtvec (2, reg
, vrsave
),
22283 UNSPECV_SET_VRSAVE
));
22287 /* We need to clobber the registers in the mask so the scheduler
22288 does not move sets to VRSAVE before sets of AltiVec registers.
22290 However, if the function receives nonlocal gotos, reload will set
22291 all call saved registers live. We will end up with:
22293 (set (reg 999) (mem))
22294 (parallel [ (set (reg vrsave) (unspec blah))
22295 (clobber (reg 999))])
22297 The clobber will cause the store into reg 999 to be dead, and
22298 flow will attempt to delete an epilogue insn. In this case, we
22299 need an unspec use/set of the register. */
22301 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22302 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22304 if (!epiloguep
|| call_used_regs
[i
])
22305 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
22306 gen_rtx_REG (V4SImode
, i
));
22309 rtx reg
= gen_rtx_REG (V4SImode
, i
);
22312 = gen_rtx_SET (VOIDmode
,
22314 gen_rtx_UNSPEC (V4SImode
,
22315 gen_rtvec (1, reg
), 27));
22319 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
22321 for (i
= 0; i
< nclobs
; ++i
)
22322 XVECEXP (insn
, 0, i
) = clobs
[i
];
22328 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
22332 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
22333 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
22334 return gen_rtx_SET (VOIDmode
, store
? mem
: reg
, store
? reg
: mem
);
22338 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
22340 return gen_frame_set (reg
, frame_reg
, offset
, false);
22344 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
22346 return gen_frame_set (reg
, frame_reg
, offset
, true);
22349 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
22350 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
22353 emit_frame_save (rtx frame_reg
, enum machine_mode mode
,
22354 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
22358 /* Some cases that need register indexed addressing. */
22359 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
22360 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
22361 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
22363 && SPE_VECTOR_MODE (mode
)
22364 && !SPE_CONST_OFFSET_OK (offset
))));
22366 reg
= gen_rtx_REG (mode
, regno
);
22367 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
22368 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
22369 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22372 /* Emit an offset memory reference suitable for a frame store, while
22373 converting to a valid addressing mode. */
22376 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
22378 rtx int_rtx
, offset_rtx
;
22380 int_rtx
= GEN_INT (offset
);
22382 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
22383 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
22385 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
22386 emit_move_insn (offset_rtx
, int_rtx
);
22389 offset_rtx
= int_rtx
;
22391 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
22394 #ifndef TARGET_FIX_AND_CONTINUE
22395 #define TARGET_FIX_AND_CONTINUE 0
22398 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
22399 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
22400 #define LAST_SAVRES_REGISTER 31
22401 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
22412 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
22414 /* Temporary holding space for an out-of-line register save/restore
22416 static char savres_routine_name
[30];
22418 /* Return the name for an out-of-line register save/restore routine.
22419 We are saving/restoring GPRs if GPR is true. */
22422 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
22424 const char *prefix
= "";
22425 const char *suffix
= "";
22427 /* Different targets are supposed to define
22428 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
22429 routine name could be defined with:
22431 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
22433 This is a nice idea in practice, but in reality, things are
22434 complicated in several ways:
22436 - ELF targets have save/restore routines for GPRs.
22438 - SPE targets use different prefixes for 32/64-bit registers, and
22439 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
22441 - PPC64 ELF targets have routines for save/restore of GPRs that
22442 differ in what they do with the link register, so having a set
22443 prefix doesn't work. (We only use one of the save routines at
22444 the moment, though.)
22446 - PPC32 elf targets have "exit" versions of the restore routines
22447 that restore the link register and can save some extra space.
22448 These require an extra suffix. (There are also "tail" versions
22449 of the restore routines and "GOT" versions of the save routines,
22450 but we don't generate those at present. Same problems apply,
22453 We deal with all this by synthesizing our own prefix/suffix and
22454 using that for the simple sprintf call shown above. */
22457 /* No floating point saves on the SPE. */
22458 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
22460 if ((sel
& SAVRES_SAVE
))
22461 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
22463 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
22465 if ((sel
& SAVRES_LR
))
22468 else if (DEFAULT_ABI
== ABI_V4
)
22473 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
22474 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
22475 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
22476 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
22477 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22478 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
22482 if ((sel
& SAVRES_LR
))
22485 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22487 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
22488 /* No out-of-line save/restore routines for GPRs on AIX. */
22489 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
22493 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
22494 prefix
= ((sel
& SAVRES_SAVE
)
22495 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
22496 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
22497 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
22499 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
22500 if ((sel
& SAVRES_LR
))
22501 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
22505 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
22506 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
22509 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22510 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
22515 if (DEFAULT_ABI
== ABI_DARWIN
)
22517 /* The Darwin approach is (slightly) different, in order to be
22518 compatible with code generated by the system toolchain. There is a
22519 single symbol for the start of save sequence, and the code here
22520 embeds an offset into that code on the basis of the first register
22522 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
22523 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
22524 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
22525 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
22526 (regno
- 13) * 4, prefix
, regno
);
22527 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
22528 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
22529 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
22530 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22531 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
22532 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
22537 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
22539 return savres_routine_name
;
22542 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
22543 We are saving/restoring GPRs if GPR is true. */
22546 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
22548 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
22549 ? info
->first_gp_reg_save
22550 : (sel
& SAVRES_REG
) == SAVRES_FPR
22551 ? info
->first_fp_reg_save
- 32
22552 : (sel
& SAVRES_REG
) == SAVRES_VR
22553 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
22558 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
22559 versions of the gpr routines. */
22560 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
22561 && info
->spe_64bit_regs_used
)
22562 select
^= SAVRES_FPR
^ SAVRES_GPR
;
22564 /* Don't generate bogus routine names. */
22565 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
22566 && regno
<= LAST_SAVRES_REGISTER
22567 && select
>= 0 && select
<= 12);
22569 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
22575 name
= rs6000_savres_routine_name (info
, regno
, sel
);
22577 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
22578 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
22579 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
22585 /* Emit a sequence of insns, including a stack tie if needed, for
22586 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
22587 reset the stack pointer, but move the base of the frame into
22588 reg UPDT_REGNO for use by out-of-line register restore routines. */
22591 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
22592 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
22593 unsigned updt_regno
)
22597 /* This blockage is needed so that sched doesn't decide to move
22598 the sp change before the register restores. */
22599 if (DEFAULT_ABI
== ABI_V4
22601 && info
->spe_64bit_regs_used
!= 0
22602 && info
->first_gp_reg_save
!= 32))
22603 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
22605 /* If we are restoring registers out-of-line, we will be using the
22606 "exit" variants of the restore routines, which will reset the
22607 stack for us. But we do need to point updt_reg into the
22608 right place for those routines. */
22609 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
22611 if (frame_off
!= 0)
22612 return emit_insn (gen_add3_insn (updt_reg_rtx
,
22613 frame_reg_rtx
, GEN_INT (frame_off
)));
22614 else if (REGNO (frame_reg_rtx
) != updt_regno
)
22615 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
22620 /* Return the register number used as a pointer by out-of-line
22621 save/restore functions. */
22623 static inline unsigned
22624 ptr_regno_for_savres (int sel
)
22626 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22627 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
22628 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
22631 /* Construct a parallel rtx describing the effect of a call to an
22632 out-of-line register save/restore routine, and emit the insn
22633 or jump_insn as appropriate. */
22636 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
22637 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
22638 enum machine_mode reg_mode
, int sel
)
22641 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
22642 int reg_size
= GET_MODE_SIZE (reg_mode
);
22648 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
22649 ? info
->first_gp_reg_save
22650 : (sel
& SAVRES_REG
) == SAVRES_FPR
22651 ? info
->first_fp_reg_save
22652 : (sel
& SAVRES_REG
) == SAVRES_VR
22653 ? info
->first_altivec_reg_save
22655 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
22657 : (sel
& SAVRES_REG
) == SAVRES_FPR
22659 : (sel
& SAVRES_REG
) == SAVRES_VR
22660 ? LAST_ALTIVEC_REGNO
+ 1
22662 n_regs
= end_reg
- start_reg
;
22663 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
22664 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
22667 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22668 RTVEC_ELT (p
, offset
++) = ret_rtx
;
22670 RTVEC_ELT (p
, offset
++)
22671 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
22673 sym
= rs6000_savres_routine_sym (info
, sel
);
22674 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
22676 use_reg
= ptr_regno_for_savres (sel
);
22677 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22679 /* Vector regs are saved/restored using [reg+reg] addressing. */
22680 RTVEC_ELT (p
, offset
++)
22681 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
22682 RTVEC_ELT (p
, offset
++)
22683 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
22686 RTVEC_ELT (p
, offset
++)
22687 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
22689 for (i
= 0; i
< end_reg
- start_reg
; i
++)
22690 RTVEC_ELT (p
, i
+ offset
)
22691 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
22692 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
22693 (sel
& SAVRES_SAVE
) != 0);
22695 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22696 RTVEC_ELT (p
, i
+ offset
)
22697 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
22699 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
22701 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22703 insn
= emit_jump_insn (par
);
22704 JUMP_LABEL (insn
) = ret_rtx
;
22707 insn
= emit_insn (par
);
22711 /* Emit code to store CR fields that need to be saved into REG. */
22714 rs6000_emit_move_from_cr (rtx reg
)
22716 /* Only the ELFv2 ABI allows storing only selected fields. */
22717 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
22719 int i
, cr_reg
[8], count
= 0;
22721 /* Collect CR fields that must be saved. */
22722 for (i
= 0; i
< 8; i
++)
22723 if (save_reg_p (CR0_REGNO
+ i
))
22724 cr_reg
[count
++] = i
;
22726 /* If it's just a single one, use mfcrf. */
22729 rtvec p
= rtvec_alloc (1);
22730 rtvec r
= rtvec_alloc (2);
22731 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
22732 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
22734 = gen_rtx_SET (VOIDmode
, reg
,
22735 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
22737 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22741 /* ??? It might be better to handle count == 2 / 3 cases here
22742 as well, using logical operations to combine the values. */
22745 emit_insn (gen_movesi_from_cr (reg
));
22748 /* Determine whether the gp REG is really used. */
22751 rs6000_reg_live_or_pic_offset_p (int reg
)
22753 /* If the function calls eh_return, claim used all the registers that would
22754 be checked for liveness otherwise. This is required for the PIC offset
22755 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
22756 register allocation purposes in this case. */
22758 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
22759 && (!call_used_regs
[reg
]
22760 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22761 && !TARGET_SINGLE_PIC_BASE
22762 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
22763 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22764 && !TARGET_SINGLE_PIC_BASE
22765 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
22766 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
22769 /* Emit function prologue as insns. */
22772 rs6000_emit_prologue (void)
22774 rs6000_stack_t
*info
= rs6000_stack_info ();
22775 enum machine_mode reg_mode
= Pmode
;
22776 int reg_size
= TARGET_32BIT
? 4 : 8;
22777 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
22778 rtx frame_reg_rtx
= sp_reg_rtx
;
22779 unsigned int cr_save_regno
;
22780 rtx cr_save_rtx
= NULL_RTX
;
22783 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
22784 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
22785 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
22786 /* Offset to top of frame for frame_reg and sp respectively. */
22787 HOST_WIDE_INT frame_off
= 0;
22788 HOST_WIDE_INT sp_off
= 0;
22790 #ifdef ENABLE_CHECKING
22791 /* Track and check usage of r0, r11, r12. */
22792 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
22793 #define START_USE(R) do \
22795 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22796 reg_inuse |= 1 << (R); \
22798 #define END_USE(R) do \
22800 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
22801 reg_inuse &= ~(1 << (R)); \
22803 #define NOT_INUSE(R) do \
22805 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22808 #define START_USE(R) do {} while (0)
22809 #define END_USE(R) do {} while (0)
22810 #define NOT_INUSE(R) do {} while (0)
22813 if (DEFAULT_ABI
== ABI_ELFv2
)
22815 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
22817 /* With -mminimal-toc we may generate an extra use of r2 below. */
22818 if (!TARGET_SINGLE_PIC_BASE
22819 && TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
22820 cfun
->machine
->r2_setup_needed
= true;
22824 if (flag_stack_usage_info
)
22825 current_function_static_stack_size
= info
->total_size
;
22827 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
22829 HOST_WIDE_INT size
= info
->total_size
;
22831 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
22833 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
22834 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
,
22835 size
- STACK_CHECK_PROTECT
);
22838 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
22841 if (TARGET_FIX_AND_CONTINUE
)
22843 /* gdb on darwin arranges to forward a function from the old
22844 address by modifying the first 5 instructions of the function
22845 to branch to the overriding function. This is necessary to
22846 permit function pointers that point to the old function to
22847 actually forward to the new function. */
22848 emit_insn (gen_nop ());
22849 emit_insn (gen_nop ());
22850 emit_insn (gen_nop ());
22851 emit_insn (gen_nop ());
22852 emit_insn (gen_nop ());
22855 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
22857 reg_mode
= V2SImode
;
22861 /* Handle world saves specially here. */
22862 if (WORLD_SAVE_P (info
))
22869 /* save_world expects lr in r0. */
22870 reg0
= gen_rtx_REG (Pmode
, 0);
22871 if (info
->lr_save_p
)
22873 insn
= emit_move_insn (reg0
,
22874 gen_rtx_REG (Pmode
, LR_REGNO
));
22875 RTX_FRAME_RELATED_P (insn
) = 1;
22878 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
22879 assumptions about the offsets of various bits of the stack
22881 gcc_assert (info
->gp_save_offset
== -220
22882 && info
->fp_save_offset
== -144
22883 && info
->lr_save_offset
== 8
22884 && info
->cr_save_offset
== 4
22887 && (!crtl
->calls_eh_return
22888 || info
->ehrd_offset
== -432)
22889 && info
->vrsave_save_offset
== -224
22890 && info
->altivec_save_offset
== -416);
22892 treg
= gen_rtx_REG (SImode
, 11);
22893 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
22895 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
22896 in R11. It also clobbers R12, so beware! */
22898 /* Preserve CR2 for save_world prologues */
22900 sz
+= 32 - info
->first_gp_reg_save
;
22901 sz
+= 64 - info
->first_fp_reg_save
;
22902 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
22903 p
= rtvec_alloc (sz
);
22905 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
22906 gen_rtx_REG (SImode
,
22908 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
22909 gen_rtx_SYMBOL_REF (Pmode
,
22911 /* We do floats first so that the instruction pattern matches
22913 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22915 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22917 info
->first_fp_reg_save
+ i
),
22919 info
->fp_save_offset
+ frame_off
+ 8 * i
);
22920 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
22922 = gen_frame_store (gen_rtx_REG (V4SImode
,
22923 info
->first_altivec_reg_save
+ i
),
22925 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
22926 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22928 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
22930 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
22932 /* CR register traditionally saved as CR2. */
22934 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
22935 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
22936 /* Explain about use of R0. */
22937 if (info
->lr_save_p
)
22939 = gen_frame_store (reg0
,
22940 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
22941 /* Explain what happens to the stack pointer. */
22943 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
22944 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
22947 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22948 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22949 treg
, GEN_INT (-info
->total_size
), NULL_RTX
);
22950 sp_off
= frame_off
= info
->total_size
;
22953 strategy
= info
->savres_strategy
;
22955 /* For V.4, update stack before we do any saving and set back pointer. */
22956 if (! WORLD_SAVE_P (info
)
22958 && (DEFAULT_ABI
== ABI_V4
22959 || crtl
->calls_eh_return
))
22961 bool need_r11
= (TARGET_SPE
22962 ? (!(strategy
& SAVE_INLINE_GPRS
)
22963 && info
->spe_64bit_regs_used
== 0)
22964 : (!(strategy
& SAVE_INLINE_FPRS
)
22965 || !(strategy
& SAVE_INLINE_GPRS
)
22966 || !(strategy
& SAVE_INLINE_VRS
)));
22967 int ptr_regno
= -1;
22968 rtx ptr_reg
= NULL_RTX
;
22971 if (info
->total_size
< 32767)
22972 frame_off
= info
->total_size
;
22975 else if (info
->cr_save_p
22977 || info
->first_fp_reg_save
< 64
22978 || info
->first_gp_reg_save
< 32
22979 || info
->altivec_size
!= 0
22980 || info
->vrsave_mask
!= 0
22981 || crtl
->calls_eh_return
)
22985 /* The prologue won't be saving any regs so there is no need
22986 to set up a frame register to access any frame save area.
22987 We also won't be using frame_off anywhere below, but set
22988 the correct value anyway to protect against future
22989 changes to this function. */
22990 frame_off
= info
->total_size
;
22992 if (ptr_regno
!= -1)
22994 /* Set up the frame offset to that needed by the first
22995 out-of-line save function. */
22996 START_USE (ptr_regno
);
22997 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22998 frame_reg_rtx
= ptr_reg
;
22999 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
23000 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
23001 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
23002 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
23003 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
23004 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
23005 frame_off
= -ptr_off
;
23007 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
23008 sp_off
= info
->total_size
;
23009 if (frame_reg_rtx
!= sp_reg_rtx
)
23010 rs6000_emit_stack_tie (frame_reg_rtx
, false);
23013 /* If we use the link register, get it into r0. */
23014 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
23016 rtx addr
, reg
, mem
;
23018 reg
= gen_rtx_REG (Pmode
, 0);
23020 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
23021 RTX_FRAME_RELATED_P (insn
) = 1;
23023 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
23024 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
23026 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
23027 GEN_INT (info
->lr_save_offset
+ frame_off
));
23028 mem
= gen_rtx_MEM (Pmode
, addr
);
23029 /* This should not be of rs6000_sr_alias_set, because of
23030 __builtin_return_address. */
23032 insn
= emit_move_insn (mem
, reg
);
23033 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23034 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23039 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
23040 r12 will be needed by out-of-line gpr restore. */
23041 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23042 && !(strategy
& (SAVE_INLINE_GPRS
23043 | SAVE_NOINLINE_GPRS_SAVES_LR
))
23045 if (!WORLD_SAVE_P (info
)
23047 && REGNO (frame_reg_rtx
) != cr_save_regno
23048 && !(using_static_chain_p
&& cr_save_regno
== 11))
23050 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
23051 START_USE (cr_save_regno
);
23052 rs6000_emit_move_from_cr (cr_save_rtx
);
23055 /* Do any required saving of fpr's. If only one or two to save, do
23056 it ourselves. Otherwise, call function. */
23057 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
23060 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
23061 if (save_reg_p (info
->first_fp_reg_save
+ i
))
23062 emit_frame_save (frame_reg_rtx
,
23063 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
23064 ? DFmode
: SFmode
),
23065 info
->first_fp_reg_save
+ i
,
23066 info
->fp_save_offset
+ frame_off
+ 8 * i
,
23067 sp_off
- frame_off
);
23069 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
23071 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
23072 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23073 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
23074 rtx ptr_reg
= frame_reg_rtx
;
23076 if (REGNO (frame_reg_rtx
) == ptr_regno
)
23077 gcc_checking_assert (frame_off
== 0);
23080 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23081 NOT_INUSE (ptr_regno
);
23082 emit_insn (gen_add3_insn (ptr_reg
,
23083 frame_reg_rtx
, GEN_INT (frame_off
)));
23085 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
23086 info
->fp_save_offset
,
23087 info
->lr_save_offset
,
23089 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
23090 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23095 /* Save GPRs. This is done as a PARALLEL if we are using
23096 the store-multiple instructions. */
23097 if (!WORLD_SAVE_P (info
)
23099 && info
->spe_64bit_regs_used
!= 0
23100 && info
->first_gp_reg_save
!= 32)
23103 rtx spe_save_area_ptr
;
23104 HOST_WIDE_INT save_off
;
23105 int ool_adjust
= 0;
23107 /* Determine whether we can address all of the registers that need
23108 to be saved with an offset from frame_reg_rtx that fits in
23109 the small const field for SPE memory instructions. */
23110 int spe_regs_addressable
23111 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
23112 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
23113 && (strategy
& SAVE_INLINE_GPRS
));
23115 if (spe_regs_addressable
)
23117 spe_save_area_ptr
= frame_reg_rtx
;
23118 save_off
= frame_off
;
23122 /* Make r11 point to the start of the SPE save area. We need
23123 to be careful here if r11 is holding the static chain. If
23124 it is, then temporarily save it in r0. */
23125 HOST_WIDE_INT offset
;
23127 if (!(strategy
& SAVE_INLINE_GPRS
))
23128 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
23129 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
23130 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
23131 save_off
= frame_off
- offset
;
23133 if (using_static_chain_p
)
23135 rtx r0
= gen_rtx_REG (Pmode
, 0);
23138 gcc_assert (info
->first_gp_reg_save
> 11);
23140 emit_move_insn (r0
, spe_save_area_ptr
);
23142 else if (REGNO (frame_reg_rtx
) != 11)
23145 emit_insn (gen_addsi3 (spe_save_area_ptr
,
23146 frame_reg_rtx
, GEN_INT (offset
)));
23147 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
23148 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
23151 if ((strategy
& SAVE_INLINE_GPRS
))
23153 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23154 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23155 emit_frame_save (spe_save_area_ptr
, reg_mode
,
23156 info
->first_gp_reg_save
+ i
,
23157 (info
->spe_gp_save_offset
+ save_off
23159 sp_off
- save_off
);
23163 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
23164 info
->spe_gp_save_offset
+ save_off
,
23166 SAVRES_SAVE
| SAVRES_GPR
);
23168 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
23169 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23172 /* Move the static chain pointer back. */
23173 if (!spe_regs_addressable
)
23175 if (using_static_chain_p
)
23177 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
23180 else if (REGNO (frame_reg_rtx
) != 11)
23184 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
23186 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
23187 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
23188 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
23189 rtx ptr_reg
= frame_reg_rtx
;
23190 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
23191 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
23195 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23197 /* Need to adjust r11 (r12) if we saved any FPRs. */
23198 if (end_save
+ frame_off
!= 0)
23200 rtx offset
= GEN_INT (end_save
+ frame_off
);
23203 frame_off
= -end_save
;
23205 NOT_INUSE (ptr_regno
);
23206 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23208 else if (!ptr_set_up
)
23210 NOT_INUSE (ptr_regno
);
23211 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23213 ptr_off
= -end_save
;
23214 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
23215 info
->gp_save_offset
+ ptr_off
,
23216 info
->lr_save_offset
+ ptr_off
,
23218 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
23219 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23223 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
23227 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
23228 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23230 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
23232 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
23233 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23234 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23235 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23237 else if (!WORLD_SAVE_P (info
))
23240 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23241 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23242 emit_frame_save (frame_reg_rtx
, reg_mode
,
23243 info
->first_gp_reg_save
+ i
,
23244 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
23245 sp_off
- frame_off
);
23248 if (crtl
->calls_eh_return
)
23255 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
23256 if (regno
== INVALID_REGNUM
)
23260 p
= rtvec_alloc (i
);
23264 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
23265 if (regno
== INVALID_REGNUM
)
23269 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
23271 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
23272 RTVEC_ELT (p
, i
) = insn
;
23273 RTX_FRAME_RELATED_P (insn
) = 1;
23276 insn
= emit_insn (gen_blockage ());
23277 RTX_FRAME_RELATED_P (insn
) = 1;
23278 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
23281 /* In AIX ABI we need to make sure r2 is really saved. */
23282 if (TARGET_AIX
&& crtl
->calls_eh_return
)
23284 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
23285 rtx save_insn
, join_insn
, note
;
23286 long toc_restore_insn
;
23288 tmp_reg
= gen_rtx_REG (Pmode
, 11);
23289 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
23290 if (using_static_chain_p
)
23293 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
23297 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
23298 /* Peek at instruction to which this function returns. If it's
23299 restoring r2, then we know we've already saved r2. We can't
23300 unconditionally save r2 because the value we have will already
23301 be updated if we arrived at this function via a plt call or
23302 toc adjusting stub. */
23303 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
23304 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
23305 + RS6000_TOC_SAVE_SLOT
);
23306 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
23307 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
23308 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
23309 validate_condition_mode (EQ
, CCUNSmode
);
23310 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
23311 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
23312 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
23313 toc_save_done
= gen_label_rtx ();
23314 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
23315 gen_rtx_EQ (VOIDmode
, compare_result
,
23317 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
23319 jump
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, jump
));
23320 JUMP_LABEL (jump
) = toc_save_done
;
23321 LABEL_NUSES (toc_save_done
) += 1;
23323 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
23324 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
23325 sp_off
- frame_off
);
23327 emit_label (toc_save_done
);
23329 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
23330 have a CFG that has different saves along different paths.
23331 Move the note to a dummy blockage insn, which describes that
23332 R2 is unconditionally saved after the label. */
23333 /* ??? An alternate representation might be a special insn pattern
23334 containing both the branch and the store. That might let the
23335 code that minimizes the number of DW_CFA_advance opcodes better
23336 freedom in placing the annotations. */
23337 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
23339 remove_note (save_insn
, note
);
23341 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
23342 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
23343 RTX_FRAME_RELATED_P (save_insn
) = 0;
23345 join_insn
= emit_insn (gen_blockage ());
23346 REG_NOTES (join_insn
) = note
;
23347 RTX_FRAME_RELATED_P (join_insn
) = 1;
23349 if (using_static_chain_p
)
23351 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
23358 /* Save CR if we use any that must be preserved. */
23359 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
23361 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
23362 GEN_INT (info
->cr_save_offset
+ frame_off
));
23363 rtx mem
= gen_frame_mem (SImode
, addr
);
23365 /* If we didn't copy cr before, do so now using r0. */
23366 if (cr_save_rtx
== NULL_RTX
)
23369 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
23370 rs6000_emit_move_from_cr (cr_save_rtx
);
23373 /* Saving CR requires a two-instruction sequence: one instruction
23374 to move the CR to a general-purpose register, and a second
23375 instruction that stores the GPR to memory.
23377 We do not emit any DWARF CFI records for the first of these,
23378 because we cannot properly represent the fact that CR is saved in
23379 a register. One reason is that we cannot express that multiple
23380 CR fields are saved; another reason is that on 64-bit, the size
23381 of the CR register in DWARF (4 bytes) differs from the size of
23382 a general-purpose register.
23384 This means if any intervening instruction were to clobber one of
23385 the call-saved CR fields, we'd have incorrect CFI. To prevent
23386 this from happening, we mark the store to memory as a use of
23387 those CR fields, which prevents any such instruction from being
23388 scheduled in between the two instructions. */
23393 crsave_v
[n_crsave
++] = gen_rtx_SET (VOIDmode
, mem
, cr_save_rtx
);
23394 for (i
= 0; i
< 8; i
++)
23395 if (save_reg_p (CR0_REGNO
+ i
))
23396 crsave_v
[n_crsave
++]
23397 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
23399 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
23400 gen_rtvec_v (n_crsave
, crsave_v
)));
23401 END_USE (REGNO (cr_save_rtx
));
23403 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
23404 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
23405 so we need to construct a frame expression manually. */
23406 RTX_FRAME_RELATED_P (insn
) = 1;
23408 /* Update address to be stack-pointer relative, like
23409 rs6000_frame_related would do. */
23410 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
23411 GEN_INT (info
->cr_save_offset
+ sp_off
));
23412 mem
= gen_frame_mem (SImode
, addr
);
23414 if (DEFAULT_ABI
== ABI_ELFv2
)
23416 /* In the ELFv2 ABI we generate separate CFI records for each
23417 CR field that was actually saved. They all point to the
23418 same 32-bit stack slot. */
23422 for (i
= 0; i
< 8; i
++)
23423 if (save_reg_p (CR0_REGNO
+ i
))
23426 = gen_rtx_SET (VOIDmode
, mem
,
23427 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23429 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
23433 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
23434 gen_rtx_PARALLEL (VOIDmode
,
23435 gen_rtvec_v (n_crframe
, crframe
)));
23439 /* In other ABIs, by convention, we use a single CR regnum to
23440 represent the fact that all call-saved CR fields are saved.
23441 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
23442 rtx set
= gen_rtx_SET (VOIDmode
, mem
,
23443 gen_rtx_REG (SImode
, CR2_REGNO
));
23444 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
23448 /* In the ELFv2 ABI we need to save all call-saved CR fields into
23449 *separate* slots if the routine calls __builtin_eh_return, so
23450 that they can be independently restored by the unwinder. */
23451 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
23453 int i
, cr_off
= info
->ehcr_offset
;
23456 /* ??? We might get better performance by using multiple mfocrf
23458 crsave
= gen_rtx_REG (SImode
, 0);
23459 emit_insn (gen_movesi_from_cr (crsave
));
23461 for (i
= 0; i
< 8; i
++)
23462 if (!call_used_regs
[CR0_REGNO
+ i
])
23464 rtvec p
= rtvec_alloc (2);
23466 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
23468 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
23470 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23472 RTX_FRAME_RELATED_P (insn
) = 1;
23473 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
23474 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
23475 sp_reg_rtx
, cr_off
+ sp_off
));
23477 cr_off
+= reg_size
;
23481 /* Update stack and set back pointer unless this is V.4,
23482 for which it was done previously. */
23483 if (!WORLD_SAVE_P (info
) && info
->push_p
23484 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
23486 rtx ptr_reg
= NULL
;
23489 /* If saving altivec regs we need to be able to address all save
23490 locations using a 16-bit offset. */
23491 if ((strategy
& SAVE_INLINE_VRS
) == 0
23492 || (info
->altivec_size
!= 0
23493 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
23494 + info
->total_size
- frame_off
) > 32767)
23495 || (info
->vrsave_size
!= 0
23496 && (info
->vrsave_save_offset
23497 + info
->total_size
- frame_off
) > 32767))
23499 int sel
= SAVRES_SAVE
| SAVRES_VR
;
23500 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
23502 if (using_static_chain_p
23503 && ptr_regno
== STATIC_CHAIN_REGNUM
)
23505 if (REGNO (frame_reg_rtx
) != ptr_regno
)
23506 START_USE (ptr_regno
);
23507 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23508 frame_reg_rtx
= ptr_reg
;
23509 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
23510 frame_off
= -ptr_off
;
23512 else if (REGNO (frame_reg_rtx
) == 1)
23513 frame_off
= info
->total_size
;
23514 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
23515 sp_off
= info
->total_size
;
23516 if (frame_reg_rtx
!= sp_reg_rtx
)
23517 rs6000_emit_stack_tie (frame_reg_rtx
, false);
23520 /* Set frame pointer, if needed. */
23521 if (frame_pointer_needed
)
23523 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
23525 RTX_FRAME_RELATED_P (insn
) = 1;
23528 /* Save AltiVec registers if needed. Save here because the red zone does
23529 not always include AltiVec registers. */
23530 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
23531 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
23533 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
23535 /* Oddly, the vector save/restore functions point r0 at the end
23536 of the save area, then use r11 or r12 to load offsets for
23537 [reg+reg] addressing. */
23538 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
23539 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
23540 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
23542 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
23544 if (end_save
+ frame_off
!= 0)
23546 rtx offset
= GEN_INT (end_save
+ frame_off
);
23548 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23551 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23553 ptr_off
= -end_save
;
23554 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
23555 info
->altivec_save_offset
+ ptr_off
,
23556 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
23557 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
23558 NULL_RTX
, NULL_RTX
, NULL_RTX
);
23559 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
23561 /* The oddity mentioned above clobbered our frame reg. */
23562 emit_move_insn (frame_reg_rtx
, ptr_reg
);
23563 frame_off
= ptr_off
;
23566 else if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
23567 && info
->altivec_size
!= 0)
23571 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23572 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
23574 rtx areg
, savereg
, mem
, split_reg
;
23577 offset
= (info
->altivec_save_offset
+ frame_off
23578 + 16 * (i
- info
->first_altivec_reg_save
));
23580 savereg
= gen_rtx_REG (V4SImode
, i
);
23583 areg
= gen_rtx_REG (Pmode
, 0);
23584 emit_move_insn (areg
, GEN_INT (offset
));
23586 /* AltiVec addressing mode is [reg+reg]. */
23587 mem
= gen_frame_mem (V4SImode
,
23588 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
23590 insn
= emit_move_insn (mem
, savereg
);
23592 /* When we split a VSX store into two insns, we need to make
23593 sure the DWARF info knows which register we are storing.
23594 Pass it in to be used on the appropriate note. */
23595 if (!BYTES_BIG_ENDIAN
23596 && GET_CODE (PATTERN (insn
)) == SET
23597 && GET_CODE (SET_SRC (PATTERN (insn
))) == VEC_SELECT
)
23598 split_reg
= savereg
;
23600 split_reg
= NULL_RTX
;
23602 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23603 areg
, GEN_INT (offset
), split_reg
);
23607 /* VRSAVE is a bit vector representing which AltiVec registers
23608 are used. The OS uses this to determine which vector
23609 registers to save on a context switch. We need to save
23610 VRSAVE on the stack frame, add whatever AltiVec registers we
23611 used in this function, and do the corresponding magic in the
23614 if (!WORLD_SAVE_P (info
)
23616 && TARGET_ALTIVEC_VRSAVE
23617 && info
->vrsave_mask
!= 0)
23623 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
23624 be using r12 as frame_reg_rtx and r11 as the static chain
23625 pointer for nested functions. */
23627 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23628 && !using_static_chain_p
)
23630 else if (REGNO (frame_reg_rtx
) == 12)
23633 if (using_static_chain_p
)
23637 NOT_INUSE (save_regno
);
23638 reg
= gen_rtx_REG (SImode
, save_regno
);
23639 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
23641 emit_insn (gen_get_vrsave_internal (reg
));
23643 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
23646 offset
= info
->vrsave_save_offset
+ frame_off
;
23647 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
23649 /* Include the registers in the mask. */
23650 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
23652 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
23655 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
23656 if (!TARGET_SINGLE_PIC_BASE
23657 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
23658 || (DEFAULT_ABI
== ABI_V4
23659 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
23660 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
23662 /* If emit_load_toc_table will use the link register, we need to save
23663 it. We use R12 for this purpose because emit_load_toc_table
23664 can use register 0. This allows us to use a plain 'blr' to return
23665 from the procedure more often. */
23666 int save_LR_around_toc_setup
= (TARGET_ELF
23667 && DEFAULT_ABI
== ABI_V4
23669 && ! info
->lr_save_p
23670 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
23671 if (save_LR_around_toc_setup
)
23673 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23674 rtx tmp
= gen_rtx_REG (Pmode
, 12);
23676 insn
= emit_move_insn (tmp
, lr
);
23677 RTX_FRAME_RELATED_P (insn
) = 1;
23679 rs6000_emit_load_toc_table (TRUE
);
23681 insn
= emit_move_insn (lr
, tmp
);
23682 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
23683 RTX_FRAME_RELATED_P (insn
) = 1;
23686 rs6000_emit_load_toc_table (TRUE
);
23690 if (!TARGET_SINGLE_PIC_BASE
23691 && DEFAULT_ABI
== ABI_DARWIN
23692 && flag_pic
&& crtl
->uses_pic_offset_table
)
23694 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23695 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
23697 /* Save and restore LR locally around this call (in R0). */
23698 if (!info
->lr_save_p
)
23699 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
23701 emit_insn (gen_load_macho_picbase (src
));
23703 emit_move_insn (gen_rtx_REG (Pmode
,
23704 RS6000_PIC_OFFSET_TABLE_REGNUM
),
23707 if (!info
->lr_save_p
)
23708 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
23712 /* If we need to, save the TOC register after doing the stack setup.
23713 Do not emit eh frame info for this save. The unwinder wants info,
23714 conceptually attached to instructions in this function, about
23715 register values in the caller of this function. This R2 may have
23716 already been changed from the value in the caller.
23717 We don't attempt to write accurate DWARF EH frame info for R2
23718 because code emitted by gcc for a (non-pointer) function call
23719 doesn't save and restore R2. Instead, R2 is managed out-of-line
23720 by a linker generated plt call stub when the function resides in
23721 a shared library. This behaviour is costly to describe in DWARF,
23722 both in terms of the size of DWARF info and the time taken in the
23723 unwinder to interpret it. R2 changes, apart from the
23724 calls_eh_return case earlier in this function, are handled by
23725 linux-unwind.h frob_update_context. */
23726 if (rs6000_save_toc_in_prologue_p ())
23728 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
23729 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
23733 /* Write function prologue. */
23736 rs6000_output_function_prologue (FILE *file
,
23737 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
23739 rs6000_stack_t
*info
= rs6000_stack_info ();
23741 if (TARGET_DEBUG_STACK
)
23742 debug_stack_info (info
);
23744 /* Write .extern for any function we will call to save and restore
23746 if (info
->first_fp_reg_save
< 64
23751 int regno
= info
->first_fp_reg_save
- 32;
23753 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
23755 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
23756 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23757 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23758 fprintf (file
, "\t.extern %s\n", name
);
23760 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
23762 bool lr
= (info
->savres_strategy
23763 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
23764 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23765 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23766 fprintf (file
, "\t.extern %s\n", name
);
23770 /* ELFv2 ABI r2 setup code and local entry point. This must follow
23771 immediately after the global entry point label. */
23772 if (DEFAULT_ABI
== ABI_ELFv2
&& cfun
->machine
->r2_setup_needed
)
23774 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
23776 fprintf (file
, "0:\taddis 2,12,.TOC.-0b@ha\n");
23777 fprintf (file
, "\taddi 2,2,.TOC.-0b@l\n");
23779 fputs ("\t.localentry\t", file
);
23780 assemble_name (file
, name
);
23781 fputs (",.-", file
);
23782 assemble_name (file
, name
);
23783 fputs ("\n", file
);
23786 /* Output -mprofile-kernel code. This needs to be done here instead of
23787 in output_function_profile since it must go after the ELFv2 ABI
23788 local entry point. */
23789 if (TARGET_PROFILE_KERNEL
&& crtl
->profile
)
23791 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
23792 gcc_assert (!TARGET_32BIT
);
23794 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
23795 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
23797 /* In the ELFv2 ABI we have no compiler stack word. It must be
23798 the resposibility of _mcount to preserve the static chain
23799 register if required. */
23800 if (DEFAULT_ABI
!= ABI_ELFv2
23801 && cfun
->static_chain_decl
!= NULL
)
23803 asm_fprintf (file
, "\tstd %s,24(%s)\n",
23804 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23805 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23806 asm_fprintf (file
, "\tld %s,24(%s)\n",
23807 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23810 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23813 rs6000_pic_labelno
++;
23816 /* Non-zero if vmx regs are restored before the frame pop, zero if
23817 we restore after the pop when possible. */
23818 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
23820 /* Restoring cr is a two step process: loading a reg from the frame
23821 save, then moving the reg to cr. For ABI_V4 we must let the
23822 unwinder know that the stack location is no longer valid at or
23823 before the stack deallocation, but we can't emit a cfa_restore for
23824 cr at the stack deallocation like we do for other registers.
23825 The trouble is that it is possible for the move to cr to be
23826 scheduled after the stack deallocation. So say exactly where cr
23827 is located on each of the two insns. */
23830 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
23832 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
23833 rtx reg
= gen_rtx_REG (SImode
, regno
);
23834 rtx insn
= emit_move_insn (reg
, mem
);
23836 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
23838 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
23839 rtx set
= gen_rtx_SET (VOIDmode
, reg
, cr
);
23841 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
23842 RTX_FRAME_RELATED_P (insn
) = 1;
23847 /* Reload CR from REG. */
23850 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
23855 if (using_mfcr_multiple
)
23857 for (i
= 0; i
< 8; i
++)
23858 if (save_reg_p (CR0_REGNO
+ i
))
23860 gcc_assert (count
);
23863 if (using_mfcr_multiple
&& count
> 1)
23869 p
= rtvec_alloc (count
);
23872 for (i
= 0; i
< 8; i
++)
23873 if (save_reg_p (CR0_REGNO
+ i
))
23875 rtvec r
= rtvec_alloc (2);
23876 RTVEC_ELT (r
, 0) = reg
;
23877 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
23878 RTVEC_ELT (p
, ndx
) =
23879 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
23880 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
23883 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23884 gcc_assert (ndx
== count
);
23886 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
23887 CR field separately. */
23888 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
23890 for (i
= 0; i
< 8; i
++)
23891 if (save_reg_p (CR0_REGNO
+ i
))
23892 add_reg_note (insn
, REG_CFA_RESTORE
,
23893 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23895 RTX_FRAME_RELATED_P (insn
) = 1;
23899 for (i
= 0; i
< 8; i
++)
23900 if (save_reg_p (CR0_REGNO
+ i
))
23902 rtx insn
= emit_insn (gen_movsi_to_cr_one
23903 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
23905 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
23906 CR field separately, attached to the insn that in fact
23907 restores this particular CR field. */
23908 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
23910 add_reg_note (insn
, REG_CFA_RESTORE
,
23911 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23913 RTX_FRAME_RELATED_P (insn
) = 1;
23917 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
23918 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
23919 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
23921 rtx insn
= get_last_insn ();
23922 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
23924 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
23925 RTX_FRAME_RELATED_P (insn
) = 1;
23929 /* Like cr, the move to lr instruction can be scheduled after the
23930 stack deallocation, but unlike cr, its stack frame save is still
23931 valid. So we only need to emit the cfa_restore on the correct
23935 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
23937 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
23938 rtx reg
= gen_rtx_REG (Pmode
, regno
);
23940 emit_move_insn (reg
, mem
);
23944 restore_saved_lr (int regno
, bool exit_func
)
23946 rtx reg
= gen_rtx_REG (Pmode
, regno
);
23947 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23948 rtx insn
= emit_move_insn (lr
, reg
);
23950 if (!exit_func
&& flag_shrink_wrap
)
23952 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
23953 RTX_FRAME_RELATED_P (insn
) = 1;
23958 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
23960 if (DEFAULT_ABI
== ABI_ELFv2
)
23963 for (i
= 0; i
< 8; i
++)
23964 if (save_reg_p (CR0_REGNO
+ i
))
23966 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
23967 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
23971 else if (info
->cr_save_p
)
23972 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23973 gen_rtx_REG (SImode
, CR2_REGNO
),
23976 if (info
->lr_save_p
)
23977 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23978 gen_rtx_REG (Pmode
, LR_REGNO
),
23980 return cfa_restores
;
23983 /* Return true if OFFSET from stack pointer can be clobbered by signals.
23984 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
23985 below stack pointer not cloberred by signals. */
23988 offset_below_red_zone_p (HOST_WIDE_INT offset
)
23990 return offset
< (DEFAULT_ABI
== ABI_V4
23992 : TARGET_32BIT
? -220 : -288);
23995 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
23998 emit_cfa_restores (rtx cfa_restores
)
24000 rtx insn
= get_last_insn ();
24001 rtx
*loc
= ®_NOTES (insn
);
24004 loc
= &XEXP (*loc
, 1);
24005 *loc
= cfa_restores
;
24006 RTX_FRAME_RELATED_P (insn
) = 1;
24009 /* Emit function epilogue as insns. */
24012 rs6000_emit_epilogue (int sibcall
)
24014 rs6000_stack_t
*info
;
24015 int restoring_GPRs_inline
;
24016 int restoring_FPRs_inline
;
24017 int using_load_multiple
;
24018 int using_mtcr_multiple
;
24019 int use_backchain_to_restore_sp
;
24022 HOST_WIDE_INT frame_off
= 0;
24023 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
24024 rtx frame_reg_rtx
= sp_reg_rtx
;
24025 rtx cfa_restores
= NULL_RTX
;
24027 rtx cr_save_reg
= NULL_RTX
;
24028 enum machine_mode reg_mode
= Pmode
;
24029 int reg_size
= TARGET_32BIT
? 4 : 8;
24032 unsigned ptr_regno
;
24034 info
= rs6000_stack_info ();
24036 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
24038 reg_mode
= V2SImode
;
24042 strategy
= info
->savres_strategy
;
24043 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
24044 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
24045 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
24046 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
24047 || rs6000_cpu
== PROCESSOR_PPC603
24048 || rs6000_cpu
== PROCESSOR_PPC750
24050 /* Restore via the backchain when we have a large frame, since this
24051 is more efficient than an addis, addi pair. The second condition
24052 here will not trigger at the moment; We don't actually need a
24053 frame pointer for alloca, but the generic parts of the compiler
24054 give us one anyway. */
24055 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
24056 || (cfun
->calls_alloca
24057 && !frame_pointer_needed
));
24058 restore_lr
= (info
->lr_save_p
24059 && (restoring_FPRs_inline
24060 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
24061 && (restoring_GPRs_inline
24062 || info
->first_fp_reg_save
< 64));
24064 if (WORLD_SAVE_P (info
))
24068 const char *alloc_rname
;
24071 /* eh_rest_world_r10 will return to the location saved in the LR
24072 stack slot (which is not likely to be our caller.)
24073 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
24074 rest_world is similar, except any R10 parameter is ignored.
24075 The exception-handling stuff that was here in 2.95 is no
24076 longer necessary. */
24080 + 32 - info
->first_gp_reg_save
24081 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
24082 + 63 + 1 - info
->first_fp_reg_save
);
24084 strcpy (rname
, ((crtl
->calls_eh_return
) ?
24085 "*eh_rest_world_r10" : "*rest_world"));
24086 alloc_rname
= ggc_strdup (rname
);
24089 RTVEC_ELT (p
, j
++) = ret_rtx
;
24090 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
24091 gen_rtx_REG (Pmode
,
24094 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
24095 /* The instruction pattern requires a clobber here;
24096 it is shared with the restVEC helper. */
24098 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
24101 /* CR register traditionally saved as CR2. */
24102 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
24104 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
24105 if (flag_shrink_wrap
)
24107 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
24108 gen_rtx_REG (Pmode
, LR_REGNO
),
24110 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24114 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24116 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
24118 = gen_frame_load (reg
,
24119 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
24120 if (flag_shrink_wrap
)
24121 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24123 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
24125 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
24127 = gen_frame_load (reg
,
24128 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
24129 if (flag_shrink_wrap
)
24130 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24132 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
24134 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
24135 ? DFmode
: SFmode
),
24136 info
->first_fp_reg_save
+ i
);
24138 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
24139 if (flag_shrink_wrap
)
24140 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24143 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
24145 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
24147 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
24149 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
24151 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
24152 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24154 if (flag_shrink_wrap
)
24156 REG_NOTES (insn
) = cfa_restores
;
24157 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24158 RTX_FRAME_RELATED_P (insn
) = 1;
24163 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
24165 frame_off
= info
->total_size
;
24167 /* Restore AltiVec registers if we must do so before adjusting the
24169 if (TARGET_ALTIVEC_ABI
24170 && info
->altivec_size
!= 0
24171 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24172 || (DEFAULT_ABI
!= ABI_V4
24173 && offset_below_red_zone_p (info
->altivec_save_offset
))))
24176 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
24178 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
24179 if (use_backchain_to_restore_sp
)
24181 int frame_regno
= 11;
24183 if ((strategy
& REST_INLINE_VRS
) == 0)
24185 /* Of r11 and r12, select the one not clobbered by an
24186 out-of-line restore function for the frame register. */
24187 frame_regno
= 11 + 12 - scratch_regno
;
24189 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
24190 emit_move_insn (frame_reg_rtx
,
24191 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24194 else if (frame_pointer_needed
)
24195 frame_reg_rtx
= hard_frame_pointer_rtx
;
24197 if ((strategy
& REST_INLINE_VRS
) == 0)
24199 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
24201 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
24202 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
24204 if (end_save
+ frame_off
!= 0)
24206 rtx offset
= GEN_INT (end_save
+ frame_off
);
24208 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
24211 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24213 ptr_off
= -end_save
;
24214 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
24215 info
->altivec_save_offset
+ ptr_off
,
24216 0, V4SImode
, SAVRES_VR
);
24220 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24221 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
24223 rtx addr
, areg
, mem
, reg
;
24225 areg
= gen_rtx_REG (Pmode
, 0);
24227 (areg
, GEN_INT (info
->altivec_save_offset
24229 + 16 * (i
- info
->first_altivec_reg_save
)));
24231 /* AltiVec addressing mode is [reg+reg]. */
24232 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
24233 mem
= gen_frame_mem (V4SImode
, addr
);
24235 reg
= gen_rtx_REG (V4SImode
, i
);
24236 emit_move_insn (reg
, mem
);
24240 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24241 if (((strategy
& REST_INLINE_VRS
) == 0
24242 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
24243 && (flag_shrink_wrap
24244 || (offset_below_red_zone_p
24245 (info
->altivec_save_offset
24246 + 16 * (i
- info
->first_altivec_reg_save
)))))
24248 rtx reg
= gen_rtx_REG (V4SImode
, i
);
24249 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24253 /* Restore VRSAVE if we must do so before adjusting the stack. */
24255 && TARGET_ALTIVEC_VRSAVE
24256 && info
->vrsave_mask
!= 0
24257 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24258 || (DEFAULT_ABI
!= ABI_V4
24259 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
24263 if (frame_reg_rtx
== sp_reg_rtx
)
24265 if (use_backchain_to_restore_sp
)
24267 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24268 emit_move_insn (frame_reg_rtx
,
24269 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24272 else if (frame_pointer_needed
)
24273 frame_reg_rtx
= hard_frame_pointer_rtx
;
24276 reg
= gen_rtx_REG (SImode
, 12);
24277 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24278 info
->vrsave_save_offset
+ frame_off
));
24280 emit_insn (generate_set_vrsave (reg
, info
, 1));
24284 /* If we have a large stack frame, restore the old stack pointer
24285 using the backchain. */
24286 if (use_backchain_to_restore_sp
)
24288 if (frame_reg_rtx
== sp_reg_rtx
)
24290 /* Under V.4, don't reset the stack pointer until after we're done
24291 loading the saved registers. */
24292 if (DEFAULT_ABI
== ABI_V4
)
24293 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24295 insn
= emit_move_insn (frame_reg_rtx
,
24296 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24299 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24300 && DEFAULT_ABI
== ABI_V4
)
24301 /* frame_reg_rtx has been set up by the altivec restore. */
24305 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
24306 frame_reg_rtx
= sp_reg_rtx
;
24309 /* If we have a frame pointer, we can restore the old stack pointer
24311 else if (frame_pointer_needed
)
24313 frame_reg_rtx
= sp_reg_rtx
;
24314 if (DEFAULT_ABI
== ABI_V4
)
24315 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24316 /* Prevent reordering memory accesses against stack pointer restore. */
24317 else if (cfun
->calls_alloca
24318 || offset_below_red_zone_p (-info
->total_size
))
24319 rs6000_emit_stack_tie (frame_reg_rtx
, true);
24321 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
24322 GEN_INT (info
->total_size
)));
24325 else if (info
->push_p
24326 && DEFAULT_ABI
!= ABI_V4
24327 && !crtl
->calls_eh_return
)
24329 /* Prevent reordering memory accesses against stack pointer restore. */
24330 if (cfun
->calls_alloca
24331 || offset_below_red_zone_p (-info
->total_size
))
24332 rs6000_emit_stack_tie (frame_reg_rtx
, false);
24333 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
24334 GEN_INT (info
->total_size
)));
24337 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
24341 REG_NOTES (insn
) = cfa_restores
;
24342 cfa_restores
= NULL_RTX
;
24344 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24345 RTX_FRAME_RELATED_P (insn
) = 1;
24348 /* Restore AltiVec registers if we have not done so already. */
24349 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24350 && TARGET_ALTIVEC_ABI
24351 && info
->altivec_size
!= 0
24352 && (DEFAULT_ABI
== ABI_V4
24353 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
24357 if ((strategy
& REST_INLINE_VRS
) == 0)
24359 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
24361 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
24362 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
24363 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
24365 if (end_save
+ frame_off
!= 0)
24367 rtx offset
= GEN_INT (end_save
+ frame_off
);
24369 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
24372 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24374 ptr_off
= -end_save
;
24375 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
24376 info
->altivec_save_offset
+ ptr_off
,
24377 0, V4SImode
, SAVRES_VR
);
24378 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
24380 /* Frame reg was clobbered by out-of-line save. Restore it
24381 from ptr_reg, and if we are calling out-of-line gpr or
24382 fpr restore set up the correct pointer and offset. */
24383 unsigned newptr_regno
= 1;
24384 if (!restoring_GPRs_inline
)
24386 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
24387 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
24388 newptr_regno
= ptr_regno_for_savres (sel
);
24389 end_save
= info
->gp_save_offset
+ info
->gp_size
;
24391 else if (!restoring_FPRs_inline
)
24393 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
24394 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24395 newptr_regno
= ptr_regno_for_savres (sel
);
24396 end_save
= info
->gp_save_offset
+ info
->gp_size
;
24399 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
24400 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
24402 if (end_save
+ ptr_off
!= 0)
24404 rtx offset
= GEN_INT (end_save
+ ptr_off
);
24406 frame_off
= -end_save
;
24407 emit_insn (gen_add3_insn (frame_reg_rtx
, ptr_reg
, offset
));
24411 frame_off
= ptr_off
;
24412 emit_move_insn (frame_reg_rtx
, ptr_reg
);
24418 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24419 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
24421 rtx addr
, areg
, mem
, reg
;
24423 areg
= gen_rtx_REG (Pmode
, 0);
24425 (areg
, GEN_INT (info
->altivec_save_offset
24427 + 16 * (i
- info
->first_altivec_reg_save
)));
24429 /* AltiVec addressing mode is [reg+reg]. */
24430 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
24431 mem
= gen_frame_mem (V4SImode
, addr
);
24433 reg
= gen_rtx_REG (V4SImode
, i
);
24434 emit_move_insn (reg
, mem
);
24438 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24439 if (((strategy
& REST_INLINE_VRS
) == 0
24440 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
24441 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
24443 rtx reg
= gen_rtx_REG (V4SImode
, i
);
24444 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24448 /* Restore VRSAVE if we have not done so already. */
24449 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24451 && TARGET_ALTIVEC_VRSAVE
24452 && info
->vrsave_mask
!= 0
24453 && (DEFAULT_ABI
== ABI_V4
24454 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
24458 reg
= gen_rtx_REG (SImode
, 12);
24459 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24460 info
->vrsave_save_offset
+ frame_off
));
24462 emit_insn (generate_set_vrsave (reg
, info
, 1));
24465 /* If we exit by an out-of-line restore function on ABI_V4 then that
24466 function will deallocate the stack, so we don't need to worry
24467 about the unwinder restoring cr from an invalid stack frame
24469 exit_func
= (!restoring_FPRs_inline
24470 || (!restoring_GPRs_inline
24471 && info
->first_fp_reg_save
== 64));
24473 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
24474 *separate* slots if the routine calls __builtin_eh_return, so
24475 that they can be independently restored by the unwinder. */
24476 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
24478 int i
, cr_off
= info
->ehcr_offset
;
24480 for (i
= 0; i
< 8; i
++)
24481 if (!call_used_regs
[CR0_REGNO
+ i
])
24483 rtx reg
= gen_rtx_REG (SImode
, 0);
24484 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24485 cr_off
+ frame_off
));
24487 insn
= emit_insn (gen_movsi_to_cr_one
24488 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
24490 if (!exit_func
&& flag_shrink_wrap
)
24492 add_reg_note (insn
, REG_CFA_RESTORE
,
24493 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
24495 RTX_FRAME_RELATED_P (insn
) = 1;
24498 cr_off
+= reg_size
;
24502 /* Get the old lr if we saved it. If we are restoring registers
24503 out-of-line, then the out-of-line routines can do this for us. */
24504 if (restore_lr
&& restoring_GPRs_inline
)
24505 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
24507 /* Get the old cr if we saved it. */
24508 if (info
->cr_save_p
)
24510 unsigned cr_save_regno
= 12;
24512 if (!restoring_GPRs_inline
)
24514 /* Ensure we don't use the register used by the out-of-line
24515 gpr register restore below. */
24516 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
24517 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
24518 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
24520 if (gpr_ptr_regno
== 12)
24521 cr_save_regno
= 11;
24522 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
24524 else if (REGNO (frame_reg_rtx
) == 12)
24525 cr_save_regno
= 11;
24527 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
24528 info
->cr_save_offset
+ frame_off
,
24532 /* Set LR here to try to overlap restores below. */
24533 if (restore_lr
&& restoring_GPRs_inline
)
24534 restore_saved_lr (0, exit_func
);
24536 /* Load exception handler data registers, if needed. */
24537 if (crtl
->calls_eh_return
)
24539 unsigned int i
, regno
;
24543 rtx reg
= gen_rtx_REG (reg_mode
, 2);
24544 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24545 frame_off
+ RS6000_TOC_SAVE_SLOT
));
24552 regno
= EH_RETURN_DATA_REGNO (i
);
24553 if (regno
== INVALID_REGNUM
)
24556 /* Note: possible use of r0 here to address SPE regs. */
24557 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
24558 info
->ehrd_offset
+ frame_off
24559 + reg_size
* (int) i
);
24561 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
24565 /* Restore GPRs. This is done as a PARALLEL if we are using
24566 the load-multiple instructions. */
24568 && info
->spe_64bit_regs_used
24569 && info
->first_gp_reg_save
!= 32)
24571 /* Determine whether we can address all of the registers that need
24572 to be saved with an offset from frame_reg_rtx that fits in
24573 the small const field for SPE memory instructions. */
24574 int spe_regs_addressable
24575 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
24576 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
24577 && restoring_GPRs_inline
);
24579 if (!spe_regs_addressable
)
24581 int ool_adjust
= 0;
24582 rtx old_frame_reg_rtx
= frame_reg_rtx
;
24583 /* Make r11 point to the start of the SPE save area. We worried about
24584 not clobbering it when we were saving registers in the prologue.
24585 There's no need to worry here because the static chain is passed
24586 anew to every function. */
24588 if (!restoring_GPRs_inline
)
24589 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
24590 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24591 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
24592 GEN_INT (info
->spe_gp_save_offset
24595 /* Keep the invariant that frame_reg_rtx + frame_off points
24596 at the top of the stack frame. */
24597 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
24600 if (restoring_GPRs_inline
)
24602 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
24604 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24605 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
24607 rtx offset
, addr
, mem
, reg
;
24609 /* We're doing all this to ensure that the immediate offset
24610 fits into the immediate field of 'evldd'. */
24611 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
24613 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
24614 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
24615 mem
= gen_rtx_MEM (V2SImode
, addr
);
24616 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
24618 emit_move_insn (reg
, mem
);
24622 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
24623 info
->spe_gp_save_offset
+ frame_off
,
24624 info
->lr_save_offset
+ frame_off
,
24626 SAVRES_GPR
| SAVRES_LR
);
24628 else if (!restoring_GPRs_inline
)
24630 /* We are jumping to an out-of-line function. */
24632 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
24633 bool can_use_exit
= end_save
== 0;
24634 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
24637 /* Emit stack reset code if we need it. */
24638 ptr_regno
= ptr_regno_for_savres (sel
);
24639 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
24641 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
24642 else if (end_save
+ frame_off
!= 0)
24643 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
24644 GEN_INT (end_save
+ frame_off
)));
24645 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
24646 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24647 if (REGNO (frame_reg_rtx
) == ptr_regno
)
24648 frame_off
= -end_save
;
24650 if (can_use_exit
&& info
->cr_save_p
)
24651 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
24653 ptr_off
= -end_save
;
24654 rs6000_emit_savres_rtx (info
, ptr_reg
,
24655 info
->gp_save_offset
+ ptr_off
,
24656 info
->lr_save_offset
+ ptr_off
,
24659 else if (using_load_multiple
)
24662 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
24663 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24665 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
24667 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
24668 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24672 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24673 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
24674 emit_insn (gen_frame_load
24675 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
24677 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
24680 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
24682 /* If the frame pointer was used then we can't delay emitting
24683 a REG_CFA_DEF_CFA note. This must happen on the insn that
24684 restores the frame pointer, r31. We may have already emitted
24685 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
24686 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
24687 be harmless if emitted. */
24688 if (frame_pointer_needed
)
24690 insn
= get_last_insn ();
24691 add_reg_note (insn
, REG_CFA_DEF_CFA
,
24692 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
24693 RTX_FRAME_RELATED_P (insn
) = 1;
24696 /* Set up cfa_restores. We always need these when
24697 shrink-wrapping. If not shrink-wrapping then we only need
24698 the cfa_restore when the stack location is no longer valid.
24699 The cfa_restores must be emitted on or before the insn that
24700 invalidates the stack, and of course must not be emitted
24701 before the insn that actually does the restore. The latter
24702 is why it is a bad idea to emit the cfa_restores as a group
24703 on the last instruction here that actually does a restore:
24704 That insn may be reordered with respect to others doing
24706 if (flag_shrink_wrap
24707 && !restoring_GPRs_inline
24708 && info
->first_fp_reg_save
== 64)
24709 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
24711 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
24712 if (!restoring_GPRs_inline
24713 || using_load_multiple
24714 || rs6000_reg_live_or_pic_offset_p (i
))
24716 rtx reg
= gen_rtx_REG (reg_mode
, i
);
24718 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24722 if (!restoring_GPRs_inline
24723 && info
->first_fp_reg_save
== 64)
24725 /* We are jumping to an out-of-line function. */
24727 emit_cfa_restores (cfa_restores
);
24731 if (restore_lr
&& !restoring_GPRs_inline
)
24733 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
24734 restore_saved_lr (0, exit_func
);
24737 /* Restore fpr's if we need to do it without calling a function. */
24738 if (restoring_FPRs_inline
)
24739 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24740 if (save_reg_p (info
->first_fp_reg_save
+ i
))
24742 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
24743 ? DFmode
: SFmode
),
24744 info
->first_fp_reg_save
+ i
);
24745 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24746 info
->fp_save_offset
+ frame_off
+ 8 * i
));
24747 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
24748 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24751 /* If we saved cr, restore it here. Just those that were used. */
24752 if (info
->cr_save_p
)
24753 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
24755 /* If this is V.4, unwind the stack pointer after all of the loads
24756 have been done, or set up r11 if we are restoring fp out of line. */
24758 if (!restoring_FPRs_inline
)
24760 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24761 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24762 ptr_regno
= ptr_regno_for_savres (sel
);
24765 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
24766 if (REGNO (frame_reg_rtx
) == ptr_regno
)
24769 if (insn
&& restoring_FPRs_inline
)
24773 REG_NOTES (insn
) = cfa_restores
;
24774 cfa_restores
= NULL_RTX
;
24776 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24777 RTX_FRAME_RELATED_P (insn
) = 1;
24780 if (crtl
->calls_eh_return
)
24782 rtx sa
= EH_RETURN_STACKADJ_RTX
;
24783 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
24789 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24790 if (! restoring_FPRs_inline
)
24792 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
24793 RTVEC_ELT (p
, 0) = ret_rtx
;
24799 /* We can't hang the cfa_restores off a simple return,
24800 since the shrink-wrap code sometimes uses an existing
24801 return. This means there might be a path from
24802 pre-prologue code to this return, and dwarf2cfi code
24803 wants the eh_frame unwinder state to be the same on
24804 all paths to any point. So we need to emit the
24805 cfa_restores before the return. For -m64 we really
24806 don't need epilogue cfa_restores at all, except for
24807 this irritating dwarf2cfi with shrink-wrap
24808 requirement; The stack red-zone means eh_frame info
24809 from the prologue telling the unwinder to restore
24810 from the stack is perfectly good right to the end of
24812 emit_insn (gen_blockage ());
24813 emit_cfa_restores (cfa_restores
);
24814 cfa_restores
= NULL_RTX
;
24816 p
= rtvec_alloc (2);
24817 RTVEC_ELT (p
, 0) = simple_return_rtx
;
24820 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
24821 ? gen_rtx_USE (VOIDmode
,
24822 gen_rtx_REG (Pmode
, LR_REGNO
))
24823 : gen_rtx_CLOBBER (VOIDmode
,
24824 gen_rtx_REG (Pmode
, LR_REGNO
)));
24826 /* If we have to restore more than two FP registers, branch to the
24827 restore function. It will return to our caller. */
24828 if (! restoring_FPRs_inline
)
24834 if (flag_shrink_wrap
)
24835 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
24837 sym
= rs6000_savres_routine_sym (info
,
24838 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
24839 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
24840 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
24841 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
24843 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24845 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
24847 RTVEC_ELT (p
, i
+ 4)
24848 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
24849 if (flag_shrink_wrap
)
24850 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
24855 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24861 /* Ensure the cfa_restores are hung off an insn that won't
24862 be reordered above other restores. */
24863 emit_insn (gen_blockage ());
24865 emit_cfa_restores (cfa_restores
);
24869 /* Write function epilogue. */
24872 rs6000_output_function_epilogue (FILE *file
,
24873 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
24876 macho_branch_islands ();
24877 /* Mach-O doesn't support labels at the end of objects, so if
24878 it looks like we might want one, insert a NOP. */
24880 rtx insn
= get_last_insn ();
24881 rtx deleted_debug_label
= NULL_RTX
;
24884 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
24886 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
24887 notes only, instead set their CODE_LABEL_NUMBER to -1,
24888 otherwise there would be code generation differences
24889 in between -g and -g0. */
24890 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
24891 deleted_debug_label
= insn
;
24892 insn
= PREV_INSN (insn
);
24897 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
24898 fputs ("\tnop\n", file
);
24899 else if (deleted_debug_label
)
24900 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
24901 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
24902 CODE_LABEL_NUMBER (insn
) = -1;
24906 /* Output a traceback table here. See /usr/include/sys/debug.h for info
24909 We don't output a traceback table if -finhibit-size-directive was
24910 used. The documentation for -finhibit-size-directive reads
24911 ``don't output a @code{.size} assembler directive, or anything
24912 else that would cause trouble if the function is split in the
24913 middle, and the two halves are placed at locations far apart in
24914 memory.'' The traceback table has this property, since it
24915 includes the offset from the start of the function to the
24916 traceback table itself.
24918 System V.4 Powerpc's (and the embedded ABI derived from it) use a
24919 different traceback table. */
24920 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24921 && ! flag_inhibit_size_directive
24922 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
24924 const char *fname
= NULL
;
24925 const char *language_string
= lang_hooks
.name
;
24926 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
24928 int optional_tbtab
;
24929 rs6000_stack_t
*info
= rs6000_stack_info ();
24931 if (rs6000_traceback
== traceback_full
)
24932 optional_tbtab
= 1;
24933 else if (rs6000_traceback
== traceback_part
)
24934 optional_tbtab
= 0;
24936 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
24938 if (optional_tbtab
)
24940 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
24941 while (*fname
== '.') /* V.4 encodes . in the name */
24944 /* Need label immediately before tbtab, so we can compute
24945 its offset from the function start. */
24946 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
24947 ASM_OUTPUT_LABEL (file
, fname
);
24950 /* The .tbtab pseudo-op can only be used for the first eight
24951 expressions, since it can't handle the possibly variable
24952 length fields that follow. However, if you omit the optional
24953 fields, the assembler outputs zeros for all optional fields
24954 anyways, giving each variable length field is minimum length
24955 (as defined in sys/debug.h). Thus we can not use the .tbtab
24956 pseudo-op at all. */
24958 /* An all-zero word flags the start of the tbtab, for debuggers
24959 that have to find it by searching forward from the entry
24960 point or from the current pc. */
24961 fputs ("\t.long 0\n", file
);
24963 /* Tbtab format type. Use format type 0. */
24964 fputs ("\t.byte 0,", file
);
24966 /* Language type. Unfortunately, there does not seem to be any
24967 official way to discover the language being compiled, so we
24968 use language_string.
24969 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
24970 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
24971 a number, so for now use 9. LTO and Go aren't assigned numbers
24972 either, so for now use 0. */
24973 if (! strcmp (language_string
, "GNU C")
24974 || ! strcmp (language_string
, "GNU GIMPLE")
24975 || ! strcmp (language_string
, "GNU Go"))
24977 else if (! strcmp (language_string
, "GNU F77")
24978 || ! strcmp (language_string
, "GNU Fortran"))
24980 else if (! strcmp (language_string
, "GNU Pascal"))
24982 else if (! strcmp (language_string
, "GNU Ada"))
24984 else if (! strcmp (language_string
, "GNU C++")
24985 || ! strcmp (language_string
, "GNU Objective-C++"))
24987 else if (! strcmp (language_string
, "GNU Java"))
24989 else if (! strcmp (language_string
, "GNU Objective-C"))
24992 gcc_unreachable ();
24993 fprintf (file
, "%d,", i
);
24995 /* 8 single bit fields: global linkage (not set for C extern linkage,
24996 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
24997 from start of procedure stored in tbtab, internal function, function
24998 has controlled storage, function has no toc, function uses fp,
24999 function logs/aborts fp operations. */
25000 /* Assume that fp operations are used if any fp reg must be saved. */
25001 fprintf (file
, "%d,",
25002 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
25004 /* 6 bitfields: function is interrupt handler, name present in
25005 proc table, function calls alloca, on condition directives
25006 (controls stack walks, 3 bits), saves condition reg, saves
25008 /* The `function calls alloca' bit seems to be set whenever reg 31 is
25009 set up as a frame pointer, even when there is no alloca call. */
25010 fprintf (file
, "%d,",
25011 ((optional_tbtab
<< 6)
25012 | ((optional_tbtab
& frame_pointer_needed
) << 5)
25013 | (info
->cr_save_p
<< 1)
25014 | (info
->lr_save_p
)));
25016 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
25018 fprintf (file
, "%d,",
25019 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
25021 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
25022 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
25024 if (optional_tbtab
)
25026 /* Compute the parameter info from the function decl argument
25029 int next_parm_info_bit
= 31;
25031 for (decl
= DECL_ARGUMENTS (current_function_decl
);
25032 decl
; decl
= DECL_CHAIN (decl
))
25034 rtx parameter
= DECL_INCOMING_RTL (decl
);
25035 enum machine_mode mode
= GET_MODE (parameter
);
25037 if (GET_CODE (parameter
) == REG
)
25039 if (SCALAR_FLOAT_MODE_P (mode
))
25060 gcc_unreachable ();
25063 /* If only one bit will fit, don't or in this entry. */
25064 if (next_parm_info_bit
> 0)
25065 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
25066 next_parm_info_bit
-= 2;
25070 fixed_parms
+= ((GET_MODE_SIZE (mode
)
25071 + (UNITS_PER_WORD
- 1))
25073 next_parm_info_bit
-= 1;
25079 /* Number of fixed point parameters. */
25080 /* This is actually the number of words of fixed point parameters; thus
25081 an 8 byte struct counts as 2; and thus the maximum value is 8. */
25082 fprintf (file
, "%d,", fixed_parms
);
25084 /* 2 bitfields: number of floating point parameters (7 bits), parameters
25086 /* This is actually the number of fp registers that hold parameters;
25087 and thus the maximum value is 13. */
25088 /* Set parameters on stack bit if parameters are not in their original
25089 registers, regardless of whether they are on the stack? Xlc
25090 seems to set the bit when not optimizing. */
25091 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
25093 if (! optional_tbtab
)
25096 /* Optional fields follow. Some are variable length. */
25098 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
25099 11 double float. */
25100 /* There is an entry for each parameter in a register, in the order that
25101 they occur in the parameter list. Any intervening arguments on the
25102 stack are ignored. If the list overflows a long (max possible length
25103 34 bits) then completely leave off all elements that don't fit. */
25104 /* Only emit this long if there was at least one parameter. */
25105 if (fixed_parms
|| float_parms
)
25106 fprintf (file
, "\t.long %d\n", parm_info
);
25108 /* Offset from start of code to tb table. */
25109 fputs ("\t.long ", file
);
25110 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
25111 RS6000_OUTPUT_BASENAME (file
, fname
);
25113 rs6000_output_function_entry (file
, fname
);
25116 /* Interrupt handler mask. */
25117 /* Omit this long, since we never set the interrupt handler bit
25120 /* Number of CTL (controlled storage) anchors. */
25121 /* Omit this long, since the has_ctl bit is never set above. */
25123 /* Displacement into stack of each CTL anchor. */
25124 /* Omit this list of longs, because there are no CTL anchors. */
25126 /* Length of function name. */
25129 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
25131 /* Function name. */
25132 assemble_string (fname
, strlen (fname
));
25134 /* Register for alloca automatic storage; this is always reg 31.
25135 Only emit this if the alloca bit was set above. */
25136 if (frame_pointer_needed
)
25137 fputs ("\t.byte 31\n", file
);
25139 fputs ("\t.align 2\n", file
);
25143 /* A C compound statement that outputs the assembler code for a thunk
25144 function, used to implement C++ virtual function calls with
25145 multiple inheritance. The thunk acts as a wrapper around a virtual
25146 function, adjusting the implicit object parameter before handing
25147 control off to the real function.
25149 First, emit code to add the integer DELTA to the location that
25150 contains the incoming first argument. Assume that this argument
25151 contains a pointer, and is the one used to pass the `this' pointer
25152 in C++. This is the incoming argument *before* the function
25153 prologue, e.g. `%o0' on a sparc. The addition must preserve the
25154 values of all other incoming arguments.
25156 After the addition, emit code to jump to FUNCTION, which is a
25157 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
25158 not touch the return address. Hence returning from FUNCTION will
25159 return to whoever called the current `thunk'.
25161 The effect must be as if FUNCTION had been called directly with the
25162 adjusted first argument. This macro is responsible for emitting
25163 all of the code for a thunk function; output_function_prologue()
25164 and output_function_epilogue() are not invoked.
25166 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
25167 been extracted from it.) It might possibly be useful on some
25168 targets, but probably not.
25170 If you do not define this macro, the target-independent code in the
25171 C++ frontend will generate a less efficient heavyweight thunk that
25172 calls FUNCTION instead of jumping to it. The generic approach does
25173 not support varargs. */
25176 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
25177 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
25180 rtx this_rtx
, insn
, funexp
;
25182 reload_completed
= 1;
25183 epilogue_completed
= 1;
25185 /* Mark the end of the (empty) prologue. */
25186 emit_note (NOTE_INSN_PROLOGUE_END
);
25188 /* Find the "this" pointer. If the function returns a structure,
25189 the structure return pointer is in r3. */
25190 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
25191 this_rtx
= gen_rtx_REG (Pmode
, 4);
25193 this_rtx
= gen_rtx_REG (Pmode
, 3);
25195 /* Apply the constant offset, if required. */
25197 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
25199 /* Apply the offset from the vtable, if required. */
25202 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
25203 rtx tmp
= gen_rtx_REG (Pmode
, 12);
25205 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
25206 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
25208 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
25209 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
25213 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
25215 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
25217 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
25220 /* Generate a tail call to the target function. */
25221 if (!TREE_USED (function
))
25223 assemble_external (function
);
25224 TREE_USED (function
) = 1;
25226 funexp
= XEXP (DECL_RTL (function
), 0);
25227 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
25230 if (MACHOPIC_INDIRECT
)
25231 funexp
= machopic_indirect_call_target (funexp
);
25234 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
25235 generate sibcall RTL explicitly. */
25236 insn
= emit_call_insn (
25237 gen_rtx_PARALLEL (VOIDmode
,
25239 gen_rtx_CALL (VOIDmode
,
25240 funexp
, const0_rtx
),
25241 gen_rtx_USE (VOIDmode
, const0_rtx
),
25242 gen_rtx_USE (VOIDmode
,
25243 gen_rtx_REG (SImode
,
25245 simple_return_rtx
)));
25246 SIBLING_CALL_P (insn
) = 1;
25249 /* Ensure we have a global entry point for the thunk. ??? We could
25250 avoid that if the target routine doesn't need a global entry point,
25251 but we do not know whether this is the case at this point. */
25252 if (DEFAULT_ABI
== ABI_ELFv2
)
25253 cfun
->machine
->r2_setup_needed
= true;
25255 /* Run just enough of rest_of_compilation to get the insns emitted.
25256 There's not really enough bulk here to make other passes such as
25257 instruction scheduling worth while. Note that use_thunk calls
25258 assemble_start_function and assemble_end_function. */
25259 insn
= get_insns ();
25260 shorten_branches (insn
);
25261 final_start_function (insn
, file
, 1);
25262 final (insn
, file
, 1);
25263 final_end_function ();
25265 reload_completed
= 0;
25266 epilogue_completed
= 0;
25269 /* A quick summary of the various types of 'constant-pool tables'
25272 Target Flags Name One table per
25273 AIX (none) AIX TOC object file
25274 AIX -mfull-toc AIX TOC object file
25275 AIX -mminimal-toc AIX minimal TOC translation unit
25276 SVR4/EABI (none) SVR4 SDATA object file
25277 SVR4/EABI -fpic SVR4 pic object file
25278 SVR4/EABI -fPIC SVR4 PIC translation unit
25279 SVR4/EABI -mrelocatable EABI TOC function
25280 SVR4/EABI -maix AIX TOC object file
25281 SVR4/EABI -maix -mminimal-toc
25282 AIX minimal TOC translation unit
25284 Name Reg. Set by entries contains:
25285 made by addrs? fp? sum?
25287 AIX TOC 2 crt0 as Y option option
25288 AIX minimal TOC 30 prolog gcc Y Y option
25289 SVR4 SDATA 13 crt0 gcc N Y N
25290 SVR4 pic 30 prolog ld Y not yet N
25291 SVR4 PIC 30 prolog gcc Y option option
25292 EABI TOC 30 prolog gcc Y option option
25296 /* Hash functions for the hash table. */
25299 rs6000_hash_constant (rtx k
)
25301 enum rtx_code code
= GET_CODE (k
);
25302 enum machine_mode mode
= GET_MODE (k
);
25303 unsigned result
= (code
<< 3) ^ mode
;
25304 const char *format
;
25307 format
= GET_RTX_FORMAT (code
);
25308 flen
= strlen (format
);
25314 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
25316 case CONST_WIDE_INT
:
25319 flen
= CONST_WIDE_INT_NUNITS (k
);
25320 for (i
= 0; i
< flen
; i
++)
25321 result
= result
* 613 + CONST_WIDE_INT_ELT (k
, i
);
25326 if (mode
!= VOIDmode
)
25327 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
25339 for (; fidx
< flen
; fidx
++)
25340 switch (format
[fidx
])
25345 const char *str
= XSTR (k
, fidx
);
25346 len
= strlen (str
);
25347 result
= result
* 613 + len
;
25348 for (i
= 0; i
< len
; i
++)
25349 result
= result
* 613 + (unsigned) str
[i
];
25354 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
25358 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
25361 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
25362 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
25366 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
25367 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
25374 gcc_unreachable ();
25381 toc_hash_function (const void *hash_entry
)
25383 const struct toc_hash_struct
*thc
=
25384 (const struct toc_hash_struct
*) hash_entry
;
25385 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
25388 /* Compare H1 and H2 for equivalence. */
25391 toc_hash_eq (const void *h1
, const void *h2
)
25393 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
25394 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
25396 if (((const struct toc_hash_struct
*) h1
)->key_mode
25397 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
25400 return rtx_equal_p (r1
, r2
);
25403 /* These are the names given by the C++ front-end to vtables, and
25404 vtable-like objects. Ideally, this logic should not be here;
25405 instead, there should be some programmatic way of inquiring as
25406 to whether or not an object is a vtable. */
25408 #define VTABLE_NAME_P(NAME) \
25409 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
25410 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
25411 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
25412 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
25413 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
25415 #ifdef NO_DOLLAR_IN_LABEL
25416 /* Return a GGC-allocated character string translating dollar signs in
25417 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
25420 rs6000_xcoff_strip_dollar (const char *name
)
25426 q
= (const char *) strchr (name
, '$');
25428 if (q
== 0 || q
== name
)
25431 len
= strlen (name
);
25432 strip
= XALLOCAVEC (char, len
+ 1);
25433 strcpy (strip
, name
);
25434 p
= strip
+ (q
- name
);
25438 p
= strchr (p
+ 1, '$');
25441 return ggc_alloc_string (strip
, len
);
25446 rs6000_output_symbol_ref (FILE *file
, rtx x
)
25448 /* Currently C++ toc references to vtables can be emitted before it
25449 is decided whether the vtable is public or private. If this is
25450 the case, then the linker will eventually complain that there is
25451 a reference to an unknown section. Thus, for vtables only,
25452 we emit the TOC reference to reference the symbol and not the
25454 const char *name
= XSTR (x
, 0);
25456 if (VTABLE_NAME_P (name
))
25458 RS6000_OUTPUT_BASENAME (file
, name
);
25461 assemble_name (file
, name
);
25464 /* Output a TOC entry. We derive the entry name from what is being
25468 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
25471 const char *name
= buf
;
25473 HOST_WIDE_INT offset
= 0;
25475 gcc_assert (!TARGET_NO_TOC
);
25477 /* When the linker won't eliminate them, don't output duplicate
25478 TOC entries (this happens on AIX if there is any kind of TOC,
25479 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
25481 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
25483 struct toc_hash_struct
*h
;
25486 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
25487 time because GGC is not initialized at that point. */
25488 if (toc_hash_table
== NULL
)
25489 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
25490 toc_hash_eq
, NULL
);
25492 h
= ggc_alloc
<toc_hash_struct
> ();
25494 h
->key_mode
= mode
;
25495 h
->labelno
= labelno
;
25497 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
25498 if (*found
== NULL
)
25500 else /* This is indeed a duplicate.
25501 Set this label equal to that label. */
25503 fputs ("\t.set ", file
);
25504 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
25505 fprintf (file
, "%d,", labelno
);
25506 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
25507 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
25511 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
25512 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
25513 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
25515 fputs ("\t.set ", file
);
25516 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
25517 fprintf (file
, "%d,", labelno
);
25518 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
25519 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
25527 /* If we're going to put a double constant in the TOC, make sure it's
25528 aligned properly when strict alignment is on. */
25529 if ((CONST_DOUBLE_P (x
) || CONST_WIDE_INT_P (x
))
25530 && STRICT_ALIGNMENT
25531 && GET_MODE_BITSIZE (mode
) >= 64
25532 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
25533 ASM_OUTPUT_ALIGN (file
, 3);
25536 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
25538 /* Handle FP constants specially. Note that if we have a minimal
25539 TOC, things we put here aren't actually in the TOC, so we can allow
25541 if (GET_CODE (x
) == CONST_DOUBLE
&&
25542 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
25544 REAL_VALUE_TYPE rv
;
25547 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
25548 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
25549 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
25551 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
25555 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25556 fputs (DOUBLE_INT_ASM_OP
, file
);
25558 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
25559 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
25560 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
25561 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
25562 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
25563 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
25564 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
25565 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
25570 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25571 fputs ("\t.long ", file
);
25573 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
25574 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
25575 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
25576 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
25577 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
25578 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
25582 else if (GET_CODE (x
) == CONST_DOUBLE
&&
25583 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
25585 REAL_VALUE_TYPE rv
;
25588 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
25590 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
25591 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
25593 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
25597 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25598 fputs (DOUBLE_INT_ASM_OP
, file
);
25600 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
25601 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
25602 fprintf (file
, "0x%lx%08lx\n",
25603 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
25604 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
25609 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25610 fputs ("\t.long ", file
);
25612 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
25613 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
25614 fprintf (file
, "0x%lx,0x%lx\n",
25615 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
25619 else if (GET_CODE (x
) == CONST_DOUBLE
&&
25620 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
25622 REAL_VALUE_TYPE rv
;
25625 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
25626 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
25627 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
25629 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
25633 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25634 fputs (DOUBLE_INT_ASM_OP
, file
);
25636 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
25637 if (WORDS_BIG_ENDIAN
)
25638 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
25640 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
25645 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25646 fputs ("\t.long ", file
);
25648 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
25649 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
25653 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
25655 unsigned HOST_WIDE_INT low
;
25656 HOST_WIDE_INT high
;
25658 low
= INTVAL (x
) & 0xffffffff;
25659 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
25661 /* TOC entries are always Pmode-sized, so when big-endian
25662 smaller integer constants in the TOC need to be padded.
25663 (This is still a win over putting the constants in
25664 a separate constant pool, because then we'd have
25665 to have both a TOC entry _and_ the actual constant.)
25667 For a 32-bit target, CONST_INT values are loaded and shifted
25668 entirely within `low' and can be stored in one TOC entry. */
25670 /* It would be easy to make this work, but it doesn't now. */
25671 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
25673 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
25676 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
25677 high
= (HOST_WIDE_INT
) low
>> 32;
25683 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25684 fputs (DOUBLE_INT_ASM_OP
, file
);
25686 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
25687 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25688 fprintf (file
, "0x%lx%08lx\n",
25689 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25694 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
25696 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25697 fputs ("\t.long ", file
);
25699 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
25700 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25701 fprintf (file
, "0x%lx,0x%lx\n",
25702 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25706 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25707 fputs ("\t.long ", file
);
25709 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
25710 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
25716 if (GET_CODE (x
) == CONST
)
25718 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
25719 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
25721 base
= XEXP (XEXP (x
, 0), 0);
25722 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
25725 switch (GET_CODE (base
))
25728 name
= XSTR (base
, 0);
25732 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
25733 CODE_LABEL_NUMBER (XEXP (base
, 0)));
25737 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
25741 gcc_unreachable ();
25744 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25745 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
25748 fputs ("\t.tc ", file
);
25749 RS6000_OUTPUT_BASENAME (file
, name
);
25752 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
25754 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
25756 /* Mark large TOC symbols on AIX with [TE] so they are mapped
25757 after other TOC symbols, reducing overflow of small TOC access
25758 to [TC] symbols. */
25759 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
25760 ? "[TE]," : "[TC],", file
);
25763 /* Currently C++ toc references to vtables can be emitted before it
25764 is decided whether the vtable is public or private. If this is
25765 the case, then the linker will eventually complain that there is
25766 a TOC reference to an unknown section. Thus, for vtables only,
25767 we emit the TOC reference to reference the symbol and not the
25769 if (VTABLE_NAME_P (name
))
25771 RS6000_OUTPUT_BASENAME (file
, name
);
25773 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
25774 else if (offset
> 0)
25775 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
25778 output_addr_const (file
, x
);
25781 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
25782 && SYMBOL_REF_TLS_MODEL (base
) != 0)
25784 if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_EXEC
)
25785 fputs ("@le", file
);
25786 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_INITIAL_EXEC
)
25787 fputs ("@ie", file
);
25788 /* Use global-dynamic for local-dynamic. */
25789 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_GLOBAL_DYNAMIC
25790 || SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_DYNAMIC
)
25793 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
25794 fputs ("\t.tc .", file
);
25795 RS6000_OUTPUT_BASENAME (file
, name
);
25796 fputs ("[TC],", file
);
25797 output_addr_const (file
, x
);
25798 fputs ("@m", file
);
25806 /* Output an assembler pseudo-op to write an ASCII string of N characters
25807 starting at P to FILE.
25809 On the RS/6000, we have to do this using the .byte operation and
25810 write out special characters outside the quoted string.
25811 Also, the assembler is broken; very long strings are truncated,
25812 so we must artificially break them up early. */
25815 output_ascii (FILE *file
, const char *p
, int n
)
25818 int i
, count_string
;
25819 const char *for_string
= "\t.byte \"";
25820 const char *for_decimal
= "\t.byte ";
25821 const char *to_close
= NULL
;
25824 for (i
= 0; i
< n
; i
++)
25827 if (c
>= ' ' && c
< 0177)
25830 fputs (for_string
, file
);
25833 /* Write two quotes to get one. */
25841 for_decimal
= "\"\n\t.byte ";
25845 if (count_string
>= 512)
25847 fputs (to_close
, file
);
25849 for_string
= "\t.byte \"";
25850 for_decimal
= "\t.byte ";
25858 fputs (for_decimal
, file
);
25859 fprintf (file
, "%d", c
);
25861 for_string
= "\n\t.byte \"";
25862 for_decimal
= ", ";
25868 /* Now close the string if we have written one. Then end the line. */
25870 fputs (to_close
, file
);
25873 /* Generate a unique section name for FILENAME for a section type
25874 represented by SECTION_DESC. Output goes into BUF.
25876 SECTION_DESC can be any string, as long as it is different for each
25877 possible section type.
25879 We name the section in the same manner as xlc. The name begins with an
25880 underscore followed by the filename (after stripping any leading directory
25881 names) with the last period replaced by the string SECTION_DESC. If
25882 FILENAME does not contain a period, SECTION_DESC is appended to the end of
25886 rs6000_gen_section_name (char **buf
, const char *filename
,
25887 const char *section_desc
)
25889 const char *q
, *after_last_slash
, *last_period
= 0;
25893 after_last_slash
= filename
;
25894 for (q
= filename
; *q
; q
++)
25897 after_last_slash
= q
+ 1;
25898 else if (*q
== '.')
25902 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
25903 *buf
= (char *) xmalloc (len
);
25908 for (q
= after_last_slash
; *q
; q
++)
25910 if (q
== last_period
)
25912 strcpy (p
, section_desc
);
25913 p
+= strlen (section_desc
);
25917 else if (ISALNUM (*q
))
25921 if (last_period
== 0)
25922 strcpy (p
, section_desc
);
25927 /* Emit profile function. */
25930 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
25932 /* Non-standard profiling for kernels, which just saves LR then calls
25933 _mcount without worrying about arg saves. The idea is to change
25934 the function prologue as little as possible as it isn't easy to
25935 account for arg save/restore code added just for _mcount. */
25936 if (TARGET_PROFILE_KERNEL
)
25939 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25941 #ifndef NO_PROFILE_COUNTERS
25942 # define NO_PROFILE_COUNTERS 0
25944 if (NO_PROFILE_COUNTERS
)
25945 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
25946 LCT_NORMAL
, VOIDmode
, 0);
25950 const char *label_name
;
25953 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
25954 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
25955 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
25957 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
25958 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
25961 else if (DEFAULT_ABI
== ABI_DARWIN
)
25963 const char *mcount_name
= RS6000_MCOUNT
;
25964 int caller_addr_regno
= LR_REGNO
;
25966 /* Be conservative and always set this, at least for now. */
25967 crtl
->uses_pic_offset_table
= 1;
25970 /* For PIC code, set up a stub and collect the caller's address
25971 from r0, which is where the prologue puts it. */
25972 if (MACHOPIC_INDIRECT
25973 && crtl
->uses_pic_offset_table
)
25974 caller_addr_regno
= 0;
25976 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
25977 LCT_NORMAL
, VOIDmode
, 1,
25978 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
25982 /* Write function profiler code. */
25985 output_function_profiler (FILE *file
, int labelno
)
25989 switch (DEFAULT_ABI
)
25992 gcc_unreachable ();
25997 warning (0, "no profiling of 64-bit code for this ABI");
26000 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
26001 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
26002 if (NO_PROFILE_COUNTERS
)
26004 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26005 reg_names
[0], reg_names
[1]);
26007 else if (TARGET_SECURE_PLT
&& flag_pic
)
26009 if (TARGET_LINK_STACK
)
26012 get_ppc476_thunk_name (name
);
26013 asm_fprintf (file
, "\tbl %s\n", name
);
26016 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
26017 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26018 reg_names
[0], reg_names
[1]);
26019 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
26020 asm_fprintf (file
, "\taddis %s,%s,",
26021 reg_names
[12], reg_names
[12]);
26022 assemble_name (file
, buf
);
26023 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
26024 assemble_name (file
, buf
);
26025 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
26027 else if (flag_pic
== 1)
26029 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
26030 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26031 reg_names
[0], reg_names
[1]);
26032 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
26033 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
26034 assemble_name (file
, buf
);
26035 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
26037 else if (flag_pic
> 1)
26039 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26040 reg_names
[0], reg_names
[1]);
26041 /* Now, we need to get the address of the label. */
26042 if (TARGET_LINK_STACK
)
26045 get_ppc476_thunk_name (name
);
26046 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
26047 assemble_name (file
, buf
);
26048 fputs ("-.\n1:", file
);
26049 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
26050 asm_fprintf (file
, "\taddi %s,%s,4\n",
26051 reg_names
[11], reg_names
[11]);
26055 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
26056 assemble_name (file
, buf
);
26057 fputs ("-.\n1:", file
);
26058 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
26060 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
26061 reg_names
[0], reg_names
[11]);
26062 asm_fprintf (file
, "\tadd %s,%s,%s\n",
26063 reg_names
[0], reg_names
[0], reg_names
[11]);
26067 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
26068 assemble_name (file
, buf
);
26069 fputs ("@ha\n", file
);
26070 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26071 reg_names
[0], reg_names
[1]);
26072 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
26073 assemble_name (file
, buf
);
26074 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
26077 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
26078 fprintf (file
, "\tbl %s%s\n",
26079 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
26085 /* Don't do anything, done in output_profile_hook (). */
26092 /* The following variable value is the last issued insn. */
26094 static rtx last_scheduled_insn
;
26096 /* The following variable helps to balance issuing of load and
26097 store instructions */
26099 static int load_store_pendulum
;
26101 /* Power4 load update and store update instructions are cracked into a
26102 load or store and an integer insn which are executed in the same cycle.
26103 Branches have their own dispatch slot which does not count against the
26104 GCC issue rate, but it changes the program flow so there are no other
26105 instructions to issue in this cycle. */
26108 rs6000_variable_issue_1 (rtx insn
, int more
)
26110 last_scheduled_insn
= insn
;
26111 if (GET_CODE (PATTERN (insn
)) == USE
26112 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26114 cached_can_issue_more
= more
;
26115 return cached_can_issue_more
;
26118 if (insn_terminates_group_p (insn
, current_group
))
26120 cached_can_issue_more
= 0;
26121 return cached_can_issue_more
;
26124 /* If no reservation, but reach here */
26125 if (recog_memoized (insn
) < 0)
26128 if (rs6000_sched_groups
)
26130 if (is_microcoded_insn (insn
))
26131 cached_can_issue_more
= 0;
26132 else if (is_cracked_insn (insn
))
26133 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
26135 cached_can_issue_more
= more
- 1;
26137 return cached_can_issue_more
;
26140 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
26143 cached_can_issue_more
= more
- 1;
26144 return cached_can_issue_more
;
26148 rs6000_variable_issue (FILE *stream
, int verbose
, rtx insn
, int more
)
26150 int r
= rs6000_variable_issue_1 (insn
, more
);
26152 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
26156 /* Adjust the cost of a scheduling dependency. Return the new cost of
26157 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
26160 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
26162 enum attr_type attr_type
;
26164 if (! recog_memoized (insn
))
26167 switch (REG_NOTE_KIND (link
))
26171 /* Data dependency; DEP_INSN writes a register that INSN reads
26172 some cycles later. */
26174 /* Separate a load from a narrower, dependent store. */
26175 if (rs6000_sched_groups
26176 && GET_CODE (PATTERN (insn
)) == SET
26177 && GET_CODE (PATTERN (dep_insn
)) == SET
26178 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
26179 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
26180 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
26181 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
26184 attr_type
= get_attr_type (insn
);
26189 /* Tell the first scheduling pass about the latency between
26190 a mtctr and bctr (and mtlr and br/blr). The first
26191 scheduling pass will not know about this latency since
26192 the mtctr instruction, which has the latency associated
26193 to it, will be generated by reload. */
26196 /* Leave some extra cycles between a compare and its
26197 dependent branch, to inhibit expensive mispredicts. */
26198 if ((rs6000_cpu_attr
== CPU_PPC603
26199 || rs6000_cpu_attr
== CPU_PPC604
26200 || rs6000_cpu_attr
== CPU_PPC604E
26201 || rs6000_cpu_attr
== CPU_PPC620
26202 || rs6000_cpu_attr
== CPU_PPC630
26203 || rs6000_cpu_attr
== CPU_PPC750
26204 || rs6000_cpu_attr
== CPU_PPC7400
26205 || rs6000_cpu_attr
== CPU_PPC7450
26206 || rs6000_cpu_attr
== CPU_PPCE5500
26207 || rs6000_cpu_attr
== CPU_PPCE6500
26208 || rs6000_cpu_attr
== CPU_POWER4
26209 || rs6000_cpu_attr
== CPU_POWER5
26210 || rs6000_cpu_attr
== CPU_POWER7
26211 || rs6000_cpu_attr
== CPU_POWER8
26212 || rs6000_cpu_attr
== CPU_CELL
)
26213 && recog_memoized (dep_insn
)
26214 && (INSN_CODE (dep_insn
) >= 0))
26216 switch (get_attr_type (dep_insn
))
26220 case TYPE_FPCOMPARE
:
26221 case TYPE_CR_LOGICAL
:
26222 case TYPE_DELAYED_CR
:
26225 if (get_attr_dot (dep_insn
) == DOT_YES
)
26230 if (get_attr_dot (dep_insn
) == DOT_YES
26231 && get_attr_var_shift (dep_insn
) == VAR_SHIFT_NO
)
26242 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26243 && recog_memoized (dep_insn
)
26244 && (INSN_CODE (dep_insn
) >= 0))
26247 if (GET_CODE (PATTERN (insn
)) != SET
)
26248 /* If this happens, we have to extend this to schedule
26249 optimally. Return default for now. */
26252 /* Adjust the cost for the case where the value written
26253 by a fixed point operation is used as the address
26254 gen value on a store. */
26255 switch (get_attr_type (dep_insn
))
26260 if (! store_data_bypass_p (dep_insn
, insn
))
26261 return get_attr_sign_extend (dep_insn
)
26262 == SIGN_EXTEND_YES
? 6 : 4;
26267 if (! store_data_bypass_p (dep_insn
, insn
))
26268 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
26279 if (! store_data_bypass_p (dep_insn
, insn
))
26287 if (get_attr_update (dep_insn
) == UPDATE_YES
26288 && ! store_data_bypass_p (dep_insn
, insn
))
26294 if (! store_data_bypass_p (dep_insn
, insn
))
26300 if (! store_data_bypass_p (dep_insn
, insn
))
26301 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
26311 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26312 && recog_memoized (dep_insn
)
26313 && (INSN_CODE (dep_insn
) >= 0))
26316 /* Adjust the cost for the case where the value written
26317 by a fixed point instruction is used within the address
26318 gen portion of a subsequent load(u)(x) */
26319 switch (get_attr_type (dep_insn
))
26324 if (set_to_load_agen (dep_insn
, insn
))
26325 return get_attr_sign_extend (dep_insn
)
26326 == SIGN_EXTEND_YES
? 6 : 4;
26331 if (set_to_load_agen (dep_insn
, insn
))
26332 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
26343 if (set_to_load_agen (dep_insn
, insn
))
26351 if (get_attr_update (dep_insn
) == UPDATE_YES
26352 && set_to_load_agen (dep_insn
, insn
))
26358 if (set_to_load_agen (dep_insn
, insn
))
26364 if (set_to_load_agen (dep_insn
, insn
))
26365 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
26375 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26376 && get_attr_update (insn
) == UPDATE_NO
26377 && recog_memoized (dep_insn
)
26378 && (INSN_CODE (dep_insn
) >= 0)
26379 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
26386 /* Fall out to return default cost. */
26390 case REG_DEP_OUTPUT
:
26391 /* Output dependency; DEP_INSN writes a register that INSN writes some
26393 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26394 && recog_memoized (dep_insn
)
26395 && (INSN_CODE (dep_insn
) >= 0))
26397 attr_type
= get_attr_type (insn
);
26402 if (get_attr_type (dep_insn
) == TYPE_FP
)
26406 if (get_attr_update (insn
) == UPDATE_NO
26407 && get_attr_type (dep_insn
) == TYPE_MFFGPR
)
26415 /* Anti dependency; DEP_INSN reads a register that INSN writes some
26420 gcc_unreachable ();
26426 /* Debug version of rs6000_adjust_cost. */
26429 rs6000_debug_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
26431 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
26437 switch (REG_NOTE_KIND (link
))
26439 default: dep
= "unknown depencency"; break;
26440 case REG_DEP_TRUE
: dep
= "data dependency"; break;
26441 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
26442 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
26446 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
26447 "%s, insn:\n", ret
, cost
, dep
);
26455 /* The function returns a true if INSN is microcoded.
26456 Return false otherwise. */
26459 is_microcoded_insn (rtx insn
)
26461 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26462 || GET_CODE (PATTERN (insn
)) == USE
26463 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26466 if (rs6000_cpu_attr
== CPU_CELL
)
26467 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
26469 if (rs6000_sched_groups
26470 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
26472 enum attr_type type
= get_attr_type (insn
);
26473 if ((type
== TYPE_LOAD
26474 && get_attr_update (insn
) == UPDATE_YES
26475 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
)
26476 || ((type
== TYPE_LOAD
|| type
== TYPE_STORE
)
26477 && get_attr_update (insn
) == UPDATE_YES
26478 && get_attr_indexed (insn
) == INDEXED_YES
)
26479 || type
== TYPE_MFCR
)
26486 /* The function returns true if INSN is cracked into 2 instructions
26487 by the processor (and therefore occupies 2 issue slots). */
26490 is_cracked_insn (rtx insn
)
26492 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26493 || GET_CODE (PATTERN (insn
)) == USE
26494 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26497 if (rs6000_sched_groups
26498 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
26500 enum attr_type type
= get_attr_type (insn
);
26501 if ((type
== TYPE_LOAD
26502 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
26503 && get_attr_update (insn
) == UPDATE_NO
)
26504 || (type
== TYPE_LOAD
26505 && get_attr_sign_extend (insn
) == SIGN_EXTEND_NO
26506 && get_attr_update (insn
) == UPDATE_YES
26507 && get_attr_indexed (insn
) == INDEXED_NO
)
26508 || (type
== TYPE_STORE
26509 && get_attr_update (insn
) == UPDATE_YES
26510 && get_attr_indexed (insn
) == INDEXED_NO
)
26511 || ((type
== TYPE_FPLOAD
|| type
== TYPE_FPSTORE
)
26512 && get_attr_update (insn
) == UPDATE_YES
)
26513 || type
== TYPE_DELAYED_CR
26514 || type
== TYPE_COMPARE
26515 || (type
== TYPE_SHIFT
26516 && get_attr_dot (insn
) == DOT_YES
26517 && get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
26518 || (type
== TYPE_MUL
26519 && get_attr_dot (insn
) == DOT_YES
)
26520 || type
== TYPE_DIV
26521 || (type
== TYPE_INSERT
26522 && get_attr_size (insn
) == SIZE_32
))
26529 /* The function returns true if INSN can be issued only from
26530 the branch slot. */
26533 is_branch_slot_insn (rtx insn
)
26535 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26536 || GET_CODE (PATTERN (insn
)) == USE
26537 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26540 if (rs6000_sched_groups
)
26542 enum attr_type type
= get_attr_type (insn
);
26543 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
26551 /* The function returns true if out_inst sets a value that is
26552 used in the address generation computation of in_insn */
26554 set_to_load_agen (rtx out_insn
, rtx in_insn
)
26556 rtx out_set
, in_set
;
26558 /* For performance reasons, only handle the simple case where
26559 both loads are a single_set. */
26560 out_set
= single_set (out_insn
);
26563 in_set
= single_set (in_insn
);
26565 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
26571 /* Try to determine base/offset/size parts of the given MEM.
26572 Return true if successful, false if all the values couldn't
26575 This function only looks for REG or REG+CONST address forms.
26576 REG+REG address form will return false. */
26579 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
26580 HOST_WIDE_INT
*size
)
26583 if MEM_SIZE_KNOWN_P (mem
)
26584 *size
= MEM_SIZE (mem
);
26588 if (GET_CODE (XEXP (mem
, 0)) == PRE_MODIFY
)
26589 addr_rtx
= XEXP (XEXP (mem
, 0), 1);
26591 addr_rtx
= (XEXP (mem
, 0));
26593 if (GET_CODE (addr_rtx
) == REG
)
26598 else if (GET_CODE (addr_rtx
) == PLUS
26599 && CONST_INT_P (XEXP (addr_rtx
, 1)))
26601 *base
= XEXP (addr_rtx
, 0);
26602 *offset
= INTVAL (XEXP (addr_rtx
, 1));
26610 /* The function returns true if the target storage location of
26611 mem1 is adjacent to the target storage location of mem2 */
26612 /* Return 1 if memory locations are adjacent. */
26615 adjacent_mem_locations (rtx mem1
, rtx mem2
)
26618 HOST_WIDE_INT off1
, size1
, off2
, size2
;
26620 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
26621 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
26622 return ((REGNO (reg1
) == REGNO (reg2
))
26623 && ((off1
+ size1
== off2
)
26624 || (off2
+ size2
== off1
)));
26629 /* This function returns true if it can be determined that the two MEM
26630 locations overlap by at least 1 byte based on base reg/offset/size. */
26633 mem_locations_overlap (rtx mem1
, rtx mem2
)
26636 HOST_WIDE_INT off1
, size1
, off2
, size2
;
26638 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
26639 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
26640 return ((REGNO (reg1
) == REGNO (reg2
))
26641 && (((off1
<= off2
) && (off1
+ size1
> off2
))
26642 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
26647 /* A C statement (sans semicolon) to update the integer scheduling
26648 priority INSN_PRIORITY (INSN). Increase the priority to execute the
26649 INSN earlier, reduce the priority to execute INSN later. Do not
26650 define this macro if you do not need to adjust the scheduling
26651 priorities of insns. */
26654 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
26656 rtx load_mem
, str_mem
;
26657 /* On machines (like the 750) which have asymmetric integer units,
26658 where one integer unit can do multiply and divides and the other
26659 can't, reduce the priority of multiply/divide so it is scheduled
26660 before other integer operations. */
26663 if (! INSN_P (insn
))
26666 if (GET_CODE (PATTERN (insn
)) == USE
)
26669 switch (rs6000_cpu_attr
) {
26671 switch (get_attr_type (insn
))
26678 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
26679 priority
, priority
);
26680 if (priority
>= 0 && priority
< 0x01000000)
26687 if (insn_must_be_first_in_group (insn
)
26688 && reload_completed
26689 && current_sched_info
->sched_max_insns_priority
26690 && rs6000_sched_restricted_insns_priority
)
26693 /* Prioritize insns that can be dispatched only in the first
26695 if (rs6000_sched_restricted_insns_priority
== 1)
26696 /* Attach highest priority to insn. This means that in
26697 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
26698 precede 'priority' (critical path) considerations. */
26699 return current_sched_info
->sched_max_insns_priority
;
26700 else if (rs6000_sched_restricted_insns_priority
== 2)
26701 /* Increase priority of insn by a minimal amount. This means that in
26702 haifa-sched.c:ready_sort(), only 'priority' (critical path)
26703 considerations precede dispatch-slot restriction considerations. */
26704 return (priority
+ 1);
26707 if (rs6000_cpu
== PROCESSOR_POWER6
26708 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
26709 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
26710 /* Attach highest priority to insn if the scheduler has just issued two
26711 stores and this instruction is a load, or two loads and this instruction
26712 is a store. Power6 wants loads and stores scheduled alternately
26714 return current_sched_info
->sched_max_insns_priority
;
26719 /* Return true if the instruction is nonpipelined on the Cell. */
26721 is_nonpipeline_insn (rtx insn
)
26723 enum attr_type type
;
26724 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26725 || GET_CODE (PATTERN (insn
)) == USE
26726 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26729 type
= get_attr_type (insn
);
26730 if (type
== TYPE_MUL
26731 || type
== TYPE_DIV
26732 || type
== TYPE_SDIV
26733 || type
== TYPE_DDIV
26734 || type
== TYPE_SSQRT
26735 || type
== TYPE_DSQRT
26736 || type
== TYPE_MFCR
26737 || type
== TYPE_MFCRF
26738 || type
== TYPE_MFJMPR
)
26746 /* Return how many instructions the machine can issue per cycle. */
26749 rs6000_issue_rate (void)
26751 /* Unless scheduling for register pressure, use issue rate of 1 for
26752 first scheduling pass to decrease degradation. */
26753 if (!reload_completed
&& !flag_sched_pressure
)
26756 switch (rs6000_cpu_attr
) {
26758 case CPU_PPC601
: /* ? */
26768 case CPU_PPCE300C2
:
26769 case CPU_PPCE300C3
:
26770 case CPU_PPCE500MC
:
26771 case CPU_PPCE500MC64
:
26794 /* Return how many instructions to look ahead for better insn
26798 rs6000_use_sched_lookahead (void)
26800 switch (rs6000_cpu_attr
)
26807 return (reload_completed
? 8 : 0);
26814 /* We are choosing insn from the ready queue. Return zero if INSN can be
26817 rs6000_use_sched_lookahead_guard (rtx insn
, int ready_index
)
26819 if (ready_index
== 0)
26822 if (rs6000_cpu_attr
!= CPU_CELL
)
26825 gcc_assert (insn
!= NULL_RTX
&& INSN_P (insn
));
26827 if (!reload_completed
26828 || is_nonpipeline_insn (insn
)
26829 || is_microcoded_insn (insn
))
26835 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
26836 and return true. */
26839 find_mem_ref (rtx pat
, rtx
*mem_ref
)
26844 /* stack_tie does not produce any real memory traffic. */
26845 if (tie_operand (pat
, VOIDmode
))
26848 if (GET_CODE (pat
) == MEM
)
26854 /* Recursively process the pattern. */
26855 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
26857 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
26861 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
26864 else if (fmt
[i
] == 'E')
26865 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
26867 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
26875 /* Determine if PAT is a PATTERN of a load insn. */
26878 is_load_insn1 (rtx pat
, rtx
*load_mem
)
26880 if (!pat
|| pat
== NULL_RTX
)
26883 if (GET_CODE (pat
) == SET
)
26884 return find_mem_ref (SET_SRC (pat
), load_mem
);
26886 if (GET_CODE (pat
) == PARALLEL
)
26890 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
26891 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
26898 /* Determine if INSN loads from memory. */
26901 is_load_insn (rtx insn
, rtx
*load_mem
)
26903 if (!insn
|| !INSN_P (insn
))
26909 return is_load_insn1 (PATTERN (insn
), load_mem
);
26912 /* Determine if PAT is a PATTERN of a store insn. */
26915 is_store_insn1 (rtx pat
, rtx
*str_mem
)
26917 if (!pat
|| pat
== NULL_RTX
)
26920 if (GET_CODE (pat
) == SET
)
26921 return find_mem_ref (SET_DEST (pat
), str_mem
);
26923 if (GET_CODE (pat
) == PARALLEL
)
26927 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
26928 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
26935 /* Determine if INSN stores to memory. */
26938 is_store_insn (rtx insn
, rtx
*str_mem
)
26940 if (!insn
|| !INSN_P (insn
))
26943 return is_store_insn1 (PATTERN (insn
), str_mem
);
26946 /* Returns whether the dependence between INSN and NEXT is considered
26947 costly by the given target. */
26950 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
26954 rtx load_mem
, str_mem
;
26956 /* If the flag is not enabled - no dependence is considered costly;
26957 allow all dependent insns in the same group.
26958 This is the most aggressive option. */
26959 if (rs6000_sched_costly_dep
== no_dep_costly
)
26962 /* If the flag is set to 1 - a dependence is always considered costly;
26963 do not allow dependent instructions in the same group.
26964 This is the most conservative option. */
26965 if (rs6000_sched_costly_dep
== all_deps_costly
)
26968 insn
= DEP_PRO (dep
);
26969 next
= DEP_CON (dep
);
26971 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
26972 && is_load_insn (next
, &load_mem
)
26973 && is_store_insn (insn
, &str_mem
))
26974 /* Prevent load after store in the same group. */
26977 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
26978 && is_load_insn (next
, &load_mem
)
26979 && is_store_insn (insn
, &str_mem
)
26980 && DEP_TYPE (dep
) == REG_DEP_TRUE
26981 && mem_locations_overlap(str_mem
, load_mem
))
26982 /* Prevent load after store in the same group if it is a true
26986 /* The flag is set to X; dependences with latency >= X are considered costly,
26987 and will not be scheduled in the same group. */
26988 if (rs6000_sched_costly_dep
<= max_dep_latency
26989 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
26995 /* Return the next insn after INSN that is found before TAIL is reached,
26996 skipping any "non-active" insns - insns that will not actually occupy
26997 an issue slot. Return NULL_RTX if such an insn is not found. */
27000 get_next_active_insn (rtx insn
, rtx tail
)
27002 if (insn
== NULL_RTX
|| insn
== tail
)
27007 insn
= NEXT_INSN (insn
);
27008 if (insn
== NULL_RTX
|| insn
== tail
)
27012 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
27013 || (NONJUMP_INSN_P (insn
)
27014 && GET_CODE (PATTERN (insn
)) != USE
27015 && GET_CODE (PATTERN (insn
)) != CLOBBER
27016 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
27022 /* We are about to begin issuing insns for this clock cycle. */
27025 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
27026 rtx
*ready ATTRIBUTE_UNUSED
,
27027 int *pn_ready ATTRIBUTE_UNUSED
,
27028 int clock_var ATTRIBUTE_UNUSED
)
27030 int n_ready
= *pn_ready
;
27033 fprintf (dump
, "// rs6000_sched_reorder :\n");
27035 /* Reorder the ready list, if the second to last ready insn
27036 is a nonepipeline insn. */
27037 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
27039 if (is_nonpipeline_insn (ready
[n_ready
- 1])
27040 && (recog_memoized (ready
[n_ready
- 2]) > 0))
27041 /* Simply swap first two insns. */
27043 rtx tmp
= ready
[n_ready
- 1];
27044 ready
[n_ready
- 1] = ready
[n_ready
- 2];
27045 ready
[n_ready
- 2] = tmp
;
27049 if (rs6000_cpu
== PROCESSOR_POWER6
)
27050 load_store_pendulum
= 0;
27052 return rs6000_issue_rate ();
27055 /* Like rs6000_sched_reorder, but called after issuing each insn. */
27058 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
27059 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
27062 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
27064 /* For Power6, we need to handle some special cases to try and keep the
27065 store queue from overflowing and triggering expensive flushes.
27067 This code monitors how load and store instructions are being issued
27068 and skews the ready list one way or the other to increase the likelihood
27069 that a desired instruction is issued at the proper time.
27071 A couple of things are done. First, we maintain a "load_store_pendulum"
27072 to track the current state of load/store issue.
27074 - If the pendulum is at zero, then no loads or stores have been
27075 issued in the current cycle so we do nothing.
27077 - If the pendulum is 1, then a single load has been issued in this
27078 cycle and we attempt to locate another load in the ready list to
27081 - If the pendulum is -2, then two stores have already been
27082 issued in this cycle, so we increase the priority of the first load
27083 in the ready list to increase it's likelihood of being chosen first
27086 - If the pendulum is -1, then a single store has been issued in this
27087 cycle and we attempt to locate another store in the ready list to
27088 issue with it, preferring a store to an adjacent memory location to
27089 facilitate store pairing in the store queue.
27091 - If the pendulum is 2, then two loads have already been
27092 issued in this cycle, so we increase the priority of the first store
27093 in the ready list to increase it's likelihood of being chosen first
27096 - If the pendulum < -2 or > 2, then do nothing.
27098 Note: This code covers the most common scenarios. There exist non
27099 load/store instructions which make use of the LSU and which
27100 would need to be accounted for to strictly model the behavior
27101 of the machine. Those instructions are currently unaccounted
27102 for to help minimize compile time overhead of this code.
27104 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
27108 rtx tmp
, load_mem
, str_mem
;
27110 if (is_store_insn (last_scheduled_insn
, &str_mem
))
27111 /* Issuing a store, swing the load_store_pendulum to the left */
27112 load_store_pendulum
--;
27113 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
27114 /* Issuing a load, swing the load_store_pendulum to the right */
27115 load_store_pendulum
++;
27117 return cached_can_issue_more
;
27119 /* If the pendulum is balanced, or there is only one instruction on
27120 the ready list, then all is well, so return. */
27121 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
27122 return cached_can_issue_more
;
27124 if (load_store_pendulum
== 1)
27126 /* A load has been issued in this cycle. Scan the ready list
27127 for another load to issue with it */
27132 if (is_load_insn (ready
[pos
], &load_mem
))
27134 /* Found a load. Move it to the head of the ready list,
27135 and adjust it's priority so that it is more likely to
27138 for (i
=pos
; i
<*pn_ready
-1; i
++)
27139 ready
[i
] = ready
[i
+ 1];
27140 ready
[*pn_ready
-1] = tmp
;
27142 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27143 INSN_PRIORITY (tmp
)++;
27149 else if (load_store_pendulum
== -2)
27151 /* Two stores have been issued in this cycle. Increase the
27152 priority of the first load in the ready list to favor it for
27153 issuing in the next cycle. */
27158 if (is_load_insn (ready
[pos
], &load_mem
)
27160 && INSN_PRIORITY_KNOWN (ready
[pos
]))
27162 INSN_PRIORITY (ready
[pos
])++;
27164 /* Adjust the pendulum to account for the fact that a load
27165 was found and increased in priority. This is to prevent
27166 increasing the priority of multiple loads */
27167 load_store_pendulum
--;
27174 else if (load_store_pendulum
== -1)
27176 /* A store has been issued in this cycle. Scan the ready list for
27177 another store to issue with it, preferring a store to an adjacent
27179 int first_store_pos
= -1;
27185 if (is_store_insn (ready
[pos
], &str_mem
))
27188 /* Maintain the index of the first store found on the
27190 if (first_store_pos
== -1)
27191 first_store_pos
= pos
;
27193 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
27194 && adjacent_mem_locations (str_mem
, str_mem2
))
27196 /* Found an adjacent store. Move it to the head of the
27197 ready list, and adjust it's priority so that it is
27198 more likely to stay there */
27200 for (i
=pos
; i
<*pn_ready
-1; i
++)
27201 ready
[i
] = ready
[i
+ 1];
27202 ready
[*pn_ready
-1] = tmp
;
27204 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27205 INSN_PRIORITY (tmp
)++;
27207 first_store_pos
= -1;
27215 if (first_store_pos
>= 0)
27217 /* An adjacent store wasn't found, but a non-adjacent store was,
27218 so move the non-adjacent store to the front of the ready
27219 list, and adjust its priority so that it is more likely to
27221 tmp
= ready
[first_store_pos
];
27222 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
27223 ready
[i
] = ready
[i
+ 1];
27224 ready
[*pn_ready
-1] = tmp
;
27225 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27226 INSN_PRIORITY (tmp
)++;
27229 else if (load_store_pendulum
== 2)
27231 /* Two loads have been issued in this cycle. Increase the priority
27232 of the first store in the ready list to favor it for issuing in
27238 if (is_store_insn (ready
[pos
], &str_mem
)
27240 && INSN_PRIORITY_KNOWN (ready
[pos
]))
27242 INSN_PRIORITY (ready
[pos
])++;
27244 /* Adjust the pendulum to account for the fact that a store
27245 was found and increased in priority. This is to prevent
27246 increasing the priority of multiple stores */
27247 load_store_pendulum
++;
27256 return cached_can_issue_more
;
27259 /* Return whether the presence of INSN causes a dispatch group termination
27260 of group WHICH_GROUP.
27262 If WHICH_GROUP == current_group, this function will return true if INSN
27263 causes the termination of the current group (i.e, the dispatch group to
27264 which INSN belongs). This means that INSN will be the last insn in the
27265 group it belongs to.
27267 If WHICH_GROUP == previous_group, this function will return true if INSN
27268 causes the termination of the previous group (i.e, the dispatch group that
27269 precedes the group to which INSN belongs). This means that INSN will be
27270 the first insn in the group it belongs to). */
27273 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
27280 first
= insn_must_be_first_in_group (insn
);
27281 last
= insn_must_be_last_in_group (insn
);
27286 if (which_group
== current_group
)
27288 else if (which_group
== previous_group
)
27296 insn_must_be_first_in_group (rtx insn
)
27298 enum attr_type type
;
27302 || DEBUG_INSN_P (insn
)
27303 || GET_CODE (PATTERN (insn
)) == USE
27304 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
27307 switch (rs6000_cpu
)
27309 case PROCESSOR_POWER5
:
27310 if (is_cracked_insn (insn
))
27312 case PROCESSOR_POWER4
:
27313 if (is_microcoded_insn (insn
))
27316 if (!rs6000_sched_groups
)
27319 type
= get_attr_type (insn
);
27326 case TYPE_DELAYED_CR
:
27327 case TYPE_CR_LOGICAL
:
27340 case PROCESSOR_POWER6
:
27341 type
= get_attr_type (insn
);
27350 case TYPE_FPCOMPARE
:
27361 if (get_attr_dot (insn
) == DOT_NO
27362 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
27367 if (get_attr_size (insn
) == SIZE_32
)
27375 if (get_attr_update (insn
) == UPDATE_YES
)
27383 case PROCESSOR_POWER7
:
27384 type
= get_attr_type (insn
);
27388 case TYPE_CR_LOGICAL
:
27402 if (get_attr_dot (insn
) == DOT_YES
)
27407 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
27408 || get_attr_update (insn
) == UPDATE_YES
)
27415 if (get_attr_update (insn
) == UPDATE_YES
)
27423 case PROCESSOR_POWER8
:
27424 type
= get_attr_type (insn
);
27428 case TYPE_CR_LOGICAL
:
27429 case TYPE_DELAYED_CR
:
27438 case TYPE_VECSTORE
:
27444 if (get_attr_dot (insn
) == DOT_YES
)
27449 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
27450 || get_attr_update (insn
) == UPDATE_YES
)
27455 if (get_attr_update (insn
) == UPDATE_YES
27456 && get_attr_indexed (insn
) == INDEXED_YES
)
27472 insn_must_be_last_in_group (rtx insn
)
27474 enum attr_type type
;
27478 || DEBUG_INSN_P (insn
)
27479 || GET_CODE (PATTERN (insn
)) == USE
27480 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
27483 switch (rs6000_cpu
) {
27484 case PROCESSOR_POWER4
:
27485 case PROCESSOR_POWER5
:
27486 if (is_microcoded_insn (insn
))
27489 if (is_branch_slot_insn (insn
))
27493 case PROCESSOR_POWER6
:
27494 type
= get_attr_type (insn
);
27502 case TYPE_FPCOMPARE
:
27513 if (get_attr_dot (insn
) == DOT_NO
27514 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
27519 if (get_attr_size (insn
) == SIZE_32
)
27527 case PROCESSOR_POWER7
:
27528 type
= get_attr_type (insn
);
27538 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
27539 && get_attr_update (insn
) == UPDATE_YES
)
27544 if (get_attr_update (insn
) == UPDATE_YES
27545 && get_attr_indexed (insn
) == INDEXED_YES
)
27553 case PROCESSOR_POWER8
:
27554 type
= get_attr_type (insn
);
27566 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
27567 && get_attr_update (insn
) == UPDATE_YES
)
27572 if (get_attr_update (insn
) == UPDATE_YES
27573 && get_attr_indexed (insn
) == INDEXED_YES
)
27588 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
27589 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
27592 is_costly_group (rtx
*group_insns
, rtx next_insn
)
27595 int issue_rate
= rs6000_issue_rate ();
27597 for (i
= 0; i
< issue_rate
; i
++)
27599 sd_iterator_def sd_it
;
27601 rtx insn
= group_insns
[i
];
27606 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
27608 rtx next
= DEP_CON (dep
);
27610 if (next
== next_insn
27611 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
27619 /* Utility of the function redefine_groups.
27620 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
27621 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
27622 to keep it "far" (in a separate group) from GROUP_INSNS, following
27623 one of the following schemes, depending on the value of the flag
27624 -minsert_sched_nops = X:
27625 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
27626 in order to force NEXT_INSN into a separate group.
27627 (2) X < sched_finish_regroup_exact: insert exactly X nops.
27628 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
27629 insertion (has a group just ended, how many vacant issue slots remain in the
27630 last group, and how many dispatch groups were encountered so far). */
27633 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
27634 rtx next_insn
, bool *group_end
, int can_issue_more
,
27639 int issue_rate
= rs6000_issue_rate ();
27640 bool end
= *group_end
;
27643 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
27644 return can_issue_more
;
27646 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
27647 return can_issue_more
;
27649 force
= is_costly_group (group_insns
, next_insn
);
27651 return can_issue_more
;
27653 if (sched_verbose
> 6)
27654 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
27655 *group_count
,can_issue_more
);
27657 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
27660 can_issue_more
= 0;
27662 /* Since only a branch can be issued in the last issue_slot, it is
27663 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
27664 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
27665 in this case the last nop will start a new group and the branch
27666 will be forced to the new group. */
27667 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
27670 /* Do we have a special group ending nop? */
27671 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
27672 || rs6000_cpu_attr
== CPU_POWER8
)
27674 nop
= gen_group_ending_nop ();
27675 emit_insn_before (nop
, next_insn
);
27676 can_issue_more
= 0;
27679 while (can_issue_more
> 0)
27682 emit_insn_before (nop
, next_insn
);
27690 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
27692 int n_nops
= rs6000_sched_insert_nops
;
27694 /* Nops can't be issued from the branch slot, so the effective
27695 issue_rate for nops is 'issue_rate - 1'. */
27696 if (can_issue_more
== 0)
27697 can_issue_more
= issue_rate
;
27699 if (can_issue_more
== 0)
27701 can_issue_more
= issue_rate
- 1;
27704 for (i
= 0; i
< issue_rate
; i
++)
27706 group_insns
[i
] = 0;
27713 emit_insn_before (nop
, next_insn
);
27714 if (can_issue_more
== issue_rate
- 1) /* new group begins */
27717 if (can_issue_more
== 0)
27719 can_issue_more
= issue_rate
- 1;
27722 for (i
= 0; i
< issue_rate
; i
++)
27724 group_insns
[i
] = 0;
27730 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
27733 /* Is next_insn going to start a new group? */
27736 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
27737 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
27738 || (can_issue_more
< issue_rate
&&
27739 insn_terminates_group_p (next_insn
, previous_group
)));
27740 if (*group_end
&& end
)
27743 if (sched_verbose
> 6)
27744 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
27745 *group_count
, can_issue_more
);
27746 return can_issue_more
;
27749 return can_issue_more
;
27752 /* This function tries to synch the dispatch groups that the compiler "sees"
27753 with the dispatch groups that the processor dispatcher is expected to
27754 form in practice. It tries to achieve this synchronization by forcing the
27755 estimated processor grouping on the compiler (as opposed to the function
27756 'pad_goups' which tries to force the scheduler's grouping on the processor).
27758 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
27759 examines the (estimated) dispatch groups that will be formed by the processor
27760 dispatcher. It marks these group boundaries to reflect the estimated
27761 processor grouping, overriding the grouping that the scheduler had marked.
27762 Depending on the value of the flag '-minsert-sched-nops' this function can
27763 force certain insns into separate groups or force a certain distance between
27764 them by inserting nops, for example, if there exists a "costly dependence"
27767 The function estimates the group boundaries that the processor will form as
27768 follows: It keeps track of how many vacant issue slots are available after
27769 each insn. A subsequent insn will start a new group if one of the following
27771 - no more vacant issue slots remain in the current dispatch group.
27772 - only the last issue slot, which is the branch slot, is vacant, but the next
27773 insn is not a branch.
27774 - only the last 2 or less issue slots, including the branch slot, are vacant,
27775 which means that a cracked insn (which occupies two issue slots) can't be
27776 issued in this group.
27777 - less than 'issue_rate' slots are vacant, and the next insn always needs to
27778 start a new group. */
27781 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
27783 rtx insn
, next_insn
;
27785 int can_issue_more
;
27788 int group_count
= 0;
27792 issue_rate
= rs6000_issue_rate ();
27793 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
27794 for (i
= 0; i
< issue_rate
; i
++)
27796 group_insns
[i
] = 0;
27798 can_issue_more
= issue_rate
;
27800 insn
= get_next_active_insn (prev_head_insn
, tail
);
27803 while (insn
!= NULL_RTX
)
27805 slot
= (issue_rate
- can_issue_more
);
27806 group_insns
[slot
] = insn
;
27808 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
27809 if (insn_terminates_group_p (insn
, current_group
))
27810 can_issue_more
= 0;
27812 next_insn
= get_next_active_insn (insn
, tail
);
27813 if (next_insn
== NULL_RTX
)
27814 return group_count
+ 1;
27816 /* Is next_insn going to start a new group? */
27818 = (can_issue_more
== 0
27819 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
27820 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
27821 || (can_issue_more
< issue_rate
&&
27822 insn_terminates_group_p (next_insn
, previous_group
)));
27824 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
27825 next_insn
, &group_end
, can_issue_more
,
27831 can_issue_more
= 0;
27832 for (i
= 0; i
< issue_rate
; i
++)
27834 group_insns
[i
] = 0;
27838 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
27839 PUT_MODE (next_insn
, VOIDmode
);
27840 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
27841 PUT_MODE (next_insn
, TImode
);
27844 if (can_issue_more
== 0)
27845 can_issue_more
= issue_rate
;
27848 return group_count
;
27851 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
27852 dispatch group boundaries that the scheduler had marked. Pad with nops
27853 any dispatch groups which have vacant issue slots, in order to force the
27854 scheduler's grouping on the processor dispatcher. The function
27855 returns the number of dispatch groups found. */
27858 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
27860 rtx insn
, next_insn
;
27863 int can_issue_more
;
27865 int group_count
= 0;
27867 /* Initialize issue_rate. */
27868 issue_rate
= rs6000_issue_rate ();
27869 can_issue_more
= issue_rate
;
27871 insn
= get_next_active_insn (prev_head_insn
, tail
);
27872 next_insn
= get_next_active_insn (insn
, tail
);
27874 while (insn
!= NULL_RTX
)
27877 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
27879 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
27881 if (next_insn
== NULL_RTX
)
27886 /* If the scheduler had marked group termination at this location
27887 (between insn and next_insn), and neither insn nor next_insn will
27888 force group termination, pad the group with nops to force group
27891 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
27892 && !insn_terminates_group_p (insn
, current_group
)
27893 && !insn_terminates_group_p (next_insn
, previous_group
))
27895 if (!is_branch_slot_insn (next_insn
))
27898 while (can_issue_more
)
27901 emit_insn_before (nop
, next_insn
);
27906 can_issue_more
= issue_rate
;
27911 next_insn
= get_next_active_insn (insn
, tail
);
27914 return group_count
;
27917 /* We're beginning a new block. Initialize data structures as necessary. */
27920 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
27921 int sched_verbose ATTRIBUTE_UNUSED
,
27922 int max_ready ATTRIBUTE_UNUSED
)
27924 last_scheduled_insn
= NULL_RTX
;
27925 load_store_pendulum
= 0;
27928 /* The following function is called at the end of scheduling BB.
27929 After reload, it inserts nops at insn group bundling. */
27932 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
27937 fprintf (dump
, "=== Finishing schedule.\n");
27939 if (reload_completed
&& rs6000_sched_groups
)
27941 /* Do not run sched_finish hook when selective scheduling enabled. */
27942 if (sel_sched_p ())
27945 if (rs6000_sched_insert_nops
== sched_finish_none
)
27948 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
27949 n_groups
= pad_groups (dump
, sched_verbose
,
27950 current_sched_info
->prev_head
,
27951 current_sched_info
->next_tail
);
27953 n_groups
= redefine_groups (dump
, sched_verbose
,
27954 current_sched_info
->prev_head
,
27955 current_sched_info
->next_tail
);
27957 if (sched_verbose
>= 6)
27959 fprintf (dump
, "ngroups = %d\n", n_groups
);
27960 print_rtl (dump
, current_sched_info
->prev_head
);
27961 fprintf (dump
, "Done finish_sched\n");
27966 struct _rs6000_sched_context
27968 short cached_can_issue_more
;
27969 rtx last_scheduled_insn
;
27970 int load_store_pendulum
;
27973 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
27974 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
27976 /* Allocate store for new scheduling context. */
27978 rs6000_alloc_sched_context (void)
27980 return xmalloc (sizeof (rs6000_sched_context_def
));
27983 /* If CLEAN_P is true then initializes _SC with clean data,
27984 and from the global context otherwise. */
27986 rs6000_init_sched_context (void *_sc
, bool clean_p
)
27988 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
27992 sc
->cached_can_issue_more
= 0;
27993 sc
->last_scheduled_insn
= NULL_RTX
;
27994 sc
->load_store_pendulum
= 0;
27998 sc
->cached_can_issue_more
= cached_can_issue_more
;
27999 sc
->last_scheduled_insn
= last_scheduled_insn
;
28000 sc
->load_store_pendulum
= load_store_pendulum
;
28004 /* Sets the global scheduling context to the one pointed to by _SC. */
28006 rs6000_set_sched_context (void *_sc
)
28008 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
28010 gcc_assert (sc
!= NULL
);
28012 cached_can_issue_more
= sc
->cached_can_issue_more
;
28013 last_scheduled_insn
= sc
->last_scheduled_insn
;
28014 load_store_pendulum
= sc
->load_store_pendulum
;
28019 rs6000_free_sched_context (void *_sc
)
28021 gcc_assert (_sc
!= NULL
);
28027 /* Length in units of the trampoline for entering a nested function. */
28030 rs6000_trampoline_size (void)
28034 switch (DEFAULT_ABI
)
28037 gcc_unreachable ();
28040 ret
= (TARGET_32BIT
) ? 12 : 24;
28044 gcc_assert (!TARGET_32BIT
);
28050 ret
= (TARGET_32BIT
) ? 40 : 48;
28057 /* Emit RTL insns to initialize the variable parts of a trampoline.
28058 FNADDR is an RTX for the address of the function's pure code.
28059 CXT is an RTX for the static chain value for the function. */
28062 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
28064 int regsize
= (TARGET_32BIT
) ? 4 : 8;
28065 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
28066 rtx ctx_reg
= force_reg (Pmode
, cxt
);
28067 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
28069 switch (DEFAULT_ABI
)
28072 gcc_unreachable ();
28074 /* Under AIX, just build the 3 word function descriptor */
28077 rtx fnmem
, fn_reg
, toc_reg
;
28079 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
28080 error ("You cannot take the address of a nested function if you use "
28081 "the -mno-pointers-to-nested-functions option.");
28083 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
28084 fn_reg
= gen_reg_rtx (Pmode
);
28085 toc_reg
= gen_reg_rtx (Pmode
);
28087 /* Macro to shorten the code expansions below. */
28088 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
28090 m_tramp
= replace_equiv_address (m_tramp
, addr
);
28092 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
28093 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
28094 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
28095 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
28096 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
28102 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
28106 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
28107 LCT_NORMAL
, VOIDmode
, 4,
28109 GEN_INT (rs6000_trampoline_size ()), SImode
,
28117 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
28118 identifier as an argument, so the front end shouldn't look it up. */
28121 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
28123 return is_attribute_p ("altivec", attr_id
);
28126 /* Handle the "altivec" attribute. The attribute may have
28127 arguments as follows:
28129 __attribute__((altivec(vector__)))
28130 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
28131 __attribute__((altivec(bool__))) (always followed by 'unsigned')
28133 and may appear more than once (e.g., 'vector bool char') in a
28134 given declaration. */
28137 rs6000_handle_altivec_attribute (tree
*node
,
28138 tree name ATTRIBUTE_UNUSED
,
28140 int flags ATTRIBUTE_UNUSED
,
28141 bool *no_add_attrs
)
28143 tree type
= *node
, result
= NULL_TREE
;
28144 enum machine_mode mode
;
28147 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
28148 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
28149 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
28152 while (POINTER_TYPE_P (type
)
28153 || TREE_CODE (type
) == FUNCTION_TYPE
28154 || TREE_CODE (type
) == METHOD_TYPE
28155 || TREE_CODE (type
) == ARRAY_TYPE
)
28156 type
= TREE_TYPE (type
);
28158 mode
= TYPE_MODE (type
);
28160 /* Check for invalid AltiVec type qualifiers. */
28161 if (type
== long_double_type_node
)
28162 error ("use of %<long double%> in AltiVec types is invalid");
28163 else if (type
== boolean_type_node
)
28164 error ("use of boolean types in AltiVec types is invalid");
28165 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
28166 error ("use of %<complex%> in AltiVec types is invalid");
28167 else if (DECIMAL_FLOAT_MODE_P (mode
))
28168 error ("use of decimal floating point types in AltiVec types is invalid");
28169 else if (!TARGET_VSX
)
28171 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
28174 error ("use of %<long%> in AltiVec types is invalid for "
28175 "64-bit code without -mvsx");
28176 else if (rs6000_warn_altivec_long
)
28177 warning (0, "use of %<long%> in AltiVec types is deprecated; "
28180 else if (type
== long_long_unsigned_type_node
28181 || type
== long_long_integer_type_node
)
28182 error ("use of %<long long%> in AltiVec types is invalid without "
28184 else if (type
== double_type_node
)
28185 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
28188 switch (altivec_type
)
28191 unsigned_p
= TYPE_UNSIGNED (type
);
28195 result
= (unsigned_p
? unsigned_V1TI_type_node
: V1TI_type_node
);
28198 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
28201 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
28204 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
28207 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
28209 case SFmode
: result
= V4SF_type_node
; break;
28210 case DFmode
: result
= V2DF_type_node
; break;
28211 /* If the user says 'vector int bool', we may be handed the 'bool'
28212 attribute _before_ the 'vector' attribute, and so select the
28213 proper type in the 'b' case below. */
28214 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
28215 case V2DImode
: case V2DFmode
:
28223 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
28224 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
28225 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
28226 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
28233 case V8HImode
: result
= pixel_V8HI_type_node
;
28239 /* Propagate qualifiers attached to the element type
28240 onto the vector type. */
28241 if (result
&& result
!= type
&& TYPE_QUALS (type
))
28242 result
= build_qualified_type (result
, TYPE_QUALS (type
));
28244 *no_add_attrs
= true; /* No need to hang on to the attribute. */
28247 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
28252 /* AltiVec defines four built-in scalar types that serve as vector
28253 elements; we must teach the compiler how to mangle them. */
28255 static const char *
28256 rs6000_mangle_type (const_tree type
)
28258 type
= TYPE_MAIN_VARIANT (type
);
28260 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
28261 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
28264 if (type
== bool_char_type_node
) return "U6__boolc";
28265 if (type
== bool_short_type_node
) return "U6__bools";
28266 if (type
== pixel_type_node
) return "u7__pixel";
28267 if (type
== bool_int_type_node
) return "U6__booli";
28268 if (type
== bool_long_type_node
) return "U6__booll";
28270 /* Mangle IBM extended float long double as `g' (__float128) on
28271 powerpc*-linux where long-double-64 previously was the default. */
28272 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
28274 && TARGET_LONG_DOUBLE_128
28275 && !TARGET_IEEEQUAD
)
28278 /* For all other types, use normal C++ mangling. */
28282 /* Handle a "longcall" or "shortcall" attribute; arguments as in
28283 struct attribute_spec.handler. */
28286 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
28287 tree args ATTRIBUTE_UNUSED
,
28288 int flags ATTRIBUTE_UNUSED
,
28289 bool *no_add_attrs
)
28291 if (TREE_CODE (*node
) != FUNCTION_TYPE
28292 && TREE_CODE (*node
) != FIELD_DECL
28293 && TREE_CODE (*node
) != TYPE_DECL
)
28295 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
28297 *no_add_attrs
= true;
28303 /* Set longcall attributes on all functions declared when
28304 rs6000_default_long_calls is true. */
28306 rs6000_set_default_type_attributes (tree type
)
28308 if (rs6000_default_long_calls
28309 && (TREE_CODE (type
) == FUNCTION_TYPE
28310 || TREE_CODE (type
) == METHOD_TYPE
))
28311 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
28313 TYPE_ATTRIBUTES (type
));
28316 darwin_set_default_type_attributes (type
);
28320 /* Return a reference suitable for calling a function with the
28321 longcall attribute. */
28324 rs6000_longcall_ref (rtx call_ref
)
28326 const char *call_name
;
28329 if (GET_CODE (call_ref
) != SYMBOL_REF
)
28332 /* System V adds '.' to the internal name, so skip them. */
28333 call_name
= XSTR (call_ref
, 0);
28334 if (*call_name
== '.')
28336 while (*call_name
== '.')
28339 node
= get_identifier (call_name
);
28340 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
28343 return force_reg (Pmode
, call_ref
);
28346 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
28347 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
28350 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
28351 struct attribute_spec.handler. */
28353 rs6000_handle_struct_attribute (tree
*node
, tree name
,
28354 tree args ATTRIBUTE_UNUSED
,
28355 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
28358 if (DECL_P (*node
))
28360 if (TREE_CODE (*node
) == TYPE_DECL
)
28361 type
= &TREE_TYPE (*node
);
28366 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
28367 || TREE_CODE (*type
) == UNION_TYPE
)))
28369 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
28370 *no_add_attrs
= true;
28373 else if ((is_attribute_p ("ms_struct", name
)
28374 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
28375 || ((is_attribute_p ("gcc_struct", name
)
28376 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
28378 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
28380 *no_add_attrs
= true;
28387 rs6000_ms_bitfield_layout_p (const_tree record_type
)
28389 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
28390 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
28391 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
28394 #ifdef USING_ELFOS_H
28396 /* A get_unnamed_section callback, used for switching to toc_section. */
28399 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
28401 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28402 && TARGET_MINIMAL_TOC
28403 && !TARGET_RELOCATABLE
)
28405 if (!toc_initialized
)
28407 toc_initialized
= 1;
28408 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
28409 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
28410 fprintf (asm_out_file
, "\t.tc ");
28411 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
28412 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
28413 fprintf (asm_out_file
, "\n");
28415 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28416 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
28417 fprintf (asm_out_file
, " = .+32768\n");
28420 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28422 else if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28423 && !TARGET_RELOCATABLE
)
28424 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
28427 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28428 if (!toc_initialized
)
28430 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
28431 fprintf (asm_out_file
, " = .+32768\n");
28432 toc_initialized
= 1;
28437 /* Implement TARGET_ASM_INIT_SECTIONS. */
28440 rs6000_elf_asm_init_sections (void)
28443 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
28446 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
28447 SDATA2_SECTION_ASM_OP
);
28450 /* Implement TARGET_SELECT_RTX_SECTION. */
28453 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
28454 unsigned HOST_WIDE_INT align
)
28456 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
28457 return toc_section
;
28459 return default_elf_select_rtx_section (mode
, x
, align
);
28462 /* For a SYMBOL_REF, set generic flags and then perform some
28463 target-specific processing.
28465 When the AIX ABI is requested on a non-AIX system, replace the
28466 function name with the real name (with a leading .) rather than the
28467 function descriptor name. This saves a lot of overriding code to
28468 read the prefixes. */
28470 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
28472 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
28474 default_encode_section_info (decl
, rtl
, first
);
28477 && TREE_CODE (decl
) == FUNCTION_DECL
28479 && DEFAULT_ABI
== ABI_AIX
)
28481 rtx sym_ref
= XEXP (rtl
, 0);
28482 size_t len
= strlen (XSTR (sym_ref
, 0));
28483 char *str
= XALLOCAVEC (char, len
+ 2);
28485 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
28486 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
28491 compare_section_name (const char *section
, const char *templ
)
28495 len
= strlen (templ
);
28496 return (strncmp (section
, templ
, len
) == 0
28497 && (section
[len
] == 0 || section
[len
] == '.'));
28501 rs6000_elf_in_small_data_p (const_tree decl
)
28503 if (rs6000_sdata
== SDATA_NONE
)
28506 /* We want to merge strings, so we never consider them small data. */
28507 if (TREE_CODE (decl
) == STRING_CST
)
28510 /* Functions are never in the small data area. */
28511 if (TREE_CODE (decl
) == FUNCTION_DECL
)
28514 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
28516 const char *section
= DECL_SECTION_NAME (decl
);
28517 if (compare_section_name (section
, ".sdata")
28518 || compare_section_name (section
, ".sdata2")
28519 || compare_section_name (section
, ".gnu.linkonce.s")
28520 || compare_section_name (section
, ".sbss")
28521 || compare_section_name (section
, ".sbss2")
28522 || compare_section_name (section
, ".gnu.linkonce.sb")
28523 || strcmp (section
, ".PPC.EMB.sdata0") == 0
28524 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
28529 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
28532 && size
<= g_switch_value
28533 /* If it's not public, and we're not going to reference it there,
28534 there's no need to put it in the small data section. */
28535 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
28542 #endif /* USING_ELFOS_H */
28544 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
28547 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
28549 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
28552 /* Do not place thread-local symbols refs in the object blocks. */
28555 rs6000_use_blocks_for_decl_p (const_tree decl
)
28557 return !DECL_THREAD_LOCAL_P (decl
);
28560 /* Return a REG that occurs in ADDR with coefficient 1.
28561 ADDR can be effectively incremented by incrementing REG.
28563 r0 is special and we must not select it as an address
28564 register by this routine since our caller will try to
28565 increment the returned register via an "la" instruction. */
28568 find_addr_reg (rtx addr
)
28570 while (GET_CODE (addr
) == PLUS
)
28572 if (GET_CODE (XEXP (addr
, 0)) == REG
28573 && REGNO (XEXP (addr
, 0)) != 0)
28574 addr
= XEXP (addr
, 0);
28575 else if (GET_CODE (XEXP (addr
, 1)) == REG
28576 && REGNO (XEXP (addr
, 1)) != 0)
28577 addr
= XEXP (addr
, 1);
28578 else if (CONSTANT_P (XEXP (addr
, 0)))
28579 addr
= XEXP (addr
, 1);
28580 else if (CONSTANT_P (XEXP (addr
, 1)))
28581 addr
= XEXP (addr
, 0);
28583 gcc_unreachable ();
28585 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
28590 rs6000_fatal_bad_address (rtx op
)
28592 fatal_insn ("bad address", op
);
28597 typedef struct branch_island_d
{
28598 tree function_name
;
28604 static vec
<branch_island
, va_gc
> *branch_islands
;
28606 /* Remember to generate a branch island for far calls to the given
28610 add_compiler_branch_island (tree label_name
, tree function_name
,
28613 branch_island bi
= {function_name
, label_name
, line_number
};
28614 vec_safe_push (branch_islands
, bi
);
28617 /* Generate far-jump branch islands for everything recorded in
28618 branch_islands. Invoked immediately after the last instruction of
28619 the epilogue has been emitted; the branch islands must be appended
28620 to, and contiguous with, the function body. Mach-O stubs are
28621 generated in machopic_output_stub(). */
28624 macho_branch_islands (void)
28628 while (!vec_safe_is_empty (branch_islands
))
28630 branch_island
*bi
= &branch_islands
->last ();
28631 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
28632 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
28633 char name_buf
[512];
28634 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
28635 if (name
[0] == '*' || name
[0] == '&')
28636 strcpy (name_buf
, name
+1);
28640 strcpy (name_buf
+1, name
);
28642 strcpy (tmp_buf
, "\n");
28643 strcat (tmp_buf
, label
);
28644 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
28645 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
28646 dbxout_stabd (N_SLINE
, bi
->line_number
);
28647 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
28650 if (TARGET_LINK_STACK
)
28653 get_ppc476_thunk_name (name
);
28654 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
28655 strcat (tmp_buf
, name
);
28656 strcat (tmp_buf
, "\n");
28657 strcat (tmp_buf
, label
);
28658 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
28662 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
28663 strcat (tmp_buf
, label
);
28664 strcat (tmp_buf
, "_pic\n");
28665 strcat (tmp_buf
, label
);
28666 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
28669 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
28670 strcat (tmp_buf
, name_buf
);
28671 strcat (tmp_buf
, " - ");
28672 strcat (tmp_buf
, label
);
28673 strcat (tmp_buf
, "_pic)\n");
28675 strcat (tmp_buf
, "\tmtlr r0\n");
28677 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
28678 strcat (tmp_buf
, name_buf
);
28679 strcat (tmp_buf
, " - ");
28680 strcat (tmp_buf
, label
);
28681 strcat (tmp_buf
, "_pic)\n");
28683 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
28687 strcat (tmp_buf
, ":\nlis r12,hi16(");
28688 strcat (tmp_buf
, name_buf
);
28689 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
28690 strcat (tmp_buf
, name_buf
);
28691 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
28693 output_asm_insn (tmp_buf
, 0);
28694 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
28695 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
28696 dbxout_stabd (N_SLINE
, bi
->line_number
);
28697 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
28698 branch_islands
->pop ();
28702 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
28703 already there or not. */
28706 no_previous_def (tree function_name
)
28711 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
28712 if (function_name
== bi
->function_name
)
28717 /* GET_PREV_LABEL gets the label name from the previous definition of
28721 get_prev_label (tree function_name
)
28726 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
28727 if (function_name
== bi
->function_name
)
28728 return bi
->label_name
;
28732 /* INSN is either a function call or a millicode call. It may have an
28733 unconditional jump in its delay slot.
28735 CALL_DEST is the routine we are calling. */
28738 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
28739 int cookie_operand_number
)
28741 static char buf
[256];
28742 if (darwin_emit_branch_islands
28743 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
28744 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
28747 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
28749 if (no_previous_def (funname
))
28751 rtx label_rtx
= gen_label_rtx ();
28752 char *label_buf
, temp_buf
[256];
28753 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
28754 CODE_LABEL_NUMBER (label_rtx
));
28755 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
28756 labelname
= get_identifier (label_buf
);
28757 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
28760 labelname
= get_prev_label (funname
);
28762 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
28763 instruction will reach 'foo', otherwise link as 'bl L42'".
28764 "L42" should be a 'branch island', that will do a far jump to
28765 'foo'. Branch islands are generated in
28766 macho_branch_islands(). */
28767 sprintf (buf
, "jbsr %%z%d,%.246s",
28768 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
28771 sprintf (buf
, "bl %%z%d", dest_operand_number
);
28775 /* Generate PIC and indirect symbol stubs. */
28778 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
28780 unsigned int length
;
28781 char *symbol_name
, *lazy_ptr_name
;
28782 char *local_label_0
;
28783 static int label
= 0;
28785 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
28786 symb
= (*targetm
.strip_name_encoding
) (symb
);
28789 length
= strlen (symb
);
28790 symbol_name
= XALLOCAVEC (char, length
+ 32);
28791 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
28793 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
28794 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
28797 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
28799 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
28803 fprintf (file
, "\t.align 5\n");
28805 fprintf (file
, "%s:\n", stub
);
28806 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28809 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
28810 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
28812 fprintf (file
, "\tmflr r0\n");
28813 if (TARGET_LINK_STACK
)
28816 get_ppc476_thunk_name (name
);
28817 fprintf (file
, "\tbl %s\n", name
);
28818 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
28822 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
28823 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
28825 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
28826 lazy_ptr_name
, local_label_0
);
28827 fprintf (file
, "\tmtlr r0\n");
28828 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
28829 (TARGET_64BIT
? "ldu" : "lwzu"),
28830 lazy_ptr_name
, local_label_0
);
28831 fprintf (file
, "\tmtctr r12\n");
28832 fprintf (file
, "\tbctr\n");
28836 fprintf (file
, "\t.align 4\n");
28838 fprintf (file
, "%s:\n", stub
);
28839 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28841 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
28842 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
28843 (TARGET_64BIT
? "ldu" : "lwzu"),
28845 fprintf (file
, "\tmtctr r12\n");
28846 fprintf (file
, "\tbctr\n");
28849 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
28850 fprintf (file
, "%s:\n", lazy_ptr_name
);
28851 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28852 fprintf (file
, "%sdyld_stub_binding_helper\n",
28853 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
28856 /* Legitimize PIC addresses. If the address is already
28857 position-independent, we return ORIG. Newly generated
28858 position-independent addresses go into a reg. This is REG if non
28859 zero, otherwise we allocate register(s) as necessary. */
28861 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
28864 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
28869 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
28870 reg
= gen_reg_rtx (Pmode
);
28872 if (GET_CODE (orig
) == CONST
)
28876 if (GET_CODE (XEXP (orig
, 0)) == PLUS
28877 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
28880 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
28882 /* Use a different reg for the intermediate value, as
28883 it will be marked UNCHANGING. */
28884 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
28885 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
28888 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
28891 if (GET_CODE (offset
) == CONST_INT
)
28893 if (SMALL_INT (offset
))
28894 return plus_constant (Pmode
, base
, INTVAL (offset
));
28895 else if (! reload_in_progress
&& ! reload_completed
)
28896 offset
= force_reg (Pmode
, offset
);
28899 rtx mem
= force_const_mem (Pmode
, orig
);
28900 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
28903 return gen_rtx_PLUS (Pmode
, base
, offset
);
28906 /* Fall back on generic machopic code. */
28907 return machopic_legitimize_pic_address (orig
, mode
, reg
);
28910 /* Output a .machine directive for the Darwin assembler, and call
28911 the generic start_file routine. */
28914 rs6000_darwin_file_start (void)
28916 static const struct
28920 HOST_WIDE_INT if_set
;
28922 { "ppc64", "ppc64", MASK_64BIT
},
28923 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
28924 { "power4", "ppc970", 0 },
28925 { "G5", "ppc970", 0 },
28926 { "7450", "ppc7450", 0 },
28927 { "7400", "ppc7400", MASK_ALTIVEC
},
28928 { "G4", "ppc7400", 0 },
28929 { "750", "ppc750", 0 },
28930 { "740", "ppc750", 0 },
28931 { "G3", "ppc750", 0 },
28932 { "604e", "ppc604e", 0 },
28933 { "604", "ppc604", 0 },
28934 { "603e", "ppc603", 0 },
28935 { "603", "ppc603", 0 },
28936 { "601", "ppc601", 0 },
28937 { NULL
, "ppc", 0 } };
28938 const char *cpu_id
= "";
28941 rs6000_file_start ();
28942 darwin_file_start ();
28944 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
28946 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
28947 cpu_id
= rs6000_default_cpu
;
28949 if (global_options_set
.x_rs6000_cpu_index
)
28950 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
28952 /* Look through the mapping array. Pick the first name that either
28953 matches the argument, has a bit set in IF_SET that is also set
28954 in the target flags, or has a NULL name. */
28957 while (mapping
[i
].arg
!= NULL
28958 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
28959 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
28962 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
28965 #endif /* TARGET_MACHO */
28969 rs6000_elf_reloc_rw_mask (void)
28973 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28979 /* Record an element in the table of global constructors. SYMBOL is
28980 a SYMBOL_REF of the function to be called; PRIORITY is a number
28981 between 0 and MAX_INIT_PRIORITY.
28983 This differs from default_named_section_asm_out_constructor in
28984 that we have special handling for -mrelocatable. */
28986 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
28988 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
28990 const char *section
= ".ctors";
28993 if (priority
!= DEFAULT_INIT_PRIORITY
)
28995 sprintf (buf
, ".ctors.%.5u",
28996 /* Invert the numbering so the linker puts us in the proper
28997 order; constructors are run from right to left, and the
28998 linker sorts in increasing order. */
28999 MAX_INIT_PRIORITY
- priority
);
29003 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
29004 assemble_align (POINTER_SIZE
);
29006 if (TARGET_RELOCATABLE
)
29008 fputs ("\t.long (", asm_out_file
);
29009 output_addr_const (asm_out_file
, symbol
);
29010 fputs (")@fixup\n", asm_out_file
);
29013 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
29016 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
29018 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
29020 const char *section
= ".dtors";
29023 if (priority
!= DEFAULT_INIT_PRIORITY
)
29025 sprintf (buf
, ".dtors.%.5u",
29026 /* Invert the numbering so the linker puts us in the proper
29027 order; constructors are run from right to left, and the
29028 linker sorts in increasing order. */
29029 MAX_INIT_PRIORITY
- priority
);
29033 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
29034 assemble_align (POINTER_SIZE
);
29036 if (TARGET_RELOCATABLE
)
29038 fputs ("\t.long (", asm_out_file
);
29039 output_addr_const (asm_out_file
, symbol
);
29040 fputs (")@fixup\n", asm_out_file
);
29043 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
29047 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
29049 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
29051 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
29052 ASM_OUTPUT_LABEL (file
, name
);
29053 fputs (DOUBLE_INT_ASM_OP
, file
);
29054 rs6000_output_function_entry (file
, name
);
29055 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
29058 fputs ("\t.size\t", file
);
29059 assemble_name (file
, name
);
29060 fputs (",24\n\t.type\t.", file
);
29061 assemble_name (file
, name
);
29062 fputs (",@function\n", file
);
29063 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
29065 fputs ("\t.globl\t.", file
);
29066 assemble_name (file
, name
);
29071 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
29072 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
29073 rs6000_output_function_entry (file
, name
);
29074 fputs (":\n", file
);
29078 if (TARGET_RELOCATABLE
29079 && !TARGET_SECURE_PLT
29080 && (get_pool_size () != 0 || crtl
->profile
)
29085 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
29087 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
29088 fprintf (file
, "\t.long ");
29089 assemble_name (file
, buf
);
29091 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
29092 assemble_name (file
, buf
);
29096 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
29097 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
29099 if (DEFAULT_ABI
== ABI_AIX
)
29101 const char *desc_name
, *orig_name
;
29103 orig_name
= (*targetm
.strip_name_encoding
) (name
);
29104 desc_name
= orig_name
;
29105 while (*desc_name
== '.')
29108 if (TREE_PUBLIC (decl
))
29109 fprintf (file
, "\t.globl %s\n", desc_name
);
29111 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
29112 fprintf (file
, "%s:\n", desc_name
);
29113 fprintf (file
, "\t.long %s\n", orig_name
);
29114 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
29115 fputs ("\t.long 0\n", file
);
29116 fprintf (file
, "\t.previous\n");
29118 ASM_OUTPUT_LABEL (file
, name
);
29121 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
29123 rs6000_elf_file_end (void)
29125 #ifdef HAVE_AS_GNU_ATTRIBUTE
29126 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
29128 if (rs6000_passes_float
)
29129 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
29130 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
29131 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
29133 if (rs6000_passes_vector
)
29134 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
29135 (TARGET_ALTIVEC_ABI
? 2
29136 : TARGET_SPE_ABI
? 3
29138 if (rs6000_returns_struct
)
29139 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
29140 aix_struct_return
? 2 : 1);
29143 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
29144 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
29145 file_end_indicate_exec_stack ();
29152 rs6000_xcoff_asm_output_anchor (rtx symbol
)
29156 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
29157 SYMBOL_REF_BLOCK_OFFSET (symbol
));
29158 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
29162 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
29164 fputs (GLOBAL_ASM_OP
, stream
);
29165 RS6000_OUTPUT_BASENAME (stream
, name
);
29166 putc ('\n', stream
);
29169 /* A get_unnamed_decl callback, used for read-only sections. PTR
29170 points to the section string variable. */
29173 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
29175 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
29176 *(const char *const *) directive
,
29177 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
29180 /* Likewise for read-write sections. */
29183 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
29185 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
29186 *(const char *const *) directive
,
29187 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
29191 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
29193 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
29194 *(const char *const *) directive
,
29195 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
29198 /* A get_unnamed_section callback, used for switching to toc_section. */
29201 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
29203 if (TARGET_MINIMAL_TOC
)
29205 /* toc_section is always selected at least once from
29206 rs6000_xcoff_file_start, so this is guaranteed to
29207 always be defined once and only once in each file. */
29208 if (!toc_initialized
)
29210 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
29211 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
29212 toc_initialized
= 1;
29214 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
29215 (TARGET_32BIT
? "" : ",3"));
29218 fputs ("\t.toc\n", asm_out_file
);
29221 /* Implement TARGET_ASM_INIT_SECTIONS. */
29224 rs6000_xcoff_asm_init_sections (void)
29226 read_only_data_section
29227 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
29228 &xcoff_read_only_section_name
);
29230 private_data_section
29231 = get_unnamed_section (SECTION_WRITE
,
29232 rs6000_xcoff_output_readwrite_section_asm_op
,
29233 &xcoff_private_data_section_name
);
29236 = get_unnamed_section (SECTION_TLS
,
29237 rs6000_xcoff_output_tls_section_asm_op
,
29238 &xcoff_tls_data_section_name
);
29240 tls_private_data_section
29241 = get_unnamed_section (SECTION_TLS
,
29242 rs6000_xcoff_output_tls_section_asm_op
,
29243 &xcoff_private_data_section_name
);
29245 read_only_private_data_section
29246 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
29247 &xcoff_private_data_section_name
);
29250 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
29252 readonly_data_section
= read_only_data_section
;
29253 exception_section
= data_section
;
29257 rs6000_xcoff_reloc_rw_mask (void)
29263 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
29264 tree decl ATTRIBUTE_UNUSED
)
29267 static const char * const suffix
[4] = { "PR", "RO", "RW", "TL" };
29269 if (flags
& SECTION_CODE
)
29271 else if (flags
& SECTION_TLS
)
29273 else if (flags
& SECTION_WRITE
)
29278 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
29279 (flags
& SECTION_CODE
) ? "." : "",
29280 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
29283 #define IN_NAMED_SECTION(DECL) \
29284 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
29285 && DECL_SECTION_NAME (DECL) != NULL)
29288 rs6000_xcoff_select_section (tree decl
, int reloc
,
29289 unsigned HOST_WIDE_INT align
)
29291 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
29293 if (align
> BIGGEST_ALIGNMENT
)
29295 resolve_unique_section (decl
, reloc
, true);
29296 if (IN_NAMED_SECTION (decl
))
29297 return get_named_section (decl
, NULL
, reloc
);
29300 if (decl_readonly_section (decl
, reloc
))
29302 if (TREE_PUBLIC (decl
))
29303 return read_only_data_section
;
29305 return read_only_private_data_section
;
29310 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
29312 if (TREE_PUBLIC (decl
))
29313 return tls_data_section
;
29314 else if (bss_initializer_p (decl
))
29316 /* Convert to COMMON to emit in BSS. */
29317 DECL_COMMON (decl
) = 1;
29318 return tls_comm_section
;
29321 return tls_private_data_section
;
29325 if (TREE_PUBLIC (decl
))
29326 return data_section
;
29328 return private_data_section
;
29333 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
29337 /* Use select_section for private data and uninitialized data with
29338 alignment <= BIGGEST_ALIGNMENT. */
29339 if (!TREE_PUBLIC (decl
)
29340 || DECL_COMMON (decl
)
29341 || (DECL_INITIAL (decl
) == NULL_TREE
29342 && DECL_ALIGN (decl
) <= BIGGEST_ALIGNMENT
)
29343 || DECL_INITIAL (decl
) == error_mark_node
29344 || (flag_zero_initialized_in_bss
29345 && initializer_zerop (DECL_INITIAL (decl
))))
29348 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
29349 name
= (*targetm
.strip_name_encoding
) (name
);
29350 set_decl_section_name (decl
, name
);
29353 /* Select section for constant in constant pool.
29355 On RS/6000, all constants are in the private read-only data area.
29356 However, if this is being placed in the TOC it must be output as a
29360 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
29361 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
29363 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
29364 return toc_section
;
29366 return read_only_private_data_section
;
29369 /* Remove any trailing [DS] or the like from the symbol name. */
29371 static const char *
29372 rs6000_xcoff_strip_name_encoding (const char *name
)
29377 len
= strlen (name
);
29378 if (name
[len
- 1] == ']')
29379 return ggc_alloc_string (name
, len
- 4);
29384 /* Section attributes. AIX is always PIC. */
29386 static unsigned int
29387 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
29389 unsigned int align
;
29390 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
29392 /* Align to at least UNIT size. */
29393 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
29394 align
= MIN_UNITS_PER_WORD
;
29396 /* Increase alignment of large objects if not already stricter. */
29397 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
29398 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
29399 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
29401 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
29404 /* Output at beginning of assembler file.
29406 Initialize the section names for the RS/6000 at this point.
29408 Specify filename, including full path, to assembler.
29410 We want to go into the TOC section so at least one .toc will be emitted.
29411 Also, in order to output proper .bs/.es pairs, we need at least one static
29412 [RW] section emitted.
29414 Finally, declare mcount when profiling to make the assembler happy. */
29417 rs6000_xcoff_file_start (void)
29419 rs6000_gen_section_name (&xcoff_bss_section_name
,
29420 main_input_filename
, ".bss_");
29421 rs6000_gen_section_name (&xcoff_private_data_section_name
,
29422 main_input_filename
, ".rw_");
29423 rs6000_gen_section_name (&xcoff_read_only_section_name
,
29424 main_input_filename
, ".ro_");
29425 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
29426 main_input_filename
, ".tls_");
29427 rs6000_gen_section_name (&xcoff_tbss_section_name
,
29428 main_input_filename
, ".tbss_[UL]");
29430 fputs ("\t.file\t", asm_out_file
);
29431 output_quoted_string (asm_out_file
, main_input_filename
);
29432 fputc ('\n', asm_out_file
);
29433 if (write_symbols
!= NO_DEBUG
)
29434 switch_to_section (private_data_section
);
29435 switch_to_section (text_section
);
29437 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
29438 rs6000_file_start ();
29441 /* Output at end of assembler file.
29442 On the RS/6000, referencing data should automatically pull in text. */
29445 rs6000_xcoff_file_end (void)
29447 switch_to_section (text_section
);
29448 fputs ("_section_.text:\n", asm_out_file
);
29449 switch_to_section (data_section
);
29450 fputs (TARGET_32BIT
29451 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
29455 /* This macro produces the initial definition of a function name.
29456 On the RS/6000, we need to place an extra '.' in the function name and
29457 output the function descriptor.
29458 Dollar signs are converted to underscores.
29460 The csect for the function will have already been created when
29461 text_section was selected. We do have to go back to that csect, however.
29463 The third and fourth parameters to the .function pseudo-op (16 and 044)
29464 are placeholders which no longer have any use. */
29467 rs6000_xcoff_declare_function_name (FILE *file
, const char *name
, tree decl
)
29469 char *buffer
= (char *) alloca (strlen (name
) + 1);
29471 int dollar_inside
= 0;
29472 strcpy (buffer
, name
);
29473 p
= strchr (buffer
, '$');
29477 p
= strchr (p
+ 1, '$');
29479 if (TREE_PUBLIC (decl
))
29481 if (!RS6000_WEAK
|| !DECL_WEAK (decl
))
29483 if (dollar_inside
) {
29484 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
29485 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
29487 fputs ("\t.globl .", file
);
29488 RS6000_OUTPUT_BASENAME (file
, buffer
);
29494 if (dollar_inside
) {
29495 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
29496 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
29498 fputs ("\t.lglobl .", file
);
29499 RS6000_OUTPUT_BASENAME (file
, buffer
);
29502 fputs ("\t.csect ", file
);
29503 RS6000_OUTPUT_BASENAME (file
, buffer
);
29504 fputs (TARGET_32BIT
? "[DS]\n" : "[DS],3\n", file
);
29505 RS6000_OUTPUT_BASENAME (file
, buffer
);
29506 fputs (":\n", file
);
29507 fputs (TARGET_32BIT
? "\t.long ." : "\t.llong .", file
);
29508 RS6000_OUTPUT_BASENAME (file
, buffer
);
29509 fputs (", TOC[tc0], 0\n", file
);
29511 switch_to_section (function_section (decl
));
29513 RS6000_OUTPUT_BASENAME (file
, buffer
);
29514 fputs (":\n", file
);
29515 if (write_symbols
!= NO_DEBUG
&& !DECL_IGNORED_P (decl
))
29516 xcoffout_declare_function (file
, decl
, buffer
);
29522 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
29527 default_encode_section_info (decl
, rtl
, first
);
29529 /* Careful not to prod global register variables. */
29532 symbol
= XEXP (rtl
, 0);
29533 if (GET_CODE (symbol
) != SYMBOL_REF
)
29536 flags
= SYMBOL_REF_FLAGS (symbol
);
29538 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
29539 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
29541 SYMBOL_REF_FLAGS (symbol
) = flags
;
29543 #endif /* HAVE_AS_TLS */
29544 #endif /* TARGET_XCOFF */
29546 /* Compute a (partial) cost for rtx X. Return true if the complete
29547 cost has been computed, and false if subexpressions should be
29548 scanned. In either case, *TOTAL contains the cost result. */
29551 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
29552 int *total
, bool speed
)
29554 enum machine_mode mode
= GET_MODE (x
);
29558 /* On the RS/6000, if it is valid in the insn, it is free. */
29560 if (((outer_code
== SET
29561 || outer_code
== PLUS
29562 || outer_code
== MINUS
)
29563 && (satisfies_constraint_I (x
)
29564 || satisfies_constraint_L (x
)))
29565 || (outer_code
== AND
29566 && (satisfies_constraint_K (x
)
29568 ? satisfies_constraint_L (x
)
29569 : satisfies_constraint_J (x
))
29570 || mask_operand (x
, mode
)
29572 && mask64_operand (x
, DImode
))))
29573 || ((outer_code
== IOR
|| outer_code
== XOR
)
29574 && (satisfies_constraint_K (x
)
29576 ? satisfies_constraint_L (x
)
29577 : satisfies_constraint_J (x
))))
29578 || outer_code
== ASHIFT
29579 || outer_code
== ASHIFTRT
29580 || outer_code
== LSHIFTRT
29581 || outer_code
== ROTATE
29582 || outer_code
== ROTATERT
29583 || outer_code
== ZERO_EXTRACT
29584 || (outer_code
== MULT
29585 && satisfies_constraint_I (x
))
29586 || ((outer_code
== DIV
|| outer_code
== UDIV
29587 || outer_code
== MOD
|| outer_code
== UMOD
)
29588 && exact_log2 (INTVAL (x
)) >= 0)
29589 || (outer_code
== COMPARE
29590 && (satisfies_constraint_I (x
)
29591 || satisfies_constraint_K (x
)))
29592 || ((outer_code
== EQ
|| outer_code
== NE
)
29593 && (satisfies_constraint_I (x
)
29594 || satisfies_constraint_K (x
)
29596 ? satisfies_constraint_L (x
)
29597 : satisfies_constraint_J (x
))))
29598 || (outer_code
== GTU
29599 && satisfies_constraint_I (x
))
29600 || (outer_code
== LTU
29601 && satisfies_constraint_P (x
)))
29606 else if ((outer_code
== PLUS
29607 && reg_or_add_cint_operand (x
, VOIDmode
))
29608 || (outer_code
== MINUS
29609 && reg_or_sub_cint_operand (x
, VOIDmode
))
29610 || ((outer_code
== SET
29611 || outer_code
== IOR
29612 || outer_code
== XOR
)
29614 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
29616 *total
= COSTS_N_INSNS (1);
29622 case CONST_WIDE_INT
:
29627 /* When optimizing for size, MEM should be slightly more expensive
29628 than generating address, e.g., (plus (reg) (const)).
29629 L1 cache latency is about two instructions. */
29630 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
29639 if (FLOAT_MODE_P (mode
))
29640 *total
= rs6000_cost
->fp
;
29642 *total
= COSTS_N_INSNS (1);
29646 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
29647 && satisfies_constraint_I (XEXP (x
, 1)))
29649 if (INTVAL (XEXP (x
, 1)) >= -256
29650 && INTVAL (XEXP (x
, 1)) <= 255)
29651 *total
= rs6000_cost
->mulsi_const9
;
29653 *total
= rs6000_cost
->mulsi_const
;
29655 else if (mode
== SFmode
)
29656 *total
= rs6000_cost
->fp
;
29657 else if (FLOAT_MODE_P (mode
))
29658 *total
= rs6000_cost
->dmul
;
29659 else if (mode
== DImode
)
29660 *total
= rs6000_cost
->muldi
;
29662 *total
= rs6000_cost
->mulsi
;
29666 if (mode
== SFmode
)
29667 *total
= rs6000_cost
->fp
;
29669 *total
= rs6000_cost
->dmul
;
29674 if (FLOAT_MODE_P (mode
))
29676 *total
= mode
== DFmode
? rs6000_cost
->ddiv
29677 : rs6000_cost
->sdiv
;
29684 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
29685 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
29687 if (code
== DIV
|| code
== MOD
)
29689 *total
= COSTS_N_INSNS (2);
29692 *total
= COSTS_N_INSNS (1);
29696 if (GET_MODE (XEXP (x
, 1)) == DImode
)
29697 *total
= rs6000_cost
->divdi
;
29699 *total
= rs6000_cost
->divsi
;
29701 /* Add in shift and subtract for MOD. */
29702 if (code
== MOD
|| code
== UMOD
)
29703 *total
+= COSTS_N_INSNS (2);
29708 *total
= COSTS_N_INSNS (4);
29712 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
29716 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
29720 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
29732 *total
= COSTS_N_INSNS (1);
29740 /* Handle mul_highpart. */
29741 if (outer_code
== TRUNCATE
29742 && GET_CODE (XEXP (x
, 0)) == MULT
)
29744 if (mode
== DImode
)
29745 *total
= rs6000_cost
->muldi
;
29747 *total
= rs6000_cost
->mulsi
;
29750 else if (outer_code
== AND
)
29753 *total
= COSTS_N_INSNS (1);
29758 if (GET_CODE (XEXP (x
, 0)) == MEM
)
29761 *total
= COSTS_N_INSNS (1);
29767 if (!FLOAT_MODE_P (mode
))
29769 *total
= COSTS_N_INSNS (1);
29775 case UNSIGNED_FLOAT
:
29778 case FLOAT_TRUNCATE
:
29779 *total
= rs6000_cost
->fp
;
29783 if (mode
== DFmode
)
29786 *total
= rs6000_cost
->fp
;
29790 switch (XINT (x
, 1))
29793 *total
= rs6000_cost
->fp
;
29805 *total
= COSTS_N_INSNS (1);
29808 else if (FLOAT_MODE_P (mode
)
29809 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
29811 *total
= rs6000_cost
->fp
;
29819 /* Carry bit requires mode == Pmode.
29820 NEG or PLUS already counted so only add one. */
29822 && (outer_code
== NEG
|| outer_code
== PLUS
))
29824 *total
= COSTS_N_INSNS (1);
29827 if (outer_code
== SET
)
29829 if (XEXP (x
, 1) == const0_rtx
)
29831 if (TARGET_ISEL
&& !TARGET_MFCRF
)
29832 *total
= COSTS_N_INSNS (8);
29834 *total
= COSTS_N_INSNS (2);
29837 else if (mode
== Pmode
)
29839 *total
= COSTS_N_INSNS (3);
29848 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
29850 if (TARGET_ISEL
&& !TARGET_MFCRF
)
29851 *total
= COSTS_N_INSNS (8);
29853 *total
= COSTS_N_INSNS (2);
29857 if (outer_code
== COMPARE
)
29871 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
29874 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
29877 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
29880 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
29881 "opno = %d, total = %d, speed = %s, x:\n",
29882 ret
? "complete" : "scan inner",
29883 GET_RTX_NAME (code
),
29884 GET_RTX_NAME (outer_code
),
29887 speed
? "true" : "false");
29894 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
29897 rs6000_debug_address_cost (rtx x
, enum machine_mode mode
,
29898 addr_space_t as
, bool speed
)
29900 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
29902 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
29903 ret
, speed
? "true" : "false");
29910 /* A C expression returning the cost of moving data from a register of class
29911 CLASS1 to one of CLASS2. */
29914 rs6000_register_move_cost (enum machine_mode mode
,
29915 reg_class_t from
, reg_class_t to
)
29919 if (TARGET_DEBUG_COST
)
29922 /* Moves from/to GENERAL_REGS. */
29923 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
29924 || reg_classes_intersect_p (from
, GENERAL_REGS
))
29926 reg_class_t rclass
= from
;
29928 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
29931 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
29932 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
29933 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
29935 /* It's more expensive to move CR_REGS than CR0_REGS because of the
29937 else if (rclass
== CR_REGS
)
29940 /* For those processors that have slow LR/CTR moves, make them more
29941 expensive than memory in order to bias spills to memory .*/
29942 else if ((rs6000_cpu
== PROCESSOR_POWER6
29943 || rs6000_cpu
== PROCESSOR_POWER7
29944 || rs6000_cpu
== PROCESSOR_POWER8
)
29945 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
29946 ret
= 6 * hard_regno_nregs
[0][mode
];
29949 /* A move will cost one instruction per GPR moved. */
29950 ret
= 2 * hard_regno_nregs
[0][mode
];
29953 /* If we have VSX, we can easily move between FPR or Altivec registers. */
29954 else if (VECTOR_MEM_VSX_P (mode
)
29955 && reg_classes_intersect_p (to
, VSX_REGS
)
29956 && reg_classes_intersect_p (from
, VSX_REGS
))
29957 ret
= 2 * hard_regno_nregs
[32][mode
];
29959 /* Moving between two similar registers is just one instruction. */
29960 else if (reg_classes_intersect_p (to
, from
))
29961 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
29963 /* Everything else has to go through GENERAL_REGS. */
29965 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
29966 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
29968 if (TARGET_DEBUG_COST
)
29970 if (dbg_cost_ctrl
== 1)
29972 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
29973 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
29974 reg_class_names
[to
]);
29981 /* A C expressions returning the cost of moving data of MODE from a register to
29985 rs6000_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
29986 bool in ATTRIBUTE_UNUSED
)
29990 if (TARGET_DEBUG_COST
)
29993 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
29994 ret
= 4 * hard_regno_nregs
[0][mode
];
29995 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
29996 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
29997 ret
= 4 * hard_regno_nregs
[32][mode
];
29998 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
29999 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
30001 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
30003 if (TARGET_DEBUG_COST
)
30005 if (dbg_cost_ctrl
== 1)
30007 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
30008 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
30015 /* Returns a code for a target-specific builtin that implements
30016 reciprocal of the function, or NULL_TREE if not available. */
30019 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
30020 bool sqrt ATTRIBUTE_UNUSED
)
30022 if (optimize_insn_for_size_p ())
30028 case VSX_BUILTIN_XVSQRTDP
:
30029 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
30032 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
30034 case VSX_BUILTIN_XVSQRTSP
:
30035 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
30038 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
30047 case BUILT_IN_SQRT
:
30048 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
30051 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
30053 case BUILT_IN_SQRTF
:
30054 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
30057 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
30064 /* Load up a constant. If the mode is a vector mode, splat the value across
30065 all of the vector elements. */
30068 rs6000_load_constant_and_splat (enum machine_mode mode
, REAL_VALUE_TYPE dconst
)
30072 if (mode
== SFmode
|| mode
== DFmode
)
30074 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
30075 reg
= force_reg (mode
, d
);
30077 else if (mode
== V4SFmode
)
30079 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
30080 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
30081 reg
= gen_reg_rtx (mode
);
30082 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
30084 else if (mode
== V2DFmode
)
30086 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
30087 rtvec v
= gen_rtvec (2, d
, d
);
30088 reg
= gen_reg_rtx (mode
);
30089 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
30092 gcc_unreachable ();
30097 /* Generate an FMA instruction. */
30100 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
30102 enum machine_mode mode
= GET_MODE (target
);
30105 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
30106 gcc_assert (dst
!= NULL
);
30109 emit_move_insn (target
, dst
);
30112 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
30115 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
30117 enum machine_mode mode
= GET_MODE (target
);
30120 /* Altivec does not support fms directly;
30121 generate in terms of fma in that case. */
30122 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
30123 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
30126 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
30127 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
30129 gcc_assert (dst
!= NULL
);
30132 emit_move_insn (target
, dst
);
30135 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
30138 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
30140 enum machine_mode mode
= GET_MODE (dst
);
30143 /* This is a tad more complicated, since the fnma_optab is for
30144 a different expression: fma(-m1, m2, a), which is the same
30145 thing except in the case of signed zeros.
30147 Fortunately we know that if FMA is supported that FNMSUB is
30148 also supported in the ISA. Just expand it directly. */
30150 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
30152 r
= gen_rtx_NEG (mode
, a
);
30153 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
30154 r
= gen_rtx_NEG (mode
, r
);
30155 emit_insn (gen_rtx_SET (VOIDmode
, dst
, r
));
30158 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
30159 add a reg_note saying that this was a division. Support both scalar and
30160 vector divide. Assumes no trapping math and finite arguments. */
30163 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
30165 enum machine_mode mode
= GET_MODE (dst
);
30166 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
30169 /* Low precision estimates guarantee 5 bits of accuracy. High
30170 precision estimates guarantee 14 bits of accuracy. SFmode
30171 requires 23 bits of accuracy. DFmode requires 52 bits of
30172 accuracy. Each pass at least doubles the accuracy, leading
30173 to the following. */
30174 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
30175 if (mode
== DFmode
|| mode
== V2DFmode
)
30178 enum insn_code code
= optab_handler (smul_optab
, mode
);
30179 insn_gen_fn gen_mul
= GEN_FCN (code
);
30181 gcc_assert (code
!= CODE_FOR_nothing
);
30183 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
30185 /* x0 = 1./d estimate */
30186 x0
= gen_reg_rtx (mode
);
30187 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
30188 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
30191 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
30194 /* e0 = 1. - d * x0 */
30195 e0
= gen_reg_rtx (mode
);
30196 rs6000_emit_nmsub (e0
, d
, x0
, one
);
30198 /* x1 = x0 + e0 * x0 */
30199 x1
= gen_reg_rtx (mode
);
30200 rs6000_emit_madd (x1
, e0
, x0
, x0
);
30202 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
30203 ++i
, xprev
= xnext
, eprev
= enext
) {
30205 /* enext = eprev * eprev */
30206 enext
= gen_reg_rtx (mode
);
30207 emit_insn (gen_mul (enext
, eprev
, eprev
));
30209 /* xnext = xprev + enext * xprev */
30210 xnext
= gen_reg_rtx (mode
);
30211 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
30217 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
30219 /* u = n * xprev */
30220 u
= gen_reg_rtx (mode
);
30221 emit_insn (gen_mul (u
, n
, xprev
));
30223 /* v = n - (d * u) */
30224 v
= gen_reg_rtx (mode
);
30225 rs6000_emit_nmsub (v
, d
, u
, n
);
30227 /* dst = (v * xprev) + u */
30228 rs6000_emit_madd (dst
, v
, xprev
, u
);
30231 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
30234 /* Newton-Raphson approximation of single/double-precision floating point
30235 rsqrt. Assumes no trapping math and finite arguments. */
30238 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
30240 enum machine_mode mode
= GET_MODE (src
);
30241 rtx x0
= gen_reg_rtx (mode
);
30242 rtx y
= gen_reg_rtx (mode
);
30244 /* Low precision estimates guarantee 5 bits of accuracy. High
30245 precision estimates guarantee 14 bits of accuracy. SFmode
30246 requires 23 bits of accuracy. DFmode requires 52 bits of
30247 accuracy. Each pass at least doubles the accuracy, leading
30248 to the following. */
30249 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
30250 if (mode
== DFmode
|| mode
== V2DFmode
)
30253 REAL_VALUE_TYPE dconst3_2
;
30256 enum insn_code code
= optab_handler (smul_optab
, mode
);
30257 insn_gen_fn gen_mul
= GEN_FCN (code
);
30259 gcc_assert (code
!= CODE_FOR_nothing
);
30261 /* Load up the constant 1.5 either as a scalar, or as a vector. */
30262 real_from_integer (&dconst3_2
, VOIDmode
, 3, SIGNED
);
30263 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
30265 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
30267 /* x0 = rsqrt estimate */
30268 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
30269 gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
30272 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
30273 rs6000_emit_msub (y
, src
, halfthree
, src
);
30275 for (i
= 0; i
< passes
; i
++)
30277 rtx x1
= gen_reg_rtx (mode
);
30278 rtx u
= gen_reg_rtx (mode
);
30279 rtx v
= gen_reg_rtx (mode
);
30281 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
30282 emit_insn (gen_mul (u
, x0
, x0
));
30283 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
30284 emit_insn (gen_mul (x1
, x0
, v
));
30288 emit_move_insn (dst
, x0
);
30292 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
30293 (Power7) targets. DST is the target, and SRC is the argument operand. */
30296 rs6000_emit_popcount (rtx dst
, rtx src
)
30298 enum machine_mode mode
= GET_MODE (dst
);
30301 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
30302 if (TARGET_POPCNTD
)
30304 if (mode
== SImode
)
30305 emit_insn (gen_popcntdsi2 (dst
, src
));
30307 emit_insn (gen_popcntddi2 (dst
, src
));
30311 tmp1
= gen_reg_rtx (mode
);
30313 if (mode
== SImode
)
30315 emit_insn (gen_popcntbsi2 (tmp1
, src
));
30316 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
30318 tmp2
= force_reg (SImode
, tmp2
);
30319 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
30323 emit_insn (gen_popcntbdi2 (tmp1
, src
));
30324 tmp2
= expand_mult (DImode
, tmp1
,
30325 GEN_INT ((HOST_WIDE_INT
)
30326 0x01010101 << 32 | 0x01010101),
30328 tmp2
= force_reg (DImode
, tmp2
);
30329 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
30334 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
30335 target, and SRC is the argument operand. */
30338 rs6000_emit_parity (rtx dst
, rtx src
)
30340 enum machine_mode mode
= GET_MODE (dst
);
30343 tmp
= gen_reg_rtx (mode
);
30345 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
30348 if (mode
== SImode
)
30350 emit_insn (gen_popcntbsi2 (tmp
, src
));
30351 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
30355 emit_insn (gen_popcntbdi2 (tmp
, src
));
30356 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
30361 if (mode
== SImode
)
30363 /* Is mult+shift >= shift+xor+shift+xor? */
30364 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
30366 rtx tmp1
, tmp2
, tmp3
, tmp4
;
30368 tmp1
= gen_reg_rtx (SImode
);
30369 emit_insn (gen_popcntbsi2 (tmp1
, src
));
30371 tmp2
= gen_reg_rtx (SImode
);
30372 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
30373 tmp3
= gen_reg_rtx (SImode
);
30374 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
30376 tmp4
= gen_reg_rtx (SImode
);
30377 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
30378 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
30381 rs6000_emit_popcount (tmp
, src
);
30382 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
30386 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
30387 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
30389 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
30391 tmp1
= gen_reg_rtx (DImode
);
30392 emit_insn (gen_popcntbdi2 (tmp1
, src
));
30394 tmp2
= gen_reg_rtx (DImode
);
30395 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
30396 tmp3
= gen_reg_rtx (DImode
);
30397 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
30399 tmp4
= gen_reg_rtx (DImode
);
30400 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
30401 tmp5
= gen_reg_rtx (DImode
);
30402 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
30404 tmp6
= gen_reg_rtx (DImode
);
30405 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
30406 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
30409 rs6000_emit_popcount (tmp
, src
);
30410 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
30414 /* Expand an Altivec constant permutation for little endian mode.
30415 There are two issues: First, the two input operands must be
30416 swapped so that together they form a double-wide array in LE
30417 order. Second, the vperm instruction has surprising behavior
30418 in LE mode: it interprets the elements of the source vectors
30419 in BE mode ("left to right") and interprets the elements of
30420 the destination vector in LE mode ("right to left"). To
30421 correct for this, we must subtract each element of the permute
30422 control vector from 31.
30424 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
30425 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
30426 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
30427 serve as the permute control vector. Then, in BE mode,
30431 places the desired result in vr9. However, in LE mode the
30432 vector contents will be
30434 vr10 = 00000003 00000002 00000001 00000000
30435 vr11 = 00000007 00000006 00000005 00000004
30437 The result of the vperm using the same permute control vector is
30439 vr9 = 05000000 07000000 01000000 03000000
30441 That is, the leftmost 4 bytes of vr10 are interpreted as the
30442 source for the rightmost 4 bytes of vr9, and so on.
30444 If we change the permute control vector to
30446 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
30454 vr9 = 00000006 00000004 00000002 00000000. */
30457 altivec_expand_vec_perm_const_le (rtx operands
[4])
30461 rtx constv
, unspec
;
30462 rtx target
= operands
[0];
30463 rtx op0
= operands
[1];
30464 rtx op1
= operands
[2];
30465 rtx sel
= operands
[3];
30467 /* Unpack and adjust the constant selector. */
30468 for (i
= 0; i
< 16; ++i
)
30470 rtx e
= XVECEXP (sel
, 0, i
);
30471 unsigned int elt
= 31 - (INTVAL (e
) & 31);
30472 perm
[i
] = GEN_INT (elt
);
30475 /* Expand to a permute, swapping the inputs and using the
30476 adjusted selector. */
30478 op0
= force_reg (V16QImode
, op0
);
30480 op1
= force_reg (V16QImode
, op1
);
30482 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
30483 constv
= force_reg (V16QImode
, constv
);
30484 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
30486 if (!REG_P (target
))
30488 rtx tmp
= gen_reg_rtx (V16QImode
);
30489 emit_move_insn (tmp
, unspec
);
30493 emit_move_insn (target
, unspec
);
30496 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
30497 permute control vector. But here it's not a constant, so we must
30498 generate a vector NAND or NOR to do the adjustment. */
30501 altivec_expand_vec_perm_le (rtx operands
[4])
30503 rtx notx
, iorx
, unspec
;
30504 rtx target
= operands
[0];
30505 rtx op0
= operands
[1];
30506 rtx op1
= operands
[2];
30507 rtx sel
= operands
[3];
30509 rtx norreg
= gen_reg_rtx (V16QImode
);
30510 enum machine_mode mode
= GET_MODE (target
);
30512 /* Get everything in regs so the pattern matches. */
30514 op0
= force_reg (mode
, op0
);
30516 op1
= force_reg (mode
, op1
);
30518 sel
= force_reg (V16QImode
, sel
);
30519 if (!REG_P (target
))
30520 tmp
= gen_reg_rtx (mode
);
30522 /* Invert the selector with a VNAND if available, else a VNOR.
30523 The VNAND is preferred for future fusion opportunities. */
30524 notx
= gen_rtx_NOT (V16QImode
, sel
);
30525 iorx
= (TARGET_P8_VECTOR
30526 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
30527 : gen_rtx_AND (V16QImode
, notx
, notx
));
30528 emit_insn (gen_rtx_SET (VOIDmode
, norreg
, iorx
));
30530 /* Permute with operands reversed and adjusted selector. */
30531 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, norreg
),
30534 /* Copy into target, possibly by way of a register. */
30535 if (!REG_P (target
))
30537 emit_move_insn (tmp
, unspec
);
30541 emit_move_insn (target
, unspec
);
30544 /* Expand an Altivec constant permutation. Return true if we match
30545 an efficient implementation; false to fall back to VPERM. */
30548 altivec_expand_vec_perm_const (rtx operands
[4])
30550 struct altivec_perm_insn
{
30551 HOST_WIDE_INT mask
;
30552 enum insn_code impl
;
30553 unsigned char perm
[16];
30555 static const struct altivec_perm_insn patterns
[] = {
30556 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum_direct
,
30557 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
30558 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum_direct
,
30559 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
30560 { OPTION_MASK_ALTIVEC
,
30561 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb_direct
30562 : CODE_FOR_altivec_vmrglb_direct
),
30563 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
30564 { OPTION_MASK_ALTIVEC
,
30565 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh_direct
30566 : CODE_FOR_altivec_vmrglh_direct
),
30567 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
30568 { OPTION_MASK_ALTIVEC
,
30569 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw_direct
30570 : CODE_FOR_altivec_vmrglw_direct
),
30571 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
30572 { OPTION_MASK_ALTIVEC
,
30573 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb_direct
30574 : CODE_FOR_altivec_vmrghb_direct
),
30575 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
30576 { OPTION_MASK_ALTIVEC
,
30577 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh_direct
30578 : CODE_FOR_altivec_vmrghh_direct
),
30579 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
30580 { OPTION_MASK_ALTIVEC
,
30581 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw_direct
30582 : CODE_FOR_altivec_vmrghw_direct
),
30583 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
30584 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
30585 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
30586 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
30587 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
30590 unsigned int i
, j
, elt
, which
;
30591 unsigned char perm
[16];
30592 rtx target
, op0
, op1
, sel
, x
;
30595 target
= operands
[0];
30600 /* Unpack the constant selector. */
30601 for (i
= which
= 0; i
< 16; ++i
)
30603 rtx e
= XVECEXP (sel
, 0, i
);
30604 elt
= INTVAL (e
) & 31;
30605 which
|= (elt
< 16 ? 1 : 2);
30609 /* Simplify the constant selector based on operands. */
30613 gcc_unreachable ();
30617 if (!rtx_equal_p (op0
, op1
))
30622 for (i
= 0; i
< 16; ++i
)
30634 /* Look for splat patterns. */
30639 for (i
= 0; i
< 16; ++i
)
30640 if (perm
[i
] != elt
)
30644 if (!BYTES_BIG_ENDIAN
)
30646 emit_insn (gen_altivec_vspltb_direct (target
, op0
, GEN_INT (elt
)));
30652 for (i
= 0; i
< 16; i
+= 2)
30653 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
30657 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
30658 x
= gen_reg_rtx (V8HImode
);
30659 emit_insn (gen_altivec_vsplth_direct (x
, gen_lowpart (V8HImode
, op0
),
30661 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
30668 for (i
= 0; i
< 16; i
+= 4)
30670 || perm
[i
+ 1] != elt
+ 1
30671 || perm
[i
+ 2] != elt
+ 2
30672 || perm
[i
+ 3] != elt
+ 3)
30676 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
30677 x
= gen_reg_rtx (V4SImode
);
30678 emit_insn (gen_altivec_vspltw_direct (x
, gen_lowpart (V4SImode
, op0
),
30680 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
30686 /* Look for merge and pack patterns. */
30687 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
30691 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
30694 elt
= patterns
[j
].perm
[0];
30695 if (perm
[0] == elt
)
30697 else if (perm
[0] == elt
+ 16)
30701 for (i
= 1; i
< 16; ++i
)
30703 elt
= patterns
[j
].perm
[i
];
30705 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
30706 else if (one_vec
&& elt
>= 16)
30708 if (perm
[i
] != elt
)
30713 enum insn_code icode
= patterns
[j
].impl
;
30714 enum machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
30715 enum machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
30717 /* For little-endian, don't use vpkuwum and vpkuhum if the
30718 underlying vector type is not V4SI and V8HI, respectively.
30719 For example, using vpkuwum with a V8HI picks up the even
30720 halfwords (BE numbering) when the even halfwords (LE
30721 numbering) are what we need. */
30722 if (!BYTES_BIG_ENDIAN
30723 && icode
== CODE_FOR_altivec_vpkuwum_direct
30724 && ((GET_CODE (op0
) == REG
30725 && GET_MODE (op0
) != V4SImode
)
30726 || (GET_CODE (op0
) == SUBREG
30727 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
30729 if (!BYTES_BIG_ENDIAN
30730 && icode
== CODE_FOR_altivec_vpkuhum_direct
30731 && ((GET_CODE (op0
) == REG
30732 && GET_MODE (op0
) != V8HImode
)
30733 || (GET_CODE (op0
) == SUBREG
30734 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
30737 /* For little-endian, the two input operands must be swapped
30738 (or swapped back) to ensure proper right-to-left numbering
30740 if (swapped
^ !BYTES_BIG_ENDIAN
)
30741 x
= op0
, op0
= op1
, op1
= x
;
30742 if (imode
!= V16QImode
)
30744 op0
= gen_lowpart (imode
, op0
);
30745 op1
= gen_lowpart (imode
, op1
);
30747 if (omode
== V16QImode
)
30750 x
= gen_reg_rtx (omode
);
30751 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
30752 if (omode
!= V16QImode
)
30753 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
30758 if (!BYTES_BIG_ENDIAN
)
30760 altivec_expand_vec_perm_const_le (operands
);
30767 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
30768 Return true if we match an efficient implementation. */
30771 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
30772 unsigned char perm0
, unsigned char perm1
)
30776 /* If both selectors come from the same operand, fold to single op. */
30777 if ((perm0
& 2) == (perm1
& 2))
30784 /* If both operands are equal, fold to simpler permutation. */
30785 if (rtx_equal_p (op0
, op1
))
30788 perm1
= (perm1
& 1) + 2;
30790 /* If the first selector comes from the second operand, swap. */
30791 else if (perm0
& 2)
30797 x
= op0
, op0
= op1
, op1
= x
;
30799 /* If the second selector does not come from the second operand, fail. */
30800 else if ((perm1
& 2) == 0)
30804 if (target
!= NULL
)
30806 enum machine_mode vmode
, dmode
;
30809 vmode
= GET_MODE (target
);
30810 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
30811 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
30812 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
30813 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
30814 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
30815 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
30821 rs6000_expand_vec_perm_const (rtx operands
[4])
30823 rtx target
, op0
, op1
, sel
;
30824 unsigned char perm0
, perm1
;
30826 target
= operands
[0];
30831 /* Unpack the constant selector. */
30832 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
30833 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
30835 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
30838 /* Test whether a constant permutation is supported. */
30841 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
30842 const unsigned char *sel
)
30844 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
30845 if (TARGET_ALTIVEC
)
30848 /* Check for ps_merge* or evmerge* insns. */
30849 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
30850 || (TARGET_SPE
&& vmode
== V2SImode
))
30852 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
30853 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
30854 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
30860 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
30863 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
30864 enum machine_mode vmode
, unsigned nelt
, rtx perm
[])
30866 enum machine_mode imode
;
30870 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
30872 imode
= GET_MODE_INNER (vmode
);
30873 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
30874 imode
= mode_for_vector (imode
, nelt
);
30877 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
30878 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
30880 emit_move_insn (target
, x
);
30883 /* Expand an extract even operation. */
30886 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
30888 enum machine_mode vmode
= GET_MODE (target
);
30889 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
30892 for (i
= 0; i
< nelt
; i
++)
30893 perm
[i
] = GEN_INT (i
* 2);
30895 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
30898 /* Expand a vector interleave operation. */
30901 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
30903 enum machine_mode vmode
= GET_MODE (target
);
30904 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
30907 high
= (highp
? 0 : nelt
/ 2);
30908 for (i
= 0; i
< nelt
/ 2; i
++)
30910 perm
[i
* 2] = GEN_INT (i
+ high
);
30911 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
30914 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
30917 /* Return an RTX representing where to find the function value of a
30918 function returning MODE. */
30920 rs6000_complex_function_value (enum machine_mode mode
)
30922 unsigned int regno
;
30924 enum machine_mode inner
= GET_MODE_INNER (mode
);
30925 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
30927 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30928 regno
= FP_ARG_RETURN
;
30931 regno
= GP_ARG_RETURN
;
30933 /* 32-bit is OK since it'll go in r3/r4. */
30934 if (TARGET_32BIT
&& inner_bytes
>= 4)
30935 return gen_rtx_REG (mode
, regno
);
30938 if (inner_bytes
>= 8)
30939 return gen_rtx_REG (mode
, regno
);
30941 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
30943 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
30944 GEN_INT (inner_bytes
));
30945 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
30948 /* Target hook for TARGET_FUNCTION_VALUE.
30950 On the SPE, both FPs and vectors are returned in r3.
30952 On RS/6000 an integer value is in r3 and a floating-point value is in
30953 fp1, unless -msoft-float. */
30956 rs6000_function_value (const_tree valtype
,
30957 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
30958 bool outgoing ATTRIBUTE_UNUSED
)
30960 enum machine_mode mode
;
30961 unsigned int regno
;
30962 enum machine_mode elt_mode
;
30965 /* Special handling for structs in darwin64. */
30967 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
30969 CUMULATIVE_ARGS valcum
;
30973 valcum
.fregno
= FP_ARG_MIN_REG
;
30974 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
30975 /* Do a trial code generation as if this were going to be passed as
30976 an argument; if any part goes in memory, we return NULL. */
30977 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
30980 /* Otherwise fall through to standard ABI rules. */
30983 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
30984 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (valtype
), valtype
,
30985 &elt_mode
, &n_elts
))
30987 int first_reg
, n_regs
, i
;
30990 if (SCALAR_FLOAT_MODE_P (elt_mode
))
30992 /* _Decimal128 must use even/odd register pairs. */
30993 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30994 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
30998 first_reg
= ALTIVEC_ARG_RETURN
;
31002 par
= gen_rtx_PARALLEL (TYPE_MODE (valtype
), rtvec_alloc (n_elts
));
31003 for (i
= 0; i
< n_elts
; i
++)
31005 rtx r
= gen_rtx_REG (elt_mode
, first_reg
+ i
* n_regs
);
31006 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
31007 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
31013 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
31015 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
31016 return gen_rtx_PARALLEL (DImode
,
31018 gen_rtx_EXPR_LIST (VOIDmode
,
31019 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
31021 gen_rtx_EXPR_LIST (VOIDmode
,
31022 gen_rtx_REG (SImode
,
31023 GP_ARG_RETURN
+ 1),
31026 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
31028 return gen_rtx_PARALLEL (DCmode
,
31030 gen_rtx_EXPR_LIST (VOIDmode
,
31031 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
31033 gen_rtx_EXPR_LIST (VOIDmode
,
31034 gen_rtx_REG (SImode
,
31035 GP_ARG_RETURN
+ 1),
31037 gen_rtx_EXPR_LIST (VOIDmode
,
31038 gen_rtx_REG (SImode
,
31039 GP_ARG_RETURN
+ 2),
31041 gen_rtx_EXPR_LIST (VOIDmode
,
31042 gen_rtx_REG (SImode
,
31043 GP_ARG_RETURN
+ 3),
31047 mode
= TYPE_MODE (valtype
);
31048 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
31049 || POINTER_TYPE_P (valtype
))
31050 mode
= TARGET_32BIT
? SImode
: DImode
;
31052 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
31053 /* _Decimal128 must use an even/odd register pair. */
31054 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
31055 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
31056 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
31057 regno
= FP_ARG_RETURN
;
31058 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
31059 && targetm
.calls
.split_complex_arg
)
31060 return rs6000_complex_function_value (mode
);
31061 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
31062 return register is used in both cases, and we won't see V2DImode/V2DFmode
31063 for pure altivec, combine the two cases. */
31064 else if (TREE_CODE (valtype
) == VECTOR_TYPE
31065 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
31066 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
31067 regno
= ALTIVEC_ARG_RETURN
;
31068 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
31069 && (mode
== DFmode
|| mode
== DCmode
31070 || mode
== TFmode
|| mode
== TCmode
))
31071 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
31073 regno
= GP_ARG_RETURN
;
31075 return gen_rtx_REG (mode
, regno
);
31078 /* Define how to find the value returned by a library function
31079 assuming the value has mode MODE. */
31081 rs6000_libcall_value (enum machine_mode mode
)
31083 unsigned int regno
;
31085 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
31087 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
31088 return gen_rtx_PARALLEL (DImode
,
31090 gen_rtx_EXPR_LIST (VOIDmode
,
31091 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
31093 gen_rtx_EXPR_LIST (VOIDmode
,
31094 gen_rtx_REG (SImode
,
31095 GP_ARG_RETURN
+ 1),
31099 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
31100 /* _Decimal128 must use an even/odd register pair. */
31101 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
31102 else if (SCALAR_FLOAT_MODE_P (mode
)
31103 && TARGET_HARD_FLOAT
&& TARGET_FPRS
31104 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
31105 regno
= FP_ARG_RETURN
;
31106 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
31107 return register is used in both cases, and we won't see V2DImode/V2DFmode
31108 for pure altivec, combine the two cases. */
31109 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
31110 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
31111 regno
= ALTIVEC_ARG_RETURN
;
31112 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
31113 return rs6000_complex_function_value (mode
);
31114 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
31115 && (mode
== DFmode
|| mode
== DCmode
31116 || mode
== TFmode
|| mode
== TCmode
))
31117 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
31119 regno
= GP_ARG_RETURN
;
31121 return gen_rtx_REG (mode
, regno
);
31125 /* Return true if we use LRA instead of reload pass. */
31127 rs6000_lra_p (void)
31129 return rs6000_lra_flag
;
31132 /* Given FROM and TO register numbers, say whether this elimination is allowed.
31133 Frame pointer elimination is automatically handled.
31135 For the RS/6000, if frame pointer elimination is being done, we would like
31136 to convert ap into fp, not sp.
31138 We need r30 if -mminimal-toc was specified, and there are constant pool
31142 rs6000_can_eliminate (const int from
, const int to
)
31144 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
31145 ? ! frame_pointer_needed
31146 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
31147 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
31151 /* Define the offset between two registers, FROM to be eliminated and its
31152 replacement TO, at the start of a routine. */
31154 rs6000_initial_elimination_offset (int from
, int to
)
31156 rs6000_stack_t
*info
= rs6000_stack_info ();
31157 HOST_WIDE_INT offset
;
31159 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
31160 offset
= info
->push_p
? 0 : -info
->total_size
;
31161 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
31163 offset
= info
->push_p
? 0 : -info
->total_size
;
31164 if (FRAME_GROWS_DOWNWARD
)
31165 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
31167 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
31168 offset
= FRAME_GROWS_DOWNWARD
31169 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
31171 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
31172 offset
= info
->total_size
;
31173 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
31174 offset
= info
->push_p
? info
->total_size
: 0;
31175 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
31178 gcc_unreachable ();
31184 rs6000_dwarf_register_span (rtx reg
)
31188 unsigned regno
= REGNO (reg
);
31189 enum machine_mode mode
= GET_MODE (reg
);
31193 && (SPE_VECTOR_MODE (GET_MODE (reg
))
31194 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
31195 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
31200 regno
= REGNO (reg
);
31202 /* The duality of the SPE register size wreaks all kinds of havoc.
31203 This is a way of distinguishing r0 in 32-bits from r0 in
31205 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
31206 gcc_assert (words
<= 4);
31207 for (i
= 0; i
< words
; i
++, regno
++)
31209 if (BYTES_BIG_ENDIAN
)
31211 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ 1200);
31212 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
31216 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
31217 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ 1200);
31221 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
31224 /* Fill in sizes for SPE register high parts in table used by unwinder. */
31227 rs6000_init_dwarf_reg_sizes_extra (tree address
)
31232 enum machine_mode mode
= TYPE_MODE (char_type_node
);
31233 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
31234 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
31235 rtx value
= gen_int_mode (4, mode
);
31237 for (i
= 1201; i
< 1232; i
++)
31239 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
31240 HOST_WIDE_INT offset
31241 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
31243 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
31247 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
31250 enum machine_mode mode
= TYPE_MODE (char_type_node
);
31251 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
31252 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
31253 rtx value
= gen_int_mode (16, mode
);
31255 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
31256 The unwinder still needs to know the size of Altivec registers. */
31258 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
31260 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
31261 HOST_WIDE_INT offset
31262 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
31264 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
31269 /* Map internal gcc register numbers to DWARF2 register numbers. */
31272 rs6000_dbx_register_number (unsigned int regno
)
31274 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
31276 if (regno
== LR_REGNO
)
31278 if (regno
== CTR_REGNO
)
31280 if (CR_REGNO_P (regno
))
31281 return regno
- CR0_REGNO
+ 86;
31282 if (regno
== CA_REGNO
)
31283 return 101; /* XER */
31284 if (ALTIVEC_REGNO_P (regno
))
31285 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
31286 if (regno
== VRSAVE_REGNO
)
31288 if (regno
== VSCR_REGNO
)
31290 if (regno
== SPE_ACC_REGNO
)
31292 if (regno
== SPEFSCR_REGNO
)
31294 /* SPE high reg number. We get these values of regno from
31295 rs6000_dwarf_register_span. */
31296 gcc_assert (regno
>= 1200 && regno
< 1232);
31300 /* target hook eh_return_filter_mode */
31301 static enum machine_mode
31302 rs6000_eh_return_filter_mode (void)
31304 return TARGET_32BIT
? SImode
: word_mode
;
31307 /* Target hook for scalar_mode_supported_p. */
31309 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
31311 if (DECIMAL_FLOAT_MODE_P (mode
))
31312 return default_decimal_float_supported_p ();
31314 return default_scalar_mode_supported_p (mode
);
31317 /* Target hook for vector_mode_supported_p. */
31319 rs6000_vector_mode_supported_p (enum machine_mode mode
)
31322 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
31325 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
31328 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
31335 /* Target hook for invalid_arg_for_unprototyped_fn. */
31336 static const char *
31337 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
31339 return (!rs6000_darwin64_abi
31341 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
31342 && (funcdecl
== NULL_TREE
31343 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
31344 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
31345 ? N_("AltiVec argument passed to unprototyped function")
31349 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
31350 setup by using __stack_chk_fail_local hidden function instead of
31351 calling __stack_chk_fail directly. Otherwise it is better to call
31352 __stack_chk_fail directly. */
31354 static tree ATTRIBUTE_UNUSED
31355 rs6000_stack_protect_fail (void)
31357 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
31358 ? default_hidden_stack_protect_fail ()
31359 : default_external_stack_protect_fail ();
31363 rs6000_final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
31364 int num_operands ATTRIBUTE_UNUSED
)
31366 if (rs6000_warn_cell_microcode
)
31369 int insn_code_number
= recog_memoized (insn
);
31370 location_t location
= INSN_LOCATION (insn
);
31372 /* Punt on insns we cannot recognize. */
31373 if (insn_code_number
< 0)
31376 temp
= get_insn_template (insn_code_number
, insn
);
31378 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
31379 warning_at (location
, OPT_mwarn_cell_microcode
,
31380 "emitting microcode insn %s\t[%s] #%d",
31381 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
31382 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
31383 warning_at (location
, OPT_mwarn_cell_microcode
,
31384 "emitting conditional microcode insn %s\t[%s] #%d",
31385 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
31389 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
31392 static unsigned HOST_WIDE_INT
31393 rs6000_asan_shadow_offset (void)
31395 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
31399 /* Mask options that we want to support inside of attribute((target)) and
31400 #pragma GCC target operations. Note, we do not include things like
31401 64/32-bit, endianess, hard/soft floating point, etc. that would have
31402 different calling sequences. */
31404 struct rs6000_opt_mask
{
31405 const char *name
; /* option name */
31406 HOST_WIDE_INT mask
; /* mask to set */
31407 bool invert
; /* invert sense of mask */
31408 bool valid_target
; /* option is a target option */
31411 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
31413 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
31414 { "cmpb", OPTION_MASK_CMPB
, false, true },
31415 { "crypto", OPTION_MASK_CRYPTO
, false, true },
31416 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
31417 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
31418 { "fprnd", OPTION_MASK_FPRND
, false, true },
31419 { "hard-dfp", OPTION_MASK_DFP
, false, true },
31420 { "htm", OPTION_MASK_HTM
, false, true },
31421 { "isel", OPTION_MASK_ISEL
, false, true },
31422 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
31423 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
31424 { "mulhw", OPTION_MASK_MULHW
, false, true },
31425 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
31426 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
31427 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
31428 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
31429 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
31430 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
31431 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
31432 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
31433 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
31434 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC
, false, true },
31435 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
31436 { "string", OPTION_MASK_STRING
, false, true },
31437 { "update", OPTION_MASK_NO_UPDATE
, true , true },
31438 { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF
, false, false },
31439 { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF
, false, false },
31440 { "vsx", OPTION_MASK_VSX
, false, true },
31441 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
31442 #ifdef OPTION_MASK_64BIT
31444 { "aix64", OPTION_MASK_64BIT
, false, false },
31445 { "aix32", OPTION_MASK_64BIT
, true, false },
31447 { "64", OPTION_MASK_64BIT
, false, false },
31448 { "32", OPTION_MASK_64BIT
, true, false },
31451 #ifdef OPTION_MASK_EABI
31452 { "eabi", OPTION_MASK_EABI
, false, false },
31454 #ifdef OPTION_MASK_LITTLE_ENDIAN
31455 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
31456 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
31458 #ifdef OPTION_MASK_RELOCATABLE
31459 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
31461 #ifdef OPTION_MASK_STRICT_ALIGN
31462 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
31464 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
31465 { "string", OPTION_MASK_STRING
, false, false },
31468 /* Builtin mask mapping for printing the flags. */
31469 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
31471 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
31472 { "vsx", RS6000_BTM_VSX
, false, false },
31473 { "spe", RS6000_BTM_SPE
, false, false },
31474 { "paired", RS6000_BTM_PAIRED
, false, false },
31475 { "fre", RS6000_BTM_FRE
, false, false },
31476 { "fres", RS6000_BTM_FRES
, false, false },
31477 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
31478 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
31479 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
31480 { "cell", RS6000_BTM_CELL
, false, false },
31481 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
31482 { "crypto", RS6000_BTM_CRYPTO
, false, false },
31483 { "htm", RS6000_BTM_HTM
, false, false },
31484 { "hard-dfp", RS6000_BTM_DFP
, false, false },
31485 { "hard-float", RS6000_BTM_HARD_FLOAT
, false, false },
31486 { "long-double-128", RS6000_BTM_LDBL128
, false, false },
31489 /* Option variables that we want to support inside attribute((target)) and
31490 #pragma GCC target operations. */
31492 struct rs6000_opt_var
{
31493 const char *name
; /* option name */
31494 size_t global_offset
; /* offset of the option in global_options. */
31495 size_t target_offset
; /* offset of the option in target optiosn. */
31498 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
31501 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
31502 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
31503 { "avoid-indexed-addresses",
31504 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
31505 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
31507 offsetof (struct gcc_options
, x_rs6000_paired_float
),
31508 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
31510 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
31511 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
31514 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
31515 parsing. Return true if there were no errors. */
31518 rs6000_inner_target_options (tree args
, bool attr_p
)
31522 if (args
== NULL_TREE
)
31525 else if (TREE_CODE (args
) == STRING_CST
)
31527 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
31530 while ((q
= strtok (p
, ",")) != NULL
)
31532 bool error_p
= false;
31533 bool not_valid_p
= false;
31534 const char *cpu_opt
= NULL
;
31537 if (strncmp (q
, "cpu=", 4) == 0)
31539 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
31540 if (cpu_index
>= 0)
31541 rs6000_cpu_index
= cpu_index
;
31548 else if (strncmp (q
, "tune=", 5) == 0)
31550 int tune_index
= rs6000_cpu_name_lookup (q
+5);
31551 if (tune_index
>= 0)
31552 rs6000_tune_index
= tune_index
;
31562 bool invert
= false;
31566 if (strncmp (r
, "no-", 3) == 0)
31572 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
31573 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
31575 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
31577 if (!rs6000_opt_masks
[i
].valid_target
)
31578 not_valid_p
= true;
31582 rs6000_isa_flags_explicit
|= mask
;
31584 /* VSX needs altivec, so -mvsx automagically sets
31586 if (mask
== OPTION_MASK_VSX
&& !invert
)
31587 mask
|= OPTION_MASK_ALTIVEC
;
31589 if (rs6000_opt_masks
[i
].invert
)
31593 rs6000_isa_flags
&= ~mask
;
31595 rs6000_isa_flags
|= mask
;
31600 if (error_p
&& !not_valid_p
)
31602 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
31603 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
31605 size_t j
= rs6000_opt_vars
[i
].global_offset
;
31606 *((int *) ((char *)&global_options
+ j
)) = !invert
;
31615 const char *eprefix
, *esuffix
;
31620 eprefix
= "__attribute__((__target__(";
31625 eprefix
= "#pragma GCC target ";
31630 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
31632 else if (not_valid_p
)
31633 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
31635 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
31640 else if (TREE_CODE (args
) == TREE_LIST
)
31644 tree value
= TREE_VALUE (args
);
31647 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
31651 args
= TREE_CHAIN (args
);
31653 while (args
!= NULL_TREE
);
31657 gcc_unreachable ();
31662 /* Print out the target options as a list for -mdebug=target. */
31665 rs6000_debug_target_options (tree args
, const char *prefix
)
31667 if (args
== NULL_TREE
)
31668 fprintf (stderr
, "%s<NULL>", prefix
);
31670 else if (TREE_CODE (args
) == STRING_CST
)
31672 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
31675 while ((q
= strtok (p
, ",")) != NULL
)
31678 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
31683 else if (TREE_CODE (args
) == TREE_LIST
)
31687 tree value
= TREE_VALUE (args
);
31690 rs6000_debug_target_options (value
, prefix
);
31693 args
= TREE_CHAIN (args
);
31695 while (args
!= NULL_TREE
);
31699 gcc_unreachable ();
31705 /* Hook to validate attribute((target("..."))). */
31708 rs6000_valid_attribute_p (tree fndecl
,
31709 tree
ARG_UNUSED (name
),
31713 struct cl_target_option cur_target
;
31715 tree old_optimize
= build_optimization_node (&global_options
);
31716 tree new_target
, new_optimize
;
31717 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
31719 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
31721 if (TARGET_DEBUG_TARGET
)
31723 tree tname
= DECL_NAME (fndecl
);
31724 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
31726 fprintf (stderr
, "function: %.*s\n",
31727 (int) IDENTIFIER_LENGTH (tname
),
31728 IDENTIFIER_POINTER (tname
));
31730 fprintf (stderr
, "function: unknown\n");
31732 fprintf (stderr
, "args:");
31733 rs6000_debug_target_options (args
, " ");
31734 fprintf (stderr
, "\n");
31737 fprintf (stderr
, "flags: 0x%x\n", flags
);
31739 fprintf (stderr
, "--------------------\n");
31742 old_optimize
= build_optimization_node (&global_options
);
31743 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
31745 /* If the function changed the optimization levels as well as setting target
31746 options, start with the optimizations specified. */
31747 if (func_optimize
&& func_optimize
!= old_optimize
)
31748 cl_optimization_restore (&global_options
,
31749 TREE_OPTIMIZATION (func_optimize
));
31751 /* The target attributes may also change some optimization flags, so update
31752 the optimization options if necessary. */
31753 cl_target_option_save (&cur_target
, &global_options
);
31754 rs6000_cpu_index
= rs6000_tune_index
= -1;
31755 ret
= rs6000_inner_target_options (args
, true);
31757 /* Set up any additional state. */
31760 ret
= rs6000_option_override_internal (false);
31761 new_target
= build_target_option_node (&global_options
);
31766 new_optimize
= build_optimization_node (&global_options
);
31773 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
31775 if (old_optimize
!= new_optimize
)
31776 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
31779 cl_target_option_restore (&global_options
, &cur_target
);
31781 if (old_optimize
!= new_optimize
)
31782 cl_optimization_restore (&global_options
,
31783 TREE_OPTIMIZATION (old_optimize
));
31789 /* Hook to validate the current #pragma GCC target and set the state, and
31790 update the macros based on what was changed. If ARGS is NULL, then
31791 POP_TARGET is used to reset the options. */
31794 rs6000_pragma_target_parse (tree args
, tree pop_target
)
31796 tree prev_tree
= build_target_option_node (&global_options
);
31798 struct cl_target_option
*prev_opt
, *cur_opt
;
31799 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
31800 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
31802 if (TARGET_DEBUG_TARGET
)
31804 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
31805 fprintf (stderr
, "args:");
31806 rs6000_debug_target_options (args
, " ");
31807 fprintf (stderr
, "\n");
31811 fprintf (stderr
, "pop_target:\n");
31812 debug_tree (pop_target
);
31815 fprintf (stderr
, "pop_target: <NULL>\n");
31817 fprintf (stderr
, "--------------------\n");
31822 cur_tree
= ((pop_target
)
31824 : target_option_default_node
);
31825 cl_target_option_restore (&global_options
,
31826 TREE_TARGET_OPTION (cur_tree
));
31830 rs6000_cpu_index
= rs6000_tune_index
= -1;
31831 if (!rs6000_inner_target_options (args
, false)
31832 || !rs6000_option_override_internal (false)
31833 || (cur_tree
= build_target_option_node (&global_options
))
31836 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
31837 fprintf (stderr
, "invalid pragma\n");
31843 target_option_current_node
= cur_tree
;
31845 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
31846 change the macros that are defined. */
31847 if (rs6000_target_modify_macros_ptr
)
31849 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
31850 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
31851 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
31853 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
31854 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
31855 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
31857 diff_bumask
= (prev_bumask
^ cur_bumask
);
31858 diff_flags
= (prev_flags
^ cur_flags
);
31860 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
31862 /* Delete old macros. */
31863 rs6000_target_modify_macros_ptr (false,
31864 prev_flags
& diff_flags
,
31865 prev_bumask
& diff_bumask
);
31867 /* Define new macros. */
31868 rs6000_target_modify_macros_ptr (true,
31869 cur_flags
& diff_flags
,
31870 cur_bumask
& diff_bumask
);
31878 /* Remember the last target of rs6000_set_current_function. */
31879 static GTY(()) tree rs6000_previous_fndecl
;
31881 /* Establish appropriate back-end context for processing the function
31882 FNDECL. The argument might be NULL to indicate processing at top
31883 level, outside of any function scope. */
31885 rs6000_set_current_function (tree fndecl
)
31887 tree old_tree
= (rs6000_previous_fndecl
31888 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
31891 tree new_tree
= (fndecl
31892 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
31895 if (TARGET_DEBUG_TARGET
)
31897 bool print_final
= false;
31898 fprintf (stderr
, "\n==================== rs6000_set_current_function");
31901 fprintf (stderr
, ", fndecl %s (%p)",
31902 (DECL_NAME (fndecl
)
31903 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
31904 : "<unknown>"), (void *)fndecl
);
31906 if (rs6000_previous_fndecl
)
31907 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
31909 fprintf (stderr
, "\n");
31912 fprintf (stderr
, "\nnew fndecl target specific options:\n");
31913 debug_tree (new_tree
);
31914 print_final
= true;
31919 fprintf (stderr
, "\nold fndecl target specific options:\n");
31920 debug_tree (old_tree
);
31921 print_final
= true;
31925 fprintf (stderr
, "--------------------\n");
31928 /* Only change the context if the function changes. This hook is called
31929 several times in the course of compiling a function, and we don't want to
31930 slow things down too much or call target_reinit when it isn't safe. */
31931 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
31933 rs6000_previous_fndecl
= fndecl
;
31934 if (old_tree
== new_tree
)
31939 cl_target_option_restore (&global_options
,
31940 TREE_TARGET_OPTION (new_tree
));
31941 if (TREE_TARGET_GLOBALS (new_tree
))
31942 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
31944 TREE_TARGET_GLOBALS (new_tree
)
31945 = save_target_globals_default_opts ();
31950 new_tree
= target_option_current_node
;
31951 cl_target_option_restore (&global_options
,
31952 TREE_TARGET_OPTION (new_tree
));
31953 if (TREE_TARGET_GLOBALS (new_tree
))
31954 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
31955 else if (new_tree
== target_option_default_node
)
31956 restore_target_globals (&default_target_globals
);
31958 TREE_TARGET_GLOBALS (new_tree
)
31959 = save_target_globals_default_opts ();
31965 /* Save the current options */
31968 rs6000_function_specific_save (struct cl_target_option
*ptr
,
31969 struct gcc_options
*opts
)
31971 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
31972 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
31975 /* Restore the current options */
31978 rs6000_function_specific_restore (struct gcc_options
*opts
,
31979 struct cl_target_option
*ptr
)
31982 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
31983 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
31984 (void) rs6000_option_override_internal (false);
31987 /* Print the current options */
31990 rs6000_function_specific_print (FILE *file
, int indent
,
31991 struct cl_target_option
*ptr
)
31993 rs6000_print_isa_options (file
, indent
, "Isa options set",
31994 ptr
->x_rs6000_isa_flags
);
31996 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
31997 ptr
->x_rs6000_isa_flags_explicit
);
32000 /* Helper function to print the current isa or misc options on a line. */
32003 rs6000_print_options_internal (FILE *file
,
32005 const char *string
,
32006 HOST_WIDE_INT flags
,
32007 const char *prefix
,
32008 const struct rs6000_opt_mask
*opts
,
32009 size_t num_elements
)
32012 size_t start_column
= 0;
32014 size_t max_column
= 76;
32015 const char *comma
= "";
32018 start_column
+= fprintf (file
, "%*s", indent
, "");
32022 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
32026 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
32028 /* Print the various mask options. */
32029 cur_column
= start_column
;
32030 for (i
= 0; i
< num_elements
; i
++)
32032 if ((flags
& opts
[i
].mask
) != 0)
32034 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
32035 size_t len
= (strlen (comma
)
32038 + strlen (rs6000_opt_masks
[i
].name
));
32041 if (cur_column
> max_column
)
32043 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
32044 cur_column
= start_column
+ len
;
32048 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
32049 rs6000_opt_masks
[i
].name
);
32050 flags
&= ~ opts
[i
].mask
;
32055 fputs ("\n", file
);
32058 /* Helper function to print the current isa options on a line. */
32061 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
32062 HOST_WIDE_INT flags
)
32064 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
32065 &rs6000_opt_masks
[0],
32066 ARRAY_SIZE (rs6000_opt_masks
));
32070 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
32071 HOST_WIDE_INT flags
)
32073 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
32074 &rs6000_builtin_mask_names
[0],
32075 ARRAY_SIZE (rs6000_builtin_mask_names
));
32079 /* Hook to determine if one function can safely inline another. */
32082 rs6000_can_inline_p (tree caller
, tree callee
)
32085 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
32086 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
32088 /* If callee has no option attributes, then it is ok to inline. */
32092 /* If caller has no option attributes, but callee does then it is not ok to
32094 else if (!caller_tree
)
32099 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
32100 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
32102 /* Callee's options should a subset of the caller's, i.e. a vsx function
32103 can inline an altivec function but a non-vsx function can't inline a
32105 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
32106 == callee_opts
->x_rs6000_isa_flags
)
32110 if (TARGET_DEBUG_TARGET
)
32111 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
32112 (DECL_NAME (caller
)
32113 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
32115 (DECL_NAME (callee
)
32116 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
32118 (ret
? "can" : "cannot"));
32123 /* Allocate a stack temp and fixup the address so it meets the particular
32124 memory requirements (either offetable or REG+REG addressing). */
32127 rs6000_allocate_stack_temp (enum machine_mode mode
,
32128 bool offsettable_p
,
32131 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
32132 rtx addr
= XEXP (stack
, 0);
32133 int strict_p
= (reload_in_progress
|| reload_completed
);
32135 if (!legitimate_indirect_address_p (addr
, strict_p
))
32138 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
32139 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
32141 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
32142 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
32148 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
32149 to such a form to deal with memory reference instructions like STFIWX that
32150 only take reg+reg addressing. */
32153 rs6000_address_for_fpconvert (rtx x
)
32155 int strict_p
= (reload_in_progress
|| reload_completed
);
32158 gcc_assert (MEM_P (x
));
32159 addr
= XEXP (x
, 0);
32160 if (! legitimate_indirect_address_p (addr
, strict_p
)
32161 && ! legitimate_indexed_address_p (addr
, strict_p
))
32163 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
32165 rtx reg
= XEXP (addr
, 0);
32166 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
32167 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
32168 gcc_assert (REG_P (reg
));
32169 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
32172 else if (GET_CODE (addr
) == PRE_MODIFY
)
32174 rtx reg
= XEXP (addr
, 0);
32175 rtx expr
= XEXP (addr
, 1);
32176 gcc_assert (REG_P (reg
));
32177 gcc_assert (GET_CODE (expr
) == PLUS
);
32178 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
32182 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
32188 /* Given a memory reference, if it is not in the form for altivec memory
32189 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
32190 convert to the altivec format. */
32193 rs6000_address_for_altivec (rtx x
)
32195 gcc_assert (MEM_P (x
));
32196 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
32198 rtx addr
= XEXP (x
, 0);
32199 int strict_p
= (reload_in_progress
|| reload_completed
);
32201 if (!legitimate_indexed_address_p (addr
, strict_p
)
32202 && !legitimate_indirect_address_p (addr
, strict_p
))
32203 addr
= copy_to_mode_reg (Pmode
, addr
);
32205 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
32206 x
= change_address (x
, GET_MODE (x
), addr
);
32212 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
32214 On the RS/6000, all integer constants are acceptable, most won't be valid
32215 for particular insns, though. Only easy FP constants are acceptable. */
32218 rs6000_legitimate_constant_p (enum machine_mode mode
, rtx x
)
32220 if (TARGET_ELF
&& rs6000_tls_referenced_p (x
))
32223 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
32224 || GET_MODE (x
) == VOIDmode
32225 || (TARGET_POWERPC64
&& mode
== DImode
)
32226 || easy_fp_constant (x
, mode
)
32227 || easy_vector_constant (x
, mode
));
32232 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
32235 rs6000_call_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
32237 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
32238 rtx toc_load
= NULL_RTX
;
32239 rtx toc_restore
= NULL_RTX
;
32241 rtx abi_reg
= NULL_RTX
;
32246 /* Handle longcall attributes. */
32247 if (INTVAL (cookie
) & CALL_LONG
)
32248 func_desc
= rs6000_longcall_ref (func_desc
);
32250 /* Handle indirect calls. */
32251 if (GET_CODE (func_desc
) != SYMBOL_REF
32252 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func_desc
)))
32254 /* Save the TOC into its reserved slot before the call,
32255 and prepare to restore it after the call. */
32256 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
32257 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
32258 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
32259 gen_rtx_PLUS (Pmode
, stack_ptr
,
32260 stack_toc_offset
));
32261 toc_restore
= gen_rtx_SET (VOIDmode
, toc_reg
, stack_toc_mem
);
32263 /* Can we optimize saving the TOC in the prologue or
32264 do we need to do it at every call? */
32265 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
32266 cfun
->machine
->save_toc_in_prologue
= true;
32269 MEM_VOLATILE_P (stack_toc_mem
) = 1;
32270 emit_move_insn (stack_toc_mem
, toc_reg
);
32273 if (DEFAULT_ABI
== ABI_ELFv2
)
32275 /* A function pointer in the ELFv2 ABI is just a plain address, but
32276 the ABI requires it to be loaded into r12 before the call. */
32277 func_addr
= gen_rtx_REG (Pmode
, 12);
32278 emit_move_insn (func_addr
, func_desc
);
32279 abi_reg
= func_addr
;
32283 /* A function pointer under AIX is a pointer to a data area whose
32284 first word contains the actual address of the function, whose
32285 second word contains a pointer to its TOC, and whose third word
32286 contains a value to place in the static chain register (r11).
32287 Note that if we load the static chain, our "trampoline" need
32288 not have any executable code. */
32290 /* Load up address of the actual function. */
32291 func_desc
= force_reg (Pmode
, func_desc
);
32292 func_addr
= gen_reg_rtx (Pmode
);
32293 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
32295 /* Prepare to load the TOC of the called function. Note that the
32296 TOC load must happen immediately before the actual call so
32297 that unwinding the TOC registers works correctly. See the
32298 comment in frob_update_context. */
32299 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
32300 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
32301 gen_rtx_PLUS (Pmode
, func_desc
,
32303 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
32305 /* If we have a static chain, load it up. */
32306 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
32308 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
32309 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
32310 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
32311 gen_rtx_PLUS (Pmode
, func_desc
,
32313 emit_move_insn (sc_reg
, func_sc_mem
);
32320 /* Direct calls use the TOC: for local calls, the callee will
32321 assume the TOC register is set; for non-local calls, the
32322 PLT stub needs the TOC register. */
32324 func_addr
= func_desc
;
32327 /* Create the call. */
32328 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), flag
);
32329 if (value
!= NULL_RTX
)
32330 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
32334 call
[n_call
++] = toc_load
;
32336 call
[n_call
++] = toc_restore
;
32338 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
32340 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
32341 insn
= emit_call_insn (insn
);
32343 /* Mention all registers defined by the ABI to hold information
32344 as uses in CALL_INSN_FUNCTION_USAGE. */
32346 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
32349 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
32352 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
32357 gcc_assert (INTVAL (cookie
) == 0);
32359 /* Create the call. */
32360 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), flag
);
32361 if (value
!= NULL_RTX
)
32362 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
32364 call
[1] = simple_return_rtx
;
32366 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
32367 insn
= emit_call_insn (insn
);
32369 /* Note use of the TOC register. */
32370 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
32371 /* We need to also mark a use of the link register since the function we
32372 sibling-call to will use it to return to our caller. */
32373 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, LR_REGNO
));
32376 /* Return whether we need to always update the saved TOC pointer when we update
32377 the stack pointer. */
32380 rs6000_save_toc_in_prologue_p (void)
32382 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
32385 #ifdef HAVE_GAS_HIDDEN
32386 # define USE_HIDDEN_LINKONCE 1
32388 # define USE_HIDDEN_LINKONCE 0
32391 /* Fills in the label name that should be used for a 476 link stack thunk. */
32394 get_ppc476_thunk_name (char name
[32])
32396 gcc_assert (TARGET_LINK_STACK
);
32398 if (USE_HIDDEN_LINKONCE
)
32399 sprintf (name
, "__ppc476.get_thunk");
32401 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
32404 /* This function emits the simple thunk routine that is used to preserve
32405 the link stack on the 476 cpu. */
32407 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
32409 rs6000_code_end (void)
32414 if (!TARGET_LINK_STACK
)
32417 get_ppc476_thunk_name (name
);
32419 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
32420 build_function_type_list (void_type_node
, NULL_TREE
));
32421 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
32422 NULL_TREE
, void_type_node
);
32423 TREE_PUBLIC (decl
) = 1;
32424 TREE_STATIC (decl
) = 1;
32427 if (USE_HIDDEN_LINKONCE
)
32429 cgraph_create_node (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
32430 targetm
.asm_out
.unique_section (decl
, 0);
32431 switch_to_section (get_named_section (decl
, NULL
, 0));
32432 DECL_WEAK (decl
) = 1;
32433 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
32434 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
32435 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
32436 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
32441 switch_to_section (text_section
);
32442 ASM_OUTPUT_LABEL (asm_out_file
, name
);
32445 DECL_INITIAL (decl
) = make_node (BLOCK
);
32446 current_function_decl
= decl
;
32447 init_function_start (decl
);
32448 first_function_block_is_cold
= false;
32449 /* Make sure unwind info is emitted for the thunk if needed. */
32450 final_start_function (emit_barrier (), asm_out_file
, 1);
32452 fputs ("\tblr\n", asm_out_file
);
32454 final_end_function ();
32455 init_insn_lengths ();
32456 free_after_compilation (cfun
);
32458 current_function_decl
= NULL
;
32461 /* Add r30 to hard reg set if the prologue sets it up and it is not
32462 pic_offset_table_rtx. */
32465 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
32467 if (!TARGET_SINGLE_PIC_BASE
32469 && TARGET_MINIMAL_TOC
32470 && get_pool_size () != 0)
32471 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
32475 /* Helper function for rs6000_split_logical to emit a logical instruction after
32476 spliting the operation to single GPR registers.
32478 DEST is the destination register.
32479 OP1 and OP2 are the input source registers.
32480 CODE is the base operation (AND, IOR, XOR, NOT).
32481 MODE is the machine mode.
32482 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
32483 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
32484 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
32485 CLOBBER_REG is either NULL or a scratch register of type CC to allow
32486 formation of the AND instructions. */
32489 rs6000_split_logical_inner (rtx dest
,
32492 enum rtx_code code
,
32493 enum machine_mode mode
,
32494 bool complement_final_p
,
32495 bool complement_op1_p
,
32496 bool complement_op2_p
,
32502 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
32503 if (op2
&& GET_CODE (op2
) == CONST_INT
32504 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
32505 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
32507 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
32508 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
32510 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
32515 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
32519 else if (value
== mask
)
32521 if (!rtx_equal_p (dest
, op1
))
32522 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
32527 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
32528 into separate ORI/ORIS or XORI/XORIS instrucitons. */
32529 else if (code
== IOR
|| code
== XOR
)
32533 if (!rtx_equal_p (dest
, op1
))
32534 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
32540 if (complement_op1_p
)
32541 op1
= gen_rtx_NOT (mode
, op1
);
32543 if (complement_op2_p
)
32544 op2
= gen_rtx_NOT (mode
, op2
);
32546 bool_rtx
= ((code
== NOT
)
32547 ? gen_rtx_NOT (mode
, op1
)
32548 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
32550 if (complement_final_p
)
32551 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
32553 set_rtx
= gen_rtx_SET (VOIDmode
, dest
, bool_rtx
);
32555 /* Is this AND with an explicit clobber? */
32558 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, clobber_reg
);
32559 set_rtx
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set_rtx
, clobber
));
32562 emit_insn (set_rtx
);
32566 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
32567 operations are split immediately during RTL generation to allow for more
32568 optimizations of the AND/IOR/XOR.
32570 OPERANDS is an array containing the destination and two input operands.
32571 CODE is the base operation (AND, IOR, XOR, NOT).
32572 MODE is the machine mode.
32573 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
32574 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
32575 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
32576 CLOBBER_REG is either NULL or a scratch register of type CC to allow
32577 formation of the AND instructions. */
32580 rs6000_split_logical_di (rtx operands
[3],
32581 enum rtx_code code
,
32582 bool complement_final_p
,
32583 bool complement_op1_p
,
32584 bool complement_op2_p
,
32587 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
32588 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
32589 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
32590 enum hi_lo
{ hi
= 0, lo
= 1 };
32591 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
32594 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
32595 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
32596 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
32597 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
32600 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
32603 if (GET_CODE (operands
[2]) != CONST_INT
)
32605 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
32606 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
32610 HOST_WIDE_INT value
= INTVAL (operands
[2]);
32611 HOST_WIDE_INT value_hi_lo
[2];
32613 gcc_assert (!complement_final_p
);
32614 gcc_assert (!complement_op1_p
);
32615 gcc_assert (!complement_op2_p
);
32617 value_hi_lo
[hi
] = value
>> 32;
32618 value_hi_lo
[lo
] = value
& lower_32bits
;
32620 for (i
= 0; i
< 2; i
++)
32622 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
32624 if (sub_value
& sign_bit
)
32625 sub_value
|= upper_32bits
;
32627 op2_hi_lo
[i
] = GEN_INT (sub_value
);
32629 /* If this is an AND instruction, check to see if we need to load
32630 the value in a register. */
32631 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
32632 && !and_operand (op2_hi_lo
[i
], SImode
))
32633 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
32638 for (i
= 0; i
< 2; i
++)
32640 /* Split large IOR/XOR operations. */
32641 if ((code
== IOR
|| code
== XOR
)
32642 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
32643 && !complement_final_p
32644 && !complement_op1_p
32645 && !complement_op2_p
32646 && clobber_reg
== NULL_RTX
32647 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
32649 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
32650 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
32651 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
32652 rtx tmp
= gen_reg_rtx (SImode
);
32654 /* Make sure the constant is sign extended. */
32655 if ((hi_16bits
& sign_bit
) != 0)
32656 hi_16bits
|= upper_32bits
;
32658 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
32659 code
, SImode
, false, false, false,
32662 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
32663 code
, SImode
, false, false, false,
32667 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
32668 code
, SImode
, complement_final_p
,
32669 complement_op1_p
, complement_op2_p
,
32676 /* Split the insns that make up boolean operations operating on multiple GPR
32677 registers. The boolean MD patterns ensure that the inputs either are
32678 exactly the same as the output registers, or there is no overlap.
32680 OPERANDS is an array containing the destination and two input operands.
32681 CODE is the base operation (AND, IOR, XOR, NOT).
32682 MODE is the machine mode.
32683 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
32684 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
32685 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
32686 CLOBBER_REG is either NULL or a scratch register of type CC to allow
32687 formation of the AND instructions. */
32690 rs6000_split_logical (rtx operands
[3],
32691 enum rtx_code code
,
32692 bool complement_final_p
,
32693 bool complement_op1_p
,
32694 bool complement_op2_p
,
32697 enum machine_mode mode
= GET_MODE (operands
[0]);
32698 enum machine_mode sub_mode
;
32700 int sub_size
, regno0
, regno1
, nregs
, i
;
32702 /* If this is DImode, use the specialized version that can run before
32703 register allocation. */
32704 if (mode
== DImode
&& !TARGET_POWERPC64
)
32706 rs6000_split_logical_di (operands
, code
, complement_final_p
,
32707 complement_op1_p
, complement_op2_p
,
32714 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
32715 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
32716 sub_size
= GET_MODE_SIZE (sub_mode
);
32717 regno0
= REGNO (op0
);
32718 regno1
= REGNO (op1
);
32720 gcc_assert (reload_completed
);
32721 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
32722 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
32724 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
32725 gcc_assert (nregs
> 1);
32727 if (op2
&& REG_P (op2
))
32728 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
32730 for (i
= 0; i
< nregs
; i
++)
32732 int offset
= i
* sub_size
;
32733 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
32734 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
32735 rtx sub_op2
= ((code
== NOT
)
32737 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
32739 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
32740 complement_final_p
, complement_op1_p
,
32741 complement_op2_p
, clobber_reg
);
32748 /* Return true if the peephole2 can combine a load involving a combination of
32749 an addis instruction and a load with an offset that can be fused together on
32753 operands[0] register set with addis
32754 operands[1] value set via addis
32755 operands[2] target register being loaded
32756 operands[3] D-form memory reference using operands[0].
32758 In addition, we are passed a boolean that is true if this is a peephole2,
32759 and we can use see if the addis_reg is dead after the insn and can be
32760 replaced by the target register. */
32763 fusion_gpr_load_p (rtx
*operands
, bool peep2_p
)
32765 rtx addis_reg
= operands
[0];
32766 rtx addis_value
= operands
[1];
32767 rtx target
= operands
[2];
32768 rtx mem
= operands
[3];
32772 /* Validate arguments. */
32773 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
32776 if (!base_reg_operand (target
, GET_MODE (target
)))
32779 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
32782 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
32785 /* Allow sign/zero extension. */
32786 if (GET_CODE (mem
) == ZERO_EXTEND
32787 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
32788 mem
= XEXP (mem
, 0);
32793 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
32794 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
32797 /* Validate that the register used to load the high value is either the
32798 register being loaded, or we can safely replace its use in a peephole2.
32800 If this is a peephole2, we assume that there are 2 instructions in the
32801 peephole (addis and load), so we want to check if the target register was
32802 not used in the memory address and the register to hold the addis result
32803 is dead after the peephole. */
32804 if (REGNO (addis_reg
) != REGNO (target
))
32809 if (reg_mentioned_p (target
, mem
))
32812 if (!peep2_reg_dead_p (2, addis_reg
))
32815 /* If the target register being loaded is the stack pointer, we must
32816 avoid loading any other value into it, even temporarily. */
32817 if (REG_P (target
) && REGNO (target
) == STACK_POINTER_REGNUM
)
32821 base_reg
= XEXP (addr
, 0);
32822 return REGNO (addis_reg
) == REGNO (base_reg
);
32825 /* During the peephole2 pass, adjust and expand the insns for a load fusion
32826 sequence. We adjust the addis register to use the target register. If the
32827 load sign extends, we adjust the code to do the zero extending load, and an
32828 explicit sign extension later since the fusion only covers zero extending
32832 operands[0] register set with addis (to be replaced with target)
32833 operands[1] value set via addis
32834 operands[2] target register being loaded
32835 operands[3] D-form memory reference using operands[0]. */
32838 expand_fusion_gpr_load (rtx
*operands
)
32840 rtx addis_value
= operands
[1];
32841 rtx target
= operands
[2];
32842 rtx orig_mem
= operands
[3];
32843 rtx new_addr
, new_mem
, orig_addr
, offset
;
32844 enum rtx_code plus_or_lo_sum
;
32845 enum machine_mode target_mode
= GET_MODE (target
);
32846 enum machine_mode extend_mode
= target_mode
;
32847 enum machine_mode ptr_mode
= Pmode
;
32848 enum rtx_code extend
= UNKNOWN
;
32849 rtx addis_reg
= ((ptr_mode
== target_mode
)
32851 : simplify_subreg (ptr_mode
, target
, target_mode
, 0));
32853 if (GET_CODE (orig_mem
) == ZERO_EXTEND
32854 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
32856 extend
= GET_CODE (orig_mem
);
32857 orig_mem
= XEXP (orig_mem
, 0);
32858 target_mode
= GET_MODE (orig_mem
);
32861 gcc_assert (MEM_P (orig_mem
));
32863 orig_addr
= XEXP (orig_mem
, 0);
32864 plus_or_lo_sum
= GET_CODE (orig_addr
);
32865 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
32867 offset
= XEXP (orig_addr
, 1);
32868 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_reg
, offset
);
32869 new_mem
= change_address (orig_mem
, target_mode
, new_addr
);
32871 if (extend
!= UNKNOWN
)
32872 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
32874 emit_insn (gen_rtx_SET (VOIDmode
, addis_reg
, addis_value
));
32875 emit_insn (gen_rtx_SET (VOIDmode
, target
, new_mem
));
32877 if (extend
== SIGN_EXTEND
)
32879 int sub_off
= ((BYTES_BIG_ENDIAN
)
32880 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
32883 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
32885 emit_insn (gen_rtx_SET (VOIDmode
, target
,
32886 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
32892 /* Return a string to fuse an addis instruction with a gpr load to the same
32893 register that we loaded up the addis instruction. The code is complicated,
32894 so we call output_asm_insn directly, and just return "".
32897 operands[0] register set with addis (must be same reg as target).
32898 operands[1] value set via addis
32899 operands[2] target register being loaded
32900 operands[3] D-form memory reference using operands[0]. */
32903 emit_fusion_gpr_load (rtx
*operands
)
32905 rtx addis_reg
= operands
[0];
32906 rtx addis_value
= operands
[1];
32907 rtx target
= operands
[2];
32908 rtx mem
= operands
[3];
32912 const char *addis_str
= NULL
;
32913 const char *load_str
= NULL
;
32914 const char *extend_insn
= NULL
;
32915 const char *mode_name
= NULL
;
32916 char insn_template
[80];
32917 enum machine_mode mode
;
32918 const char *comment_str
= ASM_COMMENT_START
;
32919 bool sign_p
= false;
32921 gcc_assert (REG_P (addis_reg
) && REG_P (target
));
32922 gcc_assert (REGNO (addis_reg
) == REGNO (target
));
32924 if (*comment_str
== ' ')
32927 /* Allow sign/zero extension. */
32928 if (GET_CODE (mem
) == ZERO_EXTEND
)
32929 mem
= XEXP (mem
, 0);
32931 else if (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
)
32934 mem
= XEXP (mem
, 0);
32937 gcc_assert (MEM_P (mem
));
32938 addr
= XEXP (mem
, 0);
32939 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
32940 gcc_unreachable ();
32942 load_offset
= XEXP (addr
, 1);
32944 /* Now emit the load instruction to the same register. */
32945 mode
= GET_MODE (mem
);
32949 mode_name
= "char";
32951 extend_insn
= "extsb %0,%0";
32955 mode_name
= "short";
32957 extend_insn
= "extsh %0,%0";
32963 extend_insn
= "extsw %0,%0";
32967 if (TARGET_POWERPC64
)
32969 mode_name
= "long";
32973 gcc_unreachable ();
32977 gcc_unreachable ();
32980 /* Emit the addis instruction. */
32981 fuse_ops
[0] = target
;
32982 if (satisfies_constraint_L (addis_value
))
32984 fuse_ops
[1] = addis_value
;
32985 addis_str
= "lis %0,%v1";
32988 else if (GET_CODE (addis_value
) == PLUS
)
32990 rtx op0
= XEXP (addis_value
, 0);
32991 rtx op1
= XEXP (addis_value
, 1);
32993 if (REG_P (op0
) && CONST_INT_P (op1
)
32994 && satisfies_constraint_L (op1
))
32998 addis_str
= "addis %0,%1,%v2";
33002 else if (GET_CODE (addis_value
) == HIGH
)
33004 rtx value
= XEXP (addis_value
, 0);
33005 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
33007 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
33008 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
33010 addis_str
= "addis %0,%2,%1@toc@ha";
33012 else if (TARGET_XCOFF
)
33013 addis_str
= "addis %0,%1@u(%2)";
33016 gcc_unreachable ();
33019 else if (GET_CODE (value
) == PLUS
)
33021 rtx op0
= XEXP (value
, 0);
33022 rtx op1
= XEXP (value
, 1);
33024 if (GET_CODE (op0
) == UNSPEC
33025 && XINT (op0
, 1) == UNSPEC_TOCREL
33026 && CONST_INT_P (op1
))
33028 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
33029 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
33032 addis_str
= "addis %0,%2,%1+%3@toc@ha";
33034 else if (TARGET_XCOFF
)
33035 addis_str
= "addis %0,%1+%3@u(%2)";
33038 gcc_unreachable ();
33042 else if (satisfies_constraint_L (value
))
33044 fuse_ops
[1] = value
;
33045 addis_str
= "lis %0,%v1";
33048 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
33050 fuse_ops
[1] = value
;
33051 addis_str
= "lis %0,%1@ha";
33056 fatal_insn ("Could not generate addis value for fusion", addis_value
);
33058 sprintf (insn_template
, "%s\t\t%s gpr load fusion, type %s", addis_str
,
33059 comment_str
, mode_name
);
33060 output_asm_insn (insn_template
, fuse_ops
);
33062 /* Emit the D-form load instruction. */
33063 if (CONST_INT_P (load_offset
) && satisfies_constraint_I (load_offset
))
33065 sprintf (insn_template
, "%s %%0,%%1(%%0)", load_str
);
33066 fuse_ops
[1] = load_offset
;
33067 output_asm_insn (insn_template
, fuse_ops
);
33070 else if (GET_CODE (load_offset
) == UNSPEC
33071 && XINT (load_offset
, 1) == UNSPEC_TOCREL
)
33074 sprintf (insn_template
, "%s %%0,%%1@toc@l(%%0)", load_str
);
33076 else if (TARGET_XCOFF
)
33077 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
33080 gcc_unreachable ();
33082 fuse_ops
[1] = XVECEXP (load_offset
, 0, 0);
33083 output_asm_insn (insn_template
, fuse_ops
);
33086 else if (GET_CODE (load_offset
) == PLUS
33087 && GET_CODE (XEXP (load_offset
, 0)) == UNSPEC
33088 && XINT (XEXP (load_offset
, 0), 1) == UNSPEC_TOCREL
33089 && CONST_INT_P (XEXP (load_offset
, 1)))
33091 rtx tocrel_unspec
= XEXP (load_offset
, 0);
33093 sprintf (insn_template
, "%s %%0,%%1+%%2@toc@l(%%0)", load_str
);
33095 else if (TARGET_XCOFF
)
33096 sprintf (insn_template
, "%s %%0,%%1+%%2@l(%%0)", load_str
);
33099 gcc_unreachable ();
33101 fuse_ops
[1] = XVECEXP (tocrel_unspec
, 0, 0);
33102 fuse_ops
[2] = XEXP (load_offset
, 1);
33103 output_asm_insn (insn_template
, fuse_ops
);
33106 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (load_offset
))
33108 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
33110 fuse_ops
[1] = load_offset
;
33111 output_asm_insn (insn_template
, fuse_ops
);
33115 fatal_insn ("Unable to generate load offset for fusion", load_offset
);
33117 /* Handle sign extension. The peephole2 pass generates this as a separate
33118 insn, but we handle it just in case it got reattached. */
33121 gcc_assert (extend_insn
!= NULL
);
33122 output_asm_insn (extend_insn
, fuse_ops
);
33129 struct gcc_target targetm
= TARGET_INITIALIZER
;
33131 #include "gt-rs6000.h"